From bc24ae901b74c5b673837d7f83423c1f7aa45c29 Mon Sep 17 00:00:00 2001 From: James McKenzie Date: Fri, 18 Apr 2025 12:37:26 +0100 Subject: fish --- smh-ac415-fpga/examples/01_led/led/led.qpf | 30 + smh-ac415-fpga/examples/01_led/led/led.qsf | 65 + smh-ac415-fpga/examples/01_led/led/led.qws | Bin 0 -> 1287 bytes smh-ac415-fpga/examples/01_led/led/led.v | 21 + ...56\236\351\252\214\347\216\260\350\261\241.txt" | 2 + .../examples/02_water_rgb/water_rgb/water_rgb.qpf | 30 + .../examples/02_water_rgb/water_rgb/water_rgb.qsf | 69 + .../examples/02_water_rgb/water_rgb/water_rgb.qws | Bin 0 -> 1359 bytes .../examples/02_water_rgb/water_rgb/water_rgb.v | 45 + .../02_water_rgb/water_rgb/water_rgb.v.bak | 45 + ...56\236\351\252\214\347\216\260\350\261\241.txt" | 2 + .../smg595_static/doc/seg_595_static.vsdx | Bin 0 -> 160248 bytes .../smg595_static/quartus_prj/seg_595_static.qpf | 30 + .../smg595_static/quartus_prj/seg_595_static.qsf | 76 + .../smg595_static/quartus_prj/seg_595_static.qws | Bin 0 -> 3107 bytes .../simulation/modelsim/seg_595_static.sft | 6 + .../simulation/modelsim/seg_595_static.vo | 2444 ++ .../modelsim/seg_595_static_8_1200mv_0c_slow.vo | 2444 ++ .../modelsim/seg_595_static_8_1200mv_0c_v_slow.sdo | 1858 ++ .../modelsim/seg_595_static_8_1200mv_85c_slow.vo | 2444 ++ .../seg_595_static_8_1200mv_85c_v_slow.sdo | 1858 ++ .../modelsim/seg_595_static_min_1200mv_0c_fast.vo | 2444 ++ .../seg_595_static_min_1200mv_0c_v_fast.sdo | 1858 ++ .../modelsim/seg_595_static_modelsim.xrf | 135 + .../simulation/modelsim/seg_595_static_v.sdo | 1858 ++ .../03_smg595/smg595_static/rtl/hc595_ctrl.v | 99 + .../03_smg595/smg595_static/rtl/hc595_ctrl.v.bak | 99 + .../03_smg595/smg595_static/rtl/seg_595_static.v | 65 + .../smg595_static/rtl/seg_595_static.v.bak | 65 + .../03_smg595/smg595_static/rtl/seg_static.v | 123 + .../03_smg595/smg595_static/rtl/seg_static.v.bak | 111 + .../smg595_static/sim/tb_seg_595_static.v | 69 + ...56\236\351\252\214\347\216\260\350\261\241.txt" | 2 + smh-ac415-fpga/examples/04_touch/touch/touch.qpf | 30 + smh-ac415-fpga/examples/04_touch/touch/touch.qsf | 59 + smh-ac415-fpga/examples/04_touch/touch/touch.qws | Bin 0 -> 1846 bytes smh-ac415-fpga/examples/04_touch/touch/touch.v | 38 + ...56\236\351\252\214\347\216\260\350\261\241.txt" | 2 + .../examples/05_rs232/rs232/doc/rs232.vsdx | Bin 0 -> 547632 bytes .../examples/05_rs232/rs232/quartus_prj/rs232.qpf | 30 + .../examples/05_rs232/rs232/quartus_prj/rs232.qsf | 92 + .../examples/05_rs232/rs232/quartus_prj/rs232.qws | Bin 0 -> 1327 bytes .../quartus_prj/rs232_assignment_defaults.qdf | 805 + .../quartus_prj/simulation/modelsim/rs232.sft | 6 + .../rs232/quartus_prj/simulation/modelsim/rs232.vo | 2836 +++ .../simulation/modelsim/rs232_8_1200mv_0c_slow.vo | 2836 +++ .../modelsim/rs232_8_1200mv_0c_v_slow.sdo | 2275 ++ .../simulation/modelsim/rs232_8_1200mv_85c_slow.vo | 2836 +++ .../modelsim/rs232_8_1200mv_85c_v_slow.sdo | 2275 ++ .../modelsim/rs232_min_1200mv_0c_fast.vo | 2836 +++ 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.../examples/06_uart_sd/uart_sd/rtl/uart_sd.v | 162 + .../examples/06_uart_sd/uart_sd/rtl/uart_tx.v | 104 + ...56\236\351\252\214\347\216\260\350\261\241.txt" | 6 + ...27\266\345\272\217\346\240\207\345\207\206.pdf" | Bin 0 -> 1086239 bytes .../examples/07_hdmi/hdmi/doc/hdmi_colorbar.vsdx | Bin 0 -> 807294 bytes .../07_hdmi/hdmi/quartus_prj/PLLJ_PLLSPE_INFO.txt | 5 + .../examples/07_hdmi/hdmi/quartus_prj/ddio_out.qip | 0 .../hdmi/quartus_prj/greybox_tmp/cbx_args.txt | 13 + .../07_hdmi/hdmi/quartus_prj/hdmi_colorbar.qpf | 30 + .../07_hdmi/hdmi/quartus_prj/hdmi_colorbar.qsf | 98 + .../07_hdmi/hdmi/quartus_prj/hdmi_colorbar.qws | Bin 0 -> 613 bytes .../hdmi_colorbar_assignment_defaults.qdf | 805 + .../hdmi/quartus_prj/ip_core/clk_gen/clk_gen.ppf | 12 + .../hdmi/quartus_prj/ip_core/clk_gen/clk_gen.qip | 6 + .../hdmi/quartus_prj/ip_core/clk_gen/clk_gen.v | 348 + .../hdmi/quartus_prj/ip_core/clk_gen/clk_gen_bb.v | 232 + .../quartus_prj/ip_core/clk_gen/clk_gen_inst.v | 7 + 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smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v create mode 100644 smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v.bak create mode 100644 "smh-ac415-fpga/examples/02_water_rgb/\345\256\236\351\252\214\347\216\260\350\261\241.txt" create mode 100644 smh-ac415-fpga/examples/03_smg595/smg595_static/doc/seg_595_static.vsdx create mode 100644 smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/seg_595_static.qpf create mode 100644 smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/seg_595_static.qsf create mode 100644 smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/seg_595_static.qws create mode 100644 smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static.sft create mode 100644 smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static.vo create mode 100644 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smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qws create mode 100644 smh-ac415-fpga/examples/09_vga/vga/rtl/vga_colorbar.v create mode 100644 smh-ac415-fpga/examples/09_vga/vga/rtl/vga_ctrl.v create mode 100644 smh-ac415-fpga/examples/09_vga/vga/rtl/vga_pic.v create mode 100644 smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_colorbar.v create mode 100644 smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_ctrl.v create mode 100644 "smh-ac415-fpga/examples/09_vga/\345\256\236\351\252\214\347\216\260\350\261\241.txt" diff --git a/smh-ac415-fpga/examples/01_led/led/led.qpf b/smh-ac415-fpga/examples/01_led/led/led.qpf new file mode 100644 index 0000000..5592af6 --- /dev/null +++ b/smh-ac415-fpga/examples/01_led/led/led.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 01:45:54 June 02, 2023 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "01:45:54 June 02, 2023" + +# Revisions + +PROJECT_REVISION = "led" diff --git a/smh-ac415-fpga/examples/01_led/led/led.qsf b/smh-ac415-fpga/examples/01_led/led/led.qsf new file mode 100644 index 0000000..1b5ae22 --- /dev/null +++ b/smh-ac415-fpga/examples/01_led/led/led.qsf @@ -0,0 +1,65 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 01:45:54 June 02, 2023 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# led_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE15F23C8 +set_global_assignment -name TOP_LEVEL_ENTITY led +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:45:54 JUNE 02, 2023" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name VERILOG_FILE led.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_location_assignment PIN_F12 -to key1 +set_location_assignment PIN_F13 -to key2 +set_location_assignment PIN_F14 -to key3 +set_location_assignment PIN_F15 -to key4 +set_location_assignment PIN_U20 -to key5 +set_location_assignment PIN_AB16 -to led1 +set_location_assignment PIN_AA17 -to led2 +set_location_assignment PIN_AA21 -to led3 +set_location_assignment PIN_W22 -to led4 +set_location_assignment PIN_W17 -to led5 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/smh-ac415-fpga/examples/01_led/led/led.qws b/smh-ac415-fpga/examples/01_led/led/led.qws new file mode 100644 index 0000000..5433526 Binary files /dev/null and b/smh-ac415-fpga/examples/01_led/led/led.qws differ diff --git a/smh-ac415-fpga/examples/01_led/led/led.v b/smh-ac415-fpga/examples/01_led/led/led.v new file mode 100644 index 0000000..6c849bc --- /dev/null +++ b/smh-ac415-fpga/examples/01_led/led/led.v @@ -0,0 +1,21 @@ +module led( +input key1, +input key2, +input key3, +input key4, +input key5, +output led1, +output led2, +output led3, +output led4, +output led5 + ); + + assign led1=key1; + assign led2=key2; + assign led3=key3; + assign led4=key4; + assign led5=key5; + + +endmodule \ No newline at end of file diff --git "a/smh-ac415-fpga/examples/01_led/\345\256\236\351\252\214\347\216\260\350\261\241.txt" "b/smh-ac415-fpga/examples/01_led/\345\256\236\351\252\214\347\216\260\350\261\241.txt" new file mode 100644 index 0000000..06a5264 --- /dev/null +++ "b/smh-ac415-fpga/examples/01_led/\345\256\236\351\252\214\347\216\260\350\261\241.txt" @@ -0,0 +1,2 @@ +现象：按下k1,k2,k3,k4,rst,分别有led灯对应点亮。 +测试：可以测试5个用户按钮是否正常。 \ No newline at end of file diff --git a/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qpf b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qpf new file mode 100644 index 0000000..75f7176 --- /dev/null +++ b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 02:23:16 June 02, 2023 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "02:23:16 June 02, 2023" + +# Revisions + +PROJECT_REVISION = "water_rgb" diff --git a/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qsf b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qsf new file mode 100644 index 0000000..1895fba --- /dev/null +++ b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qsf @@ -0,0 +1,69 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 02:23:16 June 02, 2023 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# water_rgb_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE15F23C8 +set_global_assignment -name TOP_LEVEL_ENTITY water_rgb +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "02:23:16 JUNE 02, 2023" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name VERILOG_FILE water_rgb.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_location_assignment PIN_V22 -to led_out[11] +set_location_assignment PIN_V21 -to led_out[10] +set_location_assignment PIN_W22 -to led_out[9] +set_location_assignment PIN_W21 -to led_out[8] +set_location_assignment PIN_Y22 -to led_out[7] +set_location_assignment PIN_AA21 -to led_out[6] +set_location_assignment PIN_AB20 -to led_out[5] +set_location_assignment PIN_AA20 -to led_out[4] +set_location_assignment PIN_AA17 -to led_out[3] +set_location_assignment PIN_Y17 -to led_out[2] +set_location_assignment PIN_W17 -to led_out[1] +set_location_assignment PIN_AB16 -to led_out[0] +set_location_assignment PIN_T22 -to sys_clk +set_location_assignment PIN_U20 -to sys_rst_n +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qws b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qws new file mode 100644 index 0000000..f52d856 Binary files /dev/null and b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.qws differ diff --git a/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v new file mode 100644 index 0000000..3e5789b --- /dev/null +++ b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v @@ -0,0 +1,45 @@ +`timescale 1ns/1ns + +module water_rgb +#( + parameter CNT_MAX = 25'd24_999_999 +) +( + input wire sys_clk , + input wire sys_rst_n , + + output wire [11:0] led_out + +); + +reg [24:0] cnt ; +reg cnt_flag ; +reg [11:0] led_out_reg ; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt <= 25'b0; + else if(cnt == CNT_MAX) + cnt <= 25'b0; + else + cnt <= cnt + 1'b1; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_flag <= 1'b0; + else if(cnt == CNT_MAX - 1) + cnt_flag <= 1'b1; + else + cnt_flag <= 1'b0; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + led_out_reg <= 12'b000000000001; + else if(led_out_reg == 12'b1000000000000 && cnt_flag == 1'b1) + led_out_reg <= 12'b000000000001; + else if(cnt_flag == 1'b1) + led_out_reg <= led_out_reg << 1'b1; + +assign led_out = ~led_out_reg; + +endmodule diff --git a/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v.bak b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v.bak new file mode 100644 index 0000000..26b5726 --- /dev/null +++ b/smh-ac415-fpga/examples/02_water_rgb/water_rgb/water_rgb.v.bak @@ -0,0 +1,45 @@ +`timescale 1ns/1ns + +module water_led +#( + parameter CNT_MAX = 25'd24_999_999 +) +( + input wire sys_clk , + input wire sys_rst_n , + + output wire [11:0] led_out + +); + +reg [24:0] cnt ; +reg cnt_flag ; +reg [11:0] led_out_reg ; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt <= 25'b0; + else if(cnt == CNT_MAX) + cnt <= 25'b0; + else + cnt <= cnt + 1'b1; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_flag <= 1'b0; + else if(cnt == CNT_MAX - 1) + cnt_flag <= 1'b1; + else + cnt_flag <= 1'b0; + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + led_out_reg <= 12'b000000000001; + else if(led_out_reg == 12'b1000000000000 && cnt_flag == 1'b1) + led_out_reg <= 12'b000000000001; + else if(cnt_flag == 1'b1) + led_out_reg <= led_out_reg << 1'b1; + +assign led_out = ~led_out_reg; + +endmodule diff --git "a/smh-ac415-fpga/examples/02_water_rgb/\345\256\236\351\252\214\347\216\260\350\261\241.txt" "b/smh-ac415-fpga/examples/02_water_rgb/\345\256\236\351\252\214\347\216\260\350\261\241.txt" new file mode 100644 index 0000000..1bddefc --- /dev/null +++ "b/smh-ac415-fpga/examples/02_water_rgb/\345\256\236\351\252\214\347\216\260\350\261\241.txt" @@ -0,0 +1,2 @@ +现象：4颗三色RGB灯依次闪烁。 +测试：可以测试4颗三色RGB灯是否正常。 \ No newline at end of file diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/doc/seg_595_static.vsdx b/smh-ac415-fpga/examples/03_smg595/smg595_static/doc/seg_595_static.vsdx new file mode 100644 index 0000000..5815b63 Binary files /dev/null and b/smh-ac415-fpga/examples/03_smg595/smg595_static/doc/seg_595_static.vsdx differ diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/seg_595_static.qpf b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/seg_595_static.qpf new file mode 100644 index 0000000..7eeffdb --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/seg_595_static.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 17:00:15 February 24, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "17:00:15 February 24, 2020" + +# Revisions + +PROJECT_REVISION = "seg_595_static" diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/seg_595_static.qsf b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/seg_595_static.qsf new file mode 100644 index 0000000..6b62eea --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/seg_595_static.qsf @@ -0,0 +1,76 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 17:00:15 February 24, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# seg_595_static_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE15F23C8 +set_global_assignment -name TOP_LEVEL_ENTITY seg_595_static +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:00:15 FEBRUARY 24, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb_seg_595_static -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME tb_seg_595_static -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_seg_595_static +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_seg_595_static +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_seg_595_static -section_id tb_seg_595_static +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_seg_595_static.v -section_id tb_seg_595_static +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_location_assignment PIN_AA1 -to ds +set_location_assignment PIN_Y2 -to oe +set_location_assignment PIN_W1 -to shcp +set_location_assignment PIN_Y1 -to stcp +set_location_assignment PIN_T22 -to sys_clk +set_location_assignment PIN_U20 -to sys_rst_n +set_global_assignment -name VERILOG_FILE ../sim/tb_seg_595_static.v +set_global_assignment -name VERILOG_FILE ../rtl/seg_static.v +set_global_assignment -name VERILOG_FILE ../rtl/seg_595_static.v +set_global_assignment -name VERILOG_FILE ../rtl/hc595_ctrl.v +set_global_assignment -name CDF_FILE output_files/Chain1.cdf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/seg_595_static.qws b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/seg_595_static.qws new file mode 100644 index 0000000..e1ce986 Binary files /dev/null and b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/seg_595_static.qws differ diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static.sft b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static.sft new file mode 100644 index 0000000..e1d89f4 --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static.sft @@ -0,0 +1,6 @@ +set tool_name "ModelSim (Verilog)" +set corner_file_list { + {{"Slow -8 1.2V 85 Model"} {seg_595_static_8_1200mv_85c_slow.vo seg_595_static_8_1200mv_85c_v_slow.sdo}} + {{"Slow -8 1.2V 0 Model"} {seg_595_static_8_1200mv_0c_slow.vo seg_595_static_8_1200mv_0c_v_slow.sdo}} + {{"Fast -M 1.2V 0 Model"} {seg_595_static_min_1200mv_0c_fast.vo seg_595_static_min_1200mv_0c_v_fast.sdo}} +} diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static.vo b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static.vo new file mode 100644 index 0000000..3d4f4c9 --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static.vo @@ -0,0 +1,2444 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 20:55:14" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module seg_595_static ( + sys_clk, + sys_rst_n, + stcp, + shcp, + ds, + oe); +input sys_clk; +input sys_rst_n; +output stcp; +output shcp; +output ds; +output oe; + +// Design Ports Information +// stcp => Location: PIN_Y1, I/O Standard: 2.5 V, Current Strength: Default +// shcp => Location: PIN_W1, I/O Standard: 2.5 V, Current Strength: Default +// ds => Location: PIN_AA1, I/O Standard: 2.5 V, Current Strength: Default +// oe => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("seg_595_static_v.sdo"); +// synopsys translate_on + +wire \seg_static_inst|Add0~4_combout ; +wire \seg_static_inst|Add0~14_combout ; +wire \seg_static_inst|Add0~19 ; +wire \seg_static_inst|Add0~20_combout ; +wire \seg_static_inst|Add0~21 ; +wire \seg_static_inst|Add0~22_combout ; +wire \seg_static_inst|Add0~23 ; +wire \seg_static_inst|Add0~24_combout ; +wire \seg_static_inst|Add0~25 ; +wire \seg_static_inst|Add0~26_combout ; +wire \seg_static_inst|Add0~27 ; +wire \seg_static_inst|Add0~28_combout ; +wire \seg_static_inst|Add0~29 ; +wire \seg_static_inst|Add0~30_combout ; +wire \seg_static_inst|Add0~31 ; +wire \seg_static_inst|Add0~32_combout ; +wire \seg_static_inst|Add0~33 ; +wire \seg_static_inst|Add0~34_combout ; +wire \seg_static_inst|Add0~35 ; +wire \seg_static_inst|Add0~36_combout ; +wire \seg_static_inst|Add0~37 ; +wire \seg_static_inst|Add0~38_combout ; +wire \seg_static_inst|Add0~39 ; +wire \seg_static_inst|Add0~40_combout ; +wire \seg_static_inst|Add0~41 ; +wire \seg_static_inst|Add0~42_combout ; +wire \seg_static_inst|Add0~43 ; +wire \seg_static_inst|Add0~44_combout ; +wire \seg_static_inst|Add0~45 ; +wire \seg_static_inst|Add0~46_combout ; +wire \hc595_ctrl_inst|ds~0_combout ; +wire \seg_static_inst|WideOr2~0_combout ; +wire \seg_static_inst|Equal0~0_combout ; +wire \seg_static_inst|Equal0~1_combout ; +wire \seg_static_inst|Equal0~2_combout ; +wire \seg_static_inst|Equal0~3_combout ; +wire \seg_static_inst|Equal0~4_combout ; +wire \seg_static_inst|cnt_wait~0_combout ; +wire \seg_static_inst|cnt_wait~1_combout ; +wire \seg_static_inst|cnt_wait~2_combout ; +wire \seg_static_inst|cnt_wait~3_combout ; +wire \seg_static_inst|cnt_wait~4_combout ; +wire \seg_static_inst|cnt_wait~5_combout ; +wire \seg_static_inst|cnt_wait~6_combout ; +wire \seg_static_inst|cnt_wait~7_combout ; +wire \seg_static_inst|cnt_wait~8_combout ; +wire \seg_static_inst|cnt_wait~9_combout ; +wire \seg_static_inst|cnt_wait~10_combout ; +wire \stcp~output_o ; +wire \shcp~output_o ; +wire \ds~output_o ; +wire \oe~output_o ; +wire \sys_clk~input_o ; +wire \sys_clk~inputclkctrl_outclk ; +wire \hc595_ctrl_inst|cnt_4[0]~0_combout ; +wire \sys_rst_n~input_o ; +wire \hc595_ctrl_inst|cnt_bit[0]~1_combout ; +wire \hc595_ctrl_inst|cnt_bit[1]~0_combout ; +wire \hc595_ctrl_inst|always2~0_combout ; +wire \seg_static_inst|Add0~0_combout ; +wire \hc595_ctrl_inst|Equal1~0_combout ; +wire \hc595_ctrl_inst|cnt_bit[3]~2_combout ; +wire \hc595_ctrl_inst|always2~1_combout ; +wire \hc595_ctrl_inst|stcp~feeder_combout ; +wire \hc595_ctrl_inst|stcp~q ; +wire \hc595_ctrl_inst|shcp~q ; +wire \hc595_ctrl_inst|cnt_bit[2]~3_combout ; +wire \seg_static_inst|Add0~1 ; +wire \seg_static_inst|Add0~2_combout ; +wire \seg_static_inst|Add0~3 ; +wire \seg_static_inst|Add0~5 ; +wire \seg_static_inst|Add0~6_combout ; +wire \seg_static_inst|Add0~7 ; +wire \seg_static_inst|Add0~8_combout ; +wire \seg_static_inst|Add0~9 ; +wire \seg_static_inst|Add0~10_combout ; +wire \seg_static_inst|cnt_wait~11_combout ; +wire \seg_static_inst|Add0~11 ; +wire \seg_static_inst|Add0~12_combout ; +wire \seg_static_inst|Add0~13 ; +wire \seg_static_inst|Add0~15 ; +wire \seg_static_inst|Add0~16_combout ; +wire \seg_static_inst|Add0~17 ; +wire \seg_static_inst|Add0~18_combout ; +wire \seg_static_inst|Equal0~5_combout ; +wire \seg_static_inst|Equal0~6_combout ; +wire \seg_static_inst|Equal0~7_combout ; +wire \seg_static_inst|add_flag~feeder_combout ; +wire \seg_static_inst|add_flag~q ; +wire \seg_static_inst|num[0]~0_combout ; +wire \seg_static_inst|num[1]~1_combout ; +wire \seg_static_inst|num[2]~2_combout ; +wire \seg_static_inst|num[3]~3_combout ; +wire \seg_static_inst|num[3]~4_combout ; +wire \seg_static_inst|WideOr1~0_combout ; +wire \seg_static_inst|seg[7]~feeder_combout ; +wire \seg_static_inst|WideOr0~0_combout ; +wire \hc595_ctrl_inst|Mux0~2_combout ; +wire \hc595_ctrl_inst|Mux0~3_combout ; +wire \hc595_ctrl_inst|ds~2_combout ; +wire \seg_static_inst|WideOr4~0_combout ; +wire \seg_static_inst|WideOr3~0_combout ; +wire \seg_static_inst|WideOr5~0_combout ; +wire \hc595_ctrl_inst|Mux0~0_combout ; +wire \seg_static_inst|WideOr6~0_combout ; +wire \hc595_ctrl_inst|Mux0~1_combout ; +wire \hc595_ctrl_inst|ds~1_combout ; +wire \hc595_ctrl_inst|ds~3_combout ; +wire \hc595_ctrl_inst|ds~q ; +wire [7:0] \seg_static_inst|seg ; +wire [3:0] \seg_static_inst|num ; +wire [24:0] \seg_static_inst|cnt_wait ; +wire [3:0] \hc595_ctrl_inst|cnt_bit ; +wire [1:0] \hc595_ctrl_inst|cnt_4 ; + + +// Location: LCCOMB_X14_Y13_N12 +cycloneive_lcell_comb \seg_static_inst|Add0~4 ( +// Equation(s): +// \seg_static_inst|Add0~4_combout = (\seg_static_inst|cnt_wait [3] & (\seg_static_inst|Add0~3 $ (GND))) # (!\seg_static_inst|cnt_wait [3] & (!\seg_static_inst|Add0~3 & VCC)) +// \seg_static_inst|Add0~5 = CARRY((\seg_static_inst|cnt_wait [3] & !\seg_static_inst|Add0~3 )) + + .dataa(\seg_static_inst|cnt_wait [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~3 ), + .combout(\seg_static_inst|Add0~4_combout ), + .cout(\seg_static_inst|Add0~5 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \seg_static_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N22 +cycloneive_lcell_comb \seg_static_inst|Add0~14 ( +// Equation(s): +// \seg_static_inst|Add0~14_combout = (\seg_static_inst|cnt_wait [8] & (!\seg_static_inst|Add0~13 )) # (!\seg_static_inst|cnt_wait [8] & ((\seg_static_inst|Add0~13 ) # (GND))) +// \seg_static_inst|Add0~15 = CARRY((!\seg_static_inst|Add0~13 ) # (!\seg_static_inst|cnt_wait [8])) + + .dataa(\seg_static_inst|cnt_wait [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~13 ), + .combout(\seg_static_inst|Add0~14_combout ), + .cout(\seg_static_inst|Add0~15 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N26 +cycloneive_lcell_comb \seg_static_inst|Add0~18 ( +// Equation(s): +// \seg_static_inst|Add0~18_combout = (\seg_static_inst|cnt_wait [10] & (!\seg_static_inst|Add0~17 )) # (!\seg_static_inst|cnt_wait [10] & ((\seg_static_inst|Add0~17 ) # (GND))) +// \seg_static_inst|Add0~19 = CARRY((!\seg_static_inst|Add0~17 ) # (!\seg_static_inst|cnt_wait [10])) + + .dataa(\seg_static_inst|cnt_wait [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~17 ), + .combout(\seg_static_inst|Add0~18_combout ), + .cout(\seg_static_inst|Add0~19 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~18 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N28 +cycloneive_lcell_comb \seg_static_inst|Add0~20 ( +// Equation(s): +// \seg_static_inst|Add0~20_combout = (\seg_static_inst|cnt_wait [11] & (\seg_static_inst|Add0~19 $ (GND))) # (!\seg_static_inst|cnt_wait [11] & (!\seg_static_inst|Add0~19 & VCC)) +// \seg_static_inst|Add0~21 = CARRY((\seg_static_inst|cnt_wait [11] & !\seg_static_inst|Add0~19 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [11]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~19 ), + .combout(\seg_static_inst|Add0~20_combout ), + .cout(\seg_static_inst|Add0~21 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~20 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N30 +cycloneive_lcell_comb \seg_static_inst|Add0~22 ( +// Equation(s): +// \seg_static_inst|Add0~22_combout = (\seg_static_inst|cnt_wait [12] & (!\seg_static_inst|Add0~21 )) # (!\seg_static_inst|cnt_wait [12] & ((\seg_static_inst|Add0~21 ) # (GND))) +// \seg_static_inst|Add0~23 = CARRY((!\seg_static_inst|Add0~21 ) # (!\seg_static_inst|cnt_wait [12])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [12]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~21 ), + .combout(\seg_static_inst|Add0~22_combout ), + .cout(\seg_static_inst|Add0~23 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~22 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N0 +cycloneive_lcell_comb \seg_static_inst|Add0~24 ( +// Equation(s): +// \seg_static_inst|Add0~24_combout = (\seg_static_inst|cnt_wait [13] & (\seg_static_inst|Add0~23 $ (GND))) # (!\seg_static_inst|cnt_wait [13] & (!\seg_static_inst|Add0~23 & VCC)) +// \seg_static_inst|Add0~25 = CARRY((\seg_static_inst|cnt_wait [13] & !\seg_static_inst|Add0~23 )) + + .dataa(\seg_static_inst|cnt_wait [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~23 ), + .combout(\seg_static_inst|Add0~24_combout ), + .cout(\seg_static_inst|Add0~25 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~24 .lut_mask = 16'hA50A; +defparam \seg_static_inst|Add0~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N2 +cycloneive_lcell_comb \seg_static_inst|Add0~26 ( +// Equation(s): +// \seg_static_inst|Add0~26_combout = (\seg_static_inst|cnt_wait [14] & (!\seg_static_inst|Add0~25 )) # (!\seg_static_inst|cnt_wait [14] & ((\seg_static_inst|Add0~25 ) # (GND))) +// \seg_static_inst|Add0~27 = CARRY((!\seg_static_inst|Add0~25 ) # (!\seg_static_inst|cnt_wait [14])) + + .dataa(\seg_static_inst|cnt_wait [14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~25 ), + .combout(\seg_static_inst|Add0~26_combout ), + .cout(\seg_static_inst|Add0~27 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~26 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N4 +cycloneive_lcell_comb \seg_static_inst|Add0~28 ( +// Equation(s): +// \seg_static_inst|Add0~28_combout = (\seg_static_inst|cnt_wait [15] & (\seg_static_inst|Add0~27 $ (GND))) # (!\seg_static_inst|cnt_wait [15] & (!\seg_static_inst|Add0~27 & VCC)) +// \seg_static_inst|Add0~29 = CARRY((\seg_static_inst|cnt_wait [15] & !\seg_static_inst|Add0~27 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [15]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~27 ), + .combout(\seg_static_inst|Add0~28_combout ), + .cout(\seg_static_inst|Add0~29 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~28 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N6 +cycloneive_lcell_comb \seg_static_inst|Add0~30 ( +// Equation(s): +// \seg_static_inst|Add0~30_combout = (\seg_static_inst|cnt_wait [16] & (!\seg_static_inst|Add0~29 )) # (!\seg_static_inst|cnt_wait [16] & ((\seg_static_inst|Add0~29 ) # (GND))) +// \seg_static_inst|Add0~31 = CARRY((!\seg_static_inst|Add0~29 ) # (!\seg_static_inst|cnt_wait [16])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [16]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~29 ), + .combout(\seg_static_inst|Add0~30_combout ), + .cout(\seg_static_inst|Add0~31 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~30 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N8 +cycloneive_lcell_comb \seg_static_inst|Add0~32 ( +// Equation(s): +// \seg_static_inst|Add0~32_combout = (\seg_static_inst|cnt_wait [17] & (\seg_static_inst|Add0~31 $ (GND))) # (!\seg_static_inst|cnt_wait [17] & (!\seg_static_inst|Add0~31 & VCC)) +// \seg_static_inst|Add0~33 = CARRY((\seg_static_inst|cnt_wait [17] & !\seg_static_inst|Add0~31 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [17]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~31 ), + .combout(\seg_static_inst|Add0~32_combout ), + .cout(\seg_static_inst|Add0~33 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~32 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N10 +cycloneive_lcell_comb \seg_static_inst|Add0~34 ( +// Equation(s): +// \seg_static_inst|Add0~34_combout = (\seg_static_inst|cnt_wait [18] & (!\seg_static_inst|Add0~33 )) # (!\seg_static_inst|cnt_wait [18] & ((\seg_static_inst|Add0~33 ) # (GND))) +// \seg_static_inst|Add0~35 = CARRY((!\seg_static_inst|Add0~33 ) # (!\seg_static_inst|cnt_wait [18])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [18]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~33 ), + .combout(\seg_static_inst|Add0~34_combout ), + .cout(\seg_static_inst|Add0~35 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~34 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N12 +cycloneive_lcell_comb \seg_static_inst|Add0~36 ( +// Equation(s): +// \seg_static_inst|Add0~36_combout = (\seg_static_inst|cnt_wait [19] & (\seg_static_inst|Add0~35 $ (GND))) # (!\seg_static_inst|cnt_wait [19] & (!\seg_static_inst|Add0~35 & VCC)) +// \seg_static_inst|Add0~37 = CARRY((\seg_static_inst|cnt_wait [19] & !\seg_static_inst|Add0~35 )) + + .dataa(\seg_static_inst|cnt_wait [19]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~35 ), + .combout(\seg_static_inst|Add0~36_combout ), + .cout(\seg_static_inst|Add0~37 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~36 .lut_mask = 16'hA50A; +defparam \seg_static_inst|Add0~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N14 +cycloneive_lcell_comb \seg_static_inst|Add0~38 ( +// Equation(s): +// \seg_static_inst|Add0~38_combout = (\seg_static_inst|cnt_wait [20] & (!\seg_static_inst|Add0~37 )) # (!\seg_static_inst|cnt_wait [20] & ((\seg_static_inst|Add0~37 ) # (GND))) +// \seg_static_inst|Add0~39 = CARRY((!\seg_static_inst|Add0~37 ) # (!\seg_static_inst|cnt_wait [20])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [20]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~37 ), + .combout(\seg_static_inst|Add0~38_combout ), + .cout(\seg_static_inst|Add0~39 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~38 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N16 +cycloneive_lcell_comb \seg_static_inst|Add0~40 ( +// Equation(s): +// \seg_static_inst|Add0~40_combout = (\seg_static_inst|cnt_wait [21] & (\seg_static_inst|Add0~39 $ (GND))) # (!\seg_static_inst|cnt_wait [21] & (!\seg_static_inst|Add0~39 & VCC)) +// \seg_static_inst|Add0~41 = CARRY((\seg_static_inst|cnt_wait [21] & !\seg_static_inst|Add0~39 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [21]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~39 ), + .combout(\seg_static_inst|Add0~40_combout ), + .cout(\seg_static_inst|Add0~41 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~40 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N18 +cycloneive_lcell_comb \seg_static_inst|Add0~42 ( +// Equation(s): +// \seg_static_inst|Add0~42_combout = (\seg_static_inst|cnt_wait [22] & (!\seg_static_inst|Add0~41 )) # (!\seg_static_inst|cnt_wait [22] & ((\seg_static_inst|Add0~41 ) # (GND))) +// \seg_static_inst|Add0~43 = CARRY((!\seg_static_inst|Add0~41 ) # (!\seg_static_inst|cnt_wait [22])) + + .dataa(\seg_static_inst|cnt_wait [22]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~41 ), + .combout(\seg_static_inst|Add0~42_combout ), + .cout(\seg_static_inst|Add0~43 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~42 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N20 +cycloneive_lcell_comb \seg_static_inst|Add0~44 ( +// Equation(s): +// \seg_static_inst|Add0~44_combout = (\seg_static_inst|cnt_wait [23] & (\seg_static_inst|Add0~43 $ (GND))) # (!\seg_static_inst|cnt_wait [23] & (!\seg_static_inst|Add0~43 & VCC)) +// \seg_static_inst|Add0~45 = CARRY((\seg_static_inst|cnt_wait [23] & !\seg_static_inst|Add0~43 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [23]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~43 ), + .combout(\seg_static_inst|Add0~44_combout ), + .cout(\seg_static_inst|Add0~45 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~44 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N22 +cycloneive_lcell_comb \seg_static_inst|Add0~46 ( +// Equation(s): +// \seg_static_inst|Add0~46_combout = \seg_static_inst|Add0~45 $ (\seg_static_inst|cnt_wait [24]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\seg_static_inst|cnt_wait [24]), + .cin(\seg_static_inst|Add0~45 ), + .combout(\seg_static_inst|Add0~46_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Add0~46 .lut_mask = 16'h0FF0; +defparam \seg_static_inst|Add0~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N10 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~0 ( +// Equation(s): +// \hc595_ctrl_inst|ds~0_combout = (!\hc595_ctrl_inst|cnt_4 [1] & !\hc595_ctrl_inst|cnt_4 [0]) + + .dataa(\hc595_ctrl_inst|cnt_4 [1]), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(gnd), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~0 .lut_mask = 16'h0505; +defparam \hc595_ctrl_inst|ds~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N27 +dffeas \seg_static_inst|seg[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr2~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[4] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N26 +cycloneive_lcell_comb \seg_static_inst|WideOr2~0 ( +// Equation(s): +// \seg_static_inst|WideOr2~0_combout = (\seg_static_inst|num [1] & (\seg_static_inst|num [0] & (!\seg_static_inst|num [3]))) # (!\seg_static_inst|num [1] & ((\seg_static_inst|num [2] & ((!\seg_static_inst|num [3]))) # (!\seg_static_inst|num [2] & +// (\seg_static_inst|num [0])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr2~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr2~0 .lut_mask = 16'h223A; +defparam \seg_static_inst|WideOr2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N3 +dffeas \seg_static_inst|cnt_wait[24] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [24]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[24] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[24] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N21 +dffeas \seg_static_inst|cnt_wait[23] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~44_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [23]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[23] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N24 +cycloneive_lcell_comb \seg_static_inst|Equal0~0 ( +// Equation(s): +// \seg_static_inst|Equal0~0_combout = (\hc595_ctrl_inst|cnt_4 [1] & (!\seg_static_inst|cnt_wait [23] & (\hc595_ctrl_inst|cnt_4 [0] & \seg_static_inst|cnt_wait [24]))) + + .dataa(\hc595_ctrl_inst|cnt_4 [1]), + .datab(\seg_static_inst|cnt_wait [23]), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(\seg_static_inst|cnt_wait [24]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~0 .lut_mask = 16'h2000; +defparam \seg_static_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N7 +dffeas \seg_static_inst|cnt_wait[22] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [22]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[22] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[22] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N25 +dffeas \seg_static_inst|cnt_wait[21] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [21]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[21] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[21] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N9 +dffeas \seg_static_inst|cnt_wait[20] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [20]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[20] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[20] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N27 +dffeas \seg_static_inst|cnt_wait[19] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [19]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[19] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N10 +cycloneive_lcell_comb \seg_static_inst|Equal0~1 ( +// Equation(s): +// \seg_static_inst|Equal0~1_combout = (\seg_static_inst|cnt_wait [22] & (\seg_static_inst|cnt_wait [20] & (\seg_static_inst|cnt_wait [19] & \seg_static_inst|cnt_wait [21]))) + + .dataa(\seg_static_inst|cnt_wait [22]), + .datab(\seg_static_inst|cnt_wait [20]), + .datac(\seg_static_inst|cnt_wait [19]), + .datad(\seg_static_inst|cnt_wait [21]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N29 +dffeas \seg_static_inst|cnt_wait[18] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [18]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[18] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[18] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N29 +dffeas \seg_static_inst|cnt_wait[16] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~6_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [16]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[16] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[16] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N9 +dffeas \seg_static_inst|cnt_wait[17] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~32_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [17]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[17] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[17] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N5 +dffeas \seg_static_inst|cnt_wait[15] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~28_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [15]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[15] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N18 +cycloneive_lcell_comb \seg_static_inst|Equal0~2 ( +// Equation(s): +// \seg_static_inst|Equal0~2_combout = (!\seg_static_inst|cnt_wait [17] & (\seg_static_inst|cnt_wait [16] & (!\seg_static_inst|cnt_wait [15] & \seg_static_inst|cnt_wait [18]))) + + .dataa(\seg_static_inst|cnt_wait [17]), + .datab(\seg_static_inst|cnt_wait [16]), + .datac(\seg_static_inst|cnt_wait [15]), + .datad(\seg_static_inst|cnt_wait [18]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~2 .lut_mask = 16'h0400; +defparam \seg_static_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N21 +dffeas \seg_static_inst|cnt_wait[14] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~7_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [14]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[14] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N31 +dffeas \seg_static_inst|cnt_wait[13] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~8_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [13]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[13] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N23 +dffeas \seg_static_inst|cnt_wait[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~9_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [12]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[12] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[12] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N1 +dffeas \seg_static_inst|cnt_wait[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~10_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [11]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[11] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N26 +cycloneive_lcell_comb \seg_static_inst|Equal0~3 ( +// Equation(s): +// \seg_static_inst|Equal0~3_combout = (\seg_static_inst|cnt_wait [11] & (\seg_static_inst|cnt_wait [14] & (\seg_static_inst|cnt_wait [12] & \seg_static_inst|cnt_wait [13]))) + + .dataa(\seg_static_inst|cnt_wait [11]), + .datab(\seg_static_inst|cnt_wait [14]), + .datac(\seg_static_inst|cnt_wait [12]), + .datad(\seg_static_inst|cnt_wait [13]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~3 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N12 +cycloneive_lcell_comb \seg_static_inst|Equal0~4 ( +// Equation(s): +// \seg_static_inst|Equal0~4_combout = (\seg_static_inst|Equal0~1_combout & (\seg_static_inst|Equal0~2_combout & (\seg_static_inst|Equal0~3_combout & \seg_static_inst|Equal0~0_combout ))) + + .dataa(\seg_static_inst|Equal0~1_combout ), + .datab(\seg_static_inst|Equal0~2_combout ), + .datac(\seg_static_inst|Equal0~3_combout ), + .datad(\seg_static_inst|Equal0~0_combout ), + .cin(gnd), + .combout(\seg_static_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~4 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N23 +dffeas \seg_static_inst|cnt_wait[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [8]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[8] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N13 +dffeas \seg_static_inst|cnt_wait[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [3]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[3] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N2 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~0 ( +// Equation(s): +// \seg_static_inst|cnt_wait~0_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~46_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~46_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~0 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N6 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~1 ( +// Equation(s): +// \seg_static_inst|cnt_wait~1_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~42_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~42_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~1_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~1 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N24 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~2 ( +// Equation(s): +// \seg_static_inst|cnt_wait~2_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~40_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~40_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~2_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~2 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N8 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~3 ( +// Equation(s): +// \seg_static_inst|cnt_wait~3_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~38_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~3_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~3 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N26 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~4 ( +// Equation(s): +// \seg_static_inst|cnt_wait~4_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~36_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~36_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~4_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~4 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N28 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~5 ( +// Equation(s): +// \seg_static_inst|cnt_wait~5_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~34_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~34_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~5_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~5 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N28 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~6 ( +// Equation(s): +// \seg_static_inst|cnt_wait~6_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~30_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~30_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~6_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~6 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N20 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~7 ( +// Equation(s): +// \seg_static_inst|cnt_wait~7_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~26_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~26_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~7_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~7 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N30 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~8 ( +// Equation(s): +// \seg_static_inst|cnt_wait~8_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~24_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~24_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~8_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~8 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N22 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~9 ( +// Equation(s): +// \seg_static_inst|cnt_wait~9_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~22_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~22_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~9_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~9 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N0 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~10 ( +// Equation(s): +// \seg_static_inst|cnt_wait~10_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~20_combout ) + + .dataa(gnd), + .datab(\seg_static_inst|Equal0~7_combout ), + .datac(\seg_static_inst|Add0~20_combout ), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~10_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~10 .lut_mask = 16'h3030; +defparam \seg_static_inst|cnt_wait~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y6_N9 +cycloneive_io_obuf \stcp~output ( + .i(\hc595_ctrl_inst|stcp~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\stcp~output_o ), + .obar()); +// synopsys translate_off +defparam \stcp~output .bus_hold = "false"; +defparam \stcp~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y7_N23 +cycloneive_io_obuf \shcp~output ( + .i(\hc595_ctrl_inst|shcp~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\shcp~output_o ), + .obar()); +// synopsys translate_off +defparam \shcp~output .bus_hold = "false"; +defparam \shcp~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y5_N16 +cycloneive_io_obuf \ds~output ( + .i(\hc595_ctrl_inst|ds~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\ds~output_o ), + .obar()); +// synopsys translate_off +defparam \ds~output .bus_hold = "false"; +defparam \ds~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y6_N2 +cycloneive_io_obuf \oe~output ( + .i(!\sys_rst_n~input_o ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\oe~output_o ), + .obar()); +// synopsys translate_off +defparam \oe~output .bus_hold = "false"; +defparam \oe~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \sys_clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sys_clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sys_clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \sys_clk~inputclkctrl .clock_type = "global clock"; +defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N6 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_4[0]~0 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_4[0]~0_combout = !\hc595_ctrl_inst|cnt_4 [0] + + .dataa(gnd), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(gnd), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_4[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_4[0]~0 .lut_mask = 16'h0F0F; +defparam \hc595_ctrl_inst|cnt_4[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X14_Y13_N7 +dffeas \hc595_ctrl_inst|cnt_4[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_4[0]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_4 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_4[0] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_4[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N14 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[0]~1 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[0]~1_combout = \hc595_ctrl_inst|cnt_bit [0] $ (((\hc595_ctrl_inst|cnt_4 [1] & \hc595_ctrl_inst|cnt_4 [0]))) + + .dataa(\hc595_ctrl_inst|cnt_4 [1]), + .datab(\hc595_ctrl_inst|cnt_4 [0]), + .datac(\hc595_ctrl_inst|cnt_bit [0]), + .datad(gnd), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[0]~1 .lut_mask = 16'h7878; +defparam \hc595_ctrl_inst|cnt_bit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N15 +dffeas \hc595_ctrl_inst|cnt_bit[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[0]~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[0] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N24 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[1]~0 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[1]~0_combout = (\hc595_ctrl_inst|Equal1~0_combout & (!\hc595_ctrl_inst|always2~1_combout & (\hc595_ctrl_inst|cnt_bit [0] $ (\hc595_ctrl_inst|cnt_bit [1])))) # (!\hc595_ctrl_inst|Equal1~0_combout & (((\hc595_ctrl_inst|cnt_bit +// [1])))) + + .dataa(\hc595_ctrl_inst|Equal1~0_combout ), + .datab(\hc595_ctrl_inst|cnt_bit [0]), + .datac(\hc595_ctrl_inst|cnt_bit [1]), + .datad(\hc595_ctrl_inst|always2~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[1]~0 .lut_mask = 16'h5078; +defparam \hc595_ctrl_inst|cnt_bit[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N25 +dffeas \hc595_ctrl_inst|cnt_bit[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[1]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[1] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N0 +cycloneive_lcell_comb \hc595_ctrl_inst|always2~0 ( +// Equation(s): +// \hc595_ctrl_inst|always2~0_combout = (\hc595_ctrl_inst|cnt_bit [0] & \hc595_ctrl_inst|cnt_bit [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_bit [0]), + .datad(\hc595_ctrl_inst|cnt_bit [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|always2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|always2~0 .lut_mask = 16'hF000; +defparam \hc595_ctrl_inst|always2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N8 +cycloneive_lcell_comb \seg_static_inst|Add0~0 ( +// Equation(s): +// \seg_static_inst|Add0~0_combout = (\hc595_ctrl_inst|cnt_4 [0] & (\hc595_ctrl_inst|cnt_4 [1] $ (VCC))) # (!\hc595_ctrl_inst|cnt_4 [0] & (\hc595_ctrl_inst|cnt_4 [1] & VCC)) +// \seg_static_inst|Add0~1 = CARRY((\hc595_ctrl_inst|cnt_4 [0] & \hc595_ctrl_inst|cnt_4 [1])) + + .dataa(\hc595_ctrl_inst|cnt_4 [0]), + .datab(\hc595_ctrl_inst|cnt_4 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\seg_static_inst|Add0~0_combout ), + .cout(\seg_static_inst|Add0~1 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~0 .lut_mask = 16'h6688; +defparam \seg_static_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N9 +dffeas \hc595_ctrl_inst|cnt_4[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_4 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_4[1] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_4[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N22 +cycloneive_lcell_comb \hc595_ctrl_inst|Equal1~0 ( +// Equation(s): +// \hc595_ctrl_inst|Equal1~0_combout = (\hc595_ctrl_inst|cnt_4 [0] & \hc595_ctrl_inst|cnt_4 [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(\hc595_ctrl_inst|cnt_4 [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Equal1~0 .lut_mask = 16'hF000; +defparam \hc595_ctrl_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N16 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[3]~2 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[3]~2_combout = (\hc595_ctrl_inst|always2~0_combout & ((\hc595_ctrl_inst|cnt_bit [3] & ((!\hc595_ctrl_inst|Equal1~0_combout ))) # (!\hc595_ctrl_inst|cnt_bit [3] & (\hc595_ctrl_inst|cnt_bit [2] & \hc595_ctrl_inst|Equal1~0_combout +// )))) # (!\hc595_ctrl_inst|always2~0_combout & (((\hc595_ctrl_inst|cnt_bit [3])))) + + .dataa(\hc595_ctrl_inst|cnt_bit [2]), + .datab(\hc595_ctrl_inst|always2~0_combout ), + .datac(\hc595_ctrl_inst|cnt_bit [3]), + .datad(\hc595_ctrl_inst|Equal1~0_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[3]~2 .lut_mask = 16'h38F0; +defparam \hc595_ctrl_inst|cnt_bit[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N17 +dffeas \hc595_ctrl_inst|cnt_bit[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[3]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[3] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N28 +cycloneive_lcell_comb \hc595_ctrl_inst|always2~1 ( +// Equation(s): +// \hc595_ctrl_inst|always2~1_combout = (!\hc595_ctrl_inst|cnt_bit [2] & (\hc595_ctrl_inst|cnt_bit [3] & (\hc595_ctrl_inst|Equal1~0_combout & \hc595_ctrl_inst|always2~0_combout ))) + + .dataa(\hc595_ctrl_inst|cnt_bit [2]), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|Equal1~0_combout ), + .datad(\hc595_ctrl_inst|always2~0_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|always2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|always2~1 .lut_mask = 16'h4000; +defparam \hc595_ctrl_inst|always2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N4 +cycloneive_lcell_comb \hc595_ctrl_inst|stcp~feeder ( +// Equation(s): +// \hc595_ctrl_inst|stcp~feeder_combout = \hc595_ctrl_inst|always2~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hc595_ctrl_inst|always2~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|stcp~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|stcp~feeder .lut_mask = 16'hFF00; +defparam \hc595_ctrl_inst|stcp~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N5 +dffeas \hc595_ctrl_inst|stcp ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|stcp~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|stcp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|stcp .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|stcp .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N19 +dffeas \hc595_ctrl_inst|shcp ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\hc595_ctrl_inst|cnt_4 [1]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|shcp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|shcp .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|shcp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N26 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[2]~3 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[2]~3_combout = (\hc595_ctrl_inst|Equal1~0_combout & ((\hc595_ctrl_inst|cnt_bit [2] & ((!\hc595_ctrl_inst|always2~0_combout ))) # (!\hc595_ctrl_inst|cnt_bit [2] & (!\hc595_ctrl_inst|cnt_bit [3] & +// \hc595_ctrl_inst|always2~0_combout )))) # (!\hc595_ctrl_inst|Equal1~0_combout & (((\hc595_ctrl_inst|cnt_bit [2])))) + + .dataa(\hc595_ctrl_inst|Equal1~0_combout ), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|cnt_bit [2]), + .datad(\hc595_ctrl_inst|always2~0_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[2]~3 .lut_mask = 16'h52F0; +defparam \hc595_ctrl_inst|cnt_bit[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N27 +dffeas \hc595_ctrl_inst|cnt_bit[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[2]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[2] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N10 +cycloneive_lcell_comb \seg_static_inst|Add0~2 ( +// Equation(s): +// \seg_static_inst|Add0~2_combout = (\seg_static_inst|cnt_wait [2] & (!\seg_static_inst|Add0~1 )) # (!\seg_static_inst|cnt_wait [2] & ((\seg_static_inst|Add0~1 ) # (GND))) +// \seg_static_inst|Add0~3 = CARRY((!\seg_static_inst|Add0~1 ) # (!\seg_static_inst|cnt_wait [2])) + + .dataa(\seg_static_inst|cnt_wait [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~1 ), + .combout(\seg_static_inst|Add0~2_combout ), + .cout(\seg_static_inst|Add0~3 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N11 +dffeas \seg_static_inst|cnt_wait[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [2]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[2] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N14 +cycloneive_lcell_comb \seg_static_inst|Add0~6 ( +// Equation(s): +// \seg_static_inst|Add0~6_combout = (\seg_static_inst|cnt_wait [4] & (!\seg_static_inst|Add0~5 )) # (!\seg_static_inst|cnt_wait [4] & ((\seg_static_inst|Add0~5 ) # (GND))) +// \seg_static_inst|Add0~7 = CARRY((!\seg_static_inst|Add0~5 ) # (!\seg_static_inst|cnt_wait [4])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [4]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~5 ), + .combout(\seg_static_inst|Add0~6_combout ), + .cout(\seg_static_inst|Add0~7 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N15 +dffeas \seg_static_inst|cnt_wait[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [4]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[4] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N16 +cycloneive_lcell_comb \seg_static_inst|Add0~8 ( +// Equation(s): +// \seg_static_inst|Add0~8_combout = (\seg_static_inst|cnt_wait [5] & (\seg_static_inst|Add0~7 $ (GND))) # (!\seg_static_inst|cnt_wait [5] & (!\seg_static_inst|Add0~7 & VCC)) +// \seg_static_inst|Add0~9 = CARRY((\seg_static_inst|cnt_wait [5] & !\seg_static_inst|Add0~7 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [5]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~7 ), + .combout(\seg_static_inst|Add0~8_combout ), + .cout(\seg_static_inst|Add0~9 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N17 +dffeas \seg_static_inst|cnt_wait[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [5]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[5] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N18 +cycloneive_lcell_comb \seg_static_inst|Add0~10 ( +// Equation(s): +// \seg_static_inst|Add0~10_combout = (\seg_static_inst|cnt_wait [6] & (!\seg_static_inst|Add0~9 )) # (!\seg_static_inst|cnt_wait [6] & ((\seg_static_inst|Add0~9 ) # (GND))) +// \seg_static_inst|Add0~11 = CARRY((!\seg_static_inst|Add0~9 ) # (!\seg_static_inst|cnt_wait [6])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [6]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~9 ), + .combout(\seg_static_inst|Add0~10_combout ), + .cout(\seg_static_inst|Add0~11 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~10 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N4 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~11 ( +// Equation(s): +// \seg_static_inst|cnt_wait~11_combout = (\seg_static_inst|Add0~10_combout & !\seg_static_inst|Equal0~7_combout ) + + .dataa(gnd), + .datab(\seg_static_inst|Add0~10_combout ), + .datac(gnd), + .datad(\seg_static_inst|Equal0~7_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~11_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~11 .lut_mask = 16'h00CC; +defparam \seg_static_inst|cnt_wait~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N5 +dffeas \seg_static_inst|cnt_wait[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~11_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [6]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[6] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N20 +cycloneive_lcell_comb \seg_static_inst|Add0~12 ( +// Equation(s): +// \seg_static_inst|Add0~12_combout = (\seg_static_inst|cnt_wait [7] & (\seg_static_inst|Add0~11 $ (GND))) # (!\seg_static_inst|cnt_wait [7] & (!\seg_static_inst|Add0~11 & VCC)) +// \seg_static_inst|Add0~13 = CARRY((\seg_static_inst|cnt_wait [7] & !\seg_static_inst|Add0~11 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [7]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~11 ), + .combout(\seg_static_inst|Add0~12_combout ), + .cout(\seg_static_inst|Add0~13 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N21 +dffeas \seg_static_inst|cnt_wait[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [7]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[7] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N24 +cycloneive_lcell_comb \seg_static_inst|Add0~16 ( +// Equation(s): +// \seg_static_inst|Add0~16_combout = (\seg_static_inst|cnt_wait [9] & (\seg_static_inst|Add0~15 $ (GND))) # (!\seg_static_inst|cnt_wait [9] & (!\seg_static_inst|Add0~15 & VCC)) +// \seg_static_inst|Add0~17 = CARRY((\seg_static_inst|cnt_wait [9] & !\seg_static_inst|Add0~15 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [9]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~15 ), + .combout(\seg_static_inst|Add0~16_combout ), + .cout(\seg_static_inst|Add0~17 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N25 +dffeas \seg_static_inst|cnt_wait[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~16_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [9]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[9] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N27 +dffeas \seg_static_inst|cnt_wait[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~18_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [10]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[10] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N0 +cycloneive_lcell_comb \seg_static_inst|Equal0~5 ( +// Equation(s): +// \seg_static_inst|Equal0~5_combout = (!\seg_static_inst|cnt_wait [8] & (!\seg_static_inst|cnt_wait [7] & (!\seg_static_inst|cnt_wait [10] & !\seg_static_inst|cnt_wait [9]))) + + .dataa(\seg_static_inst|cnt_wait [8]), + .datab(\seg_static_inst|cnt_wait [7]), + .datac(\seg_static_inst|cnt_wait [10]), + .datad(\seg_static_inst|cnt_wait [9]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~5_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~5 .lut_mask = 16'h0001; +defparam \seg_static_inst|Equal0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N2 +cycloneive_lcell_comb \seg_static_inst|Equal0~6 ( +// Equation(s): +// \seg_static_inst|Equal0~6_combout = (\seg_static_inst|cnt_wait [3] & (\seg_static_inst|cnt_wait [4] & (!\seg_static_inst|cnt_wait [6] & \seg_static_inst|cnt_wait [5]))) + + .dataa(\seg_static_inst|cnt_wait [3]), + .datab(\seg_static_inst|cnt_wait [4]), + .datac(\seg_static_inst|cnt_wait [6]), + .datad(\seg_static_inst|cnt_wait [5]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~6 .lut_mask = 16'h0800; +defparam \seg_static_inst|Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N14 +cycloneive_lcell_comb \seg_static_inst|Equal0~7 ( +// Equation(s): +// \seg_static_inst|Equal0~7_combout = (\seg_static_inst|Equal0~4_combout & (\seg_static_inst|cnt_wait [2] & (\seg_static_inst|Equal0~5_combout & \seg_static_inst|Equal0~6_combout ))) + + .dataa(\seg_static_inst|Equal0~4_combout ), + .datab(\seg_static_inst|cnt_wait [2]), + .datac(\seg_static_inst|Equal0~5_combout ), + .datad(\seg_static_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\seg_static_inst|Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~7 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N4 +cycloneive_lcell_comb \seg_static_inst|add_flag~feeder ( +// Equation(s): +// \seg_static_inst|add_flag~feeder_combout = \seg_static_inst|Equal0~7_combout + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|add_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|add_flag~feeder .lut_mask = 16'hF0F0; +defparam \seg_static_inst|add_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N5 +dffeas \seg_static_inst|add_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|add_flag~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|add_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|add_flag .is_wysiwyg = "true"; +defparam \seg_static_inst|add_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N10 +cycloneive_lcell_comb \seg_static_inst|num[0]~0 ( +// Equation(s): +// \seg_static_inst|num[0]~0_combout = \seg_static_inst|add_flag~q $ (\seg_static_inst|num [0]) + + .dataa(gnd), + .datab(\seg_static_inst|add_flag~q ), + .datac(\seg_static_inst|num [0]), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|num[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[0]~0 .lut_mask = 16'h3C3C; +defparam \seg_static_inst|num[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N11 +dffeas \seg_static_inst|num[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[0]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[0] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N0 +cycloneive_lcell_comb \seg_static_inst|num[1]~1 ( +// Equation(s): +// \seg_static_inst|num[1]~1_combout = \seg_static_inst|num [1] $ (((\seg_static_inst|add_flag~q & \seg_static_inst|num [0]))) + + .dataa(gnd), + .datab(\seg_static_inst|add_flag~q ), + .datac(\seg_static_inst|num [1]), + .datad(\seg_static_inst|num [0]), + .cin(gnd), + .combout(\seg_static_inst|num[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[1]~1 .lut_mask = 16'h3CF0; +defparam \seg_static_inst|num[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N1 +dffeas \seg_static_inst|num[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[1]~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[1] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N14 +cycloneive_lcell_comb \seg_static_inst|num[2]~2 ( +// Equation(s): +// \seg_static_inst|num[2]~2_combout = \seg_static_inst|num [2] $ (((\seg_static_inst|num [0] & (\seg_static_inst|add_flag~q & \seg_static_inst|num [1])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|add_flag~q ), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|num[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[2]~2 .lut_mask = 16'h78F0; +defparam \seg_static_inst|num[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N15 +dffeas \seg_static_inst|num[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[2]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[2] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N18 +cycloneive_lcell_comb \seg_static_inst|num[3]~3 ( +// Equation(s): +// \seg_static_inst|num[3]~3_combout = (\seg_static_inst|num [0] & (\seg_static_inst|num [2] & (\seg_static_inst|add_flag~q & \seg_static_inst|num [1]))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [2]), + .datac(\seg_static_inst|add_flag~q ), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|num[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[3]~3 .lut_mask = 16'h8000; +defparam \seg_static_inst|num[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N16 +cycloneive_lcell_comb \seg_static_inst|num[3]~4 ( +// Equation(s): +// \seg_static_inst|num[3]~4_combout = \seg_static_inst|num [3] $ (\seg_static_inst|num[3]~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|num [3]), + .datad(\seg_static_inst|num[3]~3_combout ), + .cin(gnd), + .combout(\seg_static_inst|num[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[3]~4 .lut_mask = 16'h0FF0; +defparam \seg_static_inst|num[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N17 +dffeas \seg_static_inst|num[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[3]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[3] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N8 +cycloneive_lcell_comb \seg_static_inst|WideOr1~0 ( +// Equation(s): +// \seg_static_inst|WideOr1~0_combout = (\seg_static_inst|num [0] & (\seg_static_inst|num [3] $ (((\seg_static_inst|num [1]) # (!\seg_static_inst|num [2]))))) # (!\seg_static_inst|num [0] & (!\seg_static_inst|num [3] & (!\seg_static_inst|num [2] & +// \seg_static_inst|num [1]))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr1~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr1~0 .lut_mask = 16'h2382; +defparam \seg_static_inst|WideOr1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N9 +dffeas \seg_static_inst|seg[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr1~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[5] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N6 +cycloneive_lcell_comb \seg_static_inst|seg[7]~feeder ( +// Equation(s): +// \seg_static_inst|seg[7]~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|seg[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|seg[7]~feeder .lut_mask = 16'hFFFF; +defparam \seg_static_inst|seg[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N7 +dffeas \seg_static_inst|seg[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|seg[7]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[7] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N22 +cycloneive_lcell_comb \seg_static_inst|WideOr0~0 ( +// Equation(s): +// \seg_static_inst|WideOr0~0_combout = (\seg_static_inst|num [0] & (!\seg_static_inst|num [3] & (\seg_static_inst|num [2] $ (!\seg_static_inst|num [1])))) # (!\seg_static_inst|num [0] & (!\seg_static_inst|num [1] & (\seg_static_inst|num [3] $ +// (!\seg_static_inst|num [2])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr0~0 .lut_mask = 16'h2043; +defparam \seg_static_inst|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N23 +dffeas \seg_static_inst|seg[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr0~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[6] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N12 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~2 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~2_combout = (\hc595_ctrl_inst|cnt_bit [0] & (((\hc595_ctrl_inst|cnt_bit [1]) # (!\seg_static_inst|seg [6])))) # (!\hc595_ctrl_inst|cnt_bit [0] & (!\seg_static_inst|seg [7] & ((!\hc595_ctrl_inst|cnt_bit [1])))) + + .dataa(\hc595_ctrl_inst|cnt_bit [0]), + .datab(\seg_static_inst|seg [7]), + .datac(\seg_static_inst|seg [6]), + .datad(\hc595_ctrl_inst|cnt_bit [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~2_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~2 .lut_mask = 16'hAA1B; +defparam \hc595_ctrl_inst|Mux0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N24 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~3 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~3_combout = (\hc595_ctrl_inst|cnt_bit [1] & ((\hc595_ctrl_inst|Mux0~2_combout & (!\seg_static_inst|seg [4])) # (!\hc595_ctrl_inst|Mux0~2_combout & ((!\seg_static_inst|seg [5]))))) # (!\hc595_ctrl_inst|cnt_bit [1] & +// (((\hc595_ctrl_inst|Mux0~2_combout )))) + + .dataa(\seg_static_inst|seg [4]), + .datab(\hc595_ctrl_inst|cnt_bit [1]), + .datac(\seg_static_inst|seg [5]), + .datad(\hc595_ctrl_inst|Mux0~2_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~3_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~3 .lut_mask = 16'h770C; +defparam \hc595_ctrl_inst|Mux0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N20 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~2 ( +// Equation(s): +// \hc595_ctrl_inst|ds~2_combout = (!\hc595_ctrl_inst|cnt_bit [3] & ((\hc595_ctrl_inst|cnt_bit [2] & ((\hc595_ctrl_inst|Mux0~3_combout ))) # (!\hc595_ctrl_inst|cnt_bit [2] & (!\seg_static_inst|seg [7])))) + + .dataa(\seg_static_inst|seg [7]), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|cnt_bit [2]), + .datad(\hc595_ctrl_inst|Mux0~3_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~2_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~2 .lut_mask = 16'h3101; +defparam \hc595_ctrl_inst|ds~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N20 +cycloneive_lcell_comb \seg_static_inst|WideOr4~0 ( +// Equation(s): +// \seg_static_inst|WideOr4~0_combout = (\seg_static_inst|num [3] & (\seg_static_inst|num [2] & ((\seg_static_inst|num [1]) # (!\seg_static_inst|num [0])))) # (!\seg_static_inst|num [3] & (!\seg_static_inst|num [0] & (!\seg_static_inst|num [2] & +// \seg_static_inst|num [1]))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr4~0 .lut_mask = 16'hC140; +defparam \seg_static_inst|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N21 +dffeas \seg_static_inst|seg[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr4~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[2] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N4 +cycloneive_lcell_comb \seg_static_inst|WideOr3~0 ( +// Equation(s): +// \seg_static_inst|WideOr3~0_combout = (\seg_static_inst|num [1] & ((\seg_static_inst|num [0] & ((\seg_static_inst|num [2]))) # (!\seg_static_inst|num [0] & (\seg_static_inst|num [3] & !\seg_static_inst|num [2])))) # (!\seg_static_inst|num [1] & +// (!\seg_static_inst|num [3] & (\seg_static_inst|num [0] $ (\seg_static_inst|num [2])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr3~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr3~0 .lut_mask = 16'hA412; +defparam \seg_static_inst|WideOr3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N5 +dffeas \seg_static_inst|seg[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr3~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[3] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N2 +cycloneive_lcell_comb \seg_static_inst|WideOr5~0 ( +// Equation(s): +// \seg_static_inst|WideOr5~0_combout = (\seg_static_inst|num [3] & ((\seg_static_inst|num [0] & ((\seg_static_inst|num [1]))) # (!\seg_static_inst|num [0] & (\seg_static_inst|num [2])))) # (!\seg_static_inst|num [3] & (\seg_static_inst|num [2] & +// (\seg_static_inst|num [0] $ (\seg_static_inst|num [1])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr5~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr5~0 .lut_mask = 16'hD860; +defparam \seg_static_inst|WideOr5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N3 +dffeas \seg_static_inst|seg[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr5~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[1] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N30 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~0 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~0_combout = (\hc595_ctrl_inst|cnt_bit [0] & (\hc595_ctrl_inst|cnt_bit [1])) # (!\hc595_ctrl_inst|cnt_bit [0] & ((\hc595_ctrl_inst|cnt_bit [1] & ((!\seg_static_inst|seg [1]))) # (!\hc595_ctrl_inst|cnt_bit [1] & (!\seg_static_inst|seg +// [3])))) + + .dataa(\hc595_ctrl_inst|cnt_bit [0]), + .datab(\hc595_ctrl_inst|cnt_bit [1]), + .datac(\seg_static_inst|seg [3]), + .datad(\seg_static_inst|seg [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~0 .lut_mask = 16'h89CD; +defparam \hc595_ctrl_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N28 +cycloneive_lcell_comb \seg_static_inst|WideOr6~0 ( +// Equation(s): +// \seg_static_inst|WideOr6~0_combout = (\seg_static_inst|num [3] & (\seg_static_inst|num [0] & (\seg_static_inst|num [2] $ (\seg_static_inst|num [1])))) # (!\seg_static_inst|num [3] & (!\seg_static_inst|num [1] & (\seg_static_inst|num [0] $ +// (\seg_static_inst|num [2])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr6~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr6~0 .lut_mask = 16'h0892; +defparam \seg_static_inst|WideOr6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N29 +dffeas \seg_static_inst|seg[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr6~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[0] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N6 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~1 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~1_combout = (\hc595_ctrl_inst|cnt_bit [0] & ((\hc595_ctrl_inst|Mux0~0_combout & ((!\seg_static_inst|seg [0]))) # (!\hc595_ctrl_inst|Mux0~0_combout & (!\seg_static_inst|seg [2])))) # (!\hc595_ctrl_inst|cnt_bit [0] & +// (((\hc595_ctrl_inst|Mux0~0_combout )))) + + .dataa(\hc595_ctrl_inst|cnt_bit [0]), + .datab(\seg_static_inst|seg [2]), + .datac(\hc595_ctrl_inst|Mux0~0_combout ), + .datad(\seg_static_inst|seg [0]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~1 .lut_mask = 16'h52F2; +defparam \hc595_ctrl_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N12 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~1 ( +// Equation(s): +// \hc595_ctrl_inst|ds~1_combout = (\hc595_ctrl_inst|cnt_bit [3] & (!\hc595_ctrl_inst|cnt_bit [2] & \hc595_ctrl_inst|Mux0~1_combout )) + + .dataa(gnd), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|cnt_bit [2]), + .datad(\hc595_ctrl_inst|Mux0~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~1 .lut_mask = 16'h0C00; +defparam \hc595_ctrl_inst|ds~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N30 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~3 ( +// Equation(s): +// \hc595_ctrl_inst|ds~3_combout = (\hc595_ctrl_inst|ds~0_combout & ((\hc595_ctrl_inst|ds~2_combout ) # ((\hc595_ctrl_inst|ds~1_combout )))) # (!\hc595_ctrl_inst|ds~0_combout & (((\hc595_ctrl_inst|ds~q )))) + + .dataa(\hc595_ctrl_inst|ds~0_combout ), + .datab(\hc595_ctrl_inst|ds~2_combout ), + .datac(\hc595_ctrl_inst|ds~q ), + .datad(\hc595_ctrl_inst|ds~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~3_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~3 .lut_mask = 16'hFAD8; +defparam \hc595_ctrl_inst|ds~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N31 +dffeas \hc595_ctrl_inst|ds ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|ds~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|ds~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|ds .power_up = "low"; +// synopsys translate_on + +assign stcp = \stcp~output_o ; + +assign shcp = \shcp~output_o ; + +assign ds = \ds~output_o ; + +assign oe = \oe~output_o ; + +endmodule diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_8_1200mv_0c_slow.vo b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_8_1200mv_0c_slow.vo new file mode 100644 index 0000000..dcc58a1 --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_8_1200mv_0c_slow.vo @@ -0,0 +1,2444 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 20:55:14" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module seg_595_static ( + sys_clk, + sys_rst_n, + stcp, + shcp, + ds, + oe); +input sys_clk; +input sys_rst_n; +output stcp; +output shcp; +output ds; +output oe; + +// Design Ports Information +// stcp => Location: PIN_Y1, I/O Standard: 2.5 V, Current Strength: Default +// shcp => Location: PIN_W1, I/O Standard: 2.5 V, Current Strength: Default +// ds => Location: PIN_AA1, I/O Standard: 2.5 V, Current Strength: Default +// oe => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("seg_595_static_8_1200mv_0c_v_slow.sdo"); +// synopsys translate_on + +wire \seg_static_inst|Add0~4_combout ; +wire \seg_static_inst|Add0~14_combout ; +wire \seg_static_inst|Add0~19 ; +wire \seg_static_inst|Add0~20_combout ; +wire \seg_static_inst|Add0~21 ; +wire \seg_static_inst|Add0~22_combout ; +wire \seg_static_inst|Add0~23 ; +wire \seg_static_inst|Add0~24_combout ; +wire \seg_static_inst|Add0~25 ; +wire \seg_static_inst|Add0~26_combout ; +wire \seg_static_inst|Add0~27 ; +wire \seg_static_inst|Add0~28_combout ; +wire \seg_static_inst|Add0~29 ; +wire \seg_static_inst|Add0~30_combout ; +wire \seg_static_inst|Add0~31 ; +wire \seg_static_inst|Add0~32_combout ; +wire \seg_static_inst|Add0~33 ; +wire \seg_static_inst|Add0~34_combout ; +wire \seg_static_inst|Add0~35 ; +wire \seg_static_inst|Add0~36_combout ; +wire \seg_static_inst|Add0~37 ; +wire \seg_static_inst|Add0~38_combout ; +wire \seg_static_inst|Add0~39 ; +wire \seg_static_inst|Add0~40_combout ; +wire \seg_static_inst|Add0~41 ; +wire \seg_static_inst|Add0~42_combout ; +wire \seg_static_inst|Add0~43 ; +wire \seg_static_inst|Add0~44_combout ; +wire \seg_static_inst|Add0~45 ; +wire \seg_static_inst|Add0~46_combout ; +wire \hc595_ctrl_inst|ds~0_combout ; +wire \seg_static_inst|WideOr2~0_combout ; +wire \seg_static_inst|Equal0~0_combout ; +wire \seg_static_inst|Equal0~1_combout ; +wire \seg_static_inst|Equal0~2_combout ; +wire \seg_static_inst|Equal0~3_combout ; +wire \seg_static_inst|Equal0~4_combout ; +wire \seg_static_inst|cnt_wait~0_combout ; +wire \seg_static_inst|cnt_wait~1_combout ; +wire \seg_static_inst|cnt_wait~2_combout ; +wire \seg_static_inst|cnt_wait~3_combout ; +wire \seg_static_inst|cnt_wait~4_combout ; +wire \seg_static_inst|cnt_wait~5_combout ; +wire \seg_static_inst|cnt_wait~6_combout ; +wire \seg_static_inst|cnt_wait~7_combout ; +wire \seg_static_inst|cnt_wait~8_combout ; +wire \seg_static_inst|cnt_wait~9_combout ; +wire \seg_static_inst|cnt_wait~10_combout ; +wire \stcp~output_o ; +wire \shcp~output_o ; +wire \ds~output_o ; +wire \oe~output_o ; +wire \sys_clk~input_o ; +wire \sys_clk~inputclkctrl_outclk ; +wire \hc595_ctrl_inst|cnt_4[0]~0_combout ; +wire \sys_rst_n~input_o ; +wire \hc595_ctrl_inst|cnt_bit[0]~1_combout ; +wire \hc595_ctrl_inst|cnt_bit[1]~0_combout ; +wire \hc595_ctrl_inst|always2~0_combout ; +wire \seg_static_inst|Add0~0_combout ; +wire \hc595_ctrl_inst|Equal1~0_combout ; +wire \hc595_ctrl_inst|cnt_bit[3]~2_combout ; +wire \hc595_ctrl_inst|always2~1_combout ; +wire \hc595_ctrl_inst|stcp~feeder_combout ; +wire \hc595_ctrl_inst|stcp~q ; +wire \hc595_ctrl_inst|shcp~q ; +wire \hc595_ctrl_inst|cnt_bit[2]~3_combout ; +wire \seg_static_inst|Add0~1 ; +wire \seg_static_inst|Add0~2_combout ; +wire \seg_static_inst|Add0~3 ; +wire \seg_static_inst|Add0~5 ; +wire \seg_static_inst|Add0~6_combout ; +wire \seg_static_inst|Add0~7 ; +wire \seg_static_inst|Add0~8_combout ; +wire \seg_static_inst|Add0~9 ; +wire \seg_static_inst|Add0~10_combout ; +wire \seg_static_inst|cnt_wait~11_combout ; +wire \seg_static_inst|Add0~11 ; +wire \seg_static_inst|Add0~12_combout ; +wire \seg_static_inst|Add0~13 ; +wire \seg_static_inst|Add0~15 ; +wire \seg_static_inst|Add0~16_combout ; +wire \seg_static_inst|Add0~17 ; +wire \seg_static_inst|Add0~18_combout ; +wire \seg_static_inst|Equal0~5_combout ; +wire \seg_static_inst|Equal0~6_combout ; +wire \seg_static_inst|Equal0~7_combout ; +wire \seg_static_inst|add_flag~feeder_combout ; +wire \seg_static_inst|add_flag~q ; +wire \seg_static_inst|num[0]~0_combout ; +wire \seg_static_inst|num[1]~1_combout ; +wire \seg_static_inst|num[2]~2_combout ; +wire \seg_static_inst|num[3]~3_combout ; +wire \seg_static_inst|num[3]~4_combout ; +wire \seg_static_inst|WideOr1~0_combout ; +wire \seg_static_inst|seg[7]~feeder_combout ; +wire \seg_static_inst|WideOr0~0_combout ; +wire \hc595_ctrl_inst|Mux0~2_combout ; +wire \hc595_ctrl_inst|Mux0~3_combout ; +wire \hc595_ctrl_inst|ds~2_combout ; +wire \seg_static_inst|WideOr4~0_combout ; +wire \seg_static_inst|WideOr3~0_combout ; +wire \seg_static_inst|WideOr5~0_combout ; +wire \hc595_ctrl_inst|Mux0~0_combout ; +wire \seg_static_inst|WideOr6~0_combout ; +wire \hc595_ctrl_inst|Mux0~1_combout ; +wire \hc595_ctrl_inst|ds~1_combout ; +wire \hc595_ctrl_inst|ds~3_combout ; +wire \hc595_ctrl_inst|ds~q ; +wire [7:0] \seg_static_inst|seg ; +wire [3:0] \seg_static_inst|num ; +wire [24:0] \seg_static_inst|cnt_wait ; +wire [3:0] \hc595_ctrl_inst|cnt_bit ; +wire [1:0] \hc595_ctrl_inst|cnt_4 ; + + +// Location: LCCOMB_X14_Y13_N12 +cycloneive_lcell_comb \seg_static_inst|Add0~4 ( +// Equation(s): +// \seg_static_inst|Add0~4_combout = (\seg_static_inst|cnt_wait [3] & (\seg_static_inst|Add0~3 $ (GND))) # (!\seg_static_inst|cnt_wait [3] & (!\seg_static_inst|Add0~3 & VCC)) +// \seg_static_inst|Add0~5 = CARRY((\seg_static_inst|cnt_wait [3] & !\seg_static_inst|Add0~3 )) + + .dataa(\seg_static_inst|cnt_wait [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~3 ), + .combout(\seg_static_inst|Add0~4_combout ), + .cout(\seg_static_inst|Add0~5 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \seg_static_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N22 +cycloneive_lcell_comb \seg_static_inst|Add0~14 ( +// Equation(s): +// \seg_static_inst|Add0~14_combout = (\seg_static_inst|cnt_wait [8] & (!\seg_static_inst|Add0~13 )) # (!\seg_static_inst|cnt_wait [8] & ((\seg_static_inst|Add0~13 ) # (GND))) +// \seg_static_inst|Add0~15 = CARRY((!\seg_static_inst|Add0~13 ) # (!\seg_static_inst|cnt_wait [8])) + + .dataa(\seg_static_inst|cnt_wait [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~13 ), + .combout(\seg_static_inst|Add0~14_combout ), + .cout(\seg_static_inst|Add0~15 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N26 +cycloneive_lcell_comb \seg_static_inst|Add0~18 ( +// Equation(s): +// \seg_static_inst|Add0~18_combout = (\seg_static_inst|cnt_wait [10] & (!\seg_static_inst|Add0~17 )) # (!\seg_static_inst|cnt_wait [10] & ((\seg_static_inst|Add0~17 ) # (GND))) +// \seg_static_inst|Add0~19 = CARRY((!\seg_static_inst|Add0~17 ) # (!\seg_static_inst|cnt_wait [10])) + + .dataa(\seg_static_inst|cnt_wait [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~17 ), + .combout(\seg_static_inst|Add0~18_combout ), + .cout(\seg_static_inst|Add0~19 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~18 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N28 +cycloneive_lcell_comb \seg_static_inst|Add0~20 ( +// Equation(s): +// \seg_static_inst|Add0~20_combout = (\seg_static_inst|cnt_wait [11] & (\seg_static_inst|Add0~19 $ (GND))) # (!\seg_static_inst|cnt_wait [11] & (!\seg_static_inst|Add0~19 & VCC)) +// \seg_static_inst|Add0~21 = CARRY((\seg_static_inst|cnt_wait [11] & !\seg_static_inst|Add0~19 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [11]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~19 ), + .combout(\seg_static_inst|Add0~20_combout ), + .cout(\seg_static_inst|Add0~21 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~20 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N30 +cycloneive_lcell_comb \seg_static_inst|Add0~22 ( +// Equation(s): +// \seg_static_inst|Add0~22_combout = (\seg_static_inst|cnt_wait [12] & (!\seg_static_inst|Add0~21 )) # (!\seg_static_inst|cnt_wait [12] & ((\seg_static_inst|Add0~21 ) # (GND))) +// \seg_static_inst|Add0~23 = CARRY((!\seg_static_inst|Add0~21 ) # (!\seg_static_inst|cnt_wait [12])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [12]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~21 ), + .combout(\seg_static_inst|Add0~22_combout ), + .cout(\seg_static_inst|Add0~23 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~22 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N0 +cycloneive_lcell_comb \seg_static_inst|Add0~24 ( +// Equation(s): +// \seg_static_inst|Add0~24_combout = (\seg_static_inst|cnt_wait [13] & (\seg_static_inst|Add0~23 $ (GND))) # (!\seg_static_inst|cnt_wait [13] & (!\seg_static_inst|Add0~23 & VCC)) +// \seg_static_inst|Add0~25 = CARRY((\seg_static_inst|cnt_wait [13] & !\seg_static_inst|Add0~23 )) + + .dataa(\seg_static_inst|cnt_wait [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~23 ), + .combout(\seg_static_inst|Add0~24_combout ), + .cout(\seg_static_inst|Add0~25 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~24 .lut_mask = 16'hA50A; +defparam \seg_static_inst|Add0~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N2 +cycloneive_lcell_comb \seg_static_inst|Add0~26 ( +// Equation(s): +// \seg_static_inst|Add0~26_combout = (\seg_static_inst|cnt_wait [14] & (!\seg_static_inst|Add0~25 )) # (!\seg_static_inst|cnt_wait [14] & ((\seg_static_inst|Add0~25 ) # (GND))) +// \seg_static_inst|Add0~27 = CARRY((!\seg_static_inst|Add0~25 ) # (!\seg_static_inst|cnt_wait [14])) + + .dataa(\seg_static_inst|cnt_wait [14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~25 ), + .combout(\seg_static_inst|Add0~26_combout ), + .cout(\seg_static_inst|Add0~27 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~26 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N4 +cycloneive_lcell_comb \seg_static_inst|Add0~28 ( +// Equation(s): +// \seg_static_inst|Add0~28_combout = (\seg_static_inst|cnt_wait [15] & (\seg_static_inst|Add0~27 $ (GND))) # (!\seg_static_inst|cnt_wait [15] & (!\seg_static_inst|Add0~27 & VCC)) +// \seg_static_inst|Add0~29 = CARRY((\seg_static_inst|cnt_wait [15] & !\seg_static_inst|Add0~27 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [15]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~27 ), + .combout(\seg_static_inst|Add0~28_combout ), + .cout(\seg_static_inst|Add0~29 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~28 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N6 +cycloneive_lcell_comb \seg_static_inst|Add0~30 ( +// Equation(s): +// \seg_static_inst|Add0~30_combout = (\seg_static_inst|cnt_wait [16] & (!\seg_static_inst|Add0~29 )) # (!\seg_static_inst|cnt_wait [16] & ((\seg_static_inst|Add0~29 ) # (GND))) +// \seg_static_inst|Add0~31 = CARRY((!\seg_static_inst|Add0~29 ) # (!\seg_static_inst|cnt_wait [16])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [16]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~29 ), + .combout(\seg_static_inst|Add0~30_combout ), + .cout(\seg_static_inst|Add0~31 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~30 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N8 +cycloneive_lcell_comb \seg_static_inst|Add0~32 ( +// Equation(s): +// \seg_static_inst|Add0~32_combout = (\seg_static_inst|cnt_wait [17] & (\seg_static_inst|Add0~31 $ (GND))) # (!\seg_static_inst|cnt_wait [17] & (!\seg_static_inst|Add0~31 & VCC)) +// \seg_static_inst|Add0~33 = CARRY((\seg_static_inst|cnt_wait [17] & !\seg_static_inst|Add0~31 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [17]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~31 ), + .combout(\seg_static_inst|Add0~32_combout ), + .cout(\seg_static_inst|Add0~33 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~32 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N10 +cycloneive_lcell_comb \seg_static_inst|Add0~34 ( +// Equation(s): +// \seg_static_inst|Add0~34_combout = (\seg_static_inst|cnt_wait [18] & (!\seg_static_inst|Add0~33 )) # (!\seg_static_inst|cnt_wait [18] & ((\seg_static_inst|Add0~33 ) # (GND))) +// \seg_static_inst|Add0~35 = CARRY((!\seg_static_inst|Add0~33 ) # (!\seg_static_inst|cnt_wait [18])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [18]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~33 ), + .combout(\seg_static_inst|Add0~34_combout ), + .cout(\seg_static_inst|Add0~35 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~34 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N12 +cycloneive_lcell_comb \seg_static_inst|Add0~36 ( +// Equation(s): +// \seg_static_inst|Add0~36_combout = (\seg_static_inst|cnt_wait [19] & (\seg_static_inst|Add0~35 $ (GND))) # (!\seg_static_inst|cnt_wait [19] & (!\seg_static_inst|Add0~35 & VCC)) +// \seg_static_inst|Add0~37 = CARRY((\seg_static_inst|cnt_wait [19] & !\seg_static_inst|Add0~35 )) + + .dataa(\seg_static_inst|cnt_wait [19]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~35 ), + .combout(\seg_static_inst|Add0~36_combout ), + .cout(\seg_static_inst|Add0~37 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~36 .lut_mask = 16'hA50A; +defparam \seg_static_inst|Add0~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N14 +cycloneive_lcell_comb \seg_static_inst|Add0~38 ( +// Equation(s): +// \seg_static_inst|Add0~38_combout = (\seg_static_inst|cnt_wait [20] & (!\seg_static_inst|Add0~37 )) # (!\seg_static_inst|cnt_wait [20] & ((\seg_static_inst|Add0~37 ) # (GND))) +// \seg_static_inst|Add0~39 = CARRY((!\seg_static_inst|Add0~37 ) # (!\seg_static_inst|cnt_wait [20])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [20]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~37 ), + .combout(\seg_static_inst|Add0~38_combout ), + .cout(\seg_static_inst|Add0~39 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~38 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N16 +cycloneive_lcell_comb \seg_static_inst|Add0~40 ( +// Equation(s): +// \seg_static_inst|Add0~40_combout = (\seg_static_inst|cnt_wait [21] & (\seg_static_inst|Add0~39 $ (GND))) # (!\seg_static_inst|cnt_wait [21] & (!\seg_static_inst|Add0~39 & VCC)) +// \seg_static_inst|Add0~41 = CARRY((\seg_static_inst|cnt_wait [21] & !\seg_static_inst|Add0~39 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [21]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~39 ), + .combout(\seg_static_inst|Add0~40_combout ), + .cout(\seg_static_inst|Add0~41 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~40 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N18 +cycloneive_lcell_comb \seg_static_inst|Add0~42 ( +// Equation(s): +// \seg_static_inst|Add0~42_combout = (\seg_static_inst|cnt_wait [22] & (!\seg_static_inst|Add0~41 )) # (!\seg_static_inst|cnt_wait [22] & ((\seg_static_inst|Add0~41 ) # (GND))) +// \seg_static_inst|Add0~43 = CARRY((!\seg_static_inst|Add0~41 ) # (!\seg_static_inst|cnt_wait [22])) + + .dataa(\seg_static_inst|cnt_wait [22]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~41 ), + .combout(\seg_static_inst|Add0~42_combout ), + .cout(\seg_static_inst|Add0~43 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~42 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N20 +cycloneive_lcell_comb \seg_static_inst|Add0~44 ( +// Equation(s): +// \seg_static_inst|Add0~44_combout = (\seg_static_inst|cnt_wait [23] & (\seg_static_inst|Add0~43 $ (GND))) # (!\seg_static_inst|cnt_wait [23] & (!\seg_static_inst|Add0~43 & VCC)) +// \seg_static_inst|Add0~45 = CARRY((\seg_static_inst|cnt_wait [23] & !\seg_static_inst|Add0~43 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [23]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~43 ), + .combout(\seg_static_inst|Add0~44_combout ), + .cout(\seg_static_inst|Add0~45 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~44 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N22 +cycloneive_lcell_comb \seg_static_inst|Add0~46 ( +// Equation(s): +// \seg_static_inst|Add0~46_combout = \seg_static_inst|Add0~45 $ (\seg_static_inst|cnt_wait [24]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\seg_static_inst|cnt_wait [24]), + .cin(\seg_static_inst|Add0~45 ), + .combout(\seg_static_inst|Add0~46_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Add0~46 .lut_mask = 16'h0FF0; +defparam \seg_static_inst|Add0~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N10 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~0 ( +// Equation(s): +// \hc595_ctrl_inst|ds~0_combout = (!\hc595_ctrl_inst|cnt_4 [1] & !\hc595_ctrl_inst|cnt_4 [0]) + + .dataa(\hc595_ctrl_inst|cnt_4 [1]), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(gnd), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~0 .lut_mask = 16'h0505; +defparam \hc595_ctrl_inst|ds~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N27 +dffeas \seg_static_inst|seg[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr2~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[4] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N26 +cycloneive_lcell_comb \seg_static_inst|WideOr2~0 ( +// Equation(s): +// \seg_static_inst|WideOr2~0_combout = (\seg_static_inst|num [1] & (\seg_static_inst|num [0] & (!\seg_static_inst|num [3]))) # (!\seg_static_inst|num [1] & ((\seg_static_inst|num [2] & ((!\seg_static_inst|num [3]))) # (!\seg_static_inst|num [2] & +// (\seg_static_inst|num [0])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr2~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr2~0 .lut_mask = 16'h223A; +defparam \seg_static_inst|WideOr2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N3 +dffeas \seg_static_inst|cnt_wait[24] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [24]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[24] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[24] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N21 +dffeas \seg_static_inst|cnt_wait[23] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~44_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [23]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[23] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N24 +cycloneive_lcell_comb \seg_static_inst|Equal0~0 ( +// Equation(s): +// \seg_static_inst|Equal0~0_combout = (\hc595_ctrl_inst|cnt_4 [1] & (!\seg_static_inst|cnt_wait [23] & (\hc595_ctrl_inst|cnt_4 [0] & \seg_static_inst|cnt_wait [24]))) + + .dataa(\hc595_ctrl_inst|cnt_4 [1]), + .datab(\seg_static_inst|cnt_wait [23]), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(\seg_static_inst|cnt_wait [24]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~0 .lut_mask = 16'h2000; +defparam \seg_static_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N7 +dffeas \seg_static_inst|cnt_wait[22] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [22]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[22] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[22] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N25 +dffeas \seg_static_inst|cnt_wait[21] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [21]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[21] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[21] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N9 +dffeas \seg_static_inst|cnt_wait[20] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [20]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[20] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[20] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N27 +dffeas \seg_static_inst|cnt_wait[19] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [19]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[19] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N10 +cycloneive_lcell_comb \seg_static_inst|Equal0~1 ( +// Equation(s): +// \seg_static_inst|Equal0~1_combout = (\seg_static_inst|cnt_wait [22] & (\seg_static_inst|cnt_wait [20] & (\seg_static_inst|cnt_wait [19] & \seg_static_inst|cnt_wait [21]))) + + .dataa(\seg_static_inst|cnt_wait [22]), + .datab(\seg_static_inst|cnt_wait [20]), + .datac(\seg_static_inst|cnt_wait [19]), + .datad(\seg_static_inst|cnt_wait [21]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N29 +dffeas \seg_static_inst|cnt_wait[18] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [18]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[18] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[18] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N29 +dffeas \seg_static_inst|cnt_wait[16] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~6_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [16]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[16] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[16] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N9 +dffeas \seg_static_inst|cnt_wait[17] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~32_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [17]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[17] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[17] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N5 +dffeas \seg_static_inst|cnt_wait[15] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~28_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [15]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[15] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N18 +cycloneive_lcell_comb \seg_static_inst|Equal0~2 ( +// Equation(s): +// \seg_static_inst|Equal0~2_combout = (!\seg_static_inst|cnt_wait [17] & (\seg_static_inst|cnt_wait [16] & (!\seg_static_inst|cnt_wait [15] & \seg_static_inst|cnt_wait [18]))) + + .dataa(\seg_static_inst|cnt_wait [17]), + .datab(\seg_static_inst|cnt_wait [16]), + .datac(\seg_static_inst|cnt_wait [15]), + .datad(\seg_static_inst|cnt_wait [18]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~2 .lut_mask = 16'h0400; +defparam \seg_static_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N21 +dffeas \seg_static_inst|cnt_wait[14] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~7_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [14]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[14] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N31 +dffeas \seg_static_inst|cnt_wait[13] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~8_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [13]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[13] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N23 +dffeas \seg_static_inst|cnt_wait[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~9_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [12]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[12] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[12] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N1 +dffeas \seg_static_inst|cnt_wait[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~10_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [11]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[11] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N26 +cycloneive_lcell_comb \seg_static_inst|Equal0~3 ( +// Equation(s): +// \seg_static_inst|Equal0~3_combout = (\seg_static_inst|cnt_wait [11] & (\seg_static_inst|cnt_wait [14] & (\seg_static_inst|cnt_wait [12] & \seg_static_inst|cnt_wait [13]))) + + .dataa(\seg_static_inst|cnt_wait [11]), + .datab(\seg_static_inst|cnt_wait [14]), + .datac(\seg_static_inst|cnt_wait [12]), + .datad(\seg_static_inst|cnt_wait [13]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~3 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N12 +cycloneive_lcell_comb \seg_static_inst|Equal0~4 ( +// Equation(s): +// \seg_static_inst|Equal0~4_combout = (\seg_static_inst|Equal0~1_combout & (\seg_static_inst|Equal0~2_combout & (\seg_static_inst|Equal0~3_combout & \seg_static_inst|Equal0~0_combout ))) + + .dataa(\seg_static_inst|Equal0~1_combout ), + .datab(\seg_static_inst|Equal0~2_combout ), + .datac(\seg_static_inst|Equal0~3_combout ), + .datad(\seg_static_inst|Equal0~0_combout ), + .cin(gnd), + .combout(\seg_static_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~4 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N23 +dffeas \seg_static_inst|cnt_wait[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [8]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[8] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N13 +dffeas \seg_static_inst|cnt_wait[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [3]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[3] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N2 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~0 ( +// Equation(s): +// \seg_static_inst|cnt_wait~0_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~46_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~46_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~0 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N6 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~1 ( +// Equation(s): +// \seg_static_inst|cnt_wait~1_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~42_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~42_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~1_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~1 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N24 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~2 ( +// Equation(s): +// \seg_static_inst|cnt_wait~2_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~40_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~40_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~2_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~2 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N8 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~3 ( +// Equation(s): +// \seg_static_inst|cnt_wait~3_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~38_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~3_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~3 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N26 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~4 ( +// Equation(s): +// \seg_static_inst|cnt_wait~4_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~36_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~36_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~4_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~4 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N28 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~5 ( +// Equation(s): +// \seg_static_inst|cnt_wait~5_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~34_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~34_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~5_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~5 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N28 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~6 ( +// Equation(s): +// \seg_static_inst|cnt_wait~6_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~30_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~30_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~6_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~6 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N20 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~7 ( +// Equation(s): +// \seg_static_inst|cnt_wait~7_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~26_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~26_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~7_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~7 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N30 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~8 ( +// Equation(s): +// \seg_static_inst|cnt_wait~8_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~24_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~24_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~8_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~8 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N22 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~9 ( +// Equation(s): +// \seg_static_inst|cnt_wait~9_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~22_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~22_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~9_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~9 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N0 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~10 ( +// Equation(s): +// \seg_static_inst|cnt_wait~10_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~20_combout ) + + .dataa(gnd), + .datab(\seg_static_inst|Equal0~7_combout ), + .datac(\seg_static_inst|Add0~20_combout ), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~10_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~10 .lut_mask = 16'h3030; +defparam \seg_static_inst|cnt_wait~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y6_N9 +cycloneive_io_obuf \stcp~output ( + .i(\hc595_ctrl_inst|stcp~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\stcp~output_o ), + .obar()); +// synopsys translate_off +defparam \stcp~output .bus_hold = "false"; +defparam \stcp~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y7_N23 +cycloneive_io_obuf \shcp~output ( + .i(\hc595_ctrl_inst|shcp~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\shcp~output_o ), + .obar()); +// synopsys translate_off +defparam \shcp~output .bus_hold = "false"; +defparam \shcp~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y5_N16 +cycloneive_io_obuf \ds~output ( + .i(\hc595_ctrl_inst|ds~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\ds~output_o ), + .obar()); +// synopsys translate_off +defparam \ds~output .bus_hold = "false"; +defparam \ds~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y6_N2 +cycloneive_io_obuf \oe~output ( + .i(!\sys_rst_n~input_o ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\oe~output_o ), + .obar()); +// synopsys translate_off +defparam \oe~output .bus_hold = "false"; +defparam \oe~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \sys_clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sys_clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sys_clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \sys_clk~inputclkctrl .clock_type = "global clock"; +defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N6 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_4[0]~0 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_4[0]~0_combout = !\hc595_ctrl_inst|cnt_4 [0] + + .dataa(gnd), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(gnd), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_4[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_4[0]~0 .lut_mask = 16'h0F0F; +defparam \hc595_ctrl_inst|cnt_4[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X14_Y13_N7 +dffeas \hc595_ctrl_inst|cnt_4[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_4[0]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_4 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_4[0] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_4[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N14 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[0]~1 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[0]~1_combout = \hc595_ctrl_inst|cnt_bit [0] $ (((\hc595_ctrl_inst|cnt_4 [1] & \hc595_ctrl_inst|cnt_4 [0]))) + + .dataa(\hc595_ctrl_inst|cnt_4 [1]), + .datab(\hc595_ctrl_inst|cnt_4 [0]), + .datac(\hc595_ctrl_inst|cnt_bit [0]), + .datad(gnd), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[0]~1 .lut_mask = 16'h7878; +defparam \hc595_ctrl_inst|cnt_bit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N15 +dffeas \hc595_ctrl_inst|cnt_bit[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[0]~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[0] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N24 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[1]~0 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[1]~0_combout = (\hc595_ctrl_inst|Equal1~0_combout & (!\hc595_ctrl_inst|always2~1_combout & (\hc595_ctrl_inst|cnt_bit [0] $ (\hc595_ctrl_inst|cnt_bit [1])))) # (!\hc595_ctrl_inst|Equal1~0_combout & (((\hc595_ctrl_inst|cnt_bit +// [1])))) + + .dataa(\hc595_ctrl_inst|Equal1~0_combout ), + .datab(\hc595_ctrl_inst|cnt_bit [0]), + .datac(\hc595_ctrl_inst|cnt_bit [1]), + .datad(\hc595_ctrl_inst|always2~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[1]~0 .lut_mask = 16'h5078; +defparam \hc595_ctrl_inst|cnt_bit[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N25 +dffeas \hc595_ctrl_inst|cnt_bit[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[1]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[1] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N0 +cycloneive_lcell_comb \hc595_ctrl_inst|always2~0 ( +// Equation(s): +// \hc595_ctrl_inst|always2~0_combout = (\hc595_ctrl_inst|cnt_bit [0] & \hc595_ctrl_inst|cnt_bit [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_bit [0]), + .datad(\hc595_ctrl_inst|cnt_bit [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|always2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|always2~0 .lut_mask = 16'hF000; +defparam \hc595_ctrl_inst|always2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N8 +cycloneive_lcell_comb \seg_static_inst|Add0~0 ( +// Equation(s): +// \seg_static_inst|Add0~0_combout = (\hc595_ctrl_inst|cnt_4 [0] & (\hc595_ctrl_inst|cnt_4 [1] $ (VCC))) # (!\hc595_ctrl_inst|cnt_4 [0] & (\hc595_ctrl_inst|cnt_4 [1] & VCC)) +// \seg_static_inst|Add0~1 = CARRY((\hc595_ctrl_inst|cnt_4 [0] & \hc595_ctrl_inst|cnt_4 [1])) + + .dataa(\hc595_ctrl_inst|cnt_4 [0]), + .datab(\hc595_ctrl_inst|cnt_4 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\seg_static_inst|Add0~0_combout ), + .cout(\seg_static_inst|Add0~1 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~0 .lut_mask = 16'h6688; +defparam \seg_static_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N9 +dffeas \hc595_ctrl_inst|cnt_4[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_4 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_4[1] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_4[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N22 +cycloneive_lcell_comb \hc595_ctrl_inst|Equal1~0 ( +// Equation(s): +// \hc595_ctrl_inst|Equal1~0_combout = (\hc595_ctrl_inst|cnt_4 [0] & \hc595_ctrl_inst|cnt_4 [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(\hc595_ctrl_inst|cnt_4 [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Equal1~0 .lut_mask = 16'hF000; +defparam \hc595_ctrl_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N16 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[3]~2 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[3]~2_combout = (\hc595_ctrl_inst|always2~0_combout & ((\hc595_ctrl_inst|cnt_bit [3] & ((!\hc595_ctrl_inst|Equal1~0_combout ))) # (!\hc595_ctrl_inst|cnt_bit [3] & (\hc595_ctrl_inst|cnt_bit [2] & \hc595_ctrl_inst|Equal1~0_combout +// )))) # (!\hc595_ctrl_inst|always2~0_combout & (((\hc595_ctrl_inst|cnt_bit [3])))) + + .dataa(\hc595_ctrl_inst|cnt_bit [2]), + .datab(\hc595_ctrl_inst|always2~0_combout ), + .datac(\hc595_ctrl_inst|cnt_bit [3]), + .datad(\hc595_ctrl_inst|Equal1~0_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[3]~2 .lut_mask = 16'h38F0; +defparam \hc595_ctrl_inst|cnt_bit[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N17 +dffeas \hc595_ctrl_inst|cnt_bit[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[3]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[3] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N28 +cycloneive_lcell_comb \hc595_ctrl_inst|always2~1 ( +// Equation(s): +// \hc595_ctrl_inst|always2~1_combout = (!\hc595_ctrl_inst|cnt_bit [2] & (\hc595_ctrl_inst|cnt_bit [3] & (\hc595_ctrl_inst|Equal1~0_combout & \hc595_ctrl_inst|always2~0_combout ))) + + .dataa(\hc595_ctrl_inst|cnt_bit [2]), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|Equal1~0_combout ), + .datad(\hc595_ctrl_inst|always2~0_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|always2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|always2~1 .lut_mask = 16'h4000; +defparam \hc595_ctrl_inst|always2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N4 +cycloneive_lcell_comb \hc595_ctrl_inst|stcp~feeder ( +// Equation(s): +// \hc595_ctrl_inst|stcp~feeder_combout = \hc595_ctrl_inst|always2~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hc595_ctrl_inst|always2~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|stcp~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|stcp~feeder .lut_mask = 16'hFF00; +defparam \hc595_ctrl_inst|stcp~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N5 +dffeas \hc595_ctrl_inst|stcp ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|stcp~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|stcp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|stcp .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|stcp .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N19 +dffeas \hc595_ctrl_inst|shcp ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\hc595_ctrl_inst|cnt_4 [1]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|shcp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|shcp .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|shcp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N26 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[2]~3 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[2]~3_combout = (\hc595_ctrl_inst|Equal1~0_combout & ((\hc595_ctrl_inst|cnt_bit [2] & ((!\hc595_ctrl_inst|always2~0_combout ))) # (!\hc595_ctrl_inst|cnt_bit [2] & (!\hc595_ctrl_inst|cnt_bit [3] & +// \hc595_ctrl_inst|always2~0_combout )))) # (!\hc595_ctrl_inst|Equal1~0_combout & (((\hc595_ctrl_inst|cnt_bit [2])))) + + .dataa(\hc595_ctrl_inst|Equal1~0_combout ), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|cnt_bit [2]), + .datad(\hc595_ctrl_inst|always2~0_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[2]~3 .lut_mask = 16'h52F0; +defparam \hc595_ctrl_inst|cnt_bit[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N27 +dffeas \hc595_ctrl_inst|cnt_bit[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[2]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[2] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N10 +cycloneive_lcell_comb \seg_static_inst|Add0~2 ( +// Equation(s): +// \seg_static_inst|Add0~2_combout = (\seg_static_inst|cnt_wait [2] & (!\seg_static_inst|Add0~1 )) # (!\seg_static_inst|cnt_wait [2] & ((\seg_static_inst|Add0~1 ) # (GND))) +// \seg_static_inst|Add0~3 = CARRY((!\seg_static_inst|Add0~1 ) # (!\seg_static_inst|cnt_wait [2])) + + .dataa(\seg_static_inst|cnt_wait [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~1 ), + .combout(\seg_static_inst|Add0~2_combout ), + .cout(\seg_static_inst|Add0~3 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N11 +dffeas \seg_static_inst|cnt_wait[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [2]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[2] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N14 +cycloneive_lcell_comb \seg_static_inst|Add0~6 ( +// Equation(s): +// \seg_static_inst|Add0~6_combout = (\seg_static_inst|cnt_wait [4] & (!\seg_static_inst|Add0~5 )) # (!\seg_static_inst|cnt_wait [4] & ((\seg_static_inst|Add0~5 ) # (GND))) +// \seg_static_inst|Add0~7 = CARRY((!\seg_static_inst|Add0~5 ) # (!\seg_static_inst|cnt_wait [4])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [4]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~5 ), + .combout(\seg_static_inst|Add0~6_combout ), + .cout(\seg_static_inst|Add0~7 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N15 +dffeas \seg_static_inst|cnt_wait[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [4]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[4] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N16 +cycloneive_lcell_comb \seg_static_inst|Add0~8 ( +// Equation(s): +// \seg_static_inst|Add0~8_combout = (\seg_static_inst|cnt_wait [5] & (\seg_static_inst|Add0~7 $ (GND))) # (!\seg_static_inst|cnt_wait [5] & (!\seg_static_inst|Add0~7 & VCC)) +// \seg_static_inst|Add0~9 = CARRY((\seg_static_inst|cnt_wait [5] & !\seg_static_inst|Add0~7 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [5]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~7 ), + .combout(\seg_static_inst|Add0~8_combout ), + .cout(\seg_static_inst|Add0~9 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N17 +dffeas \seg_static_inst|cnt_wait[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [5]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[5] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N18 +cycloneive_lcell_comb \seg_static_inst|Add0~10 ( +// Equation(s): +// \seg_static_inst|Add0~10_combout = (\seg_static_inst|cnt_wait [6] & (!\seg_static_inst|Add0~9 )) # (!\seg_static_inst|cnt_wait [6] & ((\seg_static_inst|Add0~9 ) # (GND))) +// \seg_static_inst|Add0~11 = CARRY((!\seg_static_inst|Add0~9 ) # (!\seg_static_inst|cnt_wait [6])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [6]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~9 ), + .combout(\seg_static_inst|Add0~10_combout ), + .cout(\seg_static_inst|Add0~11 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~10 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N4 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~11 ( +// Equation(s): +// \seg_static_inst|cnt_wait~11_combout = (\seg_static_inst|Add0~10_combout & !\seg_static_inst|Equal0~7_combout ) + + .dataa(gnd), + .datab(\seg_static_inst|Add0~10_combout ), + .datac(gnd), + .datad(\seg_static_inst|Equal0~7_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~11_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~11 .lut_mask = 16'h00CC; +defparam \seg_static_inst|cnt_wait~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N5 +dffeas \seg_static_inst|cnt_wait[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~11_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [6]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[6] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N20 +cycloneive_lcell_comb \seg_static_inst|Add0~12 ( +// Equation(s): +// \seg_static_inst|Add0~12_combout = (\seg_static_inst|cnt_wait [7] & (\seg_static_inst|Add0~11 $ (GND))) # (!\seg_static_inst|cnt_wait [7] & (!\seg_static_inst|Add0~11 & VCC)) +// \seg_static_inst|Add0~13 = CARRY((\seg_static_inst|cnt_wait [7] & !\seg_static_inst|Add0~11 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [7]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~11 ), + .combout(\seg_static_inst|Add0~12_combout ), + .cout(\seg_static_inst|Add0~13 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N21 +dffeas \seg_static_inst|cnt_wait[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [7]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[7] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N24 +cycloneive_lcell_comb \seg_static_inst|Add0~16 ( +// Equation(s): +// \seg_static_inst|Add0~16_combout = (\seg_static_inst|cnt_wait [9] & (\seg_static_inst|Add0~15 $ (GND))) # (!\seg_static_inst|cnt_wait [9] & (!\seg_static_inst|Add0~15 & VCC)) +// \seg_static_inst|Add0~17 = CARRY((\seg_static_inst|cnt_wait [9] & !\seg_static_inst|Add0~15 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [9]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~15 ), + .combout(\seg_static_inst|Add0~16_combout ), + .cout(\seg_static_inst|Add0~17 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N25 +dffeas \seg_static_inst|cnt_wait[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~16_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [9]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[9] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N27 +dffeas \seg_static_inst|cnt_wait[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~18_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [10]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[10] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N0 +cycloneive_lcell_comb \seg_static_inst|Equal0~5 ( +// Equation(s): +// \seg_static_inst|Equal0~5_combout = (!\seg_static_inst|cnt_wait [8] & (!\seg_static_inst|cnt_wait [7] & (!\seg_static_inst|cnt_wait [10] & !\seg_static_inst|cnt_wait [9]))) + + .dataa(\seg_static_inst|cnt_wait [8]), + .datab(\seg_static_inst|cnt_wait [7]), + .datac(\seg_static_inst|cnt_wait [10]), + .datad(\seg_static_inst|cnt_wait [9]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~5_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~5 .lut_mask = 16'h0001; +defparam \seg_static_inst|Equal0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N2 +cycloneive_lcell_comb \seg_static_inst|Equal0~6 ( +// Equation(s): +// \seg_static_inst|Equal0~6_combout = (\seg_static_inst|cnt_wait [3] & (\seg_static_inst|cnt_wait [4] & (!\seg_static_inst|cnt_wait [6] & \seg_static_inst|cnt_wait [5]))) + + .dataa(\seg_static_inst|cnt_wait [3]), + .datab(\seg_static_inst|cnt_wait [4]), + .datac(\seg_static_inst|cnt_wait [6]), + .datad(\seg_static_inst|cnt_wait [5]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~6 .lut_mask = 16'h0800; +defparam \seg_static_inst|Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N14 +cycloneive_lcell_comb \seg_static_inst|Equal0~7 ( +// Equation(s): +// \seg_static_inst|Equal0~7_combout = (\seg_static_inst|Equal0~4_combout & (\seg_static_inst|cnt_wait [2] & (\seg_static_inst|Equal0~5_combout & \seg_static_inst|Equal0~6_combout ))) + + .dataa(\seg_static_inst|Equal0~4_combout ), + .datab(\seg_static_inst|cnt_wait [2]), + .datac(\seg_static_inst|Equal0~5_combout ), + .datad(\seg_static_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\seg_static_inst|Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~7 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N4 +cycloneive_lcell_comb \seg_static_inst|add_flag~feeder ( +// Equation(s): +// \seg_static_inst|add_flag~feeder_combout = \seg_static_inst|Equal0~7_combout + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|add_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|add_flag~feeder .lut_mask = 16'hF0F0; +defparam \seg_static_inst|add_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N5 +dffeas \seg_static_inst|add_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|add_flag~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|add_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|add_flag .is_wysiwyg = "true"; +defparam \seg_static_inst|add_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N10 +cycloneive_lcell_comb \seg_static_inst|num[0]~0 ( +// Equation(s): +// \seg_static_inst|num[0]~0_combout = \seg_static_inst|add_flag~q $ (\seg_static_inst|num [0]) + + .dataa(gnd), + .datab(\seg_static_inst|add_flag~q ), + .datac(\seg_static_inst|num [0]), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|num[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[0]~0 .lut_mask = 16'h3C3C; +defparam \seg_static_inst|num[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N11 +dffeas \seg_static_inst|num[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[0]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[0] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N0 +cycloneive_lcell_comb \seg_static_inst|num[1]~1 ( +// Equation(s): +// \seg_static_inst|num[1]~1_combout = \seg_static_inst|num [1] $ (((\seg_static_inst|add_flag~q & \seg_static_inst|num [0]))) + + .dataa(gnd), + .datab(\seg_static_inst|add_flag~q ), + .datac(\seg_static_inst|num [1]), + .datad(\seg_static_inst|num [0]), + .cin(gnd), + .combout(\seg_static_inst|num[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[1]~1 .lut_mask = 16'h3CF0; +defparam \seg_static_inst|num[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N1 +dffeas \seg_static_inst|num[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[1]~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[1] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N14 +cycloneive_lcell_comb \seg_static_inst|num[2]~2 ( +// Equation(s): +// \seg_static_inst|num[2]~2_combout = \seg_static_inst|num [2] $ (((\seg_static_inst|num [0] & (\seg_static_inst|add_flag~q & \seg_static_inst|num [1])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|add_flag~q ), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|num[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[2]~2 .lut_mask = 16'h78F0; +defparam \seg_static_inst|num[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N15 +dffeas \seg_static_inst|num[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[2]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[2] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N18 +cycloneive_lcell_comb \seg_static_inst|num[3]~3 ( +// Equation(s): +// \seg_static_inst|num[3]~3_combout = (\seg_static_inst|num [0] & (\seg_static_inst|num [2] & (\seg_static_inst|add_flag~q & \seg_static_inst|num [1]))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [2]), + .datac(\seg_static_inst|add_flag~q ), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|num[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[3]~3 .lut_mask = 16'h8000; +defparam \seg_static_inst|num[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N16 +cycloneive_lcell_comb \seg_static_inst|num[3]~4 ( +// Equation(s): +// \seg_static_inst|num[3]~4_combout = \seg_static_inst|num [3] $ (\seg_static_inst|num[3]~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|num [3]), + .datad(\seg_static_inst|num[3]~3_combout ), + .cin(gnd), + .combout(\seg_static_inst|num[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[3]~4 .lut_mask = 16'h0FF0; +defparam \seg_static_inst|num[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N17 +dffeas \seg_static_inst|num[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[3]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[3] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N8 +cycloneive_lcell_comb \seg_static_inst|WideOr1~0 ( +// Equation(s): +// \seg_static_inst|WideOr1~0_combout = (\seg_static_inst|num [0] & (\seg_static_inst|num [3] $ (((\seg_static_inst|num [1]) # (!\seg_static_inst|num [2]))))) # (!\seg_static_inst|num [0] & (!\seg_static_inst|num [3] & (!\seg_static_inst|num [2] & +// \seg_static_inst|num [1]))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr1~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr1~0 .lut_mask = 16'h2382; +defparam \seg_static_inst|WideOr1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N9 +dffeas \seg_static_inst|seg[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr1~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[5] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N6 +cycloneive_lcell_comb \seg_static_inst|seg[7]~feeder ( +// Equation(s): +// \seg_static_inst|seg[7]~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|seg[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|seg[7]~feeder .lut_mask = 16'hFFFF; +defparam \seg_static_inst|seg[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N7 +dffeas \seg_static_inst|seg[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|seg[7]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[7] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N22 +cycloneive_lcell_comb \seg_static_inst|WideOr0~0 ( +// Equation(s): +// \seg_static_inst|WideOr0~0_combout = (\seg_static_inst|num [0] & (!\seg_static_inst|num [3] & (\seg_static_inst|num [2] $ (!\seg_static_inst|num [1])))) # (!\seg_static_inst|num [0] & (!\seg_static_inst|num [1] & (\seg_static_inst|num [3] $ +// (!\seg_static_inst|num [2])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr0~0 .lut_mask = 16'h2043; +defparam \seg_static_inst|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N23 +dffeas \seg_static_inst|seg[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr0~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[6] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N12 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~2 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~2_combout = (\hc595_ctrl_inst|cnt_bit [0] & (((\hc595_ctrl_inst|cnt_bit [1]) # (!\seg_static_inst|seg [6])))) # (!\hc595_ctrl_inst|cnt_bit [0] & (!\seg_static_inst|seg [7] & ((!\hc595_ctrl_inst|cnt_bit [1])))) + + .dataa(\hc595_ctrl_inst|cnt_bit [0]), + .datab(\seg_static_inst|seg [7]), + .datac(\seg_static_inst|seg [6]), + .datad(\hc595_ctrl_inst|cnt_bit [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~2_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~2 .lut_mask = 16'hAA1B; +defparam \hc595_ctrl_inst|Mux0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N24 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~3 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~3_combout = (\hc595_ctrl_inst|cnt_bit [1] & ((\hc595_ctrl_inst|Mux0~2_combout & (!\seg_static_inst|seg [4])) # (!\hc595_ctrl_inst|Mux0~2_combout & ((!\seg_static_inst|seg [5]))))) # (!\hc595_ctrl_inst|cnt_bit [1] & +// (((\hc595_ctrl_inst|Mux0~2_combout )))) + + .dataa(\seg_static_inst|seg [4]), + .datab(\hc595_ctrl_inst|cnt_bit [1]), + .datac(\seg_static_inst|seg [5]), + .datad(\hc595_ctrl_inst|Mux0~2_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~3_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~3 .lut_mask = 16'h770C; +defparam \hc595_ctrl_inst|Mux0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N20 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~2 ( +// Equation(s): +// \hc595_ctrl_inst|ds~2_combout = (!\hc595_ctrl_inst|cnt_bit [3] & ((\hc595_ctrl_inst|cnt_bit [2] & ((\hc595_ctrl_inst|Mux0~3_combout ))) # (!\hc595_ctrl_inst|cnt_bit [2] & (!\seg_static_inst|seg [7])))) + + .dataa(\seg_static_inst|seg [7]), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|cnt_bit [2]), + .datad(\hc595_ctrl_inst|Mux0~3_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~2_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~2 .lut_mask = 16'h3101; +defparam \hc595_ctrl_inst|ds~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N20 +cycloneive_lcell_comb \seg_static_inst|WideOr4~0 ( +// Equation(s): +// \seg_static_inst|WideOr4~0_combout = (\seg_static_inst|num [3] & (\seg_static_inst|num [2] & ((\seg_static_inst|num [1]) # (!\seg_static_inst|num [0])))) # (!\seg_static_inst|num [3] & (!\seg_static_inst|num [0] & (!\seg_static_inst|num [2] & +// \seg_static_inst|num [1]))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr4~0 .lut_mask = 16'hC140; +defparam \seg_static_inst|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N21 +dffeas \seg_static_inst|seg[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr4~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[2] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N4 +cycloneive_lcell_comb \seg_static_inst|WideOr3~0 ( +// Equation(s): +// \seg_static_inst|WideOr3~0_combout = (\seg_static_inst|num [1] & ((\seg_static_inst|num [0] & ((\seg_static_inst|num [2]))) # (!\seg_static_inst|num [0] & (\seg_static_inst|num [3] & !\seg_static_inst|num [2])))) # (!\seg_static_inst|num [1] & +// (!\seg_static_inst|num [3] & (\seg_static_inst|num [0] $ (\seg_static_inst|num [2])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr3~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr3~0 .lut_mask = 16'hA412; +defparam \seg_static_inst|WideOr3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N5 +dffeas \seg_static_inst|seg[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr3~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[3] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N2 +cycloneive_lcell_comb \seg_static_inst|WideOr5~0 ( +// Equation(s): +// \seg_static_inst|WideOr5~0_combout = (\seg_static_inst|num [3] & ((\seg_static_inst|num [0] & ((\seg_static_inst|num [1]))) # (!\seg_static_inst|num [0] & (\seg_static_inst|num [2])))) # (!\seg_static_inst|num [3] & (\seg_static_inst|num [2] & +// (\seg_static_inst|num [0] $ (\seg_static_inst|num [1])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr5~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr5~0 .lut_mask = 16'hD860; +defparam \seg_static_inst|WideOr5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N3 +dffeas \seg_static_inst|seg[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr5~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[1] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N30 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~0 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~0_combout = (\hc595_ctrl_inst|cnt_bit [0] & (\hc595_ctrl_inst|cnt_bit [1])) # (!\hc595_ctrl_inst|cnt_bit [0] & ((\hc595_ctrl_inst|cnt_bit [1] & ((!\seg_static_inst|seg [1]))) # (!\hc595_ctrl_inst|cnt_bit [1] & (!\seg_static_inst|seg +// [3])))) + + .dataa(\hc595_ctrl_inst|cnt_bit [0]), + .datab(\hc595_ctrl_inst|cnt_bit [1]), + .datac(\seg_static_inst|seg [3]), + .datad(\seg_static_inst|seg [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~0 .lut_mask = 16'h89CD; +defparam \hc595_ctrl_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N28 +cycloneive_lcell_comb \seg_static_inst|WideOr6~0 ( +// Equation(s): +// \seg_static_inst|WideOr6~0_combout = (\seg_static_inst|num [3] & (\seg_static_inst|num [0] & (\seg_static_inst|num [2] $ (\seg_static_inst|num [1])))) # (!\seg_static_inst|num [3] & (!\seg_static_inst|num [1] & (\seg_static_inst|num [0] $ +// (\seg_static_inst|num [2])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr6~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr6~0 .lut_mask = 16'h0892; +defparam \seg_static_inst|WideOr6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N29 +dffeas \seg_static_inst|seg[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr6~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[0] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N6 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~1 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~1_combout = (\hc595_ctrl_inst|cnt_bit [0] & ((\hc595_ctrl_inst|Mux0~0_combout & ((!\seg_static_inst|seg [0]))) # (!\hc595_ctrl_inst|Mux0~0_combout & (!\seg_static_inst|seg [2])))) # (!\hc595_ctrl_inst|cnt_bit [0] & +// (((\hc595_ctrl_inst|Mux0~0_combout )))) + + .dataa(\hc595_ctrl_inst|cnt_bit [0]), + .datab(\seg_static_inst|seg [2]), + .datac(\hc595_ctrl_inst|Mux0~0_combout ), + .datad(\seg_static_inst|seg [0]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~1 .lut_mask = 16'h52F2; +defparam \hc595_ctrl_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N12 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~1 ( +// Equation(s): +// \hc595_ctrl_inst|ds~1_combout = (\hc595_ctrl_inst|cnt_bit [3] & (!\hc595_ctrl_inst|cnt_bit [2] & \hc595_ctrl_inst|Mux0~1_combout )) + + .dataa(gnd), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|cnt_bit [2]), + .datad(\hc595_ctrl_inst|Mux0~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~1 .lut_mask = 16'h0C00; +defparam \hc595_ctrl_inst|ds~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N30 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~3 ( +// Equation(s): +// \hc595_ctrl_inst|ds~3_combout = (\hc595_ctrl_inst|ds~0_combout & ((\hc595_ctrl_inst|ds~2_combout ) # ((\hc595_ctrl_inst|ds~1_combout )))) # (!\hc595_ctrl_inst|ds~0_combout & (((\hc595_ctrl_inst|ds~q )))) + + .dataa(\hc595_ctrl_inst|ds~0_combout ), + .datab(\hc595_ctrl_inst|ds~2_combout ), + .datac(\hc595_ctrl_inst|ds~q ), + .datad(\hc595_ctrl_inst|ds~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~3_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~3 .lut_mask = 16'hFAD8; +defparam \hc595_ctrl_inst|ds~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N31 +dffeas \hc595_ctrl_inst|ds ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|ds~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|ds~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|ds .power_up = "low"; +// synopsys translate_on + +assign stcp = \stcp~output_o ; + +assign shcp = \shcp~output_o ; + +assign ds = \ds~output_o ; + +assign oe = \oe~output_o ; + +endmodule diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_8_1200mv_0c_v_slow.sdo b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_8_1200mv_0c_v_slow.sdo new file mode 100644 index 0000000..9c35a85 --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_8_1200mv_0c_v_slow.sdo @@ -0,0 +1,1858 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "seg_595_static") + (DATE "06/02/2023 20:55:14") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (391:391:391)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (390:390:390)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (387:387:387)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~20) + (DELAY + (ABSOLUTE + (PORT datab (918:918:918) (818:818:818)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~22) + (DELAY + (ABSOLUTE + (PORT datab (954:954:954) (867:867:867)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~24) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (406:406:406)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~26) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (549:549:549)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~28) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (393:393:393)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~30) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (396:396:396)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~32) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~34) + (DELAY + (ABSOLUTE + (PORT datab (554:554:554) (543:543:543)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~36) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~38) + (DELAY + (ABSOLUTE + (PORT datab (611:611:611) (565:565:565)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~40) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~42) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (548:548:548)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~44) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~46) + (DELAY + (ABSOLUTE + (PORT datad (518:518:518) (504:504:504)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~0) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (573:573:573)) + (PORT datac (534:534:534) (528:528:528)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5211:5211:5211) (5146:5146:5146)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (508:508:508)) + (PORT datab (373:373:373) (446:446:446)) + (PORT datac (336:336:336) (420:420:420)) + (PORT datad (343:343:343) (422:422:422)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[24\]) + (DELAY + (ABSOLUTE + (PORT clk (2104:2104:2104) (2077:2077:2077)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5527:5527:5527) (5538:5538:5538)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5022:5022:5022) (4904:4904:4904)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (835:835:835)) + (PORT datab (599:599:599) (549:549:549)) + (PORT datac (841:841:841) (778:778:778)) + (PORT datad (300:300:300) (356:356:356)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5527:5527:5527) (5538:5538:5538)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5022:5022:5022) (4904:4904:4904)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5527:5527:5527) (5538:5538:5538)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5022:5022:5022) (4904:4904:4904)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (PORT datab (339:339:339) (394:394:394)) + (PORT datac (548:548:548) (515:515:515)) + (PORT datad (538:538:538) (507:507:507)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5527:5527:5527) (5538:5538:5538)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5022:5022:5022) (4904:4904:4904)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5022:5022:5022) (4904:4904:4904)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5022:5022:5022) (4904:4904:4904)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (530:530:530)) + (PORT datab (598:598:598) (547:547:547)) + (PORT datac (499:499:499) (489:489:489)) + (PORT datad (298:298:298) (353:353:353)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5527:5527:5527) (5538:5538:5538)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1642:1642:1642) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5022:5022:5022) (4904:4904:4904)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5527:5527:5527) (5538:5538:5538)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5527:5527:5527) (5538:5538:5538)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (570:570:570)) + (PORT datab (339:339:339) (394:394:394)) + (PORT datac (296:296:296) (360:360:360)) + (PORT datad (498:498:498) (477:477:477)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (282:282:282)) + (PORT datab (268:268:268) (276:276:276)) + (PORT datac (226:226:226) (241:241:241)) + (PORT datad (227:227:227) (235:235:235)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4981:4981:4981) (4864:4864:4864)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4981:4981:4981) (4864:4864:4864)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~0) + (DELAY + (ABSOLUTE + (PORT datac (306:306:306) (343:343:343)) + (PORT datad (433:433:433) (368:368:368)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~1) + (DELAY + (ABSOLUTE + (PORT datac (306:306:306) (343:343:343)) + (PORT datad (432:432:432) (367:367:367)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~2) + (DELAY + (ABSOLUTE + (PORT datac (537:537:537) (486:486:486)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~3) + (DELAY + (ABSOLUTE + (PORT datac (306:306:306) (343:343:343)) + (PORT datad (438:438:438) (363:363:363)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~4) + (DELAY + (ABSOLUTE + (PORT datac (537:537:537) (486:486:486)) + (PORT datad (228:228:228) (236:236:236)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~5) + (DELAY + (ABSOLUTE + (PORT datac (306:306:306) (342:342:342)) + (PORT datad (465:465:465) (385:385:385)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~6) + (DELAY + (ABSOLUTE + (PORT datac (538:538:538) (486:486:486)) + (PORT datad (229:229:229) (237:237:237)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~7) + (DELAY + (ABSOLUTE + (PORT datac (306:306:306) (343:343:343)) + (PORT datad (464:464:464) (383:383:383)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~8) + (DELAY + (ABSOLUTE + (PORT datac (538:538:538) (486:486:486)) + (PORT datad (231:231:231) (239:239:239)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~9) + (DELAY + (ABSOLUTE + (PORT datac (306:306:306) (342:342:342)) + (PORT datad (728:728:728) (593:593:593)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~10) + (DELAY + (ABSOLUTE + (PORT datab (352:352:352) (378:378:378)) + (PORT datac (812:812:812) (683:683:683)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE stcp\~output) + (DELAY + (ABSOLUTE + (PORT i (1597:1597:1597) (1456:1456:1456)) + (IOPATH i o (3063:3063:3063) (3011:3011:3011)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE shcp\~output) + (DELAY + (ABSOLUTE + (PORT i (1823:1823:1823) (1602:1602:1602)) + (IOPATH i o (3043:3043:3043) (2991:2991:2991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE ds\~output) + (DELAY + (ABSOLUTE + (PORT i (2172:2172:2172) (1878:1878:1878)) + (IOPATH i o (3053:3053:3053) (3001:3001:3001)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE oe\~output) + (DELAY + (ABSOLUTE + (PORT i (3948:3948:3948) (3871:3871:3871)) + (IOPATH i o (3001:3001:3001) (3053:3053:3053)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (788:788:788) (813:813:813)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sys_clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (175:175:175) (172:172:172)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_4\[0\]\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_4\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4981:4981:4981) (4864:4864:4864)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (576:576:576)) + (PORT datab (579:579:579) (564:564:564)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5241:5241:5241) (5183:5183:5183)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (312:312:312) (331:331:331)) + (PORT datab (351:351:351) (409:409:409)) + (PORT datad (233:233:233) (243:243:243)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5241:5241:5241) (5183:5183:5183)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|always2\~0) + (DELAY + (ABSOLUTE + (PORT datac (306:306:306) (373:373:373)) + (PORT datad (302:302:302) (357:357:357)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (400:400:400)) + (PORT datab (338:338:338) (393:393:393)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_4\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4981:4981:4981) (4864:4864:4864)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT datac (536:536:536) (530:530:530)) + (PORT datad (536:536:536) (531:531:531)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (418:418:418)) + (PORT datab (286:286:286) (299:299:299)) + (PORT datad (459:459:459) (394:394:394)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5241:5241:5241) (5183:5183:5183)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|always2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (414:414:414)) + (PORT datab (346:346:346) (409:409:409)) + (PORT datac (268:268:268) (292:292:292)) + (PORT datad (248:248:248) (263:263:263)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|stcp\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (236:236:236) (247:247:247)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|stcp) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5241:5241:5241) (5183:5183:5183)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|shcp) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT asdata (1261:1261:1261) (1192:1192:1192)) + (PORT clrn (4981:4981:4981) (4864:4864:4864)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (312:312:312) (331:331:331)) + (PORT datab (347:347:347) (411:411:411)) + (PORT datad (248:248:248) (263:263:263)) + (IOPATH dataa combout (375:375:375) (392:392:392)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5241:5241:5241) (5183:5183:5183)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4981:4981:4981) (4864:4864:4864)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (383:383:383)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4981:4981:4981) (4864:4864:4864)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (324:324:324) (381:381:381)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4981:4981:4981) (4864:4864:4864)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~11) + (DELAY + (ABSOLUTE + (PORT datab (269:269:269) (276:276:276)) + (PORT datad (806:806:806) (705:705:705)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4981:4981:4981) (4864:4864:4864)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4981:4981:4981) (4864:4864:4864)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (323:323:323) (379:379:379)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4981:4981:4981) (4864:4864:4864)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4981:4981:4981) (4864:4864:4864)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (394:394:394)) + (PORT datab (327:327:327) (384:384:384)) + (PORT datac (287:287:287) (354:354:354)) + (PORT datad (287:287:287) (345:345:345)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (392:392:392)) + (PORT datab (326:326:326) (383:383:383)) + (PORT datac (281:281:281) (347:347:347)) + (PORT datad (285:285:285) (344:344:344)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (282:282:282)) + (PORT datab (1249:1249:1249) (1087:1087:1087)) + (PORT datac (1080:1080:1080) (893:893:893)) + (PORT datad (1065:1065:1065) (877:877:877)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|add_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (306:306:306) (343:343:343)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|add_flag) + (DELAY + (ABSOLUTE + (PORT clk (2104:2104:2104) (2077:2077:2077)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5527:5527:5527) (5538:5538:5538)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (945:945:945) (865:865:865)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5211:5211:5211) (5146:5146:5146)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (944:944:944) (864:864:864)) + (PORT datad (361:361:361) (454:454:454)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5211:5211:5211) (5146:5146:5146)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (505:505:505)) + (PORT datab (945:945:945) (865:865:865)) + (PORT datad (337:337:337) (415:415:415)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5211:5211:5211) (5146:5146:5146)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (505:505:505)) + (PORT datab (381:381:381) (454:454:454)) + (PORT datac (901:901:901) (831:831:831)) + (PORT datad (339:339:339) (418:418:418)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT datad (228:228:228) (235:235:235)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5211:5211:5211) (5146:5146:5146)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (503:503:503)) + (PORT datab (374:374:374) (447:447:447)) + (PORT datac (334:334:334) (419:419:419)) + (PORT datad (334:334:334) (413:413:413)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5211:5211:5211) (5146:5146:5146)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5241:5241:5241) (5183:5183:5183)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (507:507:507)) + (PORT datab (373:373:373) (446:446:446)) + (PORT datac (336:336:336) (420:420:420)) + (PORT datad (341:341:341) (420:420:420)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5211:5211:5211) (5146:5146:5146)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (562:562:562)) + (PORT datab (551:551:551) (528:528:528)) + (PORT datac (275:275:275) (338:338:338)) + (PORT datad (556:556:556) (531:531:531)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (378:378:378)) + (PORT datab (616:616:616) (570:570:570)) + (PORT datac (277:277:277) (340:340:340)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~2) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (404:404:404)) + (PORT datab (345:345:345) (408:408:408)) + (PORT datac (302:302:302) (376:376:376)) + (PORT datad (475:475:475) (400:400:400)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (507:507:507)) + (PORT datab (374:374:374) (447:447:447)) + (PORT datac (335:335:335) (420:420:420)) + (PORT datad (340:340:340) (419:419:419)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5211:5211:5211) (5146:5146:5146)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (503:503:503)) + (PORT datab (374:374:374) (447:447:447)) + (PORT datac (334:334:334) (418:418:418)) + (PORT datad (332:332:332) (411:411:411)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5211:5211:5211) (5146:5146:5146)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (502:502:502)) + (PORT datab (374:374:374) (447:447:447)) + (PORT datac (334:334:334) (418:418:418)) + (PORT datad (332:332:332) (410:410:410)) + (IOPATH dataa combout (420:420:420) (444:444:444)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5211:5211:5211) (5146:5146:5146)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (563:563:563)) + (PORT datab (615:615:615) (570:570:570)) + (PORT datac (278:278:278) (341:341:341)) + (PORT datad (280:280:280) (335:335:335)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (508:508:508)) + (PORT datab (373:373:373) (446:446:446)) + (PORT datac (336:336:336) (420:420:420)) + (PORT datad (343:343:343) (423:423:423)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5211:5211:5211) (5146:5146:5146)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (562:562:562)) + (PORT datab (319:319:319) (374:374:374)) + (PORT datac (228:228:228) (243:243:243)) + (PORT datad (278:278:278) (334:334:334)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~1) + (DELAY + (ABSOLUTE + (PORT datab (346:346:346) (409:409:409)) + (PORT datac (305:305:305) (379:379:379)) + (PORT datad (443:443:443) (383:383:383)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~3) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (286:286:286)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datad (229:229:229) (236:236:236)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|ds) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5241:5241:5241) (5183:5183:5183)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_8_1200mv_85c_slow.vo b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_8_1200mv_85c_slow.vo new file mode 100644 index 0000000..eba81e2 --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_8_1200mv_85c_slow.vo @@ -0,0 +1,2444 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 20:55:14" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module seg_595_static ( + sys_clk, + sys_rst_n, + stcp, + shcp, + ds, + oe); +input sys_clk; +input sys_rst_n; +output stcp; +output shcp; +output ds; +output oe; + +// Design Ports Information +// stcp => Location: PIN_Y1, I/O Standard: 2.5 V, Current Strength: Default +// shcp => Location: PIN_W1, I/O Standard: 2.5 V, Current Strength: Default +// ds => Location: PIN_AA1, I/O Standard: 2.5 V, Current Strength: Default +// oe => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("seg_595_static_8_1200mv_85c_v_slow.sdo"); +// synopsys translate_on + +wire \seg_static_inst|Add0~4_combout ; +wire \seg_static_inst|Add0~14_combout ; +wire \seg_static_inst|Add0~19 ; +wire \seg_static_inst|Add0~20_combout ; +wire \seg_static_inst|Add0~21 ; +wire \seg_static_inst|Add0~22_combout ; +wire \seg_static_inst|Add0~23 ; +wire \seg_static_inst|Add0~24_combout ; +wire \seg_static_inst|Add0~25 ; +wire \seg_static_inst|Add0~26_combout ; +wire \seg_static_inst|Add0~27 ; +wire \seg_static_inst|Add0~28_combout ; +wire \seg_static_inst|Add0~29 ; +wire \seg_static_inst|Add0~30_combout ; +wire \seg_static_inst|Add0~31 ; +wire \seg_static_inst|Add0~32_combout ; +wire \seg_static_inst|Add0~33 ; +wire \seg_static_inst|Add0~34_combout ; +wire \seg_static_inst|Add0~35 ; +wire \seg_static_inst|Add0~36_combout ; +wire \seg_static_inst|Add0~37 ; +wire \seg_static_inst|Add0~38_combout ; +wire \seg_static_inst|Add0~39 ; +wire \seg_static_inst|Add0~40_combout ; +wire \seg_static_inst|Add0~41 ; +wire \seg_static_inst|Add0~42_combout ; +wire \seg_static_inst|Add0~43 ; +wire \seg_static_inst|Add0~44_combout ; +wire \seg_static_inst|Add0~45 ; +wire \seg_static_inst|Add0~46_combout ; +wire \hc595_ctrl_inst|ds~0_combout ; +wire \seg_static_inst|WideOr2~0_combout ; +wire \seg_static_inst|Equal0~0_combout ; +wire \seg_static_inst|Equal0~1_combout ; +wire \seg_static_inst|Equal0~2_combout ; +wire \seg_static_inst|Equal0~3_combout ; +wire \seg_static_inst|Equal0~4_combout ; +wire \seg_static_inst|cnt_wait~0_combout ; +wire \seg_static_inst|cnt_wait~1_combout ; +wire \seg_static_inst|cnt_wait~2_combout ; +wire \seg_static_inst|cnt_wait~3_combout ; +wire \seg_static_inst|cnt_wait~4_combout ; +wire \seg_static_inst|cnt_wait~5_combout ; +wire \seg_static_inst|cnt_wait~6_combout ; +wire \seg_static_inst|cnt_wait~7_combout ; +wire \seg_static_inst|cnt_wait~8_combout ; +wire \seg_static_inst|cnt_wait~9_combout ; +wire \seg_static_inst|cnt_wait~10_combout ; +wire \stcp~output_o ; +wire \shcp~output_o ; +wire \ds~output_o ; +wire \oe~output_o ; +wire \sys_clk~input_o ; +wire \sys_clk~inputclkctrl_outclk ; +wire \hc595_ctrl_inst|cnt_4[0]~0_combout ; +wire \sys_rst_n~input_o ; +wire \hc595_ctrl_inst|cnt_bit[0]~1_combout ; +wire \hc595_ctrl_inst|cnt_bit[1]~0_combout ; +wire \hc595_ctrl_inst|always2~0_combout ; +wire \seg_static_inst|Add0~0_combout ; +wire \hc595_ctrl_inst|Equal1~0_combout ; +wire \hc595_ctrl_inst|cnt_bit[3]~2_combout ; +wire \hc595_ctrl_inst|always2~1_combout ; +wire \hc595_ctrl_inst|stcp~feeder_combout ; +wire \hc595_ctrl_inst|stcp~q ; +wire \hc595_ctrl_inst|shcp~q ; +wire \hc595_ctrl_inst|cnt_bit[2]~3_combout ; +wire \seg_static_inst|Add0~1 ; +wire \seg_static_inst|Add0~2_combout ; +wire \seg_static_inst|Add0~3 ; +wire \seg_static_inst|Add0~5 ; +wire \seg_static_inst|Add0~6_combout ; +wire \seg_static_inst|Add0~7 ; +wire \seg_static_inst|Add0~8_combout ; +wire \seg_static_inst|Add0~9 ; +wire \seg_static_inst|Add0~10_combout ; +wire \seg_static_inst|cnt_wait~11_combout ; +wire \seg_static_inst|Add0~11 ; +wire \seg_static_inst|Add0~12_combout ; +wire \seg_static_inst|Add0~13 ; +wire \seg_static_inst|Add0~15 ; +wire \seg_static_inst|Add0~16_combout ; +wire \seg_static_inst|Add0~17 ; +wire \seg_static_inst|Add0~18_combout ; +wire \seg_static_inst|Equal0~5_combout ; +wire \seg_static_inst|Equal0~6_combout ; +wire \seg_static_inst|Equal0~7_combout ; +wire \seg_static_inst|add_flag~feeder_combout ; +wire \seg_static_inst|add_flag~q ; +wire \seg_static_inst|num[0]~0_combout ; +wire \seg_static_inst|num[1]~1_combout ; +wire \seg_static_inst|num[2]~2_combout ; +wire \seg_static_inst|num[3]~3_combout ; +wire \seg_static_inst|num[3]~4_combout ; +wire \seg_static_inst|WideOr1~0_combout ; +wire \seg_static_inst|seg[7]~feeder_combout ; +wire \seg_static_inst|WideOr0~0_combout ; +wire \hc595_ctrl_inst|Mux0~2_combout ; +wire \hc595_ctrl_inst|Mux0~3_combout ; +wire \hc595_ctrl_inst|ds~2_combout ; +wire \seg_static_inst|WideOr4~0_combout ; +wire \seg_static_inst|WideOr3~0_combout ; +wire \seg_static_inst|WideOr5~0_combout ; +wire \hc595_ctrl_inst|Mux0~0_combout ; +wire \seg_static_inst|WideOr6~0_combout ; +wire \hc595_ctrl_inst|Mux0~1_combout ; +wire \hc595_ctrl_inst|ds~1_combout ; +wire \hc595_ctrl_inst|ds~3_combout ; +wire \hc595_ctrl_inst|ds~q ; +wire [7:0] \seg_static_inst|seg ; +wire [3:0] \seg_static_inst|num ; +wire [24:0] \seg_static_inst|cnt_wait ; +wire [3:0] \hc595_ctrl_inst|cnt_bit ; +wire [1:0] \hc595_ctrl_inst|cnt_4 ; + + +// Location: LCCOMB_X14_Y13_N12 +cycloneive_lcell_comb \seg_static_inst|Add0~4 ( +// Equation(s): +// \seg_static_inst|Add0~4_combout = (\seg_static_inst|cnt_wait [3] & (\seg_static_inst|Add0~3 $ (GND))) # (!\seg_static_inst|cnt_wait [3] & (!\seg_static_inst|Add0~3 & VCC)) +// \seg_static_inst|Add0~5 = CARRY((\seg_static_inst|cnt_wait [3] & !\seg_static_inst|Add0~3 )) + + .dataa(\seg_static_inst|cnt_wait [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~3 ), + .combout(\seg_static_inst|Add0~4_combout ), + .cout(\seg_static_inst|Add0~5 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \seg_static_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N22 +cycloneive_lcell_comb \seg_static_inst|Add0~14 ( +// Equation(s): +// \seg_static_inst|Add0~14_combout = (\seg_static_inst|cnt_wait [8] & (!\seg_static_inst|Add0~13 )) # (!\seg_static_inst|cnt_wait [8] & ((\seg_static_inst|Add0~13 ) # (GND))) +// \seg_static_inst|Add0~15 = CARRY((!\seg_static_inst|Add0~13 ) # (!\seg_static_inst|cnt_wait [8])) + + .dataa(\seg_static_inst|cnt_wait [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~13 ), + .combout(\seg_static_inst|Add0~14_combout ), + .cout(\seg_static_inst|Add0~15 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N26 +cycloneive_lcell_comb \seg_static_inst|Add0~18 ( +// Equation(s): +// \seg_static_inst|Add0~18_combout = (\seg_static_inst|cnt_wait [10] & (!\seg_static_inst|Add0~17 )) # (!\seg_static_inst|cnt_wait [10] & ((\seg_static_inst|Add0~17 ) # (GND))) +// \seg_static_inst|Add0~19 = CARRY((!\seg_static_inst|Add0~17 ) # (!\seg_static_inst|cnt_wait [10])) + + .dataa(\seg_static_inst|cnt_wait [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~17 ), + .combout(\seg_static_inst|Add0~18_combout ), + .cout(\seg_static_inst|Add0~19 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~18 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N28 +cycloneive_lcell_comb \seg_static_inst|Add0~20 ( +// Equation(s): +// \seg_static_inst|Add0~20_combout = (\seg_static_inst|cnt_wait [11] & (\seg_static_inst|Add0~19 $ (GND))) # (!\seg_static_inst|cnt_wait [11] & (!\seg_static_inst|Add0~19 & VCC)) +// \seg_static_inst|Add0~21 = CARRY((\seg_static_inst|cnt_wait [11] & !\seg_static_inst|Add0~19 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [11]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~19 ), + .combout(\seg_static_inst|Add0~20_combout ), + .cout(\seg_static_inst|Add0~21 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~20 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N30 +cycloneive_lcell_comb \seg_static_inst|Add0~22 ( +// Equation(s): +// \seg_static_inst|Add0~22_combout = (\seg_static_inst|cnt_wait [12] & (!\seg_static_inst|Add0~21 )) # (!\seg_static_inst|cnt_wait [12] & ((\seg_static_inst|Add0~21 ) # (GND))) +// \seg_static_inst|Add0~23 = CARRY((!\seg_static_inst|Add0~21 ) # (!\seg_static_inst|cnt_wait [12])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [12]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~21 ), + .combout(\seg_static_inst|Add0~22_combout ), + .cout(\seg_static_inst|Add0~23 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~22 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N0 +cycloneive_lcell_comb \seg_static_inst|Add0~24 ( +// Equation(s): +// \seg_static_inst|Add0~24_combout = (\seg_static_inst|cnt_wait [13] & (\seg_static_inst|Add0~23 $ (GND))) # (!\seg_static_inst|cnt_wait [13] & (!\seg_static_inst|Add0~23 & VCC)) +// \seg_static_inst|Add0~25 = CARRY((\seg_static_inst|cnt_wait [13] & !\seg_static_inst|Add0~23 )) + + .dataa(\seg_static_inst|cnt_wait [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~23 ), + .combout(\seg_static_inst|Add0~24_combout ), + .cout(\seg_static_inst|Add0~25 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~24 .lut_mask = 16'hA50A; +defparam \seg_static_inst|Add0~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N2 +cycloneive_lcell_comb \seg_static_inst|Add0~26 ( +// Equation(s): +// \seg_static_inst|Add0~26_combout = (\seg_static_inst|cnt_wait [14] & (!\seg_static_inst|Add0~25 )) # (!\seg_static_inst|cnt_wait [14] & ((\seg_static_inst|Add0~25 ) # (GND))) +// \seg_static_inst|Add0~27 = CARRY((!\seg_static_inst|Add0~25 ) # (!\seg_static_inst|cnt_wait [14])) + + .dataa(\seg_static_inst|cnt_wait [14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~25 ), + .combout(\seg_static_inst|Add0~26_combout ), + .cout(\seg_static_inst|Add0~27 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~26 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N4 +cycloneive_lcell_comb \seg_static_inst|Add0~28 ( +// Equation(s): +// \seg_static_inst|Add0~28_combout = (\seg_static_inst|cnt_wait [15] & (\seg_static_inst|Add0~27 $ (GND))) # (!\seg_static_inst|cnt_wait [15] & (!\seg_static_inst|Add0~27 & VCC)) +// \seg_static_inst|Add0~29 = CARRY((\seg_static_inst|cnt_wait [15] & !\seg_static_inst|Add0~27 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [15]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~27 ), + .combout(\seg_static_inst|Add0~28_combout ), + .cout(\seg_static_inst|Add0~29 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~28 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N6 +cycloneive_lcell_comb \seg_static_inst|Add0~30 ( +// Equation(s): +// \seg_static_inst|Add0~30_combout = (\seg_static_inst|cnt_wait [16] & (!\seg_static_inst|Add0~29 )) # (!\seg_static_inst|cnt_wait [16] & ((\seg_static_inst|Add0~29 ) # (GND))) +// \seg_static_inst|Add0~31 = CARRY((!\seg_static_inst|Add0~29 ) # (!\seg_static_inst|cnt_wait [16])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [16]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~29 ), + .combout(\seg_static_inst|Add0~30_combout ), + .cout(\seg_static_inst|Add0~31 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~30 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N8 +cycloneive_lcell_comb \seg_static_inst|Add0~32 ( +// Equation(s): +// \seg_static_inst|Add0~32_combout = (\seg_static_inst|cnt_wait [17] & (\seg_static_inst|Add0~31 $ (GND))) # (!\seg_static_inst|cnt_wait [17] & (!\seg_static_inst|Add0~31 & VCC)) +// \seg_static_inst|Add0~33 = CARRY((\seg_static_inst|cnt_wait [17] & !\seg_static_inst|Add0~31 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [17]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~31 ), + .combout(\seg_static_inst|Add0~32_combout ), + .cout(\seg_static_inst|Add0~33 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~32 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N10 +cycloneive_lcell_comb \seg_static_inst|Add0~34 ( +// Equation(s): +// \seg_static_inst|Add0~34_combout = (\seg_static_inst|cnt_wait [18] & (!\seg_static_inst|Add0~33 )) # (!\seg_static_inst|cnt_wait [18] & ((\seg_static_inst|Add0~33 ) # (GND))) +// \seg_static_inst|Add0~35 = CARRY((!\seg_static_inst|Add0~33 ) # (!\seg_static_inst|cnt_wait [18])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [18]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~33 ), + .combout(\seg_static_inst|Add0~34_combout ), + .cout(\seg_static_inst|Add0~35 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~34 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N12 +cycloneive_lcell_comb \seg_static_inst|Add0~36 ( +// Equation(s): +// \seg_static_inst|Add0~36_combout = (\seg_static_inst|cnt_wait [19] & (\seg_static_inst|Add0~35 $ (GND))) # (!\seg_static_inst|cnt_wait [19] & (!\seg_static_inst|Add0~35 & VCC)) +// \seg_static_inst|Add0~37 = CARRY((\seg_static_inst|cnt_wait [19] & !\seg_static_inst|Add0~35 )) + + .dataa(\seg_static_inst|cnt_wait [19]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~35 ), + .combout(\seg_static_inst|Add0~36_combout ), + .cout(\seg_static_inst|Add0~37 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~36 .lut_mask = 16'hA50A; +defparam \seg_static_inst|Add0~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N14 +cycloneive_lcell_comb \seg_static_inst|Add0~38 ( +// Equation(s): +// \seg_static_inst|Add0~38_combout = (\seg_static_inst|cnt_wait [20] & (!\seg_static_inst|Add0~37 )) # (!\seg_static_inst|cnt_wait [20] & ((\seg_static_inst|Add0~37 ) # (GND))) +// \seg_static_inst|Add0~39 = CARRY((!\seg_static_inst|Add0~37 ) # (!\seg_static_inst|cnt_wait [20])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [20]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~37 ), + .combout(\seg_static_inst|Add0~38_combout ), + .cout(\seg_static_inst|Add0~39 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~38 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N16 +cycloneive_lcell_comb \seg_static_inst|Add0~40 ( +// Equation(s): +// \seg_static_inst|Add0~40_combout = (\seg_static_inst|cnt_wait [21] & (\seg_static_inst|Add0~39 $ (GND))) # (!\seg_static_inst|cnt_wait [21] & (!\seg_static_inst|Add0~39 & VCC)) +// \seg_static_inst|Add0~41 = CARRY((\seg_static_inst|cnt_wait [21] & !\seg_static_inst|Add0~39 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [21]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~39 ), + .combout(\seg_static_inst|Add0~40_combout ), + .cout(\seg_static_inst|Add0~41 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~40 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N18 +cycloneive_lcell_comb \seg_static_inst|Add0~42 ( +// Equation(s): +// \seg_static_inst|Add0~42_combout = (\seg_static_inst|cnt_wait [22] & (!\seg_static_inst|Add0~41 )) # (!\seg_static_inst|cnt_wait [22] & ((\seg_static_inst|Add0~41 ) # (GND))) +// \seg_static_inst|Add0~43 = CARRY((!\seg_static_inst|Add0~41 ) # (!\seg_static_inst|cnt_wait [22])) + + .dataa(\seg_static_inst|cnt_wait [22]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~41 ), + .combout(\seg_static_inst|Add0~42_combout ), + .cout(\seg_static_inst|Add0~43 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~42 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N20 +cycloneive_lcell_comb \seg_static_inst|Add0~44 ( +// Equation(s): +// \seg_static_inst|Add0~44_combout = (\seg_static_inst|cnt_wait [23] & (\seg_static_inst|Add0~43 $ (GND))) # (!\seg_static_inst|cnt_wait [23] & (!\seg_static_inst|Add0~43 & VCC)) +// \seg_static_inst|Add0~45 = CARRY((\seg_static_inst|cnt_wait [23] & !\seg_static_inst|Add0~43 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [23]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~43 ), + .combout(\seg_static_inst|Add0~44_combout ), + .cout(\seg_static_inst|Add0~45 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~44 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N22 +cycloneive_lcell_comb \seg_static_inst|Add0~46 ( +// Equation(s): +// \seg_static_inst|Add0~46_combout = \seg_static_inst|Add0~45 $ (\seg_static_inst|cnt_wait [24]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\seg_static_inst|cnt_wait [24]), + .cin(\seg_static_inst|Add0~45 ), + .combout(\seg_static_inst|Add0~46_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Add0~46 .lut_mask = 16'h0FF0; +defparam \seg_static_inst|Add0~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N10 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~0 ( +// Equation(s): +// \hc595_ctrl_inst|ds~0_combout = (!\hc595_ctrl_inst|cnt_4 [1] & !\hc595_ctrl_inst|cnt_4 [0]) + + .dataa(\hc595_ctrl_inst|cnt_4 [1]), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(gnd), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~0 .lut_mask = 16'h0505; +defparam \hc595_ctrl_inst|ds~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N27 +dffeas \seg_static_inst|seg[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr2~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[4] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N26 +cycloneive_lcell_comb \seg_static_inst|WideOr2~0 ( +// Equation(s): +// \seg_static_inst|WideOr2~0_combout = (\seg_static_inst|num [1] & (\seg_static_inst|num [0] & (!\seg_static_inst|num [3]))) # (!\seg_static_inst|num [1] & ((\seg_static_inst|num [2] & ((!\seg_static_inst|num [3]))) # (!\seg_static_inst|num [2] & +// (\seg_static_inst|num [0])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr2~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr2~0 .lut_mask = 16'h223A; +defparam \seg_static_inst|WideOr2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N3 +dffeas \seg_static_inst|cnt_wait[24] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [24]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[24] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[24] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N21 +dffeas \seg_static_inst|cnt_wait[23] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~44_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [23]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[23] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N24 +cycloneive_lcell_comb \seg_static_inst|Equal0~0 ( +// Equation(s): +// \seg_static_inst|Equal0~0_combout = (\hc595_ctrl_inst|cnt_4 [1] & (!\seg_static_inst|cnt_wait [23] & (\hc595_ctrl_inst|cnt_4 [0] & \seg_static_inst|cnt_wait [24]))) + + .dataa(\hc595_ctrl_inst|cnt_4 [1]), + .datab(\seg_static_inst|cnt_wait [23]), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(\seg_static_inst|cnt_wait [24]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~0 .lut_mask = 16'h2000; +defparam \seg_static_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N7 +dffeas \seg_static_inst|cnt_wait[22] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [22]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[22] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[22] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N25 +dffeas \seg_static_inst|cnt_wait[21] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [21]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[21] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[21] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N9 +dffeas \seg_static_inst|cnt_wait[20] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [20]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[20] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[20] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N27 +dffeas \seg_static_inst|cnt_wait[19] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [19]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[19] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N10 +cycloneive_lcell_comb \seg_static_inst|Equal0~1 ( +// Equation(s): +// \seg_static_inst|Equal0~1_combout = (\seg_static_inst|cnt_wait [22] & (\seg_static_inst|cnt_wait [20] & (\seg_static_inst|cnt_wait [19] & \seg_static_inst|cnt_wait [21]))) + + .dataa(\seg_static_inst|cnt_wait [22]), + .datab(\seg_static_inst|cnt_wait [20]), + .datac(\seg_static_inst|cnt_wait [19]), + .datad(\seg_static_inst|cnt_wait [21]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N29 +dffeas \seg_static_inst|cnt_wait[18] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [18]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[18] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[18] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N29 +dffeas \seg_static_inst|cnt_wait[16] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~6_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [16]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[16] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[16] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N9 +dffeas \seg_static_inst|cnt_wait[17] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~32_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [17]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[17] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[17] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N5 +dffeas \seg_static_inst|cnt_wait[15] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~28_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [15]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[15] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N18 +cycloneive_lcell_comb \seg_static_inst|Equal0~2 ( +// Equation(s): +// \seg_static_inst|Equal0~2_combout = (!\seg_static_inst|cnt_wait [17] & (\seg_static_inst|cnt_wait [16] & (!\seg_static_inst|cnt_wait [15] & \seg_static_inst|cnt_wait [18]))) + + .dataa(\seg_static_inst|cnt_wait [17]), + .datab(\seg_static_inst|cnt_wait [16]), + .datac(\seg_static_inst|cnt_wait [15]), + .datad(\seg_static_inst|cnt_wait [18]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~2 .lut_mask = 16'h0400; +defparam \seg_static_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N21 +dffeas \seg_static_inst|cnt_wait[14] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~7_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [14]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[14] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N31 +dffeas \seg_static_inst|cnt_wait[13] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~8_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [13]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[13] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N23 +dffeas \seg_static_inst|cnt_wait[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~9_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [12]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[12] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[12] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N1 +dffeas \seg_static_inst|cnt_wait[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~10_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [11]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[11] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N26 +cycloneive_lcell_comb \seg_static_inst|Equal0~3 ( +// Equation(s): +// \seg_static_inst|Equal0~3_combout = (\seg_static_inst|cnt_wait [11] & (\seg_static_inst|cnt_wait [14] & (\seg_static_inst|cnt_wait [12] & \seg_static_inst|cnt_wait [13]))) + + .dataa(\seg_static_inst|cnt_wait [11]), + .datab(\seg_static_inst|cnt_wait [14]), + .datac(\seg_static_inst|cnt_wait [12]), + .datad(\seg_static_inst|cnt_wait [13]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~3 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N12 +cycloneive_lcell_comb \seg_static_inst|Equal0~4 ( +// Equation(s): +// \seg_static_inst|Equal0~4_combout = (\seg_static_inst|Equal0~1_combout & (\seg_static_inst|Equal0~2_combout & (\seg_static_inst|Equal0~3_combout & \seg_static_inst|Equal0~0_combout ))) + + .dataa(\seg_static_inst|Equal0~1_combout ), + .datab(\seg_static_inst|Equal0~2_combout ), + .datac(\seg_static_inst|Equal0~3_combout ), + .datad(\seg_static_inst|Equal0~0_combout ), + .cin(gnd), + .combout(\seg_static_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~4 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N23 +dffeas \seg_static_inst|cnt_wait[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [8]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[8] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N13 +dffeas \seg_static_inst|cnt_wait[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [3]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[3] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N2 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~0 ( +// Equation(s): +// \seg_static_inst|cnt_wait~0_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~46_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~46_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~0 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N6 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~1 ( +// Equation(s): +// \seg_static_inst|cnt_wait~1_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~42_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~42_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~1_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~1 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N24 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~2 ( +// Equation(s): +// \seg_static_inst|cnt_wait~2_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~40_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~40_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~2_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~2 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N8 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~3 ( +// Equation(s): +// \seg_static_inst|cnt_wait~3_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~38_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~3_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~3 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N26 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~4 ( +// Equation(s): +// \seg_static_inst|cnt_wait~4_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~36_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~36_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~4_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~4 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N28 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~5 ( +// Equation(s): +// \seg_static_inst|cnt_wait~5_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~34_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~34_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~5_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~5 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N28 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~6 ( +// Equation(s): +// \seg_static_inst|cnt_wait~6_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~30_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~30_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~6_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~6 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N20 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~7 ( +// Equation(s): +// \seg_static_inst|cnt_wait~7_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~26_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~26_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~7_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~7 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N30 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~8 ( +// Equation(s): +// \seg_static_inst|cnt_wait~8_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~24_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~24_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~8_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~8 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N22 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~9 ( +// Equation(s): +// \seg_static_inst|cnt_wait~9_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~22_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~22_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~9_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~9 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N0 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~10 ( +// Equation(s): +// \seg_static_inst|cnt_wait~10_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~20_combout ) + + .dataa(gnd), + .datab(\seg_static_inst|Equal0~7_combout ), + .datac(\seg_static_inst|Add0~20_combout ), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~10_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~10 .lut_mask = 16'h3030; +defparam \seg_static_inst|cnt_wait~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y6_N9 +cycloneive_io_obuf \stcp~output ( + .i(\hc595_ctrl_inst|stcp~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\stcp~output_o ), + .obar()); +// synopsys translate_off +defparam \stcp~output .bus_hold = "false"; +defparam \stcp~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y7_N23 +cycloneive_io_obuf \shcp~output ( + .i(\hc595_ctrl_inst|shcp~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\shcp~output_o ), + .obar()); +// synopsys translate_off +defparam \shcp~output .bus_hold = "false"; +defparam \shcp~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y5_N16 +cycloneive_io_obuf \ds~output ( + .i(\hc595_ctrl_inst|ds~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\ds~output_o ), + .obar()); +// synopsys translate_off +defparam \ds~output .bus_hold = "false"; +defparam \ds~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y6_N2 +cycloneive_io_obuf \oe~output ( + .i(!\sys_rst_n~input_o ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\oe~output_o ), + .obar()); +// synopsys translate_off +defparam \oe~output .bus_hold = "false"; +defparam \oe~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \sys_clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sys_clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sys_clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \sys_clk~inputclkctrl .clock_type = "global clock"; +defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N6 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_4[0]~0 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_4[0]~0_combout = !\hc595_ctrl_inst|cnt_4 [0] + + .dataa(gnd), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(gnd), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_4[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_4[0]~0 .lut_mask = 16'h0F0F; +defparam \hc595_ctrl_inst|cnt_4[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X14_Y13_N7 +dffeas \hc595_ctrl_inst|cnt_4[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_4[0]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_4 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_4[0] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_4[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N14 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[0]~1 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[0]~1_combout = \hc595_ctrl_inst|cnt_bit [0] $ (((\hc595_ctrl_inst|cnt_4 [1] & \hc595_ctrl_inst|cnt_4 [0]))) + + .dataa(\hc595_ctrl_inst|cnt_4 [1]), + .datab(\hc595_ctrl_inst|cnt_4 [0]), + .datac(\hc595_ctrl_inst|cnt_bit [0]), + .datad(gnd), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[0]~1 .lut_mask = 16'h7878; +defparam \hc595_ctrl_inst|cnt_bit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N15 +dffeas \hc595_ctrl_inst|cnt_bit[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[0]~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[0] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N24 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[1]~0 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[1]~0_combout = (\hc595_ctrl_inst|Equal1~0_combout & (!\hc595_ctrl_inst|always2~1_combout & (\hc595_ctrl_inst|cnt_bit [0] $ (\hc595_ctrl_inst|cnt_bit [1])))) # (!\hc595_ctrl_inst|Equal1~0_combout & (((\hc595_ctrl_inst|cnt_bit +// [1])))) + + .dataa(\hc595_ctrl_inst|Equal1~0_combout ), + .datab(\hc595_ctrl_inst|cnt_bit [0]), + .datac(\hc595_ctrl_inst|cnt_bit [1]), + .datad(\hc595_ctrl_inst|always2~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[1]~0 .lut_mask = 16'h5078; +defparam \hc595_ctrl_inst|cnt_bit[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N25 +dffeas \hc595_ctrl_inst|cnt_bit[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[1]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[1] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N0 +cycloneive_lcell_comb \hc595_ctrl_inst|always2~0 ( +// Equation(s): +// \hc595_ctrl_inst|always2~0_combout = (\hc595_ctrl_inst|cnt_bit [0] & \hc595_ctrl_inst|cnt_bit [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_bit [0]), + .datad(\hc595_ctrl_inst|cnt_bit [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|always2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|always2~0 .lut_mask = 16'hF000; +defparam \hc595_ctrl_inst|always2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N8 +cycloneive_lcell_comb \seg_static_inst|Add0~0 ( +// Equation(s): +// \seg_static_inst|Add0~0_combout = (\hc595_ctrl_inst|cnt_4 [0] & (\hc595_ctrl_inst|cnt_4 [1] $ (VCC))) # (!\hc595_ctrl_inst|cnt_4 [0] & (\hc595_ctrl_inst|cnt_4 [1] & VCC)) +// \seg_static_inst|Add0~1 = CARRY((\hc595_ctrl_inst|cnt_4 [0] & \hc595_ctrl_inst|cnt_4 [1])) + + .dataa(\hc595_ctrl_inst|cnt_4 [0]), + .datab(\hc595_ctrl_inst|cnt_4 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\seg_static_inst|Add0~0_combout ), + .cout(\seg_static_inst|Add0~1 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~0 .lut_mask = 16'h6688; +defparam \seg_static_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N9 +dffeas \hc595_ctrl_inst|cnt_4[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_4 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_4[1] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_4[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N22 +cycloneive_lcell_comb \hc595_ctrl_inst|Equal1~0 ( +// Equation(s): +// \hc595_ctrl_inst|Equal1~0_combout = (\hc595_ctrl_inst|cnt_4 [0] & \hc595_ctrl_inst|cnt_4 [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(\hc595_ctrl_inst|cnt_4 [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Equal1~0 .lut_mask = 16'hF000; +defparam \hc595_ctrl_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N16 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[3]~2 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[3]~2_combout = (\hc595_ctrl_inst|always2~0_combout & ((\hc595_ctrl_inst|cnt_bit [3] & ((!\hc595_ctrl_inst|Equal1~0_combout ))) # (!\hc595_ctrl_inst|cnt_bit [3] & (\hc595_ctrl_inst|cnt_bit [2] & \hc595_ctrl_inst|Equal1~0_combout +// )))) # (!\hc595_ctrl_inst|always2~0_combout & (((\hc595_ctrl_inst|cnt_bit [3])))) + + .dataa(\hc595_ctrl_inst|cnt_bit [2]), + .datab(\hc595_ctrl_inst|always2~0_combout ), + .datac(\hc595_ctrl_inst|cnt_bit [3]), + .datad(\hc595_ctrl_inst|Equal1~0_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[3]~2 .lut_mask = 16'h38F0; +defparam \hc595_ctrl_inst|cnt_bit[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N17 +dffeas \hc595_ctrl_inst|cnt_bit[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[3]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[3] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N28 +cycloneive_lcell_comb \hc595_ctrl_inst|always2~1 ( +// Equation(s): +// \hc595_ctrl_inst|always2~1_combout = (!\hc595_ctrl_inst|cnt_bit [2] & (\hc595_ctrl_inst|cnt_bit [3] & (\hc595_ctrl_inst|Equal1~0_combout & \hc595_ctrl_inst|always2~0_combout ))) + + .dataa(\hc595_ctrl_inst|cnt_bit [2]), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|Equal1~0_combout ), + .datad(\hc595_ctrl_inst|always2~0_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|always2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|always2~1 .lut_mask = 16'h4000; +defparam \hc595_ctrl_inst|always2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N4 +cycloneive_lcell_comb \hc595_ctrl_inst|stcp~feeder ( +// Equation(s): +// \hc595_ctrl_inst|stcp~feeder_combout = \hc595_ctrl_inst|always2~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hc595_ctrl_inst|always2~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|stcp~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|stcp~feeder .lut_mask = 16'hFF00; +defparam \hc595_ctrl_inst|stcp~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N5 +dffeas \hc595_ctrl_inst|stcp ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|stcp~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|stcp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|stcp .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|stcp .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N19 +dffeas \hc595_ctrl_inst|shcp ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\hc595_ctrl_inst|cnt_4 [1]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|shcp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|shcp .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|shcp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N26 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[2]~3 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[2]~3_combout = (\hc595_ctrl_inst|Equal1~0_combout & ((\hc595_ctrl_inst|cnt_bit [2] & ((!\hc595_ctrl_inst|always2~0_combout ))) # (!\hc595_ctrl_inst|cnt_bit [2] & (!\hc595_ctrl_inst|cnt_bit [3] & +// \hc595_ctrl_inst|always2~0_combout )))) # (!\hc595_ctrl_inst|Equal1~0_combout & (((\hc595_ctrl_inst|cnt_bit [2])))) + + .dataa(\hc595_ctrl_inst|Equal1~0_combout ), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|cnt_bit [2]), + .datad(\hc595_ctrl_inst|always2~0_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[2]~3 .lut_mask = 16'h52F0; +defparam \hc595_ctrl_inst|cnt_bit[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N27 +dffeas \hc595_ctrl_inst|cnt_bit[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[2]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[2] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N10 +cycloneive_lcell_comb \seg_static_inst|Add0~2 ( +// Equation(s): +// \seg_static_inst|Add0~2_combout = (\seg_static_inst|cnt_wait [2] & (!\seg_static_inst|Add0~1 )) # (!\seg_static_inst|cnt_wait [2] & ((\seg_static_inst|Add0~1 ) # (GND))) +// \seg_static_inst|Add0~3 = CARRY((!\seg_static_inst|Add0~1 ) # (!\seg_static_inst|cnt_wait [2])) + + .dataa(\seg_static_inst|cnt_wait [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~1 ), + .combout(\seg_static_inst|Add0~2_combout ), + .cout(\seg_static_inst|Add0~3 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N11 +dffeas \seg_static_inst|cnt_wait[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [2]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[2] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N14 +cycloneive_lcell_comb \seg_static_inst|Add0~6 ( +// Equation(s): +// \seg_static_inst|Add0~6_combout = (\seg_static_inst|cnt_wait [4] & (!\seg_static_inst|Add0~5 )) # (!\seg_static_inst|cnt_wait [4] & ((\seg_static_inst|Add0~5 ) # (GND))) +// \seg_static_inst|Add0~7 = CARRY((!\seg_static_inst|Add0~5 ) # (!\seg_static_inst|cnt_wait [4])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [4]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~5 ), + .combout(\seg_static_inst|Add0~6_combout ), + .cout(\seg_static_inst|Add0~7 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N15 +dffeas \seg_static_inst|cnt_wait[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [4]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[4] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N16 +cycloneive_lcell_comb \seg_static_inst|Add0~8 ( +// Equation(s): +// \seg_static_inst|Add0~8_combout = (\seg_static_inst|cnt_wait [5] & (\seg_static_inst|Add0~7 $ (GND))) # (!\seg_static_inst|cnt_wait [5] & (!\seg_static_inst|Add0~7 & VCC)) +// \seg_static_inst|Add0~9 = CARRY((\seg_static_inst|cnt_wait [5] & !\seg_static_inst|Add0~7 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [5]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~7 ), + .combout(\seg_static_inst|Add0~8_combout ), + .cout(\seg_static_inst|Add0~9 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N17 +dffeas \seg_static_inst|cnt_wait[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [5]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[5] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N18 +cycloneive_lcell_comb \seg_static_inst|Add0~10 ( +// Equation(s): +// \seg_static_inst|Add0~10_combout = (\seg_static_inst|cnt_wait [6] & (!\seg_static_inst|Add0~9 )) # (!\seg_static_inst|cnt_wait [6] & ((\seg_static_inst|Add0~9 ) # (GND))) +// \seg_static_inst|Add0~11 = CARRY((!\seg_static_inst|Add0~9 ) # (!\seg_static_inst|cnt_wait [6])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [6]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~9 ), + .combout(\seg_static_inst|Add0~10_combout ), + .cout(\seg_static_inst|Add0~11 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~10 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N4 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~11 ( +// Equation(s): +// \seg_static_inst|cnt_wait~11_combout = (\seg_static_inst|Add0~10_combout & !\seg_static_inst|Equal0~7_combout ) + + .dataa(gnd), + .datab(\seg_static_inst|Add0~10_combout ), + .datac(gnd), + .datad(\seg_static_inst|Equal0~7_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~11_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~11 .lut_mask = 16'h00CC; +defparam \seg_static_inst|cnt_wait~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N5 +dffeas \seg_static_inst|cnt_wait[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~11_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [6]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[6] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N20 +cycloneive_lcell_comb \seg_static_inst|Add0~12 ( +// Equation(s): +// \seg_static_inst|Add0~12_combout = (\seg_static_inst|cnt_wait [7] & (\seg_static_inst|Add0~11 $ (GND))) # (!\seg_static_inst|cnt_wait [7] & (!\seg_static_inst|Add0~11 & VCC)) +// \seg_static_inst|Add0~13 = CARRY((\seg_static_inst|cnt_wait [7] & !\seg_static_inst|Add0~11 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [7]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~11 ), + .combout(\seg_static_inst|Add0~12_combout ), + .cout(\seg_static_inst|Add0~13 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N21 +dffeas \seg_static_inst|cnt_wait[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [7]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[7] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N24 +cycloneive_lcell_comb \seg_static_inst|Add0~16 ( +// Equation(s): +// \seg_static_inst|Add0~16_combout = (\seg_static_inst|cnt_wait [9] & (\seg_static_inst|Add0~15 $ (GND))) # (!\seg_static_inst|cnt_wait [9] & (!\seg_static_inst|Add0~15 & VCC)) +// \seg_static_inst|Add0~17 = CARRY((\seg_static_inst|cnt_wait [9] & !\seg_static_inst|Add0~15 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [9]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~15 ), + .combout(\seg_static_inst|Add0~16_combout ), + .cout(\seg_static_inst|Add0~17 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N25 +dffeas \seg_static_inst|cnt_wait[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~16_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [9]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[9] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N27 +dffeas \seg_static_inst|cnt_wait[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~18_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [10]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[10] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N0 +cycloneive_lcell_comb \seg_static_inst|Equal0~5 ( +// Equation(s): +// \seg_static_inst|Equal0~5_combout = (!\seg_static_inst|cnt_wait [8] & (!\seg_static_inst|cnt_wait [7] & (!\seg_static_inst|cnt_wait [10] & !\seg_static_inst|cnt_wait [9]))) + + .dataa(\seg_static_inst|cnt_wait [8]), + .datab(\seg_static_inst|cnt_wait [7]), + .datac(\seg_static_inst|cnt_wait [10]), + .datad(\seg_static_inst|cnt_wait [9]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~5_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~5 .lut_mask = 16'h0001; +defparam \seg_static_inst|Equal0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N2 +cycloneive_lcell_comb \seg_static_inst|Equal0~6 ( +// Equation(s): +// \seg_static_inst|Equal0~6_combout = (\seg_static_inst|cnt_wait [3] & (\seg_static_inst|cnt_wait [4] & (!\seg_static_inst|cnt_wait [6] & \seg_static_inst|cnt_wait [5]))) + + .dataa(\seg_static_inst|cnt_wait [3]), + .datab(\seg_static_inst|cnt_wait [4]), + .datac(\seg_static_inst|cnt_wait [6]), + .datad(\seg_static_inst|cnt_wait [5]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~6 .lut_mask = 16'h0800; +defparam \seg_static_inst|Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N14 +cycloneive_lcell_comb \seg_static_inst|Equal0~7 ( +// Equation(s): +// \seg_static_inst|Equal0~7_combout = (\seg_static_inst|Equal0~4_combout & (\seg_static_inst|cnt_wait [2] & (\seg_static_inst|Equal0~5_combout & \seg_static_inst|Equal0~6_combout ))) + + .dataa(\seg_static_inst|Equal0~4_combout ), + .datab(\seg_static_inst|cnt_wait [2]), + .datac(\seg_static_inst|Equal0~5_combout ), + .datad(\seg_static_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\seg_static_inst|Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~7 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N4 +cycloneive_lcell_comb \seg_static_inst|add_flag~feeder ( +// Equation(s): +// \seg_static_inst|add_flag~feeder_combout = \seg_static_inst|Equal0~7_combout + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|add_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|add_flag~feeder .lut_mask = 16'hF0F0; +defparam \seg_static_inst|add_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N5 +dffeas \seg_static_inst|add_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|add_flag~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|add_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|add_flag .is_wysiwyg = "true"; +defparam \seg_static_inst|add_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N10 +cycloneive_lcell_comb \seg_static_inst|num[0]~0 ( +// Equation(s): +// \seg_static_inst|num[0]~0_combout = \seg_static_inst|add_flag~q $ (\seg_static_inst|num [0]) + + .dataa(gnd), + .datab(\seg_static_inst|add_flag~q ), + .datac(\seg_static_inst|num [0]), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|num[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[0]~0 .lut_mask = 16'h3C3C; +defparam \seg_static_inst|num[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N11 +dffeas \seg_static_inst|num[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[0]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[0] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N0 +cycloneive_lcell_comb \seg_static_inst|num[1]~1 ( +// Equation(s): +// \seg_static_inst|num[1]~1_combout = \seg_static_inst|num [1] $ (((\seg_static_inst|add_flag~q & \seg_static_inst|num [0]))) + + .dataa(gnd), + .datab(\seg_static_inst|add_flag~q ), + .datac(\seg_static_inst|num [1]), + .datad(\seg_static_inst|num [0]), + .cin(gnd), + .combout(\seg_static_inst|num[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[1]~1 .lut_mask = 16'h3CF0; +defparam \seg_static_inst|num[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N1 +dffeas \seg_static_inst|num[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[1]~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[1] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N14 +cycloneive_lcell_comb \seg_static_inst|num[2]~2 ( +// Equation(s): +// \seg_static_inst|num[2]~2_combout = \seg_static_inst|num [2] $ (((\seg_static_inst|num [0] & (\seg_static_inst|add_flag~q & \seg_static_inst|num [1])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|add_flag~q ), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|num[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[2]~2 .lut_mask = 16'h78F0; +defparam \seg_static_inst|num[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N15 +dffeas \seg_static_inst|num[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[2]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[2] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N18 +cycloneive_lcell_comb \seg_static_inst|num[3]~3 ( +// Equation(s): +// \seg_static_inst|num[3]~3_combout = (\seg_static_inst|num [0] & (\seg_static_inst|num [2] & (\seg_static_inst|add_flag~q & \seg_static_inst|num [1]))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [2]), + .datac(\seg_static_inst|add_flag~q ), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|num[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[3]~3 .lut_mask = 16'h8000; +defparam \seg_static_inst|num[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N16 +cycloneive_lcell_comb \seg_static_inst|num[3]~4 ( +// Equation(s): +// \seg_static_inst|num[3]~4_combout = \seg_static_inst|num [3] $ (\seg_static_inst|num[3]~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|num [3]), + .datad(\seg_static_inst|num[3]~3_combout ), + .cin(gnd), + .combout(\seg_static_inst|num[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[3]~4 .lut_mask = 16'h0FF0; +defparam \seg_static_inst|num[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N17 +dffeas \seg_static_inst|num[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[3]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[3] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N8 +cycloneive_lcell_comb \seg_static_inst|WideOr1~0 ( +// Equation(s): +// \seg_static_inst|WideOr1~0_combout = (\seg_static_inst|num [0] & (\seg_static_inst|num [3] $ (((\seg_static_inst|num [1]) # (!\seg_static_inst|num [2]))))) # (!\seg_static_inst|num [0] & (!\seg_static_inst|num [3] & (!\seg_static_inst|num [2] & +// \seg_static_inst|num [1]))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr1~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr1~0 .lut_mask = 16'h2382; +defparam \seg_static_inst|WideOr1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N9 +dffeas \seg_static_inst|seg[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr1~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[5] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N6 +cycloneive_lcell_comb \seg_static_inst|seg[7]~feeder ( +// Equation(s): +// \seg_static_inst|seg[7]~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|seg[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|seg[7]~feeder .lut_mask = 16'hFFFF; +defparam \seg_static_inst|seg[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N7 +dffeas \seg_static_inst|seg[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|seg[7]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[7] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N22 +cycloneive_lcell_comb \seg_static_inst|WideOr0~0 ( +// Equation(s): +// \seg_static_inst|WideOr0~0_combout = (\seg_static_inst|num [0] & (!\seg_static_inst|num [3] & (\seg_static_inst|num [2] $ (!\seg_static_inst|num [1])))) # (!\seg_static_inst|num [0] & (!\seg_static_inst|num [1] & (\seg_static_inst|num [3] $ +// (!\seg_static_inst|num [2])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr0~0 .lut_mask = 16'h2043; +defparam \seg_static_inst|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N23 +dffeas \seg_static_inst|seg[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr0~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[6] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N12 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~2 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~2_combout = (\hc595_ctrl_inst|cnt_bit [0] & (((\hc595_ctrl_inst|cnt_bit [1]) # (!\seg_static_inst|seg [6])))) # (!\hc595_ctrl_inst|cnt_bit [0] & (!\seg_static_inst|seg [7] & ((!\hc595_ctrl_inst|cnt_bit [1])))) + + .dataa(\hc595_ctrl_inst|cnt_bit [0]), + .datab(\seg_static_inst|seg [7]), + .datac(\seg_static_inst|seg [6]), + .datad(\hc595_ctrl_inst|cnt_bit [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~2_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~2 .lut_mask = 16'hAA1B; +defparam \hc595_ctrl_inst|Mux0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N24 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~3 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~3_combout = (\hc595_ctrl_inst|cnt_bit [1] & ((\hc595_ctrl_inst|Mux0~2_combout & (!\seg_static_inst|seg [4])) # (!\hc595_ctrl_inst|Mux0~2_combout & ((!\seg_static_inst|seg [5]))))) # (!\hc595_ctrl_inst|cnt_bit [1] & +// (((\hc595_ctrl_inst|Mux0~2_combout )))) + + .dataa(\seg_static_inst|seg [4]), + .datab(\hc595_ctrl_inst|cnt_bit [1]), + .datac(\seg_static_inst|seg [5]), + .datad(\hc595_ctrl_inst|Mux0~2_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~3_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~3 .lut_mask = 16'h770C; +defparam \hc595_ctrl_inst|Mux0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N20 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~2 ( +// Equation(s): +// \hc595_ctrl_inst|ds~2_combout = (!\hc595_ctrl_inst|cnt_bit [3] & ((\hc595_ctrl_inst|cnt_bit [2] & ((\hc595_ctrl_inst|Mux0~3_combout ))) # (!\hc595_ctrl_inst|cnt_bit [2] & (!\seg_static_inst|seg [7])))) + + .dataa(\seg_static_inst|seg [7]), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|cnt_bit [2]), + .datad(\hc595_ctrl_inst|Mux0~3_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~2_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~2 .lut_mask = 16'h3101; +defparam \hc595_ctrl_inst|ds~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N20 +cycloneive_lcell_comb \seg_static_inst|WideOr4~0 ( +// Equation(s): +// \seg_static_inst|WideOr4~0_combout = (\seg_static_inst|num [3] & (\seg_static_inst|num [2] & ((\seg_static_inst|num [1]) # (!\seg_static_inst|num [0])))) # (!\seg_static_inst|num [3] & (!\seg_static_inst|num [0] & (!\seg_static_inst|num [2] & +// \seg_static_inst|num [1]))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr4~0 .lut_mask = 16'hC140; +defparam \seg_static_inst|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N21 +dffeas \seg_static_inst|seg[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr4~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[2] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N4 +cycloneive_lcell_comb \seg_static_inst|WideOr3~0 ( +// Equation(s): +// \seg_static_inst|WideOr3~0_combout = (\seg_static_inst|num [1] & ((\seg_static_inst|num [0] & ((\seg_static_inst|num [2]))) # (!\seg_static_inst|num [0] & (\seg_static_inst|num [3] & !\seg_static_inst|num [2])))) # (!\seg_static_inst|num [1] & +// (!\seg_static_inst|num [3] & (\seg_static_inst|num [0] $ (\seg_static_inst|num [2])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr3~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr3~0 .lut_mask = 16'hA412; +defparam \seg_static_inst|WideOr3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N5 +dffeas \seg_static_inst|seg[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr3~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[3] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N2 +cycloneive_lcell_comb \seg_static_inst|WideOr5~0 ( +// Equation(s): +// \seg_static_inst|WideOr5~0_combout = (\seg_static_inst|num [3] & ((\seg_static_inst|num [0] & ((\seg_static_inst|num [1]))) # (!\seg_static_inst|num [0] & (\seg_static_inst|num [2])))) # (!\seg_static_inst|num [3] & (\seg_static_inst|num [2] & +// (\seg_static_inst|num [0] $ (\seg_static_inst|num [1])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr5~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr5~0 .lut_mask = 16'hD860; +defparam \seg_static_inst|WideOr5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N3 +dffeas \seg_static_inst|seg[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr5~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[1] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N30 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~0 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~0_combout = (\hc595_ctrl_inst|cnt_bit [0] & (\hc595_ctrl_inst|cnt_bit [1])) # (!\hc595_ctrl_inst|cnt_bit [0] & ((\hc595_ctrl_inst|cnt_bit [1] & ((!\seg_static_inst|seg [1]))) # (!\hc595_ctrl_inst|cnt_bit [1] & (!\seg_static_inst|seg +// [3])))) + + .dataa(\hc595_ctrl_inst|cnt_bit [0]), + .datab(\hc595_ctrl_inst|cnt_bit [1]), + .datac(\seg_static_inst|seg [3]), + .datad(\seg_static_inst|seg [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~0 .lut_mask = 16'h89CD; +defparam \hc595_ctrl_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N28 +cycloneive_lcell_comb \seg_static_inst|WideOr6~0 ( +// Equation(s): +// \seg_static_inst|WideOr6~0_combout = (\seg_static_inst|num [3] & (\seg_static_inst|num [0] & (\seg_static_inst|num [2] $ (\seg_static_inst|num [1])))) # (!\seg_static_inst|num [3] & (!\seg_static_inst|num [1] & (\seg_static_inst|num [0] $ +// (\seg_static_inst|num [2])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr6~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr6~0 .lut_mask = 16'h0892; +defparam \seg_static_inst|WideOr6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N29 +dffeas \seg_static_inst|seg[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr6~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[0] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N6 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~1 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~1_combout = (\hc595_ctrl_inst|cnt_bit [0] & ((\hc595_ctrl_inst|Mux0~0_combout & ((!\seg_static_inst|seg [0]))) # (!\hc595_ctrl_inst|Mux0~0_combout & (!\seg_static_inst|seg [2])))) # (!\hc595_ctrl_inst|cnt_bit [0] & +// (((\hc595_ctrl_inst|Mux0~0_combout )))) + + .dataa(\hc595_ctrl_inst|cnt_bit [0]), + .datab(\seg_static_inst|seg [2]), + .datac(\hc595_ctrl_inst|Mux0~0_combout ), + .datad(\seg_static_inst|seg [0]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~1 .lut_mask = 16'h52F2; +defparam \hc595_ctrl_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N12 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~1 ( +// Equation(s): +// \hc595_ctrl_inst|ds~1_combout = (\hc595_ctrl_inst|cnt_bit [3] & (!\hc595_ctrl_inst|cnt_bit [2] & \hc595_ctrl_inst|Mux0~1_combout )) + + .dataa(gnd), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|cnt_bit [2]), + .datad(\hc595_ctrl_inst|Mux0~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~1 .lut_mask = 16'h0C00; +defparam \hc595_ctrl_inst|ds~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N30 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~3 ( +// Equation(s): +// \hc595_ctrl_inst|ds~3_combout = (\hc595_ctrl_inst|ds~0_combout & ((\hc595_ctrl_inst|ds~2_combout ) # ((\hc595_ctrl_inst|ds~1_combout )))) # (!\hc595_ctrl_inst|ds~0_combout & (((\hc595_ctrl_inst|ds~q )))) + + .dataa(\hc595_ctrl_inst|ds~0_combout ), + .datab(\hc595_ctrl_inst|ds~2_combout ), + .datac(\hc595_ctrl_inst|ds~q ), + .datad(\hc595_ctrl_inst|ds~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~3_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~3 .lut_mask = 16'hFAD8; +defparam \hc595_ctrl_inst|ds~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N31 +dffeas \hc595_ctrl_inst|ds ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|ds~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|ds~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|ds .power_up = "low"; +// synopsys translate_on + +assign stcp = \stcp~output_o ; + +assign shcp = \shcp~output_o ; + +assign ds = \ds~output_o ; + +assign oe = \oe~output_o ; + +endmodule diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_8_1200mv_85c_v_slow.sdo b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_8_1200mv_85c_v_slow.sdo new file mode 100644 index 0000000..7f4cf64 --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_8_1200mv_85c_v_slow.sdo @@ -0,0 +1,1858 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "seg_595_static") + (DATE "06/02/2023 20:55:14") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (433:433:433)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (432:432:432)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (429:429:429)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~20) + (DELAY + (ABSOLUTE + (PORT datab (940:940:940) (921:921:921)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~22) + (DELAY + (ABSOLUTE + (PORT datab (984:984:984) (971:971:971)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~24) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (450:450:450)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~26) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (611:611:611)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~28) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~30) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~32) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~34) + (DELAY + (ABSOLUTE + (PORT datab (572:572:572) (603:603:603)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~36) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~38) + (DELAY + (ABSOLUTE + (PORT datab (628:628:628) (632:632:632)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~40) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~42) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (611:611:611)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~44) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~46) + (DELAY + (ABSOLUTE + (PORT datad (539:539:539) (559:559:559)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~0) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (647:647:647)) + (PORT datac (558:558:558) (595:595:595)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (560:560:560)) + (PORT datab (386:386:386) (503:503:503)) + (PORT datac (352:352:352) (467:467:467)) + (PORT datad (369:369:369) (466:466:466)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[24\]) + (DELAY + (ABSOLUTE + (PORT clk (2328:2328:2328) (2322:2322:2322)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5733:5733:5733) (5447:5447:5447)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (939:939:939)) + (PORT datab (615:615:615) (619:619:619)) + (PORT datac (876:876:876) (872:872:872)) + (PORT datad (322:322:322) (392:392:392)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5733:5733:5733) (5447:5447:5447)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5733:5733:5733) (5447:5447:5447)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (PORT datab (359:359:359) (436:436:436)) + (PORT datac (564:564:564) (579:579:579)) + (PORT datad (556:556:556) (569:569:569)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5733:5733:5733) (5447:5447:5447)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5733:5733:5733) (5447:5447:5447)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5733:5733:5733) (5447:5447:5447)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (595:595:595)) + (PORT datab (613:613:613) (617:617:617)) + (PORT datac (516:516:516) (547:547:547)) + (PORT datad (319:319:319) (389:389:389)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5733:5733:5733) (5447:5447:5447)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (642:642:642)) + (PORT datab (360:360:360) (436:436:436)) + (PORT datac (319:319:319) (396:396:396)) + (PORT datad (516:516:516) (534:534:534)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~0) + (DELAY + (ABSOLUTE + (PORT datac (319:319:319) (381:381:381)) + (PORT datad (438:438:438) (415:415:415)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~1) + (DELAY + (ABSOLUTE + (PORT datac (319:319:319) (381:381:381)) + (PORT datad (437:437:437) (414:414:414)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~2) + (DELAY + (ABSOLUTE + (PORT datac (554:554:554) (540:540:540)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~3) + (DELAY + (ABSOLUTE + (PORT datac (319:319:319) (381:381:381)) + (PORT datad (447:447:447) (410:410:410)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~4) + (DELAY + (ABSOLUTE + (PORT datac (554:554:554) (541:541:541)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~5) + (DELAY + (ABSOLUTE + (PORT datac (319:319:319) (383:383:383)) + (PORT datad (469:469:469) (437:437:437)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~6) + (DELAY + (ABSOLUTE + (PORT datac (554:554:554) (541:541:541)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~7) + (DELAY + (ABSOLUTE + (PORT datac (319:319:319) (381:381:381)) + (PORT datad (468:468:468) (435:435:435)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~8) + (DELAY + (ABSOLUTE + (PORT datac (555:555:555) (541:541:541)) + (PORT datad (241:241:241) (260:260:260)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~9) + (DELAY + (ABSOLUTE + (PORT datac (319:319:319) (381:381:381)) + (PORT datad (739:739:739) (665:665:665)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~10) + (DELAY + (ABSOLUTE + (PORT datab (365:365:365) (423:423:423)) + (PORT datac (829:829:829) (765:765:765)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE stcp\~output) + (DELAY + (ABSOLUTE + (PORT i (1656:1656:1656) (1618:1618:1618)) + (IOPATH i o (3449:3449:3449) (3386:3386:3386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE shcp\~output) + (DELAY + (ABSOLUTE + (PORT i (1872:1872:1872) (1788:1788:1788)) + (IOPATH i o (3429:3429:3429) (3366:3366:3366)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE ds\~output) + (DELAY + (ABSOLUTE + (PORT i (2238:2238:2238) (2101:2101:2101)) + (IOPATH i o (3439:3439:3439) (3376:3376:3376)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE oe\~output) + (DELAY + (ABSOLUTE + (PORT i (4546:4546:4546) (4318:4318:4318)) + (IOPATH i o (3376:3376:3376) (3439:3439:3439)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (806:806:806) (852:852:852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sys_clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (200:200:200) (189:189:189)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_4\[0\]\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_4\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (649:649:649)) + (PORT datab (602:602:602) (636:636:636)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5984:5984:5984) (5729:5729:5729)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (367:367:367)) + (PORT datab (371:371:371) (453:453:453)) + (PORT datad (245:245:245) (266:266:266)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5984:5984:5984) (5729:5729:5729)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|always2\~0) + (DELAY + (ABSOLUTE + (PORT datac (328:328:328) (413:413:413)) + (PORT datad (323:323:323) (394:394:394)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (444:444:444)) + (PORT datab (358:358:358) (435:435:435)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_4\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT datac (560:560:560) (597:597:597)) + (PORT datad (556:556:556) (596:596:596)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (464:464:464)) + (PORT datab (298:298:298) (330:330:330)) + (PORT datad (467:467:467) (441:441:441)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5984:5984:5984) (5729:5729:5729)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|always2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (460:460:460)) + (PORT datab (361:361:361) (457:457:457)) + (PORT datac (281:281:281) (320:320:320)) + (PORT datad (259:259:259) (289:289:289)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|stcp\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (248:248:248) (270:270:270)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|stcp) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5984:5984:5984) (5729:5729:5729)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|shcp) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT asdata (1335:1335:1335) (1325:1325:1325)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (367:367:367)) + (PORT datab (362:362:362) (458:458:458)) + (PORT datad (259:259:259) (289:289:289)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5984:5984:5984) (5729:5729:5729)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (444:444:444)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (420:420:420)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~11) + (DELAY + (ABSOLUTE + (PORT datab (279:279:279) (304:304:304)) + (PORT datad (833:833:833) (788:788:788)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (419:419:419)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (343:343:343) (425:425:425)) + (PORT datac (304:304:304) (388:388:388)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (299:299:299) (383:383:383)) + (PORT datad (303:303:303) (379:379:379)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (1288:1288:1288) (1220:1220:1220)) + (PORT datac (1102:1102:1102) (999:999:999)) + (PORT datad (1098:1098:1098) (983:983:983)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|add_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (319:319:319) (381:381:381)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|add_flag) + (DELAY + (ABSOLUTE + (PORT clk (2328:2328:2328) (2322:2322:2322)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (968:968:968) (969:969:969)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (968:968:968) (969:969:969)) + (PORT datad (368:368:368) (496:496:496)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (558:558:558)) + (PORT datab (969:969:969) (970:970:970)) + (PORT datad (363:363:363) (460:460:460)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (558:558:558)) + (PORT datab (396:396:396) (508:508:508)) + (PORT datac (926:926:926) (932:932:932)) + (PORT datad (365:365:365) (462:462:462)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT datad (239:239:239) (257:257:257)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (556:556:556)) + (PORT datab (387:387:387) (504:504:504)) + (PORT datac (351:351:351) (465:465:465)) + (PORT datad (361:361:361) (457:457:457)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5984:5984:5984) (5729:5729:5729)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (559:559:559)) + (PORT datab (386:386:386) (504:504:504)) + (PORT datac (352:352:352) (467:467:467)) + (PORT datad (368:368:368) (464:464:464)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (631:631:631)) + (PORT datab (571:571:571) (592:592:592)) + (PORT datac (294:294:294) (371:371:371)) + (PORT datad (574:574:574) (597:597:597)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (419:419:419)) + (PORT datab (633:633:633) (644:644:644)) + (PORT datac (295:295:295) (373:373:373)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~2) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (449:449:449)) + (PORT datab (360:360:360) (456:456:456)) + (PORT datac (318:318:318) (414:414:414)) + (PORT datad (481:481:481) (449:449:449)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (559:559:559)) + (PORT datab (386:386:386) (504:504:504)) + (PORT datac (352:352:352) (467:467:467)) + (PORT datad (367:367:367) (463:463:463)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (555:555:555)) + (PORT datab (387:387:387) (505:505:505)) + (PORT datac (351:351:351) (465:465:465)) + (PORT datad (359:359:359) (455:455:455)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (555:555:555)) + (PORT datab (387:387:387) (505:505:505)) + (PORT datac (350:350:350) (465:465:465)) + (PORT datad (358:358:358) (454:454:454)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (632:632:632)) + (PORT datab (632:632:632) (643:643:643)) + (PORT datac (296:296:296) (374:374:374)) + (PORT datad (297:297:297) (368:368:368)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (419:419:419) (561:561:561)) + (PORT datab (386:386:386) (503:503:503)) + (PORT datac (352:352:352) (467:467:467)) + (PORT datad (370:370:370) (467:467:467)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (631:631:631)) + (PORT datab (335:335:335) (412:412:412)) + (PORT datac (239:239:239) (265:265:265)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~1) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (456:456:456)) + (PORT datac (320:320:320) (417:417:417)) + (PORT datad (450:450:450) (428:428:428)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~3) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (315:315:315)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datad (240:240:240) (258:258:258)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|ds) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5984:5984:5984) (5729:5729:5729)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_min_1200mv_0c_fast.vo b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_min_1200mv_0c_fast.vo new file mode 100644 index 0000000..2a5affc --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_min_1200mv_0c_fast.vo @@ -0,0 +1,2444 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 20:55:14" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module seg_595_static ( + sys_clk, + sys_rst_n, + stcp, + shcp, + ds, + oe); +input sys_clk; +input sys_rst_n; +output stcp; +output shcp; +output ds; +output oe; + +// Design Ports Information +// stcp => Location: PIN_Y1, I/O Standard: 2.5 V, Current Strength: Default +// shcp => Location: PIN_W1, I/O Standard: 2.5 V, Current Strength: Default +// ds => Location: PIN_AA1, I/O Standard: 2.5 V, Current Strength: Default +// oe => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("seg_595_static_min_1200mv_0c_v_fast.sdo"); +// synopsys translate_on + +wire \seg_static_inst|Add0~4_combout ; +wire \seg_static_inst|Add0~14_combout ; +wire \seg_static_inst|Add0~19 ; +wire \seg_static_inst|Add0~20_combout ; +wire \seg_static_inst|Add0~21 ; +wire \seg_static_inst|Add0~22_combout ; +wire \seg_static_inst|Add0~23 ; +wire \seg_static_inst|Add0~24_combout ; +wire \seg_static_inst|Add0~25 ; +wire \seg_static_inst|Add0~26_combout ; +wire \seg_static_inst|Add0~27 ; +wire \seg_static_inst|Add0~28_combout ; +wire \seg_static_inst|Add0~29 ; +wire \seg_static_inst|Add0~30_combout ; +wire \seg_static_inst|Add0~31 ; +wire \seg_static_inst|Add0~32_combout ; +wire \seg_static_inst|Add0~33 ; +wire \seg_static_inst|Add0~34_combout ; +wire \seg_static_inst|Add0~35 ; +wire \seg_static_inst|Add0~36_combout ; +wire \seg_static_inst|Add0~37 ; +wire \seg_static_inst|Add0~38_combout ; +wire \seg_static_inst|Add0~39 ; +wire \seg_static_inst|Add0~40_combout ; +wire \seg_static_inst|Add0~41 ; +wire \seg_static_inst|Add0~42_combout ; +wire \seg_static_inst|Add0~43 ; +wire \seg_static_inst|Add0~44_combout ; +wire \seg_static_inst|Add0~45 ; +wire \seg_static_inst|Add0~46_combout ; +wire \hc595_ctrl_inst|ds~0_combout ; +wire \seg_static_inst|WideOr2~0_combout ; +wire \seg_static_inst|Equal0~0_combout ; +wire \seg_static_inst|Equal0~1_combout ; +wire \seg_static_inst|Equal0~2_combout ; +wire \seg_static_inst|Equal0~3_combout ; +wire \seg_static_inst|Equal0~4_combout ; +wire \seg_static_inst|cnt_wait~0_combout ; +wire \seg_static_inst|cnt_wait~1_combout ; +wire \seg_static_inst|cnt_wait~2_combout ; +wire \seg_static_inst|cnt_wait~3_combout ; +wire \seg_static_inst|cnt_wait~4_combout ; +wire \seg_static_inst|cnt_wait~5_combout ; +wire \seg_static_inst|cnt_wait~6_combout ; +wire \seg_static_inst|cnt_wait~7_combout ; +wire \seg_static_inst|cnt_wait~8_combout ; +wire \seg_static_inst|cnt_wait~9_combout ; +wire \seg_static_inst|cnt_wait~10_combout ; +wire \stcp~output_o ; +wire \shcp~output_o ; +wire \ds~output_o ; +wire \oe~output_o ; +wire \sys_clk~input_o ; +wire \sys_clk~inputclkctrl_outclk ; +wire \hc595_ctrl_inst|cnt_4[0]~0_combout ; +wire \sys_rst_n~input_o ; +wire \hc595_ctrl_inst|cnt_bit[0]~1_combout ; +wire \hc595_ctrl_inst|cnt_bit[1]~0_combout ; +wire \hc595_ctrl_inst|always2~0_combout ; +wire \seg_static_inst|Add0~0_combout ; +wire \hc595_ctrl_inst|Equal1~0_combout ; +wire \hc595_ctrl_inst|cnt_bit[3]~2_combout ; +wire \hc595_ctrl_inst|always2~1_combout ; +wire \hc595_ctrl_inst|stcp~feeder_combout ; +wire \hc595_ctrl_inst|stcp~q ; +wire \hc595_ctrl_inst|shcp~q ; +wire \hc595_ctrl_inst|cnt_bit[2]~3_combout ; +wire \seg_static_inst|Add0~1 ; +wire \seg_static_inst|Add0~2_combout ; +wire \seg_static_inst|Add0~3 ; +wire \seg_static_inst|Add0~5 ; +wire \seg_static_inst|Add0~6_combout ; +wire \seg_static_inst|Add0~7 ; +wire \seg_static_inst|Add0~8_combout ; +wire \seg_static_inst|Add0~9 ; +wire \seg_static_inst|Add0~10_combout ; +wire \seg_static_inst|cnt_wait~11_combout ; +wire \seg_static_inst|Add0~11 ; +wire \seg_static_inst|Add0~12_combout ; +wire \seg_static_inst|Add0~13 ; +wire \seg_static_inst|Add0~15 ; +wire \seg_static_inst|Add0~16_combout ; +wire \seg_static_inst|Add0~17 ; +wire \seg_static_inst|Add0~18_combout ; +wire \seg_static_inst|Equal0~5_combout ; +wire \seg_static_inst|Equal0~6_combout ; +wire \seg_static_inst|Equal0~7_combout ; +wire \seg_static_inst|add_flag~feeder_combout ; +wire \seg_static_inst|add_flag~q ; +wire \seg_static_inst|num[0]~0_combout ; +wire \seg_static_inst|num[1]~1_combout ; +wire \seg_static_inst|num[2]~2_combout ; +wire \seg_static_inst|num[3]~3_combout ; +wire \seg_static_inst|num[3]~4_combout ; +wire \seg_static_inst|WideOr1~0_combout ; +wire \seg_static_inst|seg[7]~feeder_combout ; +wire \seg_static_inst|WideOr0~0_combout ; +wire \hc595_ctrl_inst|Mux0~2_combout ; +wire \hc595_ctrl_inst|Mux0~3_combout ; +wire \hc595_ctrl_inst|ds~2_combout ; +wire \seg_static_inst|WideOr4~0_combout ; +wire \seg_static_inst|WideOr3~0_combout ; +wire \seg_static_inst|WideOr5~0_combout ; +wire \hc595_ctrl_inst|Mux0~0_combout ; +wire \seg_static_inst|WideOr6~0_combout ; +wire \hc595_ctrl_inst|Mux0~1_combout ; +wire \hc595_ctrl_inst|ds~1_combout ; +wire \hc595_ctrl_inst|ds~3_combout ; +wire \hc595_ctrl_inst|ds~q ; +wire [7:0] \seg_static_inst|seg ; +wire [3:0] \seg_static_inst|num ; +wire [24:0] \seg_static_inst|cnt_wait ; +wire [3:0] \hc595_ctrl_inst|cnt_bit ; +wire [1:0] \hc595_ctrl_inst|cnt_4 ; + + +// Location: LCCOMB_X14_Y13_N12 +cycloneive_lcell_comb \seg_static_inst|Add0~4 ( +// Equation(s): +// \seg_static_inst|Add0~4_combout = (\seg_static_inst|cnt_wait [3] & (\seg_static_inst|Add0~3 $ (GND))) # (!\seg_static_inst|cnt_wait [3] & (!\seg_static_inst|Add0~3 & VCC)) +// \seg_static_inst|Add0~5 = CARRY((\seg_static_inst|cnt_wait [3] & !\seg_static_inst|Add0~3 )) + + .dataa(\seg_static_inst|cnt_wait [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~3 ), + .combout(\seg_static_inst|Add0~4_combout ), + .cout(\seg_static_inst|Add0~5 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \seg_static_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N22 +cycloneive_lcell_comb \seg_static_inst|Add0~14 ( +// Equation(s): +// \seg_static_inst|Add0~14_combout = (\seg_static_inst|cnt_wait [8] & (!\seg_static_inst|Add0~13 )) # (!\seg_static_inst|cnt_wait [8] & ((\seg_static_inst|Add0~13 ) # (GND))) +// \seg_static_inst|Add0~15 = CARRY((!\seg_static_inst|Add0~13 ) # (!\seg_static_inst|cnt_wait [8])) + + .dataa(\seg_static_inst|cnt_wait [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~13 ), + .combout(\seg_static_inst|Add0~14_combout ), + .cout(\seg_static_inst|Add0~15 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N26 +cycloneive_lcell_comb \seg_static_inst|Add0~18 ( +// Equation(s): +// \seg_static_inst|Add0~18_combout = (\seg_static_inst|cnt_wait [10] & (!\seg_static_inst|Add0~17 )) # (!\seg_static_inst|cnt_wait [10] & ((\seg_static_inst|Add0~17 ) # (GND))) +// \seg_static_inst|Add0~19 = CARRY((!\seg_static_inst|Add0~17 ) # (!\seg_static_inst|cnt_wait [10])) + + .dataa(\seg_static_inst|cnt_wait [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~17 ), + .combout(\seg_static_inst|Add0~18_combout ), + .cout(\seg_static_inst|Add0~19 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~18 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N28 +cycloneive_lcell_comb \seg_static_inst|Add0~20 ( +// Equation(s): +// \seg_static_inst|Add0~20_combout = (\seg_static_inst|cnt_wait [11] & (\seg_static_inst|Add0~19 $ (GND))) # (!\seg_static_inst|cnt_wait [11] & (!\seg_static_inst|Add0~19 & VCC)) +// \seg_static_inst|Add0~21 = CARRY((\seg_static_inst|cnt_wait [11] & !\seg_static_inst|Add0~19 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [11]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~19 ), + .combout(\seg_static_inst|Add0~20_combout ), + .cout(\seg_static_inst|Add0~21 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~20 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N30 +cycloneive_lcell_comb \seg_static_inst|Add0~22 ( +// Equation(s): +// \seg_static_inst|Add0~22_combout = (\seg_static_inst|cnt_wait [12] & (!\seg_static_inst|Add0~21 )) # (!\seg_static_inst|cnt_wait [12] & ((\seg_static_inst|Add0~21 ) # (GND))) +// \seg_static_inst|Add0~23 = CARRY((!\seg_static_inst|Add0~21 ) # (!\seg_static_inst|cnt_wait [12])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [12]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~21 ), + .combout(\seg_static_inst|Add0~22_combout ), + .cout(\seg_static_inst|Add0~23 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~22 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N0 +cycloneive_lcell_comb \seg_static_inst|Add0~24 ( +// Equation(s): +// \seg_static_inst|Add0~24_combout = (\seg_static_inst|cnt_wait [13] & (\seg_static_inst|Add0~23 $ (GND))) # (!\seg_static_inst|cnt_wait [13] & (!\seg_static_inst|Add0~23 & VCC)) +// \seg_static_inst|Add0~25 = CARRY((\seg_static_inst|cnt_wait [13] & !\seg_static_inst|Add0~23 )) + + .dataa(\seg_static_inst|cnt_wait [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~23 ), + .combout(\seg_static_inst|Add0~24_combout ), + .cout(\seg_static_inst|Add0~25 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~24 .lut_mask = 16'hA50A; +defparam \seg_static_inst|Add0~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N2 +cycloneive_lcell_comb \seg_static_inst|Add0~26 ( +// Equation(s): +// \seg_static_inst|Add0~26_combout = (\seg_static_inst|cnt_wait [14] & (!\seg_static_inst|Add0~25 )) # (!\seg_static_inst|cnt_wait [14] & ((\seg_static_inst|Add0~25 ) # (GND))) +// \seg_static_inst|Add0~27 = CARRY((!\seg_static_inst|Add0~25 ) # (!\seg_static_inst|cnt_wait [14])) + + .dataa(\seg_static_inst|cnt_wait [14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~25 ), + .combout(\seg_static_inst|Add0~26_combout ), + .cout(\seg_static_inst|Add0~27 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~26 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N4 +cycloneive_lcell_comb \seg_static_inst|Add0~28 ( +// Equation(s): +// \seg_static_inst|Add0~28_combout = (\seg_static_inst|cnt_wait [15] & (\seg_static_inst|Add0~27 $ (GND))) # (!\seg_static_inst|cnt_wait [15] & (!\seg_static_inst|Add0~27 & VCC)) +// \seg_static_inst|Add0~29 = CARRY((\seg_static_inst|cnt_wait [15] & !\seg_static_inst|Add0~27 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [15]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~27 ), + .combout(\seg_static_inst|Add0~28_combout ), + .cout(\seg_static_inst|Add0~29 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~28 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N6 +cycloneive_lcell_comb \seg_static_inst|Add0~30 ( +// Equation(s): +// \seg_static_inst|Add0~30_combout = (\seg_static_inst|cnt_wait [16] & (!\seg_static_inst|Add0~29 )) # (!\seg_static_inst|cnt_wait [16] & ((\seg_static_inst|Add0~29 ) # (GND))) +// \seg_static_inst|Add0~31 = CARRY((!\seg_static_inst|Add0~29 ) # (!\seg_static_inst|cnt_wait [16])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [16]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~29 ), + .combout(\seg_static_inst|Add0~30_combout ), + .cout(\seg_static_inst|Add0~31 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~30 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N8 +cycloneive_lcell_comb \seg_static_inst|Add0~32 ( +// Equation(s): +// \seg_static_inst|Add0~32_combout = (\seg_static_inst|cnt_wait [17] & (\seg_static_inst|Add0~31 $ (GND))) # (!\seg_static_inst|cnt_wait [17] & (!\seg_static_inst|Add0~31 & VCC)) +// \seg_static_inst|Add0~33 = CARRY((\seg_static_inst|cnt_wait [17] & !\seg_static_inst|Add0~31 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [17]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~31 ), + .combout(\seg_static_inst|Add0~32_combout ), + .cout(\seg_static_inst|Add0~33 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~32 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N10 +cycloneive_lcell_comb \seg_static_inst|Add0~34 ( +// Equation(s): +// \seg_static_inst|Add0~34_combout = (\seg_static_inst|cnt_wait [18] & (!\seg_static_inst|Add0~33 )) # (!\seg_static_inst|cnt_wait [18] & ((\seg_static_inst|Add0~33 ) # (GND))) +// \seg_static_inst|Add0~35 = CARRY((!\seg_static_inst|Add0~33 ) # (!\seg_static_inst|cnt_wait [18])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [18]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~33 ), + .combout(\seg_static_inst|Add0~34_combout ), + .cout(\seg_static_inst|Add0~35 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~34 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N12 +cycloneive_lcell_comb \seg_static_inst|Add0~36 ( +// Equation(s): +// \seg_static_inst|Add0~36_combout = (\seg_static_inst|cnt_wait [19] & (\seg_static_inst|Add0~35 $ (GND))) # (!\seg_static_inst|cnt_wait [19] & (!\seg_static_inst|Add0~35 & VCC)) +// \seg_static_inst|Add0~37 = CARRY((\seg_static_inst|cnt_wait [19] & !\seg_static_inst|Add0~35 )) + + .dataa(\seg_static_inst|cnt_wait [19]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~35 ), + .combout(\seg_static_inst|Add0~36_combout ), + .cout(\seg_static_inst|Add0~37 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~36 .lut_mask = 16'hA50A; +defparam \seg_static_inst|Add0~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N14 +cycloneive_lcell_comb \seg_static_inst|Add0~38 ( +// Equation(s): +// \seg_static_inst|Add0~38_combout = (\seg_static_inst|cnt_wait [20] & (!\seg_static_inst|Add0~37 )) # (!\seg_static_inst|cnt_wait [20] & ((\seg_static_inst|Add0~37 ) # (GND))) +// \seg_static_inst|Add0~39 = CARRY((!\seg_static_inst|Add0~37 ) # (!\seg_static_inst|cnt_wait [20])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [20]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~37 ), + .combout(\seg_static_inst|Add0~38_combout ), + .cout(\seg_static_inst|Add0~39 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~38 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N16 +cycloneive_lcell_comb \seg_static_inst|Add0~40 ( +// Equation(s): +// \seg_static_inst|Add0~40_combout = (\seg_static_inst|cnt_wait [21] & (\seg_static_inst|Add0~39 $ (GND))) # (!\seg_static_inst|cnt_wait [21] & (!\seg_static_inst|Add0~39 & VCC)) +// \seg_static_inst|Add0~41 = CARRY((\seg_static_inst|cnt_wait [21] & !\seg_static_inst|Add0~39 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [21]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~39 ), + .combout(\seg_static_inst|Add0~40_combout ), + .cout(\seg_static_inst|Add0~41 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~40 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N18 +cycloneive_lcell_comb \seg_static_inst|Add0~42 ( +// Equation(s): +// \seg_static_inst|Add0~42_combout = (\seg_static_inst|cnt_wait [22] & (!\seg_static_inst|Add0~41 )) # (!\seg_static_inst|cnt_wait [22] & ((\seg_static_inst|Add0~41 ) # (GND))) +// \seg_static_inst|Add0~43 = CARRY((!\seg_static_inst|Add0~41 ) # (!\seg_static_inst|cnt_wait [22])) + + .dataa(\seg_static_inst|cnt_wait [22]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~41 ), + .combout(\seg_static_inst|Add0~42_combout ), + .cout(\seg_static_inst|Add0~43 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~42 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N20 +cycloneive_lcell_comb \seg_static_inst|Add0~44 ( +// Equation(s): +// \seg_static_inst|Add0~44_combout = (\seg_static_inst|cnt_wait [23] & (\seg_static_inst|Add0~43 $ (GND))) # (!\seg_static_inst|cnt_wait [23] & (!\seg_static_inst|Add0~43 & VCC)) +// \seg_static_inst|Add0~45 = CARRY((\seg_static_inst|cnt_wait [23] & !\seg_static_inst|Add0~43 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [23]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~43 ), + .combout(\seg_static_inst|Add0~44_combout ), + .cout(\seg_static_inst|Add0~45 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~44 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N22 +cycloneive_lcell_comb \seg_static_inst|Add0~46 ( +// Equation(s): +// \seg_static_inst|Add0~46_combout = \seg_static_inst|Add0~45 $ (\seg_static_inst|cnt_wait [24]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\seg_static_inst|cnt_wait [24]), + .cin(\seg_static_inst|Add0~45 ), + .combout(\seg_static_inst|Add0~46_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Add0~46 .lut_mask = 16'h0FF0; +defparam \seg_static_inst|Add0~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N10 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~0 ( +// Equation(s): +// \hc595_ctrl_inst|ds~0_combout = (!\hc595_ctrl_inst|cnt_4 [1] & !\hc595_ctrl_inst|cnt_4 [0]) + + .dataa(\hc595_ctrl_inst|cnt_4 [1]), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(gnd), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~0 .lut_mask = 16'h0505; +defparam \hc595_ctrl_inst|ds~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N27 +dffeas \seg_static_inst|seg[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr2~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[4] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N26 +cycloneive_lcell_comb \seg_static_inst|WideOr2~0 ( +// Equation(s): +// \seg_static_inst|WideOr2~0_combout = (\seg_static_inst|num [1] & (\seg_static_inst|num [0] & (!\seg_static_inst|num [3]))) # (!\seg_static_inst|num [1] & ((\seg_static_inst|num [2] & ((!\seg_static_inst|num [3]))) # (!\seg_static_inst|num [2] & +// (\seg_static_inst|num [0])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr2~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr2~0 .lut_mask = 16'h223A; +defparam \seg_static_inst|WideOr2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N3 +dffeas \seg_static_inst|cnt_wait[24] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [24]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[24] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[24] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N21 +dffeas \seg_static_inst|cnt_wait[23] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~44_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [23]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[23] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N24 +cycloneive_lcell_comb \seg_static_inst|Equal0~0 ( +// Equation(s): +// \seg_static_inst|Equal0~0_combout = (\hc595_ctrl_inst|cnt_4 [1] & (!\seg_static_inst|cnt_wait [23] & (\hc595_ctrl_inst|cnt_4 [0] & \seg_static_inst|cnt_wait [24]))) + + .dataa(\hc595_ctrl_inst|cnt_4 [1]), + .datab(\seg_static_inst|cnt_wait [23]), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(\seg_static_inst|cnt_wait [24]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~0 .lut_mask = 16'h2000; +defparam \seg_static_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N7 +dffeas \seg_static_inst|cnt_wait[22] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [22]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[22] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[22] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N25 +dffeas \seg_static_inst|cnt_wait[21] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [21]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[21] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[21] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N9 +dffeas \seg_static_inst|cnt_wait[20] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [20]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[20] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[20] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N27 +dffeas \seg_static_inst|cnt_wait[19] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [19]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[19] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N10 +cycloneive_lcell_comb \seg_static_inst|Equal0~1 ( +// Equation(s): +// \seg_static_inst|Equal0~1_combout = (\seg_static_inst|cnt_wait [22] & (\seg_static_inst|cnt_wait [20] & (\seg_static_inst|cnt_wait [19] & \seg_static_inst|cnt_wait [21]))) + + .dataa(\seg_static_inst|cnt_wait [22]), + .datab(\seg_static_inst|cnt_wait [20]), + .datac(\seg_static_inst|cnt_wait [19]), + .datad(\seg_static_inst|cnt_wait [21]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N29 +dffeas \seg_static_inst|cnt_wait[18] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [18]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[18] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[18] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N29 +dffeas \seg_static_inst|cnt_wait[16] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~6_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [16]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[16] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[16] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N9 +dffeas \seg_static_inst|cnt_wait[17] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~32_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [17]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[17] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[17] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N5 +dffeas \seg_static_inst|cnt_wait[15] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~28_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [15]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[15] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N18 +cycloneive_lcell_comb \seg_static_inst|Equal0~2 ( +// Equation(s): +// \seg_static_inst|Equal0~2_combout = (!\seg_static_inst|cnt_wait [17] & (\seg_static_inst|cnt_wait [16] & (!\seg_static_inst|cnt_wait [15] & \seg_static_inst|cnt_wait [18]))) + + .dataa(\seg_static_inst|cnt_wait [17]), + .datab(\seg_static_inst|cnt_wait [16]), + .datac(\seg_static_inst|cnt_wait [15]), + .datad(\seg_static_inst|cnt_wait [18]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~2 .lut_mask = 16'h0400; +defparam \seg_static_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N21 +dffeas \seg_static_inst|cnt_wait[14] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~7_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [14]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[14] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N31 +dffeas \seg_static_inst|cnt_wait[13] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~8_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [13]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[13] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N23 +dffeas \seg_static_inst|cnt_wait[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~9_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [12]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[12] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[12] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N1 +dffeas \seg_static_inst|cnt_wait[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~10_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [11]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[11] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N26 +cycloneive_lcell_comb \seg_static_inst|Equal0~3 ( +// Equation(s): +// \seg_static_inst|Equal0~3_combout = (\seg_static_inst|cnt_wait [11] & (\seg_static_inst|cnt_wait [14] & (\seg_static_inst|cnt_wait [12] & \seg_static_inst|cnt_wait [13]))) + + .dataa(\seg_static_inst|cnt_wait [11]), + .datab(\seg_static_inst|cnt_wait [14]), + .datac(\seg_static_inst|cnt_wait [12]), + .datad(\seg_static_inst|cnt_wait [13]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~3 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N12 +cycloneive_lcell_comb \seg_static_inst|Equal0~4 ( +// Equation(s): +// \seg_static_inst|Equal0~4_combout = (\seg_static_inst|Equal0~1_combout & (\seg_static_inst|Equal0~2_combout & (\seg_static_inst|Equal0~3_combout & \seg_static_inst|Equal0~0_combout ))) + + .dataa(\seg_static_inst|Equal0~1_combout ), + .datab(\seg_static_inst|Equal0~2_combout ), + .datac(\seg_static_inst|Equal0~3_combout ), + .datad(\seg_static_inst|Equal0~0_combout ), + .cin(gnd), + .combout(\seg_static_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~4 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N23 +dffeas \seg_static_inst|cnt_wait[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [8]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[8] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N13 +dffeas \seg_static_inst|cnt_wait[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [3]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[3] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N2 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~0 ( +// Equation(s): +// \seg_static_inst|cnt_wait~0_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~46_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~46_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~0 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N6 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~1 ( +// Equation(s): +// \seg_static_inst|cnt_wait~1_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~42_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~42_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~1_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~1 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N24 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~2 ( +// Equation(s): +// \seg_static_inst|cnt_wait~2_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~40_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~40_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~2_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~2 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N8 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~3 ( +// Equation(s): +// \seg_static_inst|cnt_wait~3_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~38_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~38_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~3_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~3 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N26 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~4 ( +// Equation(s): +// \seg_static_inst|cnt_wait~4_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~36_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~36_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~4_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~4 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N28 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~5 ( +// Equation(s): +// \seg_static_inst|cnt_wait~5_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~34_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~34_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~5_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~5 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N28 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~6 ( +// Equation(s): +// \seg_static_inst|cnt_wait~6_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~30_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~30_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~6_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~6 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N20 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~7 ( +// Equation(s): +// \seg_static_inst|cnt_wait~7_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~26_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~26_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~7_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~7 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N30 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~8 ( +// Equation(s): +// \seg_static_inst|cnt_wait~8_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~24_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~24_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~8_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~8 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N22 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~9 ( +// Equation(s): +// \seg_static_inst|cnt_wait~9_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~22_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(\seg_static_inst|Add0~22_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~9_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~9 .lut_mask = 16'h0F00; +defparam \seg_static_inst|cnt_wait~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N0 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~10 ( +// Equation(s): +// \seg_static_inst|cnt_wait~10_combout = (!\seg_static_inst|Equal0~7_combout & \seg_static_inst|Add0~20_combout ) + + .dataa(gnd), + .datab(\seg_static_inst|Equal0~7_combout ), + .datac(\seg_static_inst|Add0~20_combout ), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~10_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~10 .lut_mask = 16'h3030; +defparam \seg_static_inst|cnt_wait~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y6_N9 +cycloneive_io_obuf \stcp~output ( + .i(\hc595_ctrl_inst|stcp~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\stcp~output_o ), + .obar()); +// synopsys translate_off +defparam \stcp~output .bus_hold = "false"; +defparam \stcp~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y7_N23 +cycloneive_io_obuf \shcp~output ( + .i(\hc595_ctrl_inst|shcp~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\shcp~output_o ), + .obar()); +// synopsys translate_off +defparam \shcp~output .bus_hold = "false"; +defparam \shcp~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y5_N16 +cycloneive_io_obuf \ds~output ( + .i(\hc595_ctrl_inst|ds~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\ds~output_o ), + .obar()); +// synopsys translate_off +defparam \ds~output .bus_hold = "false"; +defparam \ds~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y6_N2 +cycloneive_io_obuf \oe~output ( + .i(!\sys_rst_n~input_o ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\oe~output_o ), + .obar()); +// synopsys translate_off +defparam \oe~output .bus_hold = "false"; +defparam \oe~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \sys_clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sys_clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sys_clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \sys_clk~inputclkctrl .clock_type = "global clock"; +defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N6 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_4[0]~0 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_4[0]~0_combout = !\hc595_ctrl_inst|cnt_4 [0] + + .dataa(gnd), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(gnd), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_4[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_4[0]~0 .lut_mask = 16'h0F0F; +defparam \hc595_ctrl_inst|cnt_4[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X14_Y13_N7 +dffeas \hc595_ctrl_inst|cnt_4[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_4[0]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_4 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_4[0] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_4[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N14 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[0]~1 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[0]~1_combout = \hc595_ctrl_inst|cnt_bit [0] $ (((\hc595_ctrl_inst|cnt_4 [1] & \hc595_ctrl_inst|cnt_4 [0]))) + + .dataa(\hc595_ctrl_inst|cnt_4 [1]), + .datab(\hc595_ctrl_inst|cnt_4 [0]), + .datac(\hc595_ctrl_inst|cnt_bit [0]), + .datad(gnd), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[0]~1 .lut_mask = 16'h7878; +defparam \hc595_ctrl_inst|cnt_bit[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N15 +dffeas \hc595_ctrl_inst|cnt_bit[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[0]~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[0] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N24 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[1]~0 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[1]~0_combout = (\hc595_ctrl_inst|Equal1~0_combout & (!\hc595_ctrl_inst|always2~1_combout & (\hc595_ctrl_inst|cnt_bit [0] $ (\hc595_ctrl_inst|cnt_bit [1])))) # (!\hc595_ctrl_inst|Equal1~0_combout & (((\hc595_ctrl_inst|cnt_bit +// [1])))) + + .dataa(\hc595_ctrl_inst|Equal1~0_combout ), + .datab(\hc595_ctrl_inst|cnt_bit [0]), + .datac(\hc595_ctrl_inst|cnt_bit [1]), + .datad(\hc595_ctrl_inst|always2~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[1]~0 .lut_mask = 16'h5078; +defparam \hc595_ctrl_inst|cnt_bit[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N25 +dffeas \hc595_ctrl_inst|cnt_bit[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[1]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[1] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N0 +cycloneive_lcell_comb \hc595_ctrl_inst|always2~0 ( +// Equation(s): +// \hc595_ctrl_inst|always2~0_combout = (\hc595_ctrl_inst|cnt_bit [0] & \hc595_ctrl_inst|cnt_bit [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_bit [0]), + .datad(\hc595_ctrl_inst|cnt_bit [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|always2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|always2~0 .lut_mask = 16'hF000; +defparam \hc595_ctrl_inst|always2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N8 +cycloneive_lcell_comb \seg_static_inst|Add0~0 ( +// Equation(s): +// \seg_static_inst|Add0~0_combout = (\hc595_ctrl_inst|cnt_4 [0] & (\hc595_ctrl_inst|cnt_4 [1] $ (VCC))) # (!\hc595_ctrl_inst|cnt_4 [0] & (\hc595_ctrl_inst|cnt_4 [1] & VCC)) +// \seg_static_inst|Add0~1 = CARRY((\hc595_ctrl_inst|cnt_4 [0] & \hc595_ctrl_inst|cnt_4 [1])) + + .dataa(\hc595_ctrl_inst|cnt_4 [0]), + .datab(\hc595_ctrl_inst|cnt_4 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\seg_static_inst|Add0~0_combout ), + .cout(\seg_static_inst|Add0~1 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~0 .lut_mask = 16'h6688; +defparam \seg_static_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N9 +dffeas \hc595_ctrl_inst|cnt_4[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_4 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_4[1] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_4[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N22 +cycloneive_lcell_comb \hc595_ctrl_inst|Equal1~0 ( +// Equation(s): +// \hc595_ctrl_inst|Equal1~0_combout = (\hc595_ctrl_inst|cnt_4 [0] & \hc595_ctrl_inst|cnt_4 [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\hc595_ctrl_inst|cnt_4 [0]), + .datad(\hc595_ctrl_inst|cnt_4 [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Equal1~0 .lut_mask = 16'hF000; +defparam \hc595_ctrl_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N16 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[3]~2 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[3]~2_combout = (\hc595_ctrl_inst|always2~0_combout & ((\hc595_ctrl_inst|cnt_bit [3] & ((!\hc595_ctrl_inst|Equal1~0_combout ))) # (!\hc595_ctrl_inst|cnt_bit [3] & (\hc595_ctrl_inst|cnt_bit [2] & \hc595_ctrl_inst|Equal1~0_combout +// )))) # (!\hc595_ctrl_inst|always2~0_combout & (((\hc595_ctrl_inst|cnt_bit [3])))) + + .dataa(\hc595_ctrl_inst|cnt_bit [2]), + .datab(\hc595_ctrl_inst|always2~0_combout ), + .datac(\hc595_ctrl_inst|cnt_bit [3]), + .datad(\hc595_ctrl_inst|Equal1~0_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[3]~2 .lut_mask = 16'h38F0; +defparam \hc595_ctrl_inst|cnt_bit[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N17 +dffeas \hc595_ctrl_inst|cnt_bit[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[3]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[3] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N28 +cycloneive_lcell_comb \hc595_ctrl_inst|always2~1 ( +// Equation(s): +// \hc595_ctrl_inst|always2~1_combout = (!\hc595_ctrl_inst|cnt_bit [2] & (\hc595_ctrl_inst|cnt_bit [3] & (\hc595_ctrl_inst|Equal1~0_combout & \hc595_ctrl_inst|always2~0_combout ))) + + .dataa(\hc595_ctrl_inst|cnt_bit [2]), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|Equal1~0_combout ), + .datad(\hc595_ctrl_inst|always2~0_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|always2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|always2~1 .lut_mask = 16'h4000; +defparam \hc595_ctrl_inst|always2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N4 +cycloneive_lcell_comb \hc595_ctrl_inst|stcp~feeder ( +// Equation(s): +// \hc595_ctrl_inst|stcp~feeder_combout = \hc595_ctrl_inst|always2~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hc595_ctrl_inst|always2~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|stcp~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|stcp~feeder .lut_mask = 16'hFF00; +defparam \hc595_ctrl_inst|stcp~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N5 +dffeas \hc595_ctrl_inst|stcp ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|stcp~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|stcp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|stcp .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|stcp .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N19 +dffeas \hc595_ctrl_inst|shcp ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\hc595_ctrl_inst|cnt_4 [1]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|shcp~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|shcp .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|shcp .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N26 +cycloneive_lcell_comb \hc595_ctrl_inst|cnt_bit[2]~3 ( +// Equation(s): +// \hc595_ctrl_inst|cnt_bit[2]~3_combout = (\hc595_ctrl_inst|Equal1~0_combout & ((\hc595_ctrl_inst|cnt_bit [2] & ((!\hc595_ctrl_inst|always2~0_combout ))) # (!\hc595_ctrl_inst|cnt_bit [2] & (!\hc595_ctrl_inst|cnt_bit [3] & +// \hc595_ctrl_inst|always2~0_combout )))) # (!\hc595_ctrl_inst|Equal1~0_combout & (((\hc595_ctrl_inst|cnt_bit [2])))) + + .dataa(\hc595_ctrl_inst|Equal1~0_combout ), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|cnt_bit [2]), + .datad(\hc595_ctrl_inst|always2~0_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|cnt_bit[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[2]~3 .lut_mask = 16'h52F0; +defparam \hc595_ctrl_inst|cnt_bit[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N27 +dffeas \hc595_ctrl_inst|cnt_bit[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|cnt_bit[2]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|cnt_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|cnt_bit[2] .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|cnt_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N10 +cycloneive_lcell_comb \seg_static_inst|Add0~2 ( +// Equation(s): +// \seg_static_inst|Add0~2_combout = (\seg_static_inst|cnt_wait [2] & (!\seg_static_inst|Add0~1 )) # (!\seg_static_inst|cnt_wait [2] & ((\seg_static_inst|Add0~1 ) # (GND))) +// \seg_static_inst|Add0~3 = CARRY((!\seg_static_inst|Add0~1 ) # (!\seg_static_inst|cnt_wait [2])) + + .dataa(\seg_static_inst|cnt_wait [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~1 ), + .combout(\seg_static_inst|Add0~2_combout ), + .cout(\seg_static_inst|Add0~3 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \seg_static_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N11 +dffeas \seg_static_inst|cnt_wait[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [2]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[2] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N14 +cycloneive_lcell_comb \seg_static_inst|Add0~6 ( +// Equation(s): +// \seg_static_inst|Add0~6_combout = (\seg_static_inst|cnt_wait [4] & (!\seg_static_inst|Add0~5 )) # (!\seg_static_inst|cnt_wait [4] & ((\seg_static_inst|Add0~5 ) # (GND))) +// \seg_static_inst|Add0~7 = CARRY((!\seg_static_inst|Add0~5 ) # (!\seg_static_inst|cnt_wait [4])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [4]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~5 ), + .combout(\seg_static_inst|Add0~6_combout ), + .cout(\seg_static_inst|Add0~7 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N15 +dffeas \seg_static_inst|cnt_wait[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [4]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[4] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N16 +cycloneive_lcell_comb \seg_static_inst|Add0~8 ( +// Equation(s): +// \seg_static_inst|Add0~8_combout = (\seg_static_inst|cnt_wait [5] & (\seg_static_inst|Add0~7 $ (GND))) # (!\seg_static_inst|cnt_wait [5] & (!\seg_static_inst|Add0~7 & VCC)) +// \seg_static_inst|Add0~9 = CARRY((\seg_static_inst|cnt_wait [5] & !\seg_static_inst|Add0~7 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [5]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~7 ), + .combout(\seg_static_inst|Add0~8_combout ), + .cout(\seg_static_inst|Add0~9 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N17 +dffeas \seg_static_inst|cnt_wait[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [5]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[5] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N18 +cycloneive_lcell_comb \seg_static_inst|Add0~10 ( +// Equation(s): +// \seg_static_inst|Add0~10_combout = (\seg_static_inst|cnt_wait [6] & (!\seg_static_inst|Add0~9 )) # (!\seg_static_inst|cnt_wait [6] & ((\seg_static_inst|Add0~9 ) # (GND))) +// \seg_static_inst|Add0~11 = CARRY((!\seg_static_inst|Add0~9 ) # (!\seg_static_inst|cnt_wait [6])) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [6]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~9 ), + .combout(\seg_static_inst|Add0~10_combout ), + .cout(\seg_static_inst|Add0~11 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~10 .lut_mask = 16'h3C3F; +defparam \seg_static_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N4 +cycloneive_lcell_comb \seg_static_inst|cnt_wait~11 ( +// Equation(s): +// \seg_static_inst|cnt_wait~11_combout = (\seg_static_inst|Add0~10_combout & !\seg_static_inst|Equal0~7_combout ) + + .dataa(gnd), + .datab(\seg_static_inst|Add0~10_combout ), + .datac(gnd), + .datad(\seg_static_inst|Equal0~7_combout ), + .cin(gnd), + .combout(\seg_static_inst|cnt_wait~11_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait~11 .lut_mask = 16'h00CC; +defparam \seg_static_inst|cnt_wait~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N5 +dffeas \seg_static_inst|cnt_wait[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|cnt_wait~11_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [6]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[6] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N20 +cycloneive_lcell_comb \seg_static_inst|Add0~12 ( +// Equation(s): +// \seg_static_inst|Add0~12_combout = (\seg_static_inst|cnt_wait [7] & (\seg_static_inst|Add0~11 $ (GND))) # (!\seg_static_inst|cnt_wait [7] & (!\seg_static_inst|Add0~11 & VCC)) +// \seg_static_inst|Add0~13 = CARRY((\seg_static_inst|cnt_wait [7] & !\seg_static_inst|Add0~11 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [7]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~11 ), + .combout(\seg_static_inst|Add0~12_combout ), + .cout(\seg_static_inst|Add0~13 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N21 +dffeas \seg_static_inst|cnt_wait[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [7]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[7] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N24 +cycloneive_lcell_comb \seg_static_inst|Add0~16 ( +// Equation(s): +// \seg_static_inst|Add0~16_combout = (\seg_static_inst|cnt_wait [9] & (\seg_static_inst|Add0~15 $ (GND))) # (!\seg_static_inst|cnt_wait [9] & (!\seg_static_inst|Add0~15 & VCC)) +// \seg_static_inst|Add0~17 = CARRY((\seg_static_inst|cnt_wait [9] & !\seg_static_inst|Add0~15 )) + + .dataa(gnd), + .datab(\seg_static_inst|cnt_wait [9]), + .datac(gnd), + .datad(vcc), + .cin(\seg_static_inst|Add0~15 ), + .combout(\seg_static_inst|Add0~16_combout ), + .cout(\seg_static_inst|Add0~17 )); +// synopsys translate_off +defparam \seg_static_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \seg_static_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y13_N25 +dffeas \seg_static_inst|cnt_wait[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~16_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [9]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[9] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N27 +dffeas \seg_static_inst|cnt_wait[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|Add0~18_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|cnt_wait [10]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|cnt_wait[10] .is_wysiwyg = "true"; +defparam \seg_static_inst|cnt_wait[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N0 +cycloneive_lcell_comb \seg_static_inst|Equal0~5 ( +// Equation(s): +// \seg_static_inst|Equal0~5_combout = (!\seg_static_inst|cnt_wait [8] & (!\seg_static_inst|cnt_wait [7] & (!\seg_static_inst|cnt_wait [10] & !\seg_static_inst|cnt_wait [9]))) + + .dataa(\seg_static_inst|cnt_wait [8]), + .datab(\seg_static_inst|cnt_wait [7]), + .datac(\seg_static_inst|cnt_wait [10]), + .datad(\seg_static_inst|cnt_wait [9]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~5_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~5 .lut_mask = 16'h0001; +defparam \seg_static_inst|Equal0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N2 +cycloneive_lcell_comb \seg_static_inst|Equal0~6 ( +// Equation(s): +// \seg_static_inst|Equal0~6_combout = (\seg_static_inst|cnt_wait [3] & (\seg_static_inst|cnt_wait [4] & (!\seg_static_inst|cnt_wait [6] & \seg_static_inst|cnt_wait [5]))) + + .dataa(\seg_static_inst|cnt_wait [3]), + .datab(\seg_static_inst|cnt_wait [4]), + .datac(\seg_static_inst|cnt_wait [6]), + .datad(\seg_static_inst|cnt_wait [5]), + .cin(gnd), + .combout(\seg_static_inst|Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~6 .lut_mask = 16'h0800; +defparam \seg_static_inst|Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N14 +cycloneive_lcell_comb \seg_static_inst|Equal0~7 ( +// Equation(s): +// \seg_static_inst|Equal0~7_combout = (\seg_static_inst|Equal0~4_combout & (\seg_static_inst|cnt_wait [2] & (\seg_static_inst|Equal0~5_combout & \seg_static_inst|Equal0~6_combout ))) + + .dataa(\seg_static_inst|Equal0~4_combout ), + .datab(\seg_static_inst|cnt_wait [2]), + .datac(\seg_static_inst|Equal0~5_combout ), + .datad(\seg_static_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\seg_static_inst|Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|Equal0~7 .lut_mask = 16'h8000; +defparam \seg_static_inst|Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N4 +cycloneive_lcell_comb \seg_static_inst|add_flag~feeder ( +// Equation(s): +// \seg_static_inst|add_flag~feeder_combout = \seg_static_inst|Equal0~7_combout + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|Equal0~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|add_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|add_flag~feeder .lut_mask = 16'hF0F0; +defparam \seg_static_inst|add_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N5 +dffeas \seg_static_inst|add_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|add_flag~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|add_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|add_flag .is_wysiwyg = "true"; +defparam \seg_static_inst|add_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N10 +cycloneive_lcell_comb \seg_static_inst|num[0]~0 ( +// Equation(s): +// \seg_static_inst|num[0]~0_combout = \seg_static_inst|add_flag~q $ (\seg_static_inst|num [0]) + + .dataa(gnd), + .datab(\seg_static_inst|add_flag~q ), + .datac(\seg_static_inst|num [0]), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|num[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[0]~0 .lut_mask = 16'h3C3C; +defparam \seg_static_inst|num[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N11 +dffeas \seg_static_inst|num[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[0]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[0] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N0 +cycloneive_lcell_comb \seg_static_inst|num[1]~1 ( +// Equation(s): +// \seg_static_inst|num[1]~1_combout = \seg_static_inst|num [1] $ (((\seg_static_inst|add_flag~q & \seg_static_inst|num [0]))) + + .dataa(gnd), + .datab(\seg_static_inst|add_flag~q ), + .datac(\seg_static_inst|num [1]), + .datad(\seg_static_inst|num [0]), + .cin(gnd), + .combout(\seg_static_inst|num[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[1]~1 .lut_mask = 16'h3CF0; +defparam \seg_static_inst|num[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N1 +dffeas \seg_static_inst|num[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[1]~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[1] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N14 +cycloneive_lcell_comb \seg_static_inst|num[2]~2 ( +// Equation(s): +// \seg_static_inst|num[2]~2_combout = \seg_static_inst|num [2] $ (((\seg_static_inst|num [0] & (\seg_static_inst|add_flag~q & \seg_static_inst|num [1])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|add_flag~q ), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|num[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[2]~2 .lut_mask = 16'h78F0; +defparam \seg_static_inst|num[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N15 +dffeas \seg_static_inst|num[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[2]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[2] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N18 +cycloneive_lcell_comb \seg_static_inst|num[3]~3 ( +// Equation(s): +// \seg_static_inst|num[3]~3_combout = (\seg_static_inst|num [0] & (\seg_static_inst|num [2] & (\seg_static_inst|add_flag~q & \seg_static_inst|num [1]))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [2]), + .datac(\seg_static_inst|add_flag~q ), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|num[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[3]~3 .lut_mask = 16'h8000; +defparam \seg_static_inst|num[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N16 +cycloneive_lcell_comb \seg_static_inst|num[3]~4 ( +// Equation(s): +// \seg_static_inst|num[3]~4_combout = \seg_static_inst|num [3] $ (\seg_static_inst|num[3]~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\seg_static_inst|num [3]), + .datad(\seg_static_inst|num[3]~3_combout ), + .cin(gnd), + .combout(\seg_static_inst|num[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|num[3]~4 .lut_mask = 16'h0FF0; +defparam \seg_static_inst|num[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N17 +dffeas \seg_static_inst|num[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|num[3]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|num[3] .is_wysiwyg = "true"; +defparam \seg_static_inst|num[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N8 +cycloneive_lcell_comb \seg_static_inst|WideOr1~0 ( +// Equation(s): +// \seg_static_inst|WideOr1~0_combout = (\seg_static_inst|num [0] & (\seg_static_inst|num [3] $ (((\seg_static_inst|num [1]) # (!\seg_static_inst|num [2]))))) # (!\seg_static_inst|num [0] & (!\seg_static_inst|num [3] & (!\seg_static_inst|num [2] & +// \seg_static_inst|num [1]))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr1~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr1~0 .lut_mask = 16'h2382; +defparam \seg_static_inst|WideOr1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N9 +dffeas \seg_static_inst|seg[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr1~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[5] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N6 +cycloneive_lcell_comb \seg_static_inst|seg[7]~feeder ( +// Equation(s): +// \seg_static_inst|seg[7]~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\seg_static_inst|seg[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|seg[7]~feeder .lut_mask = 16'hFFFF; +defparam \seg_static_inst|seg[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N7 +dffeas \seg_static_inst|seg[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|seg[7]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[7] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N22 +cycloneive_lcell_comb \seg_static_inst|WideOr0~0 ( +// Equation(s): +// \seg_static_inst|WideOr0~0_combout = (\seg_static_inst|num [0] & (!\seg_static_inst|num [3] & (\seg_static_inst|num [2] $ (!\seg_static_inst|num [1])))) # (!\seg_static_inst|num [0] & (!\seg_static_inst|num [1] & (\seg_static_inst|num [3] $ +// (!\seg_static_inst|num [2])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr0~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr0~0 .lut_mask = 16'h2043; +defparam \seg_static_inst|WideOr0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N23 +dffeas \seg_static_inst|seg[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr0~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[6] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N12 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~2 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~2_combout = (\hc595_ctrl_inst|cnt_bit [0] & (((\hc595_ctrl_inst|cnt_bit [1]) # (!\seg_static_inst|seg [6])))) # (!\hc595_ctrl_inst|cnt_bit [0] & (!\seg_static_inst|seg [7] & ((!\hc595_ctrl_inst|cnt_bit [1])))) + + .dataa(\hc595_ctrl_inst|cnt_bit [0]), + .datab(\seg_static_inst|seg [7]), + .datac(\seg_static_inst|seg [6]), + .datad(\hc595_ctrl_inst|cnt_bit [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~2_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~2 .lut_mask = 16'hAA1B; +defparam \hc595_ctrl_inst|Mux0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N24 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~3 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~3_combout = (\hc595_ctrl_inst|cnt_bit [1] & ((\hc595_ctrl_inst|Mux0~2_combout & (!\seg_static_inst|seg [4])) # (!\hc595_ctrl_inst|Mux0~2_combout & ((!\seg_static_inst|seg [5]))))) # (!\hc595_ctrl_inst|cnt_bit [1] & +// (((\hc595_ctrl_inst|Mux0~2_combout )))) + + .dataa(\seg_static_inst|seg [4]), + .datab(\hc595_ctrl_inst|cnt_bit [1]), + .datac(\seg_static_inst|seg [5]), + .datad(\hc595_ctrl_inst|Mux0~2_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~3_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~3 .lut_mask = 16'h770C; +defparam \hc595_ctrl_inst|Mux0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N20 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~2 ( +// Equation(s): +// \hc595_ctrl_inst|ds~2_combout = (!\hc595_ctrl_inst|cnt_bit [3] & ((\hc595_ctrl_inst|cnt_bit [2] & ((\hc595_ctrl_inst|Mux0~3_combout ))) # (!\hc595_ctrl_inst|cnt_bit [2] & (!\seg_static_inst|seg [7])))) + + .dataa(\seg_static_inst|seg [7]), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|cnt_bit [2]), + .datad(\hc595_ctrl_inst|Mux0~3_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~2_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~2 .lut_mask = 16'h3101; +defparam \hc595_ctrl_inst|ds~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N20 +cycloneive_lcell_comb \seg_static_inst|WideOr4~0 ( +// Equation(s): +// \seg_static_inst|WideOr4~0_combout = (\seg_static_inst|num [3] & (\seg_static_inst|num [2] & ((\seg_static_inst|num [1]) # (!\seg_static_inst|num [0])))) # (!\seg_static_inst|num [3] & (!\seg_static_inst|num [0] & (!\seg_static_inst|num [2] & +// \seg_static_inst|num [1]))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr4~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr4~0 .lut_mask = 16'hC140; +defparam \seg_static_inst|WideOr4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N21 +dffeas \seg_static_inst|seg[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr4~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[2] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N4 +cycloneive_lcell_comb \seg_static_inst|WideOr3~0 ( +// Equation(s): +// \seg_static_inst|WideOr3~0_combout = (\seg_static_inst|num [1] & ((\seg_static_inst|num [0] & ((\seg_static_inst|num [2]))) # (!\seg_static_inst|num [0] & (\seg_static_inst|num [3] & !\seg_static_inst|num [2])))) # (!\seg_static_inst|num [1] & +// (!\seg_static_inst|num [3] & (\seg_static_inst|num [0] $ (\seg_static_inst|num [2])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr3~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr3~0 .lut_mask = 16'hA412; +defparam \seg_static_inst|WideOr3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N5 +dffeas \seg_static_inst|seg[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr3~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[3] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N2 +cycloneive_lcell_comb \seg_static_inst|WideOr5~0 ( +// Equation(s): +// \seg_static_inst|WideOr5~0_combout = (\seg_static_inst|num [3] & ((\seg_static_inst|num [0] & ((\seg_static_inst|num [1]))) # (!\seg_static_inst|num [0] & (\seg_static_inst|num [2])))) # (!\seg_static_inst|num [3] & (\seg_static_inst|num [2] & +// (\seg_static_inst|num [0] $ (\seg_static_inst|num [1])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr5~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr5~0 .lut_mask = 16'hD860; +defparam \seg_static_inst|WideOr5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N3 +dffeas \seg_static_inst|seg[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr5~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[1] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N30 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~0 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~0_combout = (\hc595_ctrl_inst|cnt_bit [0] & (\hc595_ctrl_inst|cnt_bit [1])) # (!\hc595_ctrl_inst|cnt_bit [0] & ((\hc595_ctrl_inst|cnt_bit [1] & ((!\seg_static_inst|seg [1]))) # (!\hc595_ctrl_inst|cnt_bit [1] & (!\seg_static_inst|seg +// [3])))) + + .dataa(\hc595_ctrl_inst|cnt_bit [0]), + .datab(\hc595_ctrl_inst|cnt_bit [1]), + .datac(\seg_static_inst|seg [3]), + .datad(\seg_static_inst|seg [1]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~0 .lut_mask = 16'h89CD; +defparam \hc595_ctrl_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N28 +cycloneive_lcell_comb \seg_static_inst|WideOr6~0 ( +// Equation(s): +// \seg_static_inst|WideOr6~0_combout = (\seg_static_inst|num [3] & (\seg_static_inst|num [0] & (\seg_static_inst|num [2] $ (\seg_static_inst|num [1])))) # (!\seg_static_inst|num [3] & (!\seg_static_inst|num [1] & (\seg_static_inst|num [0] $ +// (\seg_static_inst|num [2])))) + + .dataa(\seg_static_inst|num [0]), + .datab(\seg_static_inst|num [3]), + .datac(\seg_static_inst|num [2]), + .datad(\seg_static_inst|num [1]), + .cin(gnd), + .combout(\seg_static_inst|WideOr6~0_combout ), + .cout()); +// synopsys translate_off +defparam \seg_static_inst|WideOr6~0 .lut_mask = 16'h0892; +defparam \seg_static_inst|WideOr6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N29 +dffeas \seg_static_inst|seg[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\seg_static_inst|WideOr6~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\seg_static_inst|seg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \seg_static_inst|seg[0] .is_wysiwyg = "true"; +defparam \seg_static_inst|seg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N6 +cycloneive_lcell_comb \hc595_ctrl_inst|Mux0~1 ( +// Equation(s): +// \hc595_ctrl_inst|Mux0~1_combout = (\hc595_ctrl_inst|cnt_bit [0] & ((\hc595_ctrl_inst|Mux0~0_combout & ((!\seg_static_inst|seg [0]))) # (!\hc595_ctrl_inst|Mux0~0_combout & (!\seg_static_inst|seg [2])))) # (!\hc595_ctrl_inst|cnt_bit [0] & +// (((\hc595_ctrl_inst|Mux0~0_combout )))) + + .dataa(\hc595_ctrl_inst|cnt_bit [0]), + .datab(\seg_static_inst|seg [2]), + .datac(\hc595_ctrl_inst|Mux0~0_combout ), + .datad(\seg_static_inst|seg [0]), + .cin(gnd), + .combout(\hc595_ctrl_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|Mux0~1 .lut_mask = 16'h52F2; +defparam \hc595_ctrl_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N12 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~1 ( +// Equation(s): +// \hc595_ctrl_inst|ds~1_combout = (\hc595_ctrl_inst|cnt_bit [3] & (!\hc595_ctrl_inst|cnt_bit [2] & \hc595_ctrl_inst|Mux0~1_combout )) + + .dataa(gnd), + .datab(\hc595_ctrl_inst|cnt_bit [3]), + .datac(\hc595_ctrl_inst|cnt_bit [2]), + .datad(\hc595_ctrl_inst|Mux0~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~1_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~1 .lut_mask = 16'h0C00; +defparam \hc595_ctrl_inst|ds~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N30 +cycloneive_lcell_comb \hc595_ctrl_inst|ds~3 ( +// Equation(s): +// \hc595_ctrl_inst|ds~3_combout = (\hc595_ctrl_inst|ds~0_combout & ((\hc595_ctrl_inst|ds~2_combout ) # ((\hc595_ctrl_inst|ds~1_combout )))) # (!\hc595_ctrl_inst|ds~0_combout & (((\hc595_ctrl_inst|ds~q )))) + + .dataa(\hc595_ctrl_inst|ds~0_combout ), + .datab(\hc595_ctrl_inst|ds~2_combout ), + .datac(\hc595_ctrl_inst|ds~q ), + .datad(\hc595_ctrl_inst|ds~1_combout ), + .cin(gnd), + .combout(\hc595_ctrl_inst|ds~3_combout ), + .cout()); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds~3 .lut_mask = 16'hFAD8; +defparam \hc595_ctrl_inst|ds~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N31 +dffeas \hc595_ctrl_inst|ds ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\hc595_ctrl_inst|ds~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hc595_ctrl_inst|ds~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hc595_ctrl_inst|ds .is_wysiwyg = "true"; +defparam \hc595_ctrl_inst|ds .power_up = "low"; +// synopsys translate_on + +assign stcp = \stcp~output_o ; + +assign shcp = \shcp~output_o ; + +assign ds = \ds~output_o ; + +assign oe = \oe~output_o ; + +endmodule diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_min_1200mv_0c_v_fast.sdo b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_min_1200mv_0c_v_fast.sdo new file mode 100644 index 0000000..831b7f2 --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_min_1200mv_0c_v_fast.sdo @@ -0,0 +1,1858 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Fast Corner delays for the design using part EP4CE15F23C8, +// with speed grade M, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "seg_595_static") + (DATE "06/02/2023 20:55:14") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (187:187:187)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~20) + (DELAY + (ABSOLUTE + (PORT datab (351:351:351) (421:421:421)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~22) + (DELAY + (ABSOLUTE + (PORT datab (379:379:379) (457:457:457)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~24) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (198:198:198)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~26) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (275:275:275)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~28) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~30) + (DELAY + (ABSOLUTE + (PORT datab (144:144:144) (193:193:193)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~32) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~34) + (DELAY + (ABSOLUTE + (PORT datab (215:215:215) (273:273:273)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~36) + (DELAY + (ABSOLUTE + (PORT dataa (144:144:144) (196:196:196)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~38) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (284:284:284)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~40) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~42) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (275:275:275)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~44) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~46) + (DELAY + (ABSOLUTE + (PORT datad (204:204:204) (250:250:250)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~0) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (294:294:294)) + (PORT datac (213:213:213) (266:266:266)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2920:2920:2920) (2600:2600:2600)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (253:253:253)) + (PORT datab (161:161:161) (219:219:219)) + (PORT datac (150:150:150) (207:207:207)) + (PORT datad (156:156:156) (207:207:207)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[24\]) + (DELAY + (ABSOLUTE + (PORT clk (1068:1068:1068) (1098:1098:1098)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3084:3084:3084) (2737:2737:2737)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2807:2807:2807) (2498:2498:2498)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (442:442:442)) + (PORT datab (224:224:224) (277:277:277)) + (PORT datac (341:341:341) (407:407:407)) + (PORT datad (131:131:131) (169:169:169)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3084:3084:3084) (2737:2737:2737)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2807:2807:2807) (2498:2498:2498)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3084:3084:3084) (2737:2737:2737)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2807:2807:2807) (2498:2498:2498)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (PORT datab (142:142:142) (189:189:189)) + (PORT datac (209:209:209) (259:259:259)) + (PORT datad (207:207:207) (253:253:253)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3084:3084:3084) (2737:2737:2737)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2807:2807:2807) (2498:2498:2498)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2807:2807:2807) (2498:2498:2498)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2807:2807:2807) (2498:2498:2498)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (267:267:267)) + (PORT datab (223:223:223) (276:276:276)) + (PORT datac (196:196:196) (243:243:243)) + (PORT datad (129:129:129) (167:167:167)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3084:3084:3084) (2737:2737:2737)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2807:2807:2807) (2498:2498:2498)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3084:3084:3084) (2737:2737:2737)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3084:3084:3084) (2737:2737:2737)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (234:234:234) (289:289:289)) + (PORT datab (142:142:142) (190:190:190)) + (PORT datac (128:128:128) (168:168:168)) + (PORT datad (193:193:193) (236:236:236)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (91:91:91) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2789:2789:2789) (2490:2490:2490)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2789:2789:2789) (2490:2490:2490)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~0) + (DELAY + (ABSOLUTE + (PORT datac (135:135:135) (172:172:172)) + (PORT datad (160:160:160) (187:187:187)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~1) + (DELAY + (ABSOLUTE + (PORT datac (134:134:134) (171:171:171)) + (PORT datad (159:159:159) (185:185:185)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~2) + (DELAY + (ABSOLUTE + (PORT datac (209:209:209) (254:254:254)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~3) + (DELAY + (ABSOLUTE + (PORT datac (134:134:134) (170:170:170)) + (PORT datad (161:161:161) (184:184:184)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~4) + (DELAY + (ABSOLUTE + (PORT datac (209:209:209) (254:254:254)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~5) + (DELAY + (ABSOLUTE + (PORT datac (135:135:135) (172:172:172)) + (PORT datad (169:169:169) (198:198:198)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~6) + (DELAY + (ABSOLUTE + (PORT datac (209:209:209) (254:254:254)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~7) + (DELAY + (ABSOLUTE + (PORT datac (134:134:134) (172:172:172)) + (PORT datad (168:168:168) (196:196:196)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~8) + (DELAY + (ABSOLUTE + (PORT datac (210:210:210) (255:255:255)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~9) + (DELAY + (ABSOLUTE + (PORT datac (134:134:134) (172:172:172)) + (PORT datad (273:273:273) (310:310:310)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~10) + (DELAY + (ABSOLUTE + (PORT datab (153:153:153) (195:195:195)) + (PORT datac (313:313:313) (361:361:361)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE stcp\~output) + (DELAY + (ABSOLUTE + (PORT i (687:687:687) (805:805:805)) + (IOPATH i o (1832:1832:1832) (1805:1805:1805)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE shcp\~output) + (DELAY + (ABSOLUTE + (PORT i (756:756:756) (878:878:878)) + (IOPATH i o (1812:1812:1812) (1785:1785:1785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE ds\~output) + (DELAY + (ABSOLUTE + (PORT i (914:914:914) (1043:1043:1043)) + (IOPATH i o (1822:1822:1822) (1795:1795:1795)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE oe\~output) + (DELAY + (ABSOLUTE + (PORT i (2303:2303:2303) (2047:2047:2047)) + (IOPATH i o (1795:1795:1795) (1822:1822:1822)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (358:358:358) (738:738:738)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sys_clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (97:97:97) (82:82:82)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_4\[0\]\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_4\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2789:2789:2789) (2490:2490:2490)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (294:294:294)) + (PORT datab (228:228:228) (288:288:288)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2934:2934:2934) (2613:2613:2613)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (162:162:162)) + (PORT datab (148:148:148) (198:198:198)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2934:2934:2934) (2613:2613:2613)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|always2\~0) + (DELAY + (ABSOLUTE + (PORT datac (134:134:134) (177:177:177)) + (PORT datad (132:132:132) (170:170:170)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (192:192:192)) + (PORT datab (141:141:141) (189:189:189)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_4\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2789:2789:2789) (2490:2490:2490)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT datac (215:215:215) (268:268:268)) + (PORT datad (218:218:218) (269:269:269)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (205:205:205)) + (PORT datab (115:115:115) (148:148:148)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2934:2934:2934) (2613:2613:2613)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|always2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (203:203:203)) + (PORT datab (146:146:146) (200:200:200)) + (PORT datac (113:113:113) (139:139:139)) + (PORT datad (104:104:104) (127:127:127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|stcp\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (97:97:97) (117:117:117)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|stcp) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2934:2934:2934) (2613:2613:2613)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|shcp) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT asdata (504:504:504) (567:567:567)) + (PORT clrn (2789:2789:2789) (2490:2490:2490)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (163:163:163)) + (PORT datab (146:146:146) (200:200:200)) + (PORT datad (103:103:103) (126:126:126)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2934:2934:2934) (2613:2613:2613)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (192:192:192)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2789:2789:2789) (2490:2490:2490)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2789:2789:2789) (2490:2490:2490)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (183:183:183)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2789:2789:2789) (2490:2490:2490)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (186:186:186)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~11) + (DELAY + (ABSOLUTE + (PORT datab (105:105:105) (134:134:134)) + (PORT datad (324:324:324) (373:373:373)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2789:2789:2789) (2490:2490:2490)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (183:183:183)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2789:2789:2789) (2490:2490:2490)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (182:182:182)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2789:2789:2789) (2490:2490:2490)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2789:2789:2789) (2490:2490:2490)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (192:192:192)) + (PORT datab (137:137:137) (187:187:187)) + (PORT datac (124:124:124) (168:168:168)) + (PORT datad (124:124:124) (164:164:164)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (120:120:120) (163:163:163)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (489:489:489) (577:577:577)) + (PORT datac (424:424:424) (479:479:479)) + (PORT datad (415:415:415) (470:470:470)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|add_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (135:135:135) (171:171:171)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|add_flag) + (DELAY + (ABSOLUTE + (PORT clk (1068:1068:1068) (1098:1098:1098)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3084:3084:3084) (2737:2737:2737)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (377:377:377) (459:459:459)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2920:2920:2920) (2600:2600:2600)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (377:377:377) (458:458:458)) + (PORT datad (161:161:161) (219:219:219)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2920:2920:2920) (2600:2600:2600)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (178:178:178) (250:250:250)) + (PORT datab (378:378:378) (459:459:459)) + (PORT datad (151:151:151) (203:203:203)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2920:2920:2920) (2600:2600:2600)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (179:179:179) (251:251:251)) + (PORT datab (166:166:166) (228:228:228)) + (PORT datac (362:362:362) (438:438:438)) + (PORT datad (154:154:154) (205:205:205)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT datad (91:91:91) (108:108:108)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2920:2920:2920) (2600:2600:2600)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (247:247:247)) + (PORT datab (161:161:161) (220:220:220)) + (PORT datac (148:148:148) (204:204:204)) + (PORT datad (148:148:148) (199:199:199)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2920:2920:2920) (2600:2600:2600)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2934:2934:2934) (2613:2613:2613)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (180:180:180) (252:252:252)) + (PORT datab (160:160:160) (218:218:218)) + (PORT datac (149:149:149) (207:207:207)) + (PORT datad (155:155:155) (206:206:206)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2920:2920:2920) (2600:2600:2600)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (285:285:285)) + (PORT datab (213:213:213) (266:266:266)) + (PORT datac (117:117:117) (159:159:159)) + (PORT datad (219:219:219) (268:268:268)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (236:236:236) (291:291:291)) + (PORT datac (118:118:118) (160:160:160)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~2) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (196:196:196)) + (PORT datab (146:146:146) (199:199:199)) + (PORT datac (132:132:132) (180:180:180)) + (PORT datad (172:172:172) (203:203:203)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (180:180:180) (252:252:252)) + (PORT datab (160:160:160) (218:218:218)) + (PORT datac (149:149:149) (206:206:206)) + (PORT datad (154:154:154) (205:205:205)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2920:2920:2920) (2600:2600:2600)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (247:247:247)) + (PORT datab (162:162:162) (221:221:221)) + (PORT datac (148:148:148) (204:204:204)) + (PORT datad (146:146:146) (197:197:197)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2920:2920:2920) (2600:2600:2600)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (247:247:247)) + (PORT datab (162:162:162) (221:221:221)) + (PORT datac (148:148:148) (205:205:205)) + (PORT datad (145:145:145) (195:195:195)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2920:2920:2920) (2600:2600:2600)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (286:286:286)) + (PORT datab (235:235:235) (291:291:291)) + (PORT datac (120:120:120) (161:161:161)) + (PORT datad (121:121:121) (158:158:158)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (182:182:182) (253:253:253)) + (PORT datab (161:161:161) (219:219:219)) + (PORT datac (151:151:151) (208:208:208)) + (PORT datad (156:156:156) (208:208:208)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2920:2920:2920) (2600:2600:2600)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (285:285:285)) + (PORT datab (132:132:132) (181:181:181)) + (PORT datac (92:92:92) (115:115:115)) + (PORT datad (120:120:120) (158:158:158)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~1) + (DELAY + (ABSOLUTE + (PORT datab (145:145:145) (199:199:199)) + (PORT datac (133:133:133) (183:183:183)) + (PORT datad (163:163:163) (192:192:192)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~3) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|ds) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2934:2934:2934) (2613:2613:2613)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_modelsim.xrf b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_modelsim.xrf new file mode 100644 index 0000000..ce539a9 --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_modelsim.xrf @@ -0,0 +1,135 @@ +vendor_name = ModelSim +source_file = 1, E:/simiao/lc/A415/03_smg595/smg595_static/smg595_static/sim/tb_seg_595_static.v +source_file = 1, E:/simiao/lc/A415/03_smg595/smg595_static/smg595_static/rtl/seg_static.v +source_file = 1, E:/simiao/lc/A415/03_smg595/smg595_static/smg595_static/rtl/seg_595_static.v +source_file = 1, E:/simiao/lc/A415/03_smg595/smg595_static/smg595_static/rtl/hc595_ctrl.v +source_file = 1, output_files/Chain1.cdf +source_file = 1, E:/simiao/lc/A415/03_smg595/smg595_static/smg595_static/quartus_prj/db/seg_595_static.cbx.xml +design_name = seg_595_static +instance = comp, \seg_static_inst|Add0~4 , seg_static_inst|Add0~4, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~14 , seg_static_inst|Add0~14, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~18 , seg_static_inst|Add0~18, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~20 , seg_static_inst|Add0~20, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~22 , seg_static_inst|Add0~22, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~24 , seg_static_inst|Add0~24, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~26 , seg_static_inst|Add0~26, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~28 , seg_static_inst|Add0~28, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~30 , seg_static_inst|Add0~30, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~32 , seg_static_inst|Add0~32, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~34 , seg_static_inst|Add0~34, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~36 , seg_static_inst|Add0~36, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~38 , seg_static_inst|Add0~38, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~40 , seg_static_inst|Add0~40, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~42 , seg_static_inst|Add0~42, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~44 , seg_static_inst|Add0~44, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~46 , seg_static_inst|Add0~46, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|ds~0 , hc595_ctrl_inst|ds~0, seg_595_static, 1 +instance = comp, \seg_static_inst|seg[4] , seg_static_inst|seg[4], seg_595_static, 1 +instance = comp, \seg_static_inst|WideOr2~0 , seg_static_inst|WideOr2~0, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[24] , seg_static_inst|cnt_wait[24], seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[23] , seg_static_inst|cnt_wait[23], seg_595_static, 1 +instance = comp, \seg_static_inst|Equal0~0 , seg_static_inst|Equal0~0, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[22] , seg_static_inst|cnt_wait[22], seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[21] , seg_static_inst|cnt_wait[21], seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[20] , seg_static_inst|cnt_wait[20], seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[19] , seg_static_inst|cnt_wait[19], seg_595_static, 1 +instance = comp, \seg_static_inst|Equal0~1 , seg_static_inst|Equal0~1, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[18] , seg_static_inst|cnt_wait[18], seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[16] , seg_static_inst|cnt_wait[16], seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[17] , seg_static_inst|cnt_wait[17], seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[15] , seg_static_inst|cnt_wait[15], seg_595_static, 1 +instance = comp, \seg_static_inst|Equal0~2 , seg_static_inst|Equal0~2, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[14] , seg_static_inst|cnt_wait[14], seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[13] , seg_static_inst|cnt_wait[13], seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[12] , seg_static_inst|cnt_wait[12], seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[11] , seg_static_inst|cnt_wait[11], seg_595_static, 1 +instance = comp, \seg_static_inst|Equal0~3 , seg_static_inst|Equal0~3, seg_595_static, 1 +instance = comp, \seg_static_inst|Equal0~4 , seg_static_inst|Equal0~4, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[8] , seg_static_inst|cnt_wait[8], seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[3] , seg_static_inst|cnt_wait[3], seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait~0 , seg_static_inst|cnt_wait~0, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait~1 , seg_static_inst|cnt_wait~1, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait~2 , seg_static_inst|cnt_wait~2, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait~3 , seg_static_inst|cnt_wait~3, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait~4 , seg_static_inst|cnt_wait~4, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait~5 , seg_static_inst|cnt_wait~5, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait~6 , seg_static_inst|cnt_wait~6, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait~7 , seg_static_inst|cnt_wait~7, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait~8 , seg_static_inst|cnt_wait~8, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait~9 , seg_static_inst|cnt_wait~9, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait~10 , seg_static_inst|cnt_wait~10, seg_595_static, 1 +instance = comp, \stcp~output , stcp~output, seg_595_static, 1 +instance = comp, \shcp~output , shcp~output, seg_595_static, 1 +instance = comp, \ds~output , ds~output, seg_595_static, 1 +instance = comp, \oe~output , oe~output, seg_595_static, 1 +instance = comp, \sys_clk~input , sys_clk~input, seg_595_static, 1 +instance = comp, \sys_clk~inputclkctrl , sys_clk~inputclkctrl, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|cnt_4[0]~0 , hc595_ctrl_inst|cnt_4[0]~0, seg_595_static, 1 +instance = comp, \sys_rst_n~input , sys_rst_n~input, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|cnt_4[0] , hc595_ctrl_inst|cnt_4[0], seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|cnt_bit[0]~1 , hc595_ctrl_inst|cnt_bit[0]~1, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|cnt_bit[0] , hc595_ctrl_inst|cnt_bit[0], seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|cnt_bit[1]~0 , hc595_ctrl_inst|cnt_bit[1]~0, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|cnt_bit[1] , hc595_ctrl_inst|cnt_bit[1], seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|always2~0 , hc595_ctrl_inst|always2~0, seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~0 , seg_static_inst|Add0~0, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|cnt_4[1] , hc595_ctrl_inst|cnt_4[1], seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|Equal1~0 , hc595_ctrl_inst|Equal1~0, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|cnt_bit[3]~2 , hc595_ctrl_inst|cnt_bit[3]~2, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|cnt_bit[3] , hc595_ctrl_inst|cnt_bit[3], seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|always2~1 , hc595_ctrl_inst|always2~1, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|stcp~feeder , hc595_ctrl_inst|stcp~feeder, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|stcp , hc595_ctrl_inst|stcp, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|shcp , hc595_ctrl_inst|shcp, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|cnt_bit[2]~3 , hc595_ctrl_inst|cnt_bit[2]~3, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|cnt_bit[2] , hc595_ctrl_inst|cnt_bit[2], seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~2 , seg_static_inst|Add0~2, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[2] , seg_static_inst|cnt_wait[2], seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~6 , seg_static_inst|Add0~6, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[4] , seg_static_inst|cnt_wait[4], seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~8 , seg_static_inst|Add0~8, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[5] , seg_static_inst|cnt_wait[5], seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~10 , seg_static_inst|Add0~10, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait~11 , seg_static_inst|cnt_wait~11, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[6] , seg_static_inst|cnt_wait[6], seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~12 , seg_static_inst|Add0~12, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[7] , seg_static_inst|cnt_wait[7], seg_595_static, 1 +instance = comp, \seg_static_inst|Add0~16 , seg_static_inst|Add0~16, seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[9] , seg_static_inst|cnt_wait[9], seg_595_static, 1 +instance = comp, \seg_static_inst|cnt_wait[10] , seg_static_inst|cnt_wait[10], seg_595_static, 1 +instance = comp, \seg_static_inst|Equal0~5 , seg_static_inst|Equal0~5, seg_595_static, 1 +instance = comp, \seg_static_inst|Equal0~6 , seg_static_inst|Equal0~6, seg_595_static, 1 +instance = comp, \seg_static_inst|Equal0~7 , seg_static_inst|Equal0~7, seg_595_static, 1 +instance = comp, \seg_static_inst|add_flag~feeder , seg_static_inst|add_flag~feeder, seg_595_static, 1 +instance = comp, \seg_static_inst|add_flag , seg_static_inst|add_flag, seg_595_static, 1 +instance = comp, \seg_static_inst|num[0]~0 , seg_static_inst|num[0]~0, seg_595_static, 1 +instance = comp, \seg_static_inst|num[0] , seg_static_inst|num[0], seg_595_static, 1 +instance = comp, \seg_static_inst|num[1]~1 , seg_static_inst|num[1]~1, seg_595_static, 1 +instance = comp, \seg_static_inst|num[1] , seg_static_inst|num[1], seg_595_static, 1 +instance = comp, \seg_static_inst|num[2]~2 , seg_static_inst|num[2]~2, seg_595_static, 1 +instance = comp, \seg_static_inst|num[2] , seg_static_inst|num[2], seg_595_static, 1 +instance = comp, \seg_static_inst|num[3]~3 , seg_static_inst|num[3]~3, seg_595_static, 1 +instance = comp, \seg_static_inst|num[3]~4 , seg_static_inst|num[3]~4, seg_595_static, 1 +instance = comp, \seg_static_inst|num[3] , seg_static_inst|num[3], seg_595_static, 1 +instance = comp, \seg_static_inst|WideOr1~0 , seg_static_inst|WideOr1~0, seg_595_static, 1 +instance = comp, \seg_static_inst|seg[5] , seg_static_inst|seg[5], seg_595_static, 1 +instance = comp, \seg_static_inst|seg[7]~feeder , seg_static_inst|seg[7]~feeder, seg_595_static, 1 +instance = comp, \seg_static_inst|seg[7] , seg_static_inst|seg[7], seg_595_static, 1 +instance = comp, \seg_static_inst|WideOr0~0 , seg_static_inst|WideOr0~0, seg_595_static, 1 +instance = comp, \seg_static_inst|seg[6] , seg_static_inst|seg[6], seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|Mux0~2 , hc595_ctrl_inst|Mux0~2, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|Mux0~3 , hc595_ctrl_inst|Mux0~3, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|ds~2 , hc595_ctrl_inst|ds~2, seg_595_static, 1 +instance = comp, \seg_static_inst|WideOr4~0 , seg_static_inst|WideOr4~0, seg_595_static, 1 +instance = comp, \seg_static_inst|seg[2] , seg_static_inst|seg[2], seg_595_static, 1 +instance = comp, \seg_static_inst|WideOr3~0 , seg_static_inst|WideOr3~0, seg_595_static, 1 +instance = comp, \seg_static_inst|seg[3] , seg_static_inst|seg[3], seg_595_static, 1 +instance = comp, \seg_static_inst|WideOr5~0 , seg_static_inst|WideOr5~0, seg_595_static, 1 +instance = comp, \seg_static_inst|seg[1] , seg_static_inst|seg[1], seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|Mux0~0 , hc595_ctrl_inst|Mux0~0, seg_595_static, 1 +instance = comp, \seg_static_inst|WideOr6~0 , seg_static_inst|WideOr6~0, seg_595_static, 1 +instance = comp, \seg_static_inst|seg[0] , seg_static_inst|seg[0], seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|Mux0~1 , hc595_ctrl_inst|Mux0~1, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|ds~1 , hc595_ctrl_inst|ds~1, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|ds~3 , hc595_ctrl_inst|ds~3, seg_595_static, 1 +instance = comp, \hc595_ctrl_inst|ds , hc595_ctrl_inst|ds, seg_595_static, 1 diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_v.sdo b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_v.sdo new file mode 100644 index 0000000..7f4cf64 --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/quartus_prj/simulation/modelsim/seg_595_static_v.sdo @@ -0,0 +1,1858 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "seg_595_static") + (DATE "06/02/2023 20:55:14") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (433:433:433)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (432:432:432)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (429:429:429)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~20) + (DELAY + (ABSOLUTE + (PORT datab (940:940:940) (921:921:921)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~22) + (DELAY + (ABSOLUTE + (PORT datab (984:984:984) (971:971:971)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~24) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (450:450:450)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~26) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (611:611:611)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~28) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~30) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~32) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~34) + (DELAY + (ABSOLUTE + (PORT datab (572:572:572) (603:603:603)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~36) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~38) + (DELAY + (ABSOLUTE + (PORT datab (628:628:628) (632:632:632)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~40) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~42) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (611:611:611)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~44) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~46) + (DELAY + (ABSOLUTE + (PORT datad (539:539:539) (559:559:559)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~0) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (647:647:647)) + (PORT datac (558:558:558) (595:595:595)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (560:560:560)) + (PORT datab (386:386:386) (503:503:503)) + (PORT datac (352:352:352) (467:467:467)) + (PORT datad (369:369:369) (466:466:466)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[24\]) + (DELAY + (ABSOLUTE + (PORT clk (2328:2328:2328) (2322:2322:2322)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5733:5733:5733) (5447:5447:5447)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (939:939:939)) + (PORT datab (615:615:615) (619:619:619)) + (PORT datac (876:876:876) (872:872:872)) + (PORT datad (322:322:322) (392:392:392)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5733:5733:5733) (5447:5447:5447)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5733:5733:5733) (5447:5447:5447)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (PORT datab (359:359:359) (436:436:436)) + (PORT datac (564:564:564) (579:579:579)) + (PORT datad (556:556:556) (569:569:569)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5733:5733:5733) (5447:5447:5447)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5733:5733:5733) (5447:5447:5447)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5733:5733:5733) (5447:5447:5447)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (595:595:595)) + (PORT datab (613:613:613) (617:617:617)) + (PORT datac (516:516:516) (547:547:547)) + (PORT datad (319:319:319) (389:389:389)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5733:5733:5733) (5447:5447:5447)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (642:642:642)) + (PORT datab (360:360:360) (436:436:436)) + (PORT datac (319:319:319) (396:396:396)) + (PORT datad (516:516:516) (534:534:534)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~0) + (DELAY + (ABSOLUTE + (PORT datac (319:319:319) (381:381:381)) + (PORT datad (438:438:438) (415:415:415)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~1) + (DELAY + (ABSOLUTE + (PORT datac (319:319:319) (381:381:381)) + (PORT datad (437:437:437) (414:414:414)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~2) + (DELAY + (ABSOLUTE + (PORT datac (554:554:554) (540:540:540)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~3) + (DELAY + (ABSOLUTE + (PORT datac (319:319:319) (381:381:381)) + (PORT datad (447:447:447) (410:410:410)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~4) + (DELAY + (ABSOLUTE + (PORT datac (554:554:554) (541:541:541)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~5) + (DELAY + (ABSOLUTE + (PORT datac (319:319:319) (383:383:383)) + (PORT datad (469:469:469) (437:437:437)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~6) + (DELAY + (ABSOLUTE + (PORT datac (554:554:554) (541:541:541)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~7) + (DELAY + (ABSOLUTE + (PORT datac (319:319:319) (381:381:381)) + (PORT datad (468:468:468) (435:435:435)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~8) + (DELAY + (ABSOLUTE + (PORT datac (555:555:555) (541:541:541)) + (PORT datad (241:241:241) (260:260:260)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~9) + (DELAY + (ABSOLUTE + (PORT datac (319:319:319) (381:381:381)) + (PORT datad (739:739:739) (665:665:665)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~10) + (DELAY + (ABSOLUTE + (PORT datab (365:365:365) (423:423:423)) + (PORT datac (829:829:829) (765:765:765)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE stcp\~output) + (DELAY + (ABSOLUTE + (PORT i (1656:1656:1656) (1618:1618:1618)) + (IOPATH i o (3449:3449:3449) (3386:3386:3386)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE shcp\~output) + (DELAY + (ABSOLUTE + (PORT i (1872:1872:1872) (1788:1788:1788)) + (IOPATH i o (3429:3429:3429) (3366:3366:3366)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE ds\~output) + (DELAY + (ABSOLUTE + (PORT i (2238:2238:2238) (2101:2101:2101)) + (IOPATH i o (3439:3439:3439) (3376:3376:3376)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE oe\~output) + (DELAY + (ABSOLUTE + (PORT i (4546:4546:4546) (4318:4318:4318)) + (IOPATH i o (3376:3376:3376) (3439:3439:3439)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (806:806:806) (852:852:852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sys_clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (200:200:200) (189:189:189)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_4\[0\]\~0) + (DELAY + (ABSOLUTE + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_4\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (649:649:649)) + (PORT datab (602:602:602) (636:636:636)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5984:5984:5984) (5729:5729:5729)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (367:367:367)) + (PORT datab (371:371:371) (453:453:453)) + (PORT datad (245:245:245) (266:266:266)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5984:5984:5984) (5729:5729:5729)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|always2\~0) + (DELAY + (ABSOLUTE + (PORT datac (328:328:328) (413:413:413)) + (PORT datad (323:323:323) (394:394:394)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (444:444:444)) + (PORT datab (358:358:358) (435:435:435)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_4\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT datac (560:560:560) (597:597:597)) + (PORT datad (556:556:556) (596:596:596)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (464:464:464)) + (PORT datab (298:298:298) (330:330:330)) + (PORT datad (467:467:467) (441:441:441)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5984:5984:5984) (5729:5729:5729)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|always2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (460:460:460)) + (PORT datab (361:361:361) (457:457:457)) + (PORT datac (281:281:281) (320:320:320)) + (PORT datad (259:259:259) (289:289:289)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|stcp\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (248:248:248) (270:270:270)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|stcp) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5984:5984:5984) (5729:5729:5729)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|shcp) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT asdata (1335:1335:1335) (1325:1325:1325)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (367:367:367)) + (PORT datab (362:362:362) (458:458:458)) + (PORT datad (259:259:259) (289:289:289)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|cnt_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5984:5984:5984) (5729:5729:5729)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (444:444:444)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (420:420:420)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|cnt_wait\~11) + (DELAY + (ABSOLUTE + (PORT datab (279:279:279) (304:304:304)) + (PORT datad (833:833:833) (788:788:788)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (419:419:419)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|cnt_wait\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1837:1837:1837) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5691:5691:5691) (5408:5408:5408)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (343:343:343) (425:425:425)) + (PORT datac (304:304:304) (388:388:388)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (299:299:299) (383:383:383)) + (PORT datad (303:303:303) (379:379:379)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|Equal0\~7) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (1288:1288:1288) (1220:1220:1220)) + (PORT datac (1102:1102:1102) (999:999:999)) + (PORT datad (1098:1098:1098) (983:983:983)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|add_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (319:319:319) (381:381:381)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|add_flag) + (DELAY + (ABSOLUTE + (PORT clk (2328:2328:2328) (2322:2322:2322)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6313:6313:6313) (6092:6092:6092)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (968:968:968) (969:969:969)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (968:968:968) (969:969:969)) + (PORT datad (368:368:368) (496:496:496)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (558:558:558)) + (PORT datab (969:969:969) (970:970:970)) + (PORT datad (363:363:363) (460:460:460)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (558:558:558)) + (PORT datab (396:396:396) (508:508:508)) + (PORT datac (926:926:926) (932:932:932)) + (PORT datad (365:365:365) (462:462:462)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|num\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT datad (239:239:239) (257:257:257)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (556:556:556)) + (PORT datab (387:387:387) (504:504:504)) + (PORT datac (351:351:351) (465:465:465)) + (PORT datad (361:361:361) (457:457:457)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5984:5984:5984) (5729:5729:5729)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (418:418:418) (559:559:559)) + (PORT datab (386:386:386) (504:504:504)) + (PORT datac (352:352:352) (467:467:467)) + (PORT datad (368:368:368) (464:464:464)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (631:631:631)) + (PORT datab (571:571:571) (592:592:592)) + (PORT datac (294:294:294) (371:371:371)) + (PORT datad (574:574:574) (597:597:597)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (419:419:419)) + (PORT datab (633:633:633) (644:644:644)) + (PORT datac (295:295:295) (373:373:373)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~2) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (449:449:449)) + (PORT datab (360:360:360) (456:456:456)) + (PORT datac (318:318:318) (414:414:414)) + (PORT datad (481:481:481) (449:449:449)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (559:559:559)) + (PORT datab (386:386:386) (504:504:504)) + (PORT datac (352:352:352) (467:467:467)) + (PORT datad (367:367:367) (463:463:463)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (555:555:555)) + (PORT datab (387:387:387) (505:505:505)) + (PORT datac (351:351:351) (465:465:465)) + (PORT datad (359:359:359) (455:455:455)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (555:555:555)) + (PORT datab (387:387:387) (505:505:505)) + (PORT datac (350:350:350) (465:465:465)) + (PORT datad (358:358:358) (454:454:454)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (632:632:632)) + (PORT datab (632:632:632) (643:643:643)) + (PORT datac (296:296:296) (374:374:374)) + (PORT datad (297:297:297) (368:368:368)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE seg_static_inst\|WideOr6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (419:419:419) (561:561:561)) + (PORT datab (386:386:386) (503:503:503)) + (PORT datac (352:352:352) (467:467:467)) + (PORT datad (370:370:370) (467:467:467)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE seg_static_inst\|seg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5952:5952:5952) (5689:5689:5689)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (631:631:631)) + (PORT datab (335:335:335) (412:412:412)) + (PORT datac (239:239:239) (265:265:265)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~1) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (456:456:456)) + (PORT datac (320:320:320) (417:417:417)) + (PORT datad (450:450:450) (428:428:428)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hc595_ctrl_inst\|ds\~3) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (315:315:315)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datad (240:240:240) (258:258:258)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hc595_ctrl_inst\|ds) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5984:5984:5984) (5729:5729:5729)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/hc595_ctrl.v b/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/hc595_ctrl.v new file mode 100644 index 0000000..de9190d --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/hc595_ctrl.v @@ -0,0 +1,99 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/07/11 +// Module Name : hc595_ctrl +// Project Name : seg_595_static +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : 595控制模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// +module hc595_ctrl +( + input wire sys_clk , //系统时钟，频率50MHz + input wire sys_rst_n , //复位信号，低有效 + input wire [3:0] sel , //数码管位选信号 + input wire [7:0] seg , //数码管段选信号 + + output reg stcp , //数据存储器时钟 + output reg shcp , //移位寄存器时钟 + output reg ds , //串行数据输入 + output wire oe //使能信号，低有效 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//reg define +reg [1:0] cnt_4 ; //分频计数器 +reg [3:0] cnt_bit ; //传输位数计数器 + +//wire define +wire [11:0] data ; //数码管信号寄存 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +//将数码管信号寄存 +assign data = {seg[0],seg[1],seg[2],seg[3],seg[4],seg[5],seg[6],seg[7],sel}; + +//将复位取反后赋值给其即可 +assign oe = ~sys_rst_n; + +//分频计数器:0~3循环计数 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_4 <= 2'd0; + else if(cnt_4 == 2'd3) + cnt_4 <= 2'd0; + else + cnt_4 <= cnt_4 + 1'b1; + +//cnt_bit:每输入一位数据加一 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_bit <= 4'd0; + else if(cnt_4 == 2'd3 && cnt_bit == 4'd11) + cnt_bit <= 4'd0; + else if(cnt_4 == 2'd3) + cnt_bit <= cnt_bit + 1'b1; + else + cnt_bit <= cnt_bit; + +//stcp:12个信号传输完成之后产生一个上升沿 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + stcp <= 1'b0; + else if(cnt_bit == 4'd11 && cnt_4 == 2'd3) + stcp <= 1'b1; + else + stcp <= 1'b0; + +//shcp:产生四分频移位时钟 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + shcp <= 1'b0; + else if(cnt_4 >= 4'd2) + shcp <= 1'b1; + else + shcp <= 1'b0; + +//ds:将寄存器里存储的数码管信号输入即 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + ds <= 1'b0; + else if(cnt_4 == 2'd0) + ds <= data[cnt_bit]; + else + ds <= ds; + +endmodule diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/hc595_ctrl.v.bak b/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/hc595_ctrl.v.bak new file mode 100644 index 0000000..cd9b0e1 --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/hc595_ctrl.v.bak @@ -0,0 +1,99 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/07/11 +// Module Name : hc595_ctrl +// Project Name : seg_595_static +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : 595控制模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// +module hc595_ctrl +( + input wire sys_clk , //系统时钟，频率50MHz + input wire sys_rst_n , //复位信号，低有效 + input wire [5:0] sel , //数码管位选信号 + input wire [7:0] seg , //数码管段选信号 + + output reg stcp , //数据存储器时钟 + output reg shcp , //移位寄存器时钟 + output reg ds , //串行数据输入 + output wire oe //使能信号，低有效 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//reg define +reg [1:0] cnt_4 ; //分频计数器 +reg [3:0] cnt_bit ; //传输位数计数器 + +//wire define +wire [13:0] data ; //数码管信号寄存 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +//将数码管信号寄存 +assign data = {seg[0],seg[1],seg[2],seg[3],seg[4],seg[5],seg[6],seg[7],sel}; + +//将复位取反后赋值给其即可 +assign oe = ~sys_rst_n; + +//分频计数器:0~3循环计数 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_4 <= 2'd0; + else if(cnt_4 == 2'd3) + cnt_4 <= 2'd0; + else + cnt_4 <= cnt_4 + 1'b1; + +//cnt_bit:每输入一位数据加一 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_bit <= 4'd0; + else if(cnt_4 == 2'd3 && cnt_bit == 4'd13) + cnt_bit <= 4'd0; + else if(cnt_4 == 2'd3) + cnt_bit <= cnt_bit + 1'b1; + else + cnt_bit <= cnt_bit; + +//stcp:14个信号传输完成之后产生一个上升沿 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + stcp <= 1'b0; + else if(cnt_bit == 4'd13 && cnt_4 == 2'd3) + stcp <= 1'b1; + else + stcp <= 1'b0; + +//shcp:产生四分频移位时钟 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + shcp <= 1'b0; + else if(cnt_4 >= 4'd2) + shcp <= 1'b1; + else + shcp <= 1'b0; + +//ds:将寄存器里存储的数码管信号输入即 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + ds <= 1'b0; + else if(cnt_4 == 2'd0) + ds <= data[cnt_bit]; + else + ds <= ds; + +endmodule diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/seg_595_static.v b/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/seg_595_static.v new file mode 100644 index 0000000..04365a7 --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/seg_595_static.v @@ -0,0 +1,65 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/07/11 +// Module Name : seg_595_static +// Project Name : seg_595_static +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : 静态数码管顶层模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module seg_595_static +( + input wire sys_clk , //系统时钟，频率50MHz + input wire sys_rst_n , //复位信号，低有效 + + output wire stcp , //输出数据存储寄时钟 + output wire shcp , //移位寄存器的时钟输入 + output wire ds , //串行数据输入 + output wire oe //输出使能信号 +); + +//********************************************************************// +//******************** Parameter And Internal Signal *****************// +//********************************************************************// +//wire define +wire [3:0] sel; +wire [7:0] seg; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// +//---------- seg_static_inst ---------- +seg_static seg_static_inst +( + .sys_clk (sys_clk ), //系统时钟，频率50MHz + .sys_rst_n (sys_rst_n ), //复位信号，低电平有效 + + .sel (sel ), //数码管位选信号 + .seg (seg ) //数码管段选信号 +); + +//---------- hc595_ctrl_inst ---------- +hc595_ctrl hc595_ctrl_inst +( + .sys_clk (sys_clk ), //系统时钟，频率50MHz + .sys_rst_n (sys_rst_n), //复位信号，低有效 + .sel (sel ), //数码管位选信号 + .seg (seg ), //数码管段选信号 + + .stcp (stcp ), //输出数据存储寄时钟 + .shcp (shcp ), //移位寄存器的时钟输入 + .ds (ds ), //串行数据输入 + .oe (oe ) //输出使能信号 +); + +endmodule diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/seg_595_static.v.bak b/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/seg_595_static.v.bak new file mode 100644 index 0000000..6d07f57 --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/seg_595_static.v.bak @@ -0,0 +1,65 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/07/11 +// Module Name : seg_595_static +// Project Name : seg_595_static +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : 静态数码管顶层模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module seg_595_static +( + input wire sys_clk , //系统时钟，频率50MHz + input wire sys_rst_n , //复位信号，低有效 + + output wire stcp , //输出数据存储寄时钟 + output wire shcp , //移位寄存器的时钟输入 + output wire ds , //串行数据输入 + output wire oe //输出使能信号 +); + +//********************************************************************// +//******************** Parameter And Internal Signal *****************// +//********************************************************************// +//wire define +wire [5:0] sel; +wire [7:0] seg; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// +//---------- seg_static_inst ---------- +seg_static seg_static_inst +( + .sys_clk (sys_clk ), //系统时钟，频率50MHz + .sys_rst_n (sys_rst_n ), //复位信号，低电平有效 + + .sel (sel ), //数码管位选信号 + .seg (seg ) //数码管段选信号 +); + +//---------- hc595_ctrl_inst ---------- +hc595_ctrl hc595_ctrl_inst +( + .sys_clk (sys_clk ), //系统时钟，频率50MHz + .sys_rst_n (sys_rst_n), //复位信号，低有效 + .sel (sel ), //数码管位选信号 + .seg (seg ), //数码管段选信号 + + .stcp (stcp ), //输出数据存储寄时钟 + .shcp (shcp ), //移位寄存器的时钟输入 + .ds (ds ), //串行数据输入 + .oe (oe ) //输出使能信号 +); + +endmodule diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/seg_static.v b/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/seg_static.v new file mode 100644 index 0000000..062e6ac --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/seg_static.v @@ -0,0 +1,123 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/07/08 +// Module Name : seg7_static +// Project Name : seg7_static +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : 静态数码管显示 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module seg_static +( + input wire sys_clk , //系统时钟，频率50MHz + input wire sys_rst_n , //复位信号，低电平有效 + + output reg [3:0] sel , //数码管位选信号 + output reg [7:0] seg //数码管段选信号 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter CNT_WAIT_MAX = 25'd24_999_999; //计数器最大值（0.5s） +//十六进制数显示编码 +parameter SEG_0 = 8'b1100_0000, SEG_1 = 8'b1111_1001, + SEG_2 = 8'b1010_0100, SEG_3 = 8'b1011_0000, + SEG_4 = 8'b1001_1001, SEG_5 = 8'b1001_0010, + SEG_6 = 8'b1000_0010, SEG_7 = 8'b1111_1000, + SEG_8 = 8'b1000_0000, SEG_9 = 8'b1001_0000, + SEG_A = 8'b1000_1000, SEG_B = 8'b1000_0011, + SEG_C = 8'b1100_0110, SEG_D = 8'b1010_0001, + SEG_E = 8'b1000_0110, SEG_F = 8'b1000_1110; + +/* +parameter SEG_0 = 8'b1100_0000, SEG_1 = 8'b1111_1001, + SEG_2 = 8'b1010_0100, SEG_3 = 8'b1011_0000, + SEG_4 = 8'b1001_1001, SEG_5 = 8'b1001_0010, + SEG_6 = 8'b1000_0010, SEG_7 = 8'b1111_1000, + SEG_8 = 8'b1000_0000, SEG_9 = 8'b1001_0000, + SEG_A = 8'b1000_1000, SEG_B = 8'b1000_0011, + SEG_C = 8'b1100_0110, SEG_D = 8'b1010_0001, + SEG_E = 8'b1000_0110, SEG_F = 8'b1000_1110; + + */ +parameter IDLE = 8'b1111_1111; //不显示状态 + +//reg define +reg add_flag ; //数码管数值+1标志信号 +reg [24:0] cnt_wait ; //时钟分频计数器 +reg [3:0] num ; //数码管显示的十六进制数 + +//********************************************************************// +//*************************** Main Code ******************************// +//********************************************************************// +//cnt_wait：0.5秒计数 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_wait <= 25'd0; + else if(cnt_wait == CNT_WAIT_MAX) + cnt_wait <= 25'd0; + else + cnt_wait <= cnt_wait + 1'b1; + +//add_flag:0.5s拉高一个标志信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + add_flag <= 1'b0; + else if(cnt_wait == CNT_WAIT_MAX) + add_flag <= 1'b1; + else + add_flag <= 1'b0; + +//num：从 4'h0 加到 4'hf 循环 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + num <= 4'd0; + else if(add_flag == 1'b1) + num <= num + 1'b1; + else + num <= num; + +//sel：选中四个数码管 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + sel <= 4'b1111; + else + sel <= 4'b0000; + +//给要显示的值编码 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + seg <= IDLE; + else case(num) + 4'd0: seg <= ~SEG_0; + 4'd1: seg <= ~SEG_1; + 4'd2: seg <= ~SEG_2; + 4'd3: seg <= ~SEG_3; + 4'd4: seg <= ~SEG_4; + 4'd5: seg <= ~SEG_5; + 4'd6: seg <= ~SEG_6; + 4'd7: seg <= ~SEG_7; + 4'd8: seg <= ~SEG_8; + 4'd9: seg <= ~SEG_9; + 4'd10: seg <= ~SEG_A; + 4'd11: seg <= ~SEG_B; + 4'd12: seg <= ~SEG_C; + 4'd13: seg <= ~SEG_D; + 4'd14: seg <= ~SEG_E; + 4'd15: seg <= ~SEG_F; + default:seg <= IDLE ; //闲置状态，不显示 + endcase + +endmodule diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/seg_static.v.bak b/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/seg_static.v.bak new file mode 100644 index 0000000..3c1e6fc --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/rtl/seg_static.v.bak @@ -0,0 +1,111 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/07/08 +// Module Name : seg7_static +// Project Name : seg7_static +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : 静态数码管显示 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module seg_static +( + input wire sys_clk , //系统时钟，频率50MHz + input wire sys_rst_n , //复位信号，低电平有效 + + output reg [5:0] sel , //数码管位选信号 + output reg [7:0] seg //数码管段选信号 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter CNT_WAIT_MAX = 25'd24_999_999; //计数器最大值（0.5s） +//十六进制数显示编码 +parameter SEG_0 = 8'b1100_0000, SEG_1 = 8'b1111_1001, + SEG_2 = 8'b1010_0100, SEG_3 = 8'b1011_0000, + SEG_4 = 8'b1001_1001, SEG_5 = 8'b1001_0010, + SEG_6 = 8'b1000_0010, SEG_7 = 8'b1111_1000, + SEG_8 = 8'b1000_0000, SEG_9 = 8'b1001_0000, + SEG_A = 8'b1000_1000, SEG_B = 8'b1000_0011, + SEG_C = 8'b1100_0110, SEG_D = 8'b1010_0001, + SEG_E = 8'b1000_0110, SEG_F = 8'b1000_1110; +parameter IDLE = 8'b1111_1111; //不显示状态 + +//reg define +reg add_flag ; //数码管数值+1标志信号 +reg [24:0] cnt_wait ; //时钟分频计数器 +reg [3:0] num ; //数码管显示的十六进制数 + +//********************************************************************// +//*************************** Main Code ******************************// +//********************************************************************// +//cnt_wait：0.5秒计数 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_wait <= 25'd0; + else if(cnt_wait == CNT_WAIT_MAX) + cnt_wait <= 25'd0; + else + cnt_wait <= cnt_wait + 1'b1; + +//add_flag:0.5s拉高一个标志信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + add_flag <= 1'b0; + else if(cnt_wait == CNT_WAIT_MAX) + add_flag <= 1'b1; + else + add_flag <= 1'b0; + +//num：从 4'h0 加到 4'hf 循环 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + num <= 4'd0; + else if(add_flag == 1'b1) + num <= num + 1'b1; + else + num <= num; + +//sel：选中六个数码管 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + sel <= 6'b000000; + else + sel <= 6'b111111; + +//给要显示的值编码 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + seg <= IDLE; + else case(num) + 4'd0: seg <= SEG_0; + 4'd1: seg <= SEG_1; + 4'd2: seg <= SEG_2; + 4'd3: seg <= SEG_3; + 4'd4: seg <= SEG_4; + 4'd5: seg <= SEG_5; + 4'd6: seg <= SEG_6; + 4'd7: seg <= SEG_7; + 4'd8: seg <= SEG_8; + 4'd9: seg <= SEG_9; + 4'd10: seg <= SEG_A; + 4'd11: seg <= SEG_B; + 4'd12: seg <= SEG_C; + 4'd13: seg <= SEG_D; + 4'd14: seg <= SEG_E; + 4'd15: seg <= SEG_F; + default:seg <= IDLE ; //闲置状态，不显示 + endcase + +endmodule diff --git a/smh-ac415-fpga/examples/03_smg595/smg595_static/sim/tb_seg_595_static.v b/smh-ac415-fpga/examples/03_smg595/smg595_static/sim/tb_seg_595_static.v new file mode 100644 index 0000000..4fd8ce3 --- /dev/null +++ b/smh-ac415-fpga/examples/03_smg595/smg595_static/sim/tb_seg_595_static.v @@ -0,0 +1,69 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/07/08 +// Module Name : tb_seg7_static +// Project Name : seg7_static +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : seg_led_static仿真文件 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module tb_seg_595_static(); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//wire define +wire stcp ; //输出数据存储寄时钟 +wire shcp ; //移位寄存器的时钟输入 +wire ds ; //串行数据输入 +wire oe ; //输出使能信号 + +//reg define +reg sys_clk ; +reg sys_rst_n ; + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//对sys_clk,sys_rst_n赋初始值 +initial + begin + sys_clk = 1'b1; + sys_rst_n <= 1'b0; + #100 + sys_rst_n <= 1'b1; + end + +//clk:产生时钟 +always #10 sys_clk <= ~sys_clk; + +//重新定义参数值，缩短仿真时间 +defparam seg_595_static_inst.seg_static_inst.CNT_WAIT_MAX = 10; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//-------------seg_595_static_inst------------- +seg_595_static seg_595_static_inst +( + .sys_clk (sys_clk ), //系统时钟，频率50MHz + .sys_rst_n (sys_rst_n ), //复位信号，低电平有效 + + .stcp (stcp ), //输出数据存储寄时钟 + .shcp (shcp ), //移位寄存器的时钟输入 + .ds (ds ), //串行数据输入 + .oe (oe ) //输出使能信号 +); + +endmodule diff --git "a/smh-ac415-fpga/examples/03_smg595/\345\256\236\351\252\214\347\216\260\350\261\241.txt" "b/smh-ac415-fpga/examples/03_smg595/\345\256\236\351\252\214\347\216\260\350\261\241.txt" new file mode 100644 index 0000000..b9581e2 --- /dev/null +++ "b/smh-ac415-fpga/examples/03_smg595/\345\256\236\351\252\214\347\216\260\350\261\241.txt" @@ -0,0 +1,2 @@ +现象：数码管依次显示0-9ABCDEF。 +测试：可以测试数码管是否正常。 \ No newline at end of file diff --git a/smh-ac415-fpga/examples/04_touch/touch/touch.qpf b/smh-ac415-fpga/examples/04_touch/touch/touch.qpf new file mode 100644 index 0000000..6a3b058 --- /dev/null +++ b/smh-ac415-fpga/examples/04_touch/touch/touch.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 02:54:06 June 02, 2023 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "02:54:06 June 02, 2023" + +# Revisions + +PROJECT_REVISION = "touch" diff --git a/smh-ac415-fpga/examples/04_touch/touch/touch.qsf b/smh-ac415-fpga/examples/04_touch/touch/touch.qsf new file mode 100644 index 0000000..9bfa3c8 --- /dev/null +++ b/smh-ac415-fpga/examples/04_touch/touch/touch.qsf @@ -0,0 +1,59 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 02:54:06 June 02, 2023 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# touch_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE15F23C8 +set_global_assignment -name TOP_LEVEL_ENTITY touch +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "02:54:06 JUNE 02, 2023" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name VERILOG_FILE touch.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_location_assignment PIN_AB16 -to led +set_location_assignment PIN_T22 -to sys_clk +set_location_assignment PIN_U20 -to sys_rst_n +set_location_assignment PIN_G9 -to touch_key +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/smh-ac415-fpga/examples/04_touch/touch/touch.qws b/smh-ac415-fpga/examples/04_touch/touch/touch.qws new file mode 100644 index 0000000..7232112 Binary files /dev/null and b/smh-ac415-fpga/examples/04_touch/touch/touch.qws differ diff --git a/smh-ac415-fpga/examples/04_touch/touch/touch.v b/smh-ac415-fpga/examples/04_touch/touch/touch.v new file mode 100644 index 0000000..dcf9d12 --- /dev/null +++ b/smh-ac415-fpga/examples/04_touch/touch/touch.v @@ -0,0 +1,38 @@ +`timescale 1ns/1ns + +module touch +( + input wire sys_clk , + input wire sys_rst_n , + input wire touch_key , + + output reg led +); + +wire touch_en ; + +//reg define +reg touch_key_dly1 ; +reg touch_key_dly2 ; + +assign touch_en = touch_key_dly2 & (~touch_key_dly1); + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + touch_key_dly1 <= 1'b0; + touch_key_dly2 <= 1'b0; + end + else + begin + touch_key_dly1 <= touch_key; + touch_key_dly2 <= touch_key_dly1; + end + +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + led <= 1'b1; + else if(touch_en == 1'b1) + led <= ~led; + +endmodule diff --git "a/smh-ac415-fpga/examples/04_touch/\345\256\236\351\252\214\347\216\260\350\261\241.txt" "b/smh-ac415-fpga/examples/04_touch/\345\256\236\351\252\214\347\216\260\350\261\241.txt" new file mode 100644 index 0000000..41b7e47 --- /dev/null +++ "b/smh-ac415-fpga/examples/04_touch/\345\256\236\351\252\214\347\216\260\350\261\241.txt" @@ -0,0 +1,2 @@ +现象：点按触摸按键，可以开关led灯。 +测试：可以测试触摸按键是否正常。 \ No newline at end of file diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/doc/rs232.vsdx b/smh-ac415-fpga/examples/05_rs232/rs232/doc/rs232.vsdx new file mode 100644 index 0000000..195deeb Binary files /dev/null and b/smh-ac415-fpga/examples/05_rs232/rs232/doc/rs232.vsdx differ diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qpf b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qpf new file mode 100644 index 0000000..6f228f9 --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 17:20:04 March 05, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "17:20:04 March 05, 2020" + +# Revisions + +PROJECT_REVISION = "rs232" diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qsf b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qsf new file mode 100644 index 0000000..6d675f3 --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qsf @@ -0,0 +1,92 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 17:20:04 March 05, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# rs232_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE15F23C8 +set_global_assignment -name TOP_LEVEL_ENTITY rs232 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:20:04 MARCH 05, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb_rs232 -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME tb_rs232 -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_rs232 +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_rs232 +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_rs232 -section_id tb_rs232 +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_rs232.v -section_id tb_rs232 +set_global_assignment -name EDA_TEST_BENCH_NAME tb_uart_rx -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_uart_rx +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_uart_rx +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_uart_rx -section_id tb_uart_rx +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_uart_rx.v -section_id tb_uart_rx +set_global_assignment -name EDA_TEST_BENCH_NAME tb_uart_tx -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_uart_tx +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_uart_tx +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_uart_tx -section_id tb_uart_tx +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_uart_tx.v -section_id tb_uart_tx + + +set_location_assignment PIN_T22 -to sys_clk +set_location_assignment PIN_U20 -to sys_rst_n + +set_location_assignment PIN_V1 -to rx +set_location_assignment PIN_U1 -to tx + +#set_location_assignment PIN_N6 -to rx +#set_location_assignment PIN_N5 -to tx + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name VERILOG_FILE ../sim/tb_uart_tx.v +set_global_assignment -name VERILOG_FILE ../sim/tb_uart_rx.v +set_global_assignment -name VERILOG_FILE ../sim/tb_rs232.v +set_global_assignment -name VERILOG_FILE ../rtl/uart_tx.v +set_global_assignment -name VERILOG_FILE ../rtl/uart_rx.v +set_global_assignment -name VERILOG_FILE ../rtl/rs232.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qws b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qws new file mode 100644 index 0000000..55fe5d0 Binary files /dev/null and b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232.qws differ diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232_assignment_defaults.qdf b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232_assignment_defaults.qdf new file mode 100644 index 0000000..3d59196 --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/rs232_assignment_defaults.qdf @@ -0,0 +1,805 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 02:59:42 June 02, 2023 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus II software and is used +# to preserve global assignments across Quartus II versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name SMART_RECOMPILE Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name DISABLE_OCP_HW_EVAL Off +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone IV GX" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria VI" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix VI" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix VI" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Cyclone +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy III" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "HardCopy IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria VI" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Arria GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Stratix +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria VI" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix VI" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name SYNTHESIS_SEED 1 +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria VI" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix VI" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000B +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix VI" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000AE +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Cyclone +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000S +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy III" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Arria VI" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX3000A +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Stratix +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto +set_global_assignment -name AUTO_PACKED_REGISTERS Off +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO +set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix VI" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "HardCopy III" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria VI" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria VI" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix VI" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232.sft b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232.sft new file mode 100644 index 0000000..ad21f32 --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232.sft @@ -0,0 +1,6 @@ +set tool_name "ModelSim (Verilog)" +set corner_file_list { + {{"Slow -8 1.2V 85 Model"} {rs232_8_1200mv_85c_slow.vo rs232_8_1200mv_85c_v_slow.sdo}} + {{"Slow -8 1.2V 0 Model"} {rs232_8_1200mv_0c_slow.vo rs232_8_1200mv_0c_v_slow.sdo}} + {{"Fast -M 1.2V 0 Model"} {rs232_min_1200mv_0c_fast.vo rs232_min_1200mv_0c_v_fast.sdo}} +} diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232.vo b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232.vo new file mode 100644 index 0000000..396965f --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232.vo @@ -0,0 +1,2836 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 03:03:50" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module rs232 ( + sys_clk, + sys_rst_n, + rx, + tx); +input sys_clk; +input sys_rst_n; +input rx; +output tx; + +// Design Ports Information +// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("rs232_v.sdo"); +// synopsys translate_on + +wire \uart_tx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|baud_cnt[0]~13_combout ; +wire \uart_rx_inst|baud_cnt[0]~14 ; +wire \uart_rx_inst|baud_cnt[1]~15_combout ; +wire \uart_rx_inst|baud_cnt[1]~16 ; +wire \uart_rx_inst|baud_cnt[2]~17_combout ; +wire \uart_rx_inst|baud_cnt[2]~18 ; +wire \uart_rx_inst|baud_cnt[3]~19_combout ; +wire \uart_rx_inst|baud_cnt[3]~20 ; +wire \uart_rx_inst|baud_cnt[4]~21_combout ; +wire \uart_rx_inst|baud_cnt[4]~22 ; +wire \uart_rx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|baud_cnt[5]~24 ; +wire \uart_rx_inst|baud_cnt[6]~25_combout ; +wire \uart_rx_inst|baud_cnt[6]~26 ; +wire \uart_rx_inst|baud_cnt[7]~27_combout ; +wire \uart_rx_inst|baud_cnt[7]~28 ; +wire \uart_rx_inst|baud_cnt[8]~29_combout ; +wire \uart_rx_inst|baud_cnt[8]~30 ; +wire \uart_rx_inst|baud_cnt[9]~31_combout ; +wire \uart_rx_inst|baud_cnt[9]~32 ; +wire \uart_rx_inst|baud_cnt[10]~33_combout ; +wire \uart_rx_inst|baud_cnt[10]~34 ; +wire \uart_rx_inst|baud_cnt[11]~35_combout ; +wire \uart_rx_inst|baud_cnt[11]~36 ; +wire \uart_rx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal2~0_combout ; +wire \uart_tx_inst|Add1~0_combout ; +wire \uart_tx_inst|Add1~1_combout ; +wire \uart_rx_inst|bit_flag~q ; +wire \uart_rx_inst|Equal1~0_combout ; +wire \uart_rx_inst|Equal2~0_combout ; +wire \uart_rx_inst|Equal2~1_combout ; +wire \uart_rx_inst|Equal2~2_combout ; +wire \uart_rx_inst|work_en~q ; +wire \uart_rx_inst|Equal1~1_combout ; +wire \uart_rx_inst|Equal1~2_combout ; +wire \uart_rx_inst|Equal1~3_combout ; +wire \uart_rx_inst|always5~0_combout ; +wire \uart_rx_inst|start_nedge~q ; +wire \uart_rx_inst|work_en~0_combout ; +wire \uart_rx_inst|always3~0_combout ; +wire \tx~output_o ; +wire \sys_clk~input_o ; +wire \sys_clk~inputclkctrl_outclk ; +wire \uart_rx_inst|Add1~0_combout ; +wire \uart_rx_inst|bit_cnt~1_combout ; +wire \sys_rst_n~input_o ; +wire \uart_rx_inst|Add1~1 ; +wire \uart_rx_inst|Add1~2_combout ; +wire \uart_rx_inst|Add1~3 ; +wire \uart_rx_inst|Add1~4_combout ; +wire \uart_rx_inst|always4~0_combout ; +wire \uart_rx_inst|Add1~5 ; +wire \uart_rx_inst|Add1~6_combout ; +wire \uart_rx_inst|bit_cnt~0_combout ; +wire \uart_rx_inst|always4~1_combout ; +wire \uart_rx_inst|rx_flag~feeder_combout ; +wire \uart_rx_inst|rx_flag~q ; +wire \uart_rx_inst|po_flag~feeder_combout ; +wire \uart_rx_inst|po_flag~q ; +wire \uart_tx_inst|work_en~0_combout ; +wire \uart_tx_inst|work_en~q ; +wire \uart_tx_inst|baud_cnt[0]~13_combout ; +wire \uart_tx_inst|baud_cnt[10]~34 ; +wire \uart_tx_inst|baud_cnt[11]~35_combout ; +wire \uart_tx_inst|Equal1~0_combout ; +wire \uart_tx_inst|Equal1~1_combout ; +wire \uart_tx_inst|baud_cnt[11]~36 ; +wire \uart_tx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal1~3_combout ; +wire \uart_tx_inst|baud_cnt[2]~17_combout ; +wire \uart_tx_inst|baud_cnt[4]~21_combout ; +wire \uart_tx_inst|Equal1~2_combout ; +wire \uart_tx_inst|always1~0_combout ; +wire \uart_tx_inst|baud_cnt[0]~14 ; +wire \uart_tx_inst|baud_cnt[1]~15_combout ; +wire \uart_tx_inst|baud_cnt[1]~16 ; +wire \uart_tx_inst|baud_cnt[2]~18 ; +wire \uart_tx_inst|baud_cnt[3]~19_combout ; +wire \uart_tx_inst|baud_cnt[3]~20 ; +wire \uart_tx_inst|baud_cnt[4]~22 ; +wire \uart_tx_inst|baud_cnt[5]~24 ; +wire \uart_tx_inst|baud_cnt[6]~25_combout ; +wire \uart_tx_inst|baud_cnt[6]~26 ; +wire \uart_tx_inst|baud_cnt[7]~27_combout ; +wire \uart_tx_inst|baud_cnt[7]~28 ; +wire \uart_tx_inst|baud_cnt[8]~29_combout ; +wire \uart_tx_inst|baud_cnt[8]~30 ; +wire \uart_tx_inst|baud_cnt[9]~31_combout ; +wire \uart_tx_inst|baud_cnt[9]~32 ; +wire \uart_tx_inst|baud_cnt[10]~33_combout ; +wire \uart_tx_inst|Equal2~1_combout ; +wire \uart_tx_inst|bit_flag~q ; +wire \uart_tx_inst|always3~0_combout ; +wire \uart_tx_inst|bit_cnt[2]~2_combout ; +wire \uart_tx_inst|bit_cnt[3]~4_combout ; +wire \uart_tx_inst|always0~0_combout ; +wire \uart_tx_inst|always0~1_combout ; +wire \uart_tx_inst|bit_cnt[0]~5_combout ; +wire \rx~input_o ; +wire \uart_rx_inst|rx_reg1~0_combout ; +wire \uart_rx_inst|rx_reg1~q ; +wire \uart_rx_inst|rx_reg2~feeder_combout ; +wire \uart_rx_inst|rx_reg2~q ; +wire \uart_rx_inst|rx_reg3~feeder_combout ; +wire \uart_rx_inst|rx_reg3~q ; +wire \uart_rx_inst|rx_data[7]~0_combout ; +wire \uart_rx_inst|always8~0_combout ; +wire \uart_tx_inst|bit_cnt[1]~3_combout ; +wire \uart_tx_inst|tx~2_combout ; +wire \uart_tx_inst|tx~5_combout ; +wire \uart_rx_inst|rx_data[6]~feeder_combout ; +wire \uart_rx_inst|po_data[5]~feeder_combout ; +wire \uart_rx_inst|po_data[4]~feeder_combout ; +wire \uart_tx_inst|Mux0~0_combout ; +wire \uart_tx_inst|Mux0~1_combout ; +wire \uart_rx_inst|rx_data[2]~feeder_combout ; +wire \uart_rx_inst|rx_data[1]~feeder_combout ; +wire \uart_rx_inst|rx_data[0]~feeder_combout ; +wire \uart_tx_inst|tx~3_combout ; +wire \uart_tx_inst|tx~4_combout ; +wire \uart_tx_inst|tx~6_combout ; +wire \uart_tx_inst|tx~7_combout ; +wire \uart_tx_inst|tx~q ; +wire [7:0] \uart_rx_inst|rx_data ; +wire [7:0] \uart_rx_inst|po_data ; +wire [3:0] \uart_rx_inst|bit_cnt ; +wire [12:0] \uart_rx_inst|baud_cnt ; +wire [3:0] \uart_tx_inst|bit_cnt ; +wire [12:0] \uart_tx_inst|baud_cnt ; + + +// Location: FF_X6_Y9_N13 +dffeas \uart_tx_inst|baud_cnt[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N12 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[4]~22 ), + .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_tx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y9_N5 +dffeas \uart_rx_inst|baud_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N7 +dffeas \uart_rx_inst|baud_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N19 +dffeas \uart_rx_inst|baud_cnt[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N21 +dffeas \uart_rx_inst|baud_cnt[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N11 +dffeas \uart_rx_inst|baud_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N15 +dffeas \uart_rx_inst|baud_cnt[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N9 +dffeas \uart_rx_inst|baud_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N13 +dffeas \uart_rx_inst|baud_cnt[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N23 +dffeas \uart_rx_inst|baud_cnt[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N27 +dffeas \uart_rx_inst|baud_cnt[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N17 +dffeas \uart_rx_inst|baud_cnt[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N25 +dffeas \uart_rx_inst|baud_cnt[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N29 +dffeas \uart_rx_inst|baud_cnt[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N4 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) +// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_rx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N6 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) + + .dataa(\uart_rx_inst|baud_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[0]~14 ), + .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_rx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N8 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) +// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[1]~16 ), + .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_rx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N10 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) + + .dataa(\uart_rx_inst|baud_cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[2]~18 ), + .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_rx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N12 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) +// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[3]~20 ), + .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_rx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N14 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[4]~22 ), + .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_rx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N16 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) +// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[5]~24 ), + .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_rx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N18 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[6]~26 ), + .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_rx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N20 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) +// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[7]~28 ), + .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_rx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N22 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[8]~30 ), + .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_rx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N24 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) +// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[9]~32 ), + .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_rx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N26 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) + + .dataa(\uart_rx_inst|baud_cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[10]~34 ), + .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_rx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N28 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt[11]~36 $ (!\uart_rx_inst|baud_cnt [12]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|baud_cnt [12]), + .cin(\uart_rx_inst|baud_cnt[11]~36 ), + .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; +defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X4_Y9_N23 +dffeas \uart_rx_inst|po_data[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [2]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( +// Equation(s): +// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [6]))) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(\uart_tx_inst|baud_cnt [2]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [6]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N22 +cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( +// Equation(s): +// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(gnd), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h66AA; +defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N22 +cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( +// Equation(s): +// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [0] & (\uart_tx_inst|bit_cnt [1] & \uart_tx_inst|bit_cnt [2])))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h7F80; +defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N11 +dffeas \uart_rx_inst|bit_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|Equal2~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( +// Equation(s): +// \uart_rx_inst|Equal1~0_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [0] & !\uart_rx_inst|baud_cnt [8]))) + + .dataa(\uart_rx_inst|baud_cnt [1]), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(\uart_rx_inst|baud_cnt [0]), + .datad(\uart_rx_inst|baud_cnt [8]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N4 +cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( +// Equation(s): +// \uart_rx_inst|Equal2~0_combout = (\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [4]))) + + .dataa(\uart_rx_inst|baud_cnt [5]), + .datab(\uart_rx_inst|baud_cnt [3]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0008; +defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N6 +cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( +// Equation(s): +// \uart_rx_inst|Equal2~1_combout = (\uart_rx_inst|baud_cnt [9] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [10]))) + + .dataa(\uart_rx_inst|baud_cnt [9]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [6]), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0008; +defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N10 +cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( +// Equation(s): +// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal2~1_combout & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal2~0_combout ))) + + .dataa(\uart_rx_inst|Equal2~1_combout ), + .datab(\uart_rx_inst|baud_cnt [12]), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000; +defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X9_Y9_N17 +dffeas \uart_rx_inst|work_en ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_rx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N30 +cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( +// Equation(s): +// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N2 +cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( +// Equation(s): +// \uart_rx_inst|Equal1~2_combout = (!\uart_rx_inst|baud_cnt [11] & \uart_rx_inst|baud_cnt [10]) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|baud_cnt [11]), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0F00; +defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N8 +cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( +// Equation(s): +// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt [9] & \uart_rx_inst|Equal1~2_combout ))) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(\uart_rx_inst|baud_cnt [9]), + .datad(\uart_rx_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h0800; +defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N2 +cycloneive_lcell_comb \uart_rx_inst|always5~0 ( +// Equation(s): +// \uart_rx_inst|always5~0_combout = ((\uart_rx_inst|Equal1~0_combout & (\uart_rx_inst|Equal1~1_combout & \uart_rx_inst|Equal1~3_combout ))) # (!\uart_rx_inst|work_en~q ) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|Equal1~0_combout ), + .datac(\uart_rx_inst|Equal1~1_combout ), + .datad(\uart_rx_inst|Equal1~3_combout ), + .cin(gnd), + .combout(\uart_rx_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always5~0 .lut_mask = 16'hD555; +defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N13 +dffeas \uart_rx_inst|start_nedge ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|always3~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|start_nedge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; +defparam \uart_rx_inst|start_nedge .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N16 +cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( +// Equation(s): +// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) + + .dataa(gnd), + .datab(\uart_rx_inst|start_nedge~q ), + .datac(\uart_rx_inst|work_en~q ), + .datad(\uart_rx_inst|always4~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hCCFC; +defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N12 +cycloneive_lcell_comb \uart_rx_inst|always3~0 ( +// Equation(s): +// \uart_rx_inst|always3~0_combout = (\uart_rx_inst|rx_reg2~q & !\uart_rx_inst|rx_reg3~q ) + + .dataa(gnd), + .datab(\uart_rx_inst|rx_reg2~q ), + .datac(\uart_rx_inst|rx_reg3~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always3~0 .lut_mask = 16'h0C0C; +defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y9_N16 +cycloneive_io_obuf \tx~output ( + .i(!\uart_tx_inst|tx~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tx~output_o ), + .obar()); +// synopsys translate_off +defparam \tx~output .bus_hold = "false"; +defparam \tx~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \sys_clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sys_clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sys_clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \sys_clk~inputclkctrl .clock_type = "global clock"; +defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N16 +cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( +// Equation(s): +// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] & VCC)) +// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [0])) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|Add1~0_combout ), + .cout(\uart_rx_inst|Add1~1 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; +defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N4 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~1_combout = \uart_rx_inst|Add1~0_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(\uart_rx_inst|Add1~0_combout ), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h78F0; +defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X8_Y9_N5 +dffeas \uart_rx_inst|bit_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N18 +cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( +// Equation(s): +// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) +// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~1 ), + .combout(\uart_rx_inst|Add1~2_combout ), + .cout(\uart_rx_inst|Add1~3 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X8_Y9_N19 +dffeas \uart_rx_inst|bit_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|Add1~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N20 +cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( +// Equation(s): +// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) +// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~3 ), + .combout(\uart_rx_inst|Add1~4_combout ), + .cout(\uart_rx_inst|Add1~5 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X8_Y9_N21 +dffeas \uart_rx_inst|bit_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|Add1~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N24 +cycloneive_lcell_comb \uart_rx_inst|always4~0 ( +// Equation(s): +// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [2])) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [1]), + .datac(\uart_rx_inst|bit_cnt [0]), + .datad(\uart_rx_inst|bit_cnt [2]), + .cin(gnd), + .combout(\uart_rx_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0003; +defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N22 +cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( +// Equation(s): +// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|Add1~5 $ (\uart_rx_inst|bit_cnt [3]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(\uart_rx_inst|Add1~5 ), + .combout(\uart_rx_inst|Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h0FF0; +defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~0_combout = \uart_rx_inst|Add1~6_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout & \uart_rx_inst|bit_cnt [3])))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(\uart_rx_inst|Add1~6_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h7F80; +defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N1 +dffeas \uart_rx_inst|bit_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N30 +cycloneive_lcell_comb \uart_rx_inst|always4~1 ( +// Equation(s): +// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(gnd), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~1 .lut_mask = 16'h8800; +defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N14 +cycloneive_lcell_comb \uart_rx_inst|rx_flag~feeder ( +// Equation(s): +// \uart_rx_inst|rx_flag~feeder_combout = \uart_rx_inst|always4~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|always4~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag~feeder .lut_mask = 16'hF0F0; +defparam \uart_rx_inst|rx_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N15 +dffeas \uart_rx_inst|rx_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_flag~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N30 +cycloneive_lcell_comb \uart_rx_inst|po_flag~feeder ( +// Equation(s): +// \uart_rx_inst|po_flag~feeder_combout = \uart_rx_inst|rx_flag~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_flag~q ), + .cin(gnd), + .combout(\uart_rx_inst|po_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_flag~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N31 +dffeas \uart_rx_inst|po_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|po_flag~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N14 +cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( +// Equation(s): +// \uart_tx_inst|work_en~0_combout = (\uart_rx_inst|po_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) + + .dataa(gnd), + .datab(\uart_rx_inst|po_flag~q ), + .datac(\uart_tx_inst|work_en~q ), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hCCFC; +defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N15 +dffeas \uart_tx_inst|work_en ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_tx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N2 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) +// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_tx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N22 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) +// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[9]~32 ), + .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_tx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N24 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[10]~34 ), + .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_tx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N25 +dffeas \uart_tx_inst|baud_cnt[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N28 +cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( +// Equation(s): +// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [5] & (\uart_tx_inst|baud_cnt [0] & (!\uart_tx_inst|baud_cnt [3] & !\uart_tx_inst|baud_cnt [7]))) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(\uart_tx_inst|baud_cnt [3]), + .datad(\uart_tx_inst|baud_cnt [7]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0004; +defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N0 +cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( +// Equation(s): +// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt [11] & \uart_tx_inst|Equal1~0_combout ))) + + .dataa(\uart_tx_inst|baud_cnt [9]), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(\uart_tx_inst|baud_cnt [11]), + .datad(\uart_tx_inst|Equal1~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0100; +defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N26 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_tx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_tx_inst|baud_cnt[11]~36 ), + .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N27 +dffeas \uart_tx_inst|baud_cnt[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N16 +cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( +// Equation(s): +// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [12] & \uart_tx_inst|baud_cnt [10]) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(gnd), + .datad(\uart_tx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hCC00; +defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N6 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) +// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[1]~16 ), + .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_tx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N7 +dffeas \uart_tx_inst|baud_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N10 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) +// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[3]~20 ), + .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_tx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N11 +dffeas \uart_tx_inst|baud_cnt[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y9_N6 +cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( +// Equation(s): +// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4]))) + + .dataa(\uart_tx_inst|baud_cnt [6]), + .datab(\uart_tx_inst|baud_cnt [2]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; +defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N30 +cycloneive_lcell_comb \uart_tx_inst|always1~0 ( +// Equation(s): +// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~1_combout & (\uart_tx_inst|Equal1~3_combout & \uart_tx_inst|Equal1~2_combout ))) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|Equal1~1_combout ), + .datac(\uart_tx_inst|Equal1~3_combout ), + .datad(\uart_tx_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555; +defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X6_Y9_N3 +dffeas \uart_tx_inst|baud_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[0]~14 ), + .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_tx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N5 +dffeas \uart_tx_inst|baud_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N8 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[2]~18 ), + .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_tx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N9 +dffeas \uart_tx_inst|baud_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N14 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) +// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[5]~24 ), + .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_tx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N15 +dffeas \uart_tx_inst|baud_cnt[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N16 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[6]~26 ), + .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_tx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N17 +dffeas \uart_tx_inst|baud_cnt[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N18 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) +// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[7]~28 ), + .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_tx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N19 +dffeas \uart_tx_inst|baud_cnt[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N20 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[8]~30 ), + .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_tx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N21 +dffeas \uart_tx_inst|baud_cnt[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X6_Y9_N23 +dffeas \uart_tx_inst|baud_cnt[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N20 +cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( +// Equation(s): +// \uart_tx_inst|Equal2~1_combout = (\uart_tx_inst|Equal2~0_combout & (!\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|Equal1~1_combout & !\uart_tx_inst|baud_cnt [12]))) + + .dataa(\uart_tx_inst|Equal2~0_combout ), + .datab(\uart_tx_inst|baud_cnt [10]), + .datac(\uart_tx_inst|Equal1~1_combout ), + .datad(\uart_tx_inst|baud_cnt [12]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h0020; +defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N21 +dffeas \uart_tx_inst|bit_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|Equal2~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N24 +cycloneive_lcell_comb \uart_tx_inst|always3~0 ( +// Equation(s): +// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_tx_inst|work_en~q ), + .datad(\uart_tx_inst|bit_flag~q ), + .cin(gnd), + .combout(\uart_tx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always3~0 .lut_mask = 16'h0FFF; +defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N26 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~2 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[2]~2_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~0_combout )))) + + .dataa(\uart_tx_inst|Add1~0_combout ), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always3~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2]~2 .lut_mask = 16'h3022; +defparam \uart_tx_inst|bit_cnt[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N27 +dffeas \uart_tx_inst|bit_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[2]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N2 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~4 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[3]~4_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [3]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) + + .dataa(\uart_tx_inst|Add1~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3]~4 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N3 +dffeas \uart_tx_inst|bit_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[3]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|always0~0 ( +// Equation(s): +// \uart_tx_inst|always0~0_combout = (\uart_tx_inst|bit_cnt [3] & \uart_tx_inst|bit_flag~q ) + + .dataa(gnd), + .datab(\uart_tx_inst|bit_cnt [3]), + .datac(gnd), + .datad(\uart_tx_inst|bit_flag~q ), + .cin(gnd), + .combout(\uart_tx_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~0 .lut_mask = 16'hCC00; +defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N8 +cycloneive_lcell_comb \uart_tx_inst|always0~1 ( +// Equation(s): +// \uart_tx_inst|always0~1_combout = (!\uart_tx_inst|bit_cnt [1] & (\uart_tx_inst|bit_cnt [0] & (!\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|always0~0_combout ))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~1 .lut_mask = 16'h0400; +defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N2 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|bit_flag~q & \uart_tx_inst|work_en~q ))))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h1230; +defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N3 +dffeas \uart_tx_inst|bit_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[0]~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \rx~input ( + .i(rx), + .ibar(gnd), + .o(\rx~input_o )); +// synopsys translate_off +defparam \rx~input .bus_hold = "false"; +defparam \rx~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N18 +cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( +// Equation(s): +// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rx~input_o ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N19 +dffeas \uart_rx_inst|rx_reg1 ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_reg1~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg1~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N1 +dffeas \uart_rx_inst|rx_reg2 ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_reg2~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N26 +cycloneive_lcell_comb \uart_rx_inst|rx_reg3~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg3~feeder_combout = \uart_rx_inst|rx_reg2~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg2~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N27 +dffeas \uart_rx_inst|rx_reg3 ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_reg3~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N28 +cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( +// Equation(s): +// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg3~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N6 +cycloneive_lcell_comb \uart_rx_inst|always8~0 ( +// Equation(s): +// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|always8~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8822; +defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N29 +dffeas \uart_rx_inst|rx_data[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[7]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N5 +dffeas \uart_rx_inst|po_data[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [7]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N6 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~3 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[1]~3_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [1]), + .datad(\uart_tx_inst|always3~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1]~3 .lut_mask = 16'h3012; +defparam \uart_tx_inst|bit_cnt[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N7 +dffeas \uart_tx_inst|bit_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[1]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|tx~2 ( +// Equation(s): +// \uart_tx_inst|tx~2_combout = (\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|bit_cnt [0]) # ((\uart_rx_inst|po_data [7]) # (\uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_rx_inst|po_data [7]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~2 .lut_mask = 16'hFFFE; +defparam \uart_tx_inst|tx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N16 +cycloneive_lcell_comb \uart_tx_inst|tx~5 ( +// Equation(s): +// \uart_tx_inst|tx~5_combout = (\uart_tx_inst|bit_flag~q & (((\uart_tx_inst|tx~2_combout & \uart_tx_inst|bit_cnt [3])))) # (!\uart_tx_inst|bit_flag~q & (!\uart_tx_inst|tx~q )) + + .dataa(\uart_tx_inst|tx~q ), + .datab(\uart_tx_inst|tx~2_combout ), + .datac(\uart_tx_inst|bit_flag~q ), + .datad(\uart_tx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_tx_inst|tx~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~5 .lut_mask = 16'hC505; +defparam \uart_tx_inst|tx~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[6]~feeder_combout = \uart_rx_inst|rx_data [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [7]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N3 +dffeas \uart_rx_inst|rx_data[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X8_Y9_N7 +dffeas \uart_rx_inst|rx_data[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [6]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N20 +cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N21 +dffeas \uart_rx_inst|po_data[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|po_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N15 +dffeas \uart_rx_inst|po_data[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [6]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X8_Y9_N31 +dffeas \uart_rx_inst|rx_data[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [5]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|po_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[4]~feeder_combout = \uart_rx_inst|rx_data [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [4]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N1 +dffeas \uart_rx_inst|po_data[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|po_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X8_Y9_N23 +dffeas \uart_rx_inst|rx_data[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [4]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N25 +dffeas \uart_rx_inst|po_data[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [3]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N24 +cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( +// Equation(s): +// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & (\uart_rx_inst|po_data [4])) # (!\uart_tx_inst|bit_cnt [0] & ((\uart_rx_inst|po_data [3]))))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_rx_inst|po_data [4]), + .datac(\uart_rx_inst|po_data [3]), + .datad(\uart_tx_inst|bit_cnt [0]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hEE50; +defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N14 +cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( +// Equation(s): +// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|Mux0~0_combout & ((\uart_rx_inst|po_data [6]))) # (!\uart_tx_inst|Mux0~0_combout & (\uart_rx_inst|po_data [5])))) # (!\uart_tx_inst|bit_cnt [1] & +// (((\uart_tx_inst|Mux0~0_combout )))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_rx_inst|po_data [5]), + .datac(\uart_rx_inst|po_data [6]), + .datad(\uart_tx_inst|Mux0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF588; +defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N8 +cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|rx_data [3]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hF0F0; +defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N9 +dffeas \uart_rx_inst|rx_data[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N26 +cycloneive_lcell_comb \uart_rx_inst|rx_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[1]~feeder_combout = \uart_rx_inst|rx_data [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [2]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N27 +dffeas \uart_rx_inst|rx_data[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N19 +dffeas \uart_rx_inst|po_data[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [1]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N12 +cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|rx_data [1]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hF0F0; +defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N13 +dffeas \uart_rx_inst|rx_data[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N29 +dffeas \uart_rx_inst|po_data[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [0]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N28 +cycloneive_lcell_comb \uart_tx_inst|tx~3 ( +// Equation(s): +// \uart_tx_inst|tx~3_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\uart_rx_inst|po_data [2])) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_rx_inst|po_data [0]))))) + + .dataa(\uart_rx_inst|po_data [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_rx_inst|po_data [0]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~3 .lut_mask = 16'h88C0; +defparam \uart_tx_inst|tx~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N18 +cycloneive_lcell_comb \uart_tx_inst|tx~4 ( +// Equation(s): +// \uart_tx_inst|tx~4_combout = (\uart_tx_inst|tx~3_combout ) # ((\uart_tx_inst|bit_cnt [1] & (!\uart_tx_inst|bit_cnt [0] & \uart_rx_inst|po_data [1]))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_rx_inst|po_data [1]), + .datad(\uart_tx_inst|tx~3_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~4 .lut_mask = 16'hFF20; +defparam \uart_tx_inst|tx~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N10 +cycloneive_lcell_comb \uart_tx_inst|tx~6 ( +// Equation(s): +// \uart_tx_inst|tx~6_combout = (\uart_tx_inst|bit_flag~q & ((\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|tx~4_combout )))) # (!\uart_tx_inst|bit_flag~q & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout ))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\uart_tx_inst|Mux0~1_combout ), + .datad(\uart_tx_inst|tx~4_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~6 .lut_mask = 16'hAE8C; +defparam \uart_tx_inst|tx~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N12 +cycloneive_lcell_comb \uart_tx_inst|tx~7 ( +// Equation(s): +// \uart_tx_inst|tx~7_combout = (\uart_tx_inst|tx~5_combout & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout & !\uart_tx_inst|tx~6_combout ))) # (!\uart_tx_inst|tx~5_combout & (((\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|Mux0~1_combout )) # +// (!\uart_tx_inst|tx~6_combout ))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|tx~5_combout ), + .datac(\uart_tx_inst|Mux0~1_combout ), + .datad(\uart_tx_inst|tx~6_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~7_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~7 .lut_mask = 16'h023B; +defparam \uart_tx_inst|tx~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N13 +dffeas \uart_tx_inst|tx ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|tx~7_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|tx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|tx .is_wysiwyg = "true"; +defparam \uart_tx_inst|tx .power_up = "low"; +// synopsys translate_on + +assign tx = \tx~output_o ; + +endmodule diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_0c_slow.vo b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_0c_slow.vo new file mode 100644 index 0000000..bba2871 --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_0c_slow.vo @@ -0,0 +1,2836 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 03:03:50" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module rs232 ( + sys_clk, + sys_rst_n, + rx, + tx); +input sys_clk; +input sys_rst_n; +input rx; +output tx; + +// Design Ports Information +// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("rs232_8_1200mv_0c_v_slow.sdo"); +// synopsys translate_on + +wire \uart_tx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|baud_cnt[0]~13_combout ; +wire \uart_rx_inst|baud_cnt[0]~14 ; +wire \uart_rx_inst|baud_cnt[1]~15_combout ; +wire \uart_rx_inst|baud_cnt[1]~16 ; +wire \uart_rx_inst|baud_cnt[2]~17_combout ; +wire \uart_rx_inst|baud_cnt[2]~18 ; +wire \uart_rx_inst|baud_cnt[3]~19_combout ; +wire \uart_rx_inst|baud_cnt[3]~20 ; +wire \uart_rx_inst|baud_cnt[4]~21_combout ; +wire \uart_rx_inst|baud_cnt[4]~22 ; +wire \uart_rx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|baud_cnt[5]~24 ; +wire \uart_rx_inst|baud_cnt[6]~25_combout ; +wire \uart_rx_inst|baud_cnt[6]~26 ; +wire \uart_rx_inst|baud_cnt[7]~27_combout ; +wire \uart_rx_inst|baud_cnt[7]~28 ; +wire \uart_rx_inst|baud_cnt[8]~29_combout ; +wire \uart_rx_inst|baud_cnt[8]~30 ; +wire \uart_rx_inst|baud_cnt[9]~31_combout ; +wire \uart_rx_inst|baud_cnt[9]~32 ; +wire \uart_rx_inst|baud_cnt[10]~33_combout ; +wire \uart_rx_inst|baud_cnt[10]~34 ; +wire \uart_rx_inst|baud_cnt[11]~35_combout ; +wire \uart_rx_inst|baud_cnt[11]~36 ; +wire \uart_rx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal2~0_combout ; +wire \uart_tx_inst|Add1~0_combout ; +wire \uart_tx_inst|Add1~1_combout ; +wire \uart_rx_inst|bit_flag~q ; +wire \uart_rx_inst|Equal1~0_combout ; +wire \uart_rx_inst|Equal2~0_combout ; +wire \uart_rx_inst|Equal2~1_combout ; +wire \uart_rx_inst|Equal2~2_combout ; +wire \uart_rx_inst|work_en~q ; +wire \uart_rx_inst|Equal1~1_combout ; +wire \uart_rx_inst|Equal1~2_combout ; +wire \uart_rx_inst|Equal1~3_combout ; +wire \uart_rx_inst|always5~0_combout ; +wire \uart_rx_inst|start_nedge~q ; +wire \uart_rx_inst|work_en~0_combout ; +wire \uart_rx_inst|always3~0_combout ; +wire \tx~output_o ; +wire \sys_clk~input_o ; +wire \sys_clk~inputclkctrl_outclk ; +wire \uart_rx_inst|Add1~0_combout ; +wire \uart_rx_inst|bit_cnt~1_combout ; +wire \sys_rst_n~input_o ; +wire \uart_rx_inst|Add1~1 ; +wire \uart_rx_inst|Add1~2_combout ; +wire \uart_rx_inst|Add1~3 ; +wire \uart_rx_inst|Add1~4_combout ; +wire \uart_rx_inst|always4~0_combout ; +wire \uart_rx_inst|Add1~5 ; +wire \uart_rx_inst|Add1~6_combout ; +wire \uart_rx_inst|bit_cnt~0_combout ; +wire \uart_rx_inst|always4~1_combout ; +wire \uart_rx_inst|rx_flag~feeder_combout ; +wire \uart_rx_inst|rx_flag~q ; +wire \uart_rx_inst|po_flag~feeder_combout ; +wire \uart_rx_inst|po_flag~q ; +wire \uart_tx_inst|work_en~0_combout ; +wire \uart_tx_inst|work_en~q ; +wire \uart_tx_inst|baud_cnt[0]~13_combout ; +wire \uart_tx_inst|baud_cnt[10]~34 ; +wire \uart_tx_inst|baud_cnt[11]~35_combout ; +wire \uart_tx_inst|Equal1~0_combout ; +wire \uart_tx_inst|Equal1~1_combout ; +wire \uart_tx_inst|baud_cnt[11]~36 ; +wire \uart_tx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal1~3_combout ; +wire \uart_tx_inst|baud_cnt[2]~17_combout ; +wire \uart_tx_inst|baud_cnt[4]~21_combout ; +wire \uart_tx_inst|Equal1~2_combout ; +wire \uart_tx_inst|always1~0_combout ; +wire \uart_tx_inst|baud_cnt[0]~14 ; +wire \uart_tx_inst|baud_cnt[1]~15_combout ; +wire \uart_tx_inst|baud_cnt[1]~16 ; +wire \uart_tx_inst|baud_cnt[2]~18 ; +wire \uart_tx_inst|baud_cnt[3]~19_combout ; +wire \uart_tx_inst|baud_cnt[3]~20 ; +wire \uart_tx_inst|baud_cnt[4]~22 ; +wire \uart_tx_inst|baud_cnt[5]~24 ; +wire \uart_tx_inst|baud_cnt[6]~25_combout ; +wire \uart_tx_inst|baud_cnt[6]~26 ; +wire \uart_tx_inst|baud_cnt[7]~27_combout ; +wire \uart_tx_inst|baud_cnt[7]~28 ; +wire \uart_tx_inst|baud_cnt[8]~29_combout ; +wire \uart_tx_inst|baud_cnt[8]~30 ; +wire \uart_tx_inst|baud_cnt[9]~31_combout ; +wire \uart_tx_inst|baud_cnt[9]~32 ; +wire \uart_tx_inst|baud_cnt[10]~33_combout ; +wire \uart_tx_inst|Equal2~1_combout ; +wire \uart_tx_inst|bit_flag~q ; +wire \uart_tx_inst|always3~0_combout ; +wire \uart_tx_inst|bit_cnt[2]~2_combout ; +wire \uart_tx_inst|bit_cnt[3]~4_combout ; +wire \uart_tx_inst|always0~0_combout ; +wire \uart_tx_inst|always0~1_combout ; +wire \uart_tx_inst|bit_cnt[0]~5_combout ; +wire \rx~input_o ; +wire \uart_rx_inst|rx_reg1~0_combout ; +wire \uart_rx_inst|rx_reg1~q ; +wire \uart_rx_inst|rx_reg2~feeder_combout ; +wire \uart_rx_inst|rx_reg2~q ; +wire \uart_rx_inst|rx_reg3~feeder_combout ; +wire \uart_rx_inst|rx_reg3~q ; +wire \uart_rx_inst|rx_data[7]~0_combout ; +wire \uart_rx_inst|always8~0_combout ; +wire \uart_tx_inst|bit_cnt[1]~3_combout ; +wire \uart_tx_inst|tx~2_combout ; +wire \uart_tx_inst|tx~5_combout ; +wire \uart_rx_inst|rx_data[6]~feeder_combout ; +wire \uart_rx_inst|po_data[5]~feeder_combout ; +wire \uart_rx_inst|po_data[4]~feeder_combout ; +wire \uart_tx_inst|Mux0~0_combout ; +wire \uart_tx_inst|Mux0~1_combout ; +wire \uart_rx_inst|rx_data[2]~feeder_combout ; +wire \uart_rx_inst|rx_data[1]~feeder_combout ; +wire \uart_rx_inst|rx_data[0]~feeder_combout ; +wire \uart_tx_inst|tx~3_combout ; +wire \uart_tx_inst|tx~4_combout ; +wire \uart_tx_inst|tx~6_combout ; +wire \uart_tx_inst|tx~7_combout ; +wire \uart_tx_inst|tx~q ; +wire [7:0] \uart_rx_inst|rx_data ; +wire [7:0] \uart_rx_inst|po_data ; +wire [3:0] \uart_rx_inst|bit_cnt ; +wire [12:0] \uart_rx_inst|baud_cnt ; +wire [3:0] \uart_tx_inst|bit_cnt ; +wire [12:0] \uart_tx_inst|baud_cnt ; + + +// Location: FF_X6_Y9_N13 +dffeas \uart_tx_inst|baud_cnt[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N12 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[4]~22 ), + .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_tx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y9_N5 +dffeas \uart_rx_inst|baud_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N7 +dffeas \uart_rx_inst|baud_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N19 +dffeas \uart_rx_inst|baud_cnt[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N21 +dffeas \uart_rx_inst|baud_cnt[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N11 +dffeas \uart_rx_inst|baud_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N15 +dffeas \uart_rx_inst|baud_cnt[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N9 +dffeas \uart_rx_inst|baud_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N13 +dffeas \uart_rx_inst|baud_cnt[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N23 +dffeas \uart_rx_inst|baud_cnt[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N27 +dffeas \uart_rx_inst|baud_cnt[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N17 +dffeas \uart_rx_inst|baud_cnt[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N25 +dffeas \uart_rx_inst|baud_cnt[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N29 +dffeas \uart_rx_inst|baud_cnt[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N4 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) +// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_rx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N6 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) + + .dataa(\uart_rx_inst|baud_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[0]~14 ), + .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_rx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N8 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) +// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[1]~16 ), + .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_rx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N10 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) + + .dataa(\uart_rx_inst|baud_cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[2]~18 ), + .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_rx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N12 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) +// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[3]~20 ), + .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_rx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N14 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[4]~22 ), + .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_rx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N16 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) +// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[5]~24 ), + .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_rx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N18 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[6]~26 ), + .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_rx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N20 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) +// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[7]~28 ), + .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_rx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N22 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[8]~30 ), + .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_rx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N24 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) +// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[9]~32 ), + .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_rx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N26 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) + + .dataa(\uart_rx_inst|baud_cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[10]~34 ), + .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_rx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N28 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt[11]~36 $ (!\uart_rx_inst|baud_cnt [12]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|baud_cnt [12]), + .cin(\uart_rx_inst|baud_cnt[11]~36 ), + .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; +defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X4_Y9_N23 +dffeas \uart_rx_inst|po_data[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [2]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( +// Equation(s): +// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [6]))) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(\uart_tx_inst|baud_cnt [2]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [6]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N22 +cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( +// Equation(s): +// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(gnd), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h66AA; +defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N22 +cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( +// Equation(s): +// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [0] & (\uart_tx_inst|bit_cnt [1] & \uart_tx_inst|bit_cnt [2])))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h7F80; +defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N11 +dffeas \uart_rx_inst|bit_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|Equal2~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( +// Equation(s): +// \uart_rx_inst|Equal1~0_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [0] & !\uart_rx_inst|baud_cnt [8]))) + + .dataa(\uart_rx_inst|baud_cnt [1]), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(\uart_rx_inst|baud_cnt [0]), + .datad(\uart_rx_inst|baud_cnt [8]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N4 +cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( +// Equation(s): +// \uart_rx_inst|Equal2~0_combout = (\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [4]))) + + .dataa(\uart_rx_inst|baud_cnt [5]), + .datab(\uart_rx_inst|baud_cnt [3]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0008; +defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N6 +cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( +// Equation(s): +// \uart_rx_inst|Equal2~1_combout = (\uart_rx_inst|baud_cnt [9] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [10]))) + + .dataa(\uart_rx_inst|baud_cnt [9]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [6]), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0008; +defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N10 +cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( +// Equation(s): +// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal2~1_combout & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal2~0_combout ))) + + .dataa(\uart_rx_inst|Equal2~1_combout ), + .datab(\uart_rx_inst|baud_cnt [12]), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000; +defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X9_Y9_N17 +dffeas \uart_rx_inst|work_en ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_rx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N30 +cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( +// Equation(s): +// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N2 +cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( +// Equation(s): +// \uart_rx_inst|Equal1~2_combout = (!\uart_rx_inst|baud_cnt [11] & \uart_rx_inst|baud_cnt [10]) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|baud_cnt [11]), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0F00; +defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N8 +cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( +// Equation(s): +// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt [9] & \uart_rx_inst|Equal1~2_combout ))) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(\uart_rx_inst|baud_cnt [9]), + .datad(\uart_rx_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h0800; +defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N2 +cycloneive_lcell_comb \uart_rx_inst|always5~0 ( +// Equation(s): +// \uart_rx_inst|always5~0_combout = ((\uart_rx_inst|Equal1~0_combout & (\uart_rx_inst|Equal1~1_combout & \uart_rx_inst|Equal1~3_combout ))) # (!\uart_rx_inst|work_en~q ) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|Equal1~0_combout ), + .datac(\uart_rx_inst|Equal1~1_combout ), + .datad(\uart_rx_inst|Equal1~3_combout ), + .cin(gnd), + .combout(\uart_rx_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always5~0 .lut_mask = 16'hD555; +defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N13 +dffeas \uart_rx_inst|start_nedge ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|always3~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|start_nedge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; +defparam \uart_rx_inst|start_nedge .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N16 +cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( +// Equation(s): +// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) + + .dataa(gnd), + .datab(\uart_rx_inst|start_nedge~q ), + .datac(\uart_rx_inst|work_en~q ), + .datad(\uart_rx_inst|always4~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hCCFC; +defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N12 +cycloneive_lcell_comb \uart_rx_inst|always3~0 ( +// Equation(s): +// \uart_rx_inst|always3~0_combout = (\uart_rx_inst|rx_reg2~q & !\uart_rx_inst|rx_reg3~q ) + + .dataa(gnd), + .datab(\uart_rx_inst|rx_reg2~q ), + .datac(\uart_rx_inst|rx_reg3~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always3~0 .lut_mask = 16'h0C0C; +defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y9_N16 +cycloneive_io_obuf \tx~output ( + .i(!\uart_tx_inst|tx~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tx~output_o ), + .obar()); +// synopsys translate_off +defparam \tx~output .bus_hold = "false"; +defparam \tx~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \sys_clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sys_clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sys_clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \sys_clk~inputclkctrl .clock_type = "global clock"; +defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N16 +cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( +// Equation(s): +// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] & VCC)) +// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [0])) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|Add1~0_combout ), + .cout(\uart_rx_inst|Add1~1 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; +defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N4 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~1_combout = \uart_rx_inst|Add1~0_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(\uart_rx_inst|Add1~0_combout ), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h78F0; +defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X8_Y9_N5 +dffeas \uart_rx_inst|bit_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N18 +cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( +// Equation(s): +// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) +// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~1 ), + .combout(\uart_rx_inst|Add1~2_combout ), + .cout(\uart_rx_inst|Add1~3 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X8_Y9_N19 +dffeas \uart_rx_inst|bit_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|Add1~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N20 +cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( +// Equation(s): +// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) +// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~3 ), + .combout(\uart_rx_inst|Add1~4_combout ), + .cout(\uart_rx_inst|Add1~5 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X8_Y9_N21 +dffeas \uart_rx_inst|bit_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|Add1~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N24 +cycloneive_lcell_comb \uart_rx_inst|always4~0 ( +// Equation(s): +// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [2])) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [1]), + .datac(\uart_rx_inst|bit_cnt [0]), + .datad(\uart_rx_inst|bit_cnt [2]), + .cin(gnd), + .combout(\uart_rx_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0003; +defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N22 +cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( +// Equation(s): +// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|Add1~5 $ (\uart_rx_inst|bit_cnt [3]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(\uart_rx_inst|Add1~5 ), + .combout(\uart_rx_inst|Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h0FF0; +defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~0_combout = \uart_rx_inst|Add1~6_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout & \uart_rx_inst|bit_cnt [3])))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(\uart_rx_inst|Add1~6_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h7F80; +defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N1 +dffeas \uart_rx_inst|bit_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N30 +cycloneive_lcell_comb \uart_rx_inst|always4~1 ( +// Equation(s): +// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(gnd), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~1 .lut_mask = 16'h8800; +defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N14 +cycloneive_lcell_comb \uart_rx_inst|rx_flag~feeder ( +// Equation(s): +// \uart_rx_inst|rx_flag~feeder_combout = \uart_rx_inst|always4~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|always4~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag~feeder .lut_mask = 16'hF0F0; +defparam \uart_rx_inst|rx_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N15 +dffeas \uart_rx_inst|rx_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_flag~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N30 +cycloneive_lcell_comb \uart_rx_inst|po_flag~feeder ( +// Equation(s): +// \uart_rx_inst|po_flag~feeder_combout = \uart_rx_inst|rx_flag~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_flag~q ), + .cin(gnd), + .combout(\uart_rx_inst|po_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_flag~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N31 +dffeas \uart_rx_inst|po_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|po_flag~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N14 +cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( +// Equation(s): +// \uart_tx_inst|work_en~0_combout = (\uart_rx_inst|po_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) + + .dataa(gnd), + .datab(\uart_rx_inst|po_flag~q ), + .datac(\uart_tx_inst|work_en~q ), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hCCFC; +defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N15 +dffeas \uart_tx_inst|work_en ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_tx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N2 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) +// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_tx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N22 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) +// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[9]~32 ), + .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_tx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N24 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[10]~34 ), + .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_tx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N25 +dffeas \uart_tx_inst|baud_cnt[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N28 +cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( +// Equation(s): +// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [5] & (\uart_tx_inst|baud_cnt [0] & (!\uart_tx_inst|baud_cnt [3] & !\uart_tx_inst|baud_cnt [7]))) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(\uart_tx_inst|baud_cnt [3]), + .datad(\uart_tx_inst|baud_cnt [7]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0004; +defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N0 +cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( +// Equation(s): +// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt [11] & \uart_tx_inst|Equal1~0_combout ))) + + .dataa(\uart_tx_inst|baud_cnt [9]), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(\uart_tx_inst|baud_cnt [11]), + .datad(\uart_tx_inst|Equal1~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0100; +defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N26 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_tx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_tx_inst|baud_cnt[11]~36 ), + .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N27 +dffeas \uart_tx_inst|baud_cnt[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N16 +cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( +// Equation(s): +// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [12] & \uart_tx_inst|baud_cnt [10]) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(gnd), + .datad(\uart_tx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hCC00; +defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N6 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) +// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[1]~16 ), + .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_tx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N7 +dffeas \uart_tx_inst|baud_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N10 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) +// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[3]~20 ), + .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_tx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N11 +dffeas \uart_tx_inst|baud_cnt[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y9_N6 +cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( +// Equation(s): +// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4]))) + + .dataa(\uart_tx_inst|baud_cnt [6]), + .datab(\uart_tx_inst|baud_cnt [2]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; +defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N30 +cycloneive_lcell_comb \uart_tx_inst|always1~0 ( +// Equation(s): +// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~1_combout & (\uart_tx_inst|Equal1~3_combout & \uart_tx_inst|Equal1~2_combout ))) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|Equal1~1_combout ), + .datac(\uart_tx_inst|Equal1~3_combout ), + .datad(\uart_tx_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555; +defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X6_Y9_N3 +dffeas \uart_tx_inst|baud_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[0]~14 ), + .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_tx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N5 +dffeas \uart_tx_inst|baud_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N8 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[2]~18 ), + .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_tx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N9 +dffeas \uart_tx_inst|baud_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N14 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) +// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[5]~24 ), + .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_tx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N15 +dffeas \uart_tx_inst|baud_cnt[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N16 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[6]~26 ), + .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_tx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N17 +dffeas \uart_tx_inst|baud_cnt[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N18 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) +// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[7]~28 ), + .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_tx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N19 +dffeas \uart_tx_inst|baud_cnt[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N20 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[8]~30 ), + .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_tx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N21 +dffeas \uart_tx_inst|baud_cnt[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X6_Y9_N23 +dffeas \uart_tx_inst|baud_cnt[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N20 +cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( +// Equation(s): +// \uart_tx_inst|Equal2~1_combout = (\uart_tx_inst|Equal2~0_combout & (!\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|Equal1~1_combout & !\uart_tx_inst|baud_cnt [12]))) + + .dataa(\uart_tx_inst|Equal2~0_combout ), + .datab(\uart_tx_inst|baud_cnt [10]), + .datac(\uart_tx_inst|Equal1~1_combout ), + .datad(\uart_tx_inst|baud_cnt [12]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h0020; +defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N21 +dffeas \uart_tx_inst|bit_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|Equal2~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N24 +cycloneive_lcell_comb \uart_tx_inst|always3~0 ( +// Equation(s): +// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_tx_inst|work_en~q ), + .datad(\uart_tx_inst|bit_flag~q ), + .cin(gnd), + .combout(\uart_tx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always3~0 .lut_mask = 16'h0FFF; +defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N26 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~2 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[2]~2_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~0_combout )))) + + .dataa(\uart_tx_inst|Add1~0_combout ), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always3~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2]~2 .lut_mask = 16'h3022; +defparam \uart_tx_inst|bit_cnt[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N27 +dffeas \uart_tx_inst|bit_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[2]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N2 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~4 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[3]~4_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [3]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) + + .dataa(\uart_tx_inst|Add1~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3]~4 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N3 +dffeas \uart_tx_inst|bit_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[3]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|always0~0 ( +// Equation(s): +// \uart_tx_inst|always0~0_combout = (\uart_tx_inst|bit_cnt [3] & \uart_tx_inst|bit_flag~q ) + + .dataa(gnd), + .datab(\uart_tx_inst|bit_cnt [3]), + .datac(gnd), + .datad(\uart_tx_inst|bit_flag~q ), + .cin(gnd), + .combout(\uart_tx_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~0 .lut_mask = 16'hCC00; +defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N8 +cycloneive_lcell_comb \uart_tx_inst|always0~1 ( +// Equation(s): +// \uart_tx_inst|always0~1_combout = (!\uart_tx_inst|bit_cnt [1] & (\uart_tx_inst|bit_cnt [0] & (!\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|always0~0_combout ))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~1 .lut_mask = 16'h0400; +defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N2 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|bit_flag~q & \uart_tx_inst|work_en~q ))))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h1230; +defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N3 +dffeas \uart_tx_inst|bit_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[0]~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \rx~input ( + .i(rx), + .ibar(gnd), + .o(\rx~input_o )); +// synopsys translate_off +defparam \rx~input .bus_hold = "false"; +defparam \rx~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N18 +cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( +// Equation(s): +// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rx~input_o ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N19 +dffeas \uart_rx_inst|rx_reg1 ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_reg1~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg1~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N1 +dffeas \uart_rx_inst|rx_reg2 ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_reg2~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N26 +cycloneive_lcell_comb \uart_rx_inst|rx_reg3~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg3~feeder_combout = \uart_rx_inst|rx_reg2~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg2~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N27 +dffeas \uart_rx_inst|rx_reg3 ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_reg3~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N28 +cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( +// Equation(s): +// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg3~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N6 +cycloneive_lcell_comb \uart_rx_inst|always8~0 ( +// Equation(s): +// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|always8~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8822; +defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N29 +dffeas \uart_rx_inst|rx_data[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[7]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N5 +dffeas \uart_rx_inst|po_data[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [7]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N6 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~3 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[1]~3_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [1]), + .datad(\uart_tx_inst|always3~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1]~3 .lut_mask = 16'h3012; +defparam \uart_tx_inst|bit_cnt[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N7 +dffeas \uart_tx_inst|bit_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[1]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|tx~2 ( +// Equation(s): +// \uart_tx_inst|tx~2_combout = (\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|bit_cnt [0]) # ((\uart_rx_inst|po_data [7]) # (\uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_rx_inst|po_data [7]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~2 .lut_mask = 16'hFFFE; +defparam \uart_tx_inst|tx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N16 +cycloneive_lcell_comb \uart_tx_inst|tx~5 ( +// Equation(s): +// \uart_tx_inst|tx~5_combout = (\uart_tx_inst|bit_flag~q & (((\uart_tx_inst|tx~2_combout & \uart_tx_inst|bit_cnt [3])))) # (!\uart_tx_inst|bit_flag~q & (!\uart_tx_inst|tx~q )) + + .dataa(\uart_tx_inst|tx~q ), + .datab(\uart_tx_inst|tx~2_combout ), + .datac(\uart_tx_inst|bit_flag~q ), + .datad(\uart_tx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_tx_inst|tx~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~5 .lut_mask = 16'hC505; +defparam \uart_tx_inst|tx~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[6]~feeder_combout = \uart_rx_inst|rx_data [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [7]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N3 +dffeas \uart_rx_inst|rx_data[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X8_Y9_N7 +dffeas \uart_rx_inst|rx_data[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [6]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N20 +cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N21 +dffeas \uart_rx_inst|po_data[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|po_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N15 +dffeas \uart_rx_inst|po_data[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [6]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X8_Y9_N31 +dffeas \uart_rx_inst|rx_data[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [5]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|po_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[4]~feeder_combout = \uart_rx_inst|rx_data [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [4]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N1 +dffeas \uart_rx_inst|po_data[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|po_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X8_Y9_N23 +dffeas \uart_rx_inst|rx_data[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [4]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N25 +dffeas \uart_rx_inst|po_data[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [3]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N24 +cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( +// Equation(s): +// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & (\uart_rx_inst|po_data [4])) # (!\uart_tx_inst|bit_cnt [0] & ((\uart_rx_inst|po_data [3]))))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_rx_inst|po_data [4]), + .datac(\uart_rx_inst|po_data [3]), + .datad(\uart_tx_inst|bit_cnt [0]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hEE50; +defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N14 +cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( +// Equation(s): +// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|Mux0~0_combout & ((\uart_rx_inst|po_data [6]))) # (!\uart_tx_inst|Mux0~0_combout & (\uart_rx_inst|po_data [5])))) # (!\uart_tx_inst|bit_cnt [1] & +// (((\uart_tx_inst|Mux0~0_combout )))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_rx_inst|po_data [5]), + .datac(\uart_rx_inst|po_data [6]), + .datad(\uart_tx_inst|Mux0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF588; +defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N8 +cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|rx_data [3]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hF0F0; +defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N9 +dffeas \uart_rx_inst|rx_data[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N26 +cycloneive_lcell_comb \uart_rx_inst|rx_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[1]~feeder_combout = \uart_rx_inst|rx_data [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [2]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N27 +dffeas \uart_rx_inst|rx_data[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N19 +dffeas \uart_rx_inst|po_data[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [1]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N12 +cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|rx_data [1]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hF0F0; +defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N13 +dffeas \uart_rx_inst|rx_data[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N29 +dffeas \uart_rx_inst|po_data[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [0]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N28 +cycloneive_lcell_comb \uart_tx_inst|tx~3 ( +// Equation(s): +// \uart_tx_inst|tx~3_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\uart_rx_inst|po_data [2])) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_rx_inst|po_data [0]))))) + + .dataa(\uart_rx_inst|po_data [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_rx_inst|po_data [0]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~3 .lut_mask = 16'h88C0; +defparam \uart_tx_inst|tx~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N18 +cycloneive_lcell_comb \uart_tx_inst|tx~4 ( +// Equation(s): +// \uart_tx_inst|tx~4_combout = (\uart_tx_inst|tx~3_combout ) # ((\uart_tx_inst|bit_cnt [1] & (!\uart_tx_inst|bit_cnt [0] & \uart_rx_inst|po_data [1]))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_rx_inst|po_data [1]), + .datad(\uart_tx_inst|tx~3_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~4 .lut_mask = 16'hFF20; +defparam \uart_tx_inst|tx~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N10 +cycloneive_lcell_comb \uart_tx_inst|tx~6 ( +// Equation(s): +// \uart_tx_inst|tx~6_combout = (\uart_tx_inst|bit_flag~q & ((\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|tx~4_combout )))) # (!\uart_tx_inst|bit_flag~q & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout ))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\uart_tx_inst|Mux0~1_combout ), + .datad(\uart_tx_inst|tx~4_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~6 .lut_mask = 16'hAE8C; +defparam \uart_tx_inst|tx~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N12 +cycloneive_lcell_comb \uart_tx_inst|tx~7 ( +// Equation(s): +// \uart_tx_inst|tx~7_combout = (\uart_tx_inst|tx~5_combout & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout & !\uart_tx_inst|tx~6_combout ))) # (!\uart_tx_inst|tx~5_combout & (((\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|Mux0~1_combout )) # +// (!\uart_tx_inst|tx~6_combout ))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|tx~5_combout ), + .datac(\uart_tx_inst|Mux0~1_combout ), + .datad(\uart_tx_inst|tx~6_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~7_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~7 .lut_mask = 16'h023B; +defparam \uart_tx_inst|tx~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N13 +dffeas \uart_tx_inst|tx ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|tx~7_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|tx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|tx .is_wysiwyg = "true"; +defparam \uart_tx_inst|tx .power_up = "low"; +// synopsys translate_on + +assign tx = \tx~output_o ; + +endmodule diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_0c_v_slow.sdo b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_0c_v_slow.sdo new file mode 100644 index 0000000..4c542b2 --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_0c_v_slow.sdo @@ -0,0 +1,2275 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "rs232") + (DATE "06/02/2023 03:03:50") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5091:5091:5091) (5076:5076:5076)) + (PORT sclr (850:850:850) (911:911:911)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (393:393:393)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5313:5313:5313) (5387:5387:5387)) + (PORT sclr (845:845:845) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5313:5313:5313) (5387:5387:5387)) + (PORT sclr (845:845:845) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5313:5313:5313) (5387:5387:5387)) + (PORT sclr (845:845:845) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5313:5313:5313) (5387:5387:5387)) + (PORT sclr (845:845:845) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5313:5313:5313) (5387:5387:5387)) + (PORT sclr (845:845:845) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5313:5313:5313) (5387:5387:5387)) + (PORT sclr (845:845:845) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5313:5313:5313) (5387:5387:5387)) + (PORT sclr (845:845:845) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5313:5313:5313) (5387:5387:5387)) + (PORT sclr (845:845:845) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5313:5313:5313) (5387:5387:5387)) + (PORT sclr (845:845:845) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5313:5313:5313) (5387:5387:5387)) + (PORT sclr (845:845:845) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5313:5313:5313) (5387:5387:5387)) + (PORT sclr (845:845:845) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5313:5313:5313) (5387:5387:5387)) + (PORT sclr (845:845:845) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5313:5313:5313) (5387:5387:5387)) + (PORT sclr (845:845:845) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (526:526:526)) + (PORT datab (325:325:325) (382:382:382)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (392:392:392)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (405:405:405)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (411:411:411)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (416:416:416)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (349:349:349) (407:407:407)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (384:384:384)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (533:533:533) (518:518:518)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (425:425:425)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (514:514:514) (500:500:500)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT asdata (1249:1249:1249) (1141:1141:1141)) + (PORT clrn (4857:4857:4857) (4790:4790:4790)) + (PORT ena (1637:1637:1637) (1491:1491:1491)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (569:569:569)) + (PORT datab (559:559:559) (535:535:535)) + (PORT datac (510:510:510) (500:500:500)) + (PORT datad (520:520:520) (500:500:500)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (439:439:439)) + (PORT datab (409:409:409) (479:479:479)) + (PORT datad (353:353:353) (433:433:433)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (581:581:581)) + (PORT datab (552:552:552) (527:527:527)) + (PORT datac (555:555:555) (525:525:525)) + (PORT datad (309:309:309) (368:368:368)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (398:398:398)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5097:5097:5097) (5081:5081:5081)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (392:392:392)) + (PORT datab (328:328:328) (386:386:386)) + (PORT datac (283:283:283) (349:349:349)) + (PORT datad (287:287:287) (345:345:345)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (736:736:736)) + (PORT datab (556:556:556) (541:541:541)) + (PORT datac (561:561:561) (532:532:532)) + (PORT datad (834:834:834) (717:717:717)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (757:757:757)) + (PORT datab (889:889:889) (770:770:770)) + (PORT datac (855:855:855) (742:742:742)) + (PORT datad (557:557:557) (537:537:537)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (431:431:431)) + (PORT datab (861:861:861) (762:762:762)) + (PORT datac (775:775:775) (623:623:623)) + (PORT datad (479:479:479) (407:407:407)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5311:5311:5311) (5384:5384:5384)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (418:418:418)) + (PORT datab (350:350:350) (409:409:409)) + (PORT datac (308:308:308) (375:375:375)) + (PORT datad (310:310:310) (371:371:371)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datac (799:799:799) (710:710:710)) + (PORT datad (557:557:557) (538:538:538)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (757:757:757)) + (PORT datab (559:559:559) (549:549:549)) + (PORT datac (819:819:819) (718:718:718)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (528:528:528)) + (PORT datab (290:290:290) (298:298:298)) + (PORT datac (230:230:230) (245:245:245)) + (PORT datad (428:428:428) (359:359:359)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|start_nedge) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5084:5084:5084) (5071:5071:5071)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (834:834:834) (727:727:727)) + (PORT datad (451:451:451) (388:388:388)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (385:385:385)) + (PORT datac (300:300:300) (364:364:364)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tx\~output) + (DELAY + (ABSOLUTE + (PORT i (677:677:677) (772:772:772)) + (IOPATH i o (2961:2961:2961) (3013:3013:3013)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (788:788:788) (813:813:813)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sys_clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (175:175:175) (172:172:172)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (435:435:435)) + (PORT datab (326:326:326) (384:384:384)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (437:437:437)) + (PORT datab (341:341:341) (404:404:404)) + (PORT datac (441:441:441) (375:375:375)) + (PORT datad (255:255:255) (273:273:273)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5097:5097:5097) (5081:5081:5081)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5097:5097:5097) (5081:5081:5081)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5097:5097:5097) (5081:5081:5081)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (384:384:384)) + (PORT datac (286:286:286) (352:352:352)) + (PORT datad (285:285:285) (344:344:344)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (370:370:370)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (437:437:437)) + (PORT datab (297:297:297) (313:313:313)) + (PORT datad (437:437:437) (371:371:371)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5097:5097:5097) (5081:5081:5081)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (438:438:438)) + (PORT datab (348:348:348) (411:411:411)) + (PORT datad (249:249:249) (266:266:266)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (249:249:249) (266:266:266)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_flag) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5097:5097:5097) (5081:5081:5081)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (853:853:853) (737:737:737)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_flag) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4857:4857:4857) (4790:4790:4790)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (524:524:524) (501:501:501)) + (PORT datad (462:462:462) (399:399:399)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5084:5084:5084) (5071:5071:5071)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (558:558:558)) + (PORT datab (323:323:323) (380:380:380)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5091:5091:5091) (5076:5076:5076)) + (PORT sclr (850:850:850) (911:911:911)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (394:394:394)) + (PORT datab (329:329:329) (386:386:386)) + (PORT datac (285:285:285) (351:351:351)) + (PORT datad (285:285:285) (344:344:344)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (540:540:540)) + (PORT datab (329:329:329) (386:386:386)) + (PORT datac (517:517:517) (503:503:503)) + (PORT datad (230:230:230) (238:238:238)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (404:404:404)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5091:5091:5091) (5076:5076:5076)) + (PORT sclr (850:850:850) (911:911:911)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT datab (617:617:617) (577:577:577)) + (PORT datad (556:556:556) (536:536:536)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (401:401:401)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5091:5091:5091) (5076:5076:5076)) + (PORT sclr (850:850:850) (911:911:911)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5091:5091:5091) (5076:5076:5076)) + (PORT sclr (850:850:850) (911:911:911)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (545:545:545)) + (PORT datab (560:560:560) (536:536:536)) + (PORT datac (510:510:510) (500:500:500)) + (PORT datad (548:548:548) (519:519:519)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (561:561:561)) + (PORT datab (295:295:295) (303:303:303)) + (PORT datac (441:441:441) (377:377:377)) + (PORT datad (446:446:446) (387:387:387)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5091:5091:5091) (5076:5076:5076)) + (PORT sclr (850:850:850) (911:911:911)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5091:5091:5091) (5076:5076:5076)) + (PORT sclr (850:850:850) (911:911:911)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5091:5091:5091) (5076:5076:5076)) + (PORT sclr (850:850:850) (911:911:911)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5091:5091:5091) (5076:5076:5076)) + (PORT sclr (850:850:850) (911:911:911)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5091:5091:5091) (5076:5076:5076)) + (PORT sclr (850:850:850) (911:911:911)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5091:5091:5091) (5076:5076:5076)) + (PORT sclr (850:850:850) (911:911:911)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5091:5091:5091) (5076:5076:5076)) + (PORT sclr (850:850:850) (911:911:911)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5091:5091:5091) (5076:5076:5076)) + (PORT sclr (850:850:850) (911:911:911)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (638:638:638)) + (PORT datab (619:619:619) (579:579:579)) + (PORT datac (514:514:514) (445:445:445)) + (PORT datad (557:557:557) (537:537:537)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5084:5084:5084) (5071:5071:5071)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT datac (299:299:299) (363:363:363)) + (PORT datad (305:305:305) (364:364:364)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (610:610:610)) + (PORT datab (310:310:310) (323:323:323)) + (PORT datad (504:504:504) (435:435:435)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4857:4857:4857) (4790:4790:4790)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (285:285:285)) + (PORT datab (294:294:294) (302:302:302)) + (PORT datad (461:461:461) (398:398:398)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5084:5084:5084) (5071:5071:5071)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (403:403:403)) + (PORT datad (307:307:307) (365:365:365)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (474:474:474)) + (PORT datab (404:404:404) (474:474:474)) + (PORT datac (328:328:328) (404:404:404)) + (PORT datad (478:478:478) (406:406:406)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (577:577:577)) + (PORT datab (307:307:307) (320:320:320)) + (PORT datad (816:816:816) (723:723:723)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4857:4857:4857) (4790:4790:4790)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rx\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (778:778:778) (803:803:803)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg1\~0) + (DELAY + (ABSOLUTE + (PORT datad (3220:3220:3220) (3254:3254:3254)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5084:5084:5084) (5071:5071:5071)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (280:280:280) (335:335:335)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5084:5084:5084) (5071:5071:5071)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (289:289:289) (348:348:348)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg3) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5084:5084:5084) (5071:5071:5071)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (794:794:794) (704:704:704)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (436:436:436)) + (PORT datab (295:295:295) (310:310:310)) + (PORT datad (300:300:300) (365:365:365)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5097:5097:5097) (5081:5081:5081)) + (PORT ena (968:968:968) (937:937:937)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT asdata (1210:1210:1210) (1123:1123:1123)) + (PORT clrn (4857:4857:4857) (4790:4790:4790)) + (PORT ena (1637:1637:1637) (1491:1491:1491)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (591:591:591)) + (PORT datab (307:307:307) (321:321:321)) + (PORT datad (507:507:507) (438:438:438)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4857:4857:4857) (4790:4790:4790)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (445:445:445)) + (PORT datab (401:401:401) (472:472:472)) + (PORT datad (347:347:347) (427:427:427)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~5) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (532:532:532) (534:534:534)) + (PORT datad (517:517:517) (502:502:502)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (359:359:359)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5097:5097:5097) (5081:5081:5081)) + (PORT ena (968:968:968) (937:937:937)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT asdata (1212:1212:1212) (1107:1107:1107)) + (PORT clrn (5097:5097:5097) (5081:5081:5081)) + (PORT ena (968:968:968) (937:937:937)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (800:800:800) (702:702:702)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4857:4857:4857) (4790:4790:4790)) + (PORT ena (1637:1637:1637) (1491:1491:1491)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT asdata (1225:1225:1225) (1128:1128:1128)) + (PORT clrn (4857:4857:4857) (4790:4790:4790)) + (PORT ena (1637:1637:1637) (1491:1491:1491)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT asdata (1179:1179:1179) (1099:1099:1099)) + (PORT clrn (5097:5097:5097) (5081:5081:5081)) + (PORT ena (968:968:968) (937:937:937)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (798:798:798) (704:704:704)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4857:4857:4857) (4790:4790:4790)) + (PORT ena (1637:1637:1637) (1491:1491:1491)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT asdata (1175:1175:1175) (1097:1097:1097)) + (PORT clrn (5097:5097:5097) (5081:5081:5081)) + (PORT ena (968:968:968) (937:937:937)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT asdata (1553:1553:1553) (1357:1357:1357)) + (PORT clrn (4857:4857:4857) (4790:4790:4790)) + (PORT ena (1637:1637:1637) (1491:1491:1491)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (478:478:478)) + (PORT datab (320:320:320) (375:375:375)) + (PORT datad (367:367:367) (442:442:442)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (476:476:476)) + (PORT datab (318:318:318) (373:373:373)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (301:301:301) (365:365:365)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5097:5097:5097) (5081:5081:5081)) + (PORT ena (968:968:968) (937:937:937)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (497:497:497) (480:480:480)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5097:5097:5097) (5081:5081:5081)) + (PORT ena (968:968:968) (937:937:937)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT asdata (1246:1246:1246) (1145:1145:1145)) + (PORT clrn (4857:4857:4857) (4790:4790:4790)) + (PORT ena (1637:1637:1637) (1491:1491:1491)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (300:300:300) (364:364:364)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5097:5097:5097) (5081:5081:5081)) + (PORT ena (968:968:968) (937:937:937)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT asdata (1236:1236:1236) (1138:1138:1138)) + (PORT clrn (4857:4857:4857) (4790:4790:4790)) + (PORT ena (1637:1637:1637) (1491:1491:1491)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~3) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (379:379:379)) + (PORT datab (410:410:410) (481:481:481)) + (PORT datad (354:354:354) (434:434:434)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~4) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (478:478:478)) + (PORT datab (407:407:407) (478:478:478)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~6) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (575:575:575)) + (PORT datab (558:558:558) (545:545:545)) + (PORT datac (234:234:234) (252:252:252)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~7) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (446:446:446)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (234:234:234) (253:253:253)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|tx) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4857:4857:4857) (4790:4790:4790)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_85c_slow.vo b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_85c_slow.vo new file mode 100644 index 0000000..b3f326c --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_85c_slow.vo @@ -0,0 +1,2836 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 03:03:50" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module rs232 ( + sys_clk, + sys_rst_n, + rx, + tx); +input sys_clk; +input sys_rst_n; +input rx; +output tx; + +// Design Ports Information +// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("rs232_8_1200mv_85c_v_slow.sdo"); +// synopsys translate_on + +wire \uart_tx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|baud_cnt[0]~13_combout ; +wire \uart_rx_inst|baud_cnt[0]~14 ; +wire \uart_rx_inst|baud_cnt[1]~15_combout ; +wire \uart_rx_inst|baud_cnt[1]~16 ; +wire \uart_rx_inst|baud_cnt[2]~17_combout ; +wire \uart_rx_inst|baud_cnt[2]~18 ; +wire \uart_rx_inst|baud_cnt[3]~19_combout ; +wire \uart_rx_inst|baud_cnt[3]~20 ; +wire \uart_rx_inst|baud_cnt[4]~21_combout ; +wire \uart_rx_inst|baud_cnt[4]~22 ; +wire \uart_rx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|baud_cnt[5]~24 ; +wire \uart_rx_inst|baud_cnt[6]~25_combout ; +wire \uart_rx_inst|baud_cnt[6]~26 ; +wire \uart_rx_inst|baud_cnt[7]~27_combout ; +wire \uart_rx_inst|baud_cnt[7]~28 ; +wire \uart_rx_inst|baud_cnt[8]~29_combout ; +wire \uart_rx_inst|baud_cnt[8]~30 ; +wire \uart_rx_inst|baud_cnt[9]~31_combout ; +wire \uart_rx_inst|baud_cnt[9]~32 ; +wire \uart_rx_inst|baud_cnt[10]~33_combout ; +wire \uart_rx_inst|baud_cnt[10]~34 ; +wire \uart_rx_inst|baud_cnt[11]~35_combout ; +wire \uart_rx_inst|baud_cnt[11]~36 ; +wire \uart_rx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal2~0_combout ; +wire \uart_tx_inst|Add1~0_combout ; +wire \uart_tx_inst|Add1~1_combout ; +wire \uart_rx_inst|bit_flag~q ; +wire \uart_rx_inst|Equal1~0_combout ; +wire \uart_rx_inst|Equal2~0_combout ; +wire \uart_rx_inst|Equal2~1_combout ; +wire \uart_rx_inst|Equal2~2_combout ; +wire \uart_rx_inst|work_en~q ; +wire \uart_rx_inst|Equal1~1_combout ; +wire \uart_rx_inst|Equal1~2_combout ; +wire \uart_rx_inst|Equal1~3_combout ; +wire \uart_rx_inst|always5~0_combout ; +wire \uart_rx_inst|start_nedge~q ; +wire \uart_rx_inst|work_en~0_combout ; +wire \uart_rx_inst|always3~0_combout ; +wire \tx~output_o ; +wire \sys_clk~input_o ; +wire \sys_clk~inputclkctrl_outclk ; +wire \uart_rx_inst|Add1~0_combout ; +wire \uart_rx_inst|bit_cnt~1_combout ; +wire \sys_rst_n~input_o ; +wire \uart_rx_inst|Add1~1 ; +wire \uart_rx_inst|Add1~2_combout ; +wire \uart_rx_inst|Add1~3 ; +wire \uart_rx_inst|Add1~4_combout ; +wire \uart_rx_inst|always4~0_combout ; +wire \uart_rx_inst|Add1~5 ; +wire \uart_rx_inst|Add1~6_combout ; +wire \uart_rx_inst|bit_cnt~0_combout ; +wire \uart_rx_inst|always4~1_combout ; +wire \uart_rx_inst|rx_flag~feeder_combout ; +wire \uart_rx_inst|rx_flag~q ; +wire \uart_rx_inst|po_flag~feeder_combout ; +wire \uart_rx_inst|po_flag~q ; +wire \uart_tx_inst|work_en~0_combout ; +wire \uart_tx_inst|work_en~q ; +wire \uart_tx_inst|baud_cnt[0]~13_combout ; +wire \uart_tx_inst|baud_cnt[10]~34 ; +wire \uart_tx_inst|baud_cnt[11]~35_combout ; +wire \uart_tx_inst|Equal1~0_combout ; +wire \uart_tx_inst|Equal1~1_combout ; +wire \uart_tx_inst|baud_cnt[11]~36 ; +wire \uart_tx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal1~3_combout ; +wire \uart_tx_inst|baud_cnt[2]~17_combout ; +wire \uart_tx_inst|baud_cnt[4]~21_combout ; +wire \uart_tx_inst|Equal1~2_combout ; +wire \uart_tx_inst|always1~0_combout ; +wire \uart_tx_inst|baud_cnt[0]~14 ; +wire \uart_tx_inst|baud_cnt[1]~15_combout ; +wire \uart_tx_inst|baud_cnt[1]~16 ; +wire \uart_tx_inst|baud_cnt[2]~18 ; +wire \uart_tx_inst|baud_cnt[3]~19_combout ; +wire \uart_tx_inst|baud_cnt[3]~20 ; +wire \uart_tx_inst|baud_cnt[4]~22 ; +wire \uart_tx_inst|baud_cnt[5]~24 ; +wire \uart_tx_inst|baud_cnt[6]~25_combout ; +wire \uart_tx_inst|baud_cnt[6]~26 ; +wire \uart_tx_inst|baud_cnt[7]~27_combout ; +wire \uart_tx_inst|baud_cnt[7]~28 ; +wire \uart_tx_inst|baud_cnt[8]~29_combout ; +wire \uart_tx_inst|baud_cnt[8]~30 ; +wire \uart_tx_inst|baud_cnt[9]~31_combout ; +wire \uart_tx_inst|baud_cnt[9]~32 ; +wire \uart_tx_inst|baud_cnt[10]~33_combout ; +wire \uart_tx_inst|Equal2~1_combout ; +wire \uart_tx_inst|bit_flag~q ; +wire \uart_tx_inst|always3~0_combout ; +wire \uart_tx_inst|bit_cnt[2]~2_combout ; +wire \uart_tx_inst|bit_cnt[3]~4_combout ; +wire \uart_tx_inst|always0~0_combout ; +wire \uart_tx_inst|always0~1_combout ; +wire \uart_tx_inst|bit_cnt[0]~5_combout ; +wire \rx~input_o ; +wire \uart_rx_inst|rx_reg1~0_combout ; +wire \uart_rx_inst|rx_reg1~q ; +wire \uart_rx_inst|rx_reg2~feeder_combout ; +wire \uart_rx_inst|rx_reg2~q ; +wire \uart_rx_inst|rx_reg3~feeder_combout ; +wire \uart_rx_inst|rx_reg3~q ; +wire \uart_rx_inst|rx_data[7]~0_combout ; +wire \uart_rx_inst|always8~0_combout ; +wire \uart_tx_inst|bit_cnt[1]~3_combout ; +wire \uart_tx_inst|tx~2_combout ; +wire \uart_tx_inst|tx~5_combout ; +wire \uart_rx_inst|rx_data[6]~feeder_combout ; +wire \uart_rx_inst|po_data[5]~feeder_combout ; +wire \uart_rx_inst|po_data[4]~feeder_combout ; +wire \uart_tx_inst|Mux0~0_combout ; +wire \uart_tx_inst|Mux0~1_combout ; +wire \uart_rx_inst|rx_data[2]~feeder_combout ; +wire \uart_rx_inst|rx_data[1]~feeder_combout ; +wire \uart_rx_inst|rx_data[0]~feeder_combout ; +wire \uart_tx_inst|tx~3_combout ; +wire \uart_tx_inst|tx~4_combout ; +wire \uart_tx_inst|tx~6_combout ; +wire \uart_tx_inst|tx~7_combout ; +wire \uart_tx_inst|tx~q ; +wire [7:0] \uart_rx_inst|rx_data ; +wire [7:0] \uart_rx_inst|po_data ; +wire [3:0] \uart_rx_inst|bit_cnt ; +wire [12:0] \uart_rx_inst|baud_cnt ; +wire [3:0] \uart_tx_inst|bit_cnt ; +wire [12:0] \uart_tx_inst|baud_cnt ; + + +// Location: FF_X6_Y9_N13 +dffeas \uart_tx_inst|baud_cnt[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N12 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[4]~22 ), + .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_tx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y9_N5 +dffeas \uart_rx_inst|baud_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N7 +dffeas \uart_rx_inst|baud_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N19 +dffeas \uart_rx_inst|baud_cnt[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N21 +dffeas \uart_rx_inst|baud_cnt[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N11 +dffeas \uart_rx_inst|baud_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N15 +dffeas \uart_rx_inst|baud_cnt[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N9 +dffeas \uart_rx_inst|baud_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N13 +dffeas \uart_rx_inst|baud_cnt[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N23 +dffeas \uart_rx_inst|baud_cnt[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N27 +dffeas \uart_rx_inst|baud_cnt[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N17 +dffeas \uart_rx_inst|baud_cnt[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N25 +dffeas \uart_rx_inst|baud_cnt[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N29 +dffeas \uart_rx_inst|baud_cnt[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N4 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) +// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_rx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N6 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) + + .dataa(\uart_rx_inst|baud_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[0]~14 ), + .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_rx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N8 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) +// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[1]~16 ), + .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_rx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N10 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) + + .dataa(\uart_rx_inst|baud_cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[2]~18 ), + .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_rx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N12 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) +// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[3]~20 ), + .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_rx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N14 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[4]~22 ), + .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_rx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N16 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) +// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[5]~24 ), + .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_rx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N18 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[6]~26 ), + .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_rx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N20 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) +// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[7]~28 ), + .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_rx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N22 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[8]~30 ), + .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_rx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N24 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) +// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[9]~32 ), + .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_rx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N26 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) + + .dataa(\uart_rx_inst|baud_cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[10]~34 ), + .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_rx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N28 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt[11]~36 $ (!\uart_rx_inst|baud_cnt [12]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|baud_cnt [12]), + .cin(\uart_rx_inst|baud_cnt[11]~36 ), + .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; +defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X4_Y9_N23 +dffeas \uart_rx_inst|po_data[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [2]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( +// Equation(s): +// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [6]))) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(\uart_tx_inst|baud_cnt [2]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [6]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N22 +cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( +// Equation(s): +// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(gnd), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h66AA; +defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N22 +cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( +// Equation(s): +// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [0] & (\uart_tx_inst|bit_cnt [1] & \uart_tx_inst|bit_cnt [2])))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h7F80; +defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N11 +dffeas \uart_rx_inst|bit_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|Equal2~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( +// Equation(s): +// \uart_rx_inst|Equal1~0_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [0] & !\uart_rx_inst|baud_cnt [8]))) + + .dataa(\uart_rx_inst|baud_cnt [1]), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(\uart_rx_inst|baud_cnt [0]), + .datad(\uart_rx_inst|baud_cnt [8]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N4 +cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( +// Equation(s): +// \uart_rx_inst|Equal2~0_combout = (\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [4]))) + + .dataa(\uart_rx_inst|baud_cnt [5]), + .datab(\uart_rx_inst|baud_cnt [3]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0008; +defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N6 +cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( +// Equation(s): +// \uart_rx_inst|Equal2~1_combout = (\uart_rx_inst|baud_cnt [9] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [10]))) + + .dataa(\uart_rx_inst|baud_cnt [9]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [6]), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0008; +defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N10 +cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( +// Equation(s): +// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal2~1_combout & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal2~0_combout ))) + + .dataa(\uart_rx_inst|Equal2~1_combout ), + .datab(\uart_rx_inst|baud_cnt [12]), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000; +defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X9_Y9_N17 +dffeas \uart_rx_inst|work_en ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_rx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N30 +cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( +// Equation(s): +// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N2 +cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( +// Equation(s): +// \uart_rx_inst|Equal1~2_combout = (!\uart_rx_inst|baud_cnt [11] & \uart_rx_inst|baud_cnt [10]) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|baud_cnt [11]), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0F00; +defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N8 +cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( +// Equation(s): +// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt [9] & \uart_rx_inst|Equal1~2_combout ))) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(\uart_rx_inst|baud_cnt [9]), + .datad(\uart_rx_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h0800; +defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N2 +cycloneive_lcell_comb \uart_rx_inst|always5~0 ( +// Equation(s): +// \uart_rx_inst|always5~0_combout = ((\uart_rx_inst|Equal1~0_combout & (\uart_rx_inst|Equal1~1_combout & \uart_rx_inst|Equal1~3_combout ))) # (!\uart_rx_inst|work_en~q ) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|Equal1~0_combout ), + .datac(\uart_rx_inst|Equal1~1_combout ), + .datad(\uart_rx_inst|Equal1~3_combout ), + .cin(gnd), + .combout(\uart_rx_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always5~0 .lut_mask = 16'hD555; +defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N13 +dffeas \uart_rx_inst|start_nedge ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|always3~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|start_nedge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; +defparam \uart_rx_inst|start_nedge .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N16 +cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( +// Equation(s): +// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) + + .dataa(gnd), + .datab(\uart_rx_inst|start_nedge~q ), + .datac(\uart_rx_inst|work_en~q ), + .datad(\uart_rx_inst|always4~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hCCFC; +defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N12 +cycloneive_lcell_comb \uart_rx_inst|always3~0 ( +// Equation(s): +// \uart_rx_inst|always3~0_combout = (\uart_rx_inst|rx_reg2~q & !\uart_rx_inst|rx_reg3~q ) + + .dataa(gnd), + .datab(\uart_rx_inst|rx_reg2~q ), + .datac(\uart_rx_inst|rx_reg3~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always3~0 .lut_mask = 16'h0C0C; +defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y9_N16 +cycloneive_io_obuf \tx~output ( + .i(!\uart_tx_inst|tx~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tx~output_o ), + .obar()); +// synopsys translate_off +defparam \tx~output .bus_hold = "false"; +defparam \tx~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \sys_clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sys_clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sys_clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \sys_clk~inputclkctrl .clock_type = "global clock"; +defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N16 +cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( +// Equation(s): +// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] & VCC)) +// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [0])) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|Add1~0_combout ), + .cout(\uart_rx_inst|Add1~1 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; +defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N4 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~1_combout = \uart_rx_inst|Add1~0_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(\uart_rx_inst|Add1~0_combout ), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h78F0; +defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X8_Y9_N5 +dffeas \uart_rx_inst|bit_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N18 +cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( +// Equation(s): +// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) +// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~1 ), + .combout(\uart_rx_inst|Add1~2_combout ), + .cout(\uart_rx_inst|Add1~3 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X8_Y9_N19 +dffeas \uart_rx_inst|bit_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|Add1~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N20 +cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( +// Equation(s): +// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) +// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~3 ), + .combout(\uart_rx_inst|Add1~4_combout ), + .cout(\uart_rx_inst|Add1~5 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X8_Y9_N21 +dffeas \uart_rx_inst|bit_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|Add1~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N24 +cycloneive_lcell_comb \uart_rx_inst|always4~0 ( +// Equation(s): +// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [2])) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [1]), + .datac(\uart_rx_inst|bit_cnt [0]), + .datad(\uart_rx_inst|bit_cnt [2]), + .cin(gnd), + .combout(\uart_rx_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0003; +defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N22 +cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( +// Equation(s): +// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|Add1~5 $ (\uart_rx_inst|bit_cnt [3]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(\uart_rx_inst|Add1~5 ), + .combout(\uart_rx_inst|Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h0FF0; +defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~0_combout = \uart_rx_inst|Add1~6_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout & \uart_rx_inst|bit_cnt [3])))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(\uart_rx_inst|Add1~6_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h7F80; +defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N1 +dffeas \uart_rx_inst|bit_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N30 +cycloneive_lcell_comb \uart_rx_inst|always4~1 ( +// Equation(s): +// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(gnd), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~1 .lut_mask = 16'h8800; +defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N14 +cycloneive_lcell_comb \uart_rx_inst|rx_flag~feeder ( +// Equation(s): +// \uart_rx_inst|rx_flag~feeder_combout = \uart_rx_inst|always4~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|always4~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag~feeder .lut_mask = 16'hF0F0; +defparam \uart_rx_inst|rx_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N15 +dffeas \uart_rx_inst|rx_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_flag~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N30 +cycloneive_lcell_comb \uart_rx_inst|po_flag~feeder ( +// Equation(s): +// \uart_rx_inst|po_flag~feeder_combout = \uart_rx_inst|rx_flag~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_flag~q ), + .cin(gnd), + .combout(\uart_rx_inst|po_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_flag~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N31 +dffeas \uart_rx_inst|po_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|po_flag~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N14 +cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( +// Equation(s): +// \uart_tx_inst|work_en~0_combout = (\uart_rx_inst|po_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) + + .dataa(gnd), + .datab(\uart_rx_inst|po_flag~q ), + .datac(\uart_tx_inst|work_en~q ), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hCCFC; +defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N15 +dffeas \uart_tx_inst|work_en ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_tx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N2 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) +// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_tx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N22 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) +// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[9]~32 ), + .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_tx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N24 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[10]~34 ), + .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_tx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N25 +dffeas \uart_tx_inst|baud_cnt[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N28 +cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( +// Equation(s): +// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [5] & (\uart_tx_inst|baud_cnt [0] & (!\uart_tx_inst|baud_cnt [3] & !\uart_tx_inst|baud_cnt [7]))) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(\uart_tx_inst|baud_cnt [3]), + .datad(\uart_tx_inst|baud_cnt [7]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0004; +defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N0 +cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( +// Equation(s): +// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt [11] & \uart_tx_inst|Equal1~0_combout ))) + + .dataa(\uart_tx_inst|baud_cnt [9]), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(\uart_tx_inst|baud_cnt [11]), + .datad(\uart_tx_inst|Equal1~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0100; +defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N26 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_tx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_tx_inst|baud_cnt[11]~36 ), + .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N27 +dffeas \uart_tx_inst|baud_cnt[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N16 +cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( +// Equation(s): +// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [12] & \uart_tx_inst|baud_cnt [10]) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(gnd), + .datad(\uart_tx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hCC00; +defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N6 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) +// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[1]~16 ), + .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_tx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N7 +dffeas \uart_tx_inst|baud_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N10 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) +// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[3]~20 ), + .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_tx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N11 +dffeas \uart_tx_inst|baud_cnt[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y9_N6 +cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( +// Equation(s): +// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4]))) + + .dataa(\uart_tx_inst|baud_cnt [6]), + .datab(\uart_tx_inst|baud_cnt [2]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; +defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N30 +cycloneive_lcell_comb \uart_tx_inst|always1~0 ( +// Equation(s): +// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~1_combout & (\uart_tx_inst|Equal1~3_combout & \uart_tx_inst|Equal1~2_combout ))) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|Equal1~1_combout ), + .datac(\uart_tx_inst|Equal1~3_combout ), + .datad(\uart_tx_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555; +defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X6_Y9_N3 +dffeas \uart_tx_inst|baud_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[0]~14 ), + .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_tx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N5 +dffeas \uart_tx_inst|baud_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N8 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[2]~18 ), + .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_tx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N9 +dffeas \uart_tx_inst|baud_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N14 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) +// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[5]~24 ), + .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_tx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N15 +dffeas \uart_tx_inst|baud_cnt[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N16 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[6]~26 ), + .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_tx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N17 +dffeas \uart_tx_inst|baud_cnt[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N18 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) +// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[7]~28 ), + .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_tx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N19 +dffeas \uart_tx_inst|baud_cnt[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N20 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[8]~30 ), + .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_tx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N21 +dffeas \uart_tx_inst|baud_cnt[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X6_Y9_N23 +dffeas \uart_tx_inst|baud_cnt[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N20 +cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( +// Equation(s): +// \uart_tx_inst|Equal2~1_combout = (\uart_tx_inst|Equal2~0_combout & (!\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|Equal1~1_combout & !\uart_tx_inst|baud_cnt [12]))) + + .dataa(\uart_tx_inst|Equal2~0_combout ), + .datab(\uart_tx_inst|baud_cnt [10]), + .datac(\uart_tx_inst|Equal1~1_combout ), + .datad(\uart_tx_inst|baud_cnt [12]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h0020; +defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N21 +dffeas \uart_tx_inst|bit_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|Equal2~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N24 +cycloneive_lcell_comb \uart_tx_inst|always3~0 ( +// Equation(s): +// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_tx_inst|work_en~q ), + .datad(\uart_tx_inst|bit_flag~q ), + .cin(gnd), + .combout(\uart_tx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always3~0 .lut_mask = 16'h0FFF; +defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N26 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~2 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[2]~2_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~0_combout )))) + + .dataa(\uart_tx_inst|Add1~0_combout ), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always3~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2]~2 .lut_mask = 16'h3022; +defparam \uart_tx_inst|bit_cnt[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N27 +dffeas \uart_tx_inst|bit_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[2]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N2 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~4 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[3]~4_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [3]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) + + .dataa(\uart_tx_inst|Add1~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3]~4 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N3 +dffeas \uart_tx_inst|bit_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[3]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|always0~0 ( +// Equation(s): +// \uart_tx_inst|always0~0_combout = (\uart_tx_inst|bit_cnt [3] & \uart_tx_inst|bit_flag~q ) + + .dataa(gnd), + .datab(\uart_tx_inst|bit_cnt [3]), + .datac(gnd), + .datad(\uart_tx_inst|bit_flag~q ), + .cin(gnd), + .combout(\uart_tx_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~0 .lut_mask = 16'hCC00; +defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N8 +cycloneive_lcell_comb \uart_tx_inst|always0~1 ( +// Equation(s): +// \uart_tx_inst|always0~1_combout = (!\uart_tx_inst|bit_cnt [1] & (\uart_tx_inst|bit_cnt [0] & (!\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|always0~0_combout ))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~1 .lut_mask = 16'h0400; +defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N2 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|bit_flag~q & \uart_tx_inst|work_en~q ))))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h1230; +defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N3 +dffeas \uart_tx_inst|bit_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[0]~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \rx~input ( + .i(rx), + .ibar(gnd), + .o(\rx~input_o )); +// synopsys translate_off +defparam \rx~input .bus_hold = "false"; +defparam \rx~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N18 +cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( +// Equation(s): +// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rx~input_o ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N19 +dffeas \uart_rx_inst|rx_reg1 ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_reg1~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg1~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N1 +dffeas \uart_rx_inst|rx_reg2 ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_reg2~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N26 +cycloneive_lcell_comb \uart_rx_inst|rx_reg3~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg3~feeder_combout = \uart_rx_inst|rx_reg2~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg2~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N27 +dffeas \uart_rx_inst|rx_reg3 ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_reg3~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N28 +cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( +// Equation(s): +// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg3~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N6 +cycloneive_lcell_comb \uart_rx_inst|always8~0 ( +// Equation(s): +// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|always8~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8822; +defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N29 +dffeas \uart_rx_inst|rx_data[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[7]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N5 +dffeas \uart_rx_inst|po_data[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [7]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N6 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~3 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[1]~3_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [1]), + .datad(\uart_tx_inst|always3~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1]~3 .lut_mask = 16'h3012; +defparam \uart_tx_inst|bit_cnt[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N7 +dffeas \uart_tx_inst|bit_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[1]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|tx~2 ( +// Equation(s): +// \uart_tx_inst|tx~2_combout = (\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|bit_cnt [0]) # ((\uart_rx_inst|po_data [7]) # (\uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_rx_inst|po_data [7]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~2 .lut_mask = 16'hFFFE; +defparam \uart_tx_inst|tx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N16 +cycloneive_lcell_comb \uart_tx_inst|tx~5 ( +// Equation(s): +// \uart_tx_inst|tx~5_combout = (\uart_tx_inst|bit_flag~q & (((\uart_tx_inst|tx~2_combout & \uart_tx_inst|bit_cnt [3])))) # (!\uart_tx_inst|bit_flag~q & (!\uart_tx_inst|tx~q )) + + .dataa(\uart_tx_inst|tx~q ), + .datab(\uart_tx_inst|tx~2_combout ), + .datac(\uart_tx_inst|bit_flag~q ), + .datad(\uart_tx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_tx_inst|tx~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~5 .lut_mask = 16'hC505; +defparam \uart_tx_inst|tx~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[6]~feeder_combout = \uart_rx_inst|rx_data [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [7]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N3 +dffeas \uart_rx_inst|rx_data[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X8_Y9_N7 +dffeas \uart_rx_inst|rx_data[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [6]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N20 +cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N21 +dffeas \uart_rx_inst|po_data[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|po_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N15 +dffeas \uart_rx_inst|po_data[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [6]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X8_Y9_N31 +dffeas \uart_rx_inst|rx_data[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [5]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|po_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[4]~feeder_combout = \uart_rx_inst|rx_data [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [4]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N1 +dffeas \uart_rx_inst|po_data[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|po_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X8_Y9_N23 +dffeas \uart_rx_inst|rx_data[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [4]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N25 +dffeas \uart_rx_inst|po_data[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [3]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N24 +cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( +// Equation(s): +// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & (\uart_rx_inst|po_data [4])) # (!\uart_tx_inst|bit_cnt [0] & ((\uart_rx_inst|po_data [3]))))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_rx_inst|po_data [4]), + .datac(\uart_rx_inst|po_data [3]), + .datad(\uart_tx_inst|bit_cnt [0]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hEE50; +defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N14 +cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( +// Equation(s): +// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|Mux0~0_combout & ((\uart_rx_inst|po_data [6]))) # (!\uart_tx_inst|Mux0~0_combout & (\uart_rx_inst|po_data [5])))) # (!\uart_tx_inst|bit_cnt [1] & +// (((\uart_tx_inst|Mux0~0_combout )))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_rx_inst|po_data [5]), + .datac(\uart_rx_inst|po_data [6]), + .datad(\uart_tx_inst|Mux0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF588; +defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N8 +cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|rx_data [3]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hF0F0; +defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N9 +dffeas \uart_rx_inst|rx_data[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N26 +cycloneive_lcell_comb \uart_rx_inst|rx_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[1]~feeder_combout = \uart_rx_inst|rx_data [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [2]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N27 +dffeas \uart_rx_inst|rx_data[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N19 +dffeas \uart_rx_inst|po_data[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [1]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N12 +cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|rx_data [1]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hF0F0; +defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N13 +dffeas \uart_rx_inst|rx_data[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N29 +dffeas \uart_rx_inst|po_data[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [0]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N28 +cycloneive_lcell_comb \uart_tx_inst|tx~3 ( +// Equation(s): +// \uart_tx_inst|tx~3_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\uart_rx_inst|po_data [2])) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_rx_inst|po_data [0]))))) + + .dataa(\uart_rx_inst|po_data [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_rx_inst|po_data [0]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~3 .lut_mask = 16'h88C0; +defparam \uart_tx_inst|tx~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N18 +cycloneive_lcell_comb \uart_tx_inst|tx~4 ( +// Equation(s): +// \uart_tx_inst|tx~4_combout = (\uart_tx_inst|tx~3_combout ) # ((\uart_tx_inst|bit_cnt [1] & (!\uart_tx_inst|bit_cnt [0] & \uart_rx_inst|po_data [1]))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_rx_inst|po_data [1]), + .datad(\uart_tx_inst|tx~3_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~4 .lut_mask = 16'hFF20; +defparam \uart_tx_inst|tx~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N10 +cycloneive_lcell_comb \uart_tx_inst|tx~6 ( +// Equation(s): +// \uart_tx_inst|tx~6_combout = (\uart_tx_inst|bit_flag~q & ((\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|tx~4_combout )))) # (!\uart_tx_inst|bit_flag~q & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout ))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\uart_tx_inst|Mux0~1_combout ), + .datad(\uart_tx_inst|tx~4_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~6 .lut_mask = 16'hAE8C; +defparam \uart_tx_inst|tx~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N12 +cycloneive_lcell_comb \uart_tx_inst|tx~7 ( +// Equation(s): +// \uart_tx_inst|tx~7_combout = (\uart_tx_inst|tx~5_combout & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout & !\uart_tx_inst|tx~6_combout ))) # (!\uart_tx_inst|tx~5_combout & (((\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|Mux0~1_combout )) # +// (!\uart_tx_inst|tx~6_combout ))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|tx~5_combout ), + .datac(\uart_tx_inst|Mux0~1_combout ), + .datad(\uart_tx_inst|tx~6_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~7_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~7 .lut_mask = 16'h023B; +defparam \uart_tx_inst|tx~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N13 +dffeas \uart_tx_inst|tx ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|tx~7_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|tx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|tx .is_wysiwyg = "true"; +defparam \uart_tx_inst|tx .power_up = "low"; +// synopsys translate_on + +assign tx = \tx~output_o ; + +endmodule diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_85c_v_slow.sdo b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_85c_v_slow.sdo new file mode 100644 index 0000000..588ece3 --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_8_1200mv_85c_v_slow.sdo @@ -0,0 +1,2275 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "rs232") + (DATE "06/02/2023 03:03:50") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (590:590:590)) + (PORT datab (341:341:341) (422:422:422)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (457:457:457)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (461:461:461)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (368:368:368) (452:452:452)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (543:543:543) (580:580:580)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (471:471:471)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (533:533:533) (560:560:560)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (1301:1301:1301) (1261:1261:1261)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (642:642:642)) + (PORT datab (577:577:577) (601:601:601)) + (PORT datac (526:526:526) (560:560:560)) + (PORT datad (541:541:541) (560:560:560)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (487:487:487)) + (PORT datab (429:429:429) (538:538:538)) + (PORT datad (372:372:372) (479:479:479)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (654:654:654)) + (PORT datab (570:570:570) (590:590:590)) + (PORT datac (573:573:573) (591:591:591)) + (PORT datad (330:330:330) (407:407:407)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (PORT datab (344:344:344) (427:427:427)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (830:830:830)) + (PORT datab (575:575:575) (601:601:601)) + (PORT datac (579:579:579) (594:594:594)) + (PORT datad (851:851:851) (810:810:810)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (854:854:854)) + (PORT datab (901:901:901) (869:869:869)) + (PORT datac (872:872:872) (840:840:840)) + (PORT datad (577:577:577) (599:599:599)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (485:485:485)) + (PORT datab (878:878:878) (859:859:859)) + (PORT datac (783:783:783) (700:700:700)) + (PORT datad (485:485:485) (457:457:457)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6063:6063:6063) (5936:5936:5936)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (464:464:464)) + (PORT datab (370:370:370) (454:454:454)) + (PORT datac (330:330:330) (415:415:415)) + (PORT datad (331:331:331) (408:408:408)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datac (822:822:822) (795:795:795)) + (PORT datad (577:577:577) (600:600:600)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (854:854:854)) + (PORT datab (579:579:579) (612:612:612)) + (PORT datac (827:827:827) (807:807:807)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (592:592:592)) + (PORT datab (304:304:304) (328:328:328)) + (PORT datac (240:240:240) (267:267:267)) + (PORT datad (433:433:433) (406:406:406)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|start_nedge) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5805:5805:5805) (5615:5615:5615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (849:849:849) (813:813:813)) + (PORT datad (461:461:461) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (425:425:425)) + (PORT datac (323:323:323) (401:401:401)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tx\~output) + (DELAY + (ABSOLUTE + (PORT i (758:758:758) (794:794:794)) + (IOPATH i o (3336:3336:3336) (3399:3399:3399)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (806:806:806) (852:852:852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sys_clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (200:200:200) (189:189:189)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (482:482:482)) + (PORT datab (342:342:342) (423:423:423)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (484:484:484)) + (PORT datab (360:360:360) (449:449:449)) + (PORT datac (448:448:448) (419:419:419)) + (PORT datad (267:267:267) (303:303:303)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (424:424:424)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (PORT datac (303:303:303) (388:388:388)) + (PORT datad (303:303:303) (379:379:379)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datad (323:323:323) (410:410:410)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (484:484:484)) + (PORT datab (308:308:308) (347:347:347)) + (PORT datad (441:441:441) (417:417:417)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (485:485:485)) + (PORT datab (366:366:366) (456:456:456)) + (PORT datad (261:261:261) (295:295:295)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (265:265:265) (290:290:290)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_flag) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (866:866:866) (834:834:834)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_flag) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (535:535:535) (562:562:562)) + (PORT datad (475:475:475) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5805:5805:5805) (5615:5615:5615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (629:629:629)) + (PORT datab (339:339:339) (421:421:421)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (344:344:344) (427:427:427)) + (PORT datac (302:302:302) (387:387:387)) + (PORT datad (302:302:302) (379:379:379)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (604:604:604)) + (PORT datab (344:344:344) (427:427:427)) + (PORT datac (538:538:538) (561:561:561)) + (PORT datad (241:241:241) (260:260:260)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (449:449:449)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT datab (635:635:635) (646:646:646)) + (PORT datad (575:575:575) (598:598:598)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (613:613:613)) + (PORT datab (578:578:578) (602:602:602)) + (PORT datac (526:526:526) (560:560:560)) + (PORT datad (560:560:560) (584:584:584)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (633:633:633)) + (PORT datab (308:308:308) (333:333:333)) + (PORT datac (450:450:450) (425:425:425)) + (PORT datad (454:454:454) (432:432:432)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (421:421:421)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (726:726:726)) + (PORT datab (636:636:636) (648:648:648)) + (PORT datac (524:524:524) (497:497:497)) + (PORT datad (576:576:576) (598:598:598)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5805:5805:5805) (5615:5615:5615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT datac (321:321:321) (399:399:399)) + (PORT datad (329:329:329) (402:402:402)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (756:756:756) (694:694:694)) + (PORT datab (322:322:322) (359:359:359)) + (PORT datad (517:517:517) (486:486:486)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (315:315:315)) + (PORT datab (308:308:308) (332:332:332)) + (PORT datad (474:474:474) (447:447:447)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5805:5805:5805) (5615:5615:5615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (446:446:446)) + (PORT datad (330:330:330) (403:403:403)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (528:528:528)) + (PORT datab (425:425:425) (533:533:533)) + (PORT datac (346:346:346) (445:445:445)) + (PORT datad (485:485:485) (457:457:457)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (643:643:643)) + (PORT datab (320:320:320) (356:356:356)) + (PORT datad (836:836:836) (817:817:817)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rx\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (796:796:796) (842:842:842)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg1\~0) + (DELAY + (ABSOLUTE + (PORT datad (3626:3626:3626) (3787:3787:3787)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5805:5805:5805) (5615:5615:5615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5805:5805:5805) (5615:5615:5615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (307:307:307) (384:384:384)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg3) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5805:5805:5805) (5615:5615:5615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (819:819:819) (787:787:787)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (483:483:483)) + (PORT datab (306:306:306) (344:344:344)) + (PORT datad (318:318:318) (405:405:405)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (1271:1271:1271) (1242:1242:1242)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (663:663:663)) + (PORT datab (320:320:320) (357:357:357)) + (PORT datad (520:520:520) (490:490:490)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (492:492:492)) + (PORT datab (423:423:423) (530:530:530)) + (PORT datad (367:367:367) (473:473:473)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~5) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (448:448:448)) + (PORT datab (278:278:278) (304:304:304)) + (PORT datac (549:549:549) (592:592:592)) + (PORT datad (538:538:538) (558:558:558)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (325:325:325) (396:396:396)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT asdata (1261:1261:1261) (1233:1233:1233)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (812:812:812) (791:791:791)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (1280:1280:1280) (1251:1251:1251)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT asdata (1244:1244:1244) (1213:1213:1213)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (809:809:809) (792:792:792)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT asdata (1240:1240:1240) (1212:1212:1212)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (1606:1606:1606) (1505:1505:1505)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (532:532:532)) + (PORT datab (336:336:336) (413:413:413)) + (PORT datad (389:389:389) (495:495:495)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (529:529:529)) + (PORT datab (335:335:335) (411:411:411)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (323:323:323) (402:402:402)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (511:511:511) (537:537:537)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (1299:1299:1299) (1269:1269:1269)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (323:323:323) (401:401:401)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (1290:1290:1290) (1262:1262:1262)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~3) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (420:420:420)) + (PORT datab (431:431:431) (540:540:540)) + (PORT datad (374:374:374) (481:481:481)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~4) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (531:531:531)) + (PORT datab (429:429:429) (537:537:537)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~6) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (641:641:641)) + (PORT datab (580:580:580) (608:608:608)) + (PORT datac (245:245:245) (276:276:276)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~7) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (493:493:493)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (245:245:245) (277:277:277)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|tx) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_min_1200mv_0c_fast.vo b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_min_1200mv_0c_fast.vo new file mode 100644 index 0000000..c7cf150 --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_min_1200mv_0c_fast.vo @@ -0,0 +1,2836 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 03:03:50" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module rs232 ( + sys_clk, + sys_rst_n, + rx, + tx); +input sys_clk; +input sys_rst_n; +input rx; +output tx; + +// Design Ports Information +// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("rs232_min_1200mv_0c_v_fast.sdo"); +// synopsys translate_on + +wire \uart_tx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|baud_cnt[0]~13_combout ; +wire \uart_rx_inst|baud_cnt[0]~14 ; +wire \uart_rx_inst|baud_cnt[1]~15_combout ; +wire \uart_rx_inst|baud_cnt[1]~16 ; +wire \uart_rx_inst|baud_cnt[2]~17_combout ; +wire \uart_rx_inst|baud_cnt[2]~18 ; +wire \uart_rx_inst|baud_cnt[3]~19_combout ; +wire \uart_rx_inst|baud_cnt[3]~20 ; +wire \uart_rx_inst|baud_cnt[4]~21_combout ; +wire \uart_rx_inst|baud_cnt[4]~22 ; +wire \uart_rx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|baud_cnt[5]~24 ; +wire \uart_rx_inst|baud_cnt[6]~25_combout ; +wire \uart_rx_inst|baud_cnt[6]~26 ; +wire \uart_rx_inst|baud_cnt[7]~27_combout ; +wire \uart_rx_inst|baud_cnt[7]~28 ; +wire \uart_rx_inst|baud_cnt[8]~29_combout ; +wire \uart_rx_inst|baud_cnt[8]~30 ; +wire \uart_rx_inst|baud_cnt[9]~31_combout ; +wire \uart_rx_inst|baud_cnt[9]~32 ; +wire \uart_rx_inst|baud_cnt[10]~33_combout ; +wire \uart_rx_inst|baud_cnt[10]~34 ; +wire \uart_rx_inst|baud_cnt[11]~35_combout ; +wire \uart_rx_inst|baud_cnt[11]~36 ; +wire \uart_rx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal2~0_combout ; +wire \uart_tx_inst|Add1~0_combout ; +wire \uart_tx_inst|Add1~1_combout ; +wire \uart_rx_inst|bit_flag~q ; +wire \uart_rx_inst|Equal1~0_combout ; +wire \uart_rx_inst|Equal2~0_combout ; +wire \uart_rx_inst|Equal2~1_combout ; +wire \uart_rx_inst|Equal2~2_combout ; +wire \uart_rx_inst|work_en~q ; +wire \uart_rx_inst|Equal1~1_combout ; +wire \uart_rx_inst|Equal1~2_combout ; +wire \uart_rx_inst|Equal1~3_combout ; +wire \uart_rx_inst|always5~0_combout ; +wire \uart_rx_inst|start_nedge~q ; +wire \uart_rx_inst|work_en~0_combout ; +wire \uart_rx_inst|always3~0_combout ; +wire \tx~output_o ; +wire \sys_clk~input_o ; +wire \sys_clk~inputclkctrl_outclk ; +wire \uart_rx_inst|Add1~0_combout ; +wire \uart_rx_inst|bit_cnt~1_combout ; +wire \sys_rst_n~input_o ; +wire \uart_rx_inst|Add1~1 ; +wire \uart_rx_inst|Add1~2_combout ; +wire \uart_rx_inst|Add1~3 ; +wire \uart_rx_inst|Add1~4_combout ; +wire \uart_rx_inst|always4~0_combout ; +wire \uart_rx_inst|Add1~5 ; +wire \uart_rx_inst|Add1~6_combout ; +wire \uart_rx_inst|bit_cnt~0_combout ; +wire \uart_rx_inst|always4~1_combout ; +wire \uart_rx_inst|rx_flag~feeder_combout ; +wire \uart_rx_inst|rx_flag~q ; +wire \uart_rx_inst|po_flag~feeder_combout ; +wire \uart_rx_inst|po_flag~q ; +wire \uart_tx_inst|work_en~0_combout ; +wire \uart_tx_inst|work_en~q ; +wire \uart_tx_inst|baud_cnt[0]~13_combout ; +wire \uart_tx_inst|baud_cnt[10]~34 ; +wire \uart_tx_inst|baud_cnt[11]~35_combout ; +wire \uart_tx_inst|Equal1~0_combout ; +wire \uart_tx_inst|Equal1~1_combout ; +wire \uart_tx_inst|baud_cnt[11]~36 ; +wire \uart_tx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal1~3_combout ; +wire \uart_tx_inst|baud_cnt[2]~17_combout ; +wire \uart_tx_inst|baud_cnt[4]~21_combout ; +wire \uart_tx_inst|Equal1~2_combout ; +wire \uart_tx_inst|always1~0_combout ; +wire \uart_tx_inst|baud_cnt[0]~14 ; +wire \uart_tx_inst|baud_cnt[1]~15_combout ; +wire \uart_tx_inst|baud_cnt[1]~16 ; +wire \uart_tx_inst|baud_cnt[2]~18 ; +wire \uart_tx_inst|baud_cnt[3]~19_combout ; +wire \uart_tx_inst|baud_cnt[3]~20 ; +wire \uart_tx_inst|baud_cnt[4]~22 ; +wire \uart_tx_inst|baud_cnt[5]~24 ; +wire \uart_tx_inst|baud_cnt[6]~25_combout ; +wire \uart_tx_inst|baud_cnt[6]~26 ; +wire \uart_tx_inst|baud_cnt[7]~27_combout ; +wire \uart_tx_inst|baud_cnt[7]~28 ; +wire \uart_tx_inst|baud_cnt[8]~29_combout ; +wire \uart_tx_inst|baud_cnt[8]~30 ; +wire \uart_tx_inst|baud_cnt[9]~31_combout ; +wire \uart_tx_inst|baud_cnt[9]~32 ; +wire \uart_tx_inst|baud_cnt[10]~33_combout ; +wire \uart_tx_inst|Equal2~1_combout ; +wire \uart_tx_inst|bit_flag~q ; +wire \uart_tx_inst|always3~0_combout ; +wire \uart_tx_inst|bit_cnt[2]~2_combout ; +wire \uart_tx_inst|bit_cnt[3]~4_combout ; +wire \uart_tx_inst|always0~0_combout ; +wire \uart_tx_inst|always0~1_combout ; +wire \uart_tx_inst|bit_cnt[0]~5_combout ; +wire \rx~input_o ; +wire \uart_rx_inst|rx_reg1~0_combout ; +wire \uart_rx_inst|rx_reg1~q ; +wire \uart_rx_inst|rx_reg2~feeder_combout ; +wire \uart_rx_inst|rx_reg2~q ; +wire \uart_rx_inst|rx_reg3~feeder_combout ; +wire \uart_rx_inst|rx_reg3~q ; +wire \uart_rx_inst|rx_data[7]~0_combout ; +wire \uart_rx_inst|always8~0_combout ; +wire \uart_tx_inst|bit_cnt[1]~3_combout ; +wire \uart_tx_inst|tx~2_combout ; +wire \uart_tx_inst|tx~5_combout ; +wire \uart_rx_inst|rx_data[6]~feeder_combout ; +wire \uart_rx_inst|po_data[5]~feeder_combout ; +wire \uart_rx_inst|po_data[4]~feeder_combout ; +wire \uart_tx_inst|Mux0~0_combout ; +wire \uart_tx_inst|Mux0~1_combout ; +wire \uart_rx_inst|rx_data[2]~feeder_combout ; +wire \uart_rx_inst|rx_data[1]~feeder_combout ; +wire \uart_rx_inst|rx_data[0]~feeder_combout ; +wire \uart_tx_inst|tx~3_combout ; +wire \uart_tx_inst|tx~4_combout ; +wire \uart_tx_inst|tx~6_combout ; +wire \uart_tx_inst|tx~7_combout ; +wire \uart_tx_inst|tx~q ; +wire [7:0] \uart_rx_inst|rx_data ; +wire [7:0] \uart_rx_inst|po_data ; +wire [3:0] \uart_rx_inst|bit_cnt ; +wire [12:0] \uart_rx_inst|baud_cnt ; +wire [3:0] \uart_tx_inst|bit_cnt ; +wire [12:0] \uart_tx_inst|baud_cnt ; + + +// Location: FF_X6_Y9_N13 +dffeas \uart_tx_inst|baud_cnt[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N12 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[4]~22 ), + .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_tx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y9_N5 +dffeas \uart_rx_inst|baud_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N7 +dffeas \uart_rx_inst|baud_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N19 +dffeas \uart_rx_inst|baud_cnt[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N21 +dffeas \uart_rx_inst|baud_cnt[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N11 +dffeas \uart_rx_inst|baud_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N15 +dffeas \uart_rx_inst|baud_cnt[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N9 +dffeas \uart_rx_inst|baud_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N13 +dffeas \uart_rx_inst|baud_cnt[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N23 +dffeas \uart_rx_inst|baud_cnt[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N27 +dffeas \uart_rx_inst|baud_cnt[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N17 +dffeas \uart_rx_inst|baud_cnt[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N25 +dffeas \uart_rx_inst|baud_cnt[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y9_N29 +dffeas \uart_rx_inst|baud_cnt[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N4 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) +// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_rx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N6 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) + + .dataa(\uart_rx_inst|baud_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[0]~14 ), + .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_rx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N8 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) +// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[1]~16 ), + .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_rx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N10 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) + + .dataa(\uart_rx_inst|baud_cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[2]~18 ), + .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_rx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N12 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) +// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[3]~20 ), + .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_rx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N14 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[4]~22 ), + .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_rx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N16 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) +// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[5]~24 ), + .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_rx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N18 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[6]~26 ), + .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_rx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N20 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) +// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[7]~28 ), + .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_rx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N22 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[8]~30 ), + .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_rx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N24 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) +// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[9]~32 ), + .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_rx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N26 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) + + .dataa(\uart_rx_inst|baud_cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[10]~34 ), + .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_rx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N28 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt[11]~36 $ (!\uart_rx_inst|baud_cnt [12]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|baud_cnt [12]), + .cin(\uart_rx_inst|baud_cnt[11]~36 ), + .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; +defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X4_Y9_N23 +dffeas \uart_rx_inst|po_data[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [2]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( +// Equation(s): +// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [6]))) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(\uart_tx_inst|baud_cnt [2]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [6]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N22 +cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( +// Equation(s): +// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(gnd), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h66AA; +defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N22 +cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( +// Equation(s): +// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [0] & (\uart_tx_inst|bit_cnt [1] & \uart_tx_inst|bit_cnt [2])))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h7F80; +defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N11 +dffeas \uart_rx_inst|bit_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|Equal2~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( +// Equation(s): +// \uart_rx_inst|Equal1~0_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [0] & !\uart_rx_inst|baud_cnt [8]))) + + .dataa(\uart_rx_inst|baud_cnt [1]), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(\uart_rx_inst|baud_cnt [0]), + .datad(\uart_rx_inst|baud_cnt [8]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N4 +cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( +// Equation(s): +// \uart_rx_inst|Equal2~0_combout = (\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [4]))) + + .dataa(\uart_rx_inst|baud_cnt [5]), + .datab(\uart_rx_inst|baud_cnt [3]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0008; +defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N6 +cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( +// Equation(s): +// \uart_rx_inst|Equal2~1_combout = (\uart_rx_inst|baud_cnt [9] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [10]))) + + .dataa(\uart_rx_inst|baud_cnt [9]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [6]), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0008; +defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N10 +cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( +// Equation(s): +// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal2~1_combout & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal2~0_combout ))) + + .dataa(\uart_rx_inst|Equal2~1_combout ), + .datab(\uart_rx_inst|baud_cnt [12]), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000; +defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X9_Y9_N17 +dffeas \uart_rx_inst|work_en ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_rx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N30 +cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( +// Equation(s): +// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N2 +cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( +// Equation(s): +// \uart_rx_inst|Equal1~2_combout = (!\uart_rx_inst|baud_cnt [11] & \uart_rx_inst|baud_cnt [10]) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|baud_cnt [11]), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0F00; +defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N8 +cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( +// Equation(s): +// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt [9] & \uart_rx_inst|Equal1~2_combout ))) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(\uart_rx_inst|baud_cnt [9]), + .datad(\uart_rx_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h0800; +defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y9_N2 +cycloneive_lcell_comb \uart_rx_inst|always5~0 ( +// Equation(s): +// \uart_rx_inst|always5~0_combout = ((\uart_rx_inst|Equal1~0_combout & (\uart_rx_inst|Equal1~1_combout & \uart_rx_inst|Equal1~3_combout ))) # (!\uart_rx_inst|work_en~q ) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|Equal1~0_combout ), + .datac(\uart_rx_inst|Equal1~1_combout ), + .datad(\uart_rx_inst|Equal1~3_combout ), + .cin(gnd), + .combout(\uart_rx_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always5~0 .lut_mask = 16'hD555; +defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N13 +dffeas \uart_rx_inst|start_nedge ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|always3~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|start_nedge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; +defparam \uart_rx_inst|start_nedge .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y9_N16 +cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( +// Equation(s): +// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) + + .dataa(gnd), + .datab(\uart_rx_inst|start_nedge~q ), + .datac(\uart_rx_inst|work_en~q ), + .datad(\uart_rx_inst|always4~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hCCFC; +defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N12 +cycloneive_lcell_comb \uart_rx_inst|always3~0 ( +// Equation(s): +// \uart_rx_inst|always3~0_combout = (\uart_rx_inst|rx_reg2~q & !\uart_rx_inst|rx_reg3~q ) + + .dataa(gnd), + .datab(\uart_rx_inst|rx_reg2~q ), + .datac(\uart_rx_inst|rx_reg3~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always3~0 .lut_mask = 16'h0C0C; +defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y9_N16 +cycloneive_io_obuf \tx~output ( + .i(!\uart_tx_inst|tx~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\tx~output_o ), + .obar()); +// synopsys translate_off +defparam \tx~output .bus_hold = "false"; +defparam \tx~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \sys_clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sys_clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sys_clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \sys_clk~inputclkctrl .clock_type = "global clock"; +defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N16 +cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( +// Equation(s): +// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] & VCC)) +// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [0])) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|Add1~0_combout ), + .cout(\uart_rx_inst|Add1~1 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; +defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N4 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~1_combout = \uart_rx_inst|Add1~0_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(\uart_rx_inst|Add1~0_combout ), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h78F0; +defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X8_Y9_N5 +dffeas \uart_rx_inst|bit_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N18 +cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( +// Equation(s): +// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) +// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~1 ), + .combout(\uart_rx_inst|Add1~2_combout ), + .cout(\uart_rx_inst|Add1~3 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X8_Y9_N19 +dffeas \uart_rx_inst|bit_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|Add1~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N20 +cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( +// Equation(s): +// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) +// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~3 ), + .combout(\uart_rx_inst|Add1~4_combout ), + .cout(\uart_rx_inst|Add1~5 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X8_Y9_N21 +dffeas \uart_rx_inst|bit_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|Add1~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N24 +cycloneive_lcell_comb \uart_rx_inst|always4~0 ( +// Equation(s): +// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [2])) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [1]), + .datac(\uart_rx_inst|bit_cnt [0]), + .datad(\uart_rx_inst|bit_cnt [2]), + .cin(gnd), + .combout(\uart_rx_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0003; +defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N22 +cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( +// Equation(s): +// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|Add1~5 $ (\uart_rx_inst|bit_cnt [3]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(\uart_rx_inst|Add1~5 ), + .combout(\uart_rx_inst|Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h0FF0; +defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~0_combout = \uart_rx_inst|Add1~6_combout $ (((\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout & \uart_rx_inst|bit_cnt [3])))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(\uart_rx_inst|Add1~6_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h7F80; +defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N1 +dffeas \uart_rx_inst|bit_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N30 +cycloneive_lcell_comb \uart_rx_inst|always4~1 ( +// Equation(s): +// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [3] & \uart_rx_inst|always4~0_combout )) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(gnd), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~1 .lut_mask = 16'h8800; +defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N14 +cycloneive_lcell_comb \uart_rx_inst|rx_flag~feeder ( +// Equation(s): +// \uart_rx_inst|rx_flag~feeder_combout = \uart_rx_inst|always4~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|always4~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag~feeder .lut_mask = 16'hF0F0; +defparam \uart_rx_inst|rx_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N15 +dffeas \uart_rx_inst|rx_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_flag~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N30 +cycloneive_lcell_comb \uart_rx_inst|po_flag~feeder ( +// Equation(s): +// \uart_rx_inst|po_flag~feeder_combout = \uart_rx_inst|rx_flag~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_flag~q ), + .cin(gnd), + .combout(\uart_rx_inst|po_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_flag~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N31 +dffeas \uart_rx_inst|po_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|po_flag~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N14 +cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( +// Equation(s): +// \uart_tx_inst|work_en~0_combout = (\uart_rx_inst|po_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) + + .dataa(gnd), + .datab(\uart_rx_inst|po_flag~q ), + .datac(\uart_tx_inst|work_en~q ), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hCCFC; +defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N15 +dffeas \uart_tx_inst|work_en ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_tx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N2 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) +// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_tx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N22 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) +// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[9]~32 ), + .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_tx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N24 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[10]~34 ), + .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_tx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N25 +dffeas \uart_tx_inst|baud_cnt[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N28 +cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( +// Equation(s): +// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [5] & (\uart_tx_inst|baud_cnt [0] & (!\uart_tx_inst|baud_cnt [3] & !\uart_tx_inst|baud_cnt [7]))) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(\uart_tx_inst|baud_cnt [3]), + .datad(\uart_tx_inst|baud_cnt [7]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0004; +defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N0 +cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( +// Equation(s): +// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt [11] & \uart_tx_inst|Equal1~0_combout ))) + + .dataa(\uart_tx_inst|baud_cnt [9]), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(\uart_tx_inst|baud_cnt [11]), + .datad(\uart_tx_inst|Equal1~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0100; +defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N26 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_tx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_tx_inst|baud_cnt[11]~36 ), + .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N27 +dffeas \uart_tx_inst|baud_cnt[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N16 +cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( +// Equation(s): +// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [12] & \uart_tx_inst|baud_cnt [10]) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(gnd), + .datad(\uart_tx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hCC00; +defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N6 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) +// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[1]~16 ), + .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_tx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N7 +dffeas \uart_tx_inst|baud_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N10 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) +// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[3]~20 ), + .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_tx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N11 +dffeas \uart_tx_inst|baud_cnt[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X7_Y9_N6 +cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( +// Equation(s): +// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4]))) + + .dataa(\uart_tx_inst|baud_cnt [6]), + .datab(\uart_tx_inst|baud_cnt [2]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; +defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N30 +cycloneive_lcell_comb \uart_tx_inst|always1~0 ( +// Equation(s): +// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~1_combout & (\uart_tx_inst|Equal1~3_combout & \uart_tx_inst|Equal1~2_combout ))) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|Equal1~1_combout ), + .datac(\uart_tx_inst|Equal1~3_combout ), + .datad(\uart_tx_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555; +defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X6_Y9_N3 +dffeas \uart_tx_inst|baud_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[0]~14 ), + .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_tx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N5 +dffeas \uart_tx_inst|baud_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N8 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[2]~18 ), + .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_tx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N9 +dffeas \uart_tx_inst|baud_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N14 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) +// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[5]~24 ), + .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_tx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N15 +dffeas \uart_tx_inst|baud_cnt[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N16 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[6]~26 ), + .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_tx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N17 +dffeas \uart_tx_inst|baud_cnt[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N18 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) +// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[7]~28 ), + .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_tx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N19 +dffeas \uart_tx_inst|baud_cnt[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N20 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[8]~30 ), + .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_tx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X6_Y9_N21 +dffeas \uart_tx_inst|baud_cnt[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X6_Y9_N23 +dffeas \uart_tx_inst|baud_cnt[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N20 +cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( +// Equation(s): +// \uart_tx_inst|Equal2~1_combout = (\uart_tx_inst|Equal2~0_combout & (!\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|Equal1~1_combout & !\uart_tx_inst|baud_cnt [12]))) + + .dataa(\uart_tx_inst|Equal2~0_combout ), + .datab(\uart_tx_inst|baud_cnt [10]), + .datac(\uart_tx_inst|Equal1~1_combout ), + .datad(\uart_tx_inst|baud_cnt [12]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h0020; +defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N21 +dffeas \uart_tx_inst|bit_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|Equal2~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N24 +cycloneive_lcell_comb \uart_tx_inst|always3~0 ( +// Equation(s): +// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_tx_inst|work_en~q ), + .datad(\uart_tx_inst|bit_flag~q ), + .cin(gnd), + .combout(\uart_tx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always3~0 .lut_mask = 16'h0FFF; +defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N26 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~2 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[2]~2_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~0_combout )))) + + .dataa(\uart_tx_inst|Add1~0_combout ), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always3~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[2]~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2]~2 .lut_mask = 16'h3022; +defparam \uart_tx_inst|bit_cnt[2]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N27 +dffeas \uart_tx_inst|bit_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[2]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N2 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~4 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[3]~4_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [3]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) + + .dataa(\uart_tx_inst|Add1~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3]~4 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N3 +dffeas \uart_tx_inst|bit_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[3]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|always0~0 ( +// Equation(s): +// \uart_tx_inst|always0~0_combout = (\uart_tx_inst|bit_cnt [3] & \uart_tx_inst|bit_flag~q ) + + .dataa(gnd), + .datab(\uart_tx_inst|bit_cnt [3]), + .datac(gnd), + .datad(\uart_tx_inst|bit_flag~q ), + .cin(gnd), + .combout(\uart_tx_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~0 .lut_mask = 16'hCC00; +defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N8 +cycloneive_lcell_comb \uart_tx_inst|always0~1 ( +// Equation(s): +// \uart_tx_inst|always0~1_combout = (!\uart_tx_inst|bit_cnt [1] & (\uart_tx_inst|bit_cnt [0] & (!\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|always0~0_combout ))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~1 .lut_mask = 16'h0400; +defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N2 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|bit_flag~q & \uart_tx_inst|work_en~q ))))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h1230; +defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N3 +dffeas \uart_tx_inst|bit_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[0]~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \rx~input ( + .i(rx), + .ibar(gnd), + .o(\rx~input_o )); +// synopsys translate_off +defparam \rx~input .bus_hold = "false"; +defparam \rx~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N18 +cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( +// Equation(s): +// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rx~input_o ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N19 +dffeas \uart_rx_inst|rx_reg1 ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_reg1~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg1~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N1 +dffeas \uart_rx_inst|rx_reg2 ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_reg2~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X5_Y9_N26 +cycloneive_lcell_comb \uart_rx_inst|rx_reg3~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg3~feeder_combout = \uart_rx_inst|rx_reg2~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg2~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X5_Y9_N27 +dffeas \uart_rx_inst|rx_reg3 ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_reg3~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N28 +cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( +// Equation(s): +// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg3~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N6 +cycloneive_lcell_comb \uart_rx_inst|always8~0 ( +// Equation(s): +// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|always8~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8822; +defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N29 +dffeas \uart_rx_inst|rx_data[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[7]~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N5 +dffeas \uart_rx_inst|po_data[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [7]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N6 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~3 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[1]~3_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [1]), + .datad(\uart_tx_inst|always3~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1]~3 .lut_mask = 16'h3012; +defparam \uart_tx_inst|bit_cnt[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N7 +dffeas \uart_tx_inst|bit_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[1]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N4 +cycloneive_lcell_comb \uart_tx_inst|tx~2 ( +// Equation(s): +// \uart_tx_inst|tx~2_combout = (\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|bit_cnt [0]) # ((\uart_rx_inst|po_data [7]) # (\uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_rx_inst|po_data [7]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~2 .lut_mask = 16'hFFFE; +defparam \uart_tx_inst|tx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N16 +cycloneive_lcell_comb \uart_tx_inst|tx~5 ( +// Equation(s): +// \uart_tx_inst|tx~5_combout = (\uart_tx_inst|bit_flag~q & (((\uart_tx_inst|tx~2_combout & \uart_tx_inst|bit_cnt [3])))) # (!\uart_tx_inst|bit_flag~q & (!\uart_tx_inst|tx~q )) + + .dataa(\uart_tx_inst|tx~q ), + .datab(\uart_tx_inst|tx~2_combout ), + .datac(\uart_tx_inst|bit_flag~q ), + .datad(\uart_tx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_tx_inst|tx~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~5 .lut_mask = 16'hC505; +defparam \uart_tx_inst|tx~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[6]~feeder_combout = \uart_rx_inst|rx_data [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [7]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N3 +dffeas \uart_rx_inst|rx_data[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X8_Y9_N7 +dffeas \uart_rx_inst|rx_data[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [6]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N20 +cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N21 +dffeas \uart_rx_inst|po_data[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|po_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N15 +dffeas \uart_rx_inst|po_data[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [6]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X8_Y9_N31 +dffeas \uart_rx_inst|rx_data[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [5]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N0 +cycloneive_lcell_comb \uart_rx_inst|po_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[4]~feeder_combout = \uart_rx_inst|rx_data [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [4]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N1 +dffeas \uart_rx_inst|po_data[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|po_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X8_Y9_N23 +dffeas \uart_rx_inst|rx_data[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [4]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N25 +dffeas \uart_rx_inst|po_data[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [3]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N24 +cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( +// Equation(s): +// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & (\uart_rx_inst|po_data [4])) # (!\uart_tx_inst|bit_cnt [0] & ((\uart_rx_inst|po_data [3]))))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_rx_inst|po_data [4]), + .datac(\uart_rx_inst|po_data [3]), + .datad(\uart_tx_inst|bit_cnt [0]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hEE50; +defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N14 +cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( +// Equation(s): +// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|Mux0~0_combout & ((\uart_rx_inst|po_data [6]))) # (!\uart_tx_inst|Mux0~0_combout & (\uart_rx_inst|po_data [5])))) # (!\uart_tx_inst|bit_cnt [1] & +// (((\uart_tx_inst|Mux0~0_combout )))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_rx_inst|po_data [5]), + .datac(\uart_rx_inst|po_data [6]), + .datad(\uart_tx_inst|Mux0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF588; +defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N8 +cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|rx_data [3]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hF0F0; +defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N9 +dffeas \uart_rx_inst|rx_data[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N26 +cycloneive_lcell_comb \uart_rx_inst|rx_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[1]~feeder_combout = \uart_rx_inst|rx_data [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [2]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N27 +dffeas \uart_rx_inst|rx_data[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N19 +dffeas \uart_rx_inst|po_data[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [1]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X8_Y9_N12 +cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|rx_data [1]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hF0F0; +defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X8_Y9_N13 +dffeas \uart_rx_inst|rx_data[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_rx_inst|rx_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X4_Y9_N29 +dffeas \uart_rx_inst|po_data[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [0]), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N28 +cycloneive_lcell_comb \uart_tx_inst|tx~3 ( +// Equation(s): +// \uart_tx_inst|tx~3_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\uart_rx_inst|po_data [2])) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_rx_inst|po_data [0]))))) + + .dataa(\uart_rx_inst|po_data [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_rx_inst|po_data [0]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~3 .lut_mask = 16'h88C0; +defparam \uart_tx_inst|tx~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N18 +cycloneive_lcell_comb \uart_tx_inst|tx~4 ( +// Equation(s): +// \uart_tx_inst|tx~4_combout = (\uart_tx_inst|tx~3_combout ) # ((\uart_tx_inst|bit_cnt [1] & (!\uart_tx_inst|bit_cnt [0] & \uart_rx_inst|po_data [1]))) + + .dataa(\uart_tx_inst|bit_cnt [1]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_rx_inst|po_data [1]), + .datad(\uart_tx_inst|tx~3_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~4 .lut_mask = 16'hFF20; +defparam \uart_tx_inst|tx~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N10 +cycloneive_lcell_comb \uart_tx_inst|tx~6 ( +// Equation(s): +// \uart_tx_inst|tx~6_combout = (\uart_tx_inst|bit_flag~q & ((\uart_tx_inst|bit_cnt [2]) # ((\uart_tx_inst|tx~4_combout )))) # (!\uart_tx_inst|bit_flag~q & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout ))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\uart_tx_inst|Mux0~1_combout ), + .datad(\uart_tx_inst|tx~4_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~6 .lut_mask = 16'hAE8C; +defparam \uart_tx_inst|tx~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X4_Y9_N12 +cycloneive_lcell_comb \uart_tx_inst|tx~7 ( +// Equation(s): +// \uart_tx_inst|tx~7_combout = (\uart_tx_inst|tx~5_combout & (\uart_tx_inst|bit_cnt [2] & (!\uart_tx_inst|Mux0~1_combout & !\uart_tx_inst|tx~6_combout ))) # (!\uart_tx_inst|tx~5_combout & (((\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|Mux0~1_combout )) # +// (!\uart_tx_inst|tx~6_combout ))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|tx~5_combout ), + .datac(\uart_tx_inst|Mux0~1_combout ), + .datad(\uart_tx_inst|tx~6_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~7_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~7 .lut_mask = 16'h023B; +defparam \uart_tx_inst|tx~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X4_Y9_N13 +dffeas \uart_tx_inst|tx ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|tx~7_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|tx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|tx .is_wysiwyg = "true"; +defparam \uart_tx_inst|tx .power_up = "low"; +// synopsys translate_on + +assign tx = \tx~output_o ; + +endmodule diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_min_1200mv_0c_v_fast.sdo b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_min_1200mv_0c_v_fast.sdo new file mode 100644 index 0000000..ac7de7e --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_min_1200mv_0c_v_fast.sdo @@ -0,0 +1,2275 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Fast Corner delays for the design using part EP4CE15F23C8, +// with speed grade M, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "rs232") + (DATE "06/02/2023 03:03:50") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2871:2871:2871) (2569:2569:2569)) + (PORT sclr (321:321:321) (376:376:376)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2997:2997:2997) (2689:2689:2689)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2997:2997:2997) (2689:2689:2689)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2997:2997:2997) (2689:2689:2689)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2997:2997:2997) (2689:2689:2689)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2997:2997:2997) (2689:2689:2689)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2997:2997:2997) (2689:2689:2689)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2997:2997:2997) (2689:2689:2689)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2997:2997:2997) (2689:2689:2689)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2997:2997:2997) (2689:2689:2689)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2997:2997:2997) (2689:2689:2689)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2997:2997:2997) (2689:2689:2689)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2997:2997:2997) (2689:2689:2689)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2997:2997:2997) (2689:2689:2689)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (267:267:267)) + (PORT datab (135:135:135) (185:185:185)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (196:196:196)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (198:198:198)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (200:200:200)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (197:197:197)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (183:183:183)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (205:205:205) (263:263:263)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (205:205:205)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (203:203:203) (248:248:248)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT asdata (489:489:489) (548:548:548)) + (PORT clrn (2734:2734:2734) (2452:2452:2452)) + (PORT ena (652:652:652) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (289:289:289)) + (PORT datab (216:216:216) (270:270:270)) + (PORT datac (200:200:200) (249:249:249)) + (PORT datad (205:205:205) (249:249:249)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (215:215:215)) + (PORT datab (183:183:183) (241:241:241)) + (PORT datad (161:161:161) (212:212:212)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (294:294:294)) + (PORT datab (213:213:213) (265:265:265)) + (PORT datac (212:212:212) (264:264:264)) + (PORT datad (136:136:136) (176:176:176)) + (IOPATH dataa combout (181:181:181) (180:180:180)) + (IOPATH datab combout (182:182:182) (181:181:181)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2876:2876:2876) (2574:2574:2574)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (190:190:190)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (124:124:124) (164:164:164)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (381:381:381)) + (PORT datab (214:214:214) (271:271:271)) + (PORT datac (213:213:213) (265:265:265)) + (PORT datad (311:311:311) (369:369:369)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (394:394:394)) + (PORT datab (338:338:338) (400:400:400)) + (PORT datac (321:321:321) (385:385:385)) + (PORT datad (217:217:217) (269:269:269)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (220:220:220)) + (PORT datab (329:329:329) (399:399:399)) + (PORT datac (285:285:285) (322:322:322)) + (PORT datad (173:173:173) (205:205:205)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2994:2994:2994) (2686:2686:2686)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (204:204:204)) + (PORT datab (149:149:149) (199:199:199)) + (PORT datac (135:135:135) (179:179:179)) + (PORT datad (136:136:136) (176:176:176)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datac (313:313:313) (366:366:366)) + (PORT datad (218:218:218) (270:270:270)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (393:393:393)) + (PORT datab (218:218:218) (277:277:277)) + (PORT datac (309:309:309) (370:370:370)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (268:268:268)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (157:157:157) (182:182:182)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|start_nedge) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2865:2865:2865) (2564:2564:2564)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (316:316:316) (377:377:377)) + (PORT datad (169:169:169) (194:194:194)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (186:186:186)) + (PORT datac (130:130:130) (172:172:172)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tx\~output) + (DELAY + (ABSOLUTE + (PORT i (344:344:344) (297:297:297)) + (IOPATH i o (1755:1755:1755) (1782:1782:1782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (358:358:358) (738:738:738)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sys_clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (97:97:97) (82:82:82)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (153:153:153) (213:213:213)) + (PORT datab (136:136:136) (187:187:187)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (153:153:153) (212:212:212)) + (PORT datab (142:142:142) (196:196:196)) + (PORT datac (162:162:162) (189:189:189)) + (PORT datad (107:107:107) (132:132:132)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2876:2876:2876) (2574:2574:2574)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2876:2876:2876) (2574:2574:2574)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2876:2876:2876) (2574:2574:2574)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (185:185:185)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datad (134:134:134) (178:178:178)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (153:153:153) (213:213:213)) + (PORT datab (122:122:122) (157:157:157)) + (PORT datad (163:163:163) (189:189:189)) + (IOPATH dataa combout (181:181:181) (180:180:180)) + (IOPATH datab combout (182:182:182) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2876:2876:2876) (2574:2574:2574)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (156:156:156) (215:215:215)) + (PORT datab (149:149:149) (204:204:204)) + (PORT datad (101:101:101) (125:125:125)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (104:104:104) (126:126:126)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_flag) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2876:2876:2876) (2574:2574:2574)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (319:319:319) (384:384:384)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_flag) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2734:2734:2734) (2452:2452:2452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (197:197:197) (253:253:253)) + (PORT datad (177:177:177) (202:202:202)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2865:2865:2865) (2564:2564:2564)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (283:283:283)) + (PORT datab (133:133:133) (183:183:183)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2871:2871:2871) (2569:2569:2569)) + (PORT sclr (321:321:321) (376:376:376)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (191:191:191)) + (PORT datab (138:138:138) (189:189:189)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (272:272:272)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datac (204:204:204) (251:251:251)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2871:2871:2871) (2569:2569:2569)) + (PORT sclr (321:321:321) (376:376:376)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT datab (234:234:234) (292:292:292)) + (PORT datad (216:216:216) (267:267:267)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2871:2871:2871) (2569:2569:2569)) + (PORT sclr (321:321:321) (376:376:376)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2871:2871:2871) (2569:2569:2569)) + (PORT sclr (321:321:321) (376:376:376)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (275:275:275)) + (PORT datab (216:216:216) (270:270:270)) + (PORT datac (201:201:201) (249:249:249)) + (PORT datad (210:210:210) (260:260:260)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (285:285:285)) + (PORT datab (120:120:120) (149:149:149)) + (PORT datac (161:161:161) (190:190:190)) + (PORT datad (166:166:166) (195:195:195)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2871:2871:2871) (2569:2569:2569)) + (PORT sclr (321:321:321) (376:376:376)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2871:2871:2871) (2569:2569:2569)) + (PORT sclr (321:321:321) (376:376:376)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2871:2871:2871) (2569:2569:2569)) + (PORT sclr (321:321:321) (376:376:376)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2871:2871:2871) (2569:2569:2569)) + (PORT sclr (321:321:321) (376:376:376)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2871:2871:2871) (2569:2569:2569)) + (PORT sclr (321:321:321) (376:376:376)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2871:2871:2871) (2569:2569:2569)) + (PORT sclr (321:321:321) (376:376:376)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2871:2871:2871) (2569:2569:2569)) + (PORT sclr (321:321:321) (376:376:376)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2871:2871:2871) (2569:2569:2569)) + (PORT sclr (321:321:321) (376:376:376)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (293:293:293) (341:341:341)) + (PORT datab (234:234:234) (292:292:292)) + (PORT datac (190:190:190) (225:225:225)) + (PORT datad (215:215:215) (266:266:266)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2865:2865:2865) (2564:2564:2564)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT datac (129:129:129) (171:171:171)) + (PORT datad (133:133:133) (171:171:171)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (320:320:320)) + (PORT datab (128:128:128) (161:161:161)) + (PORT datad (188:188:188) (219:219:219)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2734:2734:2734) (2452:2452:2452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (119:119:119) (148:148:148)) + (PORT datad (176:176:176) (201:201:201)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2865:2865:2865) (2564:2564:2564)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT datab (145:145:145) (195:195:195)) + (PORT datad (135:135:135) (174:174:174)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (171:171:171) (233:233:233)) + (PORT datab (178:178:178) (236:236:236)) + (PORT datac (146:146:146) (195:195:195)) + (PORT datad (172:172:172) (205:205:205)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (293:293:293)) + (PORT datab (125:125:125) (157:157:157)) + (PORT datad (314:314:314) (374:374:374)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2734:2734:2734) (2452:2452:2452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rx\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (348:348:348) (728:728:728)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg1\~0) + (DELAY + (ABSOLUTE + (PORT datad (1703:1703:1703) (1891:1891:1891)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg1) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2865:2865:2865) (2564:2564:2564)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg2) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2865:2865:2865) (2564:2564:2564)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (125:125:125) (165:165:165)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg3) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2865:2865:2865) (2564:2564:2564)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (306:306:306) (360:360:360)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (153:153:153) (212:212:212)) + (PORT datab (120:120:120) (156:156:156)) + (PORT datad (129:129:129) (173:173:173)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (161:161:161) (176:176:176)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2876:2876:2876) (2574:2574:2574)) + (PORT ena (406:406:406) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT asdata (482:482:482) (537:537:537)) + (PORT clrn (2734:2734:2734) (2452:2452:2452)) + (PORT ena (652:652:652) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (296:296:296)) + (PORT datab (126:126:126) (158:158:158)) + (PORT datad (191:191:191) (223:223:223)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2734:2734:2734) (2452:2452:2452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (162:162:162) (222:222:222)) + (PORT datab (176:176:176) (234:234:234)) + (PORT datad (155:155:155) (206:206:206)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~5) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (195:195:195)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (211:211:211) (266:266:266)) + (PORT datad (203:203:203) (249:249:249)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (132:132:132) (170:170:170)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2876:2876:2876) (2574:2574:2574)) + (PORT ena (406:406:406) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (876:876:876)) + (PORT asdata (469:469:469) (529:529:529)) + (PORT clrn (2876:2876:2876) (2574:2574:2574)) + (PORT ena (406:406:406) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (366:366:366)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2734:2734:2734) (2452:2452:2452)) + (PORT ena (652:652:652) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT asdata (480:480:480) (543:543:543)) + (PORT clrn (2734:2734:2734) (2452:2452:2452)) + (PORT ena (652:652:652) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (876:876:876)) + (PORT asdata (467:467:467) (521:521:521)) + (PORT clrn (2876:2876:2876) (2574:2574:2574)) + (PORT ena (406:406:406) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (308:308:308) (368:368:368)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2734:2734:2734) (2452:2452:2452)) + (PORT ena (652:652:652) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (876:876:876)) + (PORT asdata (465:465:465) (518:518:518)) + (PORT clrn (2876:2876:2876) (2574:2574:2574)) + (PORT ena (406:406:406) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT asdata (597:597:597) (660:660:660)) + (PORT clrn (2734:2734:2734) (2452:2452:2452)) + (PORT ena (652:652:652) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (239:239:239)) + (PORT datab (133:133:133) (182:182:182)) + (PORT datad (169:169:169) (218:218:218)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (173:173:173) (236:236:236)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (130:130:130) (172:172:172)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2876:2876:2876) (2574:2574:2574)) + (PORT ena (406:406:406) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (193:193:193) (240:240:240)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2876:2876:2876) (2574:2574:2574)) + (PORT ena (406:406:406) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT asdata (491:491:491) (549:549:549)) + (PORT clrn (2734:2734:2734) (2452:2452:2452)) + (PORT ena (652:652:652) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (130:130:130) (172:172:172)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2876:2876:2876) (2574:2574:2574)) + (PORT ena (406:406:406) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT asdata (483:483:483) (546:546:546)) + (PORT clrn (2734:2734:2734) (2452:2452:2452)) + (PORT ena (652:652:652) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~3) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (184:184:184) (243:243:243)) + (PORT datad (162:162:162) (213:213:213)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~4) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (237:237:237)) + (PORT datab (182:182:182) (241:241:241)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~6) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (292:292:292)) + (PORT datab (217:217:217) (276:276:276)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~7) + (DELAY + (ABSOLUTE + (PORT dataa (161:161:161) (221:221:221)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (94:94:94) (118:118:118)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|tx) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2734:2734:2734) (2452:2452:2452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_modelsim.xrf b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_modelsim.xrf new file mode 100644 index 0000000..a2e17de --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_modelsim.xrf @@ -0,0 +1,157 @@ +vendor_name = ModelSim +source_file = 1, E:/simiao/lc/A415/05_rs232/rs232/sim/tb_uart_tx.v +source_file = 1, E:/simiao/lc/A415/05_rs232/rs232/sim/tb_uart_rx.v +source_file = 1, E:/simiao/lc/A415/05_rs232/rs232/sim/tb_rs232.v +source_file = 1, E:/simiao/lc/A415/05_rs232/rs232/rtl/uart_tx.v +source_file = 1, E:/simiao/lc/A415/05_rs232/rs232/rtl/uart_rx.v +source_file = 1, E:/simiao/lc/A415/05_rs232/rs232/rtl/rs232.v +source_file = 1, E:/simiao/lc/A415/05_rs232/rs232/quartus_prj/db/rs232.cbx.xml +design_name = rs232 +instance = comp, \uart_tx_inst|baud_cnt[5] , uart_tx_inst|baud_cnt[5], rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[5]~23 , uart_tx_inst|baud_cnt[5]~23, rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[0] , uart_rx_inst|baud_cnt[0], rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[1] , uart_rx_inst|baud_cnt[1], rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[7] , uart_rx_inst|baud_cnt[7], rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[8] , uart_rx_inst|baud_cnt[8], rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[3] , uart_rx_inst|baud_cnt[3], rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[5] , uart_rx_inst|baud_cnt[5], rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[2] , uart_rx_inst|baud_cnt[2], rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[4] , uart_rx_inst|baud_cnt[4], rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[9] , uart_rx_inst|baud_cnt[9], rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[11] , uart_rx_inst|baud_cnt[11], rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[6] , uart_rx_inst|baud_cnt[6], rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[10] , uart_rx_inst|baud_cnt[10], rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[12] , uart_rx_inst|baud_cnt[12], rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[0]~13 , uart_rx_inst|baud_cnt[0]~13, rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[1]~15 , uart_rx_inst|baud_cnt[1]~15, rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[2]~17 , uart_rx_inst|baud_cnt[2]~17, rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[3]~19 , uart_rx_inst|baud_cnt[3]~19, rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[4]~21 , uart_rx_inst|baud_cnt[4]~21, rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[5]~23 , uart_rx_inst|baud_cnt[5]~23, rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[6]~25 , uart_rx_inst|baud_cnt[6]~25, rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[7]~27 , uart_rx_inst|baud_cnt[7]~27, rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[8]~29 , uart_rx_inst|baud_cnt[8]~29, rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[9]~31 , uart_rx_inst|baud_cnt[9]~31, rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[10]~33 , uart_rx_inst|baud_cnt[10]~33, rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[11]~35 , uart_rx_inst|baud_cnt[11]~35, rs232, 1 +instance = comp, \uart_rx_inst|baud_cnt[12]~37 , uart_rx_inst|baud_cnt[12]~37, rs232, 1 +instance = comp, \uart_rx_inst|po_data[2] , uart_rx_inst|po_data[2], rs232, 1 +instance = comp, \uart_tx_inst|Equal2~0 , uart_tx_inst|Equal2~0, rs232, 1 +instance = comp, \uart_tx_inst|Add1~0 , uart_tx_inst|Add1~0, rs232, 1 +instance = comp, \uart_tx_inst|Add1~1 , uart_tx_inst|Add1~1, rs232, 1 +instance = comp, \uart_rx_inst|bit_flag , uart_rx_inst|bit_flag, rs232, 1 +instance = comp, \uart_rx_inst|Equal1~0 , uart_rx_inst|Equal1~0, rs232, 1 +instance = comp, \uart_rx_inst|Equal2~0 , uart_rx_inst|Equal2~0, rs232, 1 +instance = comp, \uart_rx_inst|Equal2~1 , uart_rx_inst|Equal2~1, rs232, 1 +instance = comp, \uart_rx_inst|Equal2~2 , uart_rx_inst|Equal2~2, rs232, 1 +instance = comp, \uart_rx_inst|work_en , uart_rx_inst|work_en, rs232, 1 +instance = comp, \uart_rx_inst|Equal1~1 , uart_rx_inst|Equal1~1, rs232, 1 +instance = comp, \uart_rx_inst|Equal1~2 , uart_rx_inst|Equal1~2, rs232, 1 +instance = comp, \uart_rx_inst|Equal1~3 , uart_rx_inst|Equal1~3, rs232, 1 +instance = comp, \uart_rx_inst|always5~0 , uart_rx_inst|always5~0, rs232, 1 +instance = comp, \uart_rx_inst|start_nedge , uart_rx_inst|start_nedge, rs232, 1 +instance = comp, \uart_rx_inst|work_en~0 , uart_rx_inst|work_en~0, rs232, 1 +instance = comp, \uart_rx_inst|always3~0 , uart_rx_inst|always3~0, rs232, 1 +instance = comp, \tx~output , tx~output, rs232, 1 +instance = comp, \sys_clk~input , sys_clk~input, rs232, 1 +instance = comp, \sys_clk~inputclkctrl , sys_clk~inputclkctrl, rs232, 1 +instance = comp, \uart_rx_inst|Add1~0 , uart_rx_inst|Add1~0, rs232, 1 +instance = comp, \uart_rx_inst|bit_cnt~1 , uart_rx_inst|bit_cnt~1, rs232, 1 +instance = comp, \sys_rst_n~input , sys_rst_n~input, rs232, 1 +instance = comp, \uart_rx_inst|bit_cnt[0] , uart_rx_inst|bit_cnt[0], rs232, 1 +instance = comp, \uart_rx_inst|Add1~2 , uart_rx_inst|Add1~2, rs232, 1 +instance = comp, \uart_rx_inst|bit_cnt[1] , uart_rx_inst|bit_cnt[1], rs232, 1 +instance = comp, \uart_rx_inst|Add1~4 , uart_rx_inst|Add1~4, rs232, 1 +instance = comp, \uart_rx_inst|bit_cnt[2] , uart_rx_inst|bit_cnt[2], rs232, 1 +instance = comp, \uart_rx_inst|always4~0 , uart_rx_inst|always4~0, rs232, 1 +instance = comp, \uart_rx_inst|Add1~6 , uart_rx_inst|Add1~6, rs232, 1 +instance = comp, \uart_rx_inst|bit_cnt~0 , uart_rx_inst|bit_cnt~0, rs232, 1 +instance = comp, \uart_rx_inst|bit_cnt[3] , uart_rx_inst|bit_cnt[3], rs232, 1 +instance = comp, \uart_rx_inst|always4~1 , uart_rx_inst|always4~1, rs232, 1 +instance = comp, \uart_rx_inst|rx_flag~feeder , uart_rx_inst|rx_flag~feeder, rs232, 1 +instance = comp, \uart_rx_inst|rx_flag , uart_rx_inst|rx_flag, rs232, 1 +instance = comp, \uart_rx_inst|po_flag~feeder , uart_rx_inst|po_flag~feeder, rs232, 1 +instance = comp, \uart_rx_inst|po_flag , uart_rx_inst|po_flag, rs232, 1 +instance = comp, \uart_tx_inst|work_en~0 , uart_tx_inst|work_en~0, rs232, 1 +instance = comp, \uart_tx_inst|work_en , uart_tx_inst|work_en, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[0]~13 , uart_tx_inst|baud_cnt[0]~13, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[10]~33 , uart_tx_inst|baud_cnt[10]~33, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[11]~35 , uart_tx_inst|baud_cnt[11]~35, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[11] , uart_tx_inst|baud_cnt[11], rs232, 1 +instance = comp, \uart_tx_inst|Equal1~0 , uart_tx_inst|Equal1~0, rs232, 1 +instance = comp, \uart_tx_inst|Equal1~1 , uart_tx_inst|Equal1~1, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[12]~37 , uart_tx_inst|baud_cnt[12]~37, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[12] , uart_tx_inst|baud_cnt[12], rs232, 1 +instance = comp, \uart_tx_inst|Equal1~3 , uart_tx_inst|Equal1~3, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[2]~17 , uart_tx_inst|baud_cnt[2]~17, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[2] , uart_tx_inst|baud_cnt[2], rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[4]~21 , uart_tx_inst|baud_cnt[4]~21, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[4] , uart_tx_inst|baud_cnt[4], rs232, 1 +instance = comp, \uart_tx_inst|Equal1~2 , uart_tx_inst|Equal1~2, rs232, 1 +instance = comp, \uart_tx_inst|always1~0 , uart_tx_inst|always1~0, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[0] , uart_tx_inst|baud_cnt[0], rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[1]~15 , uart_tx_inst|baud_cnt[1]~15, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[1] , uart_tx_inst|baud_cnt[1], rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[3]~19 , uart_tx_inst|baud_cnt[3]~19, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[3] , uart_tx_inst|baud_cnt[3], rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[6]~25 , uart_tx_inst|baud_cnt[6]~25, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[6] , uart_tx_inst|baud_cnt[6], rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[7]~27 , uart_tx_inst|baud_cnt[7]~27, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[7] , uart_tx_inst|baud_cnt[7], rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[8]~29 , uart_tx_inst|baud_cnt[8]~29, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[8] , uart_tx_inst|baud_cnt[8], rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[9]~31 , uart_tx_inst|baud_cnt[9]~31, rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[9] , uart_tx_inst|baud_cnt[9], rs232, 1 +instance = comp, \uart_tx_inst|baud_cnt[10] , uart_tx_inst|baud_cnt[10], rs232, 1 +instance = comp, \uart_tx_inst|Equal2~1 , uart_tx_inst|Equal2~1, rs232, 1 +instance = comp, \uart_tx_inst|bit_flag , uart_tx_inst|bit_flag, rs232, 1 +instance = comp, \uart_tx_inst|always3~0 , uart_tx_inst|always3~0, rs232, 1 +instance = comp, \uart_tx_inst|bit_cnt[2]~2 , uart_tx_inst|bit_cnt[2]~2, rs232, 1 +instance = comp, \uart_tx_inst|bit_cnt[2] , uart_tx_inst|bit_cnt[2], rs232, 1 +instance = comp, \uart_tx_inst|bit_cnt[3]~4 , uart_tx_inst|bit_cnt[3]~4, rs232, 1 +instance = comp, \uart_tx_inst|bit_cnt[3] , uart_tx_inst|bit_cnt[3], rs232, 1 +instance = comp, \uart_tx_inst|always0~0 , uart_tx_inst|always0~0, rs232, 1 +instance = comp, \uart_tx_inst|always0~1 , uart_tx_inst|always0~1, rs232, 1 +instance = comp, \uart_tx_inst|bit_cnt[0]~5 , uart_tx_inst|bit_cnt[0]~5, rs232, 1 +instance = comp, \uart_tx_inst|bit_cnt[0] , uart_tx_inst|bit_cnt[0], rs232, 1 +instance = comp, \rx~input , rx~input, rs232, 1 +instance = comp, \uart_rx_inst|rx_reg1~0 , uart_rx_inst|rx_reg1~0, rs232, 1 +instance = comp, \uart_rx_inst|rx_reg1 , uart_rx_inst|rx_reg1, rs232, 1 +instance = comp, \uart_rx_inst|rx_reg2~feeder , uart_rx_inst|rx_reg2~feeder, rs232, 1 +instance = comp, \uart_rx_inst|rx_reg2 , uart_rx_inst|rx_reg2, rs232, 1 +instance = comp, \uart_rx_inst|rx_reg3~feeder , uart_rx_inst|rx_reg3~feeder, rs232, 1 +instance = comp, \uart_rx_inst|rx_reg3 , uart_rx_inst|rx_reg3, rs232, 1 +instance = comp, \uart_rx_inst|rx_data[7]~0 , uart_rx_inst|rx_data[7]~0, rs232, 1 +instance = comp, \uart_rx_inst|always8~0 , uart_rx_inst|always8~0, rs232, 1 +instance = comp, \uart_rx_inst|rx_data[7] , uart_rx_inst|rx_data[7], rs232, 1 +instance = comp, \uart_rx_inst|po_data[7] , uart_rx_inst|po_data[7], rs232, 1 +instance = comp, \uart_tx_inst|bit_cnt[1]~3 , uart_tx_inst|bit_cnt[1]~3, rs232, 1 +instance = comp, \uart_tx_inst|bit_cnt[1] , uart_tx_inst|bit_cnt[1], rs232, 1 +instance = comp, \uart_tx_inst|tx~2 , uart_tx_inst|tx~2, rs232, 1 +instance = comp, \uart_tx_inst|tx~5 , uart_tx_inst|tx~5, rs232, 1 +instance = comp, \uart_rx_inst|rx_data[6]~feeder , uart_rx_inst|rx_data[6]~feeder, rs232, 1 +instance = comp, \uart_rx_inst|rx_data[6] , uart_rx_inst|rx_data[6], rs232, 1 +instance = comp, \uart_rx_inst|rx_data[5] , uart_rx_inst|rx_data[5], rs232, 1 +instance = comp, \uart_rx_inst|po_data[5]~feeder , uart_rx_inst|po_data[5]~feeder, rs232, 1 +instance = comp, \uart_rx_inst|po_data[5] , uart_rx_inst|po_data[5], rs232, 1 +instance = comp, \uart_rx_inst|po_data[6] , uart_rx_inst|po_data[6], rs232, 1 +instance = comp, \uart_rx_inst|rx_data[4] , uart_rx_inst|rx_data[4], rs232, 1 +instance = comp, \uart_rx_inst|po_data[4]~feeder , uart_rx_inst|po_data[4]~feeder, rs232, 1 +instance = comp, \uart_rx_inst|po_data[4] , uart_rx_inst|po_data[4], rs232, 1 +instance = comp, \uart_rx_inst|rx_data[3] , uart_rx_inst|rx_data[3], rs232, 1 +instance = comp, \uart_rx_inst|po_data[3] , uart_rx_inst|po_data[3], rs232, 1 +instance = comp, \uart_tx_inst|Mux0~0 , uart_tx_inst|Mux0~0, rs232, 1 +instance = comp, \uart_tx_inst|Mux0~1 , uart_tx_inst|Mux0~1, rs232, 1 +instance = comp, \uart_rx_inst|rx_data[2]~feeder , uart_rx_inst|rx_data[2]~feeder, rs232, 1 +instance = comp, \uart_rx_inst|rx_data[2] , uart_rx_inst|rx_data[2], rs232, 1 +instance = comp, \uart_rx_inst|rx_data[1]~feeder , uart_rx_inst|rx_data[1]~feeder, rs232, 1 +instance = comp, \uart_rx_inst|rx_data[1] , uart_rx_inst|rx_data[1], rs232, 1 +instance = comp, \uart_rx_inst|po_data[1] , uart_rx_inst|po_data[1], rs232, 1 +instance = comp, \uart_rx_inst|rx_data[0]~feeder , uart_rx_inst|rx_data[0]~feeder, rs232, 1 +instance = comp, \uart_rx_inst|rx_data[0] , uart_rx_inst|rx_data[0], rs232, 1 +instance = comp, \uart_rx_inst|po_data[0] , uart_rx_inst|po_data[0], rs232, 1 +instance = comp, \uart_tx_inst|tx~3 , uart_tx_inst|tx~3, rs232, 1 +instance = comp, \uart_tx_inst|tx~4 , uart_tx_inst|tx~4, rs232, 1 +instance = comp, \uart_tx_inst|tx~6 , uart_tx_inst|tx~6, rs232, 1 +instance = comp, \uart_tx_inst|tx~7 , uart_tx_inst|tx~7, rs232, 1 +instance = comp, \uart_tx_inst|tx , uart_tx_inst|tx, rs232, 1 diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_v.sdo b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_v.sdo new file mode 100644 index 0000000..588ece3 --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/quartus_prj/simulation/modelsim/rs232_v.sdo @@ -0,0 +1,2275 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "rs232") + (DATE "06/02/2023 03:03:50") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6066:6066:6066) (5939:5939:5939)) + (PORT sclr (903:903:903) (966:966:966)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (590:590:590)) + (PORT datab (341:341:341) (422:422:422)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (457:457:457)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (461:461:461)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (368:368:368) (452:452:452)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (543:543:543) (580:580:580)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (471:471:471)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (533:533:533) (560:560:560)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (1301:1301:1301) (1261:1261:1261)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (642:642:642)) + (PORT datab (577:577:577) (601:601:601)) + (PORT datac (526:526:526) (560:560:560)) + (PORT datad (541:541:541) (560:560:560)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (487:487:487)) + (PORT datab (429:429:429) (538:538:538)) + (PORT datad (372:372:372) (479:479:479)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (654:654:654)) + (PORT datab (570:570:570) (590:590:590)) + (PORT datac (573:573:573) (591:591:591)) + (PORT datad (330:330:330) (407:407:407)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (PORT datab (344:344:344) (427:427:427)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (830:830:830)) + (PORT datab (575:575:575) (601:601:601)) + (PORT datac (579:579:579) (594:594:594)) + (PORT datad (851:851:851) (810:810:810)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (854:854:854)) + (PORT datab (901:901:901) (869:869:869)) + (PORT datac (872:872:872) (840:840:840)) + (PORT datad (577:577:577) (599:599:599)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (485:485:485)) + (PORT datab (878:878:878) (859:859:859)) + (PORT datac (783:783:783) (700:700:700)) + (PORT datad (485:485:485) (457:457:457)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6063:6063:6063) (5936:5936:5936)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (464:464:464)) + (PORT datab (370:370:370) (454:454:454)) + (PORT datac (330:330:330) (415:415:415)) + (PORT datad (331:331:331) (408:408:408)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datac (822:822:822) (795:795:795)) + (PORT datad (577:577:577) (600:600:600)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (854:854:854)) + (PORT datab (579:579:579) (612:612:612)) + (PORT datac (827:827:827) (807:807:807)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (592:592:592)) + (PORT datab (304:304:304) (328:328:328)) + (PORT datac (240:240:240) (267:267:267)) + (PORT datad (433:433:433) (406:406:406)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|start_nedge) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5805:5805:5805) (5615:5615:5615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (849:849:849) (813:813:813)) + (PORT datad (461:461:461) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (425:425:425)) + (PORT datac (323:323:323) (401:401:401)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tx\~output) + (DELAY + (ABSOLUTE + (PORT i (758:758:758) (794:794:794)) + (IOPATH i o (3336:3336:3336) (3399:3399:3399)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (806:806:806) (852:852:852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sys_clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (200:200:200) (189:189:189)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (482:482:482)) + (PORT datab (342:342:342) (423:423:423)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (484:484:484)) + (PORT datab (360:360:360) (449:449:449)) + (PORT datac (448:448:448) (419:419:419)) + (PORT datad (267:267:267) (303:303:303)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (424:424:424)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (PORT datac (303:303:303) (388:388:388)) + (PORT datad (303:303:303) (379:379:379)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datad (323:323:323) (410:410:410)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (484:484:484)) + (PORT datab (308:308:308) (347:347:347)) + (PORT datad (441:441:441) (417:417:417)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (485:485:485)) + (PORT datab (366:366:366) (456:456:456)) + (PORT datad (261:261:261) (295:295:295)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (265:265:265) (290:290:290)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_flag) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (866:866:866) (834:834:834)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_flag) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (535:535:535) (562:562:562)) + (PORT datad (475:475:475) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5805:5805:5805) (5615:5615:5615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (629:629:629)) + (PORT datab (339:339:339) (421:421:421)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (344:344:344) (427:427:427)) + (PORT datac (302:302:302) (387:387:387)) + (PORT datad (302:302:302) (379:379:379)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (604:604:604)) + (PORT datab (344:344:344) (427:427:427)) + (PORT datac (538:538:538) (561:561:561)) + (PORT datad (241:241:241) (260:260:260)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (449:449:449)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT datab (635:635:635) (646:646:646)) + (PORT datad (575:575:575) (598:598:598)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (613:613:613)) + (PORT datab (578:578:578) (602:602:602)) + (PORT datac (526:526:526) (560:560:560)) + (PORT datad (560:560:560) (584:584:584)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (633:633:633)) + (PORT datab (308:308:308) (333:333:333)) + (PORT datac (450:450:450) (425:425:425)) + (PORT datad (454:454:454) (432:432:432)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (421:421:421)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5811:5811:5811) (5620:5620:5620)) + (PORT sclr (909:909:909) (977:977:977)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (726:726:726)) + (PORT datab (636:636:636) (648:648:648)) + (PORT datac (524:524:524) (497:497:497)) + (PORT datad (576:576:576) (598:598:598)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5805:5805:5805) (5615:5615:5615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT datac (321:321:321) (399:399:399)) + (PORT datad (329:329:329) (402:402:402)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (756:756:756) (694:694:694)) + (PORT datab (322:322:322) (359:359:359)) + (PORT datad (517:517:517) (486:486:486)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (315:315:315)) + (PORT datab (308:308:308) (332:332:332)) + (PORT datad (474:474:474) (447:447:447)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5805:5805:5805) (5615:5615:5615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (446:446:446)) + (PORT datad (330:330:330) (403:403:403)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (413:413:413) (528:528:528)) + (PORT datab (425:425:425) (533:533:533)) + (PORT datac (346:346:346) (445:445:445)) + (PORT datad (485:485:485) (457:457:457)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (643:643:643)) + (PORT datab (320:320:320) (356:356:356)) + (PORT datad (836:836:836) (817:817:817)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rx\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (796:796:796) (842:842:842)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg1\~0) + (DELAY + (ABSOLUTE + (PORT datad (3626:3626:3626) (3787:3787:3787)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5805:5805:5805) (5615:5615:5615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5805:5805:5805) (5615:5615:5615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (307:307:307) (384:384:384)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg3) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5805:5805:5805) (5615:5615:5615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (819:819:819) (787:787:787)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (483:483:483)) + (PORT datab (306:306:306) (344:344:344)) + (PORT datad (318:318:318) (405:405:405)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (1271:1271:1271) (1242:1242:1242)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (663:663:663)) + (PORT datab (320:320:320) (357:357:357)) + (PORT datad (520:520:520) (490:490:490)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (492:492:492)) + (PORT datab (423:423:423) (530:530:530)) + (PORT datad (367:367:367) (473:473:473)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~5) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (448:448:448)) + (PORT datab (278:278:278) (304:304:304)) + (PORT datac (549:549:549) (592:592:592)) + (PORT datad (538:538:538) (558:558:558)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (325:325:325) (396:396:396)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT asdata (1261:1261:1261) (1233:1233:1233)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (812:812:812) (791:791:791)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (1280:1280:1280) (1251:1251:1251)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT asdata (1244:1244:1244) (1213:1213:1213)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (809:809:809) (792:792:792)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT asdata (1240:1240:1240) (1212:1212:1212)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (1606:1606:1606) (1505:1505:1505)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (532:532:532)) + (PORT datab (336:336:336) (413:413:413)) + (PORT datad (389:389:389) (495:495:495)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (529:529:529)) + (PORT datab (335:335:335) (411:411:411)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (323:323:323) (402:402:402)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (511:511:511) (537:537:537)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (1299:1299:1299) (1269:1269:1269)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (323:323:323) (401:401:401)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5817:5817:5817) (5626:5626:5626)) + (PORT ena (1037:1037:1037) (1013:1013:1013)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (1290:1290:1290) (1262:1262:1262)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (PORT ena (1708:1708:1708) (1649:1649:1649)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~3) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (420:420:420)) + (PORT datab (431:431:431) (540:540:540)) + (PORT datad (374:374:374) (481:481:481)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~4) + (DELAY + (ABSOLUTE + (PORT dataa (416:416:416) (531:531:531)) + (PORT datab (429:429:429) (537:537:537)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~6) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (641:641:641)) + (PORT datab (580:580:580) (608:608:608)) + (PORT datac (245:245:245) (276:276:276)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~7) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (493:493:493)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (245:245:245) (277:277:277)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|tx) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5544:5544:5544) (5322:5322:5322)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/rtl/rs232.v b/smh-ac415-fpga/examples/05_rs232/rs232/rtl/rs232.v new file mode 100644 index 0000000..15f9b9d --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/rtl/rs232.v @@ -0,0 +1,75 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/06/12 +// Module Name : rs232 +// Project Name : rs232 +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : RS232顶层模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module rs232 +( + input wire sys_clk , //系统时钟50MHz + input wire sys_rst_n , //全局复位 + input wire rx , //串口接收数据 + + output wire tx //串口发送数据 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter UART_BPS = 14'd9600 , //比特率 + CLK_FREQ = 26'd50_000_000 ; //时钟频率 + +//wire define +wire [7:0] po_data; +wire po_flag; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// +//------------------------ uart_rx_inst ------------------------ +uart_rx +#( + .UART_BPS (UART_BPS ), //串口波特率 + .CLK_FREQ (CLK_FREQ ) //时钟频率 +) +uart_rx_inst +( + .sys_clk (sys_clk ), //input sys_clk + .sys_rst_n (sys_rst_n ), //input sys_rst_n + .rx (rx ), //input rx + + .po_data (po_data ), //output [7:0] po_data + .po_flag (po_flag ) //output po_flag +); + +//------------------------ uart_tx_inst ------------------------ +uart_tx +#( + .UART_BPS (UART_BPS ), //串口波特率 + .CLK_FREQ (CLK_FREQ ) //时钟频率 +) +uart_tx_inst +( + .sys_clk (sys_clk ), //input sys_clk + .sys_rst_n (sys_rst_n ), //input sys_rst_n + .pi_data (po_data ), //input [7:0] pi_data + .pi_flag (po_flag ), //input pi_flag + + .tx (tx ) //output tx +); + +endmodule diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/rtl/uart_rx.v b/smh-ac415-fpga/examples/05_rs232/rs232/rtl/uart_rx.v new file mode 100644 index 0000000..5ebbaba --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/rtl/uart_rx.v @@ -0,0 +1,154 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +//Create Date : 2019/06/12 +// Module Name : uart_rx +// Project Name : rs232 +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module uart_rx +#( + parameter UART_BPS = 'd9600, //串口波特率 + parameter CLK_FREQ = 'd50_000_000 //时钟频率 +) +( + input wire sys_clk , //系统时钟50MHz + input wire sys_rst_n , //全局复位 + input wire rx , //串口接收数据 + + output reg [7:0] po_data , //串转并后的8bit数据 + output reg po_flag //串转并后的数据有效标志信号 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//localparam define +localparam BAUD_CNT_MAX = CLK_FREQ/UART_BPS ; + +//reg define +reg rx_reg1 ; +reg rx_reg2 ; +reg rx_reg3 ; +reg start_nedge ; +reg work_en ; +reg [12:0] baud_cnt ; +reg bit_flag ; +reg [3:0] bit_cnt ; +reg [7:0] rx_data ; +reg rx_flag ; + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//插入两级寄存器进行数据同步，用来消除亚稳态 +//rx_reg1:第一级寄存器，寄存器空闲状态复位为1 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rx_reg1 <= 1'b1; + else + rx_reg1 <= rx; + +//rx_reg2:第二级寄存器，寄存器空闲状态复位为1 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rx_reg2 <= 1'b1; + else + rx_reg2 <= rx_reg1; + +//rx_reg3:第三级寄存器和第二级寄存器共同构成下降沿检测 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rx_reg3 <= 1'b1; + else + rx_reg3 <= rx_reg2; + +//start_nedge:检测到下降沿时start_nedge产生一个时钟的高电平 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + start_nedge <= 1'b0; + else if((~rx_reg2) && (rx_reg3)) + start_nedge <= 1'b1; + else + start_nedge <= 1'b0; + +//work_en:接收数据工作使能信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + work_en <= 1'b0; + else if(start_nedge == 1'b1) + work_en <= 1'b1; + else if((bit_cnt == 4'd8) && (bit_flag == 1'b1)) + work_en <= 1'b0; + +//baud_cnt:波特率计数器计数，从0计数到BAUD_CNT_MAX - 1 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + baud_cnt <= 13'b0; + else if((baud_cnt == BAUD_CNT_MAX - 1) || (work_en == 1'b0)) + baud_cnt <= 13'b0; + else if(work_en == 1'b1) + baud_cnt <= baud_cnt + 1'b1; + +//bit_flag:当baud_cnt计数器计数到中间数时采样的数据最稳定， +//此时拉高一个标志信号表示数据可以被取走 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + bit_flag <= 1'b0; + else if(baud_cnt == BAUD_CNT_MAX/2 - 1) + bit_flag <= 1'b1; + else + bit_flag <= 1'b0; + +//bit_cnt:有效数据个数计数器，当8个有效数据（不含起始位和停止位） +//都接收完成后计数器清零 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + bit_cnt <= 4'b0; + else if((bit_cnt == 4'd8) && (bit_flag == 1'b1)) + bit_cnt <= 4'b0; + else if(bit_flag ==1'b1) + bit_cnt <= bit_cnt + 1'b1; + +//rx_data:输入数据进行移位 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rx_data <= 8'b0; + else if((bit_cnt >= 4'd1)&&(bit_cnt <= 4'd8)&&(bit_flag == 1'b1)) + rx_data <= {rx_reg3, rx_data[7:1]}; + +//rx_flag:输入数据移位完成时rx_flag拉高一个时钟的高电平 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rx_flag <= 1'b0; + else if((bit_cnt == 4'd8) && (bit_flag == 1'b1)) + rx_flag <= 1'b1; + else + rx_flag <= 1'b0; + +//po_data:输出完整的8位有效数据 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + po_data <= 8'b0; + else if(rx_flag == 1'b1) + po_data <= rx_data; + +//po_flag:输出数据有效标志（比rx_flag延后一个时钟周期，为了和po_data同步） +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + po_flag <= 1'b0; + else + po_flag <= rx_flag; + +endmodule diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/rtl/uart_tx.v b/smh-ac415-fpga/examples/05_rs232/rs232/rtl/uart_tx.v new file mode 100644 index 0000000..cf80fdf --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/rtl/uart_tx.v @@ -0,0 +1,104 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/06/12 +// Module Name : uart_tx +// Project Name : rs232 +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module uart_tx +#( + parameter UART_BPS = 'd9600, //串口波特率 + parameter CLK_FREQ = 'd50_000_000 //时钟频率 +) +( + input wire sys_clk , //系统时钟50MHz + input wire sys_rst_n , //全局复位 + input wire [7:0] pi_data , //模块输入的8bit数据 + input wire pi_flag , //并行数据有效标志信号 + + output reg tx //串转并后的1bit数据 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//localparam define +localparam BAUD_CNT_MAX = CLK_FREQ/UART_BPS ; + +//reg define +reg [12:0] baud_cnt; +reg bit_flag; +reg [3:0] bit_cnt ; +reg work_en ; + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//work_en:接收数据工作使能信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + work_en <= 1'b0; + else if(pi_flag == 1'b1) + work_en <= 1'b1; + else if((bit_flag == 1'b1) && (bit_cnt == 4'd9)) + work_en <= 1'b0; + +//baud_cnt:波特率计数器计数，从0计数到BAUD_CNT_MAX - 1 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + baud_cnt <= 13'b0; + else if((baud_cnt == BAUD_CNT_MAX - 1) || (work_en == 1'b0)) + baud_cnt <= 13'b0; + else if(work_en == 1'b1) + baud_cnt <= baud_cnt + 1'b1; + +//bit_flag:当baud_cnt计数器计数到1时让bit_flag拉高一个时钟的高电平 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + bit_flag <= 1'b0; + else if(baud_cnt == 13'd1) + bit_flag <= 1'b1; + else + bit_flag <= 1'b0; + +//bit_cnt:数据位数个数计数，10个有效数据（含起始位和停止位）到来后计数器清零 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + bit_cnt <= 4'b0; + else if((bit_flag == 1'b1) && (bit_cnt == 4'd9)) + bit_cnt <= 4'b0; + else if((bit_flag == 1'b1) && (work_en == 1'b1)) + bit_cnt <= bit_cnt + 1'b1; + +//tx:输出数据在满足rs232协议（起始位为0，停止位为1）的情况下一位一位输出 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + tx <= 1'b1; //空闲状态时为高电平 + else if(bit_flag == 1'b1) + case(bit_cnt) + 0 : tx <= 1'b0; + 1 : tx <= pi_data[0]; + 2 : tx <= pi_data[1]; + 3 : tx <= pi_data[2]; + 4 : tx <= pi_data[3]; + 5 : tx <= pi_data[4]; + 6 : tx <= pi_data[5]; + 7 : tx <= pi_data[6]; + 8 : tx <= pi_data[7]; + 9 : tx <= 1'b1; + default : tx <= 1'b1; + endcase + +endmodule diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_rs232.v b/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_rs232.v new file mode 100644 index 0000000..1cc87c8 --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_rs232.v @@ -0,0 +1,98 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/06/12 +// Module Name : tb_rs232 +// Project Name : rs232 +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module tb_rs232(); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//wire define +wire tx ; + +//reg define +reg sys_clk ; +reg sys_rst_n ; +reg rx ; + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//初始化系统时钟、全局复位和输入信号 +initial begin + sys_clk = 1'b1; + sys_rst_n <= 1'b0; + rx <= 1'b1; + #20; + sys_rst_n <= 1'b1; +end + +//调用任务rx_byte +initial begin + #200 + rx_byte(); +end + +//sys_clk:每10ns电平翻转一次，产生一个50MHz的时钟信号 +always #10 sys_clk = ~sys_clk; + +//创建任务rx_byte，本次任务调用rx_bit任务，发送8次数据，分别为0~7 +task rx_byte(); //因为不需要外部传递参数，所以括号中没有输入 + integer j; + for(j=0; j<8; j=j+1) //调用8次rx_bit任务，每次发送的值从0变化7 + rx_bit(j); +endtask + +//创建任务rx_bit，每次发送的数据有10位，data的值分别为0到7由j的值传递进来 +task rx_bit( + input [7:0] data +); + integer i; + for(i=0; i<10; i=i+1) begin + case(i) + 0: rx <= 1'b0; + 1: rx <= data[0]; + 2: rx <= data[1]; + 3: rx <= data[2]; + 4: rx <= data[3]; + 5: rx <= data[4]; + 6: rx <= data[5]; + 7: rx <= data[6]; + 8: rx <= data[7]; + 9: rx <= 1'b1; + endcase + #(5208*20); //每发送1位数据延时5208个时钟周期 + end +endtask + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// +//------------------------ rs232_inst ------------------------ +rs232 rs232_inst +( + .sys_clk (sys_clk ), //input sys_clk + .sys_rst_n (sys_rst_n ), //input sys_rst_n + .rx (rx ), //input rx + + .tx (tx ) //output tx +); + +endmodule + + diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_uart_rx.v b/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_uart_rx.v new file mode 100644 index 0000000..8c0c390 --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_uart_rx.v @@ -0,0 +1,103 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/06/12 +// Module Name : tb_uart_rx +// Project Name : rs232 +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module tb_uart_rx(); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//reg define +reg sys_clk; +reg sys_rst_n; +reg rx; + +//wire define +wire [7:0] po_data; +wire po_flag; + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//初始化系统时钟、全局复位和输入信号 +initial begin + sys_clk = 1'b1; + sys_rst_n <= 1'b0; + rx <= 1'b1; + #20; + sys_rst_n <= 1'b1; +end + +//模拟发送8次数据，分别为0~7 +initial begin + #200 + rx_bit(8'd0); //任务的调用，任务名+括号中要传递进任务的参数 + rx_bit(8'd1); + rx_bit(8'd2); + rx_bit(8'd3); + rx_bit(8'd4); + rx_bit(8'd5); + rx_bit(8'd6); + rx_bit(8'd7); +end + +//sys_clk:每10ns电平翻转一次，产生一个50MHz的时钟信号 +always #10 sys_clk = ~sys_clk; + +//定义一个名为rx_bit的任务，每次发送的数据有10位 +//data的值分别为0~7由j的值传递进来 +//任务以task开头，后面紧跟着的是任务名，调用时使用 +task rx_bit( + //传递到任务中的参数，调用任务的时候从外部传进来一个8位的值 + input [7:0] data +); + integer i; //定义一个常量 +//用for循环产生一帧数据，for括号中最后执行的内容只能写i=i+1 +//不可以写成C语言i=i++的形式 + for(i=0; i<10; i=i+1) begin + case(i) + 0: rx <= 1'b0; + 1: rx <= data[0]; + 2: rx <= data[1]; + 3: rx <= data[2]; + 4: rx <= data[3]; + 5: rx <= data[4]; + 6: rx <= data[5]; + 7: rx <= data[6]; + 8: rx <= data[7]; + 9: rx <= 1'b1; + endcase + #(5208*20); //每发送1位数据延时5208个时钟周期 + end +endtask //任务以endtask结束 + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// +//------------------------uart_rx_inst------------------------ +uart_rx uart_rx_inst( + .sys_clk (sys_clk ), //input sys_clk + .sys_rst_n (sys_rst_n ), //input sys_rst_n + .rx (rx ), //input rx + + .po_data (po_data ), //output [7:0] po_data + .po_flag (po_flag ) //output po_flag +); + +endmodule + diff --git a/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_uart_tx.v b/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_uart_tx.v new file mode 100644 index 0000000..b0ecf1c --- /dev/null +++ b/smh-ac415-fpga/examples/05_rs232/rs232/sim/tb_uart_tx.v @@ -0,0 +1,117 @@ +`timescale 1ns/1ns +///////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/06/12 +// Module Name : tb_uart_tx +// Project Name : rs232 +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module tb_uart_tx(); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//reg define +reg sys_clk; +reg sys_rst_n; +reg [7:0] pi_data; +reg pi_flag; + +//wire define +wire tx; + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//初始化系统时钟、全局复位 +initial begin + sys_clk = 1'b1; + sys_rst_n <= 1'b0; + #20; + sys_rst_n <= 1'b1; +end + +//模拟发送7次数据，分别为0~7 +initial begin + pi_data <= 8'b0; + pi_flag <= 1'b0; + #200 + //发送数据0 + pi_data <= 8'd0; + pi_flag <= 1'b1; + #20 + pi_flag <= 1'b0; +//每发送1bit数据需要5208个时钟周期，一帧数据为10bit +//所以需要数据延时(5208*20*10)后再产生下一个数据 + #(5208*20*10); + //发送数据1 + pi_data <= 8'd1; + pi_flag <= 1'b1; + #20 + pi_flag <= 1'b0; + #(5208*20*10); + //发送数据2 + pi_data <= 8'd2; + pi_flag <= 1'b1; + #20 + pi_flag <= 1'b0; + #(5208*20*10); + //发送数据3 + pi_data <= 8'd3; + pi_flag <= 1'b1; + #20 + pi_flag <= 1'b0; + #(5208*20*10); + //发送数据4 + pi_data <= 8'd4; + pi_flag <= 1'b1; + #20 + pi_flag <= 1'b0; + #(5208*20*10); + //发送数据5 + pi_data <= 8'd5; + pi_flag <= 1'b1; + #20 + pi_flag <= 1'b0; + #(5208*20*10); + //发送数据6 + pi_data <= 8'd6; + pi_flag <= 1'b1; + #20 + pi_flag <= 1'b0; + #(5208*20*10); + //发送数据7 + pi_data <= 8'd7; + pi_flag <= 1'b1; + #20 + pi_flag <= 1'b0; +end + +//sys_clk:每10ns电平翻转一次，产生一个50MHz的时钟信号 +always #10 sys_clk = ~sys_clk; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// +//------------------------uart_rx_inst------------------------ +uart_tx uart_tx_inst( + .sys_clk (sys_clk ), //input sys_clk + .sys_rst_n (sys_rst_n ), //input sys_rst_n + .pi_data (pi_data ), //output [7:0] pi_data + .pi_flag (pi_flag ), //output pi_flag + + .tx (tx ) //input tx +); + +endmodule diff --git "a/smh-ac415-fpga/examples/05_rs232/\345\256\236\351\252\214\347\216\260\350\261\241.txt" "b/smh-ac415-fpga/examples/05_rs232/\345\256\236\351\252\214\347\216\260\350\261\241.txt" new file mode 100644 index 0000000..33456c5 --- /dev/null +++ "b/smh-ac415-fpga/examples/05_rs232/\345\256\236\351\252\214\347\216\260\350\261\241.txt" @@ -0,0 +1,2 @@ +现象：把usb插入电脑，预先安装ch340串口驱动，打开某个串口软件，波特率选择9600，接收发送均选择hex，发送框输入“1234567890abefcd”，接收框会显示“12 34 56 78 90 AB EF CD ”，此例程参考野火fpga例程修改而来。具体可参考野火教程。 +测试：可以测试串口ch340是否正常。 \ No newline at end of file diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/doc/data.txt b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/doc/data.txt new file mode 100644 index 0000000..24ef7b8 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/doc/data.txt @@ -0,0 +1 @@ +00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F \ No newline at end of file diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/doc/uart_sd.vsdx b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/doc/uart_sd.vsdx new file mode 100644 index 0000000..83a2e48 Binary files /dev/null and b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/doc/uart_sd.vsdx differ diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/PLLJ_PLLSPE_INFO.txt b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/PLLJ_PLLSPE_INFO.txt new file mode 100644 index 0000000..790cae7 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/PLLJ_PLLSPE_INFO.txt @@ -0,0 +1,5 @@ +PLL_Name clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|pll1 +PLLJITTER 30 +PLLSPEmax 84 +PLLSPEmin -53 + diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.ppf b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.ppf new file mode 100644 index 0000000..a0d0ea9 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.qip b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.qip new file mode 100644 index 0000000..ec92e56 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clk_gen.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen.ppf"] diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.v new file mode 100644 index 0000000..07e1850 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.v @@ -0,0 +1,348 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module clk_gen ( + areset, + inclk0, + c0, + c1, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire5), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 1, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 1, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 1, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 1, + altpll_component.clk1_phase_shift = "10000", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Cyclone IV E", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clk_gen", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "10000" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen_bb.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen_bb.v new file mode 100644 index 0000000..c60b06d --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen_bb.v @@ -0,0 +1,232 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module clk_gen ( + areset, + inclk0, + c0, + c1, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "10000" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen_inst.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen_inst.v new file mode 100644 index 0000000..bad6ce7 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen_inst.v @@ -0,0 +1,7 @@ +clk_gen clk_gen_inst ( + .areset ( areset_sig ), + .inclk0 ( inclk0_sig ), + .c0 ( c0_sig ), + .c1 ( c1_sig ), + .locked ( locked_sig ) + ); diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..a059cd0 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt @@ -0,0 +1,66 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=1 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=1 +CLK0_PHASE_SHIFT=0 +CLK1_DIVIDE_BY=1 +CLK1_DUTY_CYCLE=50 +CLK1_MULTIPLY_BY=1 +CLK1_PHASE_SHIFT=10000 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=20000 +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_USED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_USED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_USED +PORT_clk2=PORT_UNUSED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +SELF_RESET_ON_LOSS_LOCK=OFF +WIDTH_CLOCK=5 +DEVICE_FAMILY="Cyclone IV E" +CBX_AUTO_BLACKBOX=ALL +areset +inclk +inclk +clk +clk +locked diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.qip b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.qip new file mode 100644 index 0000000..d27d36e --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "FIFO" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fifo_rd_data.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_rd_data_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_rd_data_bb.v"] diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.v new file mode 100644 index 0000000..7e69a6c --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.v @@ -0,0 +1,156 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo_mixed_widths + +// ============================================================ +// File Name: fifo_rd_data.v +// Megafunction Name(s): +// dcfifo_mixed_widths +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_rd_data ( + data, + rdclk, + rdreq, + wrclk, + wrreq, + q); + + input [15:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [7:0] q; + + wire [7:0] sub_wire0; + wire [7:0] q = sub_wire0[7:0]; + + dcfifo_mixed_widths dcfifo_mixed_widths_component ( + .data (data), + .rdclk (rdclk), + .rdreq (rdreq), + .wrclk (wrclk), + .wrreq (wrreq), + .q (sub_wire0), + .aclr (1'b0), + .rdempty (), + .rdfull (), + .rdusedw (), + .wrempty (), + .wrfull (), + .wrusedw ()); + defparam + dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E", + dcfifo_mixed_widths_component.lpm_numwords = 512, + dcfifo_mixed_widths_component.lpm_showahead = "OFF", + dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths", + dcfifo_mixed_widths_component.lpm_width = 16, + dcfifo_mixed_widths_component.lpm_widthu = 9, + dcfifo_mixed_widths_component.lpm_widthu_r = 10, + dcfifo_mixed_widths_component.lpm_width_r = 8, + dcfifo_mixed_widths_component.overflow_checking = "ON", + dcfifo_mixed_widths_component.rdsync_delaypipe = 4, + dcfifo_mixed_widths_component.underflow_checking = "ON", + dcfifo_mixed_widths_component.use_eab = "ON", + dcfifo_mixed_widths_component.wrsync_delaypipe = 4; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "512" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "1" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "8" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "0" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" +// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "10" +// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data_bb.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data_bb.v new file mode 100644 index 0000000..4230405 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data_bb.v @@ -0,0 +1,118 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo_mixed_widths + +// ============================================================ +// File Name: fifo_rd_data.v +// Megafunction Name(s): +// dcfifo_mixed_widths +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_rd_data ( + data, + rdclk, + rdreq, + wrclk, + wrreq, + q); + + input [15:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [7:0] q; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "512" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "1" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "8" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "0" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" +// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "10" +// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_rd_data_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data_inst.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data_inst.v new file mode 100644 index 0000000..e97cd51 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data_inst.v @@ -0,0 +1,8 @@ +fifo_rd_data fifo_rd_data_inst ( + .data ( data_sig ), + .rdclk ( rdclk_sig ), + .rdreq ( rdreq_sig ), + .wrclk ( wrclk_sig ), + .wrreq ( wrreq_sig ), + .q ( q_sig ) + ); diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..bacc0ff --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/greybox_tmp/cbx_args.txt @@ -0,0 +1,23 @@ +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_NUMWORDS=512 +LPM_SHOWAHEAD=OFF +LPM_TYPE=dcfifo_mixed_widths +LPM_WIDTH=16 +LPM_WIDTHU=9 +LPM_WIDTHU_R=10 +LPM_WIDTH_R=8 +OVERFLOW_CHECKING=ON +RDSYNC_DELAYPIPE=4 +UNDERFLOW_CHECKING=ON +USE_EAB=ON +WRSYNC_DELAYPIPE=4 +DEVICE_FAMILY="Cyclone IV E" +data +rdclk +rdreq +wrclk +wrreq +q +rdusedw +wrfull +wrusedw diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.qip b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.qip new file mode 100644 index 0000000..8ccea8e --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "FIFO" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fifo_wr_data.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_wr_data_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_wr_data_bb.v"] diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.v new file mode 100644 index 0000000..1ddb948 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.v @@ -0,0 +1,161 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo_mixed_widths + +// ============================================================ +// File Name: fifo_wr_data.v +// Megafunction Name(s): +// dcfifo_mixed_widths +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_wr_data ( + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdusedw); + + input [7:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [15:0] q; + output [8:0] rdusedw; + + wire [8:0] sub_wire0; + wire [15:0] sub_wire1; + wire [8:0] rdusedw = sub_wire0[8:0]; + wire [15:0] q = sub_wire1[15:0]; + + dcfifo_mixed_widths dcfifo_mixed_widths_component ( + .data (data), + .rdclk (rdclk), + .rdreq (rdreq), + .wrclk (wrclk), + .wrreq (wrreq), + .rdusedw (sub_wire0), + .q (sub_wire1), + .aclr (1'b0), + .rdempty (), + .rdfull (), + .wrempty (), + .wrfull (), + .wrusedw ()); + defparam + dcfifo_mixed_widths_component.intended_device_family = "Cyclone IV E", + dcfifo_mixed_widths_component.lpm_numwords = 1024, + dcfifo_mixed_widths_component.lpm_showahead = "OFF", + dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths", + dcfifo_mixed_widths_component.lpm_width = 8, + dcfifo_mixed_widths_component.lpm_widthu = 10, + dcfifo_mixed_widths_component.lpm_widthu_r = 9, + dcfifo_mixed_widths_component.lpm_width_r = 16, + dcfifo_mixed_widths_component.overflow_checking = "ON", + dcfifo_mixed_widths_component.rdsync_delaypipe = 4, + dcfifo_mixed_widths_component.underflow_checking = "ON", + dcfifo_mixed_widths_component.use_eab = "ON", + dcfifo_mixed_widths_component.wrsync_delaypipe = 4; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "1024" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "8" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "1" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "16" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "0" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9" +// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]" +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data_bb.v TRUE diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data_bb.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data_bb.v new file mode 100644 index 0000000..0d15210 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data_bb.v @@ -0,0 +1,121 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo_mixed_widths + +// ============================================================ +// File Name: fifo_wr_data.v +// Megafunction Name(s): +// dcfifo_mixed_widths +// +// Simulation Library Files(s): +// +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_wr_data ( + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdusedw); + + input [7:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [15:0] q; + output [8:0] rdusedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "1024" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "8" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "1" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "16" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "0" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9" +// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL "rdusedw[8..0]" +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_wr_data_bb.v TRUE diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data_inst.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data_inst.v new file mode 100644 index 0000000..106098f --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data_inst.v @@ -0,0 +1,9 @@ +fifo_wr_data fifo_wr_data_inst ( + .data ( data_sig ), + .rdclk ( rdclk_sig ), + .rdreq ( rdreq_sig ), + .wrclk ( wrclk_sig ), + .wrreq ( wrreq_sig ), + .q ( q_sig ), + .rdusedw ( rdusedw_sig ) + ); diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..a6f0d77 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/greybox_tmp/cbx_args.txt @@ -0,0 +1,22 @@ +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_NUMWORDS=1024 +LPM_SHOWAHEAD=OFF +LPM_TYPE=dcfifo_mixed_widths +LPM_WIDTH=8 +LPM_WIDTHU=10 +LPM_WIDTHU_R=9 +LPM_WIDTH_R=16 +OVERFLOW_CHECKING=ON +RDSYNC_DELAYPIPE=4 +UNDERFLOW_CHECKING=ON +USE_EAB=ON +WRSYNC_DELAYPIPE=4 +DEVICE_FAMILY="Cyclone IV E" +data +rdclk +rdreq +wrclk +wrreq +q +rdusedw +wrusedw diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd.sft b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd.sft new file mode 100644 index 0000000..efdb038 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd.sft @@ -0,0 +1,6 @@ +set tool_name "ModelSim (Verilog)" +set corner_file_list { + {{"Slow -8 1.2V 85 Model"} {uart_sd_8_1200mv_85c_slow.vo uart_sd_8_1200mv_85c_v_slow.sdo}} + {{"Slow -8 1.2V 0 Model"} {uart_sd_8_1200mv_0c_slow.vo uart_sd_8_1200mv_0c_v_slow.sdo}} + {{"Fast -M 1.2V 0 Model"} {uart_sd_min_1200mv_0c_fast.vo uart_sd_min_1200mv_0c_v_fast.sdo}} +} diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd.vo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd.vo new file mode 100644 index 0000000..a6403c2 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd.vo @@ -0,0 +1,24509 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:03:14" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module uart_sd ( + sys_clk, + sys_rst_n, + rx, + sd_miso, + sd_clk, + sd_cs_n, + sd_mosi, + tx); +input sys_clk; +input sys_rst_n; +input rx; +input sd_miso; +output sd_clk; +output sd_cs_n; +output sd_mosi; +output tx; + +// Design Ports Information +// sd_clk => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// sd_cs_n => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default +// sd_mosi => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default +// sd_miso => Location: PIN_E9, I/O Standard: 2.5 V, Current Strength: Default +// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("uart_sd_v.sdo"); +// synopsys translate_on + +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ; +wire \uart_tx_inst|baud_cnt[2]~17_combout ; +wire \uart_tx_inst|baud_cnt[5]~23_combout ; +wire \uart_tx_inst|baud_cnt[10]~33_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ; +wire \data_rw_ctrl_inst|cnt_wait[5]~27_combout ; +wire \uart_rx_inst|Add1~4_combout ; +wire \uart_rx_inst|baud_cnt[4]~21_combout ; +wire \uart_rx_inst|baud_cnt[10]~33_combout ; +wire \data_rw_ctrl_inst|send_data_num[3]~18_combout ; +wire \data_rw_ctrl_inst|send_data_num[6]~24_combout ; +wire \data_rw_ctrl_inst|send_data_num[7]~27 ; +wire \data_rw_ctrl_inst|send_data_num[8]~29 ; +wire \data_rw_ctrl_inst|send_data_num[8]~28_combout ; +wire \data_rw_ctrl_inst|send_data_num[9]~31 ; +wire \data_rw_ctrl_inst|send_data_num[9]~30_combout ; +wire \data_rw_ctrl_inst|send_data_num[10]~33 ; +wire \data_rw_ctrl_inst|send_data_num[10]~32_combout ; +wire \data_rw_ctrl_inst|send_data_num[11]~34_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ; +wire \sd_ctrl_inst|sd_init_inst|Equal6~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux0~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~4_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~5_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~6_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~7_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~6_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~7_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~3_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~4_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~5_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~6_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~7_combout ; +wire \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~8_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~9_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~10_combout ; +wire \uart_tx_inst|always0~0_combout ; +wire \uart_tx_inst|Mux0~1_combout ; +wire \uart_tx_inst|Mux0~2_combout ; +wire \uart_tx_inst|Mux0~3_combout ; +wire \uart_tx_inst|Mux0~4_combout ; +wire \uart_tx_inst|Mux0~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal1~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector8~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector0~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal3~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal3~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal3~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal3~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ; +wire \sd_ctrl_inst|sd_write_inst|Selector2~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Add3~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ; +wire \uart_tx_inst|work_en~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ; +wire \uart_tx_inst|Add1~1_combout ; +wire \uart_tx_inst|bit_cnt[2]~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector3~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector3~1_combout ; +wire \data_rw_ctrl_inst|tx_flag~q ; +wire \uart_tx_inst|work_en~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~6_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~7_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~1_combout ; +wire \uart_rx_inst|always8~0_combout ; +wire \uart_rx_inst|rx_reg3~q ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ; +wire \uart_rx_inst|Equal2~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ; +wire \uart_rx_inst|rx_reg2~q ; +wire \data_rw_ctrl_inst|always3~2_combout ; +wire \uart_rx_inst|Equal1~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ; +wire \uart_rx_inst|rx_reg1~q ; +wire \uart_rx_inst|start_nedge~q ; +wire \uart_rx_inst|always3~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ; +wire \uart_rx_inst|rx_data[7]~0_combout ; +wire \uart_rx_inst|rx_reg1~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ; +wire \rx~input_o ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|tx_flag~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ; +wire \uart_rx_inst|po_data[1]~feeder_combout ; +wire \uart_rx_inst|rx_data[0]~feeder_combout ; +wire \uart_rx_inst|po_data[5]~feeder_combout ; +wire \uart_rx_inst|rx_data[4]~feeder_combout ; +wire \uart_rx_inst|po_data[6]~feeder_combout ; +wire \uart_rx_inst|rx_data[5]~feeder_combout ; +wire \uart_rx_inst|po_data[7]~feeder_combout ; +wire \uart_rx_inst|rx_data[6]~feeder_combout ; +wire \uart_rx_inst|po_data[3]~feeder_combout ; +wire \uart_rx_inst|rx_data[2]~feeder_combout ; +wire \uart_rx_inst|po_data[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ; +wire \uart_rx_inst|rx_reg2~feeder_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ; +wire \sd_miso~input_o ; +wire \sd_ctrl_inst|sd_init_inst|miso_dly~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal0~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal0~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal3~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_en~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_en~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_en~q ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal1~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal2~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal2~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector0~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal0~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal0~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal0~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.IDLE~q ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~q ; +wire \sd_ctrl_inst|sd_init_inst|WideOr18~combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal5~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal5~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal5~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector2~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector1~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector1~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector5~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector4~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector7~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector3~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector3~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector15~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector15~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector15~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|init_end~q ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal2~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal2~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector3~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ; +wire \sd_ctrl_inst|sd_read_inst|Selector2~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector2~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Add3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal9~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~11_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~9_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~13_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~15_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~q ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector4~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.RD_END~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector0~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector0~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.IDLE~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal1~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal1~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~q ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal4~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal4~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal4~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector2~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Add3~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Add3~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector4~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~7_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~6_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~5_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal6~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~4_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal6~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal6~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector5~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.WR_END~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector0~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cs_n~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cs_n~q ; +wire \sd_ctrl_inst|sd_write_inst|Selector0~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.IDLE~q ; +wire \data_rw_ctrl_inst|wr_busy_dly~feeder_combout ; +wire \data_rw_ctrl_inst|wr_busy_dly~q ; +wire \data_rw_ctrl_inst|wr_busy_fall~0_combout ; +wire \data_rw_ctrl_inst|rd_en~q ; +wire \sd_ctrl_inst|sd_read_inst|cs_n~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|cs_n~q ; +wire \sd_ctrl_inst|sd_cs_n~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal6~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal6~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~3_combout ; +wire \sd_ctrl_inst|sd_init_inst|cs_n~q ; +wire \sd_ctrl_inst|sd_cs_n~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~11_combout ; +wire \sd_ctrl_inst|sd_init_inst|mosi~q ; +wire \sd_ctrl_inst|sd_read_inst|mosi~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|mosi~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|mosi~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|mosi~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ; +wire \uart_rx_inst|Add1~1 ; +wire \uart_rx_inst|Add1~3 ; +wire \uart_rx_inst|Add1~5 ; +wire \uart_rx_inst|Add1~6_combout ; +wire \uart_rx_inst|bit_cnt~0_combout ; +wire \uart_rx_inst|Add1~0_combout ; +wire \uart_rx_inst|bit_cnt~1_combout ; +wire \uart_rx_inst|Add1~2_combout ; +wire \uart_rx_inst|always4~0_combout ; +wire \uart_rx_inst|baud_cnt[0]~13_combout ; +wire \uart_rx_inst|Equal1~0_combout ; +wire \uart_rx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|baud_cnt[2]~17_combout ; +wire \uart_rx_inst|Equal1~1_combout ; +wire \uart_rx_inst|Equal1~3_combout ; +wire \uart_rx_inst|work_en~0_combout ; +wire \uart_rx_inst|work_en~q ; +wire \uart_rx_inst|always5~0_combout ; +wire \uart_rx_inst|baud_cnt[0]~14 ; +wire \uart_rx_inst|baud_cnt[1]~15_combout ; +wire \uart_rx_inst|baud_cnt[1]~16 ; +wire \uart_rx_inst|baud_cnt[2]~18 ; +wire \uart_rx_inst|baud_cnt[3]~19_combout ; +wire \uart_rx_inst|baud_cnt[3]~20 ; +wire \uart_rx_inst|baud_cnt[4]~22 ; +wire \uart_rx_inst|baud_cnt[5]~24 ; +wire \uart_rx_inst|baud_cnt[6]~25_combout ; +wire \uart_rx_inst|baud_cnt[6]~26 ; +wire \uart_rx_inst|baud_cnt[7]~27_combout ; +wire \uart_rx_inst|baud_cnt[7]~28 ; +wire \uart_rx_inst|baud_cnt[8]~29_combout ; +wire \uart_rx_inst|baud_cnt[8]~30 ; +wire \uart_rx_inst|baud_cnt[9]~31_combout ; +wire \uart_rx_inst|baud_cnt[9]~32 ; +wire \uart_rx_inst|baud_cnt[10]~34 ; +wire \uart_rx_inst|baud_cnt[11]~35_combout ; +wire \uart_rx_inst|baud_cnt[11]~36 ; +wire \uart_rx_inst|baud_cnt[12]~37_combout ; +wire \uart_rx_inst|Equal2~1_combout ; +wire \uart_rx_inst|Equal2~2_combout ; +wire \uart_rx_inst|bit_flag~q ; +wire \uart_rx_inst|always4~1_combout ; +wire \uart_rx_inst|rx_flag~q ; +wire \uart_rx_inst|po_flag~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ; +wire \sd_ctrl_inst|comb~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ; +wire \sd_ctrl_inst|comb~0_combout ; +wire \sd_ctrl_inst|comb~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector1~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector1~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux0~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal3~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~4_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~5_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~q ; +wire \sd_ctrl_inst|sd_mosi~0_combout ; +wire \sd_ctrl_inst|sd_mosi~1_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \uart_tx_inst|baud_cnt[0]~13_combout ; +wire \uart_tx_inst|Equal1~0_combout ; +wire \uart_tx_inst|Equal1~1_combout ; +wire \uart_tx_inst|baud_cnt[4]~21_combout ; +wire \uart_tx_inst|Equal1~2_combout ; +wire \uart_tx_inst|Equal1~3_combout ; +wire \uart_tx_inst|always1~0_combout ; +wire \uart_tx_inst|baud_cnt[0]~14 ; +wire \uart_tx_inst|baud_cnt[1]~15_combout ; +wire \uart_tx_inst|baud_cnt[1]~16 ; +wire \uart_tx_inst|baud_cnt[2]~18 ; +wire \uart_tx_inst|baud_cnt[3]~19_combout ; +wire \uart_tx_inst|baud_cnt[3]~20 ; +wire \uart_tx_inst|baud_cnt[4]~22 ; +wire \uart_tx_inst|baud_cnt[5]~24 ; +wire \uart_tx_inst|baud_cnt[6]~25_combout ; +wire \uart_tx_inst|baud_cnt[6]~26 ; +wire \uart_tx_inst|baud_cnt[7]~27_combout ; +wire \uart_tx_inst|baud_cnt[7]~28 ; +wire \uart_tx_inst|baud_cnt[8]~29_combout ; +wire \uart_tx_inst|baud_cnt[8]~30 ; +wire \uart_tx_inst|baud_cnt[9]~31_combout ; +wire \uart_tx_inst|baud_cnt[9]~32 ; +wire \uart_tx_inst|baud_cnt[10]~34 ; +wire \uart_tx_inst|baud_cnt[11]~35_combout ; +wire \uart_tx_inst|baud_cnt[11]~36 ; +wire \uart_tx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal2~0_combout ; +wire \uart_tx_inst|Equal2~1_combout ; +wire \uart_tx_inst|bit_flag~q ; +wire \uart_tx_inst|always3~0_combout ; +wire \uart_tx_inst|always0~1_combout ; +wire \uart_tx_inst|bit_cnt[0]~5_combout ; +wire \uart_tx_inst|bit_cnt[1]~4_combout ; +wire \uart_tx_inst|Add1~0_combout ; +wire \uart_tx_inst|bit_cnt[3]~2_combout ; +wire \data_rw_ctrl_inst|cnt_wait[0]~16_combout ; +wire \data_rw_ctrl_inst|cnt_wait[3]~23 ; +wire \data_rw_ctrl_inst|cnt_wait[4]~24_combout ; +wire \data_rw_ctrl_inst|Equal3~0_combout ; +wire \data_rw_ctrl_inst|rd_busy_dly~q ; +wire \data_rw_ctrl_inst|send_data_num[0]~12_combout ; +wire \data_rw_ctrl_inst|send_data_num[0]~13 ; +wire \data_rw_ctrl_inst|send_data_num[1]~14_combout ; +wire \data_rw_ctrl_inst|send_data_num[1]~15 ; +wire \data_rw_ctrl_inst|send_data_num[2]~16_combout ; +wire \data_rw_ctrl_inst|always3~0_combout ; +wire \data_rw_ctrl_inst|send_data_num[2]~17 ; +wire \data_rw_ctrl_inst|send_data_num[3]~19 ; +wire \data_rw_ctrl_inst|send_data_num[4]~20_combout ; +wire \data_rw_ctrl_inst|send_data_num[4]~21 ; +wire \data_rw_ctrl_inst|send_data_num[5]~23 ; +wire \data_rw_ctrl_inst|send_data_num[6]~25 ; +wire \data_rw_ctrl_inst|send_data_num[7]~26_combout ; +wire \data_rw_ctrl_inst|send_data_num[5]~22_combout ; +wire \data_rw_ctrl_inst|always3~1_combout ; +wire \data_rw_ctrl_inst|always3~3_combout ; +wire \data_rw_ctrl_inst|send_data_en~0_combout ; +wire \data_rw_ctrl_inst|send_data_en~q ; +wire \data_rw_ctrl_inst|Equal3~1_combout ; +wire \data_rw_ctrl_inst|cnt_wait[13]~26_combout ; +wire \data_rw_ctrl_inst|cnt_wait[0]~17 ; +wire \data_rw_ctrl_inst|cnt_wait[1]~18_combout ; +wire \data_rw_ctrl_inst|cnt_wait[1]~19 ; +wire \data_rw_ctrl_inst|cnt_wait[2]~20_combout ; +wire \data_rw_ctrl_inst|cnt_wait[2]~21 ; +wire \data_rw_ctrl_inst|cnt_wait[3]~22_combout ; +wire \data_rw_ctrl_inst|Equal2~3_combout ; +wire \data_rw_ctrl_inst|cnt_wait[4]~25 ; +wire \data_rw_ctrl_inst|cnt_wait[5]~28 ; +wire \data_rw_ctrl_inst|cnt_wait[6]~30 ; +wire \data_rw_ctrl_inst|cnt_wait[7]~31_combout ; +wire \data_rw_ctrl_inst|cnt_wait[7]~32 ; +wire \data_rw_ctrl_inst|cnt_wait[8]~33_combout ; +wire \data_rw_ctrl_inst|cnt_wait[8]~34 ; +wire \data_rw_ctrl_inst|cnt_wait[9]~35_combout ; +wire \data_rw_ctrl_inst|cnt_wait[9]~36 ; +wire \data_rw_ctrl_inst|cnt_wait[10]~37_combout ; +wire \data_rw_ctrl_inst|cnt_wait[10]~38 ; +wire \data_rw_ctrl_inst|cnt_wait[11]~40 ; +wire \data_rw_ctrl_inst|cnt_wait[12]~41_combout ; +wire \data_rw_ctrl_inst|cnt_wait[12]~42 ; +wire \data_rw_ctrl_inst|cnt_wait[13]~44 ; +wire \data_rw_ctrl_inst|cnt_wait[14]~45_combout ; +wire \data_rw_ctrl_inst|cnt_wait[14]~46 ; +wire \data_rw_ctrl_inst|cnt_wait[15]~47_combout ; +wire \data_rw_ctrl_inst|cnt_wait[6]~29_combout ; +wire \data_rw_ctrl_inst|Equal2~0_combout ; +wire \data_rw_ctrl_inst|cnt_wait[13]~43_combout ; +wire \data_rw_ctrl_inst|cnt_wait[11]~39_combout ; +wire \data_rw_ctrl_inst|Equal2~1_combout ; +wire \data_rw_ctrl_inst|Equal2~2_combout ; +wire \data_rw_ctrl_inst|Equal2~4_combout ; +wire \data_rw_ctrl_inst|rd_fifo_rd_en~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_en~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~13_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~14_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~15_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~11_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~7_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~9_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~16_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~6_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~2_combout ; +wire \uart_tx_inst|Mux0~0_combout ; +wire \uart_tx_inst|tx~0_combout ; +wire \uart_tx_inst|tx~q ; +wire [3:0] \sd_ctrl_inst|sd_write_inst|cnt_data_bit ; +wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit ; +wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data_reg ; +wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_ack_bit ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_ack_bit ; +wire [12:0] \uart_tx_inst|baud_cnt ; +wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data ; +wire [2:0] \sd_ctrl_inst|sd_read_inst|cnt_end ; +wire [3:0] \uart_tx_inst|bit_cnt ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|ack_data ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|busy_data ; +wire [3:0] \sd_ctrl_inst|sd_read_inst|cnt_data_bit ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit ; +wire [15:0] \sd_ctrl_inst|sd_read_inst|byte_head ; +wire [11:0] \sd_ctrl_inst|sd_read_inst|cnt_data_num ; +wire [7:0] \sd_ctrl_inst|sd_read_inst|ack_data ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \uart_rx_inst|rx_data ; +wire [7:0] \uart_rx_inst|po_data ; +wire [3:0] \uart_rx_inst|bit_cnt ; +wire [12:0] \uart_rx_inst|baud_cnt ; +wire [11:0] \data_rw_ctrl_inst|send_data_num ; +wire [15:0] \data_rw_ctrl_inst|cnt_wait ; +wire [10:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ; +wire [8:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ; +wire [2:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a ; +wire [15:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ; +wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a ; +wire [2:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a ; +wire [7:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a ; +wire [8:0] \sd_ctrl_inst|sd_init_inst|cnt_wait ; +wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit ; +wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_ack_bit ; +wire [39:0] \sd_ctrl_inst|sd_init_inst|ack_data ; +wire [2:0] \sd_ctrl_inst|sd_write_inst|cnt_end ; +wire [11:0] \sd_ctrl_inst|sd_write_inst|cnt_data_num ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; +wire [17:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; +wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [9]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [10]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [11]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [12]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [13]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [14]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [15]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [16]; + +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 7; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "10000"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 6891; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0] $ (VCC))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # (GND))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .lut_mask = 16'h66DD; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y22_N19 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N13 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N7 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N11 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N13 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y13_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y16_N13 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X13_Y13_N0 +cycloneive_ram_block \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({gnd,\uart_rx_inst|po_data [7],\uart_rx_inst|po_data [6],\uart_rx_inst|po_data [5],\uart_rx_inst|po_data [4],\uart_rx_inst|po_data [3],\uart_rx_inst|po_data [2],\uart_rx_inst|po_data [1],\uart_rx_inst|po_data [0]}), + .portaaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(18'b000000000000000000), + .portbaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_wr_data:fifo_wr_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_uqf1:auto_generated|altsyncram_3011:fifo_ram|ALTSYNCRAM"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 8; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 9; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 18; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 511; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 512; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: M9K_X25_Y27_N0 +cycloneive_ram_block \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({gnd,\sd_ctrl_inst|sd_read_inst|rd_data [15],\sd_ctrl_inst|sd_read_inst|rd_data [14],\sd_ctrl_inst|sd_read_inst|rd_data [13],\sd_ctrl_inst|sd_read_inst|rd_data [12],\sd_ctrl_inst|sd_read_inst|rd_data [11],\sd_ctrl_inst|sd_read_inst|rd_data [10],\sd_ctrl_inst|sd_read_inst|rd_data [9], +\sd_ctrl_inst|sd_read_inst|rd_data [8],gnd,\sd_ctrl_inst|sd_read_inst|rd_data [7],\sd_ctrl_inst|sd_read_inst|rd_data [6],\sd_ctrl_inst|sd_read_inst|rd_data [5],\sd_ctrl_inst|sd_read_inst|rd_data [4],\sd_ctrl_inst|sd_read_inst|rd_data [3],\sd_ctrl_inst|sd_read_inst|rd_data [2], +\sd_ctrl_inst|sd_read_inst|rd_data [1],\sd_ctrl_inst|sd_read_inst|rd_data [0]}), + .portaaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_rd_data:fifo_rd_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_h0f1:auto_generated|altsyncram_4011:fifo_ram|ALTSYNCRAM"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 9; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 18; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 511; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 512; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 8; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: FF_X14_Y25_N11 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N23 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N25 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N27 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N11 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 )) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N25 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y16_N27 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y23_N11 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y23_N7 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h55AA; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N13 +dffeas \uart_tx_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y26_N7 +dffeas \uart_tx_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y26_N23 +dffeas \uart_tx_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout = \sd_ctrl_inst|sd_read_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout = \sd_ctrl_inst|sd_init_inst|cnt_wait [0] $ (VCC) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .lut_mask = 16'h55AA; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N6 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) +// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[1]~16 ), + .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_tx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N12 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[4]~22 ), + .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_tx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N22 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) +// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[9]~32 ), + .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_tx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N11 +dffeas \data_rw_ctrl_inst|cnt_wait[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q $ (GND) +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT = CARRY(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .cout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hAA55; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[5]~27 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[5]~27_combout = (\data_rw_ctrl_inst|cnt_wait [5] & (!\data_rw_ctrl_inst|cnt_wait[4]~25 )) # (!\data_rw_ctrl_inst|cnt_wait [5] & ((\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[5]~28 = CARRY((!\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (!\data_rw_ctrl_inst|cnt_wait [5])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[4]~25 ), + .combout(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[5]~28 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N12 +cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( +// Equation(s): +// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) +// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) + + .dataa(\uart_rx_inst|bit_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~3 ), + .combout(\uart_rx_inst|Add1~4_combout ), + .cout(\uart_rx_inst|Add1~5 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N11 +dffeas \uart_rx_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y16_N23 +dffeas \uart_rx_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N7 +dffeas \data_rw_ctrl_inst|send_data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[3]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N13 +dffeas \data_rw_ctrl_inst|send_data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[6]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N17 +dffeas \data_rw_ctrl_inst|send_data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[8]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N19 +dffeas \data_rw_ctrl_inst|send_data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[9]~30_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N21 +dffeas \data_rw_ctrl_inst|send_data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[10]~32_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[10] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N23 +dffeas \data_rw_ctrl_inst|send_data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[11]~34_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [11]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[11] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N10 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) +// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[3]~20 ), + .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_rx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N22 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) +// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[9]~32 ), + .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_rx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[3]~18 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[3]~18_combout = (\data_rw_ctrl_inst|send_data_num [3] & (!\data_rw_ctrl_inst|send_data_num[2]~17 )) # (!\data_rw_ctrl_inst|send_data_num [3] & ((\data_rw_ctrl_inst|send_data_num[2]~17 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[3]~19 = CARRY((!\data_rw_ctrl_inst|send_data_num[2]~17 ) # (!\data_rw_ctrl_inst|send_data_num [3])) + + .dataa(\data_rw_ctrl_inst|send_data_num [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[2]~17 ), + .combout(\data_rw_ctrl_inst|send_data_num[3]~18_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[3]~19 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[3]~18 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|send_data_num[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[6]~24 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[6]~24_combout = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num[5]~23 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [6] & (!\data_rw_ctrl_inst|send_data_num[5]~23 & VCC)) +// \data_rw_ctrl_inst|send_data_num[6]~25 = CARRY((\data_rw_ctrl_inst|send_data_num [6] & !\data_rw_ctrl_inst|send_data_num[5]~23 )) + + .dataa(\data_rw_ctrl_inst|send_data_num [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[5]~23 ), + .combout(\data_rw_ctrl_inst|send_data_num[6]~24_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[6]~25 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[6]~24 .lut_mask = 16'hA50A; +defparam \data_rw_ctrl_inst|send_data_num[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[7]~26 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[7]~26_combout = (\data_rw_ctrl_inst|send_data_num [7] & (!\data_rw_ctrl_inst|send_data_num[6]~25 )) # (!\data_rw_ctrl_inst|send_data_num [7] & ((\data_rw_ctrl_inst|send_data_num[6]~25 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[7]~27 = CARRY((!\data_rw_ctrl_inst|send_data_num[6]~25 ) # (!\data_rw_ctrl_inst|send_data_num [7])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [7]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[6]~25 ), + .combout(\data_rw_ctrl_inst|send_data_num[7]~26_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[7]~27 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[7]~26 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|send_data_num[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[8]~28 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[8]~28_combout = (\data_rw_ctrl_inst|send_data_num [8] & (\data_rw_ctrl_inst|send_data_num[7]~27 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num[7]~27 & VCC)) +// \data_rw_ctrl_inst|send_data_num[8]~29 = CARRY((\data_rw_ctrl_inst|send_data_num [8] & !\data_rw_ctrl_inst|send_data_num[7]~27 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [8]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[7]~27 ), + .combout(\data_rw_ctrl_inst|send_data_num[8]~28_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[8]~29 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[8]~28 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[9]~30 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[9]~30_combout = (\data_rw_ctrl_inst|send_data_num [9] & (!\data_rw_ctrl_inst|send_data_num[8]~29 )) # (!\data_rw_ctrl_inst|send_data_num [9] & ((\data_rw_ctrl_inst|send_data_num[8]~29 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[9]~31 = CARRY((!\data_rw_ctrl_inst|send_data_num[8]~29 ) # (!\data_rw_ctrl_inst|send_data_num [9])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [9]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[8]~29 ), + .combout(\data_rw_ctrl_inst|send_data_num[9]~30_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[9]~31 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[9]~30 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|send_data_num[9]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[10]~32 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[10]~32_combout = (\data_rw_ctrl_inst|send_data_num [10] & (\data_rw_ctrl_inst|send_data_num[9]~31 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num[9]~31 & VCC)) +// \data_rw_ctrl_inst|send_data_num[10]~33 = CARRY((\data_rw_ctrl_inst|send_data_num [10] & !\data_rw_ctrl_inst|send_data_num[9]~31 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [10]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[9]~31 ), + .combout(\data_rw_ctrl_inst|send_data_num[10]~32_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[10]~33 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[10]~32 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[10]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[11]~34 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[11]~34_combout = \data_rw_ctrl_inst|send_data_num [11] $ (\data_rw_ctrl_inst|send_data_num[10]~33 ) + + .dataa(\data_rw_ctrl_inst|send_data_num [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|send_data_num[10]~33 ), + .combout(\data_rw_ctrl_inst|send_data_num[11]~34_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[11]~34 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|send_data_num[11]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y23_N27 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_end [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~0_combout = (\sd_ctrl_inst|sd_init_inst|init_end~q & \data_rw_ctrl_inst|rd_en~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datad(\data_rw_ctrl_inst|rd_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal6~0_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .lut_mask = 16'h0303; +defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_write_inst|always4~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]), + .datad(\sd_ctrl_inst|sd_write_inst|always4~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~1 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_write_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_write_inst|always4~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~1_combout = (\sd_ctrl_inst|sd_write_inst|mosi~0_combout & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .lut_mask = 16'h0002; +defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux0~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & +// (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .lut_mask = 16'h0026; +defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]) # ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5])))) # +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .lut_mask = 16'hB9A8; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~1_combout = (\sd_ctrl_inst|sd_write_inst|Mux1~0_combout & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]) # ((!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~0_combout & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]), + .datab(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .lut_mask = 16'hB8CC; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~2_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b +// [14]))))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .lut_mask = 16'hEE30; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~3_combout = (\sd_ctrl_inst|sd_write_inst|Mux1~2_combout & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]))) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~2_combout & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .lut_mask = 16'hEA62; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~4_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b +// [15])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .lut_mask = 16'hDC98; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~5_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]))) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~4_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .lut_mask = 16'hF838; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~6_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & +// ((\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|Mux1~5_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .lut_mask = 16'hF2C2; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~7_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] & !\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .lut_mask = 16'hCCB8; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~8_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0])) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~7_combout & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]))))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]), + .datad(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .lut_mask = 16'hBBC0; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~6_combout = (\sd_ctrl_inst|sd_write_inst|Mux1~6_combout & (((\sd_ctrl_inst|sd_write_inst|Mux1~8_combout )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) # (!\sd_ctrl_inst|sd_write_inst|Mux1~6_combout & +// (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|Mux1~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .datac(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .lut_mask = 16'hE6A2; +defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~7_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]) # ((\sd_ctrl_inst|sd_write_inst|mosi~0_combout & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_write_inst|mosi~6_combout )) # +// (!\sd_ctrl_inst|sd_write_inst|mosi~0_combout & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]) # (\sd_ctrl_inst|sd_write_inst|mosi~6_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .datad(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .lut_mask = 16'hFDF4; +defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~1_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .lut_mask = 16'h1906; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~2_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & +// (\sd_ctrl_inst|sd_init_inst|Selector14~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .lut_mask = 16'h5044; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr14~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & +// ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .lut_mask = 16'h9998; +defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~3_combout = ((\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .lut_mask = 16'h0CFF; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~4_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & +// (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .lut_mask = 16'h11E0; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~5_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & !\sd_ctrl_inst|sd_init_inst|Selector14~4_combout )) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|Selector14~4_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .lut_mask = 16'h0108; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~6_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] $ (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .lut_mask = 16'h0902; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~7_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~6_combout & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .lut_mask = 16'h8100; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr12~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .lut_mask = 16'h5F60; +defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~8_combout = ((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]))) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .lut_mask = 16'h10FF; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~9_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~5_combout & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # ((\sd_ctrl_inst|sd_init_inst|Selector14~8_combout )))) # +// (!\sd_ctrl_inst|sd_init_inst|Selector14~5_combout & (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector14~8_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .lut_mask = 16'hA8FC; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~10_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~9_combout & (\sd_ctrl_inst|sd_init_inst|Selector14~3_combout & ((\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ) # +// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .lut_mask = 16'hC400; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N15 +dffeas \uart_tx_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[2]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N10 +cycloneive_lcell_comb \uart_tx_inst|always0~0 ( +// Equation(s): +// \uart_tx_inst|always0~0_combout = (!\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|bit_cnt [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~0 .lut_mask = 16'h000F; +defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N30 +cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( +// Equation(s): +// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b +// [4]))) # (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF2C2; +defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N24 +cycloneive_lcell_comb \uart_tx_inst|Mux0~2 ( +// Equation(s): +// \uart_tx_inst|Mux0~2_combout = (\uart_tx_inst|Mux0~1_combout & (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6])) # (!\uart_tx_inst|bit_cnt [1]))) # (!\uart_tx_inst|Mux0~1_combout & +// (\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]))) + + .dataa(\uart_tx_inst|Mux0~1_combout ), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~2 .lut_mask = 16'hEA62; +defparam \uart_tx_inst|Mux0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N26 +cycloneive_lcell_comb \uart_tx_inst|Mux0~3 ( +// Equation(s): +// \uart_tx_inst|Mux0~3_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\uart_tx_inst|bit_cnt [1] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]))))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~3 .lut_mask = 16'h88C0; +defparam \uart_tx_inst|Mux0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N28 +cycloneive_lcell_comb \uart_tx_inst|Mux0~4 ( +// Equation(s): +// \uart_tx_inst|Mux0~4_combout = (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] & \uart_tx_inst|bit_cnt [1])) + + .dataa(gnd), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~4 .lut_mask = 16'h3000; +defparam \uart_tx_inst|Mux0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N22 +cycloneive_lcell_comb \uart_tx_inst|Mux0~5 ( +// Equation(s): +// \uart_tx_inst|Mux0~5_combout = (\uart_tx_inst|bit_cnt [2] & (((\uart_tx_inst|Mux0~2_combout )))) # (!\uart_tx_inst|bit_cnt [2] & ((\uart_tx_inst|Mux0~3_combout ) # ((\uart_tx_inst|Mux0~4_combout )))) + + .dataa(\uart_tx_inst|Mux0~3_combout ), + .datab(\uart_tx_inst|Mux0~4_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|Mux0~2_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~5 .lut_mask = 16'hFE0E; +defparam \uart_tx_inst|Mux0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q & (\sd_ctrl_inst|sd_read_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0]))))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [2]), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .lut_mask = 16'h7800; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_read_inst|always3~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datad(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~1 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_read_inst|always3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N7 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~2_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [9])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~2 .lut_mask = 16'h0003; +defparam \sd_ctrl_inst|sd_read_inst|always3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .lut_mask = 16'hC33C; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .lut_mask = 16'hC33C; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal1~0_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector8~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector8~0_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [32] & (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout & (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector0~0_combout = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q & (\sd_ctrl_inst|sd_init_inst|Equal5~2_combout & ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q & +// ((\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout & \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .lut_mask = 16'hDC50; +defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal3~0_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [10] & (!\sd_ctrl_inst|sd_init_inst|ack_data [9] & (!\sd_ctrl_inst|sd_init_inst|ack_data [11] & \sd_ctrl_inst|sd_init_inst|ack_data [8]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [10]), + .datab(\sd_ctrl_inst|sd_init_inst|ack_data [9]), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [11]), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .lut_mask = 16'hFC00; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~1_combout = (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & ((\sd_ctrl_inst|sd_init_inst|ack_data [32]) # ((!\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_init_inst|Equal2~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .lut_mask = 16'hB0F0; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # +// (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & ((!\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .lut_mask = 16'hA0EC; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~3_combout = (\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & ((\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector6~1_combout +// )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .lut_mask = 16'hFECC; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~1_combout = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]) # ((!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .lut_mask = 16'hBF00; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal3~1_combout = (!\sd_ctrl_inst|sd_read_inst|ack_data [0] & (!\sd_ctrl_inst|sd_read_inst|ack_data [1] & (!\sd_ctrl_inst|sd_read_inst|ack_data [3] & !\sd_ctrl_inst|sd_read_inst|ack_data [2]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|ack_data [0]), + .datab(\sd_ctrl_inst|sd_read_inst|ack_data [1]), + .datac(\sd_ctrl_inst|sd_read_inst|ack_data [3]), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal3~1_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .lut_mask = 16'h0002; +defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal3~2_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|Equal3~1_combout & \sd_ctrl_inst|sd_write_inst|Equal3~0_combout )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .lut_mask = 16'h8800; +defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N13 +dffeas \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector2~0_combout = (\sd_ctrl_inst|sd_write_inst|Equal1~1_combout & (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout & \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Add3~0_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .lut_mask = 16'h78F0; +defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y14_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEDB7; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y14_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y15_N17 +dffeas \uart_rx_inst|po_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y15_N19 +dffeas \uart_rx_inst|po_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N21 +dffeas \uart_rx_inst|po_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N15 +dffeas \uart_rx_inst|po_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N9 +dffeas \uart_rx_inst|po_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N27 +dffeas \uart_rx_inst|po_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N13 +dffeas \uart_rx_inst|po_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N31 +dffeas \uart_rx_inst|po_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y27_N21 +dffeas \uart_tx_inst|work_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_tx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N6 +cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( +// Equation(s): +// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(gnd), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h3CF0; +defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N14 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~3 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[2]~3_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) + + .dataa(\uart_tx_inst|Add1~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2]~3 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N11 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y25_N31 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y24_N15 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~1_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head [0] & (\sd_ctrl_inst|sd_read_inst|byte_head [2] & (\sd_ctrl_inst|sd_read_inst|byte_head [1] & \sd_ctrl_inst|sd_read_inst|byte_head [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [2]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .lut_mask = 16'h000A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector3~0_combout = (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q & ((!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .lut_mask = 16'h3F00; +defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector3~1_combout = (\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_write_inst|Equal3~2_combout & \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q )) + + .dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .lut_mask = 16'hFFA0; +defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y14_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y14_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y15_N1 +dffeas \uart_rx_inst|rx_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N11 +dffeas \uart_rx_inst|rx_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N29 +dffeas \uart_rx_inst|rx_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N23 +dffeas \uart_rx_inst|rx_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y16_N27 +dffeas \uart_rx_inst|rx_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[7]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N25 +dffeas \uart_rx_inst|rx_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N3 +dffeas \uart_rx_inst|rx_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N5 +dffeas \uart_rx_inst|rx_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y27_N13 +dffeas \data_rw_ctrl_inst|tx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|tx_flag~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|tx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|tx_flag .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|tx_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N20 +cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( +// Equation(s): +// \uart_tx_inst|work_en~0_combout = (\data_rw_ctrl_inst|tx_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) + + .dataa(\data_rw_ctrl_inst|tx_flag~q ), + .datab(gnd), + .datac(\uart_tx_inst|work_en~q ), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hAAFA; +defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y28_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N1 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y27_N27 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y27_N23 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y27_N31 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~4_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [2]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [2]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~5_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [1]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~6_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [0] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~7_combout = (\sd_miso~input_o & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_miso~input_o ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_en~0_combout = (!\sd_miso~input_o & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q & \sd_ctrl_inst|sd_init_inst|miso_dly~q ))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .datac(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_en~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & \sd_ctrl_inst|sd_write_inst|ack_en~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N13 +dffeas \uart_rx_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N20 +cycloneive_lcell_comb \uart_rx_inst|always8~0 ( +// Equation(s): +// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always8~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8282; +defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N31 +dffeas \uart_rx_inst|rx_reg3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg3 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & !\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y16_N8 +cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( +// Equation(s): +// \uart_rx_inst|Equal2~0_combout = (!\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt [2] & \uart_rx_inst|baud_cnt [3]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0400; +defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y10_N1 +dffeas \uart_rx_inst|rx_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~2 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~2_combout = (\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num [11] & !\data_rw_ctrl_inst|send_data_num [9]))) + + .dataa(\data_rw_ctrl_inst|send_data_num [8]), + .datab(\data_rw_ctrl_inst|send_data_num [10]), + .datac(\data_rw_ctrl_inst|send_data_num [11]), + .datad(\data_rw_ctrl_inst|send_data_num [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~2 .lut_mask = 16'h0002; +defparam \data_rw_ctrl_inst|always3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N30 +cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( +// Equation(s): +// \uart_rx_inst|Equal1~2_combout = (\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [9]))) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [6]), + .datad(\uart_rx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y10_N3 +dffeas \uart_rx_inst|rx_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y16_N7 +dffeas \uart_rx_inst|start_nedge ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|start_nedge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; +defparam \uart_rx_inst|start_nedge .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N6 +cycloneive_lcell_comb \uart_rx_inst|always3~0 ( +// Equation(s): +// \uart_rx_inst|always3~0_combout = (!\uart_rx_inst|rx_reg3~q & \uart_rx_inst|rx_reg2~q ) + + .dataa(\uart_rx_inst|rx_reg3~q ), + .datab(gnd), + .datac(\uart_rx_inst|rx_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always3~0 .lut_mask = 16'h5050; +defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h0F0F; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N26 +cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( +// Equation(s): +// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|rx_reg3~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h0F0F; +defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y10_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( +// Equation(s): +// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rx~input_o ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \rx~input ( + .i(rx), + .ibar(gnd), + .o(\rx~input_o )); +// synopsys translate_off +defparam \rx~input .bus_hold = "false"; +defparam \rx~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y14_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|tx_flag~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|tx_flag~feeder_combout = \data_rw_ctrl_inst|rd_fifo_rd_en~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|tx_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|tx_flag~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|tx_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y14_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N16 +cycloneive_lcell_comb \uart_rx_inst|po_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[1]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N18 +cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N4 +cycloneive_lcell_comb \uart_rx_inst|rx_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[4]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N20 +cycloneive_lcell_comb \uart_rx_inst|po_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[6]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N10 +cycloneive_lcell_comb \uart_rx_inst|rx_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[5]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N8 +cycloneive_lcell_comb \uart_rx_inst|po_data[7]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[7]~feeder_combout = \uart_rx_inst|rx_data [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [7]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N28 +cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[6]~feeder_combout = \uart_rx_inst|rx_data [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [7]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N26 +cycloneive_lcell_comb \uart_rx_inst|po_data[3]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[3]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N22 +cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N12 +cycloneive_lcell_comb \uart_rx_inst|po_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[0]~feeder_combout = \uart_rx_inst|rx_data [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [0]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y10_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg1~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N23 +cycloneive_io_obuf \sd_clk~output ( + .i(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sd_clk), + .obar()); +// synopsys translate_off +defparam \sd_clk~output .bus_hold = "false"; +defparam \sd_clk~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N23 +cycloneive_io_obuf \sd_cs_n~output ( + .i(\sd_ctrl_inst|sd_cs_n~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sd_cs_n), + .obar()); +// synopsys translate_off +defparam \sd_cs_n~output .bus_hold = "false"; +defparam \sd_cs_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y29_N9 +cycloneive_io_obuf \sd_mosi~output ( + .i(\sd_ctrl_inst|sd_mosi~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sd_mosi), + .obar()); +// synopsys translate_off +defparam \sd_mosi~output .bus_hold = "false"; +defparam \sd_mosi~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y9_N16 +cycloneive_io_obuf \tx~output ( + .i(!\uart_tx_inst|tx~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tx), + .obar()); +// synopsys translate_off +defparam \tx~output .bus_hold = "false"; +defparam \tx~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout = \sd_ctrl_inst|sd_read_inst|cnt_data_num [0] $ (VCC) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y1_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y1_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y1_N26 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ) # (!\sys_rst_n~input_o )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\sys_rst_n~input_o ), + .datac(gnd), + .datad(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h77FF; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N29 +cycloneive_io_ibuf \sd_miso~input ( + .i(sd_miso), + .ibar(gnd), + .o(\sd_miso~input_o )); +// synopsys translate_off +defparam \sd_miso~input .bus_hold = "false"; +defparam \sd_miso~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X16_Y24_N25 +dffeas \sd_ctrl_inst|sd_init_inst|miso_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_miso~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|miso_dly .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|miso_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_en~0_combout = (!\sd_miso~input_o & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q & (\sd_ctrl_inst|sd_init_inst|miso_dly~q & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .lut_mask = 16'h0040; +defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N13 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_en~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|ack_en~0_combout & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .datab(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .lut_mask = 16'h0004; +defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N11 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal0~1_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_en~2_combout = (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout & (!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout & ((\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_read_inst|ack_en~q )))) # +// (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout & (((\sd_ctrl_inst|sd_read_inst|ack_en~q )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .lut_mask = 16'h50F8; +defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N3 +dffeas \sd_ctrl_inst|sd_read_inst|ack_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y24_N9 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N15 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N17 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N21 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N23 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal0~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout & \sd_ctrl_inst|sd_read_inst|ack_en~q )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .lut_mask = 16'h5000; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N23 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N29 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout = \sd_ctrl_inst|sd_read_inst|ack_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N19 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N25 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout = \sd_ctrl_inst|sd_read_inst|ack_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N31 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N21 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout = \sd_ctrl_inst|sd_read_inst|ack_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N27 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N17 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal3~0_combout = (!\sd_ctrl_inst|sd_read_inst|ack_data [6] & (!\sd_ctrl_inst|sd_read_inst|ack_data [5] & (!\sd_ctrl_inst|sd_read_inst|ack_data [7] & !\sd_ctrl_inst|sd_read_inst|ack_data [4]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|ack_data [6]), + .datab(\sd_ctrl_inst|sd_read_inst|ack_data [5]), + .datac(\sd_ctrl_inst|sd_read_inst|ack_data [7]), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal3~2_combout = (\sd_ctrl_inst|sd_read_inst|Equal3~1_combout & \sd_ctrl_inst|sd_read_inst|Equal3~0_combout ) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N9 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_en~0_combout = (!\sd_miso~input_o & (\sd_ctrl_inst|sd_init_inst|miso_dly~q & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .lut_mask = 16'h0004; +defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_en~1_combout = (!\sd_ctrl_inst|sd_init_inst|Equal6~2_combout & ((\sd_ctrl_inst|sd_init_inst|ack_en~q ) # ((\sd_ctrl_inst|sd_init_inst|ack_en~0_combout & \sd_ctrl_inst|sd_init_inst|Equal1~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .lut_mask = 16'h5450; +defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N3 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal1~1_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~0_combout & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3])) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .lut_mask = 16'h000A; +defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal1~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~1_combout & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout = (\sd_ctrl_inst|sd_init_inst|ack_en~q & (((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .lut_mask = 16'h04CC; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 )) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout = (\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .lut_mask = 16'h000C; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N21 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N19 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N23 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N3 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N31 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N27 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N15 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N5 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N1 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N25 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N13 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N7 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [10]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [11] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [11]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N11 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [12] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [12]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N29 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [13] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [14] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [14]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N9 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [15] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [15]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[16] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [16]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[17] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [16]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [17]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [17] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [17]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N19 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[18] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [18]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [18] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [18]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N25 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[19] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [19]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [19] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [19]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N23 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[20] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [20]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[21] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [20]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [21]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[22] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [21]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [22]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [22] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [22]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[23] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [23]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [23] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [23]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[24] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [24]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [24] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [24]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N29 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[25] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [25]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [25] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [25]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N27 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[26] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [26]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N9 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[27] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [26]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [27]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N31 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[28] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [27]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [28]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N21 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[29] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [28]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [29]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [29] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [29]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N3 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[30] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [30]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [30] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [30]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[31] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [31]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[32] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [31]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [32] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N29 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[33] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [33]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [33] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N25 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[34] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [34]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[35] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [34]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [35]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal2~1_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [34] & (!\sd_ctrl_inst|sd_init_inst|ack_data [35] & !\sd_ctrl_inst|sd_init_inst|ack_data [33])) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [34]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [35]), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .lut_mask = 16'h0005; +defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[36] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [35]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [36]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [36] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [36]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N3 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[37] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [37]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [37] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[38] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [38]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N21 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[39] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [38]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [39]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal2~0_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [36] & (!\sd_ctrl_inst|sd_init_inst|ack_data [38] & (!\sd_ctrl_inst|sd_init_inst|ack_data [39] & !\sd_ctrl_inst|sd_init_inst|ack_data [37]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [36]), + .datab(\sd_ctrl_inst|sd_init_inst|ack_data [38]), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [39]), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal2~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout & (\sd_ctrl_inst|sd_init_inst|ack_data [32] & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector0~1_combout = (\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .lut_mask = 16'hAAEA; +defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N19 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N21 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 )) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N25 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout = \sd_ctrl_inst|sd_init_inst|cnt_wait [8] $ (!\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .lut_mask = 16'hA5A5; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N27 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N23 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal0~1_combout = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [5]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .lut_mask = 16'h7FFF; +defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal0~2_combout = (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout & (\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .lut_mask = 16'h0030; +defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N17 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N13 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal0~0_combout = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [1]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [0]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .lut_mask = 16'h7FFF; +defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.IDLE~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q ) # ((\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .lut_mask = 16'hF0F2; +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N9 +dffeas \sd_ctrl_inst|sd_init_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|Selector8~0_combout & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .lut_mask = 16'hFAF0; +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N27 +dffeas \sd_ctrl_inst|sd_init_inst|state.INIT_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr18 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|WideOr18~combout = (\sd_ctrl_inst|sd_init_inst|Selector14~0_combout & !\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .lut_mask = 16'h0C0C; +defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N21 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N23 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal5~1_combout = ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .lut_mask = 16'hFDFF; +defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout = ((!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout & !\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .lut_mask = 16'h333F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N9 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal5~0_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .lut_mask = 16'hFFFE; +defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal5~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .lut_mask = 16'hFFF0; +defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector2~0_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & +// ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .lut_mask = 16'h50DC; +defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N27 +dffeas \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector1~0_combout = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & (((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & +// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .lut_mask = 16'hF444; +defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector1~1_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & ((\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # +// (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .lut_mask = 16'hF888; +defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N19 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector5~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector5~0_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & +// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .lut_mask = 16'h50DC; +defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector4~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # +// (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .lut_mask = 16'h22F2; +defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector7~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector7~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # +// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .lut_mask = 16'h22F2; +defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N25 +dffeas \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~0_combout = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q & (!\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector3~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .lut_mask = 16'hFC00; +defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector3~1_combout = (\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal2~2_combout & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .lut_mask = 16'hECCC; +defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector15~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ) # (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .lut_mask = 16'hFFFE; +defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector15~1_combout = (!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout & (!\sd_ctrl_inst|sd_init_inst|Equal5~1_combout & \sd_ctrl_inst|sd_init_inst|Selector15~0_combout )) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .lut_mask = 16'h1010; +defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector15~2_combout = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q & ((\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ) # (!\sd_ctrl_inst|sd_init_inst|Selector14~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .lut_mask = 16'hFABA; +defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|init_end ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|init_end .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|init_end .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~2_combout = (\data_rw_ctrl_inst|rd_en~q & (\sd_ctrl_inst|sd_init_inst|init_end~q & !\sd_ctrl_inst|sd_read_inst|state.IDLE~q )) + + .dataa(\data_rw_ctrl_inst|rd_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .lut_mask = 16'h00A0; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~3_combout = (\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ) # ((\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ) # ((!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout & \sd_ctrl_inst|sd_read_inst|Selector2~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .lut_mask = 16'hFBFA; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N17 +dffeas \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N5 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N9 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N15 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N17 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal2~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .lut_mask = 16'h0040; +defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N7 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal2~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .lut_mask = 16'hA000; +defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector3~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|Equal2~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal2~0_combout & \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector3~1_combout = (\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q & ((!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .lut_mask = 16'hDCFC; +defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N9 +dffeas \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector2~0_combout = (\sd_ctrl_inst|sd_read_inst|Equal0~1_combout & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q & \sd_ctrl_inst|sd_read_inst|Equal0~0_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .lut_mask = 16'h8080; +defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector2~1_combout = (\sd_ctrl_inst|sd_read_inst|Equal3~2_combout & ((\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ) # ((!\sd_ctrl_inst|sd_read_inst|always3~4_combout & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # +// (!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout & (!\sd_ctrl_inst|sd_read_inst|always3~4_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .lut_mask = 16'hBA30; +defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N29 +dffeas \sd_ctrl_inst|sd_read_inst|state.RD_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N13 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N7 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout = (\sd_ctrl_inst|sd_read_inst|always3~2_combout & (\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout & (\sd_ctrl_inst|sd_read_inst|always3~0_combout & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .lut_mask = 16'h0080; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .lut_mask = 16'h0048; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Add3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Add3~0_combout = \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .lut_mask = 16'h5FA0; +defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (\sd_ctrl_inst|sd_read_inst|Add3~0_combout & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .lut_mask = 16'h00A0; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal9~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal9~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .lut_mask = 16'hA000; +defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~11_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [11]), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N31 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~10_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [12]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [12]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N29 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~9_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [13]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N27 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~8_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [14]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N17 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~2_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [12] & (\sd_ctrl_inst|sd_read_inst|byte_head [13] & (\sd_ctrl_inst|sd_read_inst|byte_head [14] & \sd_ctrl_inst|sd_read_inst|byte_head [15]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [12]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [13]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [15]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~14_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [8] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [8]), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N23 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~13_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [9]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [9]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~12_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [10]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [10]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N11 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~15_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [7]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [7]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N3 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~3_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [9] & (\sd_ctrl_inst|sd_read_inst|byte_head [10] & (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head [8]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [9]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [10]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [11]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~4_combout = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout = (!\sd_ctrl_inst|sd_read_inst|Equal6~4_combout & ((\sd_ctrl_inst|sd_read_inst|byte_head_en~q ) # ((\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout & \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout +// )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .lut_mask = 16'h00F8; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N15 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~1_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [5] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [5]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .lut_mask = 16'h8888; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N27 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~0_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [6]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N9 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~3_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [3] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [3]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .lut_mask = 16'h8888; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N23 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~2_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [4]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [4]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N13 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~0_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [4] & (\sd_ctrl_inst|sd_read_inst|byte_head [7] & (\sd_ctrl_inst|sd_read_inst|byte_head [6] & \sd_ctrl_inst|sd_read_inst|byte_head [5]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [4]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [7]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3])))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .lut_mask = 16'h0028; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N1 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ) # ((\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))) # +// (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .lut_mask = 16'hFDF5; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N9 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N15 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N17 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N21 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~3_combout = (\sd_ctrl_inst|sd_read_inst|always3~2_combout & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~3 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|always3~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~4_combout = (\sd_ctrl_inst|sd_read_inst|always3~1_combout & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_read_inst|always3~3_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|always3~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~4 .lut_mask = 16'h8800; +defparam \sd_ctrl_inst|sd_read_inst|always3~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector4~0_combout = (\sd_ctrl_inst|sd_read_inst|Selector0~0_combout & (\sd_ctrl_inst|sd_read_inst|always3~4_combout & ((\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout & +// ((\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # ((\sd_ctrl_inst|sd_read_inst|always3~4_combout & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .lut_mask = 16'hDC50; +defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N23 +dffeas \sd_ctrl_inst|sd_read_inst|state.RD_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_end [0] & \sd_ctrl_inst|sd_read_inst|state.RD_END~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N21 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q & (\sd_ctrl_inst|sd_read_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_end [1]))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .lut_mask = 16'h3C00; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N31 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector0~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_end [2] & (\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [2]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .lut_mask = 16'hA000; +defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector0~1_combout = (\sd_ctrl_inst|sd_read_inst|Selector1~0_combout & (((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q )) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|sd_read_inst|Selector1~0_combout +// & (\sd_ctrl_inst|sd_read_inst|state.IDLE~q & ((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .lut_mask = 16'h32FA; +defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N3 +dffeas \sd_ctrl_inst|sd_read_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_num [0] $ (VCC) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout = \sd_ctrl_inst|sd_init_inst|miso_dly~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y23_N1 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N3 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N5 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N9 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y23_N13 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal1~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal1~1_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_en~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout & (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout & ((\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_write_inst|ack_en~q )))) # +// (!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout & (((\sd_ctrl_inst|sd_write_inst|ack_en~q )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .lut_mask = 16'h30F8; +defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y23_N29 +dffeas \sd_ctrl_inst|sd_write_inst|ack_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|ack_en~q & \sd_ctrl_inst|sd_write_inst|Equal1~0_combout )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .lut_mask = 16'h4400; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N23 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N29 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout = \sd_ctrl_inst|sd_write_inst|ack_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N19 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N25 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal4~1_combout = (!\sd_ctrl_inst|sd_write_inst|ack_data [0] & (!\sd_ctrl_inst|sd_write_inst|ack_data [1] & (!\sd_ctrl_inst|sd_write_inst|ack_data [3] & !\sd_ctrl_inst|sd_write_inst|ack_data [2]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|ack_data [0]), + .datab(\sd_ctrl_inst|sd_write_inst|ack_data [1]), + .datac(\sd_ctrl_inst|sd_write_inst|ack_data [3]), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout = \sd_ctrl_inst|sd_write_inst|ack_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N31 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N21 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout = \sd_ctrl_inst|sd_write_inst|ack_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N27 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N1 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal4~0_combout = (!\sd_ctrl_inst|sd_write_inst|ack_data [6] & (!\sd_ctrl_inst|sd_write_inst|ack_data [5] & (!\sd_ctrl_inst|sd_write_inst|ack_data [7] & !\sd_ctrl_inst|sd_write_inst|ack_data [4]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|ack_data [6]), + .datab(\sd_ctrl_inst|sd_write_inst|ack_data [5]), + .datac(\sd_ctrl_inst|sd_write_inst|ack_data [7]), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal4~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal4~1_combout & \sd_ctrl_inst|sd_write_inst|Equal4~0_combout ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .lut_mask = 16'hCC00; +defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector2~1_combout = (\sd_ctrl_inst|sd_write_inst|Selector2~0_combout & ((\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ) # ((!\sd_ctrl_inst|sd_write_inst|always4~3_combout & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))) +// # (!\sd_ctrl_inst|sd_write_inst|Selector2~0_combout & (!\sd_ctrl_inst|sd_write_inst|always4~3_combout & (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .lut_mask = 16'hBA30; +defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N1 +dffeas \sd_ctrl_inst|sd_write_inst|state.WR_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y13_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Add3~2_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y13_N21 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Add3~1_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .lut_mask = 16'h3CF0; +defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y13_N3 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit +// [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .lut_mask = 16'hFF0F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X10_Y16_N5 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N9 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N19 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N21 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N25 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N27 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N23 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~2 .lut_mask = 16'h0002; +defparam \sd_ctrl_inst|sd_write_inst|always4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~3_combout = (\sd_ctrl_inst|sd_write_inst|always4~1_combout & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~2_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|always4~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_write_inst|always4~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~3 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|always4~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector4~0_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q & ((\sd_ctrl_inst|sd_write_inst|always4~3_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout )))) # +// (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q & (((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .lut_mask = 16'h88F8; +defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N17 +dffeas \sd_ctrl_inst|sd_write_inst|state.WR_BUSY ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~8_combout = (\sd_miso~input_o & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(\sd_miso~input_o ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N27 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~7_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [0]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N9 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~6_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [1] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [1]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N31 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~5_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N13 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal6~1_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & (\sd_ctrl_inst|sd_write_inst|busy_data [1] & (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|busy_data [3]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|busy_data [0]), + .datab(\sd_ctrl_inst|sd_write_inst|busy_data [1]), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]), + .datad(\sd_ctrl_inst|sd_write_inst|busy_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~4_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [3] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(\sd_ctrl_inst|sd_write_inst|busy_data [3]), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N25 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~3_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|busy_data [4]), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .lut_mask = 16'hCC00; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N15 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~2_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [5] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [5]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N5 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~1_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N19 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal6~0_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & (\sd_ctrl_inst|sd_write_inst|busy_data [5] & (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|busy_data [7]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|busy_data [4]), + .datab(\sd_ctrl_inst|sd_write_inst|busy_data [5]), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]), + .datad(\sd_ctrl_inst|sd_write_inst|busy_data [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal6~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal6~1_combout & \sd_ctrl_inst|sd_write_inst|Equal6~0_combout ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .lut_mask = 16'hCC00; +defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector5~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector5~0_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & ((\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_END~q & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) # +// (!\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & (((\sd_ctrl_inst|sd_write_inst|state.WR_END~q & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .datab(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .lut_mask = 16'h88F8; +defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N5 +dffeas \sd_ctrl_inst|sd_write_inst|state.WR_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_end [1]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .lut_mask = 16'h5A00; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|state.WR_END~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N23 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q & (\sd_ctrl_inst|sd_write_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [1]))))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [2]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .lut_mask = 16'h7800; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N29 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_end [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector0~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_end [1] & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [2])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_end [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cs_n~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cs_n~0_combout = (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout & ((\sd_ctrl_inst|comb~2_combout ) # (\sd_ctrl_inst|sd_write_inst|cs_n~q ))) + + .dataa(\sd_ctrl_inst|comb~2_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .lut_mask = 16'h00FA; +defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N3 +dffeas \sd_ctrl_inst|sd_write_inst|cs_n ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cs_n~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cs_n .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cs_n .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector0~1_combout = (\sd_ctrl_inst|comb~2_combout & (((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q )) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|comb~2_combout & +// (\sd_ctrl_inst|sd_write_inst|state.IDLE~q & ((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q ) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) + + .dataa(\sd_ctrl_inst|comb~2_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .lut_mask = 16'h32FA; +defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N9 +dffeas \sd_ctrl_inst|sd_write_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_dly~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|wr_busy_dly~feeder_combout = \sd_ctrl_inst|sd_write_inst|state.IDLE~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N19 +dffeas \data_rw_ctrl_inst|wr_busy_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|wr_busy_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|wr_busy_dly .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|wr_busy_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_fall~0 ( +// Equation(s): +// \data_rw_ctrl_inst|wr_busy_fall~0_combout = (\data_rw_ctrl_inst|wr_busy_dly~q & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|wr_busy_dly~q ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|wr_busy_fall~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|wr_busy_fall~0 .lut_mask = 16'h00CC; +defparam \data_rw_ctrl_inst|wr_busy_fall~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N11 +dffeas \data_rw_ctrl_inst|rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|wr_busy_fall~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|rd_en .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cs_n~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cs_n~2_combout = (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout & ((\sd_ctrl_inst|sd_read_inst|cs_n~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q & \data_rw_ctrl_inst|rd_en~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cs_n~q ), + .datad(\data_rw_ctrl_inst|rd_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .lut_mask = 16'h3230; +defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N25 +dffeas \sd_ctrl_inst|sd_read_inst|cs_n ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cs_n~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cs_n .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cs_n .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_cs_n~0_combout = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_write_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_read_inst|cs_n~q )) # +// (!\sd_ctrl_inst|sd_read_inst|state.IDLE~q ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .datab(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_read_inst|cs_n~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_cs_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_cs_n~0 .lut_mask = 16'h1B5F; +defparam \sd_ctrl_inst|sd_cs_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~1_combout = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q & !\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q )) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .lut_mask = 16'h0101; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal6~1_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~0_combout = ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]) # (\sd_ctrl_inst|sd_init_inst|Equal6~1_combout )))) # (!\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .lut_mask = 16'hDDD5; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal6~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|Equal6~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .lut_mask = 16'h0800; +defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_init_inst|Selector13~0_combout & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal6~2_combout )))) +// # (!\sd_ctrl_inst|sd_init_inst|Equal6~0_combout & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal6~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .lut_mask = 16'hF5C4; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~3_combout = ((\sd_ctrl_inst|sd_init_inst|Selector15~0_combout & ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # (\sd_ctrl_inst|sd_init_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .lut_mask = 16'hA8FF; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cs_n ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cs_n~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cs_n .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cs_n .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_cs_n~1_combout = (\sd_ctrl_inst|sd_init_inst|init_end~q & (\sd_ctrl_inst|sd_cs_n~0_combout )) # (!\sd_ctrl_inst|sd_init_inst|init_end~q & ((!\sd_ctrl_inst|sd_init_inst|cs_n~q ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_cs_n~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_cs_n~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_cs_n~1 .lut_mask = 16'hCC0F; +defparam \sd_ctrl_inst|sd_cs_n~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~11_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~10_combout & (((\sd_ctrl_inst|sd_init_inst|mosi~q & !\sd_ctrl_inst|sd_init_inst|Selector14~0_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Selector14~10_combout & +// ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|mosi~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|mosi~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .lut_mask = 16'h54F4; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|mosi ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|mosi~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|mosi .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|mosi .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|mosi~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] $ (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5])))) # +// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .lut_mask = 16'hEC84; +defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N11 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|mosi~1_combout = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] $ (((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|mosi~0_combout & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3])))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .lut_mask = 16'hF0B4; +defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|mosi~2_combout = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_read_inst|mosi~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ))) # +// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((!\sd_ctrl_inst|sd_read_inst|mosi~1_combout ))))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .lut_mask = 16'hA700; +defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N1 +dffeas \sd_ctrl_inst|sd_read_inst|mosi ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|mosi~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|mosi .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q $ (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT = CARRY(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hCC33; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h0F0F; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N8 +cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( +// Equation(s): +// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] & VCC)) +// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [0])) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|Add1~0_combout ), + .cout(\uart_rx_inst|Add1~1 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; +defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N10 +cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( +// Equation(s): +// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) +// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~1 ), + .combout(\uart_rx_inst|Add1~2_combout ), + .cout(\uart_rx_inst|Add1~3 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N14 +cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( +// Equation(s): +// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|bit_cnt [3] $ (\uart_rx_inst|Add1~5 ) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(gnd), + .datad(gnd), + .cin(\uart_rx_inst|Add1~5 ), + .combout(\uart_rx_inst|Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h3C3C; +defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N4 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~0_combout = (\uart_rx_inst|Add1~6_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q ))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|Add1~6_combout ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h4CCC; +defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N5 +dffeas \uart_rx_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N24 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~1_combout = (\uart_rx_inst|Add1~0_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q ))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(\uart_rx_inst|Add1~0_combout ), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h70F0; +defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N25 +dffeas \uart_rx_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y16_N11 +dffeas \uart_rx_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N18 +cycloneive_lcell_comb \uart_rx_inst|always4~0 ( +// Equation(s): +// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [2]), + .datab(\uart_rx_inst|bit_cnt [0]), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_rx_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0011; +defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N2 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) +// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_rx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N0 +cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( +// Equation(s): +// \uart_rx_inst|Equal1~0_combout = (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [1] & \uart_rx_inst|baud_cnt [0]))) + + .dataa(\uart_rx_inst|baud_cnt [8]), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(\uart_rx_inst|baud_cnt [1]), + .datad(\uart_rx_inst|baud_cnt [0]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h1000; +defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N12 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) + + .dataa(\uart_rx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[4]~22 ), + .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_rx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N13 +dffeas \uart_rx_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N6 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) +// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_rx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[1]~16 ), + .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_rx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N7 +dffeas \uart_rx_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y16_N10 +cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( +// Equation(s): +// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N2 +cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( +// Equation(s): +// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|Equal1~2_combout & (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal1~1_combout ))) + + .dataa(\uart_rx_inst|Equal1~2_combout ), + .datab(\uart_rx_inst|baud_cnt [12]), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h8000; +defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N16 +cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( +// Equation(s): +// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) + + .dataa(\uart_rx_inst|start_nedge~q ), + .datab(gnd), + .datac(\uart_rx_inst|work_en~q ), + .datad(\uart_rx_inst|always4~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hAAFA; +defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N17 +dffeas \uart_rx_inst|work_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_rx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N28 +cycloneive_lcell_comb \uart_rx_inst|always5~0 ( +// Equation(s): +// \uart_rx_inst|always5~0_combout = (\uart_rx_inst|Equal1~3_combout ) # (!\uart_rx_inst|work_en~q ) + + .dataa(gnd), + .datab(\uart_rx_inst|Equal1~3_combout ), + .datac(gnd), + .datad(\uart_rx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_rx_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always5~0 .lut_mask = 16'hCCFF; +defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y16_N3 +dffeas \uart_rx_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N4 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[0]~14 ), + .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_rx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N5 +dffeas \uart_rx_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N8 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[2]~18 ), + .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_rx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N9 +dffeas \uart_rx_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N14 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) +// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[5]~24 ), + .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_rx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N15 +dffeas \uart_rx_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N16 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[6]~26 ), + .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_rx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N17 +dffeas \uart_rx_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N18 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) +// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[7]~28 ), + .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_rx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N19 +dffeas \uart_rx_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N20 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[8]~30 ), + .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_rx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N21 +dffeas \uart_rx_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N24 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[10]~34 ), + .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_rx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N25 +dffeas \uart_rx_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N26 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt [12] $ (!\uart_rx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_rx_inst|baud_cnt[11]~36 ), + .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N27 +dffeas \uart_rx_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N28 +cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( +// Equation(s): +// \uart_rx_inst|Equal2~1_combout = (!\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & \uart_rx_inst|baud_cnt [9]))) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [6]), + .datad(\uart_rx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0400; +defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N22 +cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( +// Equation(s): +// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal2~0_combout & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal2~1_combout ))) + + .dataa(\uart_rx_inst|Equal2~0_combout ), + .datab(\uart_rx_inst|baud_cnt [12]), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal2~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000; +defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N23 +dffeas \uart_rx_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Equal2~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N0 +cycloneive_lcell_comb \uart_rx_inst|always4~1 ( +// Equation(s): +// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|always4~0_combout & (\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [3])) + + .dataa(gnd), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~1 .lut_mask = 16'hC000; +defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N1 +dffeas \uart_rx_inst|rx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always4~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_flag .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N1 +dffeas \uart_rx_inst|po_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_flag~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_flag .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0010; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .lut_mask = 16'h0500; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'hA5F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .lut_mask = 16'hF05A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y12_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X12_Y12_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h6FF6; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|always4~2_combout & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|always4~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'h3020; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hE1F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h0040; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h3CC3; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h3333; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout = (\uart_rx_inst|po_flag~q & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .datab(\uart_rx_inst|po_flag~q ), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hCC88; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout & (\uart_rx_inst|po_flag~q & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .datac(\uart_rx_inst|po_flag~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'hC080; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0100; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q )) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h6969; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'hF00F; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h2000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0200; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0300; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y12_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout )) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X16_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y12_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y12_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .lut_mask = 16'h78F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y12_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )))) # (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .lut_mask = 16'h964D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )))) # (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & +// ((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .lut_mask = 16'h962B; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )))) # (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .lut_mask = 16'h964D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N4 +cycloneive_lcell_comb \sd_ctrl_inst|comb~1 ( +// Equation(s): +// \sd_ctrl_inst|comb~1_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|comb~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|comb~1 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|comb~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N0 +cycloneive_lcell_comb \sd_ctrl_inst|comb~0 ( +// Equation(s): +// \sd_ctrl_inst|comb~0_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout & (\sd_ctrl_inst|sd_init_inst|init_end~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|comb~0 .lut_mask = 16'h0004; +defparam \sd_ctrl_inst|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N2 +cycloneive_lcell_comb \sd_ctrl_inst|comb~2 ( +// Equation(s): +// \sd_ctrl_inst|comb~2_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout & +// (\sd_ctrl_inst|comb~1_combout & \sd_ctrl_inst|comb~0_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ), + .datac(\sd_ctrl_inst|comb~1_combout ), + .datad(\sd_ctrl_inst|comb~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|comb~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|comb~2 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|comb~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector1~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal3~2_combout & (((\sd_ctrl_inst|comb~2_combout & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )))) # (!\sd_ctrl_inst|sd_write_inst|Equal3~2_combout & +// ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # ((\sd_ctrl_inst|comb~2_combout & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datac(\sd_ctrl_inst|comb~2_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .lut_mask = 16'h44F4; +defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector1~3_combout = (\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|Selector2~0_combout & ((!\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal4~1_combout +// )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .lut_mask = 16'hF2FA; +defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N15 +dffeas \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N19 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux0~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))) # +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .lut_mask = 16'h00E8; +defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N21 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y16_N23 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~2_combout = (!\sd_ctrl_inst|sd_write_inst|Mux0~0_combout & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .lut_mask = 16'h0030; +defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal3~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~3_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & +// (\sd_ctrl_inst|sd_write_inst|Mux0~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .lut_mask = 16'h0E02; +defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~4_combout = (\sd_ctrl_inst|sd_write_inst|mosi~1_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q & ((\sd_ctrl_inst|sd_write_inst|mosi~2_combout ) # (\sd_ctrl_inst|sd_write_inst|mosi~3_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datad(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .lut_mask = 16'hFAEA; +defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~5_combout = (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .lut_mask = 16'h3323; +defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~8_combout = (!\sd_ctrl_inst|sd_write_inst|mosi~4_combout & (!\sd_ctrl_inst|sd_write_inst|mosi~5_combout & ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # (!\sd_ctrl_inst|sd_write_inst|mosi~7_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datac(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .lut_mask = 16'h000D; +defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X11_Y16_N17 +dffeas \sd_ctrl_inst|sd_write_inst|mosi ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|mosi~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|mosi .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_mosi~0_combout = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_write_inst|mosi~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q )) # +// (!\sd_ctrl_inst|sd_read_inst|mosi~q ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .datab(\sd_ctrl_inst|sd_read_inst|mosi~q ), + .datac(\sd_ctrl_inst|sd_write_inst|mosi~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_mosi~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_mosi~0 .lut_mask = 16'h1B5F; +defparam \sd_ctrl_inst|sd_mosi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_mosi~1_combout = (\sd_ctrl_inst|sd_init_inst|init_end~q & ((\sd_ctrl_inst|sd_mosi~0_combout ))) # (!\sd_ctrl_inst|sd_init_inst|init_end~q & (!\sd_ctrl_inst|sd_init_inst|mosi~q )) + + .dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|mosi~q ), + .datad(\sd_ctrl_inst|sd_mosi~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_mosi~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_mosi~1 .lut_mask = 16'hAF05; +defparam \sd_ctrl_inst|sd_mosi~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N2 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) +// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_tx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N0 +cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( +// Equation(s): +// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt [3] & \uart_tx_inst|baud_cnt [0]))) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(\uart_tx_inst|baud_cnt [3]), + .datad(\uart_tx_inst|baud_cnt [0]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0100; +defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N2 +cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( +// Equation(s): +// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|Equal1~0_combout & (!\uart_tx_inst|baud_cnt [11] & !\uart_tx_inst|baud_cnt [9]))) + + .dataa(\uart_tx_inst|baud_cnt [8]), + .datab(\uart_tx_inst|Equal1~0_combout ), + .datac(\uart_tx_inst|baud_cnt [11]), + .datad(\uart_tx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0004; +defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N10 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) +// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[3]~20 ), + .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_tx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N11 +dffeas \uart_tx_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N30 +cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( +// Equation(s): +// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4]))) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; +defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N16 +cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( +// Equation(s): +// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [10] & \uart_tx_inst|baud_cnt [12]) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(gnd), + .datac(\uart_tx_inst|baud_cnt [12]), + .datad(gnd), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hA0A0; +defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N26 +cycloneive_lcell_comb \uart_tx_inst|always1~0 ( +// Equation(s): +// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~1_combout & (\uart_tx_inst|Equal1~2_combout & \uart_tx_inst|Equal1~3_combout ))) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|Equal1~1_combout ), + .datac(\uart_tx_inst|Equal1~2_combout ), + .datad(\uart_tx_inst|Equal1~3_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555; +defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y26_N3 +dffeas \uart_tx_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N4 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[0]~14 ), + .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_tx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N5 +dffeas \uart_tx_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N8 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[2]~18 ), + .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_tx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N9 +dffeas \uart_tx_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N14 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) +// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[5]~24 ), + .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_tx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N15 +dffeas \uart_tx_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N16 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[6]~26 ), + .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_tx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N17 +dffeas \uart_tx_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N18 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) +// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[7]~28 ), + .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_tx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N19 +dffeas \uart_tx_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N20 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[8]~30 ), + .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_tx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N21 +dffeas \uart_tx_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N24 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[10]~34 ), + .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_tx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N25 +dffeas \uart_tx_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N26 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_tx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_tx_inst|baud_cnt[11]~36 ), + .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N27 +dffeas \uart_tx_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N28 +cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( +// Equation(s): +// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [4]))) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N24 +cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( +// Equation(s): +// \uart_tx_inst|Equal2~1_combout = (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt [12] & (\uart_tx_inst|Equal2~0_combout & \uart_tx_inst|Equal1~1_combout ))) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(\uart_tx_inst|Equal2~0_combout ), + .datad(\uart_tx_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h1000; +defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N25 +dffeas \uart_tx_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|Equal2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N18 +cycloneive_lcell_comb \uart_tx_inst|always3~0 ( +// Equation(s): +// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(gnd), + .datac(gnd), + .datad(\uart_tx_inst|bit_flag~q ), + .cin(gnd), + .combout(\uart_tx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always3~0 .lut_mask = 16'h55FF; +defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N12 +cycloneive_lcell_comb \uart_tx_inst|always0~1 ( +// Equation(s): +// \uart_tx_inst|always0~1_combout = (\uart_tx_inst|always0~0_combout & (\uart_tx_inst|bit_flag~q & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [3]))) + + .dataa(\uart_tx_inst|always0~0_combout ), + .datab(\uart_tx_inst|bit_flag~q ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_tx_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~1 .lut_mask = 16'h8000; +defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N4 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|work_en~q & \uart_tx_inst|bit_flag~q ))))) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|bit_flag~q ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h0078; +defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N5 +dffeas \uart_tx_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[0]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N0 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~4 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[1]~4_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) + + .dataa(\uart_tx_inst|always0~1_combout ), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_tx_inst|bit_cnt [1]), + .datad(\uart_tx_inst|always3~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1]~4 .lut_mask = 16'h5014; +defparam \uart_tx_inst|bit_cnt[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N1 +dffeas \uart_tx_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[1]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N16 +cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( +// Equation(s): +// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [2] & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1])))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|bit_cnt [3]), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h6CCC; +defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N2 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~2 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[3]~2_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & (\uart_tx_inst|bit_cnt [3])) # (!\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|Add1~0_combout ))))) + + .dataa(\uart_tx_inst|always0~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|Add1~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3]~2 .lut_mask = 16'h5140; +defparam \uart_tx_inst|bit_cnt[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N3 +dffeas \uart_tx_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[3]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[0]~16 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[0]~16_combout = \data_rw_ctrl_inst|cnt_wait [0] $ (VCC) +// \data_rw_ctrl_inst|cnt_wait[0]~17 = CARRY(\data_rw_ctrl_inst|cnt_wait [0]) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[0]~17 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[3]~22 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[3]~22_combout = (\data_rw_ctrl_inst|cnt_wait [3] & (!\data_rw_ctrl_inst|cnt_wait[2]~21 )) # (!\data_rw_ctrl_inst|cnt_wait [3] & ((\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[3]~23 = CARRY((!\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (!\data_rw_ctrl_inst|cnt_wait [3])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[2]~21 ), + .combout(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[3]~23 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[4]~24 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[4]~24_combout = (\data_rw_ctrl_inst|cnt_wait [4] & (\data_rw_ctrl_inst|cnt_wait[3]~23 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [4] & (!\data_rw_ctrl_inst|cnt_wait[3]~23 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[4]~25 = CARRY((\data_rw_ctrl_inst|cnt_wait [4] & !\data_rw_ctrl_inst|cnt_wait[3]~23 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [4]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[3]~23 ), + .combout(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[4]~25 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N9 +dffeas \data_rw_ctrl_inst|cnt_wait[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal3~0_combout = (\data_rw_ctrl_inst|cnt_wait [4]) # (!\data_rw_ctrl_inst|cnt_wait [5]) + + .dataa(\data_rw_ctrl_inst|cnt_wait [5]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|cnt_wait [4]), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal3~0 .lut_mask = 16'hF5F5; +defparam \data_rw_ctrl_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N15 +dffeas \data_rw_ctrl_inst|rd_busy_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|rd_busy_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|rd_busy_dly .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|rd_busy_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[0]~12 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[0]~12_combout = \data_rw_ctrl_inst|send_data_num [0] $ (VCC) +// \data_rw_ctrl_inst|send_data_num[0]~13 = CARRY(\data_rw_ctrl_inst|send_data_num [0]) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|send_data_num[0]~12_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[0]~13 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[0]~12 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|send_data_num[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y26_N1 +dffeas \data_rw_ctrl_inst|send_data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[0]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[1]~14 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[1]~14_combout = (\data_rw_ctrl_inst|send_data_num [1] & (!\data_rw_ctrl_inst|send_data_num[0]~13 )) # (!\data_rw_ctrl_inst|send_data_num [1] & ((\data_rw_ctrl_inst|send_data_num[0]~13 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[1]~15 = CARRY((!\data_rw_ctrl_inst|send_data_num[0]~13 ) # (!\data_rw_ctrl_inst|send_data_num [1])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [1]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[0]~13 ), + .combout(\data_rw_ctrl_inst|send_data_num[1]~14_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[1]~15 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[1]~14 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|send_data_num[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N3 +dffeas \data_rw_ctrl_inst|send_data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[1]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[2]~16 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[2]~16_combout = (\data_rw_ctrl_inst|send_data_num [2] & (\data_rw_ctrl_inst|send_data_num[1]~15 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [2] & (!\data_rw_ctrl_inst|send_data_num[1]~15 & VCC)) +// \data_rw_ctrl_inst|send_data_num[2]~17 = CARRY((\data_rw_ctrl_inst|send_data_num [2] & !\data_rw_ctrl_inst|send_data_num[1]~15 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [2]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[1]~15 ), + .combout(\data_rw_ctrl_inst|send_data_num[2]~16_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[2]~17 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[2]~16 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N5 +dffeas \data_rw_ctrl_inst|send_data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[2]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~0_combout = (\data_rw_ctrl_inst|send_data_num [3] & (\data_rw_ctrl_inst|send_data_num [1] & (\data_rw_ctrl_inst|send_data_num [2] & \data_rw_ctrl_inst|send_data_num [0]))) + + .dataa(\data_rw_ctrl_inst|send_data_num [3]), + .datab(\data_rw_ctrl_inst|send_data_num [1]), + .datac(\data_rw_ctrl_inst|send_data_num [2]), + .datad(\data_rw_ctrl_inst|send_data_num [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~0 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[4]~20 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[4]~20_combout = (\data_rw_ctrl_inst|send_data_num [4] & (\data_rw_ctrl_inst|send_data_num[3]~19 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [4] & (!\data_rw_ctrl_inst|send_data_num[3]~19 & VCC)) +// \data_rw_ctrl_inst|send_data_num[4]~21 = CARRY((\data_rw_ctrl_inst|send_data_num [4] & !\data_rw_ctrl_inst|send_data_num[3]~19 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [4]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[3]~19 ), + .combout(\data_rw_ctrl_inst|send_data_num[4]~20_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[4]~21 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[4]~20 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N9 +dffeas \data_rw_ctrl_inst|send_data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[4]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[5]~22 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[5]~22_combout = (\data_rw_ctrl_inst|send_data_num [5] & (!\data_rw_ctrl_inst|send_data_num[4]~21 )) # (!\data_rw_ctrl_inst|send_data_num [5] & ((\data_rw_ctrl_inst|send_data_num[4]~21 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[5]~23 = CARRY((!\data_rw_ctrl_inst|send_data_num[4]~21 ) # (!\data_rw_ctrl_inst|send_data_num [5])) + + .dataa(\data_rw_ctrl_inst|send_data_num [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[4]~21 ), + .combout(\data_rw_ctrl_inst|send_data_num[5]~22_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[5]~23 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[5]~22 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|send_data_num[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N15 +dffeas \data_rw_ctrl_inst|send_data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[7]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N11 +dffeas \data_rw_ctrl_inst|send_data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[5]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~1 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~1_combout = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num [7] & (\data_rw_ctrl_inst|send_data_num [4] & \data_rw_ctrl_inst|send_data_num [5]))) + + .dataa(\data_rw_ctrl_inst|send_data_num [6]), + .datab(\data_rw_ctrl_inst|send_data_num [7]), + .datac(\data_rw_ctrl_inst|send_data_num [4]), + .datad(\data_rw_ctrl_inst|send_data_num [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~1 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|always3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~3 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~3_combout = (\data_rw_ctrl_inst|always3~2_combout & (\data_rw_ctrl_inst|always3~0_combout & (\data_rw_ctrl_inst|always3~1_combout & \data_rw_ctrl_inst|Equal2~4_combout ))) + + .dataa(\data_rw_ctrl_inst|always3~2_combout ), + .datab(\data_rw_ctrl_inst|always3~0_combout ), + .datac(\data_rw_ctrl_inst|always3~1_combout ), + .datad(\data_rw_ctrl_inst|Equal2~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~3 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|always3~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_en~0 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_en~0_combout = (!\data_rw_ctrl_inst|always3~3_combout & ((\data_rw_ctrl_inst|send_data_en~q ) # ((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q & \data_rw_ctrl_inst|rd_busy_dly~q )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .datab(\data_rw_ctrl_inst|rd_busy_dly~q ), + .datac(\data_rw_ctrl_inst|send_data_en~q ), + .datad(\data_rw_ctrl_inst|always3~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|send_data_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_en~0 .lut_mask = 16'h00F4; +defparam \data_rw_ctrl_inst|send_data_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N23 +dffeas \data_rw_ctrl_inst|send_data_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_en .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~1 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal3~1_combout = (\data_rw_ctrl_inst|cnt_wait [0]) # ((\data_rw_ctrl_inst|cnt_wait [3]) # ((\data_rw_ctrl_inst|cnt_wait [2]) # (\data_rw_ctrl_inst|cnt_wait [1]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [0]), + .datab(\data_rw_ctrl_inst|cnt_wait [3]), + .datac(\data_rw_ctrl_inst|cnt_wait [2]), + .datad(\data_rw_ctrl_inst|cnt_wait [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal3~1 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~26 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[13]~26_combout = ((\data_rw_ctrl_inst|Equal2~2_combout & (!\data_rw_ctrl_inst|Equal3~0_combout & !\data_rw_ctrl_inst|Equal3~1_combout ))) # (!\data_rw_ctrl_inst|send_data_en~q ) + + .dataa(\data_rw_ctrl_inst|Equal2~2_combout ), + .datab(\data_rw_ctrl_inst|Equal3~0_combout ), + .datac(\data_rw_ctrl_inst|send_data_en~q ), + .datad(\data_rw_ctrl_inst|Equal3~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .lut_mask = 16'h0F2F; +defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y27_N1 +dffeas \data_rw_ctrl_inst|cnt_wait[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[1]~18 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[1]~18_combout = (\data_rw_ctrl_inst|cnt_wait [1] & (!\data_rw_ctrl_inst|cnt_wait[0]~17 )) # (!\data_rw_ctrl_inst|cnt_wait [1] & ((\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[1]~19 = CARRY((!\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (!\data_rw_ctrl_inst|cnt_wait [1])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [1]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[0]~17 ), + .combout(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[1]~19 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N3 +dffeas \data_rw_ctrl_inst|cnt_wait[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[2]~20 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[2]~20_combout = (\data_rw_ctrl_inst|cnt_wait [2] & (\data_rw_ctrl_inst|cnt_wait[1]~19 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [2] & (!\data_rw_ctrl_inst|cnt_wait[1]~19 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[2]~21 = CARRY((\data_rw_ctrl_inst|cnt_wait [2] & !\data_rw_ctrl_inst|cnt_wait[1]~19 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [2]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[1]~19 ), + .combout(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[2]~21 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N5 +dffeas \data_rw_ctrl_inst|cnt_wait[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y27_N7 +dffeas \data_rw_ctrl_inst|cnt_wait[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~3 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~3_combout = (\data_rw_ctrl_inst|cnt_wait [0] & (\data_rw_ctrl_inst|cnt_wait [3] & (\data_rw_ctrl_inst|cnt_wait [2] & \data_rw_ctrl_inst|cnt_wait [1]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [0]), + .datab(\data_rw_ctrl_inst|cnt_wait [3]), + .datac(\data_rw_ctrl_inst|cnt_wait [2]), + .datad(\data_rw_ctrl_inst|cnt_wait [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~3 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[6]~29 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[6]~29_combout = (\data_rw_ctrl_inst|cnt_wait [6] & (\data_rw_ctrl_inst|cnt_wait[5]~28 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [6] & (!\data_rw_ctrl_inst|cnt_wait[5]~28 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[6]~30 = CARRY((\data_rw_ctrl_inst|cnt_wait [6] & !\data_rw_ctrl_inst|cnt_wait[5]~28 )) + + .dataa(\data_rw_ctrl_inst|cnt_wait [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[5]~28 ), + .combout(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[6]~30 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .lut_mask = 16'hA50A; +defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[7]~31 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[7]~31_combout = (\data_rw_ctrl_inst|cnt_wait [7] & (!\data_rw_ctrl_inst|cnt_wait[6]~30 )) # (!\data_rw_ctrl_inst|cnt_wait [7] & ((\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[7]~32 = CARRY((!\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (!\data_rw_ctrl_inst|cnt_wait [7])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [7]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[6]~30 ), + .combout(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[7]~32 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N15 +dffeas \data_rw_ctrl_inst|cnt_wait[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[8]~33 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[8]~33_combout = (\data_rw_ctrl_inst|cnt_wait [8] & (\data_rw_ctrl_inst|cnt_wait[7]~32 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [8] & (!\data_rw_ctrl_inst|cnt_wait[7]~32 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[8]~34 = CARRY((\data_rw_ctrl_inst|cnt_wait [8] & !\data_rw_ctrl_inst|cnt_wait[7]~32 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [8]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[7]~32 ), + .combout(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[8]~34 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N17 +dffeas \data_rw_ctrl_inst|cnt_wait[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[9]~35 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[9]~35_combout = (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait[8]~34 )) # (!\data_rw_ctrl_inst|cnt_wait [9] & ((\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[9]~36 = CARRY((!\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (!\data_rw_ctrl_inst|cnt_wait [9])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [9]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[8]~34 ), + .combout(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[9]~36 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N19 +dffeas \data_rw_ctrl_inst|cnt_wait[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[10]~37 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[10]~37_combout = (\data_rw_ctrl_inst|cnt_wait [10] & (\data_rw_ctrl_inst|cnt_wait[9]~36 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait[9]~36 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[10]~38 = CARRY((\data_rw_ctrl_inst|cnt_wait [10] & !\data_rw_ctrl_inst|cnt_wait[9]~36 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [10]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[9]~36 ), + .combout(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[10]~38 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N21 +dffeas \data_rw_ctrl_inst|cnt_wait[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[10] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[11]~39 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[11]~39_combout = (\data_rw_ctrl_inst|cnt_wait [11] & (!\data_rw_ctrl_inst|cnt_wait[10]~38 )) # (!\data_rw_ctrl_inst|cnt_wait [11] & ((\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[11]~40 = CARRY((!\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (!\data_rw_ctrl_inst|cnt_wait [11])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[10]~38 ), + .combout(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[11]~40 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[12]~41 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[12]~41_combout = (\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait[11]~40 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [12] & (!\data_rw_ctrl_inst|cnt_wait[11]~40 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[12]~42 = CARRY((\data_rw_ctrl_inst|cnt_wait [12] & !\data_rw_ctrl_inst|cnt_wait[11]~40 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [12]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[11]~40 ), + .combout(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[12]~42 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N25 +dffeas \data_rw_ctrl_inst|cnt_wait[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [12]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[12] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~43 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[13]~43_combout = (\data_rw_ctrl_inst|cnt_wait [13] & (!\data_rw_ctrl_inst|cnt_wait[12]~42 )) # (!\data_rw_ctrl_inst|cnt_wait [13] & ((\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[13]~44 = CARRY((!\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (!\data_rw_ctrl_inst|cnt_wait [13])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[12]~42 ), + .combout(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[13]~44 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[14]~45 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[14]~45_combout = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait[13]~44 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [14] & (!\data_rw_ctrl_inst|cnt_wait[13]~44 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[14]~46 = CARRY((\data_rw_ctrl_inst|cnt_wait [14] & !\data_rw_ctrl_inst|cnt_wait[13]~44 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [14]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[13]~44 ), + .combout(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[14]~46 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N29 +dffeas \data_rw_ctrl_inst|cnt_wait[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [14]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[14] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[15]~47 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[15]~47_combout = \data_rw_ctrl_inst|cnt_wait [15] $ (\data_rw_ctrl_inst|cnt_wait[14]~46 ) + + .dataa(\data_rw_ctrl_inst|cnt_wait [15]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|cnt_wait[14]~46 ), + .combout(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N31 +dffeas \data_rw_ctrl_inst|cnt_wait[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [15]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[15] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[15] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y27_N13 +dffeas \data_rw_ctrl_inst|cnt_wait[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~0 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~0_combout = (!\data_rw_ctrl_inst|cnt_wait [7] & (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait [8] & \data_rw_ctrl_inst|cnt_wait [6]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [7]), + .datab(\data_rw_ctrl_inst|cnt_wait [9]), + .datac(\data_rw_ctrl_inst|cnt_wait [8]), + .datad(\data_rw_ctrl_inst|cnt_wait [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~0 .lut_mask = 16'h0400; +defparam \data_rw_ctrl_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y27_N27 +dffeas \data_rw_ctrl_inst|cnt_wait[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [13]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[13] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y27_N23 +dffeas \data_rw_ctrl_inst|cnt_wait[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [11]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[11] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~1 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~1_combout = (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait [13] & \data_rw_ctrl_inst|cnt_wait [11]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [10]), + .datab(\data_rw_ctrl_inst|cnt_wait [12]), + .datac(\data_rw_ctrl_inst|cnt_wait [13]), + .datad(\data_rw_ctrl_inst|cnt_wait [11]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~1 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~2 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~2_combout = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait [15] & (\data_rw_ctrl_inst|Equal2~0_combout & \data_rw_ctrl_inst|Equal2~1_combout ))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [14]), + .datab(\data_rw_ctrl_inst|cnt_wait [15]), + .datac(\data_rw_ctrl_inst|Equal2~0_combout ), + .datad(\data_rw_ctrl_inst|Equal2~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~2 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~4 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~4_combout = (!\data_rw_ctrl_inst|cnt_wait [5] & (\data_rw_ctrl_inst|Equal2~3_combout & (\data_rw_ctrl_inst|cnt_wait [4] & \data_rw_ctrl_inst|Equal2~2_combout ))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [5]), + .datab(\data_rw_ctrl_inst|Equal2~3_combout ), + .datac(\data_rw_ctrl_inst|cnt_wait [4]), + .datad(\data_rw_ctrl_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~4 .lut_mask = 16'h4000; +defparam \data_rw_ctrl_inst|Equal2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N7 +dffeas \data_rw_ctrl_inst|rd_fifo_rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|Equal2~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|rd_fifo_rd_en .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|rd_fifo_rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0300; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]) # (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .lut_mask = 16'hFFFE; +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & ((\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|always3~0_combout )))) # (!\sd_ctrl_inst|sd_read_inst|always3~2_combout ) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .lut_mask = 16'hDF55; +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .lut_mask = 16'h0080; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N9 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y28_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9] + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .lut_mask = 16'hF0F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEBD7; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N15 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y28_N15 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y27_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hF0C0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hE1F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout & +// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0020; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .lut_mask = 16'h0100; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0300; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'hC3F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h3C3C; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h3CC3; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q +// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0A08; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h78F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout & +// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0020; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y27_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y28_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y28_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X30_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y28_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout & (\data_rw_ctrl_inst|rd_fifo_rd_en~q +// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'h8880; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0100; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9] $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .lut_mask = 16'hC3F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .lut_mask = 16'h55AA; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N15 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h3CC3; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'hF00F; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .lut_mask = 16'h78F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h3333; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout = (\data_rw_ctrl_inst|rd_fifo_rd_en~q & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hCCC0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout = (\sd_miso~input_o & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N7 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~13_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout = ((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) # (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .lut_mask = 16'h55D5; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N31 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N1 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N13 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N19 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N17 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N23 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N21 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N23 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N17 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~14_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N3 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h00FF; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .lut_mask = 16'h00FF; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~15_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [1] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N17 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~11_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N29 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~7_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N1 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~5_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N5 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~3_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N19 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~9_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N7 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~0_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N25 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N11 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~16_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N29 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~12_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N9 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~8_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N5 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~6_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N7 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N21 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~4_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N11 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~10_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N3 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N19 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [15]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N25 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N20 +cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( +// Equation(s): +// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [3] & (((\uart_tx_inst|bit_cnt [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])) # (!\uart_tx_inst|always0~0_combout ))) + + .dataa(\uart_tx_inst|always0~0_combout ), + .datab(\uart_tx_inst|bit_cnt [3]), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hCCC4; +defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N8 +cycloneive_lcell_comb \uart_tx_inst|tx~0 ( +// Equation(s): +// \uart_tx_inst|tx~0_combout = (\uart_tx_inst|bit_flag~q & (!\uart_tx_inst|Mux0~5_combout & ((!\uart_tx_inst|Mux0~0_combout )))) # (!\uart_tx_inst|bit_flag~q & (((\uart_tx_inst|tx~q )))) + + .dataa(\uart_tx_inst|Mux0~5_combout ), + .datab(\uart_tx_inst|bit_flag~q ), + .datac(\uart_tx_inst|tx~q ), + .datad(\uart_tx_inst|Mux0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~0 .lut_mask = 16'h3074; +defparam \uart_tx_inst|tx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N9 +dffeas \uart_tx_inst|tx ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|tx~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|tx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|tx .is_wysiwyg = "true"; +defparam \uart_tx_inst|tx .power_up = "low"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_0c_slow.vo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_0c_slow.vo new file mode 100644 index 0000000..6b66e8b --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_0c_slow.vo @@ -0,0 +1,24509 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:03:14" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module uart_sd ( + sys_clk, + sys_rst_n, + rx, + sd_miso, + sd_clk, + sd_cs_n, + sd_mosi, + tx); +input sys_clk; +input sys_rst_n; +input rx; +input sd_miso; +output sd_clk; +output sd_cs_n; +output sd_mosi; +output tx; + +// Design Ports Information +// sd_clk => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// sd_cs_n => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default +// sd_mosi => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default +// sd_miso => Location: PIN_E9, I/O Standard: 2.5 V, Current Strength: Default +// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("uart_sd_8_1200mv_0c_v_slow.sdo"); +// synopsys translate_on + +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ; +wire \uart_tx_inst|baud_cnt[2]~17_combout ; +wire \uart_tx_inst|baud_cnt[5]~23_combout ; +wire \uart_tx_inst|baud_cnt[10]~33_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ; +wire \data_rw_ctrl_inst|cnt_wait[5]~27_combout ; +wire \uart_rx_inst|Add1~4_combout ; +wire \uart_rx_inst|baud_cnt[4]~21_combout ; +wire \uart_rx_inst|baud_cnt[10]~33_combout ; +wire \data_rw_ctrl_inst|send_data_num[3]~18_combout ; +wire \data_rw_ctrl_inst|send_data_num[6]~24_combout ; +wire \data_rw_ctrl_inst|send_data_num[7]~27 ; +wire \data_rw_ctrl_inst|send_data_num[8]~29 ; +wire \data_rw_ctrl_inst|send_data_num[8]~28_combout ; +wire \data_rw_ctrl_inst|send_data_num[9]~31 ; +wire \data_rw_ctrl_inst|send_data_num[9]~30_combout ; +wire \data_rw_ctrl_inst|send_data_num[10]~33 ; +wire \data_rw_ctrl_inst|send_data_num[10]~32_combout ; +wire \data_rw_ctrl_inst|send_data_num[11]~34_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ; +wire \sd_ctrl_inst|sd_init_inst|Equal6~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux0~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~4_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~5_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~6_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~7_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~6_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~7_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~3_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~4_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~5_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~6_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~7_combout ; +wire \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~8_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~9_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~10_combout ; +wire \uart_tx_inst|always0~0_combout ; +wire \uart_tx_inst|Mux0~1_combout ; +wire \uart_tx_inst|Mux0~2_combout ; +wire \uart_tx_inst|Mux0~3_combout ; +wire \uart_tx_inst|Mux0~4_combout ; +wire \uart_tx_inst|Mux0~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal1~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector8~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector0~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal3~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal3~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal3~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal3~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ; +wire \sd_ctrl_inst|sd_write_inst|Selector2~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Add3~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ; +wire \uart_tx_inst|work_en~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ; +wire \uart_tx_inst|Add1~1_combout ; +wire \uart_tx_inst|bit_cnt[2]~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector3~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector3~1_combout ; +wire \data_rw_ctrl_inst|tx_flag~q ; +wire \uart_tx_inst|work_en~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~6_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~7_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~1_combout ; +wire \uart_rx_inst|always8~0_combout ; +wire \uart_rx_inst|rx_reg3~q ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ; +wire \uart_rx_inst|Equal2~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ; +wire \uart_rx_inst|rx_reg2~q ; +wire \data_rw_ctrl_inst|always3~2_combout ; +wire \uart_rx_inst|Equal1~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ; +wire \uart_rx_inst|rx_reg1~q ; +wire \uart_rx_inst|start_nedge~q ; +wire \uart_rx_inst|always3~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ; +wire \uart_rx_inst|rx_data[7]~0_combout ; +wire \uart_rx_inst|rx_reg1~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ; +wire \rx~input_o ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|tx_flag~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ; +wire \uart_rx_inst|po_data[1]~feeder_combout ; +wire \uart_rx_inst|rx_data[0]~feeder_combout ; +wire \uart_rx_inst|po_data[5]~feeder_combout ; +wire \uart_rx_inst|rx_data[4]~feeder_combout ; +wire \uart_rx_inst|po_data[6]~feeder_combout ; +wire \uart_rx_inst|rx_data[5]~feeder_combout ; +wire \uart_rx_inst|po_data[7]~feeder_combout ; +wire \uart_rx_inst|rx_data[6]~feeder_combout ; +wire \uart_rx_inst|po_data[3]~feeder_combout ; +wire \uart_rx_inst|rx_data[2]~feeder_combout ; +wire \uart_rx_inst|po_data[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ; +wire \uart_rx_inst|rx_reg2~feeder_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ; +wire \sd_miso~input_o ; +wire \sd_ctrl_inst|sd_init_inst|miso_dly~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal0~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal0~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal3~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_en~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_en~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_en~q ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal1~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal2~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal2~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector0~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal0~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal0~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal0~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.IDLE~q ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~q ; +wire \sd_ctrl_inst|sd_init_inst|WideOr18~combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal5~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal5~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal5~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector2~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector1~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector1~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector5~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector4~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector7~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector3~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector3~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector15~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector15~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector15~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|init_end~q ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal2~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal2~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector3~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ; +wire \sd_ctrl_inst|sd_read_inst|Selector2~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector2~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Add3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal9~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~11_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~9_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~13_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~15_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~q ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector4~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.RD_END~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector0~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector0~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.IDLE~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal1~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal1~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~q ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal4~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal4~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal4~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector2~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Add3~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Add3~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector4~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~7_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~6_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~5_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal6~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~4_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal6~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal6~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector5~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.WR_END~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector0~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cs_n~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cs_n~q ; +wire \sd_ctrl_inst|sd_write_inst|Selector0~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.IDLE~q ; +wire \data_rw_ctrl_inst|wr_busy_dly~feeder_combout ; +wire \data_rw_ctrl_inst|wr_busy_dly~q ; +wire \data_rw_ctrl_inst|wr_busy_fall~0_combout ; +wire \data_rw_ctrl_inst|rd_en~q ; +wire \sd_ctrl_inst|sd_read_inst|cs_n~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|cs_n~q ; +wire \sd_ctrl_inst|sd_cs_n~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal6~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal6~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~3_combout ; +wire \sd_ctrl_inst|sd_init_inst|cs_n~q ; +wire \sd_ctrl_inst|sd_cs_n~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~11_combout ; +wire \sd_ctrl_inst|sd_init_inst|mosi~q ; +wire \sd_ctrl_inst|sd_read_inst|mosi~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|mosi~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|mosi~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|mosi~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ; +wire \uart_rx_inst|Add1~1 ; +wire \uart_rx_inst|Add1~3 ; +wire \uart_rx_inst|Add1~5 ; +wire \uart_rx_inst|Add1~6_combout ; +wire \uart_rx_inst|bit_cnt~0_combout ; +wire \uart_rx_inst|Add1~0_combout ; +wire \uart_rx_inst|bit_cnt~1_combout ; +wire \uart_rx_inst|Add1~2_combout ; +wire \uart_rx_inst|always4~0_combout ; +wire \uart_rx_inst|baud_cnt[0]~13_combout ; +wire \uart_rx_inst|Equal1~0_combout ; +wire \uart_rx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|baud_cnt[2]~17_combout ; +wire \uart_rx_inst|Equal1~1_combout ; +wire \uart_rx_inst|Equal1~3_combout ; +wire \uart_rx_inst|work_en~0_combout ; +wire \uart_rx_inst|work_en~q ; +wire \uart_rx_inst|always5~0_combout ; +wire \uart_rx_inst|baud_cnt[0]~14 ; +wire \uart_rx_inst|baud_cnt[1]~15_combout ; +wire \uart_rx_inst|baud_cnt[1]~16 ; +wire \uart_rx_inst|baud_cnt[2]~18 ; +wire \uart_rx_inst|baud_cnt[3]~19_combout ; +wire \uart_rx_inst|baud_cnt[3]~20 ; +wire \uart_rx_inst|baud_cnt[4]~22 ; +wire \uart_rx_inst|baud_cnt[5]~24 ; +wire \uart_rx_inst|baud_cnt[6]~25_combout ; +wire \uart_rx_inst|baud_cnt[6]~26 ; +wire \uart_rx_inst|baud_cnt[7]~27_combout ; +wire \uart_rx_inst|baud_cnt[7]~28 ; +wire \uart_rx_inst|baud_cnt[8]~29_combout ; +wire \uart_rx_inst|baud_cnt[8]~30 ; +wire \uart_rx_inst|baud_cnt[9]~31_combout ; +wire \uart_rx_inst|baud_cnt[9]~32 ; +wire \uart_rx_inst|baud_cnt[10]~34 ; +wire \uart_rx_inst|baud_cnt[11]~35_combout ; +wire \uart_rx_inst|baud_cnt[11]~36 ; +wire \uart_rx_inst|baud_cnt[12]~37_combout ; +wire \uart_rx_inst|Equal2~1_combout ; +wire \uart_rx_inst|Equal2~2_combout ; +wire \uart_rx_inst|bit_flag~q ; +wire \uart_rx_inst|always4~1_combout ; +wire \uart_rx_inst|rx_flag~q ; +wire \uart_rx_inst|po_flag~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ; +wire \sd_ctrl_inst|comb~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ; +wire \sd_ctrl_inst|comb~0_combout ; +wire \sd_ctrl_inst|comb~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector1~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector1~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux0~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal3~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~4_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~5_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~q ; +wire \sd_ctrl_inst|sd_mosi~0_combout ; +wire \sd_ctrl_inst|sd_mosi~1_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \uart_tx_inst|baud_cnt[0]~13_combout ; +wire \uart_tx_inst|Equal1~0_combout ; +wire \uart_tx_inst|Equal1~1_combout ; +wire \uart_tx_inst|baud_cnt[4]~21_combout ; +wire \uart_tx_inst|Equal1~2_combout ; +wire \uart_tx_inst|Equal1~3_combout ; +wire \uart_tx_inst|always1~0_combout ; +wire \uart_tx_inst|baud_cnt[0]~14 ; +wire \uart_tx_inst|baud_cnt[1]~15_combout ; +wire \uart_tx_inst|baud_cnt[1]~16 ; +wire \uart_tx_inst|baud_cnt[2]~18 ; +wire \uart_tx_inst|baud_cnt[3]~19_combout ; +wire \uart_tx_inst|baud_cnt[3]~20 ; +wire \uart_tx_inst|baud_cnt[4]~22 ; +wire \uart_tx_inst|baud_cnt[5]~24 ; +wire \uart_tx_inst|baud_cnt[6]~25_combout ; +wire \uart_tx_inst|baud_cnt[6]~26 ; +wire \uart_tx_inst|baud_cnt[7]~27_combout ; +wire \uart_tx_inst|baud_cnt[7]~28 ; +wire \uart_tx_inst|baud_cnt[8]~29_combout ; +wire \uart_tx_inst|baud_cnt[8]~30 ; +wire \uart_tx_inst|baud_cnt[9]~31_combout ; +wire \uart_tx_inst|baud_cnt[9]~32 ; +wire \uart_tx_inst|baud_cnt[10]~34 ; +wire \uart_tx_inst|baud_cnt[11]~35_combout ; +wire \uart_tx_inst|baud_cnt[11]~36 ; +wire \uart_tx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal2~0_combout ; +wire \uart_tx_inst|Equal2~1_combout ; +wire \uart_tx_inst|bit_flag~q ; +wire \uart_tx_inst|always3~0_combout ; +wire \uart_tx_inst|always0~1_combout ; +wire \uart_tx_inst|bit_cnt[0]~5_combout ; +wire \uart_tx_inst|bit_cnt[1]~4_combout ; +wire \uart_tx_inst|Add1~0_combout ; +wire \uart_tx_inst|bit_cnt[3]~2_combout ; +wire \data_rw_ctrl_inst|cnt_wait[0]~16_combout ; +wire \data_rw_ctrl_inst|cnt_wait[3]~23 ; +wire \data_rw_ctrl_inst|cnt_wait[4]~24_combout ; +wire \data_rw_ctrl_inst|Equal3~0_combout ; +wire \data_rw_ctrl_inst|rd_busy_dly~q ; +wire \data_rw_ctrl_inst|send_data_num[0]~12_combout ; +wire \data_rw_ctrl_inst|send_data_num[0]~13 ; +wire \data_rw_ctrl_inst|send_data_num[1]~14_combout ; +wire \data_rw_ctrl_inst|send_data_num[1]~15 ; +wire \data_rw_ctrl_inst|send_data_num[2]~16_combout ; +wire \data_rw_ctrl_inst|always3~0_combout ; +wire \data_rw_ctrl_inst|send_data_num[2]~17 ; +wire \data_rw_ctrl_inst|send_data_num[3]~19 ; +wire \data_rw_ctrl_inst|send_data_num[4]~20_combout ; +wire \data_rw_ctrl_inst|send_data_num[4]~21 ; +wire \data_rw_ctrl_inst|send_data_num[5]~23 ; +wire \data_rw_ctrl_inst|send_data_num[6]~25 ; +wire \data_rw_ctrl_inst|send_data_num[7]~26_combout ; +wire \data_rw_ctrl_inst|send_data_num[5]~22_combout ; +wire \data_rw_ctrl_inst|always3~1_combout ; +wire \data_rw_ctrl_inst|always3~3_combout ; +wire \data_rw_ctrl_inst|send_data_en~0_combout ; +wire \data_rw_ctrl_inst|send_data_en~q ; +wire \data_rw_ctrl_inst|Equal3~1_combout ; +wire \data_rw_ctrl_inst|cnt_wait[13]~26_combout ; +wire \data_rw_ctrl_inst|cnt_wait[0]~17 ; +wire \data_rw_ctrl_inst|cnt_wait[1]~18_combout ; +wire \data_rw_ctrl_inst|cnt_wait[1]~19 ; +wire \data_rw_ctrl_inst|cnt_wait[2]~20_combout ; +wire \data_rw_ctrl_inst|cnt_wait[2]~21 ; +wire \data_rw_ctrl_inst|cnt_wait[3]~22_combout ; +wire \data_rw_ctrl_inst|Equal2~3_combout ; +wire \data_rw_ctrl_inst|cnt_wait[4]~25 ; +wire \data_rw_ctrl_inst|cnt_wait[5]~28 ; +wire \data_rw_ctrl_inst|cnt_wait[6]~30 ; +wire \data_rw_ctrl_inst|cnt_wait[7]~31_combout ; +wire \data_rw_ctrl_inst|cnt_wait[7]~32 ; +wire \data_rw_ctrl_inst|cnt_wait[8]~33_combout ; +wire \data_rw_ctrl_inst|cnt_wait[8]~34 ; +wire \data_rw_ctrl_inst|cnt_wait[9]~35_combout ; +wire \data_rw_ctrl_inst|cnt_wait[9]~36 ; +wire \data_rw_ctrl_inst|cnt_wait[10]~37_combout ; +wire \data_rw_ctrl_inst|cnt_wait[10]~38 ; +wire \data_rw_ctrl_inst|cnt_wait[11]~40 ; +wire \data_rw_ctrl_inst|cnt_wait[12]~41_combout ; +wire \data_rw_ctrl_inst|cnt_wait[12]~42 ; +wire \data_rw_ctrl_inst|cnt_wait[13]~44 ; +wire \data_rw_ctrl_inst|cnt_wait[14]~45_combout ; +wire \data_rw_ctrl_inst|cnt_wait[14]~46 ; +wire \data_rw_ctrl_inst|cnt_wait[15]~47_combout ; +wire \data_rw_ctrl_inst|cnt_wait[6]~29_combout ; +wire \data_rw_ctrl_inst|Equal2~0_combout ; +wire \data_rw_ctrl_inst|cnt_wait[13]~43_combout ; +wire \data_rw_ctrl_inst|cnt_wait[11]~39_combout ; +wire \data_rw_ctrl_inst|Equal2~1_combout ; +wire \data_rw_ctrl_inst|Equal2~2_combout ; +wire \data_rw_ctrl_inst|Equal2~4_combout ; +wire \data_rw_ctrl_inst|rd_fifo_rd_en~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_en~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~13_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~14_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~15_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~11_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~7_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~9_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~16_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~6_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~2_combout ; +wire \uart_tx_inst|Mux0~0_combout ; +wire \uart_tx_inst|tx~0_combout ; +wire \uart_tx_inst|tx~q ; +wire [3:0] \sd_ctrl_inst|sd_write_inst|cnt_data_bit ; +wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit ; +wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data_reg ; +wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_ack_bit ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_ack_bit ; +wire [12:0] \uart_tx_inst|baud_cnt ; +wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data ; +wire [2:0] \sd_ctrl_inst|sd_read_inst|cnt_end ; +wire [3:0] \uart_tx_inst|bit_cnt ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|ack_data ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|busy_data ; +wire [3:0] \sd_ctrl_inst|sd_read_inst|cnt_data_bit ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit ; +wire [15:0] \sd_ctrl_inst|sd_read_inst|byte_head ; +wire [11:0] \sd_ctrl_inst|sd_read_inst|cnt_data_num ; +wire [7:0] \sd_ctrl_inst|sd_read_inst|ack_data ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \uart_rx_inst|rx_data ; +wire [7:0] \uart_rx_inst|po_data ; +wire [3:0] \uart_rx_inst|bit_cnt ; +wire [12:0] \uart_rx_inst|baud_cnt ; +wire [11:0] \data_rw_ctrl_inst|send_data_num ; +wire [15:0] \data_rw_ctrl_inst|cnt_wait ; +wire [10:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ; +wire [8:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ; +wire [2:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a ; +wire [15:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ; +wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a ; +wire [2:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a ; +wire [7:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a ; +wire [8:0] \sd_ctrl_inst|sd_init_inst|cnt_wait ; +wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit ; +wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_ack_bit ; +wire [39:0] \sd_ctrl_inst|sd_init_inst|ack_data ; +wire [2:0] \sd_ctrl_inst|sd_write_inst|cnt_end ; +wire [11:0] \sd_ctrl_inst|sd_write_inst|cnt_data_num ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; +wire [17:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; +wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [9]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [10]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [11]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [12]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [13]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [14]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [15]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [16]; + +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 7; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "10000"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 5989; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0] $ (VCC))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # (GND))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .lut_mask = 16'h66DD; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y22_N19 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N13 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N7 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N11 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N13 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y13_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y16_N13 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X13_Y13_N0 +cycloneive_ram_block \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({gnd,\uart_rx_inst|po_data [7],\uart_rx_inst|po_data [6],\uart_rx_inst|po_data [5],\uart_rx_inst|po_data [4],\uart_rx_inst|po_data [3],\uart_rx_inst|po_data [2],\uart_rx_inst|po_data [1],\uart_rx_inst|po_data [0]}), + .portaaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(18'b000000000000000000), + .portbaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_wr_data:fifo_wr_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_uqf1:auto_generated|altsyncram_3011:fifo_ram|ALTSYNCRAM"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 8; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 9; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 18; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 511; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 512; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: M9K_X25_Y27_N0 +cycloneive_ram_block \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({gnd,\sd_ctrl_inst|sd_read_inst|rd_data [15],\sd_ctrl_inst|sd_read_inst|rd_data [14],\sd_ctrl_inst|sd_read_inst|rd_data [13],\sd_ctrl_inst|sd_read_inst|rd_data [12],\sd_ctrl_inst|sd_read_inst|rd_data [11],\sd_ctrl_inst|sd_read_inst|rd_data [10],\sd_ctrl_inst|sd_read_inst|rd_data [9], +\sd_ctrl_inst|sd_read_inst|rd_data [8],gnd,\sd_ctrl_inst|sd_read_inst|rd_data [7],\sd_ctrl_inst|sd_read_inst|rd_data [6],\sd_ctrl_inst|sd_read_inst|rd_data [5],\sd_ctrl_inst|sd_read_inst|rd_data [4],\sd_ctrl_inst|sd_read_inst|rd_data [3],\sd_ctrl_inst|sd_read_inst|rd_data [2], +\sd_ctrl_inst|sd_read_inst|rd_data [1],\sd_ctrl_inst|sd_read_inst|rd_data [0]}), + .portaaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_rd_data:fifo_rd_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_h0f1:auto_generated|altsyncram_4011:fifo_ram|ALTSYNCRAM"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 9; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 18; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 511; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 512; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 8; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: FF_X14_Y25_N11 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N23 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N25 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N27 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N11 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 )) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N25 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y16_N27 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y23_N11 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y23_N7 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h55AA; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N13 +dffeas \uart_tx_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y26_N7 +dffeas \uart_tx_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y26_N23 +dffeas \uart_tx_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout = \sd_ctrl_inst|sd_read_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout = \sd_ctrl_inst|sd_init_inst|cnt_wait [0] $ (VCC) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .lut_mask = 16'h55AA; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N6 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) +// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[1]~16 ), + .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_tx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N12 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[4]~22 ), + .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_tx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N22 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) +// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[9]~32 ), + .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_tx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N11 +dffeas \data_rw_ctrl_inst|cnt_wait[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q $ (GND) +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT = CARRY(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .cout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hAA55; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[5]~27 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[5]~27_combout = (\data_rw_ctrl_inst|cnt_wait [5] & (!\data_rw_ctrl_inst|cnt_wait[4]~25 )) # (!\data_rw_ctrl_inst|cnt_wait [5] & ((\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[5]~28 = CARRY((!\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (!\data_rw_ctrl_inst|cnt_wait [5])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[4]~25 ), + .combout(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[5]~28 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N12 +cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( +// Equation(s): +// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) +// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) + + .dataa(\uart_rx_inst|bit_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~3 ), + .combout(\uart_rx_inst|Add1~4_combout ), + .cout(\uart_rx_inst|Add1~5 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N11 +dffeas \uart_rx_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y16_N23 +dffeas \uart_rx_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N7 +dffeas \data_rw_ctrl_inst|send_data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[3]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N13 +dffeas \data_rw_ctrl_inst|send_data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[6]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N17 +dffeas \data_rw_ctrl_inst|send_data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[8]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N19 +dffeas \data_rw_ctrl_inst|send_data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[9]~30_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N21 +dffeas \data_rw_ctrl_inst|send_data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[10]~32_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[10] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N23 +dffeas \data_rw_ctrl_inst|send_data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[11]~34_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [11]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[11] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N10 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) +// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[3]~20 ), + .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_rx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N22 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) +// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[9]~32 ), + .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_rx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[3]~18 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[3]~18_combout = (\data_rw_ctrl_inst|send_data_num [3] & (!\data_rw_ctrl_inst|send_data_num[2]~17 )) # (!\data_rw_ctrl_inst|send_data_num [3] & ((\data_rw_ctrl_inst|send_data_num[2]~17 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[3]~19 = CARRY((!\data_rw_ctrl_inst|send_data_num[2]~17 ) # (!\data_rw_ctrl_inst|send_data_num [3])) + + .dataa(\data_rw_ctrl_inst|send_data_num [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[2]~17 ), + .combout(\data_rw_ctrl_inst|send_data_num[3]~18_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[3]~19 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[3]~18 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|send_data_num[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[6]~24 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[6]~24_combout = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num[5]~23 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [6] & (!\data_rw_ctrl_inst|send_data_num[5]~23 & VCC)) +// \data_rw_ctrl_inst|send_data_num[6]~25 = CARRY((\data_rw_ctrl_inst|send_data_num [6] & !\data_rw_ctrl_inst|send_data_num[5]~23 )) + + .dataa(\data_rw_ctrl_inst|send_data_num [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[5]~23 ), + .combout(\data_rw_ctrl_inst|send_data_num[6]~24_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[6]~25 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[6]~24 .lut_mask = 16'hA50A; +defparam \data_rw_ctrl_inst|send_data_num[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[7]~26 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[7]~26_combout = (\data_rw_ctrl_inst|send_data_num [7] & (!\data_rw_ctrl_inst|send_data_num[6]~25 )) # (!\data_rw_ctrl_inst|send_data_num [7] & ((\data_rw_ctrl_inst|send_data_num[6]~25 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[7]~27 = CARRY((!\data_rw_ctrl_inst|send_data_num[6]~25 ) # (!\data_rw_ctrl_inst|send_data_num [7])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [7]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[6]~25 ), + .combout(\data_rw_ctrl_inst|send_data_num[7]~26_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[7]~27 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[7]~26 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|send_data_num[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[8]~28 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[8]~28_combout = (\data_rw_ctrl_inst|send_data_num [8] & (\data_rw_ctrl_inst|send_data_num[7]~27 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num[7]~27 & VCC)) +// \data_rw_ctrl_inst|send_data_num[8]~29 = CARRY((\data_rw_ctrl_inst|send_data_num [8] & !\data_rw_ctrl_inst|send_data_num[7]~27 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [8]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[7]~27 ), + .combout(\data_rw_ctrl_inst|send_data_num[8]~28_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[8]~29 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[8]~28 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[9]~30 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[9]~30_combout = (\data_rw_ctrl_inst|send_data_num [9] & (!\data_rw_ctrl_inst|send_data_num[8]~29 )) # (!\data_rw_ctrl_inst|send_data_num [9] & ((\data_rw_ctrl_inst|send_data_num[8]~29 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[9]~31 = CARRY((!\data_rw_ctrl_inst|send_data_num[8]~29 ) # (!\data_rw_ctrl_inst|send_data_num [9])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [9]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[8]~29 ), + .combout(\data_rw_ctrl_inst|send_data_num[9]~30_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[9]~31 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[9]~30 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|send_data_num[9]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[10]~32 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[10]~32_combout = (\data_rw_ctrl_inst|send_data_num [10] & (\data_rw_ctrl_inst|send_data_num[9]~31 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num[9]~31 & VCC)) +// \data_rw_ctrl_inst|send_data_num[10]~33 = CARRY((\data_rw_ctrl_inst|send_data_num [10] & !\data_rw_ctrl_inst|send_data_num[9]~31 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [10]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[9]~31 ), + .combout(\data_rw_ctrl_inst|send_data_num[10]~32_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[10]~33 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[10]~32 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[10]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[11]~34 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[11]~34_combout = \data_rw_ctrl_inst|send_data_num [11] $ (\data_rw_ctrl_inst|send_data_num[10]~33 ) + + .dataa(\data_rw_ctrl_inst|send_data_num [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|send_data_num[10]~33 ), + .combout(\data_rw_ctrl_inst|send_data_num[11]~34_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[11]~34 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|send_data_num[11]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y23_N27 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_end [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~0_combout = (\sd_ctrl_inst|sd_init_inst|init_end~q & \data_rw_ctrl_inst|rd_en~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datad(\data_rw_ctrl_inst|rd_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal6~0_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .lut_mask = 16'h0303; +defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_write_inst|always4~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]), + .datad(\sd_ctrl_inst|sd_write_inst|always4~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~1 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_write_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_write_inst|always4~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~1_combout = (\sd_ctrl_inst|sd_write_inst|mosi~0_combout & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .lut_mask = 16'h0002; +defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux0~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & +// (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .lut_mask = 16'h0026; +defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]) # ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5])))) # +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .lut_mask = 16'hB9A8; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~1_combout = (\sd_ctrl_inst|sd_write_inst|Mux1~0_combout & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]) # ((!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~0_combout & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]), + .datab(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .lut_mask = 16'hB8CC; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~2_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b +// [14]))))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .lut_mask = 16'hEE30; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~3_combout = (\sd_ctrl_inst|sd_write_inst|Mux1~2_combout & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]))) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~2_combout & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .lut_mask = 16'hEA62; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~4_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b +// [15])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .lut_mask = 16'hDC98; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~5_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]))) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~4_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .lut_mask = 16'hF838; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~6_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & +// ((\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|Mux1~5_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .lut_mask = 16'hF2C2; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~7_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] & !\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .lut_mask = 16'hCCB8; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~8_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0])) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~7_combout & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]))))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]), + .datad(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .lut_mask = 16'hBBC0; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~6_combout = (\sd_ctrl_inst|sd_write_inst|Mux1~6_combout & (((\sd_ctrl_inst|sd_write_inst|Mux1~8_combout )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) # (!\sd_ctrl_inst|sd_write_inst|Mux1~6_combout & +// (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|Mux1~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .datac(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .lut_mask = 16'hE6A2; +defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~7_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]) # ((\sd_ctrl_inst|sd_write_inst|mosi~0_combout & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_write_inst|mosi~6_combout )) # +// (!\sd_ctrl_inst|sd_write_inst|mosi~0_combout & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]) # (\sd_ctrl_inst|sd_write_inst|mosi~6_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .datad(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .lut_mask = 16'hFDF4; +defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~1_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .lut_mask = 16'h1906; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~2_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & +// (\sd_ctrl_inst|sd_init_inst|Selector14~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .lut_mask = 16'h5044; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr14~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & +// ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .lut_mask = 16'h9998; +defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~3_combout = ((\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .lut_mask = 16'h0CFF; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~4_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & +// (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .lut_mask = 16'h11E0; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~5_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & !\sd_ctrl_inst|sd_init_inst|Selector14~4_combout )) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|Selector14~4_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .lut_mask = 16'h0108; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~6_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] $ (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .lut_mask = 16'h0902; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~7_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~6_combout & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .lut_mask = 16'h8100; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr12~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .lut_mask = 16'h5F60; +defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~8_combout = ((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]))) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .lut_mask = 16'h10FF; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~9_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~5_combout & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # ((\sd_ctrl_inst|sd_init_inst|Selector14~8_combout )))) # +// (!\sd_ctrl_inst|sd_init_inst|Selector14~5_combout & (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector14~8_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .lut_mask = 16'hA8FC; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~10_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~9_combout & (\sd_ctrl_inst|sd_init_inst|Selector14~3_combout & ((\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ) # +// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .lut_mask = 16'hC400; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N15 +dffeas \uart_tx_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[2]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N10 +cycloneive_lcell_comb \uart_tx_inst|always0~0 ( +// Equation(s): +// \uart_tx_inst|always0~0_combout = (!\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|bit_cnt [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~0 .lut_mask = 16'h000F; +defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N30 +cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( +// Equation(s): +// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b +// [4]))) # (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF2C2; +defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N24 +cycloneive_lcell_comb \uart_tx_inst|Mux0~2 ( +// Equation(s): +// \uart_tx_inst|Mux0~2_combout = (\uart_tx_inst|Mux0~1_combout & (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6])) # (!\uart_tx_inst|bit_cnt [1]))) # (!\uart_tx_inst|Mux0~1_combout & +// (\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]))) + + .dataa(\uart_tx_inst|Mux0~1_combout ), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~2 .lut_mask = 16'hEA62; +defparam \uart_tx_inst|Mux0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N26 +cycloneive_lcell_comb \uart_tx_inst|Mux0~3 ( +// Equation(s): +// \uart_tx_inst|Mux0~3_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\uart_tx_inst|bit_cnt [1] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]))))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~3 .lut_mask = 16'h88C0; +defparam \uart_tx_inst|Mux0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N28 +cycloneive_lcell_comb \uart_tx_inst|Mux0~4 ( +// Equation(s): +// \uart_tx_inst|Mux0~4_combout = (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] & \uart_tx_inst|bit_cnt [1])) + + .dataa(gnd), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~4 .lut_mask = 16'h3000; +defparam \uart_tx_inst|Mux0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N22 +cycloneive_lcell_comb \uart_tx_inst|Mux0~5 ( +// Equation(s): +// \uart_tx_inst|Mux0~5_combout = (\uart_tx_inst|bit_cnt [2] & (((\uart_tx_inst|Mux0~2_combout )))) # (!\uart_tx_inst|bit_cnt [2] & ((\uart_tx_inst|Mux0~3_combout ) # ((\uart_tx_inst|Mux0~4_combout )))) + + .dataa(\uart_tx_inst|Mux0~3_combout ), + .datab(\uart_tx_inst|Mux0~4_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|Mux0~2_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~5 .lut_mask = 16'hFE0E; +defparam \uart_tx_inst|Mux0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q & (\sd_ctrl_inst|sd_read_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0]))))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [2]), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .lut_mask = 16'h7800; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_read_inst|always3~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datad(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~1 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_read_inst|always3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N7 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~2_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [9])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~2 .lut_mask = 16'h0003; +defparam \sd_ctrl_inst|sd_read_inst|always3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .lut_mask = 16'hC33C; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .lut_mask = 16'hC33C; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal1~0_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector8~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector8~0_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [32] & (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout & (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector0~0_combout = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q & (\sd_ctrl_inst|sd_init_inst|Equal5~2_combout & ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q & +// ((\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout & \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .lut_mask = 16'hDC50; +defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal3~0_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [10] & (!\sd_ctrl_inst|sd_init_inst|ack_data [9] & (!\sd_ctrl_inst|sd_init_inst|ack_data [11] & \sd_ctrl_inst|sd_init_inst|ack_data [8]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [10]), + .datab(\sd_ctrl_inst|sd_init_inst|ack_data [9]), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [11]), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .lut_mask = 16'hFC00; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~1_combout = (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & ((\sd_ctrl_inst|sd_init_inst|ack_data [32]) # ((!\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_init_inst|Equal2~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .lut_mask = 16'hB0F0; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # +// (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & ((!\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .lut_mask = 16'hA0EC; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~3_combout = (\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & ((\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector6~1_combout +// )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .lut_mask = 16'hFECC; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~1_combout = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]) # ((!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .lut_mask = 16'hBF00; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal3~1_combout = (!\sd_ctrl_inst|sd_read_inst|ack_data [0] & (!\sd_ctrl_inst|sd_read_inst|ack_data [1] & (!\sd_ctrl_inst|sd_read_inst|ack_data [3] & !\sd_ctrl_inst|sd_read_inst|ack_data [2]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|ack_data [0]), + .datab(\sd_ctrl_inst|sd_read_inst|ack_data [1]), + .datac(\sd_ctrl_inst|sd_read_inst|ack_data [3]), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal3~1_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .lut_mask = 16'h0002; +defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal3~2_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|Equal3~1_combout & \sd_ctrl_inst|sd_write_inst|Equal3~0_combout )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .lut_mask = 16'h8800; +defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N13 +dffeas \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector2~0_combout = (\sd_ctrl_inst|sd_write_inst|Equal1~1_combout & (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout & \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Add3~0_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .lut_mask = 16'h78F0; +defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y14_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEDB7; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y14_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y15_N17 +dffeas \uart_rx_inst|po_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y15_N19 +dffeas \uart_rx_inst|po_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N21 +dffeas \uart_rx_inst|po_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N15 +dffeas \uart_rx_inst|po_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N9 +dffeas \uart_rx_inst|po_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N27 +dffeas \uart_rx_inst|po_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N13 +dffeas \uart_rx_inst|po_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N31 +dffeas \uart_rx_inst|po_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y27_N21 +dffeas \uart_tx_inst|work_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_tx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N6 +cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( +// Equation(s): +// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(gnd), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h3CF0; +defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N14 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~3 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[2]~3_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) + + .dataa(\uart_tx_inst|Add1~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2]~3 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N11 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y25_N31 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y24_N15 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~1_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head [0] & (\sd_ctrl_inst|sd_read_inst|byte_head [2] & (\sd_ctrl_inst|sd_read_inst|byte_head [1] & \sd_ctrl_inst|sd_read_inst|byte_head [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [2]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .lut_mask = 16'h000A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector3~0_combout = (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q & ((!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .lut_mask = 16'h3F00; +defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector3~1_combout = (\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_write_inst|Equal3~2_combout & \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q )) + + .dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .lut_mask = 16'hFFA0; +defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y14_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y14_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y15_N1 +dffeas \uart_rx_inst|rx_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N11 +dffeas \uart_rx_inst|rx_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N29 +dffeas \uart_rx_inst|rx_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N23 +dffeas \uart_rx_inst|rx_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y16_N27 +dffeas \uart_rx_inst|rx_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[7]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N25 +dffeas \uart_rx_inst|rx_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N3 +dffeas \uart_rx_inst|rx_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N5 +dffeas \uart_rx_inst|rx_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y27_N13 +dffeas \data_rw_ctrl_inst|tx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|tx_flag~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|tx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|tx_flag .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|tx_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N20 +cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( +// Equation(s): +// \uart_tx_inst|work_en~0_combout = (\data_rw_ctrl_inst|tx_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) + + .dataa(\data_rw_ctrl_inst|tx_flag~q ), + .datab(gnd), + .datac(\uart_tx_inst|work_en~q ), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hAAFA; +defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y28_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N1 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y27_N27 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y27_N23 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y27_N31 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~4_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [2]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [2]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~5_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [1]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~6_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [0] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~7_combout = (\sd_miso~input_o & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_miso~input_o ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_en~0_combout = (!\sd_miso~input_o & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q & \sd_ctrl_inst|sd_init_inst|miso_dly~q ))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .datac(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_en~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & \sd_ctrl_inst|sd_write_inst|ack_en~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N13 +dffeas \uart_rx_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N20 +cycloneive_lcell_comb \uart_rx_inst|always8~0 ( +// Equation(s): +// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always8~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8282; +defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N31 +dffeas \uart_rx_inst|rx_reg3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg3 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & !\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y16_N8 +cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( +// Equation(s): +// \uart_rx_inst|Equal2~0_combout = (!\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt [2] & \uart_rx_inst|baud_cnt [3]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0400; +defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y10_N1 +dffeas \uart_rx_inst|rx_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~2 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~2_combout = (\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num [11] & !\data_rw_ctrl_inst|send_data_num [9]))) + + .dataa(\data_rw_ctrl_inst|send_data_num [8]), + .datab(\data_rw_ctrl_inst|send_data_num [10]), + .datac(\data_rw_ctrl_inst|send_data_num [11]), + .datad(\data_rw_ctrl_inst|send_data_num [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~2 .lut_mask = 16'h0002; +defparam \data_rw_ctrl_inst|always3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N30 +cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( +// Equation(s): +// \uart_rx_inst|Equal1~2_combout = (\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [9]))) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [6]), + .datad(\uart_rx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y10_N3 +dffeas \uart_rx_inst|rx_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y16_N7 +dffeas \uart_rx_inst|start_nedge ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|start_nedge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; +defparam \uart_rx_inst|start_nedge .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N6 +cycloneive_lcell_comb \uart_rx_inst|always3~0 ( +// Equation(s): +// \uart_rx_inst|always3~0_combout = (!\uart_rx_inst|rx_reg3~q & \uart_rx_inst|rx_reg2~q ) + + .dataa(\uart_rx_inst|rx_reg3~q ), + .datab(gnd), + .datac(\uart_rx_inst|rx_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always3~0 .lut_mask = 16'h5050; +defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h0F0F; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N26 +cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( +// Equation(s): +// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|rx_reg3~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h0F0F; +defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y10_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( +// Equation(s): +// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rx~input_o ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \rx~input ( + .i(rx), + .ibar(gnd), + .o(\rx~input_o )); +// synopsys translate_off +defparam \rx~input .bus_hold = "false"; +defparam \rx~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y14_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|tx_flag~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|tx_flag~feeder_combout = \data_rw_ctrl_inst|rd_fifo_rd_en~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|tx_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|tx_flag~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|tx_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y14_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N16 +cycloneive_lcell_comb \uart_rx_inst|po_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[1]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N18 +cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N4 +cycloneive_lcell_comb \uart_rx_inst|rx_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[4]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N20 +cycloneive_lcell_comb \uart_rx_inst|po_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[6]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N10 +cycloneive_lcell_comb \uart_rx_inst|rx_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[5]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N8 +cycloneive_lcell_comb \uart_rx_inst|po_data[7]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[7]~feeder_combout = \uart_rx_inst|rx_data [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [7]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N28 +cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[6]~feeder_combout = \uart_rx_inst|rx_data [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [7]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N26 +cycloneive_lcell_comb \uart_rx_inst|po_data[3]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[3]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N22 +cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N12 +cycloneive_lcell_comb \uart_rx_inst|po_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[0]~feeder_combout = \uart_rx_inst|rx_data [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [0]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y10_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg1~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N23 +cycloneive_io_obuf \sd_clk~output ( + .i(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sd_clk), + .obar()); +// synopsys translate_off +defparam \sd_clk~output .bus_hold = "false"; +defparam \sd_clk~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N23 +cycloneive_io_obuf \sd_cs_n~output ( + .i(\sd_ctrl_inst|sd_cs_n~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sd_cs_n), + .obar()); +// synopsys translate_off +defparam \sd_cs_n~output .bus_hold = "false"; +defparam \sd_cs_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y29_N9 +cycloneive_io_obuf \sd_mosi~output ( + .i(\sd_ctrl_inst|sd_mosi~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sd_mosi), + .obar()); +// synopsys translate_off +defparam \sd_mosi~output .bus_hold = "false"; +defparam \sd_mosi~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y9_N16 +cycloneive_io_obuf \tx~output ( + .i(!\uart_tx_inst|tx~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tx), + .obar()); +// synopsys translate_off +defparam \tx~output .bus_hold = "false"; +defparam \tx~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout = \sd_ctrl_inst|sd_read_inst|cnt_data_num [0] $ (VCC) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y1_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y1_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y1_N26 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ) # (!\sys_rst_n~input_o )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\sys_rst_n~input_o ), + .datac(gnd), + .datad(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h77FF; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N29 +cycloneive_io_ibuf \sd_miso~input ( + .i(sd_miso), + .ibar(gnd), + .o(\sd_miso~input_o )); +// synopsys translate_off +defparam \sd_miso~input .bus_hold = "false"; +defparam \sd_miso~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X16_Y24_N25 +dffeas \sd_ctrl_inst|sd_init_inst|miso_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_miso~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|miso_dly .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|miso_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_en~0_combout = (!\sd_miso~input_o & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q & (\sd_ctrl_inst|sd_init_inst|miso_dly~q & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .lut_mask = 16'h0040; +defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N13 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_en~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|ack_en~0_combout & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .datab(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .lut_mask = 16'h0004; +defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N11 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal0~1_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_en~2_combout = (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout & (!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout & ((\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_read_inst|ack_en~q )))) # +// (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout & (((\sd_ctrl_inst|sd_read_inst|ack_en~q )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .lut_mask = 16'h50F8; +defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N3 +dffeas \sd_ctrl_inst|sd_read_inst|ack_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y24_N9 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N15 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N17 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N21 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N23 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal0~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout & \sd_ctrl_inst|sd_read_inst|ack_en~q )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .lut_mask = 16'h5000; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N23 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N29 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout = \sd_ctrl_inst|sd_read_inst|ack_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N19 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N25 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout = \sd_ctrl_inst|sd_read_inst|ack_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N31 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N21 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout = \sd_ctrl_inst|sd_read_inst|ack_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N27 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N17 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal3~0_combout = (!\sd_ctrl_inst|sd_read_inst|ack_data [6] & (!\sd_ctrl_inst|sd_read_inst|ack_data [5] & (!\sd_ctrl_inst|sd_read_inst|ack_data [7] & !\sd_ctrl_inst|sd_read_inst|ack_data [4]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|ack_data [6]), + .datab(\sd_ctrl_inst|sd_read_inst|ack_data [5]), + .datac(\sd_ctrl_inst|sd_read_inst|ack_data [7]), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal3~2_combout = (\sd_ctrl_inst|sd_read_inst|Equal3~1_combout & \sd_ctrl_inst|sd_read_inst|Equal3~0_combout ) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N9 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_en~0_combout = (!\sd_miso~input_o & (\sd_ctrl_inst|sd_init_inst|miso_dly~q & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .lut_mask = 16'h0004; +defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_en~1_combout = (!\sd_ctrl_inst|sd_init_inst|Equal6~2_combout & ((\sd_ctrl_inst|sd_init_inst|ack_en~q ) # ((\sd_ctrl_inst|sd_init_inst|ack_en~0_combout & \sd_ctrl_inst|sd_init_inst|Equal1~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .lut_mask = 16'h5450; +defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N3 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal1~1_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~0_combout & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3])) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .lut_mask = 16'h000A; +defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal1~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~1_combout & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout = (\sd_ctrl_inst|sd_init_inst|ack_en~q & (((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .lut_mask = 16'h04CC; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 )) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout = (\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .lut_mask = 16'h000C; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N21 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N19 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N23 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N3 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N31 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N27 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N15 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N5 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N1 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N25 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N13 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N7 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [10]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [11] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [11]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N11 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [12] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [12]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N29 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [13] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [14] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [14]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N9 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [15] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [15]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[16] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [16]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[17] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [16]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [17]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [17] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [17]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N19 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[18] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [18]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [18] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [18]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N25 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[19] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [19]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [19] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [19]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N23 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[20] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [20]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[21] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [20]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [21]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[22] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [21]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [22]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [22] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [22]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[23] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [23]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [23] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [23]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[24] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [24]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [24] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [24]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N29 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[25] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [25]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [25] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [25]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N27 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[26] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [26]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N9 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[27] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [26]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [27]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N31 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[28] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [27]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [28]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N21 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[29] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [28]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [29]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [29] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [29]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N3 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[30] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [30]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [30] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [30]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[31] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [31]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[32] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [31]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [32] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N29 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[33] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [33]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [33] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N25 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[34] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [34]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[35] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [34]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [35]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal2~1_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [34] & (!\sd_ctrl_inst|sd_init_inst|ack_data [35] & !\sd_ctrl_inst|sd_init_inst|ack_data [33])) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [34]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [35]), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .lut_mask = 16'h0005; +defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[36] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [35]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [36]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [36] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [36]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N3 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[37] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [37]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [37] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[38] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [38]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N21 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[39] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [38]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [39]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal2~0_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [36] & (!\sd_ctrl_inst|sd_init_inst|ack_data [38] & (!\sd_ctrl_inst|sd_init_inst|ack_data [39] & !\sd_ctrl_inst|sd_init_inst|ack_data [37]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [36]), + .datab(\sd_ctrl_inst|sd_init_inst|ack_data [38]), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [39]), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal2~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout & (\sd_ctrl_inst|sd_init_inst|ack_data [32] & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector0~1_combout = (\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .lut_mask = 16'hAAEA; +defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N19 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N21 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 )) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N25 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout = \sd_ctrl_inst|sd_init_inst|cnt_wait [8] $ (!\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .lut_mask = 16'hA5A5; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N27 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N23 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal0~1_combout = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [5]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .lut_mask = 16'h7FFF; +defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal0~2_combout = (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout & (\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .lut_mask = 16'h0030; +defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N17 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N13 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal0~0_combout = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [1]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [0]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .lut_mask = 16'h7FFF; +defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.IDLE~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q ) # ((\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .lut_mask = 16'hF0F2; +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N9 +dffeas \sd_ctrl_inst|sd_init_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|Selector8~0_combout & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .lut_mask = 16'hFAF0; +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N27 +dffeas \sd_ctrl_inst|sd_init_inst|state.INIT_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr18 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|WideOr18~combout = (\sd_ctrl_inst|sd_init_inst|Selector14~0_combout & !\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .lut_mask = 16'h0C0C; +defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N21 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N23 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal5~1_combout = ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .lut_mask = 16'hFDFF; +defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout = ((!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout & !\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .lut_mask = 16'h333F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N9 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal5~0_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .lut_mask = 16'hFFFE; +defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal5~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .lut_mask = 16'hFFF0; +defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector2~0_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & +// ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .lut_mask = 16'h50DC; +defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N27 +dffeas \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector1~0_combout = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & (((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & +// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .lut_mask = 16'hF444; +defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector1~1_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & ((\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # +// (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .lut_mask = 16'hF888; +defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N19 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector5~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector5~0_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & +// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .lut_mask = 16'h50DC; +defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector4~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # +// (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .lut_mask = 16'h22F2; +defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector7~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector7~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # +// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .lut_mask = 16'h22F2; +defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N25 +dffeas \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~0_combout = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q & (!\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector3~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .lut_mask = 16'hFC00; +defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector3~1_combout = (\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal2~2_combout & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .lut_mask = 16'hECCC; +defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector15~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ) # (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .lut_mask = 16'hFFFE; +defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector15~1_combout = (!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout & (!\sd_ctrl_inst|sd_init_inst|Equal5~1_combout & \sd_ctrl_inst|sd_init_inst|Selector15~0_combout )) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .lut_mask = 16'h1010; +defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector15~2_combout = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q & ((\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ) # (!\sd_ctrl_inst|sd_init_inst|Selector14~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .lut_mask = 16'hFABA; +defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|init_end ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|init_end .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|init_end .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~2_combout = (\data_rw_ctrl_inst|rd_en~q & (\sd_ctrl_inst|sd_init_inst|init_end~q & !\sd_ctrl_inst|sd_read_inst|state.IDLE~q )) + + .dataa(\data_rw_ctrl_inst|rd_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .lut_mask = 16'h00A0; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~3_combout = (\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ) # ((\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ) # ((!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout & \sd_ctrl_inst|sd_read_inst|Selector2~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .lut_mask = 16'hFBFA; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N17 +dffeas \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N5 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N9 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N15 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N17 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal2~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .lut_mask = 16'h0040; +defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N7 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal2~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .lut_mask = 16'hA000; +defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector3~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|Equal2~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal2~0_combout & \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector3~1_combout = (\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q & ((!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .lut_mask = 16'hDCFC; +defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N9 +dffeas \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector2~0_combout = (\sd_ctrl_inst|sd_read_inst|Equal0~1_combout & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q & \sd_ctrl_inst|sd_read_inst|Equal0~0_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .lut_mask = 16'h8080; +defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector2~1_combout = (\sd_ctrl_inst|sd_read_inst|Equal3~2_combout & ((\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ) # ((!\sd_ctrl_inst|sd_read_inst|always3~4_combout & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # +// (!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout & (!\sd_ctrl_inst|sd_read_inst|always3~4_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .lut_mask = 16'hBA30; +defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N29 +dffeas \sd_ctrl_inst|sd_read_inst|state.RD_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N13 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N7 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout = (\sd_ctrl_inst|sd_read_inst|always3~2_combout & (\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout & (\sd_ctrl_inst|sd_read_inst|always3~0_combout & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .lut_mask = 16'h0080; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .lut_mask = 16'h0048; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Add3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Add3~0_combout = \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .lut_mask = 16'h5FA0; +defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (\sd_ctrl_inst|sd_read_inst|Add3~0_combout & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .lut_mask = 16'h00A0; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal9~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal9~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .lut_mask = 16'hA000; +defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~11_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [11]), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N31 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~10_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [12]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [12]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N29 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~9_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [13]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N27 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~8_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [14]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N17 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~2_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [12] & (\sd_ctrl_inst|sd_read_inst|byte_head [13] & (\sd_ctrl_inst|sd_read_inst|byte_head [14] & \sd_ctrl_inst|sd_read_inst|byte_head [15]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [12]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [13]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [15]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~14_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [8] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [8]), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N23 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~13_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [9]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [9]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~12_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [10]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [10]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N11 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~15_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [7]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [7]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N3 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~3_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [9] & (\sd_ctrl_inst|sd_read_inst|byte_head [10] & (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head [8]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [9]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [10]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [11]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~4_combout = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout = (!\sd_ctrl_inst|sd_read_inst|Equal6~4_combout & ((\sd_ctrl_inst|sd_read_inst|byte_head_en~q ) # ((\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout & \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout +// )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .lut_mask = 16'h00F8; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N15 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~1_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [5] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [5]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .lut_mask = 16'h8888; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N27 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~0_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [6]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N9 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~3_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [3] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [3]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .lut_mask = 16'h8888; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N23 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~2_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [4]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [4]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N13 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~0_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [4] & (\sd_ctrl_inst|sd_read_inst|byte_head [7] & (\sd_ctrl_inst|sd_read_inst|byte_head [6] & \sd_ctrl_inst|sd_read_inst|byte_head [5]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [4]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [7]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3])))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .lut_mask = 16'h0028; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N1 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ) # ((\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))) # +// (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .lut_mask = 16'hFDF5; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N9 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N15 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N17 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N21 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~3_combout = (\sd_ctrl_inst|sd_read_inst|always3~2_combout & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~3 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|always3~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~4_combout = (\sd_ctrl_inst|sd_read_inst|always3~1_combout & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_read_inst|always3~3_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|always3~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~4 .lut_mask = 16'h8800; +defparam \sd_ctrl_inst|sd_read_inst|always3~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector4~0_combout = (\sd_ctrl_inst|sd_read_inst|Selector0~0_combout & (\sd_ctrl_inst|sd_read_inst|always3~4_combout & ((\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout & +// ((\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # ((\sd_ctrl_inst|sd_read_inst|always3~4_combout & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .lut_mask = 16'hDC50; +defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N23 +dffeas \sd_ctrl_inst|sd_read_inst|state.RD_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_end [0] & \sd_ctrl_inst|sd_read_inst|state.RD_END~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N21 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q & (\sd_ctrl_inst|sd_read_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_end [1]))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .lut_mask = 16'h3C00; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N31 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector0~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_end [2] & (\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [2]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .lut_mask = 16'hA000; +defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector0~1_combout = (\sd_ctrl_inst|sd_read_inst|Selector1~0_combout & (((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q )) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|sd_read_inst|Selector1~0_combout +// & (\sd_ctrl_inst|sd_read_inst|state.IDLE~q & ((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .lut_mask = 16'h32FA; +defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N3 +dffeas \sd_ctrl_inst|sd_read_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_num [0] $ (VCC) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout = \sd_ctrl_inst|sd_init_inst|miso_dly~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y23_N1 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N3 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N5 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N9 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y23_N13 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal1~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal1~1_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_en~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout & (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout & ((\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_write_inst|ack_en~q )))) # +// (!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout & (((\sd_ctrl_inst|sd_write_inst|ack_en~q )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .lut_mask = 16'h30F8; +defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y23_N29 +dffeas \sd_ctrl_inst|sd_write_inst|ack_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|ack_en~q & \sd_ctrl_inst|sd_write_inst|Equal1~0_combout )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .lut_mask = 16'h4400; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N23 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N29 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout = \sd_ctrl_inst|sd_write_inst|ack_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N19 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N25 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal4~1_combout = (!\sd_ctrl_inst|sd_write_inst|ack_data [0] & (!\sd_ctrl_inst|sd_write_inst|ack_data [1] & (!\sd_ctrl_inst|sd_write_inst|ack_data [3] & !\sd_ctrl_inst|sd_write_inst|ack_data [2]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|ack_data [0]), + .datab(\sd_ctrl_inst|sd_write_inst|ack_data [1]), + .datac(\sd_ctrl_inst|sd_write_inst|ack_data [3]), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout = \sd_ctrl_inst|sd_write_inst|ack_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N31 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N21 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout = \sd_ctrl_inst|sd_write_inst|ack_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N27 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N1 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal4~0_combout = (!\sd_ctrl_inst|sd_write_inst|ack_data [6] & (!\sd_ctrl_inst|sd_write_inst|ack_data [5] & (!\sd_ctrl_inst|sd_write_inst|ack_data [7] & !\sd_ctrl_inst|sd_write_inst|ack_data [4]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|ack_data [6]), + .datab(\sd_ctrl_inst|sd_write_inst|ack_data [5]), + .datac(\sd_ctrl_inst|sd_write_inst|ack_data [7]), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal4~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal4~1_combout & \sd_ctrl_inst|sd_write_inst|Equal4~0_combout ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .lut_mask = 16'hCC00; +defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector2~1_combout = (\sd_ctrl_inst|sd_write_inst|Selector2~0_combout & ((\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ) # ((!\sd_ctrl_inst|sd_write_inst|always4~3_combout & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))) +// # (!\sd_ctrl_inst|sd_write_inst|Selector2~0_combout & (!\sd_ctrl_inst|sd_write_inst|always4~3_combout & (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .lut_mask = 16'hBA30; +defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N1 +dffeas \sd_ctrl_inst|sd_write_inst|state.WR_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y13_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Add3~2_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y13_N21 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Add3~1_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .lut_mask = 16'h3CF0; +defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y13_N3 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit +// [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .lut_mask = 16'hFF0F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X10_Y16_N5 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N9 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N19 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N21 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N25 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N27 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N23 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~2 .lut_mask = 16'h0002; +defparam \sd_ctrl_inst|sd_write_inst|always4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~3_combout = (\sd_ctrl_inst|sd_write_inst|always4~1_combout & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~2_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|always4~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_write_inst|always4~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~3 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|always4~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector4~0_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q & ((\sd_ctrl_inst|sd_write_inst|always4~3_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout )))) # +// (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q & (((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .lut_mask = 16'h88F8; +defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N17 +dffeas \sd_ctrl_inst|sd_write_inst|state.WR_BUSY ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~8_combout = (\sd_miso~input_o & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(\sd_miso~input_o ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N27 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~7_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [0]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N9 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~6_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [1] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [1]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N31 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~5_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N13 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal6~1_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & (\sd_ctrl_inst|sd_write_inst|busy_data [1] & (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|busy_data [3]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|busy_data [0]), + .datab(\sd_ctrl_inst|sd_write_inst|busy_data [1]), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]), + .datad(\sd_ctrl_inst|sd_write_inst|busy_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~4_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [3] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(\sd_ctrl_inst|sd_write_inst|busy_data [3]), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N25 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~3_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|busy_data [4]), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .lut_mask = 16'hCC00; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N15 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~2_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [5] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [5]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N5 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~1_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N19 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal6~0_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & (\sd_ctrl_inst|sd_write_inst|busy_data [5] & (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|busy_data [7]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|busy_data [4]), + .datab(\sd_ctrl_inst|sd_write_inst|busy_data [5]), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]), + .datad(\sd_ctrl_inst|sd_write_inst|busy_data [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal6~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal6~1_combout & \sd_ctrl_inst|sd_write_inst|Equal6~0_combout ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .lut_mask = 16'hCC00; +defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector5~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector5~0_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & ((\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_END~q & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) # +// (!\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & (((\sd_ctrl_inst|sd_write_inst|state.WR_END~q & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .datab(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .lut_mask = 16'h88F8; +defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N5 +dffeas \sd_ctrl_inst|sd_write_inst|state.WR_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_end [1]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .lut_mask = 16'h5A00; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|state.WR_END~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N23 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q & (\sd_ctrl_inst|sd_write_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [1]))))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [2]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .lut_mask = 16'h7800; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N29 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_end [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector0~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_end [1] & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [2])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_end [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cs_n~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cs_n~0_combout = (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout & ((\sd_ctrl_inst|comb~2_combout ) # (\sd_ctrl_inst|sd_write_inst|cs_n~q ))) + + .dataa(\sd_ctrl_inst|comb~2_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .lut_mask = 16'h00FA; +defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N3 +dffeas \sd_ctrl_inst|sd_write_inst|cs_n ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cs_n~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cs_n .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cs_n .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector0~1_combout = (\sd_ctrl_inst|comb~2_combout & (((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q )) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|comb~2_combout & +// (\sd_ctrl_inst|sd_write_inst|state.IDLE~q & ((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q ) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) + + .dataa(\sd_ctrl_inst|comb~2_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .lut_mask = 16'h32FA; +defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N9 +dffeas \sd_ctrl_inst|sd_write_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_dly~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|wr_busy_dly~feeder_combout = \sd_ctrl_inst|sd_write_inst|state.IDLE~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N19 +dffeas \data_rw_ctrl_inst|wr_busy_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|wr_busy_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|wr_busy_dly .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|wr_busy_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_fall~0 ( +// Equation(s): +// \data_rw_ctrl_inst|wr_busy_fall~0_combout = (\data_rw_ctrl_inst|wr_busy_dly~q & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|wr_busy_dly~q ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|wr_busy_fall~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|wr_busy_fall~0 .lut_mask = 16'h00CC; +defparam \data_rw_ctrl_inst|wr_busy_fall~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N11 +dffeas \data_rw_ctrl_inst|rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|wr_busy_fall~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|rd_en .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cs_n~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cs_n~2_combout = (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout & ((\sd_ctrl_inst|sd_read_inst|cs_n~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q & \data_rw_ctrl_inst|rd_en~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cs_n~q ), + .datad(\data_rw_ctrl_inst|rd_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .lut_mask = 16'h3230; +defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N25 +dffeas \sd_ctrl_inst|sd_read_inst|cs_n ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cs_n~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cs_n .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cs_n .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_cs_n~0_combout = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_write_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_read_inst|cs_n~q )) # +// (!\sd_ctrl_inst|sd_read_inst|state.IDLE~q ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .datab(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_read_inst|cs_n~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_cs_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_cs_n~0 .lut_mask = 16'h1B5F; +defparam \sd_ctrl_inst|sd_cs_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~1_combout = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q & !\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q )) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .lut_mask = 16'h0101; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal6~1_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~0_combout = ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]) # (\sd_ctrl_inst|sd_init_inst|Equal6~1_combout )))) # (!\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .lut_mask = 16'hDDD5; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal6~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|Equal6~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .lut_mask = 16'h0800; +defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_init_inst|Selector13~0_combout & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal6~2_combout )))) +// # (!\sd_ctrl_inst|sd_init_inst|Equal6~0_combout & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal6~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .lut_mask = 16'hF5C4; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~3_combout = ((\sd_ctrl_inst|sd_init_inst|Selector15~0_combout & ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # (\sd_ctrl_inst|sd_init_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .lut_mask = 16'hA8FF; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cs_n ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cs_n~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cs_n .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cs_n .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_cs_n~1_combout = (\sd_ctrl_inst|sd_init_inst|init_end~q & (\sd_ctrl_inst|sd_cs_n~0_combout )) # (!\sd_ctrl_inst|sd_init_inst|init_end~q & ((!\sd_ctrl_inst|sd_init_inst|cs_n~q ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_cs_n~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_cs_n~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_cs_n~1 .lut_mask = 16'hCC0F; +defparam \sd_ctrl_inst|sd_cs_n~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~11_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~10_combout & (((\sd_ctrl_inst|sd_init_inst|mosi~q & !\sd_ctrl_inst|sd_init_inst|Selector14~0_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Selector14~10_combout & +// ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|mosi~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|mosi~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .lut_mask = 16'h54F4; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|mosi ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|mosi~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|mosi .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|mosi .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|mosi~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] $ (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5])))) # +// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .lut_mask = 16'hEC84; +defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N11 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|mosi~1_combout = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] $ (((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|mosi~0_combout & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3])))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .lut_mask = 16'hF0B4; +defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|mosi~2_combout = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_read_inst|mosi~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ))) # +// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((!\sd_ctrl_inst|sd_read_inst|mosi~1_combout ))))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .lut_mask = 16'hA700; +defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N1 +dffeas \sd_ctrl_inst|sd_read_inst|mosi ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|mosi~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|mosi .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q $ (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT = CARRY(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hCC33; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h0F0F; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N8 +cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( +// Equation(s): +// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] & VCC)) +// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [0])) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|Add1~0_combout ), + .cout(\uart_rx_inst|Add1~1 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; +defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N10 +cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( +// Equation(s): +// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) +// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~1 ), + .combout(\uart_rx_inst|Add1~2_combout ), + .cout(\uart_rx_inst|Add1~3 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N14 +cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( +// Equation(s): +// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|bit_cnt [3] $ (\uart_rx_inst|Add1~5 ) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(gnd), + .datad(gnd), + .cin(\uart_rx_inst|Add1~5 ), + .combout(\uart_rx_inst|Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h3C3C; +defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N4 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~0_combout = (\uart_rx_inst|Add1~6_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q ))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|Add1~6_combout ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h4CCC; +defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N5 +dffeas \uart_rx_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N24 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~1_combout = (\uart_rx_inst|Add1~0_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q ))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(\uart_rx_inst|Add1~0_combout ), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h70F0; +defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N25 +dffeas \uart_rx_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y16_N11 +dffeas \uart_rx_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N18 +cycloneive_lcell_comb \uart_rx_inst|always4~0 ( +// Equation(s): +// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [2]), + .datab(\uart_rx_inst|bit_cnt [0]), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_rx_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0011; +defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N2 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) +// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_rx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N0 +cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( +// Equation(s): +// \uart_rx_inst|Equal1~0_combout = (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [1] & \uart_rx_inst|baud_cnt [0]))) + + .dataa(\uart_rx_inst|baud_cnt [8]), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(\uart_rx_inst|baud_cnt [1]), + .datad(\uart_rx_inst|baud_cnt [0]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h1000; +defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N12 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) + + .dataa(\uart_rx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[4]~22 ), + .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_rx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N13 +dffeas \uart_rx_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N6 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) +// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_rx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[1]~16 ), + .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_rx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N7 +dffeas \uart_rx_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y16_N10 +cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( +// Equation(s): +// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N2 +cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( +// Equation(s): +// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|Equal1~2_combout & (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal1~1_combout ))) + + .dataa(\uart_rx_inst|Equal1~2_combout ), + .datab(\uart_rx_inst|baud_cnt [12]), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h8000; +defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N16 +cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( +// Equation(s): +// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) + + .dataa(\uart_rx_inst|start_nedge~q ), + .datab(gnd), + .datac(\uart_rx_inst|work_en~q ), + .datad(\uart_rx_inst|always4~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hAAFA; +defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N17 +dffeas \uart_rx_inst|work_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_rx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N28 +cycloneive_lcell_comb \uart_rx_inst|always5~0 ( +// Equation(s): +// \uart_rx_inst|always5~0_combout = (\uart_rx_inst|Equal1~3_combout ) # (!\uart_rx_inst|work_en~q ) + + .dataa(gnd), + .datab(\uart_rx_inst|Equal1~3_combout ), + .datac(gnd), + .datad(\uart_rx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_rx_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always5~0 .lut_mask = 16'hCCFF; +defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y16_N3 +dffeas \uart_rx_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N4 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[0]~14 ), + .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_rx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N5 +dffeas \uart_rx_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N8 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[2]~18 ), + .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_rx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N9 +dffeas \uart_rx_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N14 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) +// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[5]~24 ), + .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_rx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N15 +dffeas \uart_rx_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N16 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[6]~26 ), + .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_rx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N17 +dffeas \uart_rx_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N18 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) +// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[7]~28 ), + .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_rx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N19 +dffeas \uart_rx_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N20 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[8]~30 ), + .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_rx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N21 +dffeas \uart_rx_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N24 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[10]~34 ), + .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_rx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N25 +dffeas \uart_rx_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N26 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt [12] $ (!\uart_rx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_rx_inst|baud_cnt[11]~36 ), + .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N27 +dffeas \uart_rx_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N28 +cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( +// Equation(s): +// \uart_rx_inst|Equal2~1_combout = (!\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & \uart_rx_inst|baud_cnt [9]))) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [6]), + .datad(\uart_rx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0400; +defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N22 +cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( +// Equation(s): +// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal2~0_combout & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal2~1_combout ))) + + .dataa(\uart_rx_inst|Equal2~0_combout ), + .datab(\uart_rx_inst|baud_cnt [12]), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal2~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000; +defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N23 +dffeas \uart_rx_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Equal2~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N0 +cycloneive_lcell_comb \uart_rx_inst|always4~1 ( +// Equation(s): +// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|always4~0_combout & (\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [3])) + + .dataa(gnd), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~1 .lut_mask = 16'hC000; +defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N1 +dffeas \uart_rx_inst|rx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always4~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_flag .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N1 +dffeas \uart_rx_inst|po_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_flag~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_flag .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0010; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .lut_mask = 16'h0500; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'hA5F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .lut_mask = 16'hF05A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y12_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X12_Y12_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h6FF6; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|always4~2_combout & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|always4~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'h3020; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hE1F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h0040; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h3CC3; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h3333; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout = (\uart_rx_inst|po_flag~q & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .datab(\uart_rx_inst|po_flag~q ), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hCC88; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout & (\uart_rx_inst|po_flag~q & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .datac(\uart_rx_inst|po_flag~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'hC080; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0100; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q )) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h6969; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'hF00F; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h2000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0200; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0300; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y12_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout )) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X16_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y12_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y12_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .lut_mask = 16'h78F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y12_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )))) # (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .lut_mask = 16'h964D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )))) # (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & +// ((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .lut_mask = 16'h962B; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )))) # (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .lut_mask = 16'h964D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N4 +cycloneive_lcell_comb \sd_ctrl_inst|comb~1 ( +// Equation(s): +// \sd_ctrl_inst|comb~1_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|comb~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|comb~1 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|comb~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N0 +cycloneive_lcell_comb \sd_ctrl_inst|comb~0 ( +// Equation(s): +// \sd_ctrl_inst|comb~0_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout & (\sd_ctrl_inst|sd_init_inst|init_end~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|comb~0 .lut_mask = 16'h0004; +defparam \sd_ctrl_inst|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N2 +cycloneive_lcell_comb \sd_ctrl_inst|comb~2 ( +// Equation(s): +// \sd_ctrl_inst|comb~2_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout & +// (\sd_ctrl_inst|comb~1_combout & \sd_ctrl_inst|comb~0_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ), + .datac(\sd_ctrl_inst|comb~1_combout ), + .datad(\sd_ctrl_inst|comb~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|comb~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|comb~2 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|comb~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector1~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal3~2_combout & (((\sd_ctrl_inst|comb~2_combout & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )))) # (!\sd_ctrl_inst|sd_write_inst|Equal3~2_combout & +// ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # ((\sd_ctrl_inst|comb~2_combout & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datac(\sd_ctrl_inst|comb~2_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .lut_mask = 16'h44F4; +defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector1~3_combout = (\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|Selector2~0_combout & ((!\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal4~1_combout +// )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .lut_mask = 16'hF2FA; +defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N15 +dffeas \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N19 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux0~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))) # +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .lut_mask = 16'h00E8; +defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N21 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y16_N23 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~2_combout = (!\sd_ctrl_inst|sd_write_inst|Mux0~0_combout & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .lut_mask = 16'h0030; +defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal3~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~3_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & +// (\sd_ctrl_inst|sd_write_inst|Mux0~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .lut_mask = 16'h0E02; +defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~4_combout = (\sd_ctrl_inst|sd_write_inst|mosi~1_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q & ((\sd_ctrl_inst|sd_write_inst|mosi~2_combout ) # (\sd_ctrl_inst|sd_write_inst|mosi~3_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datad(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .lut_mask = 16'hFAEA; +defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~5_combout = (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .lut_mask = 16'h3323; +defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~8_combout = (!\sd_ctrl_inst|sd_write_inst|mosi~4_combout & (!\sd_ctrl_inst|sd_write_inst|mosi~5_combout & ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # (!\sd_ctrl_inst|sd_write_inst|mosi~7_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datac(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .lut_mask = 16'h000D; +defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X11_Y16_N17 +dffeas \sd_ctrl_inst|sd_write_inst|mosi ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|mosi~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|mosi .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_mosi~0_combout = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_write_inst|mosi~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q )) # +// (!\sd_ctrl_inst|sd_read_inst|mosi~q ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .datab(\sd_ctrl_inst|sd_read_inst|mosi~q ), + .datac(\sd_ctrl_inst|sd_write_inst|mosi~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_mosi~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_mosi~0 .lut_mask = 16'h1B5F; +defparam \sd_ctrl_inst|sd_mosi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_mosi~1_combout = (\sd_ctrl_inst|sd_init_inst|init_end~q & ((\sd_ctrl_inst|sd_mosi~0_combout ))) # (!\sd_ctrl_inst|sd_init_inst|init_end~q & (!\sd_ctrl_inst|sd_init_inst|mosi~q )) + + .dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|mosi~q ), + .datad(\sd_ctrl_inst|sd_mosi~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_mosi~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_mosi~1 .lut_mask = 16'hAF05; +defparam \sd_ctrl_inst|sd_mosi~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N2 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) +// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_tx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N0 +cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( +// Equation(s): +// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt [3] & \uart_tx_inst|baud_cnt [0]))) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(\uart_tx_inst|baud_cnt [3]), + .datad(\uart_tx_inst|baud_cnt [0]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0100; +defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N2 +cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( +// Equation(s): +// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|Equal1~0_combout & (!\uart_tx_inst|baud_cnt [11] & !\uart_tx_inst|baud_cnt [9]))) + + .dataa(\uart_tx_inst|baud_cnt [8]), + .datab(\uart_tx_inst|Equal1~0_combout ), + .datac(\uart_tx_inst|baud_cnt [11]), + .datad(\uart_tx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0004; +defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N10 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) +// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[3]~20 ), + .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_tx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N11 +dffeas \uart_tx_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N30 +cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( +// Equation(s): +// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4]))) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; +defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N16 +cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( +// Equation(s): +// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [10] & \uart_tx_inst|baud_cnt [12]) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(gnd), + .datac(\uart_tx_inst|baud_cnt [12]), + .datad(gnd), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hA0A0; +defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N26 +cycloneive_lcell_comb \uart_tx_inst|always1~0 ( +// Equation(s): +// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~1_combout & (\uart_tx_inst|Equal1~2_combout & \uart_tx_inst|Equal1~3_combout ))) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|Equal1~1_combout ), + .datac(\uart_tx_inst|Equal1~2_combout ), + .datad(\uart_tx_inst|Equal1~3_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555; +defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y26_N3 +dffeas \uart_tx_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N4 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[0]~14 ), + .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_tx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N5 +dffeas \uart_tx_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N8 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[2]~18 ), + .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_tx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N9 +dffeas \uart_tx_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N14 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) +// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[5]~24 ), + .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_tx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N15 +dffeas \uart_tx_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N16 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[6]~26 ), + .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_tx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N17 +dffeas \uart_tx_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N18 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) +// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[7]~28 ), + .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_tx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N19 +dffeas \uart_tx_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N20 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[8]~30 ), + .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_tx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N21 +dffeas \uart_tx_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N24 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[10]~34 ), + .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_tx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N25 +dffeas \uart_tx_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N26 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_tx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_tx_inst|baud_cnt[11]~36 ), + .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N27 +dffeas \uart_tx_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N28 +cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( +// Equation(s): +// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [4]))) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N24 +cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( +// Equation(s): +// \uart_tx_inst|Equal2~1_combout = (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt [12] & (\uart_tx_inst|Equal2~0_combout & \uart_tx_inst|Equal1~1_combout ))) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(\uart_tx_inst|Equal2~0_combout ), + .datad(\uart_tx_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h1000; +defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N25 +dffeas \uart_tx_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|Equal2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N18 +cycloneive_lcell_comb \uart_tx_inst|always3~0 ( +// Equation(s): +// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(gnd), + .datac(gnd), + .datad(\uart_tx_inst|bit_flag~q ), + .cin(gnd), + .combout(\uart_tx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always3~0 .lut_mask = 16'h55FF; +defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N12 +cycloneive_lcell_comb \uart_tx_inst|always0~1 ( +// Equation(s): +// \uart_tx_inst|always0~1_combout = (\uart_tx_inst|always0~0_combout & (\uart_tx_inst|bit_flag~q & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [3]))) + + .dataa(\uart_tx_inst|always0~0_combout ), + .datab(\uart_tx_inst|bit_flag~q ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_tx_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~1 .lut_mask = 16'h8000; +defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N4 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|work_en~q & \uart_tx_inst|bit_flag~q ))))) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|bit_flag~q ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h0078; +defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N5 +dffeas \uart_tx_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[0]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N0 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~4 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[1]~4_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) + + .dataa(\uart_tx_inst|always0~1_combout ), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_tx_inst|bit_cnt [1]), + .datad(\uart_tx_inst|always3~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1]~4 .lut_mask = 16'h5014; +defparam \uart_tx_inst|bit_cnt[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N1 +dffeas \uart_tx_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[1]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N16 +cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( +// Equation(s): +// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [2] & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1])))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|bit_cnt [3]), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h6CCC; +defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N2 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~2 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[3]~2_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & (\uart_tx_inst|bit_cnt [3])) # (!\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|Add1~0_combout ))))) + + .dataa(\uart_tx_inst|always0~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|Add1~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3]~2 .lut_mask = 16'h5140; +defparam \uart_tx_inst|bit_cnt[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N3 +dffeas \uart_tx_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[3]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[0]~16 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[0]~16_combout = \data_rw_ctrl_inst|cnt_wait [0] $ (VCC) +// \data_rw_ctrl_inst|cnt_wait[0]~17 = CARRY(\data_rw_ctrl_inst|cnt_wait [0]) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[0]~17 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[3]~22 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[3]~22_combout = (\data_rw_ctrl_inst|cnt_wait [3] & (!\data_rw_ctrl_inst|cnt_wait[2]~21 )) # (!\data_rw_ctrl_inst|cnt_wait [3] & ((\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[3]~23 = CARRY((!\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (!\data_rw_ctrl_inst|cnt_wait [3])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[2]~21 ), + .combout(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[3]~23 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[4]~24 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[4]~24_combout = (\data_rw_ctrl_inst|cnt_wait [4] & (\data_rw_ctrl_inst|cnt_wait[3]~23 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [4] & (!\data_rw_ctrl_inst|cnt_wait[3]~23 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[4]~25 = CARRY((\data_rw_ctrl_inst|cnt_wait [4] & !\data_rw_ctrl_inst|cnt_wait[3]~23 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [4]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[3]~23 ), + .combout(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[4]~25 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N9 +dffeas \data_rw_ctrl_inst|cnt_wait[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal3~0_combout = (\data_rw_ctrl_inst|cnt_wait [4]) # (!\data_rw_ctrl_inst|cnt_wait [5]) + + .dataa(\data_rw_ctrl_inst|cnt_wait [5]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|cnt_wait [4]), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal3~0 .lut_mask = 16'hF5F5; +defparam \data_rw_ctrl_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N15 +dffeas \data_rw_ctrl_inst|rd_busy_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|rd_busy_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|rd_busy_dly .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|rd_busy_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[0]~12 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[0]~12_combout = \data_rw_ctrl_inst|send_data_num [0] $ (VCC) +// \data_rw_ctrl_inst|send_data_num[0]~13 = CARRY(\data_rw_ctrl_inst|send_data_num [0]) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|send_data_num[0]~12_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[0]~13 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[0]~12 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|send_data_num[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y26_N1 +dffeas \data_rw_ctrl_inst|send_data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[0]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[1]~14 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[1]~14_combout = (\data_rw_ctrl_inst|send_data_num [1] & (!\data_rw_ctrl_inst|send_data_num[0]~13 )) # (!\data_rw_ctrl_inst|send_data_num [1] & ((\data_rw_ctrl_inst|send_data_num[0]~13 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[1]~15 = CARRY((!\data_rw_ctrl_inst|send_data_num[0]~13 ) # (!\data_rw_ctrl_inst|send_data_num [1])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [1]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[0]~13 ), + .combout(\data_rw_ctrl_inst|send_data_num[1]~14_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[1]~15 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[1]~14 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|send_data_num[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N3 +dffeas \data_rw_ctrl_inst|send_data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[1]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[2]~16 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[2]~16_combout = (\data_rw_ctrl_inst|send_data_num [2] & (\data_rw_ctrl_inst|send_data_num[1]~15 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [2] & (!\data_rw_ctrl_inst|send_data_num[1]~15 & VCC)) +// \data_rw_ctrl_inst|send_data_num[2]~17 = CARRY((\data_rw_ctrl_inst|send_data_num [2] & !\data_rw_ctrl_inst|send_data_num[1]~15 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [2]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[1]~15 ), + .combout(\data_rw_ctrl_inst|send_data_num[2]~16_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[2]~17 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[2]~16 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N5 +dffeas \data_rw_ctrl_inst|send_data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[2]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~0_combout = (\data_rw_ctrl_inst|send_data_num [3] & (\data_rw_ctrl_inst|send_data_num [1] & (\data_rw_ctrl_inst|send_data_num [2] & \data_rw_ctrl_inst|send_data_num [0]))) + + .dataa(\data_rw_ctrl_inst|send_data_num [3]), + .datab(\data_rw_ctrl_inst|send_data_num [1]), + .datac(\data_rw_ctrl_inst|send_data_num [2]), + .datad(\data_rw_ctrl_inst|send_data_num [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~0 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[4]~20 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[4]~20_combout = (\data_rw_ctrl_inst|send_data_num [4] & (\data_rw_ctrl_inst|send_data_num[3]~19 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [4] & (!\data_rw_ctrl_inst|send_data_num[3]~19 & VCC)) +// \data_rw_ctrl_inst|send_data_num[4]~21 = CARRY((\data_rw_ctrl_inst|send_data_num [4] & !\data_rw_ctrl_inst|send_data_num[3]~19 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [4]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[3]~19 ), + .combout(\data_rw_ctrl_inst|send_data_num[4]~20_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[4]~21 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[4]~20 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N9 +dffeas \data_rw_ctrl_inst|send_data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[4]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[5]~22 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[5]~22_combout = (\data_rw_ctrl_inst|send_data_num [5] & (!\data_rw_ctrl_inst|send_data_num[4]~21 )) # (!\data_rw_ctrl_inst|send_data_num [5] & ((\data_rw_ctrl_inst|send_data_num[4]~21 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[5]~23 = CARRY((!\data_rw_ctrl_inst|send_data_num[4]~21 ) # (!\data_rw_ctrl_inst|send_data_num [5])) + + .dataa(\data_rw_ctrl_inst|send_data_num [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[4]~21 ), + .combout(\data_rw_ctrl_inst|send_data_num[5]~22_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[5]~23 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[5]~22 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|send_data_num[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N15 +dffeas \data_rw_ctrl_inst|send_data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[7]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N11 +dffeas \data_rw_ctrl_inst|send_data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[5]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~1 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~1_combout = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num [7] & (\data_rw_ctrl_inst|send_data_num [4] & \data_rw_ctrl_inst|send_data_num [5]))) + + .dataa(\data_rw_ctrl_inst|send_data_num [6]), + .datab(\data_rw_ctrl_inst|send_data_num [7]), + .datac(\data_rw_ctrl_inst|send_data_num [4]), + .datad(\data_rw_ctrl_inst|send_data_num [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~1 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|always3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~3 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~3_combout = (\data_rw_ctrl_inst|always3~2_combout & (\data_rw_ctrl_inst|always3~0_combout & (\data_rw_ctrl_inst|always3~1_combout & \data_rw_ctrl_inst|Equal2~4_combout ))) + + .dataa(\data_rw_ctrl_inst|always3~2_combout ), + .datab(\data_rw_ctrl_inst|always3~0_combout ), + .datac(\data_rw_ctrl_inst|always3~1_combout ), + .datad(\data_rw_ctrl_inst|Equal2~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~3 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|always3~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_en~0 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_en~0_combout = (!\data_rw_ctrl_inst|always3~3_combout & ((\data_rw_ctrl_inst|send_data_en~q ) # ((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q & \data_rw_ctrl_inst|rd_busy_dly~q )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .datab(\data_rw_ctrl_inst|rd_busy_dly~q ), + .datac(\data_rw_ctrl_inst|send_data_en~q ), + .datad(\data_rw_ctrl_inst|always3~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|send_data_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_en~0 .lut_mask = 16'h00F4; +defparam \data_rw_ctrl_inst|send_data_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N23 +dffeas \data_rw_ctrl_inst|send_data_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_en .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~1 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal3~1_combout = (\data_rw_ctrl_inst|cnt_wait [0]) # ((\data_rw_ctrl_inst|cnt_wait [3]) # ((\data_rw_ctrl_inst|cnt_wait [2]) # (\data_rw_ctrl_inst|cnt_wait [1]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [0]), + .datab(\data_rw_ctrl_inst|cnt_wait [3]), + .datac(\data_rw_ctrl_inst|cnt_wait [2]), + .datad(\data_rw_ctrl_inst|cnt_wait [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal3~1 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~26 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[13]~26_combout = ((\data_rw_ctrl_inst|Equal2~2_combout & (!\data_rw_ctrl_inst|Equal3~0_combout & !\data_rw_ctrl_inst|Equal3~1_combout ))) # (!\data_rw_ctrl_inst|send_data_en~q ) + + .dataa(\data_rw_ctrl_inst|Equal2~2_combout ), + .datab(\data_rw_ctrl_inst|Equal3~0_combout ), + .datac(\data_rw_ctrl_inst|send_data_en~q ), + .datad(\data_rw_ctrl_inst|Equal3~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .lut_mask = 16'h0F2F; +defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y27_N1 +dffeas \data_rw_ctrl_inst|cnt_wait[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[1]~18 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[1]~18_combout = (\data_rw_ctrl_inst|cnt_wait [1] & (!\data_rw_ctrl_inst|cnt_wait[0]~17 )) # (!\data_rw_ctrl_inst|cnt_wait [1] & ((\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[1]~19 = CARRY((!\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (!\data_rw_ctrl_inst|cnt_wait [1])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [1]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[0]~17 ), + .combout(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[1]~19 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N3 +dffeas \data_rw_ctrl_inst|cnt_wait[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[2]~20 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[2]~20_combout = (\data_rw_ctrl_inst|cnt_wait [2] & (\data_rw_ctrl_inst|cnt_wait[1]~19 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [2] & (!\data_rw_ctrl_inst|cnt_wait[1]~19 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[2]~21 = CARRY((\data_rw_ctrl_inst|cnt_wait [2] & !\data_rw_ctrl_inst|cnt_wait[1]~19 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [2]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[1]~19 ), + .combout(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[2]~21 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N5 +dffeas \data_rw_ctrl_inst|cnt_wait[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y27_N7 +dffeas \data_rw_ctrl_inst|cnt_wait[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~3 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~3_combout = (\data_rw_ctrl_inst|cnt_wait [0] & (\data_rw_ctrl_inst|cnt_wait [3] & (\data_rw_ctrl_inst|cnt_wait [2] & \data_rw_ctrl_inst|cnt_wait [1]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [0]), + .datab(\data_rw_ctrl_inst|cnt_wait [3]), + .datac(\data_rw_ctrl_inst|cnt_wait [2]), + .datad(\data_rw_ctrl_inst|cnt_wait [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~3 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[6]~29 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[6]~29_combout = (\data_rw_ctrl_inst|cnt_wait [6] & (\data_rw_ctrl_inst|cnt_wait[5]~28 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [6] & (!\data_rw_ctrl_inst|cnt_wait[5]~28 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[6]~30 = CARRY((\data_rw_ctrl_inst|cnt_wait [6] & !\data_rw_ctrl_inst|cnt_wait[5]~28 )) + + .dataa(\data_rw_ctrl_inst|cnt_wait [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[5]~28 ), + .combout(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[6]~30 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .lut_mask = 16'hA50A; +defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[7]~31 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[7]~31_combout = (\data_rw_ctrl_inst|cnt_wait [7] & (!\data_rw_ctrl_inst|cnt_wait[6]~30 )) # (!\data_rw_ctrl_inst|cnt_wait [7] & ((\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[7]~32 = CARRY((!\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (!\data_rw_ctrl_inst|cnt_wait [7])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [7]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[6]~30 ), + .combout(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[7]~32 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N15 +dffeas \data_rw_ctrl_inst|cnt_wait[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[8]~33 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[8]~33_combout = (\data_rw_ctrl_inst|cnt_wait [8] & (\data_rw_ctrl_inst|cnt_wait[7]~32 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [8] & (!\data_rw_ctrl_inst|cnt_wait[7]~32 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[8]~34 = CARRY((\data_rw_ctrl_inst|cnt_wait [8] & !\data_rw_ctrl_inst|cnt_wait[7]~32 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [8]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[7]~32 ), + .combout(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[8]~34 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N17 +dffeas \data_rw_ctrl_inst|cnt_wait[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[9]~35 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[9]~35_combout = (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait[8]~34 )) # (!\data_rw_ctrl_inst|cnt_wait [9] & ((\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[9]~36 = CARRY((!\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (!\data_rw_ctrl_inst|cnt_wait [9])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [9]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[8]~34 ), + .combout(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[9]~36 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N19 +dffeas \data_rw_ctrl_inst|cnt_wait[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[10]~37 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[10]~37_combout = (\data_rw_ctrl_inst|cnt_wait [10] & (\data_rw_ctrl_inst|cnt_wait[9]~36 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait[9]~36 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[10]~38 = CARRY((\data_rw_ctrl_inst|cnt_wait [10] & !\data_rw_ctrl_inst|cnt_wait[9]~36 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [10]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[9]~36 ), + .combout(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[10]~38 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N21 +dffeas \data_rw_ctrl_inst|cnt_wait[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[10] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[11]~39 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[11]~39_combout = (\data_rw_ctrl_inst|cnt_wait [11] & (!\data_rw_ctrl_inst|cnt_wait[10]~38 )) # (!\data_rw_ctrl_inst|cnt_wait [11] & ((\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[11]~40 = CARRY((!\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (!\data_rw_ctrl_inst|cnt_wait [11])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[10]~38 ), + .combout(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[11]~40 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[12]~41 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[12]~41_combout = (\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait[11]~40 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [12] & (!\data_rw_ctrl_inst|cnt_wait[11]~40 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[12]~42 = CARRY((\data_rw_ctrl_inst|cnt_wait [12] & !\data_rw_ctrl_inst|cnt_wait[11]~40 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [12]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[11]~40 ), + .combout(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[12]~42 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N25 +dffeas \data_rw_ctrl_inst|cnt_wait[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [12]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[12] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~43 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[13]~43_combout = (\data_rw_ctrl_inst|cnt_wait [13] & (!\data_rw_ctrl_inst|cnt_wait[12]~42 )) # (!\data_rw_ctrl_inst|cnt_wait [13] & ((\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[13]~44 = CARRY((!\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (!\data_rw_ctrl_inst|cnt_wait [13])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[12]~42 ), + .combout(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[13]~44 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[14]~45 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[14]~45_combout = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait[13]~44 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [14] & (!\data_rw_ctrl_inst|cnt_wait[13]~44 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[14]~46 = CARRY((\data_rw_ctrl_inst|cnt_wait [14] & !\data_rw_ctrl_inst|cnt_wait[13]~44 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [14]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[13]~44 ), + .combout(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[14]~46 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N29 +dffeas \data_rw_ctrl_inst|cnt_wait[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [14]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[14] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[15]~47 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[15]~47_combout = \data_rw_ctrl_inst|cnt_wait [15] $ (\data_rw_ctrl_inst|cnt_wait[14]~46 ) + + .dataa(\data_rw_ctrl_inst|cnt_wait [15]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|cnt_wait[14]~46 ), + .combout(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N31 +dffeas \data_rw_ctrl_inst|cnt_wait[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [15]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[15] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[15] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y27_N13 +dffeas \data_rw_ctrl_inst|cnt_wait[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~0 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~0_combout = (!\data_rw_ctrl_inst|cnt_wait [7] & (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait [8] & \data_rw_ctrl_inst|cnt_wait [6]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [7]), + .datab(\data_rw_ctrl_inst|cnt_wait [9]), + .datac(\data_rw_ctrl_inst|cnt_wait [8]), + .datad(\data_rw_ctrl_inst|cnt_wait [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~0 .lut_mask = 16'h0400; +defparam \data_rw_ctrl_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y27_N27 +dffeas \data_rw_ctrl_inst|cnt_wait[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [13]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[13] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y27_N23 +dffeas \data_rw_ctrl_inst|cnt_wait[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [11]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[11] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~1 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~1_combout = (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait [13] & \data_rw_ctrl_inst|cnt_wait [11]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [10]), + .datab(\data_rw_ctrl_inst|cnt_wait [12]), + .datac(\data_rw_ctrl_inst|cnt_wait [13]), + .datad(\data_rw_ctrl_inst|cnt_wait [11]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~1 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~2 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~2_combout = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait [15] & (\data_rw_ctrl_inst|Equal2~0_combout & \data_rw_ctrl_inst|Equal2~1_combout ))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [14]), + .datab(\data_rw_ctrl_inst|cnt_wait [15]), + .datac(\data_rw_ctrl_inst|Equal2~0_combout ), + .datad(\data_rw_ctrl_inst|Equal2~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~2 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~4 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~4_combout = (!\data_rw_ctrl_inst|cnt_wait [5] & (\data_rw_ctrl_inst|Equal2~3_combout & (\data_rw_ctrl_inst|cnt_wait [4] & \data_rw_ctrl_inst|Equal2~2_combout ))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [5]), + .datab(\data_rw_ctrl_inst|Equal2~3_combout ), + .datac(\data_rw_ctrl_inst|cnt_wait [4]), + .datad(\data_rw_ctrl_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~4 .lut_mask = 16'h4000; +defparam \data_rw_ctrl_inst|Equal2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N7 +dffeas \data_rw_ctrl_inst|rd_fifo_rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|Equal2~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|rd_fifo_rd_en .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|rd_fifo_rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0300; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]) # (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .lut_mask = 16'hFFFE; +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & ((\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|always3~0_combout )))) # (!\sd_ctrl_inst|sd_read_inst|always3~2_combout ) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .lut_mask = 16'hDF55; +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .lut_mask = 16'h0080; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N9 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y28_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9] + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .lut_mask = 16'hF0F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEBD7; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N15 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y28_N15 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y27_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hF0C0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hE1F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout & +// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0020; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .lut_mask = 16'h0100; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0300; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'hC3F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h3C3C; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h3CC3; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q +// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0A08; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h78F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout & +// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0020; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y27_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y28_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y28_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X30_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y28_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout & (\data_rw_ctrl_inst|rd_fifo_rd_en~q +// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'h8880; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0100; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9] $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .lut_mask = 16'hC3F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .lut_mask = 16'h55AA; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N15 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h3CC3; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'hF00F; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .lut_mask = 16'h78F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h3333; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout = (\data_rw_ctrl_inst|rd_fifo_rd_en~q & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hCCC0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout = (\sd_miso~input_o & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N7 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~13_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout = ((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) # (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .lut_mask = 16'h55D5; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N31 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N1 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N13 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N19 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N17 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N23 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N21 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N23 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N17 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~14_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N3 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h00FF; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .lut_mask = 16'h00FF; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~15_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [1] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N17 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~11_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N29 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~7_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N1 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~5_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N5 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~3_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N19 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~9_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N7 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~0_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N25 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N11 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~16_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N29 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~12_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N9 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~8_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N5 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~6_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N7 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N21 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~4_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N11 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~10_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N3 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N19 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [15]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N25 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N20 +cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( +// Equation(s): +// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [3] & (((\uart_tx_inst|bit_cnt [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])) # (!\uart_tx_inst|always0~0_combout ))) + + .dataa(\uart_tx_inst|always0~0_combout ), + .datab(\uart_tx_inst|bit_cnt [3]), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hCCC4; +defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N8 +cycloneive_lcell_comb \uart_tx_inst|tx~0 ( +// Equation(s): +// \uart_tx_inst|tx~0_combout = (\uart_tx_inst|bit_flag~q & (!\uart_tx_inst|Mux0~5_combout & ((!\uart_tx_inst|Mux0~0_combout )))) # (!\uart_tx_inst|bit_flag~q & (((\uart_tx_inst|tx~q )))) + + .dataa(\uart_tx_inst|Mux0~5_combout ), + .datab(\uart_tx_inst|bit_flag~q ), + .datac(\uart_tx_inst|tx~q ), + .datad(\uart_tx_inst|Mux0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~0 .lut_mask = 16'h3074; +defparam \uart_tx_inst|tx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N9 +dffeas \uart_tx_inst|tx ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|tx~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|tx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|tx .is_wysiwyg = "true"; +defparam \uart_tx_inst|tx .power_up = "low"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_0c_v_slow.sdo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_0c_v_slow.sdo new file mode 100644 index 0000000..273365b --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_0c_v_slow.sdo @@ -0,0 +1,19061 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "uart_sd") + (DATE "06/02/2023 04:03:14") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (3924:3924:3924) (3924:3924:3924)) + (PORT inclk[0] (2063:2063:2063) (2063:2063:2063)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (825:825:825)) + (PORT datab (786:786:786) (701:701:701)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (715:715:715)) + (PORT datab (1205:1205:1205) (1035:1035:1035)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (510:510:510)) + (PORT datab (318:318:318) (372:372:372)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1644:1644:1644)) + (PORT sclr (845:845:845) (900:900:900)) + (PORT ena (973:973:973) (947:947:947)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1644:1644:1644)) + (PORT sclr (845:845:845) (900:900:900)) + (PORT ena (973:973:973) (947:947:947)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (PORT sclr (1475:1475:1475) (1597:1597:1597)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (PORT sclr (2461:2461:2461) (2829:2829:2829)) + (PORT ena (1213:1213:1213) (1111:1111:1111)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (PORT sclr (2461:2461:2461) (2829:2829:2829)) + (PORT ena (1213:1213:1213) (1111:1111:1111)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (PORT sclr (2461:2461:2461) (2829:2829:2829)) + (PORT ena (1213:1213:1213) (1111:1111:1111)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1644:1644:1644)) + (PORT sclr (2620:2620:2620) (2938:2938:2938)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1685:1685:1685)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1650:1650:1650)) + (PORT sclr (2316:2316:2316) (2582:2582:2582)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1351:1351:1351) (1246:1246:1246)) + (PORT d[1] (1315:1315:1315) (1212:1212:1212)) + (PORT d[2] (1409:1409:1409) (1283:1283:1283)) + (PORT d[3] (1520:1520:1520) (1415:1415:1415)) + (PORT d[4] (1344:1344:1344) (1239:1239:1239)) + (PORT d[5] (1527:1527:1527) (1423:1423:1423)) + (PORT d[6] (1371:1371:1371) (1259:1259:1259)) + (PORT d[7] (1368:1368:1368) (1248:1248:1248)) + (PORT clk (2015:2015:2015) (2062:2062:2062)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (968:968:968) (912:912:912)) + (PORT d[1] (1018:1018:1018) (953:953:953)) + (PORT d[2] (1244:1244:1244) (1117:1117:1117)) + (PORT d[3] (1112:1112:1112) (982:982:982)) + (PORT d[4] (963:963:963) (912:912:912)) + (PORT d[5] (1701:1701:1701) (1533:1533:1533)) + (PORT d[6] (1351:1351:1351) (1225:1225:1225)) + (PORT d[7] (1689:1689:1689) (1491:1491:1491)) + (PORT d[8] (991:991:991) (934:934:934)) + (PORT d[9] (900:900:900) (797:797:797)) + (PORT clk (2012:2012:2012) (2058:2058:2058)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1186:1186:1186) (1045:1045:1045)) + (PORT clk (2012:2012:2012) (2058:2058:2058)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2015:2015:2015) (2062:2062:2062)) + (PORT d[0] (1808:1808:1808) (1677:1677:1677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2016:2016:2016) (2063:2063:2063)) + (IOPATH (posedge clk) pulse (0:0:0) (2490:2490:2490)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2016:2016:2016) (2063:2063:2063)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2016:2016:2016) (2063:2063:2063)) + (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2016:2016:2016) (2063:2063:2063)) + (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1305:1305:1305) (1132:1132:1132)) + (PORT d[1] (993:993:993) (932:932:932)) + (PORT d[2] (1709:1709:1709) (1550:1550:1550)) + (PORT d[3] (1702:1702:1702) (1564:1564:1564)) + (PORT d[4] (1550:1550:1550) (1467:1467:1467)) + (PORT d[5] (1790:1790:1790) (1643:1643:1643)) + (PORT d[6] (1307:1307:1307) (1204:1204:1204)) + (PORT d[7] (1388:1388:1388) (1291:1291:1291)) + (PORT d[8] (948:948:948) (832:832:832)) + (PORT clk (1968:1968:1968) (1970:1970:1970)) + (PORT stall (1428:1428:1428) (1622:1622:1622)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + (HOLD stall (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1968:1968:1968) (1970:1970:1970)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1969:1969:1969) (1971:1971:1971)) + (IOPATH (posedge clk) pulse (0:0:0) (2891:2891:2891)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1969:1969:1969) (1971:1971:1971)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1969:1969:1969) (1971:1971:1971)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1959:1959:1959) (1963:1963:1963)) + (PORT ena (1982:1982:1982) (1809:1809:1809)) + (IOPATH (posedge clk) q (353:353:353) (353:353:353)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (56:56:56)) + (SETUP ena (posedge clk) (56:56:56)) + (HOLD d (posedge clk) (190:190:190)) + (HOLD ena (posedge clk) (190:190:190)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1178:1178:1178) (1038:1038:1038)) + (PORT d[1] (1142:1142:1142) (1014:1014:1014)) + (PORT d[2] (1158:1158:1158) (1032:1032:1032)) + (PORT d[3] (1542:1542:1542) (1346:1346:1346)) + (PORT d[4] (1177:1177:1177) (1035:1035:1035)) + (PORT d[5] (1138:1138:1138) (1014:1014:1014)) + (PORT d[6] (1182:1182:1182) (1044:1044:1044)) + (PORT d[7] (1174:1174:1174) (1037:1037:1037)) + (PORT d[9] (1145:1145:1145) (1019:1019:1019)) + (PORT d[10] (1231:1231:1231) (1107:1107:1107)) + (PORT d[11] (1219:1219:1219) (1088:1088:1088)) + (PORT d[12] (1181:1181:1181) (1042:1042:1042)) + (PORT d[13] (1473:1473:1473) (1295:1295:1295)) + (PORT d[14] (1142:1142:1142) (1016:1016:1016)) + (PORT d[15] (1528:1528:1528) (1325:1325:1325)) + (PORT d[16] (1536:1536:1536) (1333:1333:1333)) + (PORT clk (2030:2030:2030) (2071:2071:2071)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1301:1301:1301) (1179:1179:1179)) + (PORT d[1] (1266:1266:1266) (1130:1130:1130)) + (PORT d[2] (1619:1619:1619) (1420:1420:1420)) + (PORT d[3] (1163:1163:1163) (1043:1043:1043)) + (PORT d[4] (971:971:971) (897:897:897)) + (PORT d[5] (1757:1757:1757) (1503:1503:1503)) + (PORT d[6] (1632:1632:1632) (1440:1440:1440)) + (PORT d[7] (919:919:919) (863:863:863)) + (PORT d[8] (1531:1531:1531) (1279:1279:1279)) + (PORT clk (2027:2027:2027) (2067:2067:2067)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1207:1207:1207) (1072:1072:1072)) + (PORT clk (2027:2027:2027) (2067:2067:2067)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2030:2030:2030) (2071:2071:2071)) + (PORT d[0] (1829:1829:1829) (1704:1704:1704)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2031:2031:2031) (2072:2072:2072)) + (IOPATH (posedge clk) pulse (0:0:0) (2490:2490:2490)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2031:2031:2031) (2072:2072:2072)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2031:2031:2031) (2072:2072:2072)) + (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2031:2031:2031) (2072:2072:2072)) + (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1276:1276:1276) (1087:1087:1087)) + (PORT d[1] (1734:1734:1734) (1574:1574:1574)) + (PORT d[2] (1396:1396:1396) (1305:1305:1305)) + (PORT d[3] (989:989:989) (923:923:923)) + (PORT d[4] (1025:1025:1025) (949:949:949)) + (PORT d[5] (1508:1508:1508) (1409:1409:1409)) + (PORT d[6] (973:973:973) (898:898:898)) + (PORT d[7] (1281:1281:1281) (1179:1179:1179)) + (PORT d[8] (1263:1263:1263) (1150:1150:1150)) + (PORT d[9] (1574:1574:1574) (1365:1365:1365)) + (PORT clk (1983:1983:1983) (1979:1979:1979)) + (PORT stall (1126:1126:1126) (1286:1286:1286)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + (HOLD stall (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1983:1983:1983) (1979:1979:1979)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1984:1984:1984) (1980:1980:1980)) + (IOPATH (posedge clk) pulse (0:0:0) (2891:2891:2891)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1984:1984:1984) (1980:1980:1980)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1984:1984:1984) (1980:1980:1980)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1974:1974:1974) (1972:1972:1972)) + (PORT ena (1647:1647:1647) (1507:1507:1507)) + (IOPATH (posedge clk) q (353:353:353) (353:353:353)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (56:56:56)) + (SETUP ena (posedge clk) (56:56:56)) + (HOLD d (posedge clk) (190:190:190)) + (HOLD ena (posedge clk) (190:190:190)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1465:1465:1465) (1586:1586:1586)) + (PORT ena (1210:1210:1210) (1105:1105:1105)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1465:1465:1465) (1586:1586:1586)) + (PORT ena (1210:1210:1210) (1105:1105:1105)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1465:1465:1465) (1586:1586:1586)) + (PORT ena (1210:1210:1210) (1105:1105:1105)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1465:1465:1465) (1586:1586:1586)) + (PORT ena (1210:1210:1210) (1105:1105:1105)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (PORT sload (985:985:985) (1051:1051:1051)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (545:545:545)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (435:435:435)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1685:1685:1685)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1650:1650:1650)) + (PORT sclr (2316:2316:2316) (2582:2582:2582)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1685:1685:1685)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1650:1650:1650)) + (PORT sclr (2316:2316:2316) (2582:2582:2582)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT sclr (959:959:959) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT sclr (959:959:959) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (392:392:392)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (389:389:389)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (420:420:420)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (414:414:414)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1426:1426:1426) (1369:1369:1369)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1426:1426:1426) (1369:1369:1369)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1426:1426:1426) (1369:1369:1369)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (393:393:393)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (404:404:404)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (393:393:393)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (390:390:390)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (418:418:418)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (393:393:393)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (404:404:404)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (393:393:393)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (388:388:388)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0) + (DELAY + (ABSOLUTE + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (392:392:392)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1652:1652:1652)) + (PORT sclr (1077:1077:1077) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1652:1652:1652)) + (PORT sclr (1077:1077:1077) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1443:1443:1443) (1567:1567:1567)) + (PORT ena (1557:1557:1557) (1415:1415:1415)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1443:1443:1443) (1567:1567:1567)) + (PORT ena (1557:1557:1557) (1415:1415:1415)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1443:1443:1443) (1567:1567:1567)) + (PORT ena (1557:1557:1557) (1415:1415:1415)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1443:1443:1443) (1567:1567:1567)) + (PORT ena (1557:1557:1557) (1415:1415:1415)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1443:1443:1443) (1567:1567:1567)) + (PORT ena (1557:1557:1557) (1415:1415:1415)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1443:1443:1443) (1567:1567:1567)) + (PORT ena (1557:1557:1557) (1415:1415:1415)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (407:407:407)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (391:391:391)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (393:393:393)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (385:385:385)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (393:393:393)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT datac (782:782:782) (713:713:713)) + (PORT datad (293:293:293) (356:356:356)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD55) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT datab (611:611:611) (566:566:566)) + (PORT datac (561:561:561) (533:533:533)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (390:390:390)) + (PORT datab (546:546:546) (532:532:532)) + (PORT datac (282:282:282) (348:348:348)) + (PORT datad (285:285:285) (344:344:344)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (552:552:552) (542:542:542)) + (PORT datab (326:326:326) (384:384:384)) + (PORT datac (283:283:283) (349:349:349)) + (PORT datad (225:225:225) (232:232:232)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~0) + (DELAY + (ABSOLUTE + (PORT datac (508:508:508) (498:498:498)) + (PORT datad (472:472:472) (393:393:393)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~1) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (295:295:295)) + (PORT datab (624:624:624) (581:581:581)) + (PORT datac (1899:1899:1899) (1688:1688:1688)) + (PORT datad (1100:1100:1100) (900:900:900)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (419:419:419)) + (PORT datab (344:344:344) (407:407:407)) + (PORT datac (300:300:300) (371:371:371)) + (PORT datad (300:300:300) (365:365:365)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (561:561:561)) + (PORT datab (377:377:377) (452:452:452)) + (PORT datac (893:893:893) (774:774:774)) + (PORT datad (487:487:487) (427:427:427)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (920:920:920) (813:813:813)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (488:488:488) (436:436:436)) + (PORT datad (339:339:339) (417:417:417)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (513:513:513)) + (PORT datab (365:365:365) (428:428:428)) + (PORT datac (545:545:545) (478:478:478)) + (PORT datad (340:340:340) (418:418:418)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (273:273:273) (285:285:285)) + (PORT datab (366:366:366) (430:430:430)) + (PORT datac (1608:1608:1608) (1382:1382:1382)) + (PORT datad (897:897:897) (786:786:786)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (561:561:561)) + (PORT datab (371:371:371) (447:447:447)) + (PORT datac (878:878:878) (758:758:758)) + (PORT datad (492:492:492) (434:434:434)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (821:821:821)) + (PORT datab (366:366:366) (429:429:429)) + (PORT datac (441:441:441) (378:378:378)) + (PORT datad (909:909:909) (787:787:787)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (282:282:282)) + (PORT datab (347:347:347) (412:412:412)) + (PORT datac (322:322:322) (395:395:395)) + (PORT datad (228:228:228) (236:236:236)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (821:821:821)) + (PORT datab (365:365:365) (429:429:429)) + (PORT datac (538:538:538) (469:469:469)) + (PORT datad (337:337:337) (415:415:415)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (804:804:804)) + (PORT datab (380:380:380) (456:456:456)) + (PORT datac (536:536:536) (468:468:468)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (350:350:350) (417:417:417)) + (PORT datac (227:227:227) (242:242:242)) + (PORT datad (229:229:229) (236:236:236)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (296:296:296)) + (PORT datab (624:624:624) (581:581:581)) + (PORT datac (555:555:555) (526:526:526)) + (PORT datad (847:847:847) (734:734:734)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (921:921:921)) + (PORT datab (1067:1067:1067) (988:988:988)) + (PORT datac (945:945:945) (896:896:896)) + (PORT datad (975:975:975) (912:912:912)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~2) + (DELAY + (ABSOLUTE + (PORT dataa (968:968:968) (905:905:905)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (944:944:944) (895:895:895)) + (PORT datad (946:946:946) (869:869:869)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (921:921:921)) + (PORT datab (989:989:989) (928:928:928)) + (PORT datac (1008:1008:1008) (949:949:949)) + (PORT datad (973:973:973) (909:909:909)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~3) + (DELAY + (ABSOLUTE + (PORT datab (268:268:268) (274:274:274)) + (PORT datac (926:926:926) (867:867:867)) + (PORT datad (870:870:870) (810:810:810)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~4) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (921:921:921)) + (PORT datab (1063:1063:1063) (983:983:983)) + (PORT datac (928:928:928) (879:879:879)) + (PORT datad (973:973:973) (910:910:910)) + (IOPATH dataa combout (420:420:420) (377:377:377)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~5) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (921:921:921)) + (PORT datab (988:988:988) (927:927:927)) + (PORT datac (924:924:924) (866:866:866)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~6) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (921:921:921)) + (PORT datab (990:990:990) (930:930:930)) + (PORT datac (926:926:926) (877:877:877)) + (PORT datad (974:974:974) (911:911:911)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~7) + (DELAY + (ABSOLUTE + (PORT dataa (967:967:967) (904:904:904)) + (PORT datab (1066:1066:1066) (987:987:987)) + (PORT datac (945:945:945) (895:895:895)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (351:351:351) (377:377:377)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (921:921:921)) + (PORT datab (1069:1069:1069) (991:991:991)) + (PORT datac (946:946:946) (897:897:897)) + (PORT datad (976:976:976) (913:913:913)) + (IOPATH dataa combout (420:420:420) (444:444:444)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~8) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (903:903:903)) + (PORT datab (267:267:267) (274:274:274)) + (PORT datac (924:924:924) (875:875:875)) + (PORT datad (870:870:870) (805:805:805)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~9) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (225:225:225) (240:240:240)) + (PORT datad (876:876:876) (811:811:811)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1024:1024:1024) (928:928:928)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (226:226:226) (241:241:241)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1666:1666:1666) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1698:1698:1698) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT datac (313:313:313) (382:382:382)) + (PORT datad (320:320:320) (396:396:396)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (777:777:777)) + (PORT datab (371:371:371) (443:443:443)) + (PORT datac (338:338:338) (424:424:424)) + (PORT datad (844:844:844) (708:708:708)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (281:281:281)) + (PORT datab (368:368:368) (441:441:441)) + (PORT datac (832:832:832) (701:701:701)) + (PORT datad (853:853:853) (720:720:720)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (719:719:719)) + (PORT datab (383:383:383) (458:458:458)) + (PORT datac (786:786:786) (667:667:667)) + (PORT datad (328:328:328) (404:404:404)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~4) + (DELAY + (ABSOLUTE + (PORT datab (384:384:384) (459:459:459)) + (PORT datac (788:788:788) (669:669:669)) + (PORT datad (328:328:328) (405:405:405)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (281:281:281)) + (PORT datab (268:268:268) (274:274:274)) + (PORT datac (314:314:314) (384:384:384)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~0) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (390:390:390)) + (PORT datab (336:336:336) (396:396:396)) + (PORT datad (513:513:513) (499:499:499)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (562:562:562)) + (PORT datab (342:342:342) (404:404:404)) + (PORT datac (300:300:300) (372:372:372)) + (PORT datad (248:248:248) (255:255:255)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~2) + (DELAY + (ABSOLUTE + (PORT datab (599:599:599) (549:549:549)) + (PORT datac (548:548:548) (515:515:515)) + (PORT datad (502:502:502) (482:482:482)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1674:1674:1674)) + (PORT asdata (1620:1620:1620) (1493:1493:1493)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (803:803:803)) + (PORT datab (1189:1189:1189) (1061:1061:1061)) + (PORT datac (318:318:318) (388:388:388)) + (PORT datad (243:243:243) (258:258:258)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (396:396:396)) + (PORT datac (330:330:330) (397:397:397)) + (PORT datad (257:257:257) (269:269:269)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT datab (576:576:576) (562:562:562)) + (PORT datad (243:243:243) (258:258:258)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT datab (864:864:864) (756:756:756)) + (PORT datac (781:781:781) (705:705:705)) + (PORT datad (749:749:749) (622:622:622)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT datac (781:781:781) (705:705:705)) + (PORT datad (749:749:749) (622:622:622)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datac (1236:1236:1236) (1101:1101:1101)) + (PORT datad (1166:1166:1166) (1029:1029:1029)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (395:395:395)) + (PORT datac (293:293:293) (363:363:363)) + (PORT datad (300:300:300) (365:365:365)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (426:426:426)) + (PORT datab (337:337:337) (398:398:398)) + (PORT datac (314:314:314) (384:384:384)) + (PORT datad (294:294:294) (356:356:356)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (401:401:401)) + (PORT datab (286:286:286) (299:299:299)) + (PORT datac (826:826:826) (743:743:743)) + (PORT datad (243:243:243) (257:257:257)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (821:821:821)) + (PORT datab (580:580:580) (502:502:502)) + (PORT datac (1072:1072:1072) (898:898:898)) + (PORT datad (315:315:315) (378:378:378)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (PORT datab (326:326:326) (383:383:383)) + (PORT datad (281:281:281) (339:339:339)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT datab (955:955:955) (812:812:812)) + (PORT datac (765:765:765) (639:639:639)) + (PORT datad (320:320:320) (385:385:385)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (403:403:403)) + (PORT datab (286:286:286) (299:299:299)) + (PORT datac (826:826:826) (743:743:743)) + (PORT datad (242:242:242) (257:257:257)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (978:978:978)) + (PORT datab (346:346:346) (408:408:408)) + (PORT datac (302:302:302) (374:374:374)) + (PORT datad (472:472:472) (419:419:419)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (270:270:270) (276:276:276)) + (PORT datac (489:489:489) (416:416:416)) + (PORT datad (811:811:811) (671:671:671)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (437:437:437)) + (PORT datab (277:277:277) (286:286:286)) + (PORT datac (481:481:481) (425:425:425)) + (PORT datad (939:939:939) (859:859:859)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (389:389:389)) + (PORT datab (323:323:323) (379:379:379)) + (PORT datad (298:298:298) (354:354:354)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (416:416:416)) + (PORT datab (326:326:326) (384:384:384)) + (PORT datac (285:285:285) (352:352:352)) + (PORT datad (302:302:302) (367:367:367)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (419:419:419)) + (PORT datab (267:267:267) (273:273:273)) + (PORT datad (236:236:236) (248:248:248)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.CMD24_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1669:1669:1669)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datab (507:507:507) (444:444:444)) + (PORT datac (471:471:471) (413:413:413)) + (PORT datad (307:307:307) (366:366:366)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (540:540:540)) + (PORT datab (379:379:379) (455:455:455)) + (PORT datad (309:309:309) (378:378:378)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (1271:1271:1271) (1205:1205:1205)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (829:829:829)) + (PORT datab (847:847:847) (774:774:774)) + (PORT datad (873:873:873) (797:797:797)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (701:701:701) (762:762:762)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (836:836:836)) + (PORT datab (922:922:922) (835:835:835)) + (PORT datad (276:276:276) (330:330:330)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (701:701:701) (762:762:762)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (850:850:850)) + (PORT datab (865:865:865) (786:786:786)) + (PORT datad (853:853:853) (782:782:782)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (917:917:917) (899:899:899)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (980:980:980)) + (PORT datab (877:877:877) (797:797:797)) + (PORT datad (278:278:278) (333:333:333)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (418:418:418)) + (PORT datab (269:269:269) (275:275:275)) + (PORT datac (225:225:225) (240:240:240)) + (PORT datad (476:476:476) (401:401:401)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (834:834:834)) + (PORT datab (1298:1298:1298) (1148:1148:1148)) + (PORT datad (293:293:293) (355:355:355)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1561:1561:1561) (1345:1345:1345)) + (PORT datab (890:890:890) (808:808:808)) + (PORT datad (531:531:531) (515:515:515)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1621:1621:1621) (1512:1512:1512)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1513:1513:1513) (1328:1328:1328)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[9\]) + (DELAY + (ABSOLUTE + (PORT datad (300:300:300) (356:356:356)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1621:1621:1621) (1512:1512:1512)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1621:1621:1621) (1512:1512:1512)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT asdata (710:710:710) (774:774:774)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1621:1621:1621) (1512:1512:1512)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1621:1621:1621) (1512:1512:1512)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1621:1621:1621) (1512:1512:1512)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1621:1621:1621) (1512:1512:1512)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT asdata (713:713:713) (778:778:778)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1621:1621:1621) (1512:1512:1512)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1682:1682:1682)) + (PORT asdata (1268:1268:1268) (1171:1171:1171)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (806:806:806)) + (PORT datab (602:602:602) (564:564:564)) + (PORT datad (277:277:277) (332:332:332)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1694:1694:1694)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1275:1275:1275) (1180:1180:1180)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1672:1672:1672) (1693:1693:1693)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1672:1672:1672) (1693:1693:1693)) + (PORT asdata (702:702:702) (763:763:763)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (555:555:555)) + (PORT datab (802:802:802) (730:730:730)) + (PORT datad (276:276:276) (331:331:331)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT datab (377:377:377) (451:451:451)) + (PORT datac (314:314:314) (383:383:383)) + (PORT datad (319:319:319) (395:395:395)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (283:283:283)) + (PORT datab (285:285:285) (298:298:298)) + (PORT datad (276:276:276) (297:297:297)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (842:842:842)) + (PORT datab (325:325:325) (381:381:381)) + (PORT datac (287:287:287) (354:354:354)) + (PORT datad (284:284:284) (344:344:344)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1331:1331:1331) (1219:1219:1219)) + (PORT datad (272:272:272) (290:290:290)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT asdata (701:701:701) (762:762:762)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datab (506:506:506) (444:444:444)) + (PORT datac (472:472:472) (413:413:413)) + (PORT datad (307:307:307) (366:366:366)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1954:1954:1954) (1640:1640:1640)) + (PORT datac (308:308:308) (375:375:375)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (1648:1648:1648) (1549:1549:1549)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (1726:1726:1726) (1621:1621:1621)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (731:731:731) (796:796:796)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT asdata (712:712:712) (776:776:776)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1627:1627:1627) (1478:1478:1478)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1627:1627:1627) (1478:1478:1478)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1627:1627:1627) (1478:1478:1478)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1627:1627:1627) (1478:1478:1478)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (PORT ena (1034:1034:1034) (1005:1005:1005)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT asdata (712:712:712) (777:777:777)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1627:1627:1627) (1478:1478:1478)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1627:1627:1627) (1478:1478:1478)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1627:1627:1627) (1478:1478:1478)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|tx_flag) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (383:383:383)) + (PORT datad (1104:1104:1104) (901:901:901)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1694:1694:1694)) + (PORT asdata (709:709:709) (774:774:774)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1694:1694:1694)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1672:1672:1672) (1693:1693:1693)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1672:1672:1672) (1693:1693:1693)) + (PORT asdata (703:703:703) (764:764:764)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1286:1286:1286) (1095:1095:1095)) + (PORT datab (953:953:953) (837:837:837)) + (PORT datac (339:339:339) (408:408:408)) + (PORT datad (264:264:264) (278:278:278)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1688:1688:1688) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1688:1688:1688) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1688:1688:1688) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~4) + (DELAY + (ABSOLUTE + (PORT datab (405:405:405) (481:481:481)) + (PORT datac (285:285:285) (351:351:351)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~5) + (DELAY + (ABSOLUTE + (PORT datab (404:404:404) (481:481:481)) + (PORT datac (288:288:288) (355:355:355)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~6) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (849:849:849)) + (PORT datac (359:359:359) (446:446:446)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~7) + (DELAY + (ABSOLUTE + (PORT dataa (3765:3765:3765) (3815:3815:3815)) + (PORT datad (879:879:879) (812:812:812)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT asdata (726:726:726) (788:788:788)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3339:3339:3339) (3439:3439:3439)) + (PORT datab (337:337:337) (397:397:397)) + (PORT datac (561:561:561) (533:533:533)) + (PORT datad (889:889:889) (823:823:823)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (424:424:424)) + (PORT datab (338:338:338) (398:398:398)) + (PORT datac (517:517:517) (501:501:501)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (432:432:432)) + (PORT datab (292:292:292) (306:306:306)) + (PORT datac (316:316:316) (387:387:387)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg3) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT asdata (2039:2039:2039) (1871:1871:1871)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT asdata (971:971:971) (978:978:978)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1672:1672:1672) (1693:1693:1693)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1632:1632:1632) (1472:1472:1472)) + (PORT datab (1270:1270:1270) (1090:1090:1090)) + (PORT datac (290:290:290) (359:359:359)) + (PORT datad (1169:1169:1169) (1007:1007:1007)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1617:1617:1617) (1456:1456:1456)) + (PORT datab (1266:1266:1266) (1085:1085:1085)) + (PORT datac (284:284:284) (351:351:351)) + (PORT datad (1175:1175:1175) (1013:1013:1013)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1341:1341:1341) (1233:1233:1233)) + (PORT datab (871:871:871) (768:768:768)) + (PORT datac (1097:1097:1097) (949:949:949)) + (PORT datad (284:284:284) (343:343:343)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1243:1243:1243) (1063:1063:1063)) + (PORT datab (1266:1266:1266) (1085:1085:1085)) + (PORT datac (1566:1566:1566) (1407:1407:1407)) + (PORT datad (288:288:288) (347:347:347)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~2) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (421:421:421)) + (PORT datab (353:353:353) (419:419:419)) + (PORT datac (293:293:293) (362:362:362)) + (PORT datad (291:291:291) (352:352:352)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1332:1332:1332) (1220:1220:1220)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (572:572:572)) + (PORT datab (828:828:828) (757:757:757)) + (PORT datac (516:516:516) (501:501:501)) + (PORT datad (509:509:509) (492:492:492)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a2) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1514:1514:1514) (1346:1346:1346)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (535:535:535)) + (PORT datab (326:326:326) (383:383:383)) + (PORT datac (284:284:284) (351:351:351)) + (PORT datad (284:284:284) (343:343:343)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (405:405:405)) + (PORT datab (334:334:334) (394:394:394)) + (PORT datac (293:293:293) (362:362:362)) + (PORT datad (292:292:292) (354:354:354)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT datab (344:344:344) (400:400:400)) + (PORT datad (302:302:302) (358:358:358)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|start_nedge) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (395:395:395)) + (PORT datac (1609:1609:1609) (1442:1442:1442)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (288:288:288) (355:355:355)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (284:284:284) (351:351:351)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg1\~0) + (DELAY + (ABSOLUTE + (PORT datad (3250:3250:3250) (3300:3300:3300)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (325:325:325) (391:391:391)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rx\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (778:778:778) (803:803:803)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (530:530:530) (517:517:517)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (934:934:934) (865:865:865)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1197:1197:1197) (1078:1078:1078)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (360:360:360)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (517:517:517) (507:507:507)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1434:1434:1434) (1189:1189:1189)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|tx_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (300:300:300) (356:356:356)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (359:359:359)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (872:872:872) (799:799:799)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (332:332:332)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (279:279:279) (334:334:334)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (286:286:286) (345:345:345)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (283:283:283) (341:341:341)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (286:286:286) (344:344:344)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (285:285:285) (343:343:343)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (284:284:284) (342:342:342)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (286:286:286) (345:345:345)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (879:879:879) (812:812:812)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (877:877:877) (810:810:810)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (285:285:285) (343:343:343)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (285:285:285) (343:343:343)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (856:856:856) (784:784:784)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (279:279:279) (334:334:334)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (792:792:792) (695:695:695)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (277:277:277) (331:331:331)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sd_clk\~output) + (DELAY + (ABSOLUTE + (PORT i (1459:1459:1459) (1377:1377:1377)) + (IOPATH i o (2882:2882:2882) (2802:2802:2802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sd_cs_n\~output) + (DELAY + (ABSOLUTE + (PORT i (1830:1830:1830) (1575:1575:1575)) + (IOPATH i o (2882:2882:2882) (2802:2802:2802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sd_mosi\~output) + (DELAY + (ABSOLUTE + (PORT i (1773:1773:1773) (1522:1522:1522)) + (IOPATH i o (2882:2882:2882) (2802:2802:2802)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tx\~output) + (DELAY + (ABSOLUTE + (PORT i (2595:2595:2595) (2962:2962:2962)) + (IOPATH i o (2961:2961:2961) (3013:3013:3013)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (788:788:788) (813:813:813)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2044:2044:2044) (2012:2012:2012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (354:354:354) (414:414:414)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (3317:3317:3317) (3784:3784:3784)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4032:4032:4032) (3954:3954:3954)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2706:2706:2706) (3154:3154:3154)) + (PORT datab (3372:3372:3372) (3373:3373:3373)) + (PORT datad (278:278:278) (333:333:333)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2513:2513:2513) (2225:2225:2225)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (332:332:332) (392:392:392)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sd_miso\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|miso_dly) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT asdata (4129:4129:4129) (4194:4194:4194)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3765:3765:3765) (3815:3815:3815)) + (PORT datab (328:328:328) (386:386:386)) + (PORT datad (512:512:512) (496:496:496)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1635:1635:1635)) + (PORT sclr (1119:1119:1119) (1185:1185:1185)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (569:569:569)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (823:823:823) (727:727:727)) + (PORT datad (530:530:530) (512:512:512)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1635:1635:1635)) + (PORT sclr (1119:1119:1119) (1185:1185:1185)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (538:538:538)) + (PORT datab (866:866:866) (764:764:764)) + (PORT datac (821:821:821) (725:725:725)) + (PORT datad (529:529:529) (512:512:512)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~2) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (466:466:466)) + (PORT datab (483:483:483) (424:424:424)) + (PORT datad (243:243:243) (258:258:258)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1635:1635:1635)) + (PORT sclr (1119:1119:1119) (1185:1185:1185)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1635:1635:1635)) + (PORT sclr (1119:1119:1119) (1185:1185:1185)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1635:1635:1635)) + (PORT sclr (1119:1119:1119) (1185:1185:1185)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1635:1635:1635)) + (PORT sclr (1119:1119:1119) (1185:1185:1185)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1635:1635:1635)) + (PORT sclr (1119:1119:1119) (1185:1185:1185)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (392:392:392)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1635:1635:1635)) + (PORT sclr (1119:1119:1119) (1185:1185:1185)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (539:539:539)) + (PORT datab (327:327:327) (384:384:384)) + (PORT datac (286:286:286) (353:353:353)) + (PORT datad (286:286:286) (344:344:344)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (556:556:556)) + (PORT datac (500:500:500) (424:424:424)) + (PORT datad (298:298:298) (353:353:353)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT asdata (1592:1592:1592) (1474:1474:1474)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1566:1566:1566) (1407:1407:1407)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT asdata (710:710:710) (775:775:775)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1566:1566:1566) (1407:1407:1407)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (286:286:286) (344:344:344)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1566:1566:1566) (1407:1407:1407)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT asdata (934:934:934) (925:925:925)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1566:1566:1566) (1407:1407:1407)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (277:277:277) (332:332:332)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1566:1566:1566) (1407:1407:1407)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT asdata (723:723:723) (785:785:785)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1566:1566:1566) (1407:1407:1407)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (286:286:286) (344:344:344)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1566:1566:1566) (1407:1407:1407)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT asdata (710:710:710) (775:775:775)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1566:1566:1566) (1407:1407:1407)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (389:389:389)) + (PORT datab (325:325:325) (381:381:381)) + (PORT datad (507:507:507) (492:492:492)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (682:682:682)) + (PORT datac (439:439:439) (373:373:373)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (331:331:331) (391:391:391)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (332:332:332) (392:392:392)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (414:414:414)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (364:364:364) (427:427:427)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT sclr (960:960:960) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (432:432:432)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT sclr (960:960:960) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3409:3409:3409) (3573:3573:3573)) + (PORT datab (916:916:916) (847:847:847)) + (PORT datac (326:326:326) (399:399:399)) + (PORT datad (325:325:325) (393:393:393)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (460:460:460)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datad (236:236:236) (247:247:247)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT sclr (960:960:960) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (329:329:329) (389:389:389)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT sclr (960:960:960) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT sclr (960:960:960) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT sclr (960:960:960) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (281:281:281)) + (PORT datac (292:292:292) (361:361:361)) + (PORT datad (305:305:305) (375:375:375)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datab (275:275:275) (285:285:285)) + (PORT datac (326:326:326) (399:399:399)) + (PORT datad (325:325:325) (393:393:393)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (417:417:417)) + (PORT datab (325:325:325) (382:382:382)) + (PORT datac (323:323:323) (396:396:396)) + (PORT datad (323:323:323) (390:390:390)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (426:426:426)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (420:420:420)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT sclr (960:960:960) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT sclr (960:960:960) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (315:315:315) (385:385:385)) + (PORT datad (318:318:318) (384:384:384)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT asdata (1192:1192:1192) (1121:1121:1121)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT asdata (703:703:703) (765:765:765)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (281:281:281) (337:337:337)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT asdata (700:700:700) (761:761:761)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT asdata (702:702:702) (763:763:763)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT asdata (702:702:702) (763:763:763)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT asdata (700:700:700) (761:761:761)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (287:287:287) (345:345:345)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (287:287:287) (346:346:346)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT asdata (934:934:934) (930:930:930)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (280:280:280) (335:335:335)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (279:279:279) (334:334:334)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1671:1671:1671)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1636:1636:1636)) + (PORT ena (1852:1852:1852) (1626:1626:1626)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (865:865:865) (795:795:795)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT asdata (701:701:701) (763:763:763)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (279:279:279) (334:334:334)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (332:332:332)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT asdata (703:703:703) (764:764:764)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT asdata (701:701:701) (762:762:762)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (334:334:334)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (279:279:279) (334:334:334)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (280:280:280) (336:336:336)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (277:277:277) (332:332:332)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[27\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT asdata (703:703:703) (764:764:764)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[28\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT asdata (704:704:704) (765:765:765)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[29\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT asdata (701:701:701) (762:762:762)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (280:280:280) (335:335:335)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (277:277:277) (331:331:331)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1691:1691:1691) (1644:1644:1644)) + (PORT ena (1515:1515:1515) (1335:1335:1335)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[32\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT asdata (1188:1188:1188) (1101:1101:1101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT ena (1269:1269:1269) (1167:1167:1167)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (363:363:363)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT ena (1269:1269:1269) (1167:1167:1167)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (495:495:495) (478:478:478)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT ena (1269:1269:1269) (1167:1167:1167)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[35\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT asdata (928:928:928) (911:911:911)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT ena (1269:1269:1269) (1167:1167:1167)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (525:525:525)) + (PORT datad (494:494:494) (477:477:477)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[36\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT asdata (916:916:916) (897:897:897)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT ena (1269:1269:1269) (1167:1167:1167)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (286:286:286) (346:346:346)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT ena (1269:1269:1269) (1167:1167:1167)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (283:283:283) (341:341:341)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT ena (1269:1269:1269) (1167:1167:1167)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT asdata (711:711:711) (776:776:776)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (PORT ena (1269:1269:1269) (1167:1167:1167)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (389:389:389)) + (PORT datab (327:327:327) (384:384:384)) + (PORT datad (284:284:284) (343:343:343)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT datab (286:286:286) (299:299:299)) + (PORT datad (243:243:243) (257:257:257)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (281:281:281)) + (PORT datab (869:869:869) (708:708:708)) + (PORT datac (304:304:304) (378:378:378)) + (PORT datad (471:471:471) (418:418:418)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD0) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (389:389:389)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (PORT sload (985:985:985) (1051:1051:1051)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (PORT sload (985:985:985) (1051:1051:1051)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (391:391:391)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (PORT sload (985:985:985) (1051:1051:1051)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (403:403:403)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (PORT sload (985:985:985) (1051:1051:1051)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (PORT sload (985:985:985) (1051:1051:1051)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (536:536:536)) + (PORT datab (326:326:326) (383:383:383)) + (PORT datac (283:283:283) (350:350:350)) + (PORT datad (284:284:284) (343:343:343)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (275:275:275) (285:285:285)) + (PORT datac (295:295:295) (366:366:366)) + (PORT datad (236:236:236) (247:247:247)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (PORT sload (985:985:985) (1051:1051:1051)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (PORT sload (985:985:985) (1051:1051:1051)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (PORT sload (985:985:985) (1051:1051:1051)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (391:391:391)) + (PORT datab (326:326:326) (384:384:384)) + (PORT datac (283:283:283) (349:349:349)) + (PORT datad (285:285:285) (344:344:344)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE\~0) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (408:408:408)) + (PORT datab (277:277:277) (287:287:287)) + (PORT datad (237:237:237) (248:248:248)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END\~0) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (696:696:696)) + (PORT datad (779:779:779) (624:624:624)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr18) + (DELAY + (ABSOLUTE + (PORT datab (520:520:520) (464:464:464)) + (PORT datac (289:289:289) (357:357:357)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1644:1644:1644)) + (PORT sclr (845:845:845) (900:900:900)) + (PORT ena (973:973:973) (947:947:947)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (406:406:406)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1644:1644:1644)) + (PORT sclr (845:845:845) (900:900:900)) + (PORT ena (973:973:973) (947:947:947)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (385:385:385)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1644:1644:1644)) + (PORT sclr (845:845:845) (900:900:900)) + (PORT ena (973:973:973) (947:947:947)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (393:393:393)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1644:1644:1644)) + (PORT sclr (845:845:845) (900:900:900)) + (PORT ena (973:973:973) (947:947:947)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (543:543:543)) + (PORT datab (326:326:326) (383:383:383)) + (PORT datac (284:284:284) (350:350:350)) + (PORT datad (307:307:307) (366:366:366)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (934:934:934) (844:844:844)) + (PORT datac (837:837:837) (729:729:729)) + (PORT datad (269:269:269) (284:284:284)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1644:1644:1644)) + (PORT sclr (845:845:845) (900:900:900)) + (PORT ena (973:973:973) (947:947:947)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1644:1644:1644)) + (PORT sclr (845:845:845) (900:900:900)) + (PORT ena (973:973:973) (947:947:947)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (921:921:921)) + (PORT datab (1068:1068:1068) (990:990:990)) + (PORT datac (946:946:946) (897:897:897)) + (PORT datad (975:975:975) (913:913:913)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~2) + (DELAY + (ABSOLUTE + (PORT datac (830:830:830) (722:722:722)) + (PORT datad (263:263:263) (277:277:277)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (775:775:775) (648:648:648)) + (PORT datab (358:358:358) (418:418:418)) + (PORT datad (518:518:518) (462:462:462)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD0_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1163:1163:1163) (979:979:979)) + (PORT datab (344:344:344) (407:407:407)) + (PORT datac (305:305:305) (379:379:379)) + (PORT datad (469:469:469) (416:416:416)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (777:777:777) (649:649:649)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datad (519:519:519) (464:464:464)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD8) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (778:778:778) (651:651:651)) + (PORT datab (351:351:351) (410:410:410)) + (PORT datad (520:520:520) (465:465:465)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD8_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (427:427:427)) + (PORT datab (584:584:584) (507:507:507)) + (PORT datad (812:812:812) (671:671:671)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD55_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (416:416:416)) + (PORT datab (580:580:580) (503:503:503)) + (PORT datad (806:806:806) (665:665:665)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.ACMD41_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (416:416:416)) + (PORT datab (343:343:343) (406:406:406)) + (PORT datac (299:299:299) (371:371:371)) + (PORT datad (300:300:300) (355:355:355)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datab (959:959:959) (817:817:817)) + (PORT datac (770:770:770) (645:645:645)) + (PORT datad (308:308:308) (368:368:368)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (512:512:512) (460:460:460)) + (PORT datab (267:267:267) (274:274:274)) + (PORT datac (301:301:301) (373:373:373)) + (PORT datad (810:810:810) (669:669:669)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_ACMD41) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (424:424:424)) + (PORT datab (350:350:350) (409:409:409)) + (PORT datac (513:513:513) (513:513:513)) + (PORT datad (315:315:315) (378:378:378)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~1) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (766:766:766)) + (PORT datab (308:308:308) (321:321:321)) + (PORT datac (512:512:512) (441:441:441)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (398:398:398)) + (PORT datab (520:520:520) (464:464:464)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|init_end) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (401:401:401)) + (PORT datac (781:781:781) (713:713:713)) + (PORT datad (315:315:315) (377:377:377)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (727:727:727)) + (PORT datab (814:814:814) (683:683:683)) + (PORT datac (227:227:227) (242:242:242)) + (PORT datad (1154:1154:1154) (971:971:971)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.SEND_CMD17) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (PORT sclr (1475:1475:1475) (1597:1597:1597)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (398:398:398)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (406:406:406)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (PORT sclr (1475:1475:1475) (1597:1597:1597)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (344:344:344) (406:406:406)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (PORT sclr (1475:1475:1475) (1597:1597:1597)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (PORT sclr (1475:1475:1475) (1597:1597:1597)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (385:385:385)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (PORT sclr (1475:1475:1475) (1597:1597:1597)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (535:535:535)) + (PORT datab (336:336:336) (396:396:396)) + (PORT datac (301:301:301) (373:373:373)) + (PORT datad (284:284:284) (343:343:343)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (PORT sclr (1475:1475:1475) (1597:1597:1597)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (401:401:401)) + (PORT datac (305:305:305) (371:371:371)) + (PORT datad (291:291:291) (353:353:353)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (437:437:437)) + (PORT datab (276:276:276) (286:286:286)) + (PORT datac (482:482:482) (425:425:425)) + (PORT datad (939:939:939) (860:860:860)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (468:468:468)) + (PORT datab (1176:1176:1176) (960:960:960)) + (PORT datad (243:243:243) (259:259:259)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.CMD17_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (286:286:286) (303:303:303)) + (PORT datab (329:329:329) (387:387:387)) + (PORT datac (506:506:506) (430:430:430)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (694:694:694)) + (PORT datab (835:835:835) (730:730:730)) + (PORT datad (1154:1154:1154) (971:971:971)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_DATA) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (561:561:561)) + (PORT datab (344:344:344) (407:407:407)) + (PORT datac (316:316:316) (386:386:386)) + (PORT datad (300:300:300) (365:365:365)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1465:1465:1465) (1586:1586:1586)) + (PORT ena (1210:1210:1210) (1105:1105:1105)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (389:389:389)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1465:1465:1465) (1586:1586:1586)) + (PORT ena (1210:1210:1210) (1105:1105:1105)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (391:391:391)) + (PORT datab (547:547:547) (533:533:533)) + (PORT datac (283:283:283) (348:348:348)) + (PORT datad (285:285:285) (344:344:344)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (309:309:309)) + (PORT datab (528:528:528) (432:432:432)) + (PORT datac (499:499:499) (425:425:425)) + (PORT datad (555:555:555) (529:529:529)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~2) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (420:420:420)) + (PORT datab (1597:1597:1597) (1427:1427:1427)) + (PORT datad (272:272:272) (289:289:289)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (425:425:425)) + (PORT datac (296:296:296) (366:366:366)) + (PORT datad (292:292:292) (353:353:353)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1334:1334:1334) (1222:1222:1222)) + (PORT datac (226:226:226) (241:241:241)) + (PORT datad (272:272:272) (290:290:290)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (420:420:420)) + (PORT datac (291:291:291) (361:361:361)) + (PORT datad (291:291:291) (352:352:352)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~11) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (408:408:408)) + (PORT datad (582:582:582) (583:583:583)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~10) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (626:626:626)) + (PORT datac (283:283:283) (351:351:351)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~9) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (626:626:626)) + (PORT datad (495:495:495) (479:479:479)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~8) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (624:624:624)) + (PORT datac (285:285:285) (351:351:351)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (394:394:394)) + (PORT datab (539:539:539) (522:522:522)) + (PORT datac (286:286:286) (352:352:352)) + (PORT datad (277:277:277) (332:332:332)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~14) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (550:550:550)) + (PORT datad (580:580:580) (582:582:582)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~13) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (622:622:622)) + (PORT datac (287:287:287) (354:354:354)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~12) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (623:623:623)) + (PORT datac (284:284:284) (350:350:350)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~15) + (DELAY + (ABSOLUTE + (PORT datab (404:404:404) (481:481:481)) + (PORT datac (284:284:284) (350:350:350)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (388:388:388)) + (PORT datab (327:327:327) (384:384:384)) + (PORT datac (515:515:515) (496:496:496)) + (PORT datad (526:526:526) (498:498:498)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~4) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (468:468:468)) + (PORT datab (278:278:278) (288:288:288)) + (PORT datac (500:500:500) (432:432:432)) + (PORT datad (482:482:482) (411:411:411)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~4) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (420:420:420)) + (PORT datab (871:871:871) (706:706:706)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~1) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (393:393:393)) + (PORT datab (405:405:405) (482:482:482)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~0) + (DELAY + (ABSOLUTE + (PORT datab (405:405:405) (481:481:481)) + (PORT datac (286:286:286) (352:352:352)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~3) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (393:393:393)) + (PORT datab (405:405:405) (481:481:481)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~2) + (DELAY + (ABSOLUTE + (PORT datab (405:405:405) (481:481:481)) + (PORT datac (287:287:287) (355:355:355)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (390:390:390)) + (PORT datab (326:326:326) (383:383:383)) + (PORT datac (282:282:282) (348:348:348)) + (PORT datad (286:286:286) (346:346:346)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (467:467:467)) + (PORT datab (278:278:278) (288:288:288)) + (PORT datac (498:498:498) (431:431:431)) + (PORT datad (482:482:482) (411:411:411)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1330:1330:1330) (1218:1218:1218)) + (PORT datab (310:310:310) (323:323:323)) + (PORT datad (272:272:272) (290:290:290)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1334:1334:1334) (1222:1222:1222)) + (PORT datab (309:309:309) (323:323:323)) + (PORT datac (437:437:437) (383:383:383)) + (PORT datad (314:314:314) (384:384:384)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1465:1465:1465) (1586:1586:1586)) + (PORT ena (1210:1210:1210) (1105:1105:1105)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1465:1465:1465) (1586:1586:1586)) + (PORT ena (1210:1210:1210) (1105:1105:1105)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (344:344:344) (407:407:407)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1465:1465:1465) (1586:1586:1586)) + (PORT ena (1210:1210:1210) (1105:1105:1105)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1465:1465:1465) (1586:1586:1586)) + (PORT ena (1210:1210:1210) (1105:1105:1105)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (404:404:404)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1465:1465:1465) (1586:1586:1586)) + (PORT ena (1210:1210:1210) (1105:1105:1105)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1465:1465:1465) (1586:1586:1586)) + (PORT ena (1210:1210:1210) (1105:1105:1105)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~3) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (312:312:312)) + (PORT datab (308:308:308) (322:322:322)) + (PORT datac (502:502:502) (492:492:492)) + (PORT datad (314:314:314) (383:383:383)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~4) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (437:437:437)) + (PORT datab (615:615:615) (570:570:570)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (502:502:502) (447:447:447)) + (PORT datab (834:834:834) (730:730:730)) + (PORT datad (501:501:501) (493:493:493)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_END) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~1) + (DELAY + (ABSOLUTE + (PORT datad (514:514:514) (499:499:499)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~2) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (396:396:396)) + (PORT datad (513:513:513) (498:498:498)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (382:382:382)) + (PORT datac (286:286:286) (353:353:353)) + (PORT datad (294:294:294) (356:356:356)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (299:299:299) (310:310:310)) + (PORT datad (516:516:516) (501:501:501)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (534:534:534) (510:510:510)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (331:331:331) (390:390:390)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT sclr (959:959:959) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (553:553:553) (528:528:528)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT sclr (959:959:959) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (332:332:332) (392:392:392)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT sclr (959:959:959) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT sclr (959:959:959) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (390:390:390)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (329:329:329) (387:387:387)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT sclr (959:959:959) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT sclr (959:959:959) (953:953:953)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (393:393:393)) + (PORT datab (326:326:326) (384:384:384)) + (PORT datac (284:284:284) (350:350:350)) + (PORT datad (286:286:286) (346:346:346)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (421:421:421)) + (PORT datab (557:557:557) (533:533:533)) + (PORT datac (292:292:292) (362:362:362)) + (PORT datad (295:295:295) (357:357:357)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~2) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (282:282:282)) + (PORT datab (300:300:300) (310:310:310)) + (PORT datad (251:251:251) (259:259:259)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (423:423:423)) + (PORT datab (325:325:325) (382:382:382)) + (PORT datad (259:259:259) (271:271:271)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (PORT ena (1522:1522:1522) (1364:1364:1364)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT asdata (710:710:710) (775:775:775)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (PORT ena (1522:1522:1522) (1364:1364:1364)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (286:286:286) (344:344:344)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (PORT ena (1522:1522:1522) (1364:1364:1364)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT asdata (931:931:931) (921:921:921)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (PORT ena (1522:1522:1522) (1364:1364:1364)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (390:390:390)) + (PORT datab (323:323:323) (380:380:380)) + (PORT datad (299:299:299) (354:354:354)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (277:277:277) (332:332:332)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (PORT ena (1522:1522:1522) (1364:1364:1364)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT asdata (723:723:723) (785:785:785)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (PORT ena (1522:1522:1522) (1364:1364:1364)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (285:285:285) (344:344:344)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (PORT ena (1522:1522:1522) (1364:1364:1364)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT asdata (714:714:714) (781:781:781)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (PORT ena (1522:1522:1522) (1364:1364:1364)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (395:395:395)) + (PORT datab (327:327:327) (384:384:384)) + (PORT datad (511:511:511) (496:496:496)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~2) + (DELAY + (ABSOLUTE + (PORT datab (873:873:873) (738:738:738)) + (PORT datad (813:813:813) (687:687:687)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (295:295:295)) + (PORT datab (1862:1862:1862) (1592:1592:1592)) + (PORT datad (230:230:230) (237:237:237)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_DATA) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1669:1669:1669)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\~0) + (DELAY + (ABSOLUTE + (PORT datad (2280:2280:2280) (2002:2002:2002)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~2) + (DELAY + (ABSOLUTE + (PORT datab (368:368:368) (431:431:431)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1644:1644:1644)) + (PORT sclr (2620:2620:2620) (2938:2938:2938)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~1) + (DELAY + (ABSOLUTE + (PORT datab (368:368:368) (431:431:431)) + (PORT datad (311:311:311) (381:381:381)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1644:1644:1644)) + (PORT sclr (2620:2620:2620) (2938:2938:2938)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (561:561:561)) + (PORT datab (371:371:371) (446:446:446)) + (PORT datac (321:321:321) (394:394:394)) + (PORT datad (308:308:308) (377:377:377)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~16) + (DELAY + (ABSOLUTE + (PORT datac (1892:1892:1892) (1670:1670:1670)) + (PORT datad (1100:1100:1100) (900:900:900)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (PORT sclr (2461:2461:2461) (2829:2829:2829)) + (PORT ena (1213:1213:1213) (1111:1111:1111)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (PORT sclr (2461:2461:2461) (2829:2829:2829)) + (PORT ena (1213:1213:1213) (1111:1111:1111)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (PORT sclr (2461:2461:2461) (2829:2829:2829)) + (PORT ena (1213:1213:1213) (1111:1111:1111)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (PORT sclr (2461:2461:2461) (2829:2829:2829)) + (PORT ena (1213:1213:1213) (1111:1111:1111)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (PORT sclr (2461:2461:2461) (2829:2829:2829)) + (PORT ena (1213:1213:1213) (1111:1111:1111)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (PORT sclr (2461:2461:2461) (2829:2829:2829)) + (PORT ena (1213:1213:1213) (1111:1111:1111)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (PORT sclr (2461:2461:2461) (2829:2829:2829)) + (PORT ena (1213:1213:1213) (1111:1111:1111)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (404:404:404)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (PORT sclr (2461:2461:2461) (2829:2829:2829)) + (PORT ena (1213:1213:1213) (1111:1111:1111)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (PORT sclr (2461:2461:2461) (2829:2829:2829)) + (PORT ena (1213:1213:1213) (1111:1111:1111)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1140:1140:1140) (942:942:942)) + (PORT datab (605:605:605) (557:557:557)) + (PORT datac (556:556:556) (528:528:528)) + (PORT datad (514:514:514) (497:497:497)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~3) + (DELAY + (ABSOLUTE + (PORT dataa (543:543:543) (447:447:447)) + (PORT datab (623:623:623) (580:580:580)) + (PORT datac (511:511:511) (501:501:501)) + (PORT datad (250:250:250) (259:259:259)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1189:1189:1189) (1031:1031:1031)) + (PORT datab (1595:1595:1595) (1376:1376:1376)) + (PORT datad (458:458:458) (393:393:393)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_BUSY) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (3810:3810:3810) (3892:3892:3892)) + (PORT datad (352:352:352) (428:428:428)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~7) + (DELAY + (ABSOLUTE + (PORT datac (287:287:287) (354:354:354)) + (PORT datad (352:352:352) (429:429:429)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~6) + (DELAY + (ABSOLUTE + (PORT datac (288:288:288) (356:356:356)) + (PORT datad (352:352:352) (428:428:428)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~5) + (DELAY + (ABSOLUTE + (PORT datac (286:286:286) (352:352:352)) + (PORT datad (352:352:352) (429:429:429)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (387:387:387)) + (PORT datab (328:328:328) (386:386:386)) + (PORT datac (280:280:280) (346:346:346)) + (PORT datad (287:287:287) (347:347:347)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~4) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (394:394:394)) + (PORT datad (352:352:352) (428:428:428)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~3) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (399:399:399)) + (PORT datad (352:352:352) (429:429:429)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~2) + (DELAY + (ABSOLUTE + (PORT datac (286:286:286) (352:352:352)) + (PORT datad (352:352:352) (429:429:429)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~1) + (DELAY + (ABSOLUTE + (PORT datac (286:286:286) (352:352:352)) + (PORT datad (352:352:352) (429:429:429)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (539:539:539)) + (PORT datab (326:326:326) (383:383:383)) + (PORT datac (282:282:282) (348:348:348)) + (PORT datad (277:277:277) (331:331:331)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT datab (268:268:268) (274:274:274)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1099:1099:1099)) + (PORT datab (1160:1160:1160) (964:964:964)) + (PORT datad (246:246:246) (260:260:260)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_END) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1669:1669:1669)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~2) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (407:407:407)) + (PORT datad (513:513:513) (505:505:505)) + (IOPATH dataa combout (375:375:375) (392:392:392)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1669:1669:1669)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~1) + (DELAY + (ABSOLUTE + (PORT datad (514:514:514) (506:506:506)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1669:1669:1669)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~0) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (406:406:406)) + (PORT datab (329:329:329) (387:387:387)) + (PORT datad (516:516:516) (508:508:508)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1669:1669:1669)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT datab (328:328:328) (385:385:385)) + (PORT datac (294:294:294) (366:366:366)) + (PORT datad (277:277:277) (331:331:331)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1627:1627:1627) (1454:1454:1454)) + (PORT datad (246:246:246) (261:261:261)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1669:1669:1669)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1625:1625:1625) (1452:1452:1452)) + (PORT datab (286:286:286) (299:299:299)) + (PORT datad (510:510:510) (502:502:502)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1669:1669:1669)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|wr_busy_dly\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (815:815:815) (722:722:722)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|wr_busy_dly) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|wr_busy_fall\~0) + (DELAY + (ABSOLUTE + (PORT datab (321:321:321) (376:376:376)) + (PORT datad (814:814:814) (721:721:721)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|rd_en) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n\~2) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (749:749:749)) + (PORT datab (301:301:301) (312:312:312)) + (PORT datad (295:295:295) (359:359:359)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_cs_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (767:767:767)) + (PORT datab (351:351:351) (411:411:411)) + (PORT datac (784:784:784) (682:682:682)) + (PORT datad (277:277:277) (332:332:332)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (413:413:413)) + (PORT datab (344:344:344) (406:406:406)) + (PORT datac (302:302:302) (373:373:373)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (418:418:418)) + (PORT datab (338:338:338) (398:398:398)) + (PORT datac (293:293:293) (362:362:362)) + (PORT datad (294:294:294) (356:356:356)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (782:782:782)) + (PORT datab (567:567:567) (553:553:553)) + (PORT datac (568:568:568) (544:544:544)) + (PORT datad (481:481:481) (410:410:410)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (284:284:284) (301:301:301)) + (PORT datab (566:566:566) (551:551:551)) + (PORT datac (566:566:566) (542:542:542)) + (PORT datad (485:485:485) (414:414:414)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (295:295:295)) + (PORT datab (532:532:532) (436:436:436)) + (PORT datac (226:226:226) (241:241:241)) + (PORT datad (250:250:250) (259:259:259)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~3) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (461:461:461)) + (PORT datab (745:745:745) (628:628:628)) + (PORT datad (227:227:227) (235:235:235)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cs_n) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_cs_n\~1) + (DELAY + (ABSOLUTE + (PORT datab (1195:1195:1195) (970:970:970)) + (PORT datac (275:275:275) (338:338:338)) + (PORT datad (796:796:796) (716:716:716)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~11) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (281:281:281)) + (PORT datab (909:909:909) (778:778:778)) + (PORT datad (850:850:850) (728:728:728)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|mosi) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1694:1694:1694) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (542:542:542)) + (PORT datab (336:336:336) (396:396:396)) + (PORT datac (301:301:301) (373:373:373)) + (PORT datad (294:294:294) (356:356:356)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (PORT sclr (1475:1475:1475) (1597:1597:1597)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~1) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (437:437:437)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (302:302:302) (374:374:374)) + (PORT datad (296:296:296) (360:360:360)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~2) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (436:436:436)) + (PORT datab (291:291:291) (298:298:298)) + (PORT datac (228:228:228) (244:244:244)) + (PORT datad (936:936:936) (855:855:855)) + (IOPATH dataa combout (377:377:377) (380:380:380)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0) + (DELAY + (ABSOLUTE + (PORT datac (228:228:228) (244:244:244)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (434:434:434)) + (PORT datab (327:327:327) (384:384:384)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (388:388:388)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datab (357:357:357) (419:419:419)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (438:438:438)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datad (254:254:254) (271:271:271)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (433:433:433)) + (PORT datab (362:362:362) (423:423:423)) + (PORT datac (228:228:228) (244:244:244)) + (PORT datad (252:252:252) (269:269:269)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (393:393:393)) + (PORT datab (325:325:325) (383:383:383)) + (PORT datad (286:286:286) (346:346:346)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (534:534:534)) + (PORT datab (324:324:324) (380:380:380)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (543:543:543)) + (PORT datab (327:327:327) (385:385:385)) + (PORT datac (282:282:282) (348:348:348)) + (PORT datad (283:283:283) (341:341:341)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1652:1652:1652)) + (PORT sclr (1077:1077:1077) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (401:401:401)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1652:1652:1652)) + (PORT sclr (1077:1077:1077) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (571:571:571)) + (PORT datab (827:827:827) (756:756:756)) + (PORT datac (516:516:516) (500:500:500)) + (PORT datad (509:509:509) (491:491:491)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (552:552:552) (461:461:461)) + (PORT datab (620:620:620) (581:581:581)) + (PORT datac (494:494:494) (425:425:425)) + (PORT datad (732:732:732) (582:582:582)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (383:383:383)) + (PORT datad (228:228:228) (236:236:236)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT datab (271:271:271) (279:279:279)) + (PORT datad (300:300:300) (356:356:356)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1652:1652:1652)) + (PORT sclr (1077:1077:1077) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1652:1652:1652)) + (PORT sclr (1077:1077:1077) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1652:1652:1652)) + (PORT sclr (1077:1077:1077) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (335:335:335) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1652:1652:1652)) + (PORT sclr (1077:1077:1077) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1652:1652:1652)) + (PORT sclr (1077:1077:1077) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1652:1652:1652)) + (PORT sclr (1077:1077:1077) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (334:334:334) (393:393:393)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1652:1652:1652)) + (PORT sclr (1077:1077:1077) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (396:396:396)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1652:1652:1652)) + (PORT sclr (1077:1077:1077) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (404:404:404)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1652:1652:1652)) + (PORT sclr (1077:1077:1077) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (407:407:407)) + (PORT datab (336:336:336) (396:396:396)) + (PORT datac (294:294:294) (364:364:364)) + (PORT datad (293:293:293) (355:355:355)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (641:641:641)) + (PORT datab (619:619:619) (579:579:579)) + (PORT datac (499:499:499) (431:431:431)) + (PORT datad (441:441:441) (379:379:379)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT datab (295:295:295) (310:310:310)) + (PORT datac (318:318:318) (398:398:398)) + (PORT datad (507:507:507) (493:493:493)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_flag) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1651:1651:1651)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_flag) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (1371:1371:1371) (1289:1289:1289)) + (PORT clrn (1684:1684:1684) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT asdata (1254:1254:1254) (1155:1155:1155)) + (PORT ena (1513:1513:1513) (1328:1328:1328)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1431:1431:1431) (1276:1276:1276)) + (PORT datab (1310:1310:1310) (1200:1200:1200)) + (PORT datac (840:840:840) (739:739:739)) + (PORT datad (1403:1403:1403) (1299:1299:1299)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (234:234:234)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (311:311:311) (329:329:329)) + (PORT datad (324:324:324) (391:391:391)) + (IOPATH dataa combout (375:375:375) (392:392:392)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1430:1430:1430) (1276:1276:1276)) + (PORT datab (1308:1308:1308) (1198:1198:1198)) + (PORT datac (841:841:841) (739:739:739)) + (PORT datad (1401:1401:1401) (1297:1297:1297)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (436:436:436)) + (PORT datab (569:569:569) (549:549:549)) + (PORT datad (457:457:457) (393:393:393)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (417:417:417)) + (PORT datab (367:367:367) (430:430:430)) + (PORT datac (265:265:265) (288:288:288)) + (PORT datad (324:324:324) (390:390:390)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (434:434:434)) + (PORT datad (241:241:241) (255:255:255)) + (IOPATH dataa combout (375:375:375) (392:392:392)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (430:430:430)) + (PORT datac (326:326:326) (399:399:399)) + (PORT datad (241:241:241) (254:254:254)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (437:437:437)) + (PORT datad (235:235:235) (246:246:246)) + (IOPATH dataa combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1273:1273:1273) (1176:1176:1176)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1594:1594:1594) (1459:1459:1459)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (276:276:276) (290:290:290)) + (PORT datad (519:519:519) (509:509:509)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (518:518:518) (502:502:502)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1513:1513:1513) (1328:1328:1328)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1272:1272:1272) (1121:1121:1121)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (280:280:280) (335:335:335)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1232:1232:1232) (1086:1086:1086)) + (PORT datab (953:953:953) (862:862:862)) + (PORT datad (295:295:295) (359:359:359)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (550:550:550) (527:527:527)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1513:1513:1513) (1328:1328:1328)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1269:1269:1269) (1114:1114:1114)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (531:531:531) (508:508:508)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (280:280:280) (335:335:335)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (294:294:294) (313:313:313)) + (PORT datab (357:357:357) (418:418:418)) + (PORT datad (525:525:525) (500:500:500)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (534:534:534) (513:513:513)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1513:1513:1513) (1328:1328:1328)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1675:1675:1675)) + (PORT asdata (1298:1298:1298) (1219:1219:1219)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (782:782:782) (682:682:682)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1674:1674:1674)) + (PORT asdata (701:701:701) (763:763:763)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1679:1679:1679)) + (PORT asdata (750:750:750) (821:821:821)) + (PORT ena (1589:1589:1589) (1445:1445:1445)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (946:946:946) (886:886:886)) + (PORT datab (346:346:346) (404:404:404)) + (PORT datad (930:930:930) (879:879:879)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1679:1679:1679)) + (PORT asdata (747:747:747) (819:819:819)) + (PORT ena (1589:1589:1589) (1445:1445:1445)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT asdata (969:969:969) (944:944:944)) + (PORT ena (1513:1513:1513) (1328:1328:1328)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (827:827:827) (771:771:771)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (491:491:491) (478:478:478)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (920:920:920) (901:901:901)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (576:576:576) (547:547:547)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1513:1513:1513) (1328:1328:1328)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (1637:1637:1637) (1503:1503:1503)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (601:601:601)) + (PORT datab (976:976:976) (891:891:891)) + (PORT datad (284:284:284) (342:342:342)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (280:280:280)) + (PORT datab (848:848:848) (703:703:703)) + (PORT datac (433:433:433) (378:378:378)) + (PORT datad (794:794:794) (667:667:667)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (1398:1398:1398) (1257:1257:1257)) + (PORT datac (1225:1225:1225) (1065:1065:1065)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (558:558:558)) + (PORT datab (367:367:367) (431:431:431)) + (PORT datad (861:861:861) (755:755:755)) + (IOPATH dataa combout (377:377:377) (377:377:377)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1410:1410:1410) (1273:1273:1273)) + (PORT datab (367:367:367) (431:431:431)) + (PORT datac (322:322:322) (386:386:386)) + (PORT datad (1253:1253:1253) (1147:1147:1147)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1594:1594:1594) (1459:1459:1459)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (432:432:432)) + (PORT datad (233:233:233) (244:244:244)) + (IOPATH dataa combout (375:375:375) (392:392:392)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[8\]) + (DELAY + (ABSOLUTE + (PORT datab (1333:1333:1333) (1216:1216:1216)) + (PORT datad (1237:1237:1237) (1116:1116:1116)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1594:1594:1594) (1459:1459:1459)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (415:415:415)) + (PORT datab (365:365:365) (428:428:428)) + (PORT datac (268:268:268) (291:291:291)) + (PORT datad (324:324:324) (391:391:391)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (229:229:229) (237:237:237)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (433:433:433)) + (PORT datab (368:368:368) (431:431:431)) + (PORT datac (325:325:325) (398:398:398)) + (PORT datad (548:548:548) (549:549:549)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1589:1589:1589) (1445:1445:1445)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (320:320:320) (375:375:375)) + (PORT datac (278:278:278) (341:341:341)) + (PORT datad (1258:1258:1258) (1143:1143:1143)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity6) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1594:1594:1594) (1459:1459:1459)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datad (300:300:300) (356:356:356)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1594:1594:1594) (1459:1459:1459)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (368:368:368) (431:431:431)) + (IOPATH datab combout (438:438:438) (455:455:455)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1594:1594:1594) (1459:1459:1459)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1145:1145:1145) (1018:1018:1018)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (916:916:916) (909:909:909)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (1369:1369:1369) (1281:1281:1281)) + (PORT ena (1663:1663:1663) (1506:1506:1506)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (739:739:739) (808:808:808)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (529:529:529) (503:503:503)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (866:866:866)) + (PORT datab (904:904:904) (823:823:823)) + (PORT datad (277:277:277) (331:331:331)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (295:295:295)) + (PORT datab (318:318:318) (372:372:372)) + (PORT datad (235:235:235) (245:245:245)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1513:1513:1513) (1328:1328:1328)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0) + (DELAY + (ABSOLUTE + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (294:294:294)) + (PORT datab (885:885:885) (726:726:726)) + (PORT datad (234:234:234) (244:244:244)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (785:785:785)) + (PORT datab (865:865:865) (774:774:774)) + (PORT datac (727:727:727) (605:605:605)) + (PORT datad (492:492:492) (475:475:475)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (553:553:553)) + (PORT datab (358:358:358) (419:419:419)) + (PORT datac (530:530:530) (519:519:519)) + (PORT datad (250:250:250) (268:268:268)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (370:370:370) (434:434:434)) + (PORT datad (241:241:241) (254:254:254)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (553:553:553)) + (PORT datab (369:369:369) (432:432:432)) + (PORT datac (331:331:331) (398:398:398)) + (PORT datad (513:513:513) (503:503:503)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a1) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1514:1514:1514) (1346:1346:1346)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (896:896:896) (789:789:789)) + (PORT datab (360:360:360) (422:422:422)) + (PORT datac (827:827:827) (745:745:745)) + (PORT datad (315:315:315) (378:378:378)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a0) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1514:1514:1514) (1346:1346:1346)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (383:383:383)) + (PORT datab (321:321:321) (376:376:376)) + (PORT datac (279:279:279) (342:342:342)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity8) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1514:1514:1514) (1346:1346:1346)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datad (833:833:833) (769:769:769)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1313:1313:1313) (1211:1211:1211)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (PORT datab (348:348:348) (405:405:405)) + (PORT datac (529:529:529) (459:459:459)) + (PORT datad (832:832:832) (768:768:768)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT datad (693:693:693) (573:573:573)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (420:420:420)) + (PORT datad (250:250:250) (269:269:269)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (553:553:553)) + (PORT datab (359:359:359) (421:421:421)) + (PORT datac (530:530:530) (518:518:518)) + (PORT datad (251:251:251) (270:270:270)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\]\~6) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (234:234:234)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (571:571:571)) + (PORT datab (368:368:368) (432:432:432)) + (PORT datad (242:242:242) (256:256:256)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT datab (368:368:368) (432:432:432)) + (PORT datac (327:327:327) (394:394:394)) + (PORT datad (241:241:241) (254:254:254)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (561:561:561) (549:549:549)) + (PORT datad (235:235:235) (247:247:247)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT asdata (991:991:991) (961:961:961)) + (PORT ena (1513:1513:1513) (1328:1328:1328)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (1576:1576:1576) (1444:1444:1444)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (704:704:704) (766:766:766)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (700:700:700) (761:761:761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datac (296:296:296) (365:365:365)) + (PORT datad (301:301:301) (366:366:366)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (429:429:429)) + (PORT datab (372:372:372) (436:436:436)) + (PORT datad (240:240:240) (254:254:254)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1675:1675:1675)) + (PORT asdata (1390:1390:1390) (1327:1327:1327)) + (PORT ena (1495:1495:1495) (1350:1350:1350)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1239:1239:1239) (1118:1118:1118)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1594:1594:1594) (1459:1459:1459)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (1293:1293:1293) (1143:1143:1143)) + (PORT datac (332:332:332) (400:400:400)) + (PORT datad (1165:1165:1165) (1028:1028:1028)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (393:393:393)) + (PORT datab (324:324:324) (380:380:380)) + (PORT datac (289:289:289) (357:357:357)) + (PORT datad (296:296:296) (360:360:360)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1363:1363:1363) (1245:1245:1245)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1663:1663:1663) (1506:1506:1506)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1141:1141:1141)) + (PORT datab (1204:1204:1204) (1064:1064:1064)) + (PORT datac (329:329:329) (397:397:397)) + (PORT datad (910:910:910) (843:843:843)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT datac (307:307:307) (374:374:374)) + (PORT datad (803:803:803) (701:701:701)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (1401:1401:1401) (1273:1273:1273)) + (PORT datac (310:310:310) (377:377:377)) + (PORT datad (801:801:801) (698:698:698)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (1754:1754:1754) (1626:1626:1626)) + (PORT ena (1663:1663:1663) (1506:1506:1506)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT dataa (1401:1401:1401) (1273:1273:1273)) + (PORT datab (1599:1599:1599) (1414:1414:1414)) + (PORT datac (306:306:306) (372:372:372)) + (PORT datad (801:801:801) (699:699:699)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (521:521:521) (512:512:512)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1513:1513:1513) (1328:1328:1328)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1675:1675:1675)) + (PORT asdata (1251:1251:1251) (1193:1193:1193)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (788:788:788) (688:688:688)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (277:277:277) (331:331:331)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT asdata (993:993:993) (965:965:965)) + (PORT ena (1513:1513:1513) (1328:1328:1328)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1675:1675:1675)) + (PORT asdata (1599:1599:1599) (1451:1451:1451)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (836:836:836) (715:715:715)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1674:1674:1674)) + (PORT asdata (703:703:703) (765:765:765)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (PORT datab (534:534:534) (519:519:519)) + (PORT datac (305:305:305) (372:372:372)) + (PORT datad (1531:1531:1531) (1264:1264:1264)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT datac (870:870:870) (765:765:765)) + (PORT datad (717:717:717) (597:597:597)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT asdata (1676:1676:1676) (1573:1573:1573)) + (PORT ena (1663:1663:1663) (1506:1506:1506)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (302:302:302)) + (PORT datac (316:316:316) (387:387:387)) + (PORT datad (534:534:534) (521:521:521)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (589:589:589) (503:503:503)) + (PORT datab (351:351:351) (409:409:409)) + (PORT datad (834:834:834) (770:770:770)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (809:809:809) (720:720:720)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1513:1513:1513) (1328:1328:1328)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1136:1136:1136) (1003:1003:1003)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1674:1674:1674)) + (PORT asdata (1233:1233:1233) (1119:1119:1119)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (279:279:279) (334:334:334)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT dataa (843:843:843) (736:736:736)) + (PORT datab (337:337:337) (397:397:397)) + (PORT datac (334:334:334) (401:401:401)) + (PORT datad (255:255:255) (266:266:266)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (737:737:737)) + (PORT datab (1170:1170:1170) (1026:1026:1026)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (804:804:804)) + (PORT datab (589:589:589) (544:544:544)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (531:531:531)) + (PORT datab (931:931:931) (827:827:827)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (554:554:554)) + (PORT datab (857:857:857) (791:791:791)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (379:379:379)) + (PORT datab (520:520:520) (499:499:499)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (381:381:381)) + (PORT datad (516:516:516) (487:487:487)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|comb\~1) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (425:425:425)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (226:226:226) (242:242:242)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|comb\~0) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (281:281:281)) + (PORT datab (1912:1912:1912) (1696:1696:1696)) + (PORT datac (226:226:226) (241:241:241)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|comb\~2) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (270:270:270) (277:277:277)) + (PORT datac (224:224:224) (239:239:239)) + (PORT datad (225:225:225) (232:232:232)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1957:1957:1957) (1644:1644:1644)) + (PORT datab (350:350:350) (408:408:408)) + (PORT datac (1576:1576:1576) (1408:1408:1408)) + (PORT datad (814:814:814) (699:699:699)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (296:296:296)) + (PORT datab (874:874:874) (739:739:739)) + (PORT datac (225:225:225) (240:240:240)) + (PORT datad (815:815:815) (690:690:690)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.SEND_CMD24) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1669:1669:1669)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (344:344:344) (406:406:406)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1685:1685:1685)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1650:1650:1650)) + (PORT sclr (2316:2316:2316) (2582:2582:2582)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (344:344:344) (407:407:407)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1685:1685:1685)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1650:1650:1650)) + (PORT sclr (2316:2316:2316) (2582:2582:2582)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (403:403:403)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1685:1685:1685)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1650:1650:1650)) + (PORT sclr (2316:2316:2316) (2582:2582:2582)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (419:419:419)) + (PORT datab (345:345:345) (408:408:408)) + (PORT datac (300:300:300) (371:371:371)) + (PORT datad (301:301:301) (366:366:366)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (403:403:403)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1685:1685:1685)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1650:1650:1650)) + (PORT sclr (2316:2316:2316) (2582:2582:2582)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1685:1685:1685)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1650:1650:1650)) + (PORT sclr (2316:2316:2316) (2582:2582:2582)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~2) + (DELAY + (ABSOLUTE + (PORT datab (267:267:267) (274:274:274)) + (PORT datac (303:303:303) (377:377:377)) + (PORT datad (301:301:301) (367:367:367)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (405:405:405)) + (PORT datac (300:300:300) (371:371:371)) + (PORT datad (298:298:298) (362:362:362)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (281:281:281)) + (PORT datab (342:342:342) (405:405:405)) + (PORT datac (303:303:303) (378:378:378)) + (PORT datad (236:236:236) (247:247:247)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (484:484:484) (425:425:425)) + (PORT datac (1901:1901:1901) (1690:1690:1690)) + (PORT datad (772:772:772) (643:643:643)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (801:801:801)) + (PORT datab (1942:1942:1942) (1721:1721:1721)) + (PORT datac (1892:1892:1892) (1670:1670:1670)) + (PORT datad (517:517:517) (500:500:500)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (281:281:281)) + (PORT datab (1944:1944:1944) (1723:1723:1723)) + (PORT datac (225:225:225) (240:240:240)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1685:1685:1685)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1650:1650:1650)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_mosi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (767:767:767)) + (PORT datab (914:914:914) (824:824:824)) + (PORT datac (1643:1643:1643) (1466:1466:1466)) + (PORT datad (312:312:312) (374:374:374)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_mosi\~1) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (752:752:752)) + (PORT datac (863:863:863) (794:794:794)) + (PORT datad (226:226:226) (232:232:232)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2044:2044:2044) (2012:2012:2012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (827:827:827)) + (PORT datab (324:324:324) (380:380:380)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (392:392:392)) + (PORT datab (327:327:327) (384:384:384)) + (PORT datac (283:283:283) (348:348:348)) + (PORT datad (283:283:283) (341:341:341)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (793:793:793)) + (PORT datab (859:859:859) (679:679:679)) + (PORT datac (871:871:871) (791:791:791)) + (PORT datad (903:903:903) (802:802:802)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (399:399:399)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1426:1426:1426) (1369:1369:1369)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (410:410:410)) + (PORT datab (337:337:337) (397:397:397)) + (PORT datac (295:295:295) (364:364:364)) + (PORT datad (295:295:295) (358:358:358)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (840:840:840)) + (PORT datac (879:879:879) (803:803:803)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (824:824:824)) + (PORT datab (278:278:278) (289:289:289)) + (PORT datac (797:797:797) (670:670:670)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1426:1426:1426) (1369:1369:1369)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (332:332:332) (391:391:391)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1426:1426:1426) (1369:1369:1369)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1426:1426:1426) (1369:1369:1369)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (335:335:335) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1426:1426:1426) (1369:1369:1369)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1426:1426:1426) (1369:1369:1369)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1426:1426:1426) (1369:1369:1369)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1426:1426:1426) (1369:1369:1369)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1426:1426:1426) (1369:1369:1369)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (404:404:404)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1426:1426:1426) (1369:1369:1369)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (409:409:409)) + (PORT datab (336:336:336) (397:397:397)) + (PORT datac (295:295:295) (364:364:364)) + (PORT datad (295:295:295) (358:358:358)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (841:841:841)) + (PORT datab (932:932:932) (838:838:838)) + (PORT datac (1099:1099:1099) (885:885:885)) + (PORT datad (238:238:238) (250:250:250)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1026:1026:1026)) + (PORT datad (1147:1147:1147) (1004:1004:1004)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (296:296:296)) + (PORT datab (1210:1210:1210) (1047:1047:1047)) + (PORT datac (332:332:332) (417:417:417)) + (PORT datad (292:292:292) (355:355:355)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1153:1153:1153) (1026:1026:1026)) + (PORT datab (1213:1213:1213) (1051:1051:1051)) + (PORT datad (276:276:276) (297:297:297)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1666:1666:1666) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1698:1698:1698) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (340:340:340)) + (PORT datab (376:376:376) (451:451:451)) + (PORT datad (247:247:247) (262:262:262)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1666:1666:1666) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1698:1698:1698) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (538:538:538)) + (PORT datab (336:336:336) (396:396:396)) + (PORT datac (335:335:335) (421:421:421)) + (PORT datad (325:325:325) (401:401:401)) + (IOPATH dataa combout (377:377:377) (392:392:392)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (340:340:340)) + (PORT datab (287:287:287) (300:300:300)) + (PORT datad (229:229:229) (236:236:236)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1666:1666:1666) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1698:1698:1698) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (393:393:393)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (575:575:575)) + (PORT datac (829:829:829) (742:742:742)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|rd_busy_dly) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT asdata (1594:1594:1594) (1462:1462:1462)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (322:322:322) (379:379:379)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1443:1443:1443) (1567:1567:1567)) + (PORT ena (1557:1557:1557) (1415:1415:1415)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (323:323:323) (380:380:380)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1443:1443:1443) (1567:1567:1567)) + (PORT ena (1557:1557:1557) (1415:1415:1415)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (324:324:324) (380:380:380)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1443:1443:1443) (1567:1567:1567)) + (PORT ena (1557:1557:1557) (1415:1415:1415)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (393:393:393)) + (PORT datab (328:328:328) (385:385:385)) + (PORT datac (284:284:284) (350:350:350)) + (PORT datad (287:287:287) (345:345:345)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1443:1443:1443) (1567:1567:1567)) + (PORT ena (1557:1557:1557) (1415:1415:1415)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (389:389:389)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1443:1443:1443) (1567:1567:1567)) + (PORT ena (1557:1557:1557) (1415:1415:1415)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1653:1653:1653) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1638:1638:1638)) + (PORT sclr (1443:1443:1443) (1567:1567:1567)) + (PORT ena (1557:1557:1557) (1415:1415:1415)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (394:394:394)) + (PORT datab (327:327:327) (384:384:384)) + (PORT datac (284:284:284) (350:350:350)) + (PORT datad (286:286:286) (346:346:346)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~3) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (420:420:420)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (225:225:225) (240:240:240)) + (PORT datad (820:820:820) (697:697:697)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1274:1274:1274) (1139:1139:1139)) + (PORT datab (321:321:321) (376:376:376)) + (PORT datad (1015:1015:1015) (839:839:839)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_en) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (570:570:570)) + (PORT datab (560:560:560) (536:536:536)) + (PORT datac (511:511:511) (501:501:501)) + (PORT datad (543:543:543) (514:514:514)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (293:293:293)) + (PORT datab (270:270:270) (277:277:277)) + (PORT datac (298:298:298) (361:361:361)) + (PORT datad (227:227:227) (235:235:235)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (393:393:393)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (393:393:393)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (565:565:565)) + (PORT datab (557:557:557) (533:533:533)) + (PORT datac (507:507:507) (497:497:497)) + (PORT datad (539:539:539) (511:511:511)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (553:553:553) (534:534:534)) + (PORT datab (543:543:543) (522:522:522)) + (PORT datac (510:510:510) (491:491:491)) + (PORT datad (536:536:536) (506:506:506)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT sclr (1064:1064:1064) (1056:1056:1056)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (730:730:730)) + (PORT datab (601:601:601) (551:551:551)) + (PORT datac (761:761:761) (685:685:685)) + (PORT datad (503:503:503) (484:484:484)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1483:1483:1483) (1295:1295:1295)) + (PORT datab (542:542:542) (521:521:521)) + (PORT datac (227:227:227) (242:242:242)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (575:575:575)) + (PORT datab (267:267:267) (274:274:274)) + (PORT datac (829:829:829) (742:742:742)) + (PORT datad (235:235:235) (246:246:246)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|rd_fifo_rd_en) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (281:281:281)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1671:1671:1671) (1692:1692:1692)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (419:419:419)) + (PORT datac (329:329:329) (406:406:406)) + (PORT datad (240:240:240) (254:254:254)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (419:419:419)) + (PORT datad (233:233:233) (243:243:243)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1671:1671:1671) (1692:1692:1692)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (858:858:858) (769:769:769)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1694:1694:1694)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1275:1275:1275) (1180:1180:1180)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (793:793:793)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (883:883:883) (815:815:815)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1065:1065:1065) (1040:1040:1040)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1682:1682:1682)) + (PORT asdata (1255:1255:1255) (1180:1180:1180)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1682:1682:1682)) + (PORT asdata (701:701:701) (762:762:762)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT asdata (1332:1332:1332) (1263:1263:1263)) + (PORT ena (1320:1320:1320) (1212:1212:1212)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (300:300:300) (356:356:356)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (847:847:847) (759:759:759)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1088:1088:1088)) + (PORT datab (341:341:341) (397:397:397)) + (PORT datad (277:277:277) (332:332:332)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (561:561:561)) + (PORT datab (345:345:345) (407:407:407)) + (PORT datac (317:317:317) (387:387:387)) + (PORT datad (300:300:300) (365:365:365)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (311:311:311)) + (PORT datab (469:469:469) (403:403:403)) + (PORT datac (501:501:501) (428:428:428)) + (PORT datad (554:554:554) (528:528:528)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1332:1332:1332) (1220:1220:1220)) + (PORT datab (351:351:351) (417:417:417)) + (PORT datac (473:473:473) (410:410:410)) + (PORT datad (259:259:259) (270:270:270)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1682:1682:1682)) + (PORT asdata (1372:1372:1372) (1285:1285:1285)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1682:1682:1682)) + (PORT asdata (703:703:703) (764:764:764)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (831:831:831) (764:764:764)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1695:1695:1695)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1599:1599:1599) (1424:1424:1424)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1695:1695:1695)) + (PORT asdata (726:726:726) (788:788:788)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (539:539:539) (512:512:512)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (561:561:561)) + (PORT datab (612:612:612) (568:568:568)) + (PORT datad (276:276:276) (331:331:331)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (905:905:905) (825:825:825)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1214:1214:1214) (1110:1110:1110)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1694:1694:1694)) + (PORT asdata (1797:1797:1797) (1601:1601:1601)) + (PORT ena (1275:1275:1275) (1180:1180:1180)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (299:299:299) (355:355:355)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1694:1694:1694)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1682:1682:1682)) + (PORT asdata (1346:1346:1346) (1253:1253:1253)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (417:417:417)) + (PORT datab (357:357:357) (418:418:418)) + (PORT datac (497:497:497) (424:424:424)) + (PORT datad (313:313:313) (376:376:376)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1285:1285:1285) (1094:1094:1094)) + (PORT datab (956:956:956) (840:840:840)) + (PORT datad (264:264:264) (278:278:278)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1671:1671:1671) (1692:1692:1692)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (577:577:577) (549:549:549)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1672:1672:1672) (1693:1693:1693)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1063:1063:1063) (1037:1037:1037)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (819:819:819) (734:734:734)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1695:1695:1695)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (911:911:911) (822:822:822)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (838:838:838)) + (PORT datab (535:535:535) (525:525:525)) + (PORT datad (276:276:276) (331:331:331)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (787:787:787) (723:723:723)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1506:1506:1506) (1346:1346:1346)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT asdata (723:723:723) (785:785:785)) + (PORT ena (1320:1320:1320) (1212:1212:1212)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (301:301:301) (357:357:357)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT asdata (701:701:701) (762:762:762)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (311:311:311) (370:370:370)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1320:1320:1320) (1212:1212:1212)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (299:299:299) (354:354:354)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (280:280:280) (335:335:335)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (532:532:532)) + (PORT datab (862:862:862) (796:796:796)) + (PORT datad (276:276:276) (331:331:331)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (281:281:281)) + (PORT datab (267:267:267) (274:274:274)) + (PORT datac (226:226:226) (241:241:241)) + (PORT datad (819:819:819) (676:676:676)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT datab (278:278:278) (288:288:288)) + (PORT datac (1784:1784:1784) (1562:1562:1562)) + (PORT datad (235:235:235) (246:246:246)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a0) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1506:1506:1506) (1346:1346:1346)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (793:793:793)) + (PORT datab (360:360:360) (421:421:421)) + (PORT datad (759:759:759) (646:646:646)) + (IOPATH dataa combout (377:377:377) (377:377:377)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (850:850:850)) + (PORT datab (550:550:550) (538:538:538)) + (PORT datac (281:281:281) (301:301:301)) + (PORT datad (877:877:877) (808:808:808)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (838:838:838)) + (PORT datab (834:834:834) (767:767:767)) + (PORT datad (770:770:770) (646:646:646)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (835:835:835) (768:768:768)) + (PORT datad (771:771:771) (646:646:646)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|cntr_cout\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (738:738:738)) + (PORT datab (931:931:931) (854:854:854)) + (PORT datac (805:805:805) (739:739:739)) + (PORT datad (448:448:448) (385:385:385)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6\~0) + (DELAY + (ABSOLUTE + (PORT datab (966:966:966) (863:863:863)) + (PORT datad (239:239:239) (252:252:252)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (825:825:825)) + (PORT datab (347:347:347) (410:410:410)) + (PORT datac (307:307:307) (381:381:381)) + (PORT datad (907:907:907) (827:827:827)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1214:1214:1214) (1110:1110:1110)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT datab (968:968:968) (867:867:867)) + (PORT datac (306:306:306) (379:379:379)) + (PORT datad (243:243:243) (256:256:256)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9\~0) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (407:407:407)) + (PORT datad (235:235:235) (246:246:246)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (PORT datac (497:497:497) (490:490:490)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1214:1214:1214) (1110:1110:1110)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (837:837:837)) + (PORT datab (360:360:360) (421:421:421)) + (PORT datac (302:302:302) (366:366:366)) + (PORT datad (794:794:794) (731:731:731)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1506:1506:1506) (1346:1346:1346)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (320:320:320) (374:374:374)) + (PORT datac (278:278:278) (342:342:342)) + (PORT datad (839:839:839) (766:766:766)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity9) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1214:1214:1214) (1110:1110:1110)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1829:1829:1829) (1602:1602:1602)) + (PORT datab (279:279:279) (290:290:290)) + (PORT datac (506:506:506) (503:503:503)) + (PORT datad (236:236:236) (247:247:247)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (849:849:849)) + (PORT datab (942:942:942) (853:853:853)) + (PORT datad (227:227:227) (235:235:235)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (415:415:415)) + (PORT datab (830:830:830) (762:762:762)) + (PORT datac (775:775:775) (635:635:635)) + (PORT datad (859:859:859) (787:787:787)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (234:234:234)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (413:413:413)) + (PORT datab (965:965:965) (864:864:864)) + (PORT datad (239:239:239) (252:252:252)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8\~0) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (408:408:408)) + (PORT datad (235:235:235) (245:245:245)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1680:1680:1680)) + (PORT asdata (923:923:923) (913:913:913)) + (PORT ena (1214:1214:1214) (1110:1110:1110)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1680:1680:1680)) + (PORT asdata (723:723:723) (785:785:785)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1672:1672:1672) (1693:1693:1693)) + (PORT asdata (1178:1178:1178) (1090:1090:1090)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1672:1672:1672) (1693:1693:1693)) + (PORT asdata (700:700:700) (761:761:761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (288:288:288) (346:346:346)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1214:1214:1214) (1110:1110:1110)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (779:779:779) (698:698:698)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1695:1695:1695)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (281:281:281) (336:336:336)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1695:1695:1695)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (280:280:280) (336:336:336)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1695:1695:1695)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (737:737:737)) + (PORT datab (598:598:598) (547:547:547)) + (PORT datad (771:771:771) (679:679:679)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1694:1694:1694)) + (PORT asdata (1263:1263:1263) (1184:1184:1184)) + (PORT ena (1275:1275:1275) (1180:1180:1180)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (302:302:302) (368:368:368)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1214:1214:1214) (1110:1110:1110)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (808:808:808) (719:719:719)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1694:1694:1694)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (277:277:277) (332:332:332)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1694:1694:1694)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1694:1694:1694)) + (PORT asdata (702:702:702) (763:763:763)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1663:1663:1663) (1680:1680:1680)) + (PORT asdata (729:729:729) (800:800:800)) + (PORT ena (1214:1214:1214) (1110:1110:1110)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (810:810:810) (714:714:714)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1694:1694:1694)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1694:1694:1694)) + (PORT asdata (701:701:701) (762:762:762)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (334:334:334)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1694:1694:1694)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (388:388:388)) + (PORT datab (556:556:556) (529:529:529)) + (PORT datad (276:276:276) (331:331:331)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (518:518:518) (507:507:507)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (929:929:929) (856:856:856)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1682:1682:1682)) + (PORT asdata (703:703:703) (765:765:765)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (859:859:859) (787:787:787)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1506:1506:1506) (1346:1346:1346)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1682:1682:1682)) + (PORT asdata (1526:1526:1526) (1374:1374:1374)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (277:277:277) (332:332:332)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (277:277:277) (332:332:332)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (791:791:791)) + (PORT datab (1149:1149:1149) (984:984:984)) + (PORT datad (278:278:278) (333:333:333)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (282:282:282)) + (PORT datab (267:267:267) (274:274:274)) + (PORT datac (439:439:439) (375:375:375)) + (PORT datad (758:758:758) (625:625:625)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1096:1096:1096) (897:897:897)) + (PORT datab (1772:1772:1772) (1505:1505:1505)) + (PORT datac (232:232:232) (250:250:250)) + (PORT datad (235:235:235) (246:246:246)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1359:1359:1359) (1260:1260:1260)) + (PORT datab (956:956:956) (871:871:871)) + (PORT datac (1153:1153:1153) (1031:1031:1031)) + (PORT datad (809:809:809) (683:683:683)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT datad (229:229:229) (237:237:237)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (744:744:744)) + (PORT datad (305:305:305) (364:364:364)) + (IOPATH dataa combout (375:375:375) (392:392:392)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1284:1284:1284) (1093:1093:1093)) + (PORT datab (956:956:956) (840:840:840)) + (PORT datac (335:335:335) (404:404:404)) + (PORT datad (263:263:263) (278:278:278)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (445:445:445)) + (PORT datad (242:242:242) (256:256:256)) + (IOPATH dataa combout (375:375:375) (392:392:392)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1671:1671:1671) (1692:1692:1692)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (450:450:450)) + (PORT datab (360:360:360) (421:421:421)) + (PORT datad (239:239:239) (252:252:252)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1671:1671:1671) (1692:1692:1692)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (423:423:423)) + (PORT datad (234:234:234) (244:244:244)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1671:1671:1671) (1692:1692:1692)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[9\]) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (404:404:404)) + (PORT datad (299:299:299) (354:354:354)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a2) + (DELAY + (ABSOLUTE + (PORT clk (1671:1671:1671) (1692:1692:1692)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1230:1230:1230) (1134:1134:1134)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (446:446:446)) + (PORT datab (359:359:359) (421:421:421)) + (PORT datac (339:339:339) (408:408:408)) + (PORT datad (317:317:317) (381:381:381)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a1) + (DELAY + (ABSOLUTE + (PORT clk (1671:1671:1671) (1692:1692:1692)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1230:1230:1230) (1134:1134:1134)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (416:416:416)) + (PORT datab (953:953:953) (837:837:837)) + (PORT datac (318:318:318) (390:390:390)) + (PORT datad (1219:1219:1219) (1046:1046:1046)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a0) + (DELAY + (ABSOLUTE + (PORT clk (1671:1671:1671) (1692:1692:1692)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1230:1230:1230) (1134:1134:1134)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT datab (320:320:320) (375:375:375)) + (PORT datac (278:278:278) (341:341:341)) + (PORT datad (487:487:487) (469:469:469)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity5) + (DELAY + (ABSOLUTE + (PORT clk (1671:1671:1671) (1692:1692:1692)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1230:1230:1230) (1134:1134:1134)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datad (315:315:315) (377:377:377)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1671:1671:1671) (1692:1692:1692)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1230:1230:1230) (1134:1134:1134)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (471:471:471)) + (PORT datab (362:362:362) (423:423:423)) + (PORT datad (313:313:313) (376:376:376)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1671:1671:1671) (1692:1692:1692)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT asdata (1738:1738:1738) (1642:1642:1642)) + (PORT ena (1320:1320:1320) (1212:1212:1212)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (421:421:421)) + (IOPATH datab combout (438:438:438) (455:455:455)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1506:1506:1506) (1346:1346:1346)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (300:300:300) (356:356:356)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT asdata (702:702:702) (763:763:763)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1672:1672:1672) (1693:1693:1693)) + (PORT asdata (1232:1232:1232) (1134:1134:1134)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1672:1672:1672) (1693:1693:1693)) + (PORT asdata (1208:1208:1208) (1127:1127:1127)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1672:1672:1672) (1693:1693:1693)) + (PORT asdata (913:913:913) (902:902:902)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (279:279:279) (334:334:334)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1672:1672:1672) (1693:1693:1693)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (771:771:771)) + (PORT datab (918:918:918) (788:788:788)) + (PORT datad (275:275:275) (330:330:330)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT datab (1771:1771:1771) (1503:1503:1503)) + (PORT datac (236:236:236) (254:254:254)) + (PORT datad (233:233:233) (243:243:243)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (3766:3766:3766) (3815:3815:3815)) + (PORT datab (1188:1188:1188) (1017:1017:1017)) + (PORT datac (1223:1223:1223) (1112:1112:1112)) + (PORT datad (858:858:858) (759:759:759)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~13) + (DELAY + (ABSOLUTE + (PORT datac (1290:1290:1290) (1184:1184:1184)) + (PORT datad (897:897:897) (826:826:826)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1329:1329:1329) (1217:1217:1217)) + (PORT datab (347:347:347) (413:413:413)) + (PORT datac (472:472:472) (410:410:410)) + (PORT datad (259:259:259) (271:271:271)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1544:1544:1544) (1395:1395:1395)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1270:1270:1270) (1155:1155:1155)) + (PORT datab (901:901:901) (798:798:798)) + (PORT datac (1135:1135:1135) (983:983:983)) + (PORT datad (300:300:300) (355:355:355)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1268:1268:1268) (1152:1152:1152)) + (PORT datab (899:899:899) (796:796:796)) + (PORT datac (1138:1138:1138) (986:986:986)) + (PORT datad (300:300:300) (356:356:356)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1267:1267:1267) (1151:1151:1151)) + (PORT datab (898:898:898) (795:795:795)) + (PORT datac (1140:1140:1140) (989:989:989)) + (PORT datad (301:301:301) (357:357:357)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1267:1267:1267) (1151:1151:1151)) + (PORT datab (899:899:899) (795:795:795)) + (PORT datac (1140:1140:1140) (989:989:989)) + (PORT datad (300:300:300) (356:356:356)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1266:1266:1266) (1150:1150:1150)) + (PORT datab (898:898:898) (795:795:795)) + (PORT datac (1141:1141:1141) (990:990:990)) + (PORT datad (301:301:301) (356:356:356)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1651:1651:1651) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1242:1242:1242) (1061:1061:1061)) + (PORT datab (1267:1267:1267) (1087:1087:1087)) + (PORT datac (1572:1572:1572) (1413:1413:1413)) + (PORT datad (882:882:882) (811:811:811)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1688:1688:1688) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1242:1242:1242) (1061:1061:1061)) + (PORT datab (1267:1267:1267) (1087:1087:1087)) + (PORT datac (1571:1571:1571) (1412:1412:1412)) + (PORT datad (284:284:284) (343:343:343)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1688:1688:1688) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1622:1622:1622) (1461:1461:1461)) + (PORT datab (1267:1267:1267) (1087:1087:1087)) + (PORT datac (286:286:286) (354:354:354)) + (PORT datad (1173:1173:1173) (1011:1011:1011)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1688:1688:1688) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~14) + (DELAY + (ABSOLUTE + (PORT datac (1582:1582:1582) (1424:1424:1424)) + (PORT datad (287:287:287) (345:345:345)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1688:1688:1688) (1639:1639:1639)) + (PORT ena (1854:1854:1854) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (310:310:310) (371:371:371)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1506:1506:1506) (1346:1346:1346)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[8\]) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (353:353:353)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0) + (DELAY + (ABSOLUTE + (PORT datad (229:229:229) (236:236:236)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0) + (DELAY + (ABSOLUTE + (PORT clk (1673:1673:1673) (1695:1695:1695)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1599:1599:1599) (1424:1424:1424)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (286:286:286) (346:346:346)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~15) + (DELAY + (ABSOLUTE + (PORT datab (957:957:957) (867:867:867)) + (PORT datac (1296:1296:1296) (1191:1191:1191)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1544:1544:1544) (1395:1395:1395)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~11) + (DELAY + (ABSOLUTE + (PORT datac (1291:1291:1291) (1185:1185:1185)) + (PORT datad (857:857:857) (794:794:794)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1544:1544:1544) (1395:1395:1395)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~7) + (DELAY + (ABSOLUTE + (PORT datac (1305:1305:1305) (1200:1200:1200)) + (PORT datad (897:897:897) (825:825:825)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1544:1544:1544) (1395:1395:1395)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~5) + (DELAY + (ABSOLUTE + (PORT datac (1303:1303:1303) (1198:1198:1198)) + (PORT datad (909:909:909) (836:836:836)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1544:1544:1544) (1395:1395:1395)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~3) + (DELAY + (ABSOLUTE + (PORT datac (1572:1572:1572) (1414:1414:1414)) + (PORT datad (882:882:882) (811:811:811)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1688:1688:1688) (1639:1639:1639)) + (PORT ena (1854:1854:1854) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~9) + (DELAY + (ABSOLUTE + (PORT datac (1580:1580:1580) (1422:1422:1422)) + (PORT datad (286:286:286) (344:344:344)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1688:1688:1688) (1639:1639:1639)) + (PORT ena (1854:1854:1854) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~0) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (392:392:392)) + (PORT datac (1570:1570:1570) (1411:1411:1411)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1688:1688:1688) (1639:1639:1639)) + (PORT ena (1854:1854:1854) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1239:1239:1239) (1058:1058:1058)) + (PORT datab (1269:1269:1269) (1089:1089:1089)) + (PORT datac (1578:1578:1578) (1420:1420:1420)) + (PORT datad (286:286:286) (345:345:345)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1688:1688:1688) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~16) + (DELAY + (ABSOLUTE + (PORT datac (1567:1567:1567) (1409:1409:1409)) + (PORT datad (288:288:288) (347:347:347)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1688:1688:1688) (1639:1639:1639)) + (PORT ena (1854:1854:1854) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (395:395:395)) + (PORT datac (1579:1579:1579) (1421:1421:1421)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1688:1688:1688) (1639:1639:1639)) + (PORT ena (1854:1854:1854) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (397:397:397)) + (PORT datac (1581:1581:1581) (1423:1423:1423)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1656:1656:1656) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1688:1688:1688) (1639:1639:1639)) + (PORT ena (1854:1854:1854) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~6) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (803:803:803)) + (PORT datac (1302:1302:1302) (1197:1197:1197)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1544:1544:1544) (1395:1395:1395)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (806:806:806)) + (PORT datab (1139:1139:1139) (982:982:982)) + (PORT datac (1294:1294:1294) (1189:1189:1189)) + (PORT datad (831:831:831) (730:730:730)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~4) + (DELAY + (ABSOLUTE + (PORT datac (1300:1300:1300) (1195:1195:1195)) + (PORT datad (286:286:286) (344:344:344)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1544:1544:1544) (1395:1395:1395)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~10) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (398:398:398)) + (PORT datac (1304:1304:1304) (1199:1199:1199)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1544:1544:1544) (1395:1395:1395)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~1) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (395:395:395)) + (PORT datab (1139:1139:1139) (982:982:982)) + (PORT datac (1295:1295:1295) (1190:1190:1190)) + (PORT datad (831:831:831) (730:730:730)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~2) + (DELAY + (ABSOLUTE + (PORT datac (1293:1293:1293) (1187:1187:1187)) + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1639:1639:1639)) + (PORT ena (1544:1544:1544) (1395:1395:1395)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (297:297:297)) + (PORT datab (336:336:336) (397:397:397)) + (PORT datac (336:336:336) (422:422:422)) + (PORT datad (821:821:821) (696:696:696)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (1212:1212:1212) (1049:1049:1049)) + (PORT datad (228:228:228) (236:236:236)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|tx) + (DELAY + (ABSOLUTE + (PORT clk (1666:1666:1666) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1698:1698:1698) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_85c_slow.vo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_85c_slow.vo new file mode 100644 index 0000000..74d0a72 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_85c_slow.vo @@ -0,0 +1,24509 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:03:14" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module uart_sd ( + sys_clk, + sys_rst_n, + rx, + sd_miso, + sd_clk, + sd_cs_n, + sd_mosi, + tx); +input sys_clk; +input sys_rst_n; +input rx; +input sd_miso; +output sd_clk; +output sd_cs_n; +output sd_mosi; +output tx; + +// Design Ports Information +// sd_clk => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// sd_cs_n => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default +// sd_mosi => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default +// sd_miso => Location: PIN_E9, I/O Standard: 2.5 V, Current Strength: Default +// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("uart_sd_8_1200mv_85c_v_slow.sdo"); +// synopsys translate_on + +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ; +wire \uart_tx_inst|baud_cnt[2]~17_combout ; +wire \uart_tx_inst|baud_cnt[5]~23_combout ; +wire \uart_tx_inst|baud_cnt[10]~33_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ; +wire \data_rw_ctrl_inst|cnt_wait[5]~27_combout ; +wire \uart_rx_inst|Add1~4_combout ; +wire \uart_rx_inst|baud_cnt[4]~21_combout ; +wire \uart_rx_inst|baud_cnt[10]~33_combout ; +wire \data_rw_ctrl_inst|send_data_num[3]~18_combout ; +wire \data_rw_ctrl_inst|send_data_num[6]~24_combout ; +wire \data_rw_ctrl_inst|send_data_num[7]~27 ; +wire \data_rw_ctrl_inst|send_data_num[8]~29 ; +wire \data_rw_ctrl_inst|send_data_num[8]~28_combout ; +wire \data_rw_ctrl_inst|send_data_num[9]~31 ; +wire \data_rw_ctrl_inst|send_data_num[9]~30_combout ; +wire \data_rw_ctrl_inst|send_data_num[10]~33 ; +wire \data_rw_ctrl_inst|send_data_num[10]~32_combout ; +wire \data_rw_ctrl_inst|send_data_num[11]~34_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ; +wire \sd_ctrl_inst|sd_init_inst|Equal6~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux0~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~4_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~5_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~6_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~7_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~6_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~7_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~3_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~4_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~5_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~6_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~7_combout ; +wire \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~8_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~9_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~10_combout ; +wire \uart_tx_inst|always0~0_combout ; +wire \uart_tx_inst|Mux0~1_combout ; +wire \uart_tx_inst|Mux0~2_combout ; +wire \uart_tx_inst|Mux0~3_combout ; +wire \uart_tx_inst|Mux0~4_combout ; +wire \uart_tx_inst|Mux0~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal1~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector8~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector0~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal3~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal3~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal3~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal3~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ; +wire \sd_ctrl_inst|sd_write_inst|Selector2~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Add3~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ; +wire \uart_tx_inst|work_en~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ; +wire \uart_tx_inst|Add1~1_combout ; +wire \uart_tx_inst|bit_cnt[2]~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector3~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector3~1_combout ; +wire \data_rw_ctrl_inst|tx_flag~q ; +wire \uart_tx_inst|work_en~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~6_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~7_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~1_combout ; +wire \uart_rx_inst|always8~0_combout ; +wire \uart_rx_inst|rx_reg3~q ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ; +wire \uart_rx_inst|Equal2~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ; +wire \uart_rx_inst|rx_reg2~q ; +wire \data_rw_ctrl_inst|always3~2_combout ; +wire \uart_rx_inst|Equal1~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ; +wire \uart_rx_inst|rx_reg1~q ; +wire \uart_rx_inst|start_nedge~q ; +wire \uart_rx_inst|always3~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ; +wire \uart_rx_inst|rx_data[7]~0_combout ; +wire \uart_rx_inst|rx_reg1~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ; +wire \rx~input_o ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|tx_flag~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ; +wire \uart_rx_inst|po_data[1]~feeder_combout ; +wire \uart_rx_inst|rx_data[0]~feeder_combout ; +wire \uart_rx_inst|po_data[5]~feeder_combout ; +wire \uart_rx_inst|rx_data[4]~feeder_combout ; +wire \uart_rx_inst|po_data[6]~feeder_combout ; +wire \uart_rx_inst|rx_data[5]~feeder_combout ; +wire \uart_rx_inst|po_data[7]~feeder_combout ; +wire \uart_rx_inst|rx_data[6]~feeder_combout ; +wire \uart_rx_inst|po_data[3]~feeder_combout ; +wire \uart_rx_inst|rx_data[2]~feeder_combout ; +wire \uart_rx_inst|po_data[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ; +wire \uart_rx_inst|rx_reg2~feeder_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ; +wire \sd_miso~input_o ; +wire \sd_ctrl_inst|sd_init_inst|miso_dly~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal0~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal0~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal3~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_en~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_en~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_en~q ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal1~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal2~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal2~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector0~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal0~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal0~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal0~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.IDLE~q ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~q ; +wire \sd_ctrl_inst|sd_init_inst|WideOr18~combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal5~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal5~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal5~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector2~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector1~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector1~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector5~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector4~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector7~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector3~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector3~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector15~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector15~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector15~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|init_end~q ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal2~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal2~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector3~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ; +wire \sd_ctrl_inst|sd_read_inst|Selector2~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector2~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Add3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal9~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~11_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~9_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~13_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~15_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~q ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector4~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.RD_END~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector0~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector0~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.IDLE~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal1~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal1~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~q ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal4~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal4~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal4~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector2~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Add3~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Add3~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector4~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~7_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~6_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~5_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal6~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~4_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal6~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal6~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector5~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.WR_END~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector0~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cs_n~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cs_n~q ; +wire \sd_ctrl_inst|sd_write_inst|Selector0~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.IDLE~q ; +wire \data_rw_ctrl_inst|wr_busy_dly~feeder_combout ; +wire \data_rw_ctrl_inst|wr_busy_dly~q ; +wire \data_rw_ctrl_inst|wr_busy_fall~0_combout ; +wire \data_rw_ctrl_inst|rd_en~q ; +wire \sd_ctrl_inst|sd_read_inst|cs_n~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|cs_n~q ; +wire \sd_ctrl_inst|sd_cs_n~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal6~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal6~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~3_combout ; +wire \sd_ctrl_inst|sd_init_inst|cs_n~q ; +wire \sd_ctrl_inst|sd_cs_n~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~11_combout ; +wire \sd_ctrl_inst|sd_init_inst|mosi~q ; +wire \sd_ctrl_inst|sd_read_inst|mosi~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|mosi~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|mosi~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|mosi~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ; +wire \uart_rx_inst|Add1~1 ; +wire \uart_rx_inst|Add1~3 ; +wire \uart_rx_inst|Add1~5 ; +wire \uart_rx_inst|Add1~6_combout ; +wire \uart_rx_inst|bit_cnt~0_combout ; +wire \uart_rx_inst|Add1~0_combout ; +wire \uart_rx_inst|bit_cnt~1_combout ; +wire \uart_rx_inst|Add1~2_combout ; +wire \uart_rx_inst|always4~0_combout ; +wire \uart_rx_inst|baud_cnt[0]~13_combout ; +wire \uart_rx_inst|Equal1~0_combout ; +wire \uart_rx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|baud_cnt[2]~17_combout ; +wire \uart_rx_inst|Equal1~1_combout ; +wire \uart_rx_inst|Equal1~3_combout ; +wire \uart_rx_inst|work_en~0_combout ; +wire \uart_rx_inst|work_en~q ; +wire \uart_rx_inst|always5~0_combout ; +wire \uart_rx_inst|baud_cnt[0]~14 ; +wire \uart_rx_inst|baud_cnt[1]~15_combout ; +wire \uart_rx_inst|baud_cnt[1]~16 ; +wire \uart_rx_inst|baud_cnt[2]~18 ; +wire \uart_rx_inst|baud_cnt[3]~19_combout ; +wire \uart_rx_inst|baud_cnt[3]~20 ; +wire \uart_rx_inst|baud_cnt[4]~22 ; +wire \uart_rx_inst|baud_cnt[5]~24 ; +wire \uart_rx_inst|baud_cnt[6]~25_combout ; +wire \uart_rx_inst|baud_cnt[6]~26 ; +wire \uart_rx_inst|baud_cnt[7]~27_combout ; +wire \uart_rx_inst|baud_cnt[7]~28 ; +wire \uart_rx_inst|baud_cnt[8]~29_combout ; +wire \uart_rx_inst|baud_cnt[8]~30 ; +wire \uart_rx_inst|baud_cnt[9]~31_combout ; +wire \uart_rx_inst|baud_cnt[9]~32 ; +wire \uart_rx_inst|baud_cnt[10]~34 ; +wire \uart_rx_inst|baud_cnt[11]~35_combout ; +wire \uart_rx_inst|baud_cnt[11]~36 ; +wire \uart_rx_inst|baud_cnt[12]~37_combout ; +wire \uart_rx_inst|Equal2~1_combout ; +wire \uart_rx_inst|Equal2~2_combout ; +wire \uart_rx_inst|bit_flag~q ; +wire \uart_rx_inst|always4~1_combout ; +wire \uart_rx_inst|rx_flag~q ; +wire \uart_rx_inst|po_flag~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ; +wire \sd_ctrl_inst|comb~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ; +wire \sd_ctrl_inst|comb~0_combout ; +wire \sd_ctrl_inst|comb~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector1~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector1~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux0~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal3~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~4_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~5_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~q ; +wire \sd_ctrl_inst|sd_mosi~0_combout ; +wire \sd_ctrl_inst|sd_mosi~1_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \uart_tx_inst|baud_cnt[0]~13_combout ; +wire \uart_tx_inst|Equal1~0_combout ; +wire \uart_tx_inst|Equal1~1_combout ; +wire \uart_tx_inst|baud_cnt[4]~21_combout ; +wire \uart_tx_inst|Equal1~2_combout ; +wire \uart_tx_inst|Equal1~3_combout ; +wire \uart_tx_inst|always1~0_combout ; +wire \uart_tx_inst|baud_cnt[0]~14 ; +wire \uart_tx_inst|baud_cnt[1]~15_combout ; +wire \uart_tx_inst|baud_cnt[1]~16 ; +wire \uart_tx_inst|baud_cnt[2]~18 ; +wire \uart_tx_inst|baud_cnt[3]~19_combout ; +wire \uart_tx_inst|baud_cnt[3]~20 ; +wire \uart_tx_inst|baud_cnt[4]~22 ; +wire \uart_tx_inst|baud_cnt[5]~24 ; +wire \uart_tx_inst|baud_cnt[6]~25_combout ; +wire \uart_tx_inst|baud_cnt[6]~26 ; +wire \uart_tx_inst|baud_cnt[7]~27_combout ; +wire \uart_tx_inst|baud_cnt[7]~28 ; +wire \uart_tx_inst|baud_cnt[8]~29_combout ; +wire \uart_tx_inst|baud_cnt[8]~30 ; +wire \uart_tx_inst|baud_cnt[9]~31_combout ; +wire \uart_tx_inst|baud_cnt[9]~32 ; +wire \uart_tx_inst|baud_cnt[10]~34 ; +wire \uart_tx_inst|baud_cnt[11]~35_combout ; +wire \uart_tx_inst|baud_cnt[11]~36 ; +wire \uart_tx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal2~0_combout ; +wire \uart_tx_inst|Equal2~1_combout ; +wire \uart_tx_inst|bit_flag~q ; +wire \uart_tx_inst|always3~0_combout ; +wire \uart_tx_inst|always0~1_combout ; +wire \uart_tx_inst|bit_cnt[0]~5_combout ; +wire \uart_tx_inst|bit_cnt[1]~4_combout ; +wire \uart_tx_inst|Add1~0_combout ; +wire \uart_tx_inst|bit_cnt[3]~2_combout ; +wire \data_rw_ctrl_inst|cnt_wait[0]~16_combout ; +wire \data_rw_ctrl_inst|cnt_wait[3]~23 ; +wire \data_rw_ctrl_inst|cnt_wait[4]~24_combout ; +wire \data_rw_ctrl_inst|Equal3~0_combout ; +wire \data_rw_ctrl_inst|rd_busy_dly~q ; +wire \data_rw_ctrl_inst|send_data_num[0]~12_combout ; +wire \data_rw_ctrl_inst|send_data_num[0]~13 ; +wire \data_rw_ctrl_inst|send_data_num[1]~14_combout ; +wire \data_rw_ctrl_inst|send_data_num[1]~15 ; +wire \data_rw_ctrl_inst|send_data_num[2]~16_combout ; +wire \data_rw_ctrl_inst|always3~0_combout ; +wire \data_rw_ctrl_inst|send_data_num[2]~17 ; +wire \data_rw_ctrl_inst|send_data_num[3]~19 ; +wire \data_rw_ctrl_inst|send_data_num[4]~20_combout ; +wire \data_rw_ctrl_inst|send_data_num[4]~21 ; +wire \data_rw_ctrl_inst|send_data_num[5]~23 ; +wire \data_rw_ctrl_inst|send_data_num[6]~25 ; +wire \data_rw_ctrl_inst|send_data_num[7]~26_combout ; +wire \data_rw_ctrl_inst|send_data_num[5]~22_combout ; +wire \data_rw_ctrl_inst|always3~1_combout ; +wire \data_rw_ctrl_inst|always3~3_combout ; +wire \data_rw_ctrl_inst|send_data_en~0_combout ; +wire \data_rw_ctrl_inst|send_data_en~q ; +wire \data_rw_ctrl_inst|Equal3~1_combout ; +wire \data_rw_ctrl_inst|cnt_wait[13]~26_combout ; +wire \data_rw_ctrl_inst|cnt_wait[0]~17 ; +wire \data_rw_ctrl_inst|cnt_wait[1]~18_combout ; +wire \data_rw_ctrl_inst|cnt_wait[1]~19 ; +wire \data_rw_ctrl_inst|cnt_wait[2]~20_combout ; +wire \data_rw_ctrl_inst|cnt_wait[2]~21 ; +wire \data_rw_ctrl_inst|cnt_wait[3]~22_combout ; +wire \data_rw_ctrl_inst|Equal2~3_combout ; +wire \data_rw_ctrl_inst|cnt_wait[4]~25 ; +wire \data_rw_ctrl_inst|cnt_wait[5]~28 ; +wire \data_rw_ctrl_inst|cnt_wait[6]~30 ; +wire \data_rw_ctrl_inst|cnt_wait[7]~31_combout ; +wire \data_rw_ctrl_inst|cnt_wait[7]~32 ; +wire \data_rw_ctrl_inst|cnt_wait[8]~33_combout ; +wire \data_rw_ctrl_inst|cnt_wait[8]~34 ; +wire \data_rw_ctrl_inst|cnt_wait[9]~35_combout ; +wire \data_rw_ctrl_inst|cnt_wait[9]~36 ; +wire \data_rw_ctrl_inst|cnt_wait[10]~37_combout ; +wire \data_rw_ctrl_inst|cnt_wait[10]~38 ; +wire \data_rw_ctrl_inst|cnt_wait[11]~40 ; +wire \data_rw_ctrl_inst|cnt_wait[12]~41_combout ; +wire \data_rw_ctrl_inst|cnt_wait[12]~42 ; +wire \data_rw_ctrl_inst|cnt_wait[13]~44 ; +wire \data_rw_ctrl_inst|cnt_wait[14]~45_combout ; +wire \data_rw_ctrl_inst|cnt_wait[14]~46 ; +wire \data_rw_ctrl_inst|cnt_wait[15]~47_combout ; +wire \data_rw_ctrl_inst|cnt_wait[6]~29_combout ; +wire \data_rw_ctrl_inst|Equal2~0_combout ; +wire \data_rw_ctrl_inst|cnt_wait[13]~43_combout ; +wire \data_rw_ctrl_inst|cnt_wait[11]~39_combout ; +wire \data_rw_ctrl_inst|Equal2~1_combout ; +wire \data_rw_ctrl_inst|Equal2~2_combout ; +wire \data_rw_ctrl_inst|Equal2~4_combout ; +wire \data_rw_ctrl_inst|rd_fifo_rd_en~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_en~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~13_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~14_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~15_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~11_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~7_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~9_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~16_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~6_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~2_combout ; +wire \uart_tx_inst|Mux0~0_combout ; +wire \uart_tx_inst|tx~0_combout ; +wire \uart_tx_inst|tx~q ; +wire [3:0] \sd_ctrl_inst|sd_write_inst|cnt_data_bit ; +wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit ; +wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data_reg ; +wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_ack_bit ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_ack_bit ; +wire [12:0] \uart_tx_inst|baud_cnt ; +wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data ; +wire [2:0] \sd_ctrl_inst|sd_read_inst|cnt_end ; +wire [3:0] \uart_tx_inst|bit_cnt ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|ack_data ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|busy_data ; +wire [3:0] \sd_ctrl_inst|sd_read_inst|cnt_data_bit ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit ; +wire [15:0] \sd_ctrl_inst|sd_read_inst|byte_head ; +wire [11:0] \sd_ctrl_inst|sd_read_inst|cnt_data_num ; +wire [7:0] \sd_ctrl_inst|sd_read_inst|ack_data ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \uart_rx_inst|rx_data ; +wire [7:0] \uart_rx_inst|po_data ; +wire [3:0] \uart_rx_inst|bit_cnt ; +wire [12:0] \uart_rx_inst|baud_cnt ; +wire [11:0] \data_rw_ctrl_inst|send_data_num ; +wire [15:0] \data_rw_ctrl_inst|cnt_wait ; +wire [10:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ; +wire [8:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ; +wire [2:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a ; +wire [15:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ; +wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a ; +wire [2:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a ; +wire [7:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a ; +wire [8:0] \sd_ctrl_inst|sd_init_inst|cnt_wait ; +wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit ; +wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_ack_bit ; +wire [39:0] \sd_ctrl_inst|sd_init_inst|ack_data ; +wire [2:0] \sd_ctrl_inst|sd_write_inst|cnt_end ; +wire [11:0] \sd_ctrl_inst|sd_write_inst|cnt_data_num ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; +wire [17:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; +wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [9]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [10]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [11]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [12]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [13]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [14]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [15]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [16]; + +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 7; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "10000"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 6891; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0] $ (VCC))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # (GND))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .lut_mask = 16'h66DD; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y22_N19 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N13 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N7 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N11 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N13 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y13_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y16_N13 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X13_Y13_N0 +cycloneive_ram_block \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({gnd,\uart_rx_inst|po_data [7],\uart_rx_inst|po_data [6],\uart_rx_inst|po_data [5],\uart_rx_inst|po_data [4],\uart_rx_inst|po_data [3],\uart_rx_inst|po_data [2],\uart_rx_inst|po_data [1],\uart_rx_inst|po_data [0]}), + .portaaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(18'b000000000000000000), + .portbaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_wr_data:fifo_wr_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_uqf1:auto_generated|altsyncram_3011:fifo_ram|ALTSYNCRAM"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 8; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 9; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 18; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 511; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 512; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: M9K_X25_Y27_N0 +cycloneive_ram_block \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({gnd,\sd_ctrl_inst|sd_read_inst|rd_data [15],\sd_ctrl_inst|sd_read_inst|rd_data [14],\sd_ctrl_inst|sd_read_inst|rd_data [13],\sd_ctrl_inst|sd_read_inst|rd_data [12],\sd_ctrl_inst|sd_read_inst|rd_data [11],\sd_ctrl_inst|sd_read_inst|rd_data [10],\sd_ctrl_inst|sd_read_inst|rd_data [9], +\sd_ctrl_inst|sd_read_inst|rd_data [8],gnd,\sd_ctrl_inst|sd_read_inst|rd_data [7],\sd_ctrl_inst|sd_read_inst|rd_data [6],\sd_ctrl_inst|sd_read_inst|rd_data [5],\sd_ctrl_inst|sd_read_inst|rd_data [4],\sd_ctrl_inst|sd_read_inst|rd_data [3],\sd_ctrl_inst|sd_read_inst|rd_data [2], +\sd_ctrl_inst|sd_read_inst|rd_data [1],\sd_ctrl_inst|sd_read_inst|rd_data [0]}), + .portaaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_rd_data:fifo_rd_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_h0f1:auto_generated|altsyncram_4011:fifo_ram|ALTSYNCRAM"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 9; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 18; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 511; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 512; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 8; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: FF_X14_Y25_N11 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N23 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N25 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N27 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N11 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 )) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N25 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y16_N27 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y23_N11 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y23_N7 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h55AA; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N13 +dffeas \uart_tx_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y26_N7 +dffeas \uart_tx_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y26_N23 +dffeas \uart_tx_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout = \sd_ctrl_inst|sd_read_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout = \sd_ctrl_inst|sd_init_inst|cnt_wait [0] $ (VCC) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .lut_mask = 16'h55AA; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N6 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) +// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[1]~16 ), + .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_tx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N12 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[4]~22 ), + .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_tx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N22 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) +// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[9]~32 ), + .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_tx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N11 +dffeas \data_rw_ctrl_inst|cnt_wait[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q $ (GND) +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT = CARRY(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .cout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hAA55; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[5]~27 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[5]~27_combout = (\data_rw_ctrl_inst|cnt_wait [5] & (!\data_rw_ctrl_inst|cnt_wait[4]~25 )) # (!\data_rw_ctrl_inst|cnt_wait [5] & ((\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[5]~28 = CARRY((!\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (!\data_rw_ctrl_inst|cnt_wait [5])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[4]~25 ), + .combout(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[5]~28 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N12 +cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( +// Equation(s): +// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) +// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) + + .dataa(\uart_rx_inst|bit_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~3 ), + .combout(\uart_rx_inst|Add1~4_combout ), + .cout(\uart_rx_inst|Add1~5 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N11 +dffeas \uart_rx_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y16_N23 +dffeas \uart_rx_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N7 +dffeas \data_rw_ctrl_inst|send_data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[3]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N13 +dffeas \data_rw_ctrl_inst|send_data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[6]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N17 +dffeas \data_rw_ctrl_inst|send_data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[8]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N19 +dffeas \data_rw_ctrl_inst|send_data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[9]~30_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N21 +dffeas \data_rw_ctrl_inst|send_data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[10]~32_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[10] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N23 +dffeas \data_rw_ctrl_inst|send_data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[11]~34_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [11]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[11] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N10 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) +// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[3]~20 ), + .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_rx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N22 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) +// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[9]~32 ), + .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_rx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[3]~18 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[3]~18_combout = (\data_rw_ctrl_inst|send_data_num [3] & (!\data_rw_ctrl_inst|send_data_num[2]~17 )) # (!\data_rw_ctrl_inst|send_data_num [3] & ((\data_rw_ctrl_inst|send_data_num[2]~17 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[3]~19 = CARRY((!\data_rw_ctrl_inst|send_data_num[2]~17 ) # (!\data_rw_ctrl_inst|send_data_num [3])) + + .dataa(\data_rw_ctrl_inst|send_data_num [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[2]~17 ), + .combout(\data_rw_ctrl_inst|send_data_num[3]~18_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[3]~19 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[3]~18 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|send_data_num[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[6]~24 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[6]~24_combout = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num[5]~23 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [6] & (!\data_rw_ctrl_inst|send_data_num[5]~23 & VCC)) +// \data_rw_ctrl_inst|send_data_num[6]~25 = CARRY((\data_rw_ctrl_inst|send_data_num [6] & !\data_rw_ctrl_inst|send_data_num[5]~23 )) + + .dataa(\data_rw_ctrl_inst|send_data_num [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[5]~23 ), + .combout(\data_rw_ctrl_inst|send_data_num[6]~24_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[6]~25 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[6]~24 .lut_mask = 16'hA50A; +defparam \data_rw_ctrl_inst|send_data_num[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[7]~26 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[7]~26_combout = (\data_rw_ctrl_inst|send_data_num [7] & (!\data_rw_ctrl_inst|send_data_num[6]~25 )) # (!\data_rw_ctrl_inst|send_data_num [7] & ((\data_rw_ctrl_inst|send_data_num[6]~25 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[7]~27 = CARRY((!\data_rw_ctrl_inst|send_data_num[6]~25 ) # (!\data_rw_ctrl_inst|send_data_num [7])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [7]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[6]~25 ), + .combout(\data_rw_ctrl_inst|send_data_num[7]~26_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[7]~27 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[7]~26 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|send_data_num[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[8]~28 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[8]~28_combout = (\data_rw_ctrl_inst|send_data_num [8] & (\data_rw_ctrl_inst|send_data_num[7]~27 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num[7]~27 & VCC)) +// \data_rw_ctrl_inst|send_data_num[8]~29 = CARRY((\data_rw_ctrl_inst|send_data_num [8] & !\data_rw_ctrl_inst|send_data_num[7]~27 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [8]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[7]~27 ), + .combout(\data_rw_ctrl_inst|send_data_num[8]~28_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[8]~29 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[8]~28 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[9]~30 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[9]~30_combout = (\data_rw_ctrl_inst|send_data_num [9] & (!\data_rw_ctrl_inst|send_data_num[8]~29 )) # (!\data_rw_ctrl_inst|send_data_num [9] & ((\data_rw_ctrl_inst|send_data_num[8]~29 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[9]~31 = CARRY((!\data_rw_ctrl_inst|send_data_num[8]~29 ) # (!\data_rw_ctrl_inst|send_data_num [9])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [9]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[8]~29 ), + .combout(\data_rw_ctrl_inst|send_data_num[9]~30_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[9]~31 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[9]~30 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|send_data_num[9]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[10]~32 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[10]~32_combout = (\data_rw_ctrl_inst|send_data_num [10] & (\data_rw_ctrl_inst|send_data_num[9]~31 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num[9]~31 & VCC)) +// \data_rw_ctrl_inst|send_data_num[10]~33 = CARRY((\data_rw_ctrl_inst|send_data_num [10] & !\data_rw_ctrl_inst|send_data_num[9]~31 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [10]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[9]~31 ), + .combout(\data_rw_ctrl_inst|send_data_num[10]~32_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[10]~33 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[10]~32 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[10]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[11]~34 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[11]~34_combout = \data_rw_ctrl_inst|send_data_num [11] $ (\data_rw_ctrl_inst|send_data_num[10]~33 ) + + .dataa(\data_rw_ctrl_inst|send_data_num [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|send_data_num[10]~33 ), + .combout(\data_rw_ctrl_inst|send_data_num[11]~34_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[11]~34 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|send_data_num[11]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y23_N27 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_end [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~0_combout = (\sd_ctrl_inst|sd_init_inst|init_end~q & \data_rw_ctrl_inst|rd_en~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datad(\data_rw_ctrl_inst|rd_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal6~0_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .lut_mask = 16'h0303; +defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_write_inst|always4~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]), + .datad(\sd_ctrl_inst|sd_write_inst|always4~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~1 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_write_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_write_inst|always4~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~1_combout = (\sd_ctrl_inst|sd_write_inst|mosi~0_combout & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .lut_mask = 16'h0002; +defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux0~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & +// (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .lut_mask = 16'h0026; +defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]) # ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5])))) # +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .lut_mask = 16'hB9A8; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~1_combout = (\sd_ctrl_inst|sd_write_inst|Mux1~0_combout & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]) # ((!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~0_combout & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]), + .datab(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .lut_mask = 16'hB8CC; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~2_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b +// [14]))))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .lut_mask = 16'hEE30; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~3_combout = (\sd_ctrl_inst|sd_write_inst|Mux1~2_combout & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]))) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~2_combout & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .lut_mask = 16'hEA62; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~4_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b +// [15])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .lut_mask = 16'hDC98; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~5_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]))) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~4_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .lut_mask = 16'hF838; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~6_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & +// ((\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|Mux1~5_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .lut_mask = 16'hF2C2; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~7_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] & !\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .lut_mask = 16'hCCB8; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~8_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0])) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~7_combout & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]))))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]), + .datad(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .lut_mask = 16'hBBC0; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~6_combout = (\sd_ctrl_inst|sd_write_inst|Mux1~6_combout & (((\sd_ctrl_inst|sd_write_inst|Mux1~8_combout )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) # (!\sd_ctrl_inst|sd_write_inst|Mux1~6_combout & +// (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|Mux1~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .datac(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .lut_mask = 16'hE6A2; +defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~7_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]) # ((\sd_ctrl_inst|sd_write_inst|mosi~0_combout & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_write_inst|mosi~6_combout )) # +// (!\sd_ctrl_inst|sd_write_inst|mosi~0_combout & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]) # (\sd_ctrl_inst|sd_write_inst|mosi~6_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .datad(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .lut_mask = 16'hFDF4; +defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~1_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .lut_mask = 16'h1906; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~2_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & +// (\sd_ctrl_inst|sd_init_inst|Selector14~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .lut_mask = 16'h5044; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr14~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & +// ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .lut_mask = 16'h9998; +defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~3_combout = ((\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .lut_mask = 16'h0CFF; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~4_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & +// (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .lut_mask = 16'h11E0; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~5_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & !\sd_ctrl_inst|sd_init_inst|Selector14~4_combout )) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|Selector14~4_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .lut_mask = 16'h0108; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~6_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] $ (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .lut_mask = 16'h0902; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~7_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~6_combout & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .lut_mask = 16'h8100; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr12~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .lut_mask = 16'h5F60; +defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~8_combout = ((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]))) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .lut_mask = 16'h10FF; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~9_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~5_combout & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # ((\sd_ctrl_inst|sd_init_inst|Selector14~8_combout )))) # +// (!\sd_ctrl_inst|sd_init_inst|Selector14~5_combout & (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector14~8_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .lut_mask = 16'hA8FC; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~10_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~9_combout & (\sd_ctrl_inst|sd_init_inst|Selector14~3_combout & ((\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ) # +// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .lut_mask = 16'hC400; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N15 +dffeas \uart_tx_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[2]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N10 +cycloneive_lcell_comb \uart_tx_inst|always0~0 ( +// Equation(s): +// \uart_tx_inst|always0~0_combout = (!\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|bit_cnt [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~0 .lut_mask = 16'h000F; +defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N30 +cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( +// Equation(s): +// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b +// [4]))) # (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF2C2; +defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N24 +cycloneive_lcell_comb \uart_tx_inst|Mux0~2 ( +// Equation(s): +// \uart_tx_inst|Mux0~2_combout = (\uart_tx_inst|Mux0~1_combout & (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6])) # (!\uart_tx_inst|bit_cnt [1]))) # (!\uart_tx_inst|Mux0~1_combout & +// (\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]))) + + .dataa(\uart_tx_inst|Mux0~1_combout ), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~2 .lut_mask = 16'hEA62; +defparam \uart_tx_inst|Mux0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N26 +cycloneive_lcell_comb \uart_tx_inst|Mux0~3 ( +// Equation(s): +// \uart_tx_inst|Mux0~3_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\uart_tx_inst|bit_cnt [1] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]))))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~3 .lut_mask = 16'h88C0; +defparam \uart_tx_inst|Mux0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N28 +cycloneive_lcell_comb \uart_tx_inst|Mux0~4 ( +// Equation(s): +// \uart_tx_inst|Mux0~4_combout = (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] & \uart_tx_inst|bit_cnt [1])) + + .dataa(gnd), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~4 .lut_mask = 16'h3000; +defparam \uart_tx_inst|Mux0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N22 +cycloneive_lcell_comb \uart_tx_inst|Mux0~5 ( +// Equation(s): +// \uart_tx_inst|Mux0~5_combout = (\uart_tx_inst|bit_cnt [2] & (((\uart_tx_inst|Mux0~2_combout )))) # (!\uart_tx_inst|bit_cnt [2] & ((\uart_tx_inst|Mux0~3_combout ) # ((\uart_tx_inst|Mux0~4_combout )))) + + .dataa(\uart_tx_inst|Mux0~3_combout ), + .datab(\uart_tx_inst|Mux0~4_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|Mux0~2_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~5 .lut_mask = 16'hFE0E; +defparam \uart_tx_inst|Mux0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q & (\sd_ctrl_inst|sd_read_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0]))))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [2]), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .lut_mask = 16'h7800; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_read_inst|always3~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datad(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~1 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_read_inst|always3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N7 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~2_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [9])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~2 .lut_mask = 16'h0003; +defparam \sd_ctrl_inst|sd_read_inst|always3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .lut_mask = 16'hC33C; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .lut_mask = 16'hC33C; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal1~0_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector8~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector8~0_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [32] & (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout & (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector0~0_combout = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q & (\sd_ctrl_inst|sd_init_inst|Equal5~2_combout & ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q & +// ((\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout & \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .lut_mask = 16'hDC50; +defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal3~0_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [10] & (!\sd_ctrl_inst|sd_init_inst|ack_data [9] & (!\sd_ctrl_inst|sd_init_inst|ack_data [11] & \sd_ctrl_inst|sd_init_inst|ack_data [8]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [10]), + .datab(\sd_ctrl_inst|sd_init_inst|ack_data [9]), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [11]), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .lut_mask = 16'hFC00; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~1_combout = (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & ((\sd_ctrl_inst|sd_init_inst|ack_data [32]) # ((!\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_init_inst|Equal2~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .lut_mask = 16'hB0F0; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # +// (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & ((!\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .lut_mask = 16'hA0EC; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~3_combout = (\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & ((\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector6~1_combout +// )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .lut_mask = 16'hFECC; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~1_combout = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]) # ((!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .lut_mask = 16'hBF00; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal3~1_combout = (!\sd_ctrl_inst|sd_read_inst|ack_data [0] & (!\sd_ctrl_inst|sd_read_inst|ack_data [1] & (!\sd_ctrl_inst|sd_read_inst|ack_data [3] & !\sd_ctrl_inst|sd_read_inst|ack_data [2]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|ack_data [0]), + .datab(\sd_ctrl_inst|sd_read_inst|ack_data [1]), + .datac(\sd_ctrl_inst|sd_read_inst|ack_data [3]), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal3~1_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .lut_mask = 16'h0002; +defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal3~2_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|Equal3~1_combout & \sd_ctrl_inst|sd_write_inst|Equal3~0_combout )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .lut_mask = 16'h8800; +defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N13 +dffeas \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector2~0_combout = (\sd_ctrl_inst|sd_write_inst|Equal1~1_combout & (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout & \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Add3~0_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .lut_mask = 16'h78F0; +defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y14_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEDB7; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y14_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y15_N17 +dffeas \uart_rx_inst|po_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y15_N19 +dffeas \uart_rx_inst|po_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N21 +dffeas \uart_rx_inst|po_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N15 +dffeas \uart_rx_inst|po_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N9 +dffeas \uart_rx_inst|po_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N27 +dffeas \uart_rx_inst|po_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N13 +dffeas \uart_rx_inst|po_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N31 +dffeas \uart_rx_inst|po_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y27_N21 +dffeas \uart_tx_inst|work_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_tx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N6 +cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( +// Equation(s): +// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(gnd), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h3CF0; +defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N14 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~3 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[2]~3_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) + + .dataa(\uart_tx_inst|Add1~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2]~3 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N11 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y25_N31 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y24_N15 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~1_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head [0] & (\sd_ctrl_inst|sd_read_inst|byte_head [2] & (\sd_ctrl_inst|sd_read_inst|byte_head [1] & \sd_ctrl_inst|sd_read_inst|byte_head [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [2]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .lut_mask = 16'h000A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector3~0_combout = (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q & ((!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .lut_mask = 16'h3F00; +defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector3~1_combout = (\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_write_inst|Equal3~2_combout & \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q )) + + .dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .lut_mask = 16'hFFA0; +defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y14_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y14_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y15_N1 +dffeas \uart_rx_inst|rx_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N11 +dffeas \uart_rx_inst|rx_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N29 +dffeas \uart_rx_inst|rx_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N23 +dffeas \uart_rx_inst|rx_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y16_N27 +dffeas \uart_rx_inst|rx_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[7]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N25 +dffeas \uart_rx_inst|rx_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N3 +dffeas \uart_rx_inst|rx_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N5 +dffeas \uart_rx_inst|rx_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y27_N13 +dffeas \data_rw_ctrl_inst|tx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|tx_flag~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|tx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|tx_flag .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|tx_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N20 +cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( +// Equation(s): +// \uart_tx_inst|work_en~0_combout = (\data_rw_ctrl_inst|tx_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) + + .dataa(\data_rw_ctrl_inst|tx_flag~q ), + .datab(gnd), + .datac(\uart_tx_inst|work_en~q ), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hAAFA; +defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y28_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N1 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y27_N27 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y27_N23 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y27_N31 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~4_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [2]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [2]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~5_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [1]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~6_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [0] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~7_combout = (\sd_miso~input_o & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_miso~input_o ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_en~0_combout = (!\sd_miso~input_o & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q & \sd_ctrl_inst|sd_init_inst|miso_dly~q ))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .datac(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_en~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & \sd_ctrl_inst|sd_write_inst|ack_en~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N13 +dffeas \uart_rx_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N20 +cycloneive_lcell_comb \uart_rx_inst|always8~0 ( +// Equation(s): +// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always8~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8282; +defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N31 +dffeas \uart_rx_inst|rx_reg3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg3 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & !\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y16_N8 +cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( +// Equation(s): +// \uart_rx_inst|Equal2~0_combout = (!\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt [2] & \uart_rx_inst|baud_cnt [3]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0400; +defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y10_N1 +dffeas \uart_rx_inst|rx_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~2 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~2_combout = (\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num [11] & !\data_rw_ctrl_inst|send_data_num [9]))) + + .dataa(\data_rw_ctrl_inst|send_data_num [8]), + .datab(\data_rw_ctrl_inst|send_data_num [10]), + .datac(\data_rw_ctrl_inst|send_data_num [11]), + .datad(\data_rw_ctrl_inst|send_data_num [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~2 .lut_mask = 16'h0002; +defparam \data_rw_ctrl_inst|always3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N30 +cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( +// Equation(s): +// \uart_rx_inst|Equal1~2_combout = (\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [9]))) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [6]), + .datad(\uart_rx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y10_N3 +dffeas \uart_rx_inst|rx_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y16_N7 +dffeas \uart_rx_inst|start_nedge ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|start_nedge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; +defparam \uart_rx_inst|start_nedge .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N6 +cycloneive_lcell_comb \uart_rx_inst|always3~0 ( +// Equation(s): +// \uart_rx_inst|always3~0_combout = (!\uart_rx_inst|rx_reg3~q & \uart_rx_inst|rx_reg2~q ) + + .dataa(\uart_rx_inst|rx_reg3~q ), + .datab(gnd), + .datac(\uart_rx_inst|rx_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always3~0 .lut_mask = 16'h5050; +defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h0F0F; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N26 +cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( +// Equation(s): +// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|rx_reg3~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h0F0F; +defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y10_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( +// Equation(s): +// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rx~input_o ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \rx~input ( + .i(rx), + .ibar(gnd), + .o(\rx~input_o )); +// synopsys translate_off +defparam \rx~input .bus_hold = "false"; +defparam \rx~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y14_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|tx_flag~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|tx_flag~feeder_combout = \data_rw_ctrl_inst|rd_fifo_rd_en~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|tx_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|tx_flag~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|tx_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y14_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N16 +cycloneive_lcell_comb \uart_rx_inst|po_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[1]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N18 +cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N4 +cycloneive_lcell_comb \uart_rx_inst|rx_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[4]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N20 +cycloneive_lcell_comb \uart_rx_inst|po_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[6]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N10 +cycloneive_lcell_comb \uart_rx_inst|rx_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[5]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N8 +cycloneive_lcell_comb \uart_rx_inst|po_data[7]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[7]~feeder_combout = \uart_rx_inst|rx_data [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [7]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N28 +cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[6]~feeder_combout = \uart_rx_inst|rx_data [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [7]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N26 +cycloneive_lcell_comb \uart_rx_inst|po_data[3]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[3]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N22 +cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N12 +cycloneive_lcell_comb \uart_rx_inst|po_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[0]~feeder_combout = \uart_rx_inst|rx_data [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [0]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y10_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg1~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N23 +cycloneive_io_obuf \sd_clk~output ( + .i(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sd_clk), + .obar()); +// synopsys translate_off +defparam \sd_clk~output .bus_hold = "false"; +defparam \sd_clk~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N23 +cycloneive_io_obuf \sd_cs_n~output ( + .i(\sd_ctrl_inst|sd_cs_n~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sd_cs_n), + .obar()); +// synopsys translate_off +defparam \sd_cs_n~output .bus_hold = "false"; +defparam \sd_cs_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y29_N9 +cycloneive_io_obuf \sd_mosi~output ( + .i(\sd_ctrl_inst|sd_mosi~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sd_mosi), + .obar()); +// synopsys translate_off +defparam \sd_mosi~output .bus_hold = "false"; +defparam \sd_mosi~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y9_N16 +cycloneive_io_obuf \tx~output ( + .i(!\uart_tx_inst|tx~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tx), + .obar()); +// synopsys translate_off +defparam \tx~output .bus_hold = "false"; +defparam \tx~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout = \sd_ctrl_inst|sd_read_inst|cnt_data_num [0] $ (VCC) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y1_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y1_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y1_N26 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ) # (!\sys_rst_n~input_o )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\sys_rst_n~input_o ), + .datac(gnd), + .datad(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h77FF; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N29 +cycloneive_io_ibuf \sd_miso~input ( + .i(sd_miso), + .ibar(gnd), + .o(\sd_miso~input_o )); +// synopsys translate_off +defparam \sd_miso~input .bus_hold = "false"; +defparam \sd_miso~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X16_Y24_N25 +dffeas \sd_ctrl_inst|sd_init_inst|miso_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_miso~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|miso_dly .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|miso_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_en~0_combout = (!\sd_miso~input_o & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q & (\sd_ctrl_inst|sd_init_inst|miso_dly~q & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .lut_mask = 16'h0040; +defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N13 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_en~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|ack_en~0_combout & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .datab(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .lut_mask = 16'h0004; +defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N11 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal0~1_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_en~2_combout = (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout & (!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout & ((\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_read_inst|ack_en~q )))) # +// (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout & (((\sd_ctrl_inst|sd_read_inst|ack_en~q )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .lut_mask = 16'h50F8; +defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N3 +dffeas \sd_ctrl_inst|sd_read_inst|ack_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y24_N9 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N15 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N17 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N21 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N23 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal0~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout & \sd_ctrl_inst|sd_read_inst|ack_en~q )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .lut_mask = 16'h5000; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N23 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N29 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout = \sd_ctrl_inst|sd_read_inst|ack_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N19 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N25 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout = \sd_ctrl_inst|sd_read_inst|ack_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N31 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N21 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout = \sd_ctrl_inst|sd_read_inst|ack_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N27 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N17 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal3~0_combout = (!\sd_ctrl_inst|sd_read_inst|ack_data [6] & (!\sd_ctrl_inst|sd_read_inst|ack_data [5] & (!\sd_ctrl_inst|sd_read_inst|ack_data [7] & !\sd_ctrl_inst|sd_read_inst|ack_data [4]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|ack_data [6]), + .datab(\sd_ctrl_inst|sd_read_inst|ack_data [5]), + .datac(\sd_ctrl_inst|sd_read_inst|ack_data [7]), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal3~2_combout = (\sd_ctrl_inst|sd_read_inst|Equal3~1_combout & \sd_ctrl_inst|sd_read_inst|Equal3~0_combout ) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N9 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_en~0_combout = (!\sd_miso~input_o & (\sd_ctrl_inst|sd_init_inst|miso_dly~q & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .lut_mask = 16'h0004; +defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_en~1_combout = (!\sd_ctrl_inst|sd_init_inst|Equal6~2_combout & ((\sd_ctrl_inst|sd_init_inst|ack_en~q ) # ((\sd_ctrl_inst|sd_init_inst|ack_en~0_combout & \sd_ctrl_inst|sd_init_inst|Equal1~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .lut_mask = 16'h5450; +defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N3 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal1~1_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~0_combout & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3])) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .lut_mask = 16'h000A; +defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal1~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~1_combout & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout = (\sd_ctrl_inst|sd_init_inst|ack_en~q & (((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .lut_mask = 16'h04CC; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 )) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout = (\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .lut_mask = 16'h000C; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N21 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N19 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N23 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N3 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N31 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N27 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N15 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N5 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N1 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N25 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N13 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N7 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [10]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [11] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [11]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N11 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [12] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [12]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N29 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [13] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [14] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [14]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N9 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [15] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [15]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[16] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [16]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[17] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [16]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [17]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [17] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [17]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N19 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[18] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [18]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [18] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [18]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N25 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[19] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [19]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [19] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [19]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N23 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[20] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [20]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[21] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [20]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [21]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[22] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [21]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [22]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [22] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [22]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[23] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [23]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [23] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [23]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[24] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [24]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [24] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [24]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N29 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[25] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [25]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [25] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [25]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N27 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[26] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [26]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N9 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[27] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [26]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [27]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N31 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[28] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [27]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [28]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N21 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[29] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [28]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [29]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [29] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [29]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N3 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[30] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [30]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [30] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [30]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[31] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [31]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[32] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [31]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [32] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N29 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[33] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [33]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [33] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N25 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[34] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [34]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[35] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [34]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [35]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal2~1_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [34] & (!\sd_ctrl_inst|sd_init_inst|ack_data [35] & !\sd_ctrl_inst|sd_init_inst|ack_data [33])) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [34]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [35]), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .lut_mask = 16'h0005; +defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[36] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [35]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [36]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [36] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [36]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N3 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[37] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [37]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [37] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[38] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [38]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N21 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[39] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [38]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [39]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal2~0_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [36] & (!\sd_ctrl_inst|sd_init_inst|ack_data [38] & (!\sd_ctrl_inst|sd_init_inst|ack_data [39] & !\sd_ctrl_inst|sd_init_inst|ack_data [37]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [36]), + .datab(\sd_ctrl_inst|sd_init_inst|ack_data [38]), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [39]), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal2~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout & (\sd_ctrl_inst|sd_init_inst|ack_data [32] & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector0~1_combout = (\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .lut_mask = 16'hAAEA; +defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N19 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N21 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 )) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N25 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout = \sd_ctrl_inst|sd_init_inst|cnt_wait [8] $ (!\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .lut_mask = 16'hA5A5; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N27 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N23 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal0~1_combout = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [5]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .lut_mask = 16'h7FFF; +defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal0~2_combout = (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout & (\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .lut_mask = 16'h0030; +defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N17 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N13 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal0~0_combout = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [1]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [0]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .lut_mask = 16'h7FFF; +defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.IDLE~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q ) # ((\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .lut_mask = 16'hF0F2; +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N9 +dffeas \sd_ctrl_inst|sd_init_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|Selector8~0_combout & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .lut_mask = 16'hFAF0; +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N27 +dffeas \sd_ctrl_inst|sd_init_inst|state.INIT_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr18 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|WideOr18~combout = (\sd_ctrl_inst|sd_init_inst|Selector14~0_combout & !\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .lut_mask = 16'h0C0C; +defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N21 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N23 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal5~1_combout = ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .lut_mask = 16'hFDFF; +defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout = ((!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout & !\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .lut_mask = 16'h333F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N9 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal5~0_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .lut_mask = 16'hFFFE; +defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal5~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .lut_mask = 16'hFFF0; +defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector2~0_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & +// ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .lut_mask = 16'h50DC; +defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N27 +dffeas \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector1~0_combout = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & (((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & +// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .lut_mask = 16'hF444; +defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector1~1_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & ((\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # +// (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .lut_mask = 16'hF888; +defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N19 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector5~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector5~0_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & +// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .lut_mask = 16'h50DC; +defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector4~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # +// (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .lut_mask = 16'h22F2; +defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector7~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector7~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # +// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .lut_mask = 16'h22F2; +defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N25 +dffeas \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~0_combout = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q & (!\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector3~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .lut_mask = 16'hFC00; +defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector3~1_combout = (\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal2~2_combout & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .lut_mask = 16'hECCC; +defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector15~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ) # (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .lut_mask = 16'hFFFE; +defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector15~1_combout = (!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout & (!\sd_ctrl_inst|sd_init_inst|Equal5~1_combout & \sd_ctrl_inst|sd_init_inst|Selector15~0_combout )) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .lut_mask = 16'h1010; +defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector15~2_combout = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q & ((\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ) # (!\sd_ctrl_inst|sd_init_inst|Selector14~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .lut_mask = 16'hFABA; +defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|init_end ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|init_end .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|init_end .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~2_combout = (\data_rw_ctrl_inst|rd_en~q & (\sd_ctrl_inst|sd_init_inst|init_end~q & !\sd_ctrl_inst|sd_read_inst|state.IDLE~q )) + + .dataa(\data_rw_ctrl_inst|rd_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .lut_mask = 16'h00A0; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~3_combout = (\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ) # ((\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ) # ((!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout & \sd_ctrl_inst|sd_read_inst|Selector2~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .lut_mask = 16'hFBFA; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N17 +dffeas \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N5 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N9 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N15 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N17 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal2~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .lut_mask = 16'h0040; +defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N7 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal2~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .lut_mask = 16'hA000; +defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector3~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|Equal2~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal2~0_combout & \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector3~1_combout = (\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q & ((!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .lut_mask = 16'hDCFC; +defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N9 +dffeas \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector2~0_combout = (\sd_ctrl_inst|sd_read_inst|Equal0~1_combout & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q & \sd_ctrl_inst|sd_read_inst|Equal0~0_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .lut_mask = 16'h8080; +defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector2~1_combout = (\sd_ctrl_inst|sd_read_inst|Equal3~2_combout & ((\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ) # ((!\sd_ctrl_inst|sd_read_inst|always3~4_combout & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # +// (!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout & (!\sd_ctrl_inst|sd_read_inst|always3~4_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .lut_mask = 16'hBA30; +defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N29 +dffeas \sd_ctrl_inst|sd_read_inst|state.RD_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N13 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N7 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout = (\sd_ctrl_inst|sd_read_inst|always3~2_combout & (\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout & (\sd_ctrl_inst|sd_read_inst|always3~0_combout & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .lut_mask = 16'h0080; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .lut_mask = 16'h0048; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Add3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Add3~0_combout = \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .lut_mask = 16'h5FA0; +defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (\sd_ctrl_inst|sd_read_inst|Add3~0_combout & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .lut_mask = 16'h00A0; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal9~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal9~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .lut_mask = 16'hA000; +defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~11_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [11]), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N31 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~10_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [12]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [12]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N29 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~9_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [13]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N27 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~8_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [14]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N17 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~2_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [12] & (\sd_ctrl_inst|sd_read_inst|byte_head [13] & (\sd_ctrl_inst|sd_read_inst|byte_head [14] & \sd_ctrl_inst|sd_read_inst|byte_head [15]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [12]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [13]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [15]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~14_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [8] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [8]), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N23 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~13_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [9]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [9]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~12_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [10]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [10]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N11 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~15_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [7]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [7]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N3 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~3_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [9] & (\sd_ctrl_inst|sd_read_inst|byte_head [10] & (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head [8]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [9]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [10]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [11]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~4_combout = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout = (!\sd_ctrl_inst|sd_read_inst|Equal6~4_combout & ((\sd_ctrl_inst|sd_read_inst|byte_head_en~q ) # ((\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout & \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout +// )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .lut_mask = 16'h00F8; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N15 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~1_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [5] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [5]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .lut_mask = 16'h8888; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N27 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~0_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [6]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N9 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~3_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [3] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [3]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .lut_mask = 16'h8888; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N23 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~2_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [4]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [4]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N13 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~0_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [4] & (\sd_ctrl_inst|sd_read_inst|byte_head [7] & (\sd_ctrl_inst|sd_read_inst|byte_head [6] & \sd_ctrl_inst|sd_read_inst|byte_head [5]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [4]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [7]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3])))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .lut_mask = 16'h0028; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N1 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ) # ((\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))) # +// (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .lut_mask = 16'hFDF5; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N9 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N15 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N17 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N21 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~3_combout = (\sd_ctrl_inst|sd_read_inst|always3~2_combout & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~3 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|always3~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~4_combout = (\sd_ctrl_inst|sd_read_inst|always3~1_combout & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_read_inst|always3~3_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|always3~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~4 .lut_mask = 16'h8800; +defparam \sd_ctrl_inst|sd_read_inst|always3~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector4~0_combout = (\sd_ctrl_inst|sd_read_inst|Selector0~0_combout & (\sd_ctrl_inst|sd_read_inst|always3~4_combout & ((\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout & +// ((\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # ((\sd_ctrl_inst|sd_read_inst|always3~4_combout & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .lut_mask = 16'hDC50; +defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N23 +dffeas \sd_ctrl_inst|sd_read_inst|state.RD_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_end [0] & \sd_ctrl_inst|sd_read_inst|state.RD_END~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N21 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q & (\sd_ctrl_inst|sd_read_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_end [1]))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .lut_mask = 16'h3C00; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N31 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector0~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_end [2] & (\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [2]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .lut_mask = 16'hA000; +defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector0~1_combout = (\sd_ctrl_inst|sd_read_inst|Selector1~0_combout & (((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q )) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|sd_read_inst|Selector1~0_combout +// & (\sd_ctrl_inst|sd_read_inst|state.IDLE~q & ((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .lut_mask = 16'h32FA; +defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N3 +dffeas \sd_ctrl_inst|sd_read_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_num [0] $ (VCC) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout = \sd_ctrl_inst|sd_init_inst|miso_dly~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y23_N1 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N3 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N5 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N9 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y23_N13 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal1~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal1~1_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_en~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout & (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout & ((\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_write_inst|ack_en~q )))) # +// (!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout & (((\sd_ctrl_inst|sd_write_inst|ack_en~q )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .lut_mask = 16'h30F8; +defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y23_N29 +dffeas \sd_ctrl_inst|sd_write_inst|ack_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|ack_en~q & \sd_ctrl_inst|sd_write_inst|Equal1~0_combout )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .lut_mask = 16'h4400; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N23 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N29 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout = \sd_ctrl_inst|sd_write_inst|ack_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N19 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N25 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal4~1_combout = (!\sd_ctrl_inst|sd_write_inst|ack_data [0] & (!\sd_ctrl_inst|sd_write_inst|ack_data [1] & (!\sd_ctrl_inst|sd_write_inst|ack_data [3] & !\sd_ctrl_inst|sd_write_inst|ack_data [2]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|ack_data [0]), + .datab(\sd_ctrl_inst|sd_write_inst|ack_data [1]), + .datac(\sd_ctrl_inst|sd_write_inst|ack_data [3]), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout = \sd_ctrl_inst|sd_write_inst|ack_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N31 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N21 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout = \sd_ctrl_inst|sd_write_inst|ack_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N27 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N1 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal4~0_combout = (!\sd_ctrl_inst|sd_write_inst|ack_data [6] & (!\sd_ctrl_inst|sd_write_inst|ack_data [5] & (!\sd_ctrl_inst|sd_write_inst|ack_data [7] & !\sd_ctrl_inst|sd_write_inst|ack_data [4]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|ack_data [6]), + .datab(\sd_ctrl_inst|sd_write_inst|ack_data [5]), + .datac(\sd_ctrl_inst|sd_write_inst|ack_data [7]), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal4~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal4~1_combout & \sd_ctrl_inst|sd_write_inst|Equal4~0_combout ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .lut_mask = 16'hCC00; +defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector2~1_combout = (\sd_ctrl_inst|sd_write_inst|Selector2~0_combout & ((\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ) # ((!\sd_ctrl_inst|sd_write_inst|always4~3_combout & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))) +// # (!\sd_ctrl_inst|sd_write_inst|Selector2~0_combout & (!\sd_ctrl_inst|sd_write_inst|always4~3_combout & (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .lut_mask = 16'hBA30; +defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N1 +dffeas \sd_ctrl_inst|sd_write_inst|state.WR_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y13_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Add3~2_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y13_N21 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Add3~1_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .lut_mask = 16'h3CF0; +defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y13_N3 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit +// [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .lut_mask = 16'hFF0F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X10_Y16_N5 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N9 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N19 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N21 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N25 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N27 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N23 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~2 .lut_mask = 16'h0002; +defparam \sd_ctrl_inst|sd_write_inst|always4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~3_combout = (\sd_ctrl_inst|sd_write_inst|always4~1_combout & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~2_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|always4~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_write_inst|always4~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~3 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|always4~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector4~0_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q & ((\sd_ctrl_inst|sd_write_inst|always4~3_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout )))) # +// (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q & (((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .lut_mask = 16'h88F8; +defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N17 +dffeas \sd_ctrl_inst|sd_write_inst|state.WR_BUSY ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~8_combout = (\sd_miso~input_o & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(\sd_miso~input_o ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N27 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~7_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [0]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N9 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~6_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [1] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [1]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N31 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~5_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N13 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal6~1_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & (\sd_ctrl_inst|sd_write_inst|busy_data [1] & (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|busy_data [3]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|busy_data [0]), + .datab(\sd_ctrl_inst|sd_write_inst|busy_data [1]), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]), + .datad(\sd_ctrl_inst|sd_write_inst|busy_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~4_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [3] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(\sd_ctrl_inst|sd_write_inst|busy_data [3]), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N25 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~3_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|busy_data [4]), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .lut_mask = 16'hCC00; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N15 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~2_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [5] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [5]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N5 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~1_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N19 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal6~0_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & (\sd_ctrl_inst|sd_write_inst|busy_data [5] & (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|busy_data [7]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|busy_data [4]), + .datab(\sd_ctrl_inst|sd_write_inst|busy_data [5]), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]), + .datad(\sd_ctrl_inst|sd_write_inst|busy_data [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal6~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal6~1_combout & \sd_ctrl_inst|sd_write_inst|Equal6~0_combout ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .lut_mask = 16'hCC00; +defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector5~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector5~0_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & ((\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_END~q & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) # +// (!\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & (((\sd_ctrl_inst|sd_write_inst|state.WR_END~q & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .datab(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .lut_mask = 16'h88F8; +defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N5 +dffeas \sd_ctrl_inst|sd_write_inst|state.WR_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_end [1]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .lut_mask = 16'h5A00; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|state.WR_END~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N23 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q & (\sd_ctrl_inst|sd_write_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [1]))))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [2]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .lut_mask = 16'h7800; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N29 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_end [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector0~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_end [1] & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [2])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_end [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cs_n~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cs_n~0_combout = (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout & ((\sd_ctrl_inst|comb~2_combout ) # (\sd_ctrl_inst|sd_write_inst|cs_n~q ))) + + .dataa(\sd_ctrl_inst|comb~2_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .lut_mask = 16'h00FA; +defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N3 +dffeas \sd_ctrl_inst|sd_write_inst|cs_n ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cs_n~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cs_n .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cs_n .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector0~1_combout = (\sd_ctrl_inst|comb~2_combout & (((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q )) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|comb~2_combout & +// (\sd_ctrl_inst|sd_write_inst|state.IDLE~q & ((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q ) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) + + .dataa(\sd_ctrl_inst|comb~2_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .lut_mask = 16'h32FA; +defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N9 +dffeas \sd_ctrl_inst|sd_write_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_dly~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|wr_busy_dly~feeder_combout = \sd_ctrl_inst|sd_write_inst|state.IDLE~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N19 +dffeas \data_rw_ctrl_inst|wr_busy_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|wr_busy_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|wr_busy_dly .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|wr_busy_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_fall~0 ( +// Equation(s): +// \data_rw_ctrl_inst|wr_busy_fall~0_combout = (\data_rw_ctrl_inst|wr_busy_dly~q & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|wr_busy_dly~q ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|wr_busy_fall~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|wr_busy_fall~0 .lut_mask = 16'h00CC; +defparam \data_rw_ctrl_inst|wr_busy_fall~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N11 +dffeas \data_rw_ctrl_inst|rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|wr_busy_fall~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|rd_en .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cs_n~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cs_n~2_combout = (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout & ((\sd_ctrl_inst|sd_read_inst|cs_n~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q & \data_rw_ctrl_inst|rd_en~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cs_n~q ), + .datad(\data_rw_ctrl_inst|rd_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .lut_mask = 16'h3230; +defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N25 +dffeas \sd_ctrl_inst|sd_read_inst|cs_n ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cs_n~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cs_n .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cs_n .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_cs_n~0_combout = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_write_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_read_inst|cs_n~q )) # +// (!\sd_ctrl_inst|sd_read_inst|state.IDLE~q ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .datab(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_read_inst|cs_n~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_cs_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_cs_n~0 .lut_mask = 16'h1B5F; +defparam \sd_ctrl_inst|sd_cs_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~1_combout = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q & !\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q )) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .lut_mask = 16'h0101; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal6~1_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~0_combout = ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]) # (\sd_ctrl_inst|sd_init_inst|Equal6~1_combout )))) # (!\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .lut_mask = 16'hDDD5; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal6~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|Equal6~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .lut_mask = 16'h0800; +defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_init_inst|Selector13~0_combout & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal6~2_combout )))) +// # (!\sd_ctrl_inst|sd_init_inst|Equal6~0_combout & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal6~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .lut_mask = 16'hF5C4; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~3_combout = ((\sd_ctrl_inst|sd_init_inst|Selector15~0_combout & ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # (\sd_ctrl_inst|sd_init_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .lut_mask = 16'hA8FF; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cs_n ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cs_n~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cs_n .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cs_n .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_cs_n~1_combout = (\sd_ctrl_inst|sd_init_inst|init_end~q & (\sd_ctrl_inst|sd_cs_n~0_combout )) # (!\sd_ctrl_inst|sd_init_inst|init_end~q & ((!\sd_ctrl_inst|sd_init_inst|cs_n~q ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_cs_n~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_cs_n~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_cs_n~1 .lut_mask = 16'hCC0F; +defparam \sd_ctrl_inst|sd_cs_n~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~11_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~10_combout & (((\sd_ctrl_inst|sd_init_inst|mosi~q & !\sd_ctrl_inst|sd_init_inst|Selector14~0_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Selector14~10_combout & +// ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|mosi~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|mosi~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .lut_mask = 16'h54F4; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|mosi ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|mosi~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|mosi .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|mosi .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|mosi~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] $ (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5])))) # +// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .lut_mask = 16'hEC84; +defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N11 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|mosi~1_combout = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] $ (((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|mosi~0_combout & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3])))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .lut_mask = 16'hF0B4; +defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|mosi~2_combout = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_read_inst|mosi~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ))) # +// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((!\sd_ctrl_inst|sd_read_inst|mosi~1_combout ))))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .lut_mask = 16'hA700; +defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N1 +dffeas \sd_ctrl_inst|sd_read_inst|mosi ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|mosi~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|mosi .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q $ (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT = CARRY(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hCC33; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h0F0F; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N8 +cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( +// Equation(s): +// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] & VCC)) +// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [0])) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|Add1~0_combout ), + .cout(\uart_rx_inst|Add1~1 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; +defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N10 +cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( +// Equation(s): +// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) +// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~1 ), + .combout(\uart_rx_inst|Add1~2_combout ), + .cout(\uart_rx_inst|Add1~3 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N14 +cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( +// Equation(s): +// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|bit_cnt [3] $ (\uart_rx_inst|Add1~5 ) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(gnd), + .datad(gnd), + .cin(\uart_rx_inst|Add1~5 ), + .combout(\uart_rx_inst|Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h3C3C; +defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N4 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~0_combout = (\uart_rx_inst|Add1~6_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q ))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|Add1~6_combout ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h4CCC; +defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N5 +dffeas \uart_rx_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N24 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~1_combout = (\uart_rx_inst|Add1~0_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q ))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(\uart_rx_inst|Add1~0_combout ), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h70F0; +defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N25 +dffeas \uart_rx_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y16_N11 +dffeas \uart_rx_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N18 +cycloneive_lcell_comb \uart_rx_inst|always4~0 ( +// Equation(s): +// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [2]), + .datab(\uart_rx_inst|bit_cnt [0]), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_rx_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0011; +defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N2 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) +// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_rx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N0 +cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( +// Equation(s): +// \uart_rx_inst|Equal1~0_combout = (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [1] & \uart_rx_inst|baud_cnt [0]))) + + .dataa(\uart_rx_inst|baud_cnt [8]), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(\uart_rx_inst|baud_cnt [1]), + .datad(\uart_rx_inst|baud_cnt [0]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h1000; +defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N12 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) + + .dataa(\uart_rx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[4]~22 ), + .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_rx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N13 +dffeas \uart_rx_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N6 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) +// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_rx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[1]~16 ), + .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_rx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N7 +dffeas \uart_rx_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y16_N10 +cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( +// Equation(s): +// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N2 +cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( +// Equation(s): +// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|Equal1~2_combout & (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal1~1_combout ))) + + .dataa(\uart_rx_inst|Equal1~2_combout ), + .datab(\uart_rx_inst|baud_cnt [12]), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h8000; +defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N16 +cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( +// Equation(s): +// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) + + .dataa(\uart_rx_inst|start_nedge~q ), + .datab(gnd), + .datac(\uart_rx_inst|work_en~q ), + .datad(\uart_rx_inst|always4~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hAAFA; +defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N17 +dffeas \uart_rx_inst|work_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_rx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N28 +cycloneive_lcell_comb \uart_rx_inst|always5~0 ( +// Equation(s): +// \uart_rx_inst|always5~0_combout = (\uart_rx_inst|Equal1~3_combout ) # (!\uart_rx_inst|work_en~q ) + + .dataa(gnd), + .datab(\uart_rx_inst|Equal1~3_combout ), + .datac(gnd), + .datad(\uart_rx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_rx_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always5~0 .lut_mask = 16'hCCFF; +defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y16_N3 +dffeas \uart_rx_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N4 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[0]~14 ), + .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_rx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N5 +dffeas \uart_rx_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N8 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[2]~18 ), + .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_rx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N9 +dffeas \uart_rx_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N14 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) +// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[5]~24 ), + .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_rx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N15 +dffeas \uart_rx_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N16 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[6]~26 ), + .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_rx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N17 +dffeas \uart_rx_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N18 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) +// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[7]~28 ), + .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_rx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N19 +dffeas \uart_rx_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N20 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[8]~30 ), + .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_rx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N21 +dffeas \uart_rx_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N24 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[10]~34 ), + .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_rx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N25 +dffeas \uart_rx_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N26 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt [12] $ (!\uart_rx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_rx_inst|baud_cnt[11]~36 ), + .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N27 +dffeas \uart_rx_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N28 +cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( +// Equation(s): +// \uart_rx_inst|Equal2~1_combout = (!\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & \uart_rx_inst|baud_cnt [9]))) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [6]), + .datad(\uart_rx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0400; +defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N22 +cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( +// Equation(s): +// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal2~0_combout & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal2~1_combout ))) + + .dataa(\uart_rx_inst|Equal2~0_combout ), + .datab(\uart_rx_inst|baud_cnt [12]), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal2~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000; +defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N23 +dffeas \uart_rx_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Equal2~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N0 +cycloneive_lcell_comb \uart_rx_inst|always4~1 ( +// Equation(s): +// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|always4~0_combout & (\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [3])) + + .dataa(gnd), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~1 .lut_mask = 16'hC000; +defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N1 +dffeas \uart_rx_inst|rx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always4~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_flag .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N1 +dffeas \uart_rx_inst|po_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_flag~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_flag .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0010; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .lut_mask = 16'h0500; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'hA5F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .lut_mask = 16'hF05A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y12_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X12_Y12_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h6FF6; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|always4~2_combout & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|always4~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'h3020; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hE1F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h0040; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h3CC3; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h3333; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout = (\uart_rx_inst|po_flag~q & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .datab(\uart_rx_inst|po_flag~q ), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hCC88; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout & (\uart_rx_inst|po_flag~q & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .datac(\uart_rx_inst|po_flag~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'hC080; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0100; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q )) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h6969; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'hF00F; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h2000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0200; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0300; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y12_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout )) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X16_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y12_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y12_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .lut_mask = 16'h78F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y12_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )))) # (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .lut_mask = 16'h964D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )))) # (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & +// ((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .lut_mask = 16'h962B; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )))) # (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .lut_mask = 16'h964D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N4 +cycloneive_lcell_comb \sd_ctrl_inst|comb~1 ( +// Equation(s): +// \sd_ctrl_inst|comb~1_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|comb~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|comb~1 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|comb~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N0 +cycloneive_lcell_comb \sd_ctrl_inst|comb~0 ( +// Equation(s): +// \sd_ctrl_inst|comb~0_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout & (\sd_ctrl_inst|sd_init_inst|init_end~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|comb~0 .lut_mask = 16'h0004; +defparam \sd_ctrl_inst|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N2 +cycloneive_lcell_comb \sd_ctrl_inst|comb~2 ( +// Equation(s): +// \sd_ctrl_inst|comb~2_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout & +// (\sd_ctrl_inst|comb~1_combout & \sd_ctrl_inst|comb~0_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ), + .datac(\sd_ctrl_inst|comb~1_combout ), + .datad(\sd_ctrl_inst|comb~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|comb~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|comb~2 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|comb~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector1~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal3~2_combout & (((\sd_ctrl_inst|comb~2_combout & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )))) # (!\sd_ctrl_inst|sd_write_inst|Equal3~2_combout & +// ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # ((\sd_ctrl_inst|comb~2_combout & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datac(\sd_ctrl_inst|comb~2_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .lut_mask = 16'h44F4; +defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector1~3_combout = (\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|Selector2~0_combout & ((!\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal4~1_combout +// )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .lut_mask = 16'hF2FA; +defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N15 +dffeas \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N19 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux0~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))) # +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .lut_mask = 16'h00E8; +defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N21 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y16_N23 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~2_combout = (!\sd_ctrl_inst|sd_write_inst|Mux0~0_combout & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .lut_mask = 16'h0030; +defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal3~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~3_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & +// (\sd_ctrl_inst|sd_write_inst|Mux0~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .lut_mask = 16'h0E02; +defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~4_combout = (\sd_ctrl_inst|sd_write_inst|mosi~1_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q & ((\sd_ctrl_inst|sd_write_inst|mosi~2_combout ) # (\sd_ctrl_inst|sd_write_inst|mosi~3_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datad(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .lut_mask = 16'hFAEA; +defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~5_combout = (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .lut_mask = 16'h3323; +defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~8_combout = (!\sd_ctrl_inst|sd_write_inst|mosi~4_combout & (!\sd_ctrl_inst|sd_write_inst|mosi~5_combout & ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # (!\sd_ctrl_inst|sd_write_inst|mosi~7_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datac(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .lut_mask = 16'h000D; +defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X11_Y16_N17 +dffeas \sd_ctrl_inst|sd_write_inst|mosi ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|mosi~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|mosi .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_mosi~0_combout = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_write_inst|mosi~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q )) # +// (!\sd_ctrl_inst|sd_read_inst|mosi~q ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .datab(\sd_ctrl_inst|sd_read_inst|mosi~q ), + .datac(\sd_ctrl_inst|sd_write_inst|mosi~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_mosi~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_mosi~0 .lut_mask = 16'h1B5F; +defparam \sd_ctrl_inst|sd_mosi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_mosi~1_combout = (\sd_ctrl_inst|sd_init_inst|init_end~q & ((\sd_ctrl_inst|sd_mosi~0_combout ))) # (!\sd_ctrl_inst|sd_init_inst|init_end~q & (!\sd_ctrl_inst|sd_init_inst|mosi~q )) + + .dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|mosi~q ), + .datad(\sd_ctrl_inst|sd_mosi~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_mosi~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_mosi~1 .lut_mask = 16'hAF05; +defparam \sd_ctrl_inst|sd_mosi~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N2 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) +// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_tx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N0 +cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( +// Equation(s): +// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt [3] & \uart_tx_inst|baud_cnt [0]))) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(\uart_tx_inst|baud_cnt [3]), + .datad(\uart_tx_inst|baud_cnt [0]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0100; +defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N2 +cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( +// Equation(s): +// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|Equal1~0_combout & (!\uart_tx_inst|baud_cnt [11] & !\uart_tx_inst|baud_cnt [9]))) + + .dataa(\uart_tx_inst|baud_cnt [8]), + .datab(\uart_tx_inst|Equal1~0_combout ), + .datac(\uart_tx_inst|baud_cnt [11]), + .datad(\uart_tx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0004; +defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N10 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) +// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[3]~20 ), + .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_tx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N11 +dffeas \uart_tx_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N30 +cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( +// Equation(s): +// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4]))) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; +defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N16 +cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( +// Equation(s): +// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [10] & \uart_tx_inst|baud_cnt [12]) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(gnd), + .datac(\uart_tx_inst|baud_cnt [12]), + .datad(gnd), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hA0A0; +defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N26 +cycloneive_lcell_comb \uart_tx_inst|always1~0 ( +// Equation(s): +// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~1_combout & (\uart_tx_inst|Equal1~2_combout & \uart_tx_inst|Equal1~3_combout ))) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|Equal1~1_combout ), + .datac(\uart_tx_inst|Equal1~2_combout ), + .datad(\uart_tx_inst|Equal1~3_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555; +defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y26_N3 +dffeas \uart_tx_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N4 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[0]~14 ), + .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_tx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N5 +dffeas \uart_tx_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N8 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[2]~18 ), + .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_tx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N9 +dffeas \uart_tx_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N14 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) +// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[5]~24 ), + .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_tx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N15 +dffeas \uart_tx_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N16 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[6]~26 ), + .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_tx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N17 +dffeas \uart_tx_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N18 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) +// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[7]~28 ), + .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_tx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N19 +dffeas \uart_tx_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N20 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[8]~30 ), + .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_tx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N21 +dffeas \uart_tx_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N24 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[10]~34 ), + .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_tx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N25 +dffeas \uart_tx_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N26 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_tx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_tx_inst|baud_cnt[11]~36 ), + .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N27 +dffeas \uart_tx_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N28 +cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( +// Equation(s): +// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [4]))) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N24 +cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( +// Equation(s): +// \uart_tx_inst|Equal2~1_combout = (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt [12] & (\uart_tx_inst|Equal2~0_combout & \uart_tx_inst|Equal1~1_combout ))) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(\uart_tx_inst|Equal2~0_combout ), + .datad(\uart_tx_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h1000; +defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N25 +dffeas \uart_tx_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|Equal2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N18 +cycloneive_lcell_comb \uart_tx_inst|always3~0 ( +// Equation(s): +// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(gnd), + .datac(gnd), + .datad(\uart_tx_inst|bit_flag~q ), + .cin(gnd), + .combout(\uart_tx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always3~0 .lut_mask = 16'h55FF; +defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N12 +cycloneive_lcell_comb \uart_tx_inst|always0~1 ( +// Equation(s): +// \uart_tx_inst|always0~1_combout = (\uart_tx_inst|always0~0_combout & (\uart_tx_inst|bit_flag~q & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [3]))) + + .dataa(\uart_tx_inst|always0~0_combout ), + .datab(\uart_tx_inst|bit_flag~q ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_tx_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~1 .lut_mask = 16'h8000; +defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N4 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|work_en~q & \uart_tx_inst|bit_flag~q ))))) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|bit_flag~q ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h0078; +defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N5 +dffeas \uart_tx_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[0]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N0 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~4 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[1]~4_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) + + .dataa(\uart_tx_inst|always0~1_combout ), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_tx_inst|bit_cnt [1]), + .datad(\uart_tx_inst|always3~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1]~4 .lut_mask = 16'h5014; +defparam \uart_tx_inst|bit_cnt[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N1 +dffeas \uart_tx_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[1]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N16 +cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( +// Equation(s): +// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [2] & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1])))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|bit_cnt [3]), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h6CCC; +defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N2 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~2 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[3]~2_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & (\uart_tx_inst|bit_cnt [3])) # (!\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|Add1~0_combout ))))) + + .dataa(\uart_tx_inst|always0~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|Add1~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3]~2 .lut_mask = 16'h5140; +defparam \uart_tx_inst|bit_cnt[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N3 +dffeas \uart_tx_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[3]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[0]~16 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[0]~16_combout = \data_rw_ctrl_inst|cnt_wait [0] $ (VCC) +// \data_rw_ctrl_inst|cnt_wait[0]~17 = CARRY(\data_rw_ctrl_inst|cnt_wait [0]) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[0]~17 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[3]~22 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[3]~22_combout = (\data_rw_ctrl_inst|cnt_wait [3] & (!\data_rw_ctrl_inst|cnt_wait[2]~21 )) # (!\data_rw_ctrl_inst|cnt_wait [3] & ((\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[3]~23 = CARRY((!\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (!\data_rw_ctrl_inst|cnt_wait [3])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[2]~21 ), + .combout(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[3]~23 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[4]~24 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[4]~24_combout = (\data_rw_ctrl_inst|cnt_wait [4] & (\data_rw_ctrl_inst|cnt_wait[3]~23 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [4] & (!\data_rw_ctrl_inst|cnt_wait[3]~23 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[4]~25 = CARRY((\data_rw_ctrl_inst|cnt_wait [4] & !\data_rw_ctrl_inst|cnt_wait[3]~23 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [4]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[3]~23 ), + .combout(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[4]~25 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N9 +dffeas \data_rw_ctrl_inst|cnt_wait[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal3~0_combout = (\data_rw_ctrl_inst|cnt_wait [4]) # (!\data_rw_ctrl_inst|cnt_wait [5]) + + .dataa(\data_rw_ctrl_inst|cnt_wait [5]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|cnt_wait [4]), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal3~0 .lut_mask = 16'hF5F5; +defparam \data_rw_ctrl_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N15 +dffeas \data_rw_ctrl_inst|rd_busy_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|rd_busy_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|rd_busy_dly .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|rd_busy_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[0]~12 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[0]~12_combout = \data_rw_ctrl_inst|send_data_num [0] $ (VCC) +// \data_rw_ctrl_inst|send_data_num[0]~13 = CARRY(\data_rw_ctrl_inst|send_data_num [0]) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|send_data_num[0]~12_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[0]~13 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[0]~12 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|send_data_num[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y26_N1 +dffeas \data_rw_ctrl_inst|send_data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[0]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[1]~14 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[1]~14_combout = (\data_rw_ctrl_inst|send_data_num [1] & (!\data_rw_ctrl_inst|send_data_num[0]~13 )) # (!\data_rw_ctrl_inst|send_data_num [1] & ((\data_rw_ctrl_inst|send_data_num[0]~13 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[1]~15 = CARRY((!\data_rw_ctrl_inst|send_data_num[0]~13 ) # (!\data_rw_ctrl_inst|send_data_num [1])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [1]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[0]~13 ), + .combout(\data_rw_ctrl_inst|send_data_num[1]~14_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[1]~15 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[1]~14 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|send_data_num[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N3 +dffeas \data_rw_ctrl_inst|send_data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[1]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[2]~16 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[2]~16_combout = (\data_rw_ctrl_inst|send_data_num [2] & (\data_rw_ctrl_inst|send_data_num[1]~15 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [2] & (!\data_rw_ctrl_inst|send_data_num[1]~15 & VCC)) +// \data_rw_ctrl_inst|send_data_num[2]~17 = CARRY((\data_rw_ctrl_inst|send_data_num [2] & !\data_rw_ctrl_inst|send_data_num[1]~15 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [2]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[1]~15 ), + .combout(\data_rw_ctrl_inst|send_data_num[2]~16_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[2]~17 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[2]~16 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N5 +dffeas \data_rw_ctrl_inst|send_data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[2]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~0_combout = (\data_rw_ctrl_inst|send_data_num [3] & (\data_rw_ctrl_inst|send_data_num [1] & (\data_rw_ctrl_inst|send_data_num [2] & \data_rw_ctrl_inst|send_data_num [0]))) + + .dataa(\data_rw_ctrl_inst|send_data_num [3]), + .datab(\data_rw_ctrl_inst|send_data_num [1]), + .datac(\data_rw_ctrl_inst|send_data_num [2]), + .datad(\data_rw_ctrl_inst|send_data_num [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~0 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[4]~20 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[4]~20_combout = (\data_rw_ctrl_inst|send_data_num [4] & (\data_rw_ctrl_inst|send_data_num[3]~19 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [4] & (!\data_rw_ctrl_inst|send_data_num[3]~19 & VCC)) +// \data_rw_ctrl_inst|send_data_num[4]~21 = CARRY((\data_rw_ctrl_inst|send_data_num [4] & !\data_rw_ctrl_inst|send_data_num[3]~19 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [4]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[3]~19 ), + .combout(\data_rw_ctrl_inst|send_data_num[4]~20_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[4]~21 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[4]~20 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N9 +dffeas \data_rw_ctrl_inst|send_data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[4]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[5]~22 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[5]~22_combout = (\data_rw_ctrl_inst|send_data_num [5] & (!\data_rw_ctrl_inst|send_data_num[4]~21 )) # (!\data_rw_ctrl_inst|send_data_num [5] & ((\data_rw_ctrl_inst|send_data_num[4]~21 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[5]~23 = CARRY((!\data_rw_ctrl_inst|send_data_num[4]~21 ) # (!\data_rw_ctrl_inst|send_data_num [5])) + + .dataa(\data_rw_ctrl_inst|send_data_num [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[4]~21 ), + .combout(\data_rw_ctrl_inst|send_data_num[5]~22_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[5]~23 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[5]~22 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|send_data_num[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N15 +dffeas \data_rw_ctrl_inst|send_data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[7]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N11 +dffeas \data_rw_ctrl_inst|send_data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[5]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~1 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~1_combout = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num [7] & (\data_rw_ctrl_inst|send_data_num [4] & \data_rw_ctrl_inst|send_data_num [5]))) + + .dataa(\data_rw_ctrl_inst|send_data_num [6]), + .datab(\data_rw_ctrl_inst|send_data_num [7]), + .datac(\data_rw_ctrl_inst|send_data_num [4]), + .datad(\data_rw_ctrl_inst|send_data_num [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~1 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|always3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~3 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~3_combout = (\data_rw_ctrl_inst|always3~2_combout & (\data_rw_ctrl_inst|always3~0_combout & (\data_rw_ctrl_inst|always3~1_combout & \data_rw_ctrl_inst|Equal2~4_combout ))) + + .dataa(\data_rw_ctrl_inst|always3~2_combout ), + .datab(\data_rw_ctrl_inst|always3~0_combout ), + .datac(\data_rw_ctrl_inst|always3~1_combout ), + .datad(\data_rw_ctrl_inst|Equal2~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~3 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|always3~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_en~0 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_en~0_combout = (!\data_rw_ctrl_inst|always3~3_combout & ((\data_rw_ctrl_inst|send_data_en~q ) # ((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q & \data_rw_ctrl_inst|rd_busy_dly~q )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .datab(\data_rw_ctrl_inst|rd_busy_dly~q ), + .datac(\data_rw_ctrl_inst|send_data_en~q ), + .datad(\data_rw_ctrl_inst|always3~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|send_data_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_en~0 .lut_mask = 16'h00F4; +defparam \data_rw_ctrl_inst|send_data_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N23 +dffeas \data_rw_ctrl_inst|send_data_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_en .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~1 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal3~1_combout = (\data_rw_ctrl_inst|cnt_wait [0]) # ((\data_rw_ctrl_inst|cnt_wait [3]) # ((\data_rw_ctrl_inst|cnt_wait [2]) # (\data_rw_ctrl_inst|cnt_wait [1]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [0]), + .datab(\data_rw_ctrl_inst|cnt_wait [3]), + .datac(\data_rw_ctrl_inst|cnt_wait [2]), + .datad(\data_rw_ctrl_inst|cnt_wait [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal3~1 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~26 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[13]~26_combout = ((\data_rw_ctrl_inst|Equal2~2_combout & (!\data_rw_ctrl_inst|Equal3~0_combout & !\data_rw_ctrl_inst|Equal3~1_combout ))) # (!\data_rw_ctrl_inst|send_data_en~q ) + + .dataa(\data_rw_ctrl_inst|Equal2~2_combout ), + .datab(\data_rw_ctrl_inst|Equal3~0_combout ), + .datac(\data_rw_ctrl_inst|send_data_en~q ), + .datad(\data_rw_ctrl_inst|Equal3~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .lut_mask = 16'h0F2F; +defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y27_N1 +dffeas \data_rw_ctrl_inst|cnt_wait[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[1]~18 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[1]~18_combout = (\data_rw_ctrl_inst|cnt_wait [1] & (!\data_rw_ctrl_inst|cnt_wait[0]~17 )) # (!\data_rw_ctrl_inst|cnt_wait [1] & ((\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[1]~19 = CARRY((!\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (!\data_rw_ctrl_inst|cnt_wait [1])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [1]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[0]~17 ), + .combout(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[1]~19 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N3 +dffeas \data_rw_ctrl_inst|cnt_wait[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[2]~20 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[2]~20_combout = (\data_rw_ctrl_inst|cnt_wait [2] & (\data_rw_ctrl_inst|cnt_wait[1]~19 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [2] & (!\data_rw_ctrl_inst|cnt_wait[1]~19 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[2]~21 = CARRY((\data_rw_ctrl_inst|cnt_wait [2] & !\data_rw_ctrl_inst|cnt_wait[1]~19 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [2]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[1]~19 ), + .combout(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[2]~21 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N5 +dffeas \data_rw_ctrl_inst|cnt_wait[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y27_N7 +dffeas \data_rw_ctrl_inst|cnt_wait[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~3 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~3_combout = (\data_rw_ctrl_inst|cnt_wait [0] & (\data_rw_ctrl_inst|cnt_wait [3] & (\data_rw_ctrl_inst|cnt_wait [2] & \data_rw_ctrl_inst|cnt_wait [1]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [0]), + .datab(\data_rw_ctrl_inst|cnt_wait [3]), + .datac(\data_rw_ctrl_inst|cnt_wait [2]), + .datad(\data_rw_ctrl_inst|cnt_wait [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~3 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[6]~29 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[6]~29_combout = (\data_rw_ctrl_inst|cnt_wait [6] & (\data_rw_ctrl_inst|cnt_wait[5]~28 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [6] & (!\data_rw_ctrl_inst|cnt_wait[5]~28 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[6]~30 = CARRY((\data_rw_ctrl_inst|cnt_wait [6] & !\data_rw_ctrl_inst|cnt_wait[5]~28 )) + + .dataa(\data_rw_ctrl_inst|cnt_wait [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[5]~28 ), + .combout(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[6]~30 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .lut_mask = 16'hA50A; +defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[7]~31 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[7]~31_combout = (\data_rw_ctrl_inst|cnt_wait [7] & (!\data_rw_ctrl_inst|cnt_wait[6]~30 )) # (!\data_rw_ctrl_inst|cnt_wait [7] & ((\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[7]~32 = CARRY((!\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (!\data_rw_ctrl_inst|cnt_wait [7])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [7]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[6]~30 ), + .combout(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[7]~32 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N15 +dffeas \data_rw_ctrl_inst|cnt_wait[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[8]~33 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[8]~33_combout = (\data_rw_ctrl_inst|cnt_wait [8] & (\data_rw_ctrl_inst|cnt_wait[7]~32 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [8] & (!\data_rw_ctrl_inst|cnt_wait[7]~32 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[8]~34 = CARRY((\data_rw_ctrl_inst|cnt_wait [8] & !\data_rw_ctrl_inst|cnt_wait[7]~32 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [8]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[7]~32 ), + .combout(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[8]~34 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N17 +dffeas \data_rw_ctrl_inst|cnt_wait[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[9]~35 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[9]~35_combout = (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait[8]~34 )) # (!\data_rw_ctrl_inst|cnt_wait [9] & ((\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[9]~36 = CARRY((!\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (!\data_rw_ctrl_inst|cnt_wait [9])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [9]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[8]~34 ), + .combout(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[9]~36 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N19 +dffeas \data_rw_ctrl_inst|cnt_wait[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[10]~37 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[10]~37_combout = (\data_rw_ctrl_inst|cnt_wait [10] & (\data_rw_ctrl_inst|cnt_wait[9]~36 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait[9]~36 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[10]~38 = CARRY((\data_rw_ctrl_inst|cnt_wait [10] & !\data_rw_ctrl_inst|cnt_wait[9]~36 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [10]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[9]~36 ), + .combout(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[10]~38 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N21 +dffeas \data_rw_ctrl_inst|cnt_wait[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[10] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[11]~39 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[11]~39_combout = (\data_rw_ctrl_inst|cnt_wait [11] & (!\data_rw_ctrl_inst|cnt_wait[10]~38 )) # (!\data_rw_ctrl_inst|cnt_wait [11] & ((\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[11]~40 = CARRY((!\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (!\data_rw_ctrl_inst|cnt_wait [11])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[10]~38 ), + .combout(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[11]~40 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[12]~41 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[12]~41_combout = (\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait[11]~40 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [12] & (!\data_rw_ctrl_inst|cnt_wait[11]~40 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[12]~42 = CARRY((\data_rw_ctrl_inst|cnt_wait [12] & !\data_rw_ctrl_inst|cnt_wait[11]~40 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [12]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[11]~40 ), + .combout(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[12]~42 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N25 +dffeas \data_rw_ctrl_inst|cnt_wait[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [12]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[12] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~43 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[13]~43_combout = (\data_rw_ctrl_inst|cnt_wait [13] & (!\data_rw_ctrl_inst|cnt_wait[12]~42 )) # (!\data_rw_ctrl_inst|cnt_wait [13] & ((\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[13]~44 = CARRY((!\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (!\data_rw_ctrl_inst|cnt_wait [13])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[12]~42 ), + .combout(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[13]~44 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[14]~45 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[14]~45_combout = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait[13]~44 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [14] & (!\data_rw_ctrl_inst|cnt_wait[13]~44 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[14]~46 = CARRY((\data_rw_ctrl_inst|cnt_wait [14] & !\data_rw_ctrl_inst|cnt_wait[13]~44 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [14]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[13]~44 ), + .combout(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[14]~46 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N29 +dffeas \data_rw_ctrl_inst|cnt_wait[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [14]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[14] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[15]~47 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[15]~47_combout = \data_rw_ctrl_inst|cnt_wait [15] $ (\data_rw_ctrl_inst|cnt_wait[14]~46 ) + + .dataa(\data_rw_ctrl_inst|cnt_wait [15]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|cnt_wait[14]~46 ), + .combout(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N31 +dffeas \data_rw_ctrl_inst|cnt_wait[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [15]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[15] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[15] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y27_N13 +dffeas \data_rw_ctrl_inst|cnt_wait[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~0 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~0_combout = (!\data_rw_ctrl_inst|cnt_wait [7] & (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait [8] & \data_rw_ctrl_inst|cnt_wait [6]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [7]), + .datab(\data_rw_ctrl_inst|cnt_wait [9]), + .datac(\data_rw_ctrl_inst|cnt_wait [8]), + .datad(\data_rw_ctrl_inst|cnt_wait [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~0 .lut_mask = 16'h0400; +defparam \data_rw_ctrl_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y27_N27 +dffeas \data_rw_ctrl_inst|cnt_wait[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [13]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[13] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y27_N23 +dffeas \data_rw_ctrl_inst|cnt_wait[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [11]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[11] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~1 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~1_combout = (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait [13] & \data_rw_ctrl_inst|cnt_wait [11]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [10]), + .datab(\data_rw_ctrl_inst|cnt_wait [12]), + .datac(\data_rw_ctrl_inst|cnt_wait [13]), + .datad(\data_rw_ctrl_inst|cnt_wait [11]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~1 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~2 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~2_combout = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait [15] & (\data_rw_ctrl_inst|Equal2~0_combout & \data_rw_ctrl_inst|Equal2~1_combout ))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [14]), + .datab(\data_rw_ctrl_inst|cnt_wait [15]), + .datac(\data_rw_ctrl_inst|Equal2~0_combout ), + .datad(\data_rw_ctrl_inst|Equal2~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~2 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~4 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~4_combout = (!\data_rw_ctrl_inst|cnt_wait [5] & (\data_rw_ctrl_inst|Equal2~3_combout & (\data_rw_ctrl_inst|cnt_wait [4] & \data_rw_ctrl_inst|Equal2~2_combout ))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [5]), + .datab(\data_rw_ctrl_inst|Equal2~3_combout ), + .datac(\data_rw_ctrl_inst|cnt_wait [4]), + .datad(\data_rw_ctrl_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~4 .lut_mask = 16'h4000; +defparam \data_rw_ctrl_inst|Equal2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N7 +dffeas \data_rw_ctrl_inst|rd_fifo_rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|Equal2~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|rd_fifo_rd_en .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|rd_fifo_rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0300; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]) # (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .lut_mask = 16'hFFFE; +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & ((\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|always3~0_combout )))) # (!\sd_ctrl_inst|sd_read_inst|always3~2_combout ) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .lut_mask = 16'hDF55; +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .lut_mask = 16'h0080; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N9 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y28_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9] + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .lut_mask = 16'hF0F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEBD7; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N15 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y28_N15 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y27_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hF0C0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hE1F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout & +// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0020; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .lut_mask = 16'h0100; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0300; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'hC3F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h3C3C; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h3CC3; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q +// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0A08; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h78F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout & +// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0020; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y27_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y28_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y28_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X30_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y28_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout & (\data_rw_ctrl_inst|rd_fifo_rd_en~q +// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'h8880; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0100; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9] $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .lut_mask = 16'hC3F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .lut_mask = 16'h55AA; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N15 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h3CC3; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'hF00F; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .lut_mask = 16'h78F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h3333; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout = (\data_rw_ctrl_inst|rd_fifo_rd_en~q & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hCCC0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout = (\sd_miso~input_o & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N7 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~13_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout = ((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) # (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .lut_mask = 16'h55D5; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N31 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N1 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N13 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N19 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N17 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N23 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N21 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N23 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N17 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~14_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N3 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h00FF; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .lut_mask = 16'h00FF; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~15_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [1] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N17 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~11_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N29 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~7_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N1 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~5_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N5 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~3_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N19 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~9_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N7 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~0_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N25 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N11 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~16_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N29 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~12_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N9 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~8_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N5 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~6_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N7 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N21 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~4_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N11 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~10_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N3 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N19 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [15]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N25 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N20 +cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( +// Equation(s): +// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [3] & (((\uart_tx_inst|bit_cnt [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])) # (!\uart_tx_inst|always0~0_combout ))) + + .dataa(\uart_tx_inst|always0~0_combout ), + .datab(\uart_tx_inst|bit_cnt [3]), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hCCC4; +defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N8 +cycloneive_lcell_comb \uart_tx_inst|tx~0 ( +// Equation(s): +// \uart_tx_inst|tx~0_combout = (\uart_tx_inst|bit_flag~q & (!\uart_tx_inst|Mux0~5_combout & ((!\uart_tx_inst|Mux0~0_combout )))) # (!\uart_tx_inst|bit_flag~q & (((\uart_tx_inst|tx~q )))) + + .dataa(\uart_tx_inst|Mux0~5_combout ), + .datab(\uart_tx_inst|bit_flag~q ), + .datac(\uart_tx_inst|tx~q ), + .datad(\uart_tx_inst|Mux0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~0 .lut_mask = 16'h3074; +defparam \uart_tx_inst|tx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N9 +dffeas \uart_tx_inst|tx ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|tx~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|tx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|tx .is_wysiwyg = "true"; +defparam \uart_tx_inst|tx .power_up = "low"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_85c_v_slow.sdo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_85c_v_slow.sdo new file mode 100644 index 0000000..079b0bf --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_8_1200mv_85c_v_slow.sdo @@ -0,0 +1,19061 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "uart_sd") + (DATE "06/02/2023 04:03:14") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (4506:4506:4506) (4506:4506:4506)) + (PORT inclk[0] (2340:2340:2340) (2340:2340:2340)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (923:923:923)) + (PORT datab (808:808:808) (785:785:785)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (804:804:804)) + (PORT datab (1238:1238:1238) (1164:1164:1164)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (574:574:574)) + (PORT datab (334:334:334) (410:410:410)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1867:1867:1867)) + (PORT sclr (2890:2890:2890) (3064:3064:3064)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1396:1396:1396) (1367:1367:1367)) + (PORT d[1] (1359:1359:1359) (1335:1335:1335)) + (PORT d[2] (1452:1452:1452) (1414:1414:1414)) + (PORT d[3] (1585:1585:1585) (1553:1553:1553)) + (PORT d[4] (1387:1387:1387) (1364:1364:1364)) + (PORT d[5] (1594:1594:1594) (1561:1561:1561)) + (PORT d[6] (1414:1414:1414) (1386:1386:1386)) + (PORT d[7] (1413:1413:1413) (1374:1374:1374)) + (PORT clk (2265:2265:2265) (2302:2302:2302)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1000:1000:1000) (1004:1004:1004)) + (PORT d[1] (1057:1057:1057) (1051:1051:1051)) + (PORT d[2] (1285:1285:1285) (1234:1234:1234)) + (PORT d[3] (1146:1146:1146) (1091:1091:1091)) + (PORT d[4] (998:998:998) (1003:1003:1003)) + (PORT d[5] (1764:1764:1764) (1697:1697:1697)) + (PORT d[6] (1395:1395:1395) (1356:1356:1356)) + (PORT d[7] (1735:1735:1735) (1651:1651:1651)) + (PORT d[8] (1021:1021:1021) (1025:1025:1025)) + (PORT d[9] (923:923:923) (875:875:875)) + (PORT clk (2261:2261:2261) (2297:2297:2297)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1263:1263:1263) (1151:1151:1151)) + (PORT clk (2261:2261:2261) (2297:2297:2297)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2265:2265:2265) (2302:2302:2302)) + (PORT d[0] (1970:1970:1970) (1865:1865:1865)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2266:2266:2266) (2303:2303:2303)) + (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2266:2266:2266) (2303:2303:2303)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2266:2266:2266) (2303:2303:2303)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2266:2266:2266) (2303:2303:2303)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1346:1346:1346) (1254:1254:1254)) + (PORT d[1] (1033:1033:1033) (1026:1026:1026)) + (PORT d[2] (1785:1785:1785) (1710:1710:1710)) + (PORT d[3] (1782:1782:1782) (1727:1727:1727)) + (PORT d[4] (1630:1630:1630) (1616:1616:1616)) + (PORT d[5] (1873:1873:1873) (1814:1814:1814)) + (PORT d[6] (1365:1365:1365) (1328:1328:1328)) + (PORT d[7] (1459:1459:1459) (1427:1427:1427)) + (PORT d[8] (974:974:974) (920:920:920)) + (PORT clk (2215:2215:2215) (2211:2211:2211)) + (PORT stall (1591:1591:1591) (1712:1712:1712)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + (HOLD stall (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (2215:2215:2215) (2211:2211:2211)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2216:2216:2216) (2212:2212:2212)) + (IOPATH (posedge clk) pulse (0:0:0) (3182:3182:3182)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2216:2216:2216) (2212:2212:2212)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2216:2216:2216) (2212:2212:2212)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (2207:2207:2207) (2207:2207:2207)) + (PORT ena (2140:2140:2140) (2024:2024:2024)) + (IOPATH (posedge clk) q (392:392:392) (392:392:392)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (64:64:64)) + (SETUP ena (posedge clk) (64:64:64)) + (HOLD d (posedge clk) (211:211:211)) + (HOLD ena (posedge clk) (211:211:211)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1219:1219:1219) (1143:1143:1143)) + (PORT d[1] (1184:1184:1184) (1118:1118:1118)) + (PORT d[2] (1203:1203:1203) (1138:1138:1138)) + (PORT d[3] (1598:1598:1598) (1487:1487:1487)) + (PORT d[4] (1213:1213:1213) (1146:1146:1146)) + (PORT d[5] (1177:1177:1177) (1117:1117:1117)) + (PORT d[6] (1221:1221:1221) (1147:1147:1147)) + (PORT d[7] (1211:1211:1211) (1142:1142:1142)) + (PORT d[9] (1185:1185:1185) (1123:1123:1123)) + (PORT d[10] (1282:1282:1282) (1216:1216:1216)) + (PORT d[11] (1267:1267:1267) (1194:1194:1194)) + (PORT d[12] (1220:1220:1220) (1147:1147:1147)) + (PORT d[13] (1532:1532:1532) (1431:1431:1431)) + (PORT d[14] (1183:1183:1183) (1121:1121:1121)) + (PORT d[15] (1589:1589:1589) (1459:1459:1459)) + (PORT d[16] (1587:1587:1587) (1473:1473:1473)) + (PORT clk (2277:2277:2277) (2307:2307:2307)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1343:1343:1343) (1305:1305:1305)) + (PORT d[1] (1319:1319:1319) (1250:1250:1250)) + (PORT d[2] (1673:1673:1673) (1575:1575:1575)) + (PORT d[3] (1201:1201:1201) (1154:1154:1154)) + (PORT d[4] (1004:1004:1004) (992:992:992)) + (PORT d[5] (1807:1807:1807) (1681:1681:1681)) + (PORT d[6] (1680:1680:1680) (1599:1599:1599)) + (PORT d[7] (949:949:949) (949:949:949)) + (PORT d[8] (1566:1566:1566) (1421:1421:1421)) + (PORT clk (2273:2273:2273) (2302:2302:2302)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1282:1282:1282) (1174:1174:1174)) + (PORT clk (2273:2273:2273) (2302:2302:2302)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2277:2277:2277) (2307:2307:2307)) + (PORT d[0] (1989:1989:1989) (1888:1888:1888)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2308:2308:2308)) + (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2308:2308:2308)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2308:2308:2308)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1309:1309:1309) (1203:1203:1203)) + (PORT d[1] (1804:1804:1804) (1740:1740:1740)) + (PORT d[2] (1461:1461:1461) (1445:1445:1445)) + (PORT d[3] (1021:1021:1021) (1013:1013:1013)) + (PORT d[4] (1060:1060:1060) (1047:1047:1047)) + (PORT d[5] (1578:1578:1578) (1553:1553:1553)) + (PORT d[6] (1006:1006:1006) (992:992:992)) + (PORT d[7] (1333:1333:1333) (1307:1307:1307)) + (PORT d[8] (1312:1312:1312) (1273:1273:1273)) + (PORT d[9] (1627:1627:1627) (1511:1511:1511)) + (PORT clk (2227:2227:2227) (2216:2216:2216)) + (PORT stall (1248:1248:1248) (1359:1359:1359)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + (HOLD stall (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (2227:2227:2227) (2216:2216:2216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2228:2228:2228) (2217:2217:2217)) + (IOPATH (posedge clk) pulse (0:0:0) (3182:3182:3182)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2228:2228:2228) (2217:2217:2217)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2228:2228:2228) (2217:2217:2217)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (2219:2219:2219) (2212:2212:2212)) + (PORT ena (1788:1788:1788) (1681:1681:1681)) + (IOPATH (posedge clk) q (392:392:392) (392:392:392)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (64:64:64)) + (SETUP ena (posedge clk) (64:64:64)) + (HOLD d (posedge clk) (211:211:211)) + (HOLD ena (posedge clk) (211:211:211)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (610:610:610)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (481:481:481)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (464:464:464)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (459:459:459)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (449:449:449)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (423:423:423)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (433:433:433)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (462:462:462)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (430:430:430)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (450:450:450)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (432:432:432)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (435:435:435)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (426:426:426)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (436:436:436)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT datac (805:805:805) (798:798:798)) + (PORT datad (312:312:312) (392:392:392)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD55) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT datab (628:628:628) (632:632:632)) + (PORT datac (580:580:580) (595:595:595)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (432:432:432)) + (PORT datab (565:565:565) (593:593:593)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (605:605:605)) + (PORT datab (342:342:342) (425:425:425)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~0) + (DELAY + (ABSOLUTE + (PORT datac (524:524:524) (558:558:558)) + (PORT datad (474:474:474) (446:446:446)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~1) + (DELAY + (ABSOLUTE + (PORT dataa (287:287:287) (326:326:326)) + (PORT datab (642:642:642) (657:657:657)) + (PORT datac (1966:1966:1966) (1886:1886:1886)) + (PORT datad (1111:1111:1111) (1012:1012:1012)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (463:463:463)) + (PORT datab (359:359:359) (454:454:454)) + (PORT datac (317:317:317) (411:411:411)) + (PORT datad (321:321:321) (404:404:404)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (627:627:627)) + (PORT datab (394:394:394) (508:508:508)) + (PORT datac (924:924:924) (871:871:871)) + (PORT datad (508:508:508) (485:485:485)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (953:953:953) (919:919:919)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (508:508:508) (494:494:494)) + (PORT datad (355:355:355) (466:466:466)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (585:585:585)) + (PORT datab (383:383:383) (479:479:479)) + (PORT datac (566:566:566) (543:543:543)) + (PORT datad (356:356:356) (467:467:467)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (315:315:315)) + (PORT datab (385:385:385) (481:481:481)) + (PORT datac (1679:1679:1679) (1549:1549:1549)) + (PORT datad (928:928:928) (884:884:884)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (628:628:628)) + (PORT datab (389:389:389) (503:503:503)) + (PORT datac (906:906:906) (851:851:851)) + (PORT datad (513:513:513) (492:492:492)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (925:925:925)) + (PORT datab (384:384:384) (480:480:480)) + (PORT datac (449:449:449) (425:425:425)) + (PORT datad (943:943:943) (885:885:885)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (366:366:366) (458:458:458)) + (PORT datac (343:343:343) (439:439:439)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (926:926:926)) + (PORT datab (384:384:384) (480:480:480)) + (PORT datac (559:559:559) (534:534:534)) + (PORT datad (354:354:354) (464:464:464)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (946:946:946) (905:905:905)) + (PORT datab (398:398:398) (513:513:513)) + (PORT datac (558:558:558) (533:533:533)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (370:370:370) (462:462:462)) + (PORT datac (238:238:238) (265:265:265)) + (PORT datad (240:240:240) (258:258:258)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (327:327:327)) + (PORT datab (641:641:641) (656:656:656)) + (PORT datac (573:573:573) (592:592:592)) + (PORT datad (868:868:868) (822:822:822)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1004:1004:1004) (1026:1026:1026)) + (PORT datab (1097:1097:1097) (1105:1105:1105)) + (PORT datac (975:975:975) (1007:1007:1007)) + (PORT datad (1014:1014:1014) (1020:1020:1020)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~2) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1013:1013:1013)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (974:974:974) (1005:1005:1005)) + (PORT datad (978:978:978) (973:973:973)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1026:1026:1026)) + (PORT datab (1018:1018:1018) (1046:1046:1046)) + (PORT datac (1038:1038:1038) (1061:1061:1061)) + (PORT datad (1012:1012:1012) (1018:1018:1018)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~3) + (DELAY + (ABSOLUTE + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (954:954:954) (967:967:967)) + (PORT datad (898:898:898) (902:902:902)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1004:1004:1004) (1026:1026:1026)) + (PORT datab (1093:1093:1093) (1100:1100:1100)) + (PORT datac (958:958:958) (977:977:977)) + (PORT datad (1013:1013:1013) (1018:1018:1018)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1027:1027:1027)) + (PORT datab (1017:1017:1017) (1045:1045:1045)) + (PORT datac (953:953:953) (966:966:966)) + (PORT datad (237:237:237) (256:256:256)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1004:1004:1004) (1026:1026:1026)) + (PORT datab (1019:1019:1019) (1048:1048:1048)) + (PORT datac (956:956:956) (975:975:975)) + (PORT datad (1014:1014:1014) (1019:1019:1019)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~7) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (1012:1012:1012)) + (PORT datab (1097:1097:1097) (1104:1104:1104)) + (PORT datac (974:974:974) (1006:1006:1006)) + (PORT datad (237:237:237) (256:256:256)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1026:1026:1026)) + (PORT datab (1099:1099:1099) (1107:1107:1107)) + (PORT datac (975:975:975) (1008:1008:1008)) + (PORT datad (1015:1015:1015) (1021:1021:1021)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~8) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (1011:1011:1011)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (955:955:955) (974:974:974)) + (PORT datad (900:900:900) (898:898:898)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~9) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (906:906:906) (904:904:904)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1056:1056:1056) (1042:1042:1042)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT datac (335:335:335) (423:423:423)) + (PORT datad (341:341:341) (440:440:440)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (877:877:877)) + (PORT datab (392:392:392) (494:494:494)) + (PORT datac (353:353:353) (473:473:473)) + (PORT datad (867:867:867) (797:797:797)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (310:310:310)) + (PORT datab (390:390:390) (492:492:492)) + (PORT datac (851:851:851) (786:786:786)) + (PORT datad (878:878:878) (811:811:811)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (811:811:811)) + (PORT datab (397:397:397) (515:515:515)) + (PORT datac (809:809:809) (750:750:750)) + (PORT datad (348:348:348) (449:449:449)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~4) + (DELAY + (ABSOLUTE + (PORT datab (398:398:398) (515:515:515)) + (PORT datac (811:811:811) (754:754:754)) + (PORT datad (349:349:349) (450:450:450)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (337:337:337) (424:424:424)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (433:433:433)) + (PORT datab (353:353:353) (439:439:439)) + (PORT datad (531:531:531) (559:559:559)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (628:628:628)) + (PORT datab (360:360:360) (449:449:449)) + (PORT datac (316:316:316) (413:413:413)) + (PORT datad (263:263:263) (280:280:280)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~2) + (DELAY + (ABSOLUTE + (PORT datab (615:615:615) (619:619:619)) + (PORT datac (564:564:564) (579:579:579)) + (PORT datad (521:521:521) (540:540:540)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT asdata (1696:1696:1696) (1660:1660:1660)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (907:907:907)) + (PORT datab (1228:1228:1228) (1188:1188:1188)) + (PORT datac (341:341:341) (430:430:430)) + (PORT datad (254:254:254) (283:283:283)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT datab (353:353:353) (439:439:439)) + (PORT datac (354:354:354) (438:438:438)) + (PORT datad (274:274:274) (295:295:295)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT datab (595:595:595) (631:631:631)) + (PORT datad (254:254:254) (283:283:283)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT datab (883:883:883) (842:842:842)) + (PORT datac (810:810:810) (790:790:790)) + (PORT datad (764:764:764) (700:700:700)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT datac (810:810:810) (790:790:790)) + (PORT datad (764:764:764) (700:700:700)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datac (1269:1269:1269) (1235:1235:1235)) + (PORT datad (1212:1212:1212) (1150:1150:1150)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (437:437:437)) + (PORT datac (312:312:312) (400:400:400)) + (PORT datad (323:323:323) (402:402:402)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (473:473:473)) + (PORT datab (352:352:352) (442:442:442)) + (PORT datac (336:336:336) (426:426:426)) + (PORT datad (313:313:313) (393:393:393)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (445:445:445)) + (PORT datab (294:294:294) (333:333:333)) + (PORT datac (845:845:845) (833:833:833)) + (PORT datad (256:256:256) (282:282:282)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (919:919:919)) + (PORT datab (590:590:590) (574:574:574)) + (PORT datac (1103:1103:1103) (1004:1004:1004)) + (PORT datad (338:338:338) (419:419:419)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (PORT datab (343:343:343) (423:423:423)) + (PORT datad (300:300:300) (373:373:373)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT datab (976:976:976) (910:910:910)) + (PORT datac (788:788:788) (717:717:717)) + (PORT datad (340:340:340) (424:424:424)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (446:446:446)) + (PORT datab (294:294:294) (333:333:333)) + (PORT datac (845:845:845) (833:833:833)) + (PORT datad (256:256:256) (281:281:281)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1102:1102:1102)) + (PORT datab (362:362:362) (452:452:452)) + (PORT datac (318:318:318) (416:416:416)) + (PORT datad (482:482:482) (469:469:469)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (279:279:279) (304:304:304)) + (PORT datac (494:494:494) (468:468:468)) + (PORT datad (826:826:826) (758:758:758)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (483:483:483)) + (PORT datab (285:285:285) (317:317:317)) + (PORT datac (495:495:495) (475:475:475)) + (PORT datad (972:972:972) (966:966:966)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (432:432:432)) + (PORT datab (340:340:340) (419:419:419)) + (PORT datad (320:320:320) (390:390:390)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (462:462:462)) + (PORT datab (342:342:342) (425:425:425)) + (PORT datac (302:302:302) (386:386:386)) + (PORT datad (320:320:320) (407:407:407)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (464:464:464)) + (PORT datab (276:276:276) (300:300:300)) + (PORT datad (249:249:249) (271:271:271)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.CMD24_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datab (515:515:515) (501:501:501)) + (PORT datac (486:486:486) (463:463:463)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (603:603:603)) + (PORT datab (397:397:397) (512:512:512)) + (PORT datad (329:329:329) (420:420:420)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (1341:1341:1341) (1329:1329:1329)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (934:934:934)) + (PORT datab (867:867:867) (869:869:869)) + (PORT datad (903:903:903) (893:893:893)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (760:760:760) (830:830:830)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (941:941:941)) + (PORT datab (944:944:944) (930:930:930)) + (PORT datad (293:293:293) (363:363:363)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (760:760:760) (829:829:829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (959:959:959)) + (PORT datab (888:888:888) (883:883:883)) + (PORT datad (881:881:881) (876:876:876)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (973:973:973) (988:988:988)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1189:1189:1189) (1105:1105:1105)) + (PORT datab (905:905:905) (896:896:896)) + (PORT datad (296:296:296) (365:365:365)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (471:471:471)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (482:482:482) (450:450:450)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (932:932:932)) + (PORT datab (1342:1342:1342) (1281:1281:1281)) + (PORT datad (310:310:310) (394:394:394)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1612:1612:1612) (1516:1516:1516)) + (PORT datab (921:921:921) (910:910:910)) + (PORT datad (549:549:549) (573:573:573)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[9\]) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT asdata (769:769:769) (844:844:844)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT asdata (772:772:772) (848:848:848)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT asdata (1327:1327:1327) (1294:1294:1294)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (912:912:912)) + (PORT datab (617:617:617) (631:631:631)) + (PORT datad (295:295:295) (365:365:365)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1347:1347:1347) (1288:1288:1288)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT asdata (761:761:761) (831:831:831)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (626:626:626)) + (PORT datab (827:827:827) (817:817:817)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT datab (391:391:391) (507:507:507)) + (PORT datac (336:336:336) (424:424:424)) + (PORT datad (340:340:340) (439:439:439)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (295:295:295) (330:330:330)) + (PORT datad (291:291:291) (325:325:325)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (946:946:946)) + (PORT datab (341:341:341) (421:421:421)) + (PORT datac (305:305:305) (389:389:389)) + (PORT datad (301:301:301) (378:378:378)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1366:1366:1366) (1361:1361:1361)) + (PORT datad (291:291:291) (319:319:319)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT asdata (760:760:760) (829:829:829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datab (515:515:515) (501:501:501)) + (PORT datac (487:487:487) (463:463:463)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2013:2013:2013) (1835:1835:1835)) + (PORT datac (330:330:330) (415:415:415)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (1740:1740:1740) (1706:1706:1706)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (1825:1825:1825) (1791:1791:1791)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (794:794:794) (869:869:869)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT asdata (771:771:771) (846:846:846)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1624:1624:1624)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1624:1624:1624)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1624:1624:1624)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1624:1624:1624)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT ena (1107:1107:1107) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT asdata (771:771:771) (846:846:846)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1624:1624:1624)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1624:1624:1624)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1624:1624:1624)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|tx_flag) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (424:424:424)) + (PORT datad (1118:1118:1118) (1013:1013:1013)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT asdata (768:768:768) (843:843:843)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT asdata (762:762:762) (832:832:832)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1311:1311:1311) (1233:1233:1233)) + (PORT datab (980:980:980) (943:943:943)) + (PORT datac (362:362:362) (451:451:451)) + (PORT datad (282:282:282) (306:306:306)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~4) + (DELAY + (ABSOLUTE + (PORT datab (421:421:421) (544:544:544)) + (PORT datac (303:303:303) (388:388:388)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~5) + (DELAY + (ABSOLUTE + (PORT datab (421:421:421) (544:544:544)) + (PORT datac (307:307:307) (391:391:391)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~6) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (953:953:953)) + (PORT datac (377:377:377) (502:502:502)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~7) + (DELAY + (ABSOLUTE + (PORT dataa (4197:4197:4197) (4406:4406:4406)) + (PORT datad (917:917:917) (911:911:911)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT asdata (789:789:789) (859:859:859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3759:3759:3759) (3988:3988:3988)) + (PORT datab (354:354:354) (440:440:440)) + (PORT datac (579:579:579) (595:595:595)) + (PORT datad (922:922:922) (922:922:922)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (468:468:468)) + (PORT datab (353:353:353) (441:441:441)) + (PORT datac (531:531:531) (562:562:562)) + (PORT datad (237:237:237) (256:256:256)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (478:478:478)) + (PORT datab (303:303:303) (340:340:340)) + (PORT datac (337:337:337) (429:429:429)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg3) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT asdata (2143:2143:2143) (2068:2068:2068)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT asdata (1042:1042:1042) (1075:1075:1075)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1685:1685:1685) (1653:1653:1653)) + (PORT datab (1310:1310:1310) (1222:1222:1222)) + (PORT datac (307:307:307) (394:394:394)) + (PORT datad (1199:1199:1199) (1130:1130:1130)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1672:1672:1672) (1637:1637:1637)) + (PORT datab (1306:1306:1306) (1218:1218:1218)) + (PORT datac (301:301:301) (386:386:386)) + (PORT datad (1203:1203:1203) (1136:1136:1136)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1389:1389:1389) (1384:1384:1384)) + (PORT datab (900:900:900) (861:861:861)) + (PORT datac (1136:1136:1136) (1066:1066:1066)) + (PORT datad (304:304:304) (377:377:377)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1275:1275:1275) (1196:1196:1196)) + (PORT datab (1307:1307:1307) (1218:1218:1218)) + (PORT datac (1621:1621:1621) (1577:1577:1577)) + (PORT datad (307:307:307) (382:382:382)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~2) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (466:466:466)) + (PORT datab (370:370:370) (466:466:466)) + (PORT datac (311:311:311) (399:399:399)) + (PORT datad (312:312:312) (388:388:388)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1367:1367:1367) (1362:1362:1362)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (645:645:645)) + (PORT datab (856:856:856) (845:845:845)) + (PORT datac (537:537:537) (560:560:560)) + (PORT datad (527:527:527) (551:551:551)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a2) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1595:1595:1595) (1481:1481:1481)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1875:1875:1875) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (599:599:599)) + (PORT datab (341:341:341) (424:424:424)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (449:449:449)) + (PORT datab (349:349:349) (438:438:438)) + (PORT datac (311:311:311) (401:401:401)) + (PORT datad (311:311:311) (391:391:391)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT datab (365:365:365) (442:442:442)) + (PORT datad (324:324:324) (395:395:395)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1875:1875:1875) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|start_nedge) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (438:438:438)) + (PORT datac (1672:1672:1672) (1604:1604:1604)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (306:306:306) (392:392:392)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (301:301:301) (386:386:386)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg1\~0) + (DELAY + (ABSOLUTE + (PORT datad (3662:3662:3662) (3834:3834:3834)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (346:346:346) (436:436:436)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rx\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (796:796:796) (842:842:842)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (550:550:550) (581:581:581)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (971:971:971) (966:966:966)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1242:1242:1242) (1210:1210:1210)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (326:326:326) (397:397:397)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (536:536:536) (568:568:568)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1468:1468:1468) (1342:1342:1342)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|tx_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (325:325:325) (396:396:396)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (904:904:904) (893:893:893)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (306:306:306) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (376:376:376)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (305:305:305) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (377:377:377)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (377:377:377)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (305:305:305) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (908:908:908) (909:909:909)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (906:906:906) (907:907:907)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (378:378:378)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (305:305:305) (378:378:378)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (884:884:884) (878:878:878)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (809:809:809) (780:780:780)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (364:364:364)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sd_clk\~output) + (DELAY + (ABSOLUTE + (PORT i (1609:1609:1609) (1559:1559:1559)) + (IOPATH i o (3241:3241:3241) (3144:3144:3144)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sd_cs_n\~output) + (DELAY + (ABSOLUTE + (PORT i (1891:1891:1891) (1762:1762:1762)) + (IOPATH i o (3241:3241:3241) (3144:3144:3144)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sd_mosi\~output) + (DELAY + (ABSOLUTE + (PORT i (1825:1825:1825) (1696:1696:1696)) + (IOPATH i o (3241:3241:3241) (3144:3144:3144)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tx\~output) + (DELAY + (ABSOLUTE + (PORT i (2904:2904:2904) (3042:3042:3042)) + (IOPATH i o (3336:3336:3336) (3399:3399:3399)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (806:806:806) (852:852:852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (374:374:374) (460:460:460)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (3674:3674:3674) (3934:3934:3934)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (4634:4634:4634) (4434:4434:4434)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3009:3009:3009) (3252:3252:3252)) + (PORT datab (3770:3770:3770) (3925:3925:3925)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2603:2603:2603) (2464:2464:2464)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sd_miso\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|miso_dly) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT asdata (4598:4598:4598) (4812:4812:4812)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (4196:4196:4196) (4405:4405:4405)) + (PORT datab (344:344:344) (427:427:427)) + (PORT datad (528:528:528) (555:555:555)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (643:643:643)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (846:846:846) (813:813:813)) + (PORT datad (553:553:553) (574:574:574)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (605:605:605)) + (PORT datab (891:891:891) (857:857:857)) + (PORT datac (844:844:844) (810:810:810)) + (PORT datad (552:552:552) (573:573:573)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~2) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (529:529:529)) + (PORT datab (491:491:491) (476:476:476)) + (PORT datad (254:254:254) (282:282:282)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (435:435:435)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (603:603:603)) + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (303:303:303) (387:387:387)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (626:626:626)) + (PORT datac (499:499:499) (480:480:480)) + (PORT datad (320:320:320) (390:390:390)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT asdata (1676:1676:1676) (1638:1638:1638)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT asdata (768:768:768) (844:844:844)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (380:380:380)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT asdata (998:998:998) (1014:1014:1014)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (365:365:365)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT asdata (786:786:786) (856:856:856)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (380:380:380)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT asdata (768:768:768) (844:844:844)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (432:432:432)) + (PORT datab (342:342:342) (421:421:421)) + (PORT datad (523:523:523) (549:549:549)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (774:774:774)) + (PORT datac (446:446:446) (418:418:418)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (435:435:435)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (433:433:433)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (459:459:459)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (385:385:385) (476:476:476)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (482:482:482)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3848:3848:3848) (4133:4133:4133)) + (PORT datab (949:949:949) (947:947:947)) + (PORT datac (347:347:347) (443:443:443)) + (PORT datad (349:349:349) (434:434:434)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (521:521:521)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datad (246:246:246) (271:271:271)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (430:430:430)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datac (310:310:310) (399:399:399)) + (PORT datad (320:320:320) (411:411:411)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datab (286:286:286) (314:314:314)) + (PORT datac (347:347:347) (443:443:443)) + (PORT datad (349:349:349) (433:433:433)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (462:462:462)) + (PORT datab (343:343:343) (422:422:422)) + (PORT datac (345:345:345) (440:440:440)) + (PORT datad (347:347:347) (431:431:431)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (474:474:474)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (380:380:380) (466:466:466)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (337:337:337) (427:427:427)) + (PORT datad (338:338:338) (423:423:423)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT asdata (1262:1262:1262) (1239:1239:1239)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT asdata (762:762:762) (832:832:832)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (299:299:299) (370:370:370)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT asdata (759:759:759) (828:828:828)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT asdata (761:761:761) (830:830:830)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT asdata (761:761:761) (830:830:830)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT asdata (760:760:760) (829:829:829)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (306:306:306) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (381:381:381)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT asdata (998:998:998) (1021:1021:1021)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (894:894:894) (890:890:890)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT asdata (761:761:761) (830:830:830)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT asdata (762:762:762) (832:832:832)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT asdata (760:760:760) (829:829:829)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (369:369:369)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (365:365:365)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[27\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT asdata (762:762:762) (831:831:831)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[28\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT asdata (763:763:763) (833:833:833)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[29\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT asdata (760:760:760) (829:829:829)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (364:364:364)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[32\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (1246:1246:1246) (1218:1218:1218)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (314:314:314) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (508:508:508) (535:535:535)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[35\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (982:982:982) (1002:1002:1002)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (590:590:590)) + (PORT datad (506:506:506) (534:534:534)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[36\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (971:971:971) (986:986:986)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (380:380:380)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (302:302:302) (375:375:375)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (770:770:770) (846:846:846)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (PORT datab (343:343:343) (424:424:424)) + (PORT datad (304:304:304) (376:376:376)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT datab (294:294:294) (333:333:333)) + (PORT datad (256:256:256) (282:282:282)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (883:883:883) (802:802:802)) + (PORT datac (320:320:320) (416:416:416)) + (PORT datad (482:482:482) (469:469:469)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD0) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (433:433:433)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (447:447:447)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (600:600:600)) + (PORT datab (341:341:341) (424:424:424)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (284:284:284) (315:315:315)) + (PORT datac (311:311:311) (402:402:402)) + (PORT datad (248:248:248) (270:270:270)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (433:433:433)) + (PORT datab (342:342:342) (425:425:425)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE\~0) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (452:452:452)) + (PORT datab (286:286:286) (317:317:317)) + (PORT datad (249:249:249) (271:271:271)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END\~0) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (785:785:785)) + (PORT datad (788:788:788) (706:706:706)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr18) + (DELAY + (ABSOLUTE + (PORT datab (531:531:531) (520:520:520)) + (PORT datac (306:306:306) (392:392:392)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (369:369:369) (449:449:449)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (426:426:426)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (436:436:436)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (609:609:609)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (328:328:328) (405:405:405)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (959:959:959) (947:947:947)) + (PORT datac (864:864:864) (812:812:812)) + (PORT datad (285:285:285) (313:313:313)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1004:1004:1004) (1026:1026:1026)) + (PORT datab (1099:1099:1099) (1107:1107:1107)) + (PORT datac (975:975:975) (1007:1007:1007)) + (PORT datad (1015:1015:1015) (1021:1021:1021)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~2) + (DELAY + (ABSOLUTE + (PORT datac (858:858:858) (805:805:805)) + (PORT datad (279:279:279) (306:306:306)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (782:782:782) (733:733:733)) + (PORT datab (381:381:381) (464:464:464)) + (PORT datad (530:530:530) (526:526:526)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD0_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1182:1182:1182) (1104:1104:1104)) + (PORT datab (359:359:359) (453:453:453)) + (PORT datac (320:320:320) (416:416:416)) + (PORT datad (479:479:479) (466:466:466)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (734:734:734)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datad (531:531:531) (528:528:528)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD8) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (736:736:736)) + (PORT datab (371:371:371) (455:455:455)) + (PORT datad (532:532:532) (529:529:529)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD8_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (475:475:475)) + (PORT datab (594:594:594) (578:578:578)) + (PORT datad (826:826:826) (758:758:758)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD55_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (462:462:462)) + (PORT datab (591:591:591) (574:574:574)) + (PORT datad (820:820:820) (752:752:752)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.ACMD41_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (462:462:462)) + (PORT datab (359:359:359) (452:452:452)) + (PORT datac (316:316:316) (410:410:410)) + (PORT datad (321:321:321) (392:392:392)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datab (980:980:980) (914:914:914)) + (PORT datac (793:793:793) (723:723:723)) + (PORT datad (329:329:329) (406:406:406)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (519:519:519)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (319:319:319) (413:413:413)) + (PORT datad (824:824:824) (756:756:756)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_ACMD41) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (472:472:472)) + (PORT datab (370:370:370) (454:454:454)) + (PORT datac (538:538:538) (572:572:572)) + (PORT datad (338:338:338) (419:419:419)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~1) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (857:857:857)) + (PORT datab (324:324:324) (355:355:355)) + (PORT datac (522:522:522) (494:494:494)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (441:441:441)) + (PORT datab (531:531:531) (520:520:520)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|init_end) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (445:445:445)) + (PORT datac (805:805:805) (798:798:798)) + (PORT datad (338:338:338) (418:418:418)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (818:818:818)) + (PORT datab (830:830:830) (770:770:770)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (1185:1185:1185) (1096:1096:1096)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.SEND_CMD17) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (442:442:442)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (369:369:369) (450:450:450)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (450:450:450)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (599:599:599)) + (PORT datab (351:351:351) (440:440:440)) + (PORT datac (318:318:318) (413:413:413)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (444:444:444)) + (PORT datac (326:326:326) (411:411:411)) + (PORT datad (309:309:309) (389:389:389)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (483:483:483)) + (PORT datab (285:285:285) (316:316:316)) + (PORT datac (495:495:495) (475:475:475)) + (PORT datad (972:972:972) (967:967:967)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (531:531:531)) + (PORT datab (1201:1201:1201) (1076:1076:1076)) + (PORT datad (255:255:255) (283:283:283)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.CMD17_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (336:336:336)) + (PORT datab (345:345:345) (428:428:428)) + (PORT datac (504:504:504) (486:486:486)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (784:784:784)) + (PORT datab (854:854:854) (816:816:816)) + (PORT datad (1184:1184:1184) (1095:1095:1095)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_DATA) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (627:627:627)) + (PORT datab (359:359:359) (453:453:453)) + (PORT datac (338:338:338) (428:428:428)) + (PORT datad (318:318:318) (405:405:405)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (433:433:433)) + (PORT datab (565:565:565) (594:594:594)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (301:301:301) (378:378:378)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (341:341:341)) + (PORT datab (530:530:530) (492:492:492)) + (PORT datac (509:509:509) (480:480:480)) + (PORT datad (574:574:574) (595:595:595)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~2) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (464:464:464)) + (PORT datab (1663:1663:1663) (1589:1589:1589)) + (PORT datad (291:291:291) (319:319:319)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (470:470:470)) + (PORT datac (314:314:314) (403:403:403)) + (PORT datad (312:312:312) (389:389:389)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1369:1369:1369) (1364:1364:1364)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (292:292:292) (319:319:319)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (465:465:465)) + (PORT datac (310:310:310) (398:398:398)) + (PORT datad (311:311:311) (388:388:388)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~11) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (453:453:453)) + (PORT datad (601:601:601) (651:651:651)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~10) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (704:704:704)) + (PORT datac (301:301:301) (385:385:385)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~9) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (704:704:704)) + (PORT datad (506:506:506) (537:537:537)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~8) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (702:702:702)) + (PORT datac (303:303:303) (386:386:386)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (437:437:437)) + (PORT datab (550:550:550) (585:585:585)) + (PORT datac (304:304:304) (387:387:387)) + (PORT datad (295:295:295) (365:365:365)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~14) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (622:622:622)) + (PORT datad (600:600:600) (650:650:650)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~13) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (700:700:700)) + (PORT datac (304:304:304) (389:389:389)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~12) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (701:701:701)) + (PORT datac (302:302:302) (386:386:386)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~15) + (DELAY + (ABSOLUTE + (PORT datab (421:421:421) (544:544:544)) + (PORT datac (302:302:302) (387:387:387)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (431:431:431)) + (PORT datab (343:343:343) (424:424:424)) + (PORT datac (535:535:535) (553:553:553)) + (PORT datad (534:534:534) (560:560:560)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~4) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (531:531:531)) + (PORT datab (287:287:287) (319:319:319)) + (PORT datac (506:506:506) (485:485:485)) + (PORT datad (490:490:490) (461:461:461)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~4) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (475:475:475)) + (PORT datab (889:889:889) (798:798:798)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~1) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (436:436:436)) + (PORT datab (422:422:422) (545:545:545)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~0) + (DELAY + (ABSOLUTE + (PORT datab (421:421:421) (544:544:544)) + (PORT datac (304:304:304) (388:388:388)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~3) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (435:435:435)) + (PORT datab (422:422:422) (545:545:545)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~2) + (DELAY + (ABSOLUTE + (PORT datab (421:421:421) (545:545:545)) + (PORT datac (304:304:304) (389:389:389)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (433:433:433)) + (PORT datab (343:343:343) (423:423:423)) + (PORT datac (300:300:300) (383:383:383)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (530:530:530)) + (PORT datab (286:286:286) (318:318:318)) + (PORT datac (505:505:505) (484:484:484)) + (PORT datad (490:490:490) (461:461:461)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1366:1366:1366) (1360:1360:1360)) + (PORT datab (323:323:323) (360:360:360)) + (PORT datad (291:291:291) (319:319:319)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1369:1369:1369) (1364:1364:1364)) + (PORT datab (322:322:322) (359:359:359)) + (PORT datac (445:445:445) (427:427:427)) + (PORT datad (333:333:333) (427:427:427)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (453:453:453)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (449:449:449)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~3) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (344:344:344)) + (PORT datab (321:321:321) (358:358:358)) + (PORT datac (518:518:518) (550:550:550)) + (PORT datad (332:332:332) (426:426:426)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~4) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (498:498:498)) + (PORT datab (634:634:634) (643:643:643)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (499:499:499)) + (PORT datab (854:854:854) (816:816:816)) + (PORT datad (516:516:516) (550:550:550)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_END) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~1) + (DELAY + (ABSOLUTE + (PORT datad (531:531:531) (560:560:560)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~2) + (DELAY + (ABSOLUTE + (PORT datab (353:353:353) (439:439:439)) + (PORT datad (531:531:531) (559:559:559)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (422:422:422)) + (PORT datac (303:303:303) (388:388:388)) + (PORT datad (311:311:311) (395:395:395)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (313:313:313) (343:343:343)) + (PORT datad (533:533:533) (562:562:562)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (550:550:550) (575:575:575)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (433:433:433)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (566:566:566) (593:593:593)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (435:435:435)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (432:432:432)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (428:428:428)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (PORT datab (342:342:342) (425:425:425)) + (PORT datac (301:301:301) (386:386:386)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (466:466:466)) + (PORT datab (570:570:570) (598:598:598)) + (PORT datac (309:309:309) (401:401:401)) + (PORT datad (311:311:311) (395:395:395)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~2) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (315:315:315) (342:342:342)) + (PORT datad (266:266:266) (283:283:283)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (467:467:467)) + (PORT datab (343:343:343) (421:421:421)) + (PORT datad (274:274:274) (298:298:298)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT asdata (768:768:768) (844:844:844)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (380:380:380)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT asdata (994:994:994) (1010:1010:1010)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (432:432:432)) + (PORT datab (341:341:341) (420:420:420)) + (PORT datad (320:320:320) (391:391:391)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (365:365:365)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT asdata (786:786:786) (856:856:856)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT asdata (772:772:772) (849:849:849)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (438:438:438)) + (PORT datab (344:344:344) (424:424:424)) + (PORT datad (527:527:527) (554:554:554)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~2) + (DELAY + (ABSOLUTE + (PORT datab (893:893:893) (833:833:833)) + (PORT datad (833:833:833) (773:773:773)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (326:326:326)) + (PORT datab (1925:1925:1925) (1777:1777:1777)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_DATA) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\~0) + (DELAY + (ABSOLUTE + (PORT datad (2353:2353:2353) (2234:2234:2234)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~2) + (DELAY + (ABSOLUTE + (PORT datab (388:388:388) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1867:1867:1867)) + (PORT sclr (2890:2890:2890) (3064:3064:3064)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~1) + (DELAY + (ABSOLUTE + (PORT datab (388:388:388) (480:480:480)) + (PORT datad (332:332:332) (423:423:423)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1867:1867:1867)) + (PORT sclr (2890:2890:2890) (3064:3064:3064)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (628:628:628)) + (PORT datab (388:388:388) (502:502:502)) + (PORT datac (342:342:342) (438:438:438)) + (PORT datad (328:328:328) (418:418:418)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~16) + (DELAY + (ABSOLUTE + (PORT datac (1946:1946:1946) (1865:1865:1865)) + (PORT datad (1111:1111:1111) (1012:1012:1012)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (449:449:449)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1063:1063:1063)) + (PORT datab (622:622:622) (629:629:629)) + (PORT datac (574:574:574) (593:593:593)) + (PORT datad (536:536:536) (557:557:557)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~3) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (509:509:509)) + (PORT datab (641:641:641) (655:655:655)) + (PORT datac (527:527:527) (561:561:561)) + (PORT datad (265:265:265) (283:283:283)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1156:1156:1156)) + (PORT datab (1653:1653:1653) (1531:1531:1531)) + (PORT datad (466:466:466) (440:440:440)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_BUSY) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (4262:4262:4262) (4487:4487:4487)) + (PORT datad (382:382:382) (478:478:478)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~7) + (DELAY + (ABSOLUTE + (PORT datac (304:304:304) (389:389:389)) + (PORT datad (382:382:382) (479:479:479)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~6) + (DELAY + (ABSOLUTE + (PORT datac (306:306:306) (392:392:392)) + (PORT datad (381:381:381) (478:478:478)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~5) + (DELAY + (ABSOLUTE + (PORT datac (304:304:304) (387:387:387)) + (PORT datad (382:382:382) (479:479:479)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (430:430:430)) + (PORT datab (345:345:345) (426:426:426)) + (PORT datac (299:299:299) (380:380:380)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~4) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (437:437:437)) + (PORT datad (382:382:382) (478:478:478)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~3) + (DELAY + (ABSOLUTE + (PORT datab (364:364:364) (441:441:441)) + (PORT datad (382:382:382) (479:479:479)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~2) + (DELAY + (ABSOLUTE + (PORT datac (304:304:304) (389:389:389)) + (PORT datad (382:382:382) (479:479:479)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~1) + (DELAY + (ABSOLUTE + (PORT datac (304:304:304) (387:387:387)) + (PORT datad (382:382:382) (478:478:478)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (603:603:603)) + (PORT datab (343:343:343) (423:423:423)) + (PORT datac (300:300:300) (382:382:382)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT datab (277:277:277) (302:302:302)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1231:1231:1231)) + (PORT datab (1192:1192:1192) (1083:1083:1083)) + (PORT datad (257:257:257) (287:287:287)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_END) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~2) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (451:451:451)) + (PORT datad (535:535:535) (565:565:565)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~1) + (DELAY + (ABSOLUTE + (PORT datad (536:536:536) (566:566:566)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~0) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (450:450:450)) + (PORT datab (345:345:345) (428:428:428)) + (PORT datad (537:537:537) (568:568:568)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (310:310:310) (402:402:402)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1680:1680:1680) (1629:1629:1629)) + (PORT datad (258:258:258) (287:287:287)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1678:1678:1678) (1628:1628:1628)) + (PORT datab (298:298:298) (330:330:330)) + (PORT datad (532:532:532) (561:561:561)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|wr_busy_dly\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (820:820:820) (814:814:814)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|wr_busy_dly) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|wr_busy_fall\~0) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (414:414:414)) + (PORT datad (819:819:819) (814:814:814)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|rd_en) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n\~2) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (843:843:843)) + (PORT datab (315:315:315) (345:345:345)) + (PORT datad (314:314:314) (394:394:394)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_cs_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (868:868:868)) + (PORT datab (374:374:374) (456:456:456)) + (PORT datac (792:792:792) (770:770:770)) + (PORT datad (295:295:295) (364:364:364)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (459:459:459)) + (PORT datab (359:359:359) (453:453:453)) + (PORT datac (319:319:319) (413:413:413)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (463:463:463)) + (PORT datab (353:353:353) (442:442:442)) + (PORT datac (311:311:311) (400:400:400)) + (PORT datad (313:313:313) (393:393:393)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (878:878:878)) + (PORT datab (585:585:585) (616:616:616)) + (PORT datac (588:588:588) (606:606:606)) + (PORT datad (489:489:489) (460:460:460)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (292:292:292) (332:332:332)) + (PORT datab (584:584:584) (615:615:615)) + (PORT datac (586:586:586) (604:604:604)) + (PORT datad (493:493:493) (465:465:465)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (327:327:327)) + (PORT datab (534:534:534) (498:498:498)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (266:266:266) (283:283:283)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~3) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (522:522:522)) + (PORT datab (760:760:760) (709:709:709)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cs_n) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_cs_n\~1) + (DELAY + (ABSOLUTE + (PORT datab (1224:1224:1224) (1093:1093:1093)) + (PORT datac (293:293:293) (370:370:370)) + (PORT datad (822:822:822) (800:800:800)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~11) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (926:926:926) (876:876:876)) + (PORT datad (868:868:868) (815:815:815)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|mosi) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1877:1877:1877)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1868:1868:1868)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (605:605:605)) + (PORT datab (351:351:351) (440:440:440)) + (PORT datac (319:319:319) (413:413:413)) + (PORT datad (312:312:312) (392:392:392)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~1) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (483:483:483)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (320:320:320) (414:414:414)) + (PORT datad (312:312:312) (395:395:395)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~2) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (482:482:482)) + (PORT datab (304:304:304) (328:328:328)) + (PORT datac (239:239:239) (266:266:266)) + (PORT datad (968:968:968) (962:962:962)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0) + (DELAY + (ABSOLUTE + (PORT datac (239:239:239) (266:266:266)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (480:480:480)) + (PORT datab (342:342:342) (425:425:425)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (430:430:430)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datab (377:377:377) (465:465:465)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (485:485:485)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datad (265:265:265) (301:301:301)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (480:480:480)) + (PORT datab (381:381:381) (470:470:470)) + (PORT datac (239:239:239) (266:266:266)) + (PORT datad (263:263:263) (298:298:298)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (435:435:435)) + (PORT datab (341:341:341) (423:423:423)) + (PORT datad (303:303:303) (379:379:379)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (600:600:600)) + (PORT datab (341:341:341) (420:420:420)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (606:606:606)) + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (301:301:301) (377:377:377)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (644:644:644)) + (PORT datab (855:855:855) (844:844:844)) + (PORT datac (536:536:536) (560:560:560)) + (PORT datad (527:527:527) (551:551:551)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (518:518:518)) + (PORT datab (636:636:636) (650:650:650)) + (PORT datac (501:501:501) (478:478:478)) + (PORT datad (734:734:734) (661:661:661)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (424:424:424)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT datab (280:280:280) (306:306:306)) + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (351:351:351) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (352:352:352) (435:435:435)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (351:351:351) (440:440:440)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (449:449:449)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (451:451:451)) + (PORT datab (351:351:351) (440:440:440)) + (PORT datac (312:312:312) (402:402:402)) + (PORT datad (312:312:312) (392:392:392)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (727:727:727)) + (PORT datab (635:635:635) (648:648:648)) + (PORT datac (506:506:506) (483:483:483)) + (PORT datad (449:449:449) (422:422:422)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT datab (306:306:306) (344:344:344)) + (PORT datac (331:331:331) (437:437:437)) + (PORT datad (527:527:527) (549:549:549)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_flag) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_flag) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (1440:1440:1440) (1427:1427:1427)) + (PORT clrn (1883:1883:1883) (1862:1862:1862)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT asdata (1319:1319:1319) (1273:1273:1273)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1475:1475:1475) (1423:1423:1423)) + (PORT datab (1359:1359:1359) (1341:1341:1341)) + (PORT datac (864:864:864) (825:825:825)) + (PORT datad (1466:1466:1466) (1446:1446:1446)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (365:365:365)) + (PORT datad (349:349:349) (433:433:433)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1475:1475:1475) (1423:1423:1423)) + (PORT datab (1357:1357:1357) (1339:1339:1339)) + (PORT datac (864:864:864) (825:825:825)) + (PORT datad (1465:1465:1465) (1444:1444:1444)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (485:485:485)) + (PORT datab (591:591:591) (614:614:614)) + (PORT datad (465:465:465) (440:440:440)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (463:463:463)) + (PORT datab (387:387:387) (479:479:479)) + (PORT datac (279:279:279) (316:316:316)) + (PORT datad (348:348:348) (431:431:431)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (481:481:481)) + (PORT datad (255:255:255) (279:279:279)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (477:477:477)) + (PORT datac (346:346:346) (443:443:443)) + (PORT datad (254:254:254) (279:279:279)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (485:485:485)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1326:1326:1326) (1309:1309:1309)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1681:1681:1681) (1604:1604:1604)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (287:287:287) (322:322:322)) + (PORT datad (534:534:534) (571:571:571)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (539:539:539) (558:558:558)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1319:1319:1319) (1260:1260:1260)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1218:1218:1218)) + (PORT datab (984:984:984) (967:967:967)) + (PORT datad (318:318:318) (396:396:396)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (569:569:569) (587:587:587)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1309:1309:1309) (1255:1255:1255)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (545:545:545) (568:568:568)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (348:348:348)) + (PORT datab (379:379:379) (465:465:465)) + (PORT datad (548:548:548) (559:559:559)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (550:550:550) (573:573:573)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (1365:1365:1365) (1346:1346:1346)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (792:792:792) (771:771:771)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT asdata (761:761:761) (830:830:830)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT asdata (812:812:812) (900:900:900)) + (PORT ena (1669:1669:1669) (1588:1588:1588)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (994:994:994)) + (PORT datab (367:367:367) (447:447:447)) + (PORT datad (973:973:973) (975:975:975)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT asdata (810:810:810) (898:898:898)) + (PORT ena (1669:1669:1669) (1588:1588:1588)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT asdata (1023:1023:1023) (1040:1040:1040)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (858:858:858) (861:861:861)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (507:507:507) (532:532:532)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (975:975:975) (990:990:990)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (597:597:597) (608:608:608)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (1715:1715:1715) (1669:1669:1669)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (670:670:670)) + (PORT datab (1009:1009:1009) (992:992:992)) + (PORT datad (301:301:301) (378:378:378)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (859:859:859) (797:797:797)) + (PORT datac (442:442:442) (422:422:422)) + (PORT datad (809:809:809) (756:756:756)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (1457:1457:1457) (1407:1407:1407)) + (PORT datac (1269:1269:1269) (1186:1186:1186)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (625:625:625)) + (PORT datab (388:388:388) (481:481:481)) + (PORT datad (889:889:889) (847:847:847)) + (IOPATH dataa combout (405:405:405) (407:407:407)) + (IOPATH datab combout (410:410:410) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1464:1464:1464) (1423:1423:1423)) + (PORT datab (388:388:388) (481:481:481)) + (PORT datac (346:346:346) (425:425:425)) + (PORT datad (1306:1306:1306) (1274:1274:1274)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1681:1681:1681) (1604:1604:1604)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (480:480:480)) + (PORT datad (246:246:246) (267:267:267)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[8\]) + (DELAY + (ABSOLUTE + (PORT datab (1385:1385:1385) (1356:1356:1356)) + (PORT datad (1284:1284:1284) (1241:1241:1241)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1681:1681:1681) (1604:1604:1604)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (461:461:461)) + (PORT datab (385:385:385) (478:478:478)) + (PORT datac (282:282:282) (320:320:320)) + (PORT datad (348:348:348) (432:432:432)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (240:240:240) (259:259:259)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (481:481:481)) + (PORT datab (387:387:387) (481:481:481)) + (PORT datac (346:346:346) (443:443:443)) + (PORT datad (578:578:578) (612:612:612)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1669:1669:1669) (1588:1588:1588)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (413:413:413)) + (PORT datac (296:296:296) (375:375:375)) + (PORT datad (1311:1311:1311) (1267:1267:1267)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity6) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1681:1681:1681) (1604:1604:1604)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1681:1681:1681) (1604:1604:1604)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (388:388:388) (481:481:481)) + (IOPATH datab combout (494:494:494) (496:496:496)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1681:1681:1681) (1604:1604:1604)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1184:1184:1184) (1141:1141:1141)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (971:971:971) (997:997:997)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (1446:1446:1446) (1416:1416:1416)) + (PORT ena (1747:1747:1747) (1669:1669:1669)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (803:803:803) (883:883:883)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (542:542:542) (562:562:562)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (973:973:973)) + (PORT datab (936:936:936) (925:925:925)) + (PORT datad (295:295:295) (364:364:364)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (326:326:326)) + (PORT datab (334:334:334) (410:410:410)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (287:287:287) (325:325:325)) + (PORT datab (898:898:898) (822:822:822)) + (PORT datad (246:246:246) (268:268:268)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (883:883:883)) + (PORT datab (892:892:892) (866:866:866)) + (PORT datac (752:752:752) (678:678:678)) + (PORT datad (506:506:506) (532:532:532)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (620:620:620)) + (PORT datab (377:377:377) (467:467:467)) + (PORT datac (552:552:552) (579:579:579)) + (PORT datad (263:263:263) (295:295:295)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (389:389:389) (486:486:486)) + (PORT datad (254:254:254) (279:279:279)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (620:620:620)) + (PORT datab (387:387:387) (484:484:484)) + (PORT datac (355:355:355) (439:439:439)) + (PORT datad (528:528:528) (565:565:565)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a1) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1595:1595:1595) (1481:1481:1481)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (886:886:886)) + (PORT datab (380:380:380) (470:470:470)) + (PORT datac (855:855:855) (834:834:834)) + (PORT datad (337:337:337) (421:421:421)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a0) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1595:1595:1595) (1481:1481:1481)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (424:424:424)) + (PORT datab (337:337:337) (414:414:414)) + (PORT datac (297:297:297) (375:375:375)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity8) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1595:1595:1595) (1481:1481:1481)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datad (860:860:860) (862:862:862)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1377:1377:1377) (1332:1332:1332)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (448:448:448)) + (PORT datab (368:368:368) (450:450:450)) + (PORT datac (532:532:532) (516:516:516)) + (PORT datad (859:859:859) (861:861:861)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT datad (711:711:711) (642:642:642)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (381:381:381) (467:467:467)) + (PORT datad (263:263:263) (295:295:295)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (620:620:620)) + (PORT datab (378:378:378) (468:468:468)) + (PORT datac (552:552:552) (579:579:579)) + (PORT datad (264:264:264) (296:296:296)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\]\~6) + (DELAY + (ABSOLUTE + (PORT datad (237:237:237) (256:256:256)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (636:636:636)) + (PORT datab (387:387:387) (483:483:483)) + (PORT datad (256:256:256) (281:281:281)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT datab (387:387:387) (483:483:483)) + (PORT datac (351:351:351) (434:434:434)) + (PORT datad (254:254:254) (279:279:279)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (575:575:575) (615:615:615)) + (PORT datad (245:245:245) (270:270:270)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT asdata (1051:1051:1051) (1058:1058:1058)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (1656:1656:1656) (1603:1603:1603)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (764:764:764) (833:833:833)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (759:759:759) (828:828:828)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datac (314:314:314) (402:402:402)) + (PORT datad (324:324:324) (404:404:404)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (477:477:477)) + (PORT datab (392:392:392) (486:486:486)) + (PORT datad (254:254:254) (279:279:279)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (1474:1474:1474) (1459:1459:1459)) + (PORT ena (1575:1575:1575) (1483:1483:1483)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1286:1286:1286) (1243:1243:1243)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1681:1681:1681) (1604:1604:1604)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (1330:1330:1330) (1283:1283:1283)) + (PORT datac (356:356:356) (441:441:441)) + (PORT datad (1211:1211:1211) (1150:1150:1150)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (PORT datab (341:341:341) (420:420:420)) + (PORT datac (307:307:307) (394:394:394)) + (PORT datad (319:319:319) (398:398:398)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1429:1429:1429) (1386:1386:1386)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1747:1747:1747) (1669:1669:1669)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT dataa (1328:1328:1328) (1280:1280:1280)) + (PORT datab (1249:1249:1249) (1190:1190:1190)) + (PORT datac (353:353:353) (438:438:438)) + (PORT datad (946:946:946) (938:938:938)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT datac (330:330:330) (413:413:413)) + (PORT datad (829:829:829) (787:787:787)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (1457:1457:1457) (1419:1419:1419)) + (PORT datac (332:332:332) (416:416:416)) + (PORT datad (826:826:826) (784:784:784)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (1848:1848:1848) (1802:1802:1802)) + (PORT ena (1747:1747:1747) (1669:1669:1669)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT dataa (1456:1456:1456) (1418:1418:1418)) + (PORT datab (1660:1660:1660) (1584:1584:1584)) + (PORT datac (328:328:328) (411:411:411)) + (PORT datad (827:827:827) (785:785:785)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (543:543:543) (569:569:569)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (1321:1321:1321) (1319:1319:1319)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (798:798:798) (777:777:777)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (365:365:365)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT asdata (1055:1055:1055) (1064:1064:1064)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (1680:1680:1680) (1608:1608:1608)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (846:846:846) (809:809:809)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT asdata (762:762:762) (832:832:832)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (PORT datab (550:550:550) (578:578:578)) + (PORT datac (327:327:327) (411:411:411)) + (PORT datad (1572:1572:1572) (1421:1421:1421)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT datac (900:900:900) (854:854:854)) + (PORT datad (734:734:734) (669:669:669)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (1772:1772:1772) (1735:1735:1735)) + (PORT ena (1747:1747:1747) (1669:1669:1669)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (297:297:297) (335:335:335)) + (PORT datac (339:339:339) (428:428:428)) + (PORT datad (553:553:553) (586:586:586)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (566:566:566)) + (PORT datab (370:370:370) (454:454:454)) + (PORT datad (861:861:861) (863:863:863)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (833:833:833) (808:808:808)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1179:1179:1179) (1120:1120:1120)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT asdata (1284:1284:1284) (1237:1237:1237)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (826:826:826)) + (PORT datab (354:354:354) (441:441:441)) + (PORT datac (358:358:358) (443:443:443)) + (PORT datad (272:272:272) (292:292:292)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (826:826:826)) + (PORT datab (1206:1206:1206) (1153:1153:1153)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (904:904:904)) + (PORT datab (602:602:602) (609:609:609)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (593:593:593)) + (PORT datab (955:955:955) (929:929:929)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (620:620:620)) + (PORT datab (883:883:883) (885:885:885)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (419:419:419)) + (PORT datab (532:532:532) (559:559:559)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (421:421:421)) + (PORT datad (528:528:528) (549:549:549)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|comb\~1) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (478:478:478)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|comb\~0) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (1983:1983:1983) (1881:1881:1881)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|comb\~2) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (235:235:235) (261:261:261)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2015:2015:2015) (1838:1838:1838)) + (PORT datab (370:370:370) (452:452:452)) + (PORT datac (1631:1631:1631) (1576:1576:1576)) + (PORT datad (826:826:826) (791:791:791)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (327:327:327)) + (PORT datab (894:894:894) (834:834:834)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (836:836:836) (776:776:776)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.SEND_CMD24) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (450:450:450)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (455:455:455)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (446:446:446)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (464:464:464)) + (PORT datab (359:359:359) (455:455:455)) + (PORT datac (318:318:318) (412:412:412)) + (PORT datad (321:321:321) (404:404:404)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~2) + (DELAY + (ABSOLUTE + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (319:319:319) (415:415:415)) + (PORT datad (320:320:320) (407:407:407)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datab (357:357:357) (452:452:452)) + (PORT datac (317:317:317) (411:411:411)) + (PORT datad (318:318:318) (401:401:401)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (360:360:360) (449:449:449)) + (PORT datac (319:319:319) (415:415:415)) + (PORT datad (248:248:248) (271:271:271)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (490:490:490) (475:475:475)) + (PORT datac (1968:1968:1968) (1887:1887:1887)) + (PORT datad (783:783:783) (726:726:726)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (904:904:904)) + (PORT datab (2008:2008:2008) (1923:1923:1923)) + (PORT datac (1946:1946:1946) (1865:1865:1865)) + (PORT datad (539:539:539) (560:560:560)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (2010:2010:2010) (1925:1925:1925)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_mosi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (868:868:868)) + (PORT datab (941:941:941) (925:925:925)) + (PORT datac (1707:1707:1707) (1633:1633:1633)) + (PORT datad (334:334:334) (414:414:414)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_mosi\~1) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (846:846:846)) + (PORT datac (895:895:895) (881:881:881)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (928:928:928)) + (PORT datab (341:341:341) (420:420:420)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (PORT datab (343:343:343) (425:425:425)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (301:301:301) (376:376:376)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (888:888:888)) + (PORT datab (865:865:865) (770:770:770)) + (PORT datac (903:903:903) (887:887:887)) + (PORT datad (931:931:931) (902:902:902)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (442:442:442)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (453:453:453)) + (PORT datab (352:352:352) (442:442:442)) + (PORT datac (312:312:312) (402:402:402)) + (PORT datad (313:313:313) (394:394:394)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (944:944:944)) + (PORT datac (911:911:911) (901:901:901)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (925:925:925)) + (PORT datab (289:289:289) (318:318:318)) + (PORT datac (813:813:813) (755:755:755)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (433:433:433)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (350:350:350) (440:440:440)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (449:449:449)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (453:453:453)) + (PORT datab (352:352:352) (441:441:441)) + (PORT datac (312:312:312) (402:402:402)) + (PORT datad (313:313:313) (393:393:393)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (945:945:945)) + (PORT datab (965:965:965) (941:941:941)) + (PORT datac (1124:1124:1124) (990:990:990)) + (PORT datad (248:248:248) (275:275:275)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1146:1146:1146)) + (PORT datad (1187:1187:1187) (1123:1123:1123)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (327:327:327)) + (PORT datab (1249:1249:1249) (1173:1173:1173)) + (PORT datac (347:347:347) (466:466:466)) + (PORT datad (310:310:310) (393:393:393)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1147:1147:1147)) + (PORT datab (1252:1252:1252) (1177:1177:1177)) + (PORT datad (291:291:291) (326:326:326)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (377:377:377)) + (PORT datab (391:391:391) (507:507:507)) + (PORT datad (256:256:256) (289:289:289)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (602:602:602)) + (PORT datab (353:353:353) (439:439:439)) + (PORT datac (350:350:350) (470:470:470)) + (PORT datad (346:346:346) (446:446:446)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (377:377:377)) + (PORT datab (297:297:297) (332:332:332)) + (PORT datad (240:240:240) (258:258:258)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (648:648:648)) + (PORT datac (854:854:854) (833:833:833)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|rd_busy_dly) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1865:1865:1865)) + (PORT asdata (1677:1677:1677) (1619:1619:1619)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (418:418:418)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (421:421:421)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (420:420:420)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (435:435:435)) + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (302:302:302) (386:386:386)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (302:302:302) (386:386:386)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~3) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (472:472:472)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (839:839:839) (785:785:785)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1317:1317:1317) (1271:1271:1271)) + (PORT datab (337:337:337) (414:414:414)) + (PORT datad (1043:1043:1043) (938:938:938)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_en) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (642:642:642)) + (PORT datab (578:578:578) (602:602:602)) + (PORT datac (527:527:527) (561:561:561)) + (PORT datad (559:559:559) (579:579:579)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (324:324:324)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (320:320:320) (398:398:398)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (638:638:638)) + (PORT datab (575:575:575) (599:599:599)) + (PORT datac (524:524:524) (557:557:557)) + (PORT datad (556:556:556) (575:575:575)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (448:448:448)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (600:600:600)) + (PORT datab (559:559:559) (585:585:585)) + (PORT datac (533:533:533) (549:549:549)) + (PORT datad (552:552:552) (570:570:570)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (819:819:819)) + (PORT datab (617:617:617) (622:622:622)) + (PORT datac (787:787:787) (765:765:765)) + (PORT datad (522:522:522) (541:541:541)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1524:1524:1524) (1455:1455:1455)) + (PORT datab (558:558:558) (583:583:583)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (648:648:648)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (854:854:854) (833:833:833)) + (PORT datad (245:245:245) (269:269:269)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|rd_fifo_rd_en) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (379:379:379) (466:466:466)) + (PORT datac (348:348:348) (447:447:447)) + (PORT datad (254:254:254) (278:278:278)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (377:377:377) (467:467:467)) + (PORT datad (245:245:245) (266:266:266)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (881:881:881) (867:867:867)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1347:1347:1347) (1288:1288:1288)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (886:886:886)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (916:916:916) (915:915:915)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1140:1140:1140) (1130:1130:1130)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT asdata (1322:1322:1322) (1307:1307:1307)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT asdata (760:760:760) (830:830:830)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT asdata (1407:1407:1407) (1398:1398:1398)) + (PORT ena (1387:1387:1387) (1333:1333:1333)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (865:865:865) (853:853:853)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1265:1265:1265) (1225:1225:1225)) + (PORT datab (361:361:361) (438:438:438)) + (PORT datad (295:295:295) (365:365:365)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (628:628:628)) + (PORT datab (359:359:359) (453:453:453)) + (PORT datac (339:339:339) (429:429:429)) + (PORT datad (318:318:318) (405:405:405)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (343:343:343)) + (PORT datab (472:472:472) (455:455:455)) + (PORT datac (511:511:511) (483:483:483)) + (PORT datad (573:573:573) (594:594:594)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1367:1367:1367) (1362:1362:1362)) + (PORT datab (368:368:368) (464:464:464)) + (PORT datac (484:484:484) (459:459:459)) + (PORT datad (275:275:275) (297:297:297)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT asdata (1441:1441:1441) (1423:1423:1423)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT asdata (762:762:762) (831:831:831)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (858:858:858) (857:857:857)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1875:1875:1875) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1676:1676:1676) (1565:1565:1565)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1875:1875:1875) (1890:1890:1890)) + (PORT asdata (789:789:789) (859:859:859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (549:549:549) (576:576:576)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (626:626:626)) + (PORT datab (631:631:631) (635:635:635)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (931:931:931) (925:925:925)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT asdata (1884:1884:1884) (1779:1779:1779)) + (PORT ena (1347:1347:1347) (1288:1288:1288)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (392:392:392)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT asdata (1410:1410:1410) (1388:1388:1388)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (462:462:462)) + (PORT datab (377:377:377) (465:465:465)) + (PORT datac (500:500:500) (480:480:480)) + (PORT datad (338:338:338) (415:415:415)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1310:1310:1310) (1232:1232:1232)) + (PORT datab (983:983:983) (947:947:947)) + (PORT datad (282:282:282) (305:305:305)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (598:598:598) (609:609:609)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1134:1134:1134) (1128:1128:1128)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (842:842:842) (825:825:825)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1875:1875:1875) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (939:939:939) (923:923:923)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (937:937:937)) + (PORT datab (549:549:549) (585:585:585)) + (PORT datad (294:294:294) (363:363:363)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (810:810:810) (811:811:811)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1588:1588:1588) (1477:1477:1477)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT asdata (786:786:786) (856:856:856)) + (PORT ena (1387:1387:1387) (1333:1333:1333)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (323:323:323) (394:394:394)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT asdata (760:760:760) (829:829:829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (334:334:334) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1387:1387:1387) (1333:1333:1333)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (321:321:321) (391:391:391)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (594:594:594)) + (PORT datab (887:887:887) (893:893:893)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (310:310:310)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (236:236:236) (263:263:263)) + (PORT datad (834:834:834) (764:764:764)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT datab (286:286:286) (318:318:318)) + (PORT datac (1848:1848:1848) (1742:1742:1742)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a0) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1588:1588:1588) (1477:1477:1477)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (886:886:886)) + (PORT datab (379:379:379) (470:470:470)) + (PORT datad (781:781:781) (719:719:719)) + (IOPATH dataa combout (405:405:405) (407:407:407)) + (IOPATH datab combout (410:410:410) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (954:954:954)) + (PORT datab (565:565:565) (600:600:600)) + (PORT datac (300:300:300) (330:330:330)) + (PORT datad (909:909:909) (908:908:908)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (945:945:945)) + (PORT datab (856:856:856) (861:861:861)) + (PORT datad (792:792:792) (723:723:723)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (856:856:856) (862:862:862)) + (PORT datad (792:792:792) (723:723:723)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|cntr_cout\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (826:826:826)) + (PORT datab (956:956:956) (958:958:958)) + (PORT datac (828:828:828) (828:828:828)) + (PORT datad (459:459:459) (433:433:433)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6\~0) + (DELAY + (ABSOLUTE + (PORT datab (990:990:990) (971:971:971)) + (PORT datad (252:252:252) (276:276:276)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (927:927:927)) + (PORT datab (363:363:363) (456:456:456)) + (PORT datac (324:324:324) (420:420:420)) + (PORT datad (933:933:933) (927:927:927)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT datab (993:993:993) (974:974:974)) + (PORT datac (322:322:322) (418:418:418)) + (PORT datad (256:256:256) (281:281:281)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9\~0) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (454:454:454)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT datab (344:344:344) (424:424:424)) + (PORT datac (515:515:515) (545:545:545)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (944:944:944)) + (PORT datab (380:380:380) (470:470:470)) + (PORT datac (324:324:324) (403:403:403)) + (PORT datad (817:817:817) (819:819:819)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1588:1588:1588) (1477:1477:1477)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (413:413:413)) + (PORT datac (297:297:297) (375:375:375)) + (PORT datad (863:863:863) (858:858:858)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity9) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1893:1893:1893) (1790:1790:1790)) + (PORT datab (288:288:288) (320:320:320)) + (PORT datac (523:523:523) (561:561:561)) + (PORT datad (248:248:248) (270:270:270)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (954:954:954)) + (PORT datab (973:973:973) (961:961:961)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (461:461:461)) + (PORT datab (852:852:852) (856:856:856)) + (PORT datac (791:791:791) (707:707:707)) + (PORT datad (874:874:874) (886:886:886)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (237:237:237) (256:256:256)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (459:459:459)) + (PORT datab (991:991:991) (971:971:971)) + (PORT datad (253:253:253) (277:277:277)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8\~0) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (454:454:454)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT asdata (982:982:982) (1003:1003:1003)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT asdata (787:787:787) (856:856:856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT asdata (1238:1238:1238) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT asdata (760:760:760) (829:829:829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (305:305:305) (382:382:382)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (802:802:802) (780:780:780)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1875:1875:1875) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (299:299:299) (369:369:369)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1875:1875:1875) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (299:299:299) (369:369:369)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1875:1875:1875) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (825:825:825)) + (PORT datab (613:613:613) (617:617:617)) + (PORT datad (791:791:791) (760:760:760)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT asdata (1332:1332:1332) (1310:1310:1310)) + (PORT ena (1347:1347:1347) (1288:1288:1288)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (319:319:319) (410:410:410)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (831:831:831) (807:807:807)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (365:365:365)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT asdata (761:761:761) (831:831:831)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT asdata (787:787:787) (873:873:873)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (831:831:831) (800:800:800)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT asdata (761:761:761) (830:830:830)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (431:431:431)) + (PORT datab (575:575:575) (591:591:591)) + (PORT datad (294:294:294) (363:363:363)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (537:537:537) (566:566:566)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (964:964:964) (958:958:958)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1876:1876:1876)) + (PORT asdata (763:763:763) (832:832:832)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (874:874:874) (885:885:885)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1588:1588:1588) (1477:1477:1477)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1876:1876:1876)) + (PORT asdata (1597:1597:1597) (1523:1523:1523)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (365:365:365)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (365:365:365)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (883:883:883)) + (PORT datab (1184:1184:1184) (1107:1107:1107)) + (PORT datad (295:295:295) (365:365:365)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (448:448:448) (424:424:424)) + (PORT datad (770:770:770) (705:705:705)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1020:1020:1020)) + (PORT datab (1834:1834:1834) (1684:1684:1684)) + (PORT datac (243:243:243) (274:274:274)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1419:1419:1419) (1410:1410:1410)) + (PORT datab (991:991:991) (977:977:977)) + (PORT datac (1194:1194:1194) (1158:1158:1158)) + (PORT datad (827:827:827) (769:769:769)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT datad (240:240:240) (258:258:258)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (833:833:833)) + (PORT datad (329:329:329) (402:402:402)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1309:1309:1309) (1230:1230:1230)) + (PORT datab (982:982:982) (946:946:946)) + (PORT datac (359:359:359) (447:447:447)) + (PORT datad (282:282:282) (305:305:305)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (492:492:492)) + (PORT datad (255:255:255) (280:280:280)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (498:498:498)) + (PORT datab (381:381:381) (468:468:468)) + (PORT datad (252:252:252) (277:277:277)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (380:380:380) (471:471:471)) + (PORT datad (246:246:246) (268:268:268)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[9\]) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (448:448:448)) + (PORT datad (320:320:320) (391:391:391)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a2) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1293:1293:1293) (1242:1242:1242)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (494:494:494)) + (PORT datab (379:379:379) (469:469:469)) + (PORT datac (363:363:363) (451:451:451)) + (PORT datad (339:339:339) (423:423:423)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a1) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1293:1293:1293) (1242:1242:1242)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (462:462:462)) + (PORT datab (980:980:980) (943:943:943)) + (PORT datac (340:340:340) (433:433:433)) + (PORT datad (1242:1242:1242) (1176:1176:1176)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a0) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1293:1293:1293) (1242:1242:1242)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (413:413:413)) + (PORT datac (296:296:296) (374:374:374)) + (PORT datad (498:498:498) (525:525:525)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity5) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1293:1293:1293) (1242:1242:1242)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datad (340:340:340) (417:417:417)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1293:1293:1293) (1242:1242:1242)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (533:533:533)) + (PORT datab (382:382:382) (471:471:471)) + (PORT datad (338:338:338) (415:415:415)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT asdata (1840:1840:1840) (1817:1817:1817)) + (PORT ena (1387:1387:1387) (1333:1333:1333)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (379:379:379) (469:469:469)) + (IOPATH datab combout (494:494:494) (496:496:496)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1588:1588:1588) (1477:1477:1477)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (392:392:392)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT asdata (761:761:761) (831:831:831)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT asdata (1290:1290:1290) (1255:1255:1255)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT asdata (1280:1280:1280) (1245:1245:1245)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT asdata (972:972:972) (990:990:990)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (869:869:869)) + (PORT datab (934:934:934) (890:890:890)) + (PORT datad (293:293:293) (362:362:362)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT datab (1832:1832:1832) (1682:1682:1682)) + (PORT datac (247:247:247) (278:278:278)) + (PORT datad (245:245:245) (267:267:267)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (4197:4197:4197) (4406:4406:4406)) + (PORT datab (1234:1234:1234) (1141:1141:1141)) + (PORT datac (1266:1266:1266) (1240:1240:1240)) + (PORT datad (882:882:882) (857:857:857)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~13) + (DELAY + (ABSOLUTE + (PORT datac (1338:1338:1338) (1323:1323:1323)) + (PORT datad (928:928:928) (924:924:924)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1364:1364:1364) (1359:1359:1359)) + (PORT datab (364:364:364) (459:459:459)) + (PORT datac (484:484:484) (458:458:458)) + (PORT datad (275:275:275) (297:297:297)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1313:1313:1313) (1290:1290:1290)) + (PORT datab (926:926:926) (902:902:902)) + (PORT datac (1179:1179:1179) (1102:1102:1102)) + (PORT datad (322:322:322) (392:392:392)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1311:1311:1311) (1288:1288:1288)) + (PORT datab (925:925:925) (900:900:900)) + (PORT datac (1182:1182:1182) (1106:1106:1106)) + (PORT datad (322:322:322) (392:392:392)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1310:1310:1310) (1286:1286:1286)) + (PORT datab (924:924:924) (899:899:899)) + (PORT datac (1184:1184:1184) (1108:1108:1108)) + (PORT datad (323:323:323) (393:393:393)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1310:1310:1310) (1286:1286:1286)) + (PORT datab (924:924:924) (899:899:899)) + (PORT datac (1183:1183:1183) (1108:1108:1108)) + (PORT datad (322:322:322) (393:393:393)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1309:1309:1309) (1285:1285:1285)) + (PORT datab (923:923:923) (898:898:898)) + (PORT datac (1185:1185:1185) (1109:1109:1109)) + (PORT datad (323:323:323) (393:393:393)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1274:1274:1274) (1194:1194:1194)) + (PORT datab (1308:1308:1308) (1219:1219:1219)) + (PORT datac (1626:1626:1626) (1583:1583:1583)) + (PORT datad (911:911:911) (907:907:907)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1274:1274:1274) (1194:1194:1194)) + (PORT datab (1307:1307:1307) (1219:1219:1219)) + (PORT datac (1625:1625:1625) (1582:1582:1582)) + (PORT datad (304:304:304) (377:377:377)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1676:1676:1676) (1642:1642:1642)) + (PORT datab (1308:1308:1308) (1219:1219:1219)) + (PORT datac (304:304:304) (389:389:389)) + (PORT datad (1202:1202:1202) (1134:1134:1134)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~14) + (DELAY + (ABSOLUTE + (PORT datac (1635:1635:1635) (1594:1594:1594)) + (PORT datad (306:306:306) (380:380:380)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1940:1940:1940) (1799:1799:1799)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (331:331:331) (409:409:409)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1588:1588:1588) (1477:1477:1477)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[8\]) + (DELAY + (ABSOLUTE + (PORT datad (320:320:320) (390:390:390)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0) + (DELAY + (ABSOLUTE + (PORT datad (239:239:239) (258:258:258)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0) + (DELAY + (ABSOLUTE + (PORT clk (1875:1875:1875) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1676:1676:1676) (1565:1565:1565)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~15) + (DELAY + (ABSOLUTE + (PORT datab (986:986:986) (971:971:971)) + (PORT datac (1344:1344:1344) (1330:1330:1330)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~11) + (DELAY + (ABSOLUTE + (PORT datac (1339:1339:1339) (1324:1324:1324)) + (PORT datad (887:887:887) (885:885:885)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~7) + (DELAY + (ABSOLUTE + (PORT datac (1352:1352:1352) (1339:1339:1339)) + (PORT datad (931:931:931) (921:921:921)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~5) + (DELAY + (ABSOLUTE + (PORT datac (1350:1350:1350) (1337:1337:1337)) + (PORT datad (944:944:944) (934:934:934)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~3) + (DELAY + (ABSOLUTE + (PORT datac (1627:1627:1627) (1584:1584:1584)) + (PORT datad (911:911:911) (908:908:908)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1940:1940:1940) (1799:1799:1799)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~9) + (DELAY + (ABSOLUTE + (PORT datac (1633:1633:1633) (1592:1592:1592)) + (PORT datad (305:305:305) (378:378:378)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1940:1940:1940) (1799:1799:1799)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (435:435:435)) + (PORT datac (1624:1624:1624) (1581:1581:1581)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1940:1940:1940) (1799:1799:1799)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1272:1272:1272) (1191:1191:1191)) + (PORT datab (1309:1309:1309) (1221:1221:1221)) + (PORT datac (1632:1632:1632) (1590:1590:1590)) + (PORT datad (305:305:305) (379:379:379)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~16) + (DELAY + (ABSOLUTE + (PORT datac (1622:1622:1622) (1578:1578:1578)) + (PORT datad (307:307:307) (381:381:381)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1940:1940:1940) (1799:1799:1799)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (438:438:438)) + (PORT datac (1632:1632:1632) (1591:1591:1591)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1940:1940:1940) (1799:1799:1799)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (440:440:440)) + (PORT datac (1634:1634:1634) (1593:1593:1593)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1940:1940:1940) (1799:1799:1799)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~6) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (907:907:907)) + (PORT datac (1349:1349:1349) (1336:1336:1336)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (911:911:911)) + (PORT datab (1178:1178:1178) (1103:1103:1103)) + (PORT datac (1342:1342:1342) (1328:1328:1328)) + (PORT datad (860:860:860) (819:819:819)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~4) + (DELAY + (ABSOLUTE + (PORT datac (1348:1348:1348) (1334:1334:1334)) + (PORT datad (305:305:305) (378:378:378)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~10) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (440:440:440)) + (PORT datac (1351:1351:1351) (1338:1338:1338)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~1) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (438:438:438)) + (PORT datab (1177:1177:1177) (1103:1103:1103)) + (PORT datac (1343:1343:1343) (1329:1329:1329)) + (PORT datad (860:860:860) (819:819:819)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~2) + (DELAY + (ABSOLUTE + (PORT datac (1341:1341:1341) (1326:1326:1326)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (328:328:328)) + (PORT datab (353:353:353) (440:440:440)) + (PORT datac (351:351:351) (471:471:471)) + (PORT datad (842:842:842) (786:786:786)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (1251:1251:1251) (1176:1176:1176)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|tx) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_min_1200mv_0c_fast.vo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_min_1200mv_0c_fast.vo new file mode 100644 index 0000000..0bcbc2e --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_min_1200mv_0c_fast.vo @@ -0,0 +1,24509 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:03:14" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module uart_sd ( + sys_clk, + sys_rst_n, + rx, + sd_miso, + sd_clk, + sd_cs_n, + sd_mosi, + tx); +input sys_clk; +input sys_rst_n; +input rx; +input sd_miso; +output sd_clk; +output sd_cs_n; +output sd_mosi; +output tx; + +// Design Ports Information +// sd_clk => Location: PIN_F8, I/O Standard: 2.5 V, Current Strength: Default +// sd_cs_n => Location: PIN_E7, I/O Standard: 2.5 V, Current Strength: Default +// sd_mosi => Location: PIN_F7, I/O Standard: 2.5 V, Current Strength: Default +// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default +// sd_miso => Location: PIN_E9, I/O Standard: 2.5 V, Current Strength: Default +// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("uart_sd_min_1200mv_0c_v_fast.sdo"); +// synopsys translate_on + +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ; +wire \uart_tx_inst|baud_cnt[2]~17_combout ; +wire \uart_tx_inst|baud_cnt[5]~23_combout ; +wire \uart_tx_inst|baud_cnt[10]~33_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ; +wire \data_rw_ctrl_inst|cnt_wait[5]~27_combout ; +wire \uart_rx_inst|Add1~4_combout ; +wire \uart_rx_inst|baud_cnt[4]~21_combout ; +wire \uart_rx_inst|baud_cnt[10]~33_combout ; +wire \data_rw_ctrl_inst|send_data_num[3]~18_combout ; +wire \data_rw_ctrl_inst|send_data_num[6]~24_combout ; +wire \data_rw_ctrl_inst|send_data_num[7]~27 ; +wire \data_rw_ctrl_inst|send_data_num[8]~29 ; +wire \data_rw_ctrl_inst|send_data_num[8]~28_combout ; +wire \data_rw_ctrl_inst|send_data_num[9]~31 ; +wire \data_rw_ctrl_inst|send_data_num[9]~30_combout ; +wire \data_rw_ctrl_inst|send_data_num[10]~33 ; +wire \data_rw_ctrl_inst|send_data_num[10]~32_combout ; +wire \data_rw_ctrl_inst|send_data_num[11]~34_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ; +wire \sd_ctrl_inst|sd_init_inst|Equal6~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux0~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~4_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~5_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~6_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~7_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux1~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~6_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~7_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~3_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~4_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~5_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~6_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~7_combout ; +wire \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~8_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~9_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~10_combout ; +wire \uart_tx_inst|always0~0_combout ; +wire \uart_tx_inst|Mux0~1_combout ; +wire \uart_tx_inst|Mux0~2_combout ; +wire \uart_tx_inst|Mux0~3_combout ; +wire \uart_tx_inst|Mux0~4_combout ; +wire \uart_tx_inst|Mux0~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal1~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector8~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector0~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal3~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector6~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal3~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal3~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal3~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ; +wire \sd_ctrl_inst|sd_write_inst|Selector2~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Add3~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ; +wire \uart_tx_inst|work_en~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ; +wire \uart_tx_inst|Add1~1_combout ; +wire \uart_tx_inst|bit_cnt[2]~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector3~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector3~1_combout ; +wire \data_rw_ctrl_inst|tx_flag~q ; +wire \uart_tx_inst|work_en~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~6_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~7_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~1_combout ; +wire \uart_rx_inst|always8~0_combout ; +wire \uart_rx_inst|rx_reg3~q ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ; +wire \uart_rx_inst|Equal2~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ; +wire \uart_rx_inst|rx_reg2~q ; +wire \data_rw_ctrl_inst|always3~2_combout ; +wire \uart_rx_inst|Equal1~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ; +wire \uart_rx_inst|rx_reg1~q ; +wire \uart_rx_inst|start_nedge~q ; +wire \uart_rx_inst|always3~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ; +wire \uart_rx_inst|rx_data[7]~0_combout ; +wire \uart_rx_inst|rx_reg1~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ; +wire \rx~input_o ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|tx_flag~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ; +wire \uart_rx_inst|po_data[1]~feeder_combout ; +wire \uart_rx_inst|rx_data[0]~feeder_combout ; +wire \uart_rx_inst|po_data[5]~feeder_combout ; +wire \uart_rx_inst|rx_data[4]~feeder_combout ; +wire \uart_rx_inst|po_data[6]~feeder_combout ; +wire \uart_rx_inst|rx_data[5]~feeder_combout ; +wire \uart_rx_inst|po_data[7]~feeder_combout ; +wire \uart_rx_inst|rx_data[6]~feeder_combout ; +wire \uart_rx_inst|po_data[3]~feeder_combout ; +wire \uart_rx_inst|rx_data[2]~feeder_combout ; +wire \uart_rx_inst|po_data[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ; +wire \uart_rx_inst|rx_reg2~feeder_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ; +wire \sd_miso~input_o ; +wire \sd_ctrl_inst|sd_init_inst|miso_dly~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal0~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_en~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal0~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ; +wire \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal3~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_en~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_en~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_en~q ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal1~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal2~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal2~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector0~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal0~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal0~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal0~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.IDLE~q ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.INIT_END~q ; +wire \sd_ctrl_inst|sd_init_inst|WideOr18~combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal5~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ; +wire \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal5~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal5~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector2~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector1~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector1~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector5~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector4~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector7~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector3~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector3~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ; +wire \sd_ctrl_inst|sd_init_inst|Selector15~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector15~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector15~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|init_end~q ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector1~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal2~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal2~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector3~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ; +wire \sd_ctrl_inst|sd_read_inst|Selector2~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector2~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Add3~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal9~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~11_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~9_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~13_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~15_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head_en~q ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|byte_head~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Equal6~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ; +wire \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|always3~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector4~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.RD_END~q ; +wire \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector0~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|Selector0~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|state.IDLE~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal1~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal1~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_en~q ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal4~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal4~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal4~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector2~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Add3~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Add3~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|always4~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector4~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~7_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~6_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~5_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal6~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~4_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|busy_data~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal6~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal6~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector5~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.WR_END~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector0~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cs_n~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cs_n~q ; +wire \sd_ctrl_inst|sd_write_inst|Selector0~1_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.IDLE~q ; +wire \data_rw_ctrl_inst|wr_busy_dly~feeder_combout ; +wire \data_rw_ctrl_inst|wr_busy_dly~q ; +wire \data_rw_ctrl_inst|wr_busy_fall~0_combout ; +wire \data_rw_ctrl_inst|rd_en~q ; +wire \sd_ctrl_inst|sd_read_inst|cs_n~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|cs_n~q ; +wire \sd_ctrl_inst|sd_cs_n~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal6~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~0_combout ; +wire \sd_ctrl_inst|sd_init_inst|Equal6~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~2_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector13~3_combout ; +wire \sd_ctrl_inst|sd_init_inst|cs_n~q ; +wire \sd_ctrl_inst|sd_cs_n~1_combout ; +wire \sd_ctrl_inst|sd_init_inst|Selector14~11_combout ; +wire \sd_ctrl_inst|sd_init_inst|mosi~q ; +wire \sd_ctrl_inst|sd_read_inst|mosi~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|mosi~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|mosi~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|mosi~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ; +wire \uart_rx_inst|Add1~1 ; +wire \uart_rx_inst|Add1~3 ; +wire \uart_rx_inst|Add1~5 ; +wire \uart_rx_inst|Add1~6_combout ; +wire \uart_rx_inst|bit_cnt~0_combout ; +wire \uart_rx_inst|Add1~0_combout ; +wire \uart_rx_inst|bit_cnt~1_combout ; +wire \uart_rx_inst|Add1~2_combout ; +wire \uart_rx_inst|always4~0_combout ; +wire \uart_rx_inst|baud_cnt[0]~13_combout ; +wire \uart_rx_inst|Equal1~0_combout ; +wire \uart_rx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|baud_cnt[2]~17_combout ; +wire \uart_rx_inst|Equal1~1_combout ; +wire \uart_rx_inst|Equal1~3_combout ; +wire \uart_rx_inst|work_en~0_combout ; +wire \uart_rx_inst|work_en~q ; +wire \uart_rx_inst|always5~0_combout ; +wire \uart_rx_inst|baud_cnt[0]~14 ; +wire \uart_rx_inst|baud_cnt[1]~15_combout ; +wire \uart_rx_inst|baud_cnt[1]~16 ; +wire \uart_rx_inst|baud_cnt[2]~18 ; +wire \uart_rx_inst|baud_cnt[3]~19_combout ; +wire \uart_rx_inst|baud_cnt[3]~20 ; +wire \uart_rx_inst|baud_cnt[4]~22 ; +wire \uart_rx_inst|baud_cnt[5]~24 ; +wire \uart_rx_inst|baud_cnt[6]~25_combout ; +wire \uart_rx_inst|baud_cnt[6]~26 ; +wire \uart_rx_inst|baud_cnt[7]~27_combout ; +wire \uart_rx_inst|baud_cnt[7]~28 ; +wire \uart_rx_inst|baud_cnt[8]~29_combout ; +wire \uart_rx_inst|baud_cnt[8]~30 ; +wire \uart_rx_inst|baud_cnt[9]~31_combout ; +wire \uart_rx_inst|baud_cnt[9]~32 ; +wire \uart_rx_inst|baud_cnt[10]~34 ; +wire \uart_rx_inst|baud_cnt[11]~35_combout ; +wire \uart_rx_inst|baud_cnt[11]~36 ; +wire \uart_rx_inst|baud_cnt[12]~37_combout ; +wire \uart_rx_inst|Equal2~1_combout ; +wire \uart_rx_inst|Equal2~2_combout ; +wire \uart_rx_inst|bit_flag~q ; +wire \uart_rx_inst|always4~1_combout ; +wire \uart_rx_inst|rx_flag~q ; +wire \uart_rx_inst|po_flag~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ; +wire \sd_ctrl_inst|comb~1_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ; +wire \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ; +wire \sd_ctrl_inst|comb~0_combout ; +wire \sd_ctrl_inst|comb~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector1~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Selector1~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ; +wire \sd_ctrl_inst|sd_write_inst|Mux0~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ; +wire \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~2_combout ; +wire \sd_ctrl_inst|sd_write_inst|Equal3~0_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~3_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~4_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~5_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~8_combout ; +wire \sd_ctrl_inst|sd_write_inst|mosi~q ; +wire \sd_ctrl_inst|sd_mosi~0_combout ; +wire \sd_ctrl_inst|sd_mosi~1_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \uart_tx_inst|baud_cnt[0]~13_combout ; +wire \uart_tx_inst|Equal1~0_combout ; +wire \uart_tx_inst|Equal1~1_combout ; +wire \uart_tx_inst|baud_cnt[4]~21_combout ; +wire \uart_tx_inst|Equal1~2_combout ; +wire \uart_tx_inst|Equal1~3_combout ; +wire \uart_tx_inst|always1~0_combout ; +wire \uart_tx_inst|baud_cnt[0]~14 ; +wire \uart_tx_inst|baud_cnt[1]~15_combout ; +wire \uart_tx_inst|baud_cnt[1]~16 ; +wire \uart_tx_inst|baud_cnt[2]~18 ; +wire \uart_tx_inst|baud_cnt[3]~19_combout ; +wire \uart_tx_inst|baud_cnt[3]~20 ; +wire \uart_tx_inst|baud_cnt[4]~22 ; +wire \uart_tx_inst|baud_cnt[5]~24 ; +wire \uart_tx_inst|baud_cnt[6]~25_combout ; +wire \uart_tx_inst|baud_cnt[6]~26 ; +wire \uart_tx_inst|baud_cnt[7]~27_combout ; +wire \uart_tx_inst|baud_cnt[7]~28 ; +wire \uart_tx_inst|baud_cnt[8]~29_combout ; +wire \uart_tx_inst|baud_cnt[8]~30 ; +wire \uart_tx_inst|baud_cnt[9]~31_combout ; +wire \uart_tx_inst|baud_cnt[9]~32 ; +wire \uart_tx_inst|baud_cnt[10]~34 ; +wire \uart_tx_inst|baud_cnt[11]~35_combout ; +wire \uart_tx_inst|baud_cnt[11]~36 ; +wire \uart_tx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal2~0_combout ; +wire \uart_tx_inst|Equal2~1_combout ; +wire \uart_tx_inst|bit_flag~q ; +wire \uart_tx_inst|always3~0_combout ; +wire \uart_tx_inst|always0~1_combout ; +wire \uart_tx_inst|bit_cnt[0]~5_combout ; +wire \uart_tx_inst|bit_cnt[1]~4_combout ; +wire \uart_tx_inst|Add1~0_combout ; +wire \uart_tx_inst|bit_cnt[3]~2_combout ; +wire \data_rw_ctrl_inst|cnt_wait[0]~16_combout ; +wire \data_rw_ctrl_inst|cnt_wait[3]~23 ; +wire \data_rw_ctrl_inst|cnt_wait[4]~24_combout ; +wire \data_rw_ctrl_inst|Equal3~0_combout ; +wire \data_rw_ctrl_inst|rd_busy_dly~q ; +wire \data_rw_ctrl_inst|send_data_num[0]~12_combout ; +wire \data_rw_ctrl_inst|send_data_num[0]~13 ; +wire \data_rw_ctrl_inst|send_data_num[1]~14_combout ; +wire \data_rw_ctrl_inst|send_data_num[1]~15 ; +wire \data_rw_ctrl_inst|send_data_num[2]~16_combout ; +wire \data_rw_ctrl_inst|always3~0_combout ; +wire \data_rw_ctrl_inst|send_data_num[2]~17 ; +wire \data_rw_ctrl_inst|send_data_num[3]~19 ; +wire \data_rw_ctrl_inst|send_data_num[4]~20_combout ; +wire \data_rw_ctrl_inst|send_data_num[4]~21 ; +wire \data_rw_ctrl_inst|send_data_num[5]~23 ; +wire \data_rw_ctrl_inst|send_data_num[6]~25 ; +wire \data_rw_ctrl_inst|send_data_num[7]~26_combout ; +wire \data_rw_ctrl_inst|send_data_num[5]~22_combout ; +wire \data_rw_ctrl_inst|always3~1_combout ; +wire \data_rw_ctrl_inst|always3~3_combout ; +wire \data_rw_ctrl_inst|send_data_en~0_combout ; +wire \data_rw_ctrl_inst|send_data_en~q ; +wire \data_rw_ctrl_inst|Equal3~1_combout ; +wire \data_rw_ctrl_inst|cnt_wait[13]~26_combout ; +wire \data_rw_ctrl_inst|cnt_wait[0]~17 ; +wire \data_rw_ctrl_inst|cnt_wait[1]~18_combout ; +wire \data_rw_ctrl_inst|cnt_wait[1]~19 ; +wire \data_rw_ctrl_inst|cnt_wait[2]~20_combout ; +wire \data_rw_ctrl_inst|cnt_wait[2]~21 ; +wire \data_rw_ctrl_inst|cnt_wait[3]~22_combout ; +wire \data_rw_ctrl_inst|Equal2~3_combout ; +wire \data_rw_ctrl_inst|cnt_wait[4]~25 ; +wire \data_rw_ctrl_inst|cnt_wait[5]~28 ; +wire \data_rw_ctrl_inst|cnt_wait[6]~30 ; +wire \data_rw_ctrl_inst|cnt_wait[7]~31_combout ; +wire \data_rw_ctrl_inst|cnt_wait[7]~32 ; +wire \data_rw_ctrl_inst|cnt_wait[8]~33_combout ; +wire \data_rw_ctrl_inst|cnt_wait[8]~34 ; +wire \data_rw_ctrl_inst|cnt_wait[9]~35_combout ; +wire \data_rw_ctrl_inst|cnt_wait[9]~36 ; +wire \data_rw_ctrl_inst|cnt_wait[10]~37_combout ; +wire \data_rw_ctrl_inst|cnt_wait[10]~38 ; +wire \data_rw_ctrl_inst|cnt_wait[11]~40 ; +wire \data_rw_ctrl_inst|cnt_wait[12]~41_combout ; +wire \data_rw_ctrl_inst|cnt_wait[12]~42 ; +wire \data_rw_ctrl_inst|cnt_wait[13]~44 ; +wire \data_rw_ctrl_inst|cnt_wait[14]~45_combout ; +wire \data_rw_ctrl_inst|cnt_wait[14]~46 ; +wire \data_rw_ctrl_inst|cnt_wait[15]~47_combout ; +wire \data_rw_ctrl_inst|cnt_wait[6]~29_combout ; +wire \data_rw_ctrl_inst|Equal2~0_combout ; +wire \data_rw_ctrl_inst|cnt_wait[13]~43_combout ; +wire \data_rw_ctrl_inst|cnt_wait[11]~39_combout ; +wire \data_rw_ctrl_inst|Equal2~1_combout ; +wire \data_rw_ctrl_inst|Equal2~2_combout ; +wire \data_rw_ctrl_inst|Equal2~4_combout ; +wire \data_rw_ctrl_inst|rd_fifo_rd_en~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_en~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~13_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~14_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ; +wire \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~15_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~11_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~7_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~5_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~9_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~0_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~16_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~12_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~8_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~6_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~4_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~10_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ; +wire \sd_ctrl_inst|sd_read_inst|rd_data~2_combout ; +wire \uart_tx_inst|Mux0~0_combout ; +wire \uart_tx_inst|tx~0_combout ; +wire \uart_tx_inst|tx~q ; +wire [3:0] \sd_ctrl_inst|sd_write_inst|cnt_data_bit ; +wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit ; +wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data_reg ; +wire [7:0] \sd_ctrl_inst|sd_read_inst|cnt_ack_bit ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_ack_bit ; +wire [12:0] \uart_tx_inst|baud_cnt ; +wire [15:0] \sd_ctrl_inst|sd_read_inst|rd_data ; +wire [2:0] \sd_ctrl_inst|sd_read_inst|cnt_end ; +wire [3:0] \uart_tx_inst|bit_cnt ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|ack_data ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|busy_data ; +wire [3:0] \sd_ctrl_inst|sd_read_inst|cnt_data_bit ; +wire [7:0] \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit ; +wire [15:0] \sd_ctrl_inst|sd_read_inst|byte_head ; +wire [11:0] \sd_ctrl_inst|sd_read_inst|cnt_data_num ; +wire [7:0] \sd_ctrl_inst|sd_read_inst|ack_data ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \uart_rx_inst|rx_data ; +wire [7:0] \uart_rx_inst|po_data ; +wire [3:0] \uart_rx_inst|bit_cnt ; +wire [12:0] \uart_rx_inst|baud_cnt ; +wire [11:0] \data_rw_ctrl_inst|send_data_num ; +wire [15:0] \data_rw_ctrl_inst|cnt_wait ; +wire [10:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ; +wire [8:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ; +wire [2:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a ; +wire [15:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a ; +wire [9:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b ; +wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a ; +wire [2:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a ; +wire [7:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a ; +wire [9:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a ; +wire [8:0] \sd_ctrl_inst|sd_init_inst|cnt_wait ; +wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit ; +wire [7:0] \sd_ctrl_inst|sd_init_inst|cnt_ack_bit ; +wire [39:0] \sd_ctrl_inst|sd_init_inst|ack_data ; +wire [2:0] \sd_ctrl_inst|sd_write_inst|cnt_end ; +wire [11:0] \sd_ctrl_inst|sd_write_inst|cnt_data_num ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; +wire [17:0] \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; +wire [8:0] \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [9]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [10]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [11]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [12]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [13]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [14]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [15]; +assign \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [16]; + +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 7; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "10000"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 3334; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0] $ (VCC))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # (GND))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .lut_mask = 16'h66DD; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y22_N19 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N13 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N7 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N11 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N13 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y13_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y16_N13 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X13_Y13_N0 +cycloneive_ram_block \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({gnd,\uart_rx_inst|po_data [7],\uart_rx_inst|po_data [6],\uart_rx_inst|po_data [5],\uart_rx_inst|po_data [4],\uart_rx_inst|po_data [3],\uart_rx_inst|po_data [2],\uart_rx_inst|po_data [1],\uart_rx_inst|po_data [0]}), + .portaaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2], +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(18'b000000000000000000), + .portbaddr({\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8],\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ,\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q , +\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_wr_data:fifo_wr_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_uqf1:auto_generated|altsyncram_3011:fifo_ram|ALTSYNCRAM"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 8; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 9; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 18; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 511; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 512; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: M9K_X25_Y27_N0 +cycloneive_ram_block \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({gnd,\sd_ctrl_inst|sd_read_inst|rd_data [15],\sd_ctrl_inst|sd_read_inst|rd_data [14],\sd_ctrl_inst|sd_read_inst|rd_data [13],\sd_ctrl_inst|sd_read_inst|rd_data [12],\sd_ctrl_inst|sd_read_inst|rd_data [11],\sd_ctrl_inst|sd_read_inst|rd_data [10],\sd_ctrl_inst|sd_read_inst|rd_data [9], +\sd_ctrl_inst|sd_read_inst|rd_data [8],gnd,\sd_ctrl_inst|sd_read_inst|rd_data [7],\sd_ctrl_inst|sd_read_inst|rd_data [6],\sd_ctrl_inst|sd_read_inst|rd_data [5],\sd_ctrl_inst|sd_read_inst|rd_data [4],\sd_ctrl_inst|sd_read_inst|rd_data [3],\sd_ctrl_inst|sd_read_inst|rd_data [2], +\sd_ctrl_inst|sd_read_inst|rd_data [1],\sd_ctrl_inst|sd_read_inst|rd_data [0]}), + .portaaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1], +\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0],\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 8; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "data_rw_ctrl:data_rw_ctrl_inst|fifo_rd_data:fifo_rd_data_inst|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_h0f1:auto_generated|altsyncram_4011:fifo_ram|ALTSYNCRAM"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 9; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 18; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 511; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 512; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "none"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 8; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: FF_X14_Y25_N11 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N23 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N25 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N27 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N11 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 )) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N25 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y16_N27 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y23_N11 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y23_N7 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [3])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~20 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h55AA; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N13 +dffeas \uart_tx_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y26_N7 +dffeas \uart_tx_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y26_N23 +dffeas \uart_tx_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [9])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~29 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~33 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout = \sd_ctrl_inst|sd_read_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~35 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout = \sd_ctrl_inst|sd_init_inst|cnt_wait [0] $ (VCC) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .lut_mask = 16'h55AA; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout = \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N6 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) +// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[1]~16 ), + .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_tx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N12 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[4]~22 ), + .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_tx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N22 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) +// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[9]~32 ), + .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_tx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N11 +dffeas \data_rw_ctrl_inst|cnt_wait[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q $ (GND) +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT = CARRY(!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .cout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hAA55; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[5]~27 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[5]~27_combout = (\data_rw_ctrl_inst|cnt_wait [5] & (!\data_rw_ctrl_inst|cnt_wait[4]~25 )) # (!\data_rw_ctrl_inst|cnt_wait [5] & ((\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[5]~28 = CARRY((!\data_rw_ctrl_inst|cnt_wait[4]~25 ) # (!\data_rw_ctrl_inst|cnt_wait [5])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[4]~25 ), + .combout(\data_rw_ctrl_inst|cnt_wait[5]~27_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[5]~28 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[5]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N12 +cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( +// Equation(s): +// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) +// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) + + .dataa(\uart_rx_inst|bit_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~3 ), + .combout(\uart_rx_inst|Add1~4_combout ), + .cout(\uart_rx_inst|Add1~5 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N11 +dffeas \uart_rx_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y16_N23 +dffeas \uart_rx_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N7 +dffeas \data_rw_ctrl_inst|send_data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[3]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N13 +dffeas \data_rw_ctrl_inst|send_data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[6]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N17 +dffeas \data_rw_ctrl_inst|send_data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[8]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N19 +dffeas \data_rw_ctrl_inst|send_data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[9]~30_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N21 +dffeas \data_rw_ctrl_inst|send_data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[10]~32_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[10] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N23 +dffeas \data_rw_ctrl_inst|send_data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[11]~34_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [11]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[11] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N10 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) +// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[3]~20 ), + .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_rx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N22 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) +// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[9]~32 ), + .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_rx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[3]~18 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[3]~18_combout = (\data_rw_ctrl_inst|send_data_num [3] & (!\data_rw_ctrl_inst|send_data_num[2]~17 )) # (!\data_rw_ctrl_inst|send_data_num [3] & ((\data_rw_ctrl_inst|send_data_num[2]~17 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[3]~19 = CARRY((!\data_rw_ctrl_inst|send_data_num[2]~17 ) # (!\data_rw_ctrl_inst|send_data_num [3])) + + .dataa(\data_rw_ctrl_inst|send_data_num [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[2]~17 ), + .combout(\data_rw_ctrl_inst|send_data_num[3]~18_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[3]~19 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[3]~18 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|send_data_num[3]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[6]~24 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[6]~24_combout = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num[5]~23 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [6] & (!\data_rw_ctrl_inst|send_data_num[5]~23 & VCC)) +// \data_rw_ctrl_inst|send_data_num[6]~25 = CARRY((\data_rw_ctrl_inst|send_data_num [6] & !\data_rw_ctrl_inst|send_data_num[5]~23 )) + + .dataa(\data_rw_ctrl_inst|send_data_num [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[5]~23 ), + .combout(\data_rw_ctrl_inst|send_data_num[6]~24_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[6]~25 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[6]~24 .lut_mask = 16'hA50A; +defparam \data_rw_ctrl_inst|send_data_num[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[7]~26 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[7]~26_combout = (\data_rw_ctrl_inst|send_data_num [7] & (!\data_rw_ctrl_inst|send_data_num[6]~25 )) # (!\data_rw_ctrl_inst|send_data_num [7] & ((\data_rw_ctrl_inst|send_data_num[6]~25 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[7]~27 = CARRY((!\data_rw_ctrl_inst|send_data_num[6]~25 ) # (!\data_rw_ctrl_inst|send_data_num [7])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [7]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[6]~25 ), + .combout(\data_rw_ctrl_inst|send_data_num[7]~26_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[7]~27 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[7]~26 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|send_data_num[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[8]~28 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[8]~28_combout = (\data_rw_ctrl_inst|send_data_num [8] & (\data_rw_ctrl_inst|send_data_num[7]~27 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num[7]~27 & VCC)) +// \data_rw_ctrl_inst|send_data_num[8]~29 = CARRY((\data_rw_ctrl_inst|send_data_num [8] & !\data_rw_ctrl_inst|send_data_num[7]~27 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [8]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[7]~27 ), + .combout(\data_rw_ctrl_inst|send_data_num[8]~28_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[8]~29 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[8]~28 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[8]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[9]~30 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[9]~30_combout = (\data_rw_ctrl_inst|send_data_num [9] & (!\data_rw_ctrl_inst|send_data_num[8]~29 )) # (!\data_rw_ctrl_inst|send_data_num [9] & ((\data_rw_ctrl_inst|send_data_num[8]~29 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[9]~31 = CARRY((!\data_rw_ctrl_inst|send_data_num[8]~29 ) # (!\data_rw_ctrl_inst|send_data_num [9])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [9]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[8]~29 ), + .combout(\data_rw_ctrl_inst|send_data_num[9]~30_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[9]~31 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[9]~30 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|send_data_num[9]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[10]~32 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[10]~32_combout = (\data_rw_ctrl_inst|send_data_num [10] & (\data_rw_ctrl_inst|send_data_num[9]~31 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num[9]~31 & VCC)) +// \data_rw_ctrl_inst|send_data_num[10]~33 = CARRY((\data_rw_ctrl_inst|send_data_num [10] & !\data_rw_ctrl_inst|send_data_num[9]~31 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [10]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[9]~31 ), + .combout(\data_rw_ctrl_inst|send_data_num[10]~32_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[10]~33 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[10]~32 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[10]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[11]~34 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[11]~34_combout = \data_rw_ctrl_inst|send_data_num [11] $ (\data_rw_ctrl_inst|send_data_num[10]~33 ) + + .dataa(\data_rw_ctrl_inst|send_data_num [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|send_data_num[10]~33 ), + .combout(\data_rw_ctrl_inst|send_data_num[11]~34_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[11]~34 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|send_data_num[11]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y23_N27 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_end [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~0_combout = (\sd_ctrl_inst|sd_init_inst|init_end~q & \data_rw_ctrl_inst|rd_en~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datad(\data_rw_ctrl_inst|rd_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal6~0_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .lut_mask = 16'h0303; +defparam \sd_ctrl_inst|sd_init_inst|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [1]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [4]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_write_inst|always4~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]), + .datad(\sd_ctrl_inst|sd_write_inst|always4~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~1 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_write_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_write_inst|always4~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_write_inst|mosi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~1_combout = (\sd_ctrl_inst|sd_write_inst|mosi~0_combout & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .lut_mask = 16'h0002; +defparam \sd_ctrl_inst|sd_write_inst|mosi~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux0~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & +// (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .lut_mask = 16'h0026; +defparam \sd_ctrl_inst|sd_write_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]) # ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5])))) # +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .lut_mask = 16'hB9A8; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~1_combout = (\sd_ctrl_inst|sd_write_inst|Mux1~0_combout & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]) # ((!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~0_combout & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]), + .datab(\sd_ctrl_inst|sd_write_inst|Mux1~0_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [9]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .lut_mask = 16'hB8CC; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~2_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b +// [14]))))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [10]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [14]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .lut_mask = 16'hEE30; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~3_combout = (\sd_ctrl_inst|sd_write_inst|Mux1~2_combout & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]))) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~2_combout & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux1~2_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .lut_mask = 16'hEA62; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~4_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b +// [15])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [15]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [11]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .lut_mask = 16'hDC98; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~5_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]))) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~4_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\sd_ctrl_inst|sd_write_inst|Mux1~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_write_inst|Mux1~4_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .lut_mask = 16'hF838; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~6_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0])))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & +// ((\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|Mux1~5_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux1~5_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_write_inst|Mux1~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .lut_mask = 16'hF2C2; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~7_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) # +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12] & !\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [12]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .lut_mask = 16'hCCB8; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux1~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux1~8_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & ((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0])) # +// (!\sd_ctrl_inst|sd_write_inst|Mux1~7_combout & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]))))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (((\sd_ctrl_inst|sd_write_inst|Mux1~7_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [8]), + .datad(\sd_ctrl_inst|sd_write_inst|Mux1~7_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .lut_mask = 16'hBBC0; +defparam \sd_ctrl_inst|sd_write_inst|Mux1~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~6_combout = (\sd_ctrl_inst|sd_write_inst|Mux1~6_combout & (((\sd_ctrl_inst|sd_write_inst|Mux1~8_combout )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) # (!\sd_ctrl_inst|sd_write_inst|Mux1~6_combout & +// (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1] & ((\sd_ctrl_inst|sd_write_inst|Mux1~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux1~6_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .datac(\sd_ctrl_inst|sd_write_inst|Mux1~8_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|Mux1~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .lut_mask = 16'hE6A2; +defparam \sd_ctrl_inst|sd_write_inst|mosi~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~7_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]) # ((\sd_ctrl_inst|sd_write_inst|mosi~0_combout & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_write_inst|mosi~6_combout )) # +// (!\sd_ctrl_inst|sd_write_inst|mosi~0_combout & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]) # (\sd_ctrl_inst|sd_write_inst|mosi~6_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .datad(\sd_ctrl_inst|sd_write_inst|mosi~6_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .lut_mask = 16'hFDF4; +defparam \sd_ctrl_inst|sd_write_inst|mosi~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~1_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .lut_mask = 16'h1906; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~2_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & +// (\sd_ctrl_inst|sd_init_inst|Selector14~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .lut_mask = 16'h5044; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr14~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|WideOr14~0_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & +// ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .lut_mask = 16'h9998; +defparam \sd_ctrl_inst|sd_init_inst|WideOr14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~3_combout = ((\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|WideOr14~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .lut_mask = 16'h0CFF; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~4_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] & +// (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .lut_mask = 16'h11E0; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~5_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & !\sd_ctrl_inst|sd_init_inst|Selector14~4_combout )) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|Selector14~4_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~4_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .lut_mask = 16'h0108; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~6_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] $ (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .lut_mask = 16'h0902; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~7_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~6_combout & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~6_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .lut_mask = 16'h8100; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr12~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|WideOr12~0_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2] $ (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))))) # +// (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0])))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .lut_mask = 16'h5F60; +defparam \sd_ctrl_inst|sd_init_inst|WideOr12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~8_combout = ((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout & \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]))) # (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_init_inst|WideOr12~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .lut_mask = 16'h10FF; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~9_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~5_combout & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # ((\sd_ctrl_inst|sd_init_inst|Selector14~8_combout )))) # +// (!\sd_ctrl_inst|sd_init_inst|Selector14~5_combout & (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q & ((\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector14~8_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector14~5_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~7_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector14~8_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .lut_mask = 16'hA8FC; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~10_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~9_combout & (\sd_ctrl_inst|sd_init_inst|Selector14~3_combout & ((\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ) # +// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~9_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector14~2_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .lut_mask = 16'hC400; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N15 +dffeas \uart_tx_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[2]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N10 +cycloneive_lcell_comb \uart_tx_inst|always0~0 ( +// Equation(s): +// \uart_tx_inst|always0~0_combout = (!\uart_tx_inst|bit_cnt [2] & !\uart_tx_inst|bit_cnt [1]) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~0 .lut_mask = 16'h000F; +defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N30 +cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( +// Equation(s): +// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b +// [4]))) # (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [3]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [4]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hF2C2; +defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N24 +cycloneive_lcell_comb \uart_tx_inst|Mux0~2 ( +// Equation(s): +// \uart_tx_inst|Mux0~2_combout = (\uart_tx_inst|Mux0~1_combout & (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6])) # (!\uart_tx_inst|bit_cnt [1]))) # (!\uart_tx_inst|Mux0~1_combout & +// (\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]))) + + .dataa(\uart_tx_inst|Mux0~1_combout ), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [6]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~2 .lut_mask = 16'hEA62; +defparam \uart_tx_inst|Mux0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N26 +cycloneive_lcell_comb \uart_tx_inst|Mux0~3 ( +// Equation(s): +// \uart_tx_inst|Mux0~3_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2])) # (!\uart_tx_inst|bit_cnt [1] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]))))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [2]), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [0]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~3 .lut_mask = 16'h88C0; +defparam \uart_tx_inst|Mux0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N28 +cycloneive_lcell_comb \uart_tx_inst|Mux0~4 ( +// Equation(s): +// \uart_tx_inst|Mux0~4_combout = (!\uart_tx_inst|bit_cnt [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1] & \uart_tx_inst|bit_cnt [1])) + + .dataa(gnd), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [1]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~4 .lut_mask = 16'h3000; +defparam \uart_tx_inst|Mux0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N22 +cycloneive_lcell_comb \uart_tx_inst|Mux0~5 ( +// Equation(s): +// \uart_tx_inst|Mux0~5_combout = (\uart_tx_inst|bit_cnt [2] & (((\uart_tx_inst|Mux0~2_combout )))) # (!\uart_tx_inst|bit_cnt [2] & ((\uart_tx_inst|Mux0~3_combout ) # ((\uart_tx_inst|Mux0~4_combout )))) + + .dataa(\uart_tx_inst|Mux0~3_combout ), + .datab(\uart_tx_inst|Mux0~4_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|Mux0~2_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~5 .lut_mask = 16'hFE0E; +defparam \uart_tx_inst|Mux0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_end~0_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q & (\sd_ctrl_inst|sd_read_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0]))))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [2]), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_end~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .lut_mask = 16'h7800; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & \sd_ctrl_inst|sd_read_inst|always3~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datad(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~1 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_read_inst|always3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N7 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~2_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [10] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [9])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [10]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [11]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~2 .lut_mask = 16'h0003; +defparam \sd_ctrl_inst|sd_read_inst|always3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .lut_mask = 16'hC33C; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .lut_mask = 16'hC33C; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal1~0_combout = (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_init_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector8~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector8~0_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [32] & (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout & (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|sd_init_inst|Selector8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector0~0_combout = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q & (\sd_ctrl_inst|sd_init_inst|Equal5~2_combout & ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q & +// ((\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout & \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .lut_mask = 16'hDC50; +defparam \sd_ctrl_inst|sd_init_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal3~0_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [10] & (!\sd_ctrl_inst|sd_init_inst|ack_data [9] & (!\sd_ctrl_inst|sd_init_inst|ack_data [11] & \sd_ctrl_inst|sd_init_inst|ack_data [8]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [10]), + .datab(\sd_ctrl_inst|sd_init_inst|ack_data [9]), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [11]), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_init_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .lut_mask = 16'hFC00; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~1_combout = (\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & ((\sd_ctrl_inst|sd_init_inst|ack_data [32]) # ((!\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_init_inst|Equal2~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .lut_mask = 16'hB0F0; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # +// (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & ((!\sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .lut_mask = 16'hA0EC; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector6~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector6~3_combout = (\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & ((\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ) # (\sd_ctrl_inst|sd_init_inst|Selector6~1_combout +// )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector6~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector6~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector6~1_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .lut_mask = 16'hFECC; +defparam \sd_ctrl_inst|sd_init_inst|Selector6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~1_combout = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]) # ((!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .lut_mask = 16'hBF00; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal3~1_combout = (!\sd_ctrl_inst|sd_read_inst|ack_data [0] & (!\sd_ctrl_inst|sd_read_inst|ack_data [1] & (!\sd_ctrl_inst|sd_read_inst|ack_data [3] & !\sd_ctrl_inst|sd_read_inst|ack_data [2]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|ack_data [0]), + .datab(\sd_ctrl_inst|sd_read_inst|ack_data [1]), + .datac(\sd_ctrl_inst|sd_read_inst|ack_data [3]), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal3~1_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [6]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [7]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .lut_mask = 16'h0002; +defparam \sd_ctrl_inst|sd_write_inst|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal3~2_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|Equal3~1_combout & \sd_ctrl_inst|sd_write_inst|Equal3~0_combout )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|Equal3~1_combout ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .lut_mask = 16'h8800; +defparam \sd_ctrl_inst|sd_write_inst|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N13 +dffeas \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector2~0_combout = (\sd_ctrl_inst|sd_write_inst|Equal1~1_combout & (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout & \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_write_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Add3~0_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .lut_mask = 16'h78F0; +defparam \sd_ctrl_inst|sd_write_inst|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y14_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEDB7; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y14_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [4]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y15_N17 +dffeas \uart_rx_inst|po_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [9]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y15_N19 +dffeas \uart_rx_inst|po_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N21 +dffeas \uart_rx_inst|po_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N15 +dffeas \uart_rx_inst|po_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N9 +dffeas \uart_rx_inst|po_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N27 +dffeas \uart_rx_inst|po_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N13 +dffeas \uart_rx_inst|po_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N31 +dffeas \uart_rx_inst|po_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y27_N21 +dffeas \uart_tx_inst|work_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_tx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [7]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N6 +cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( +// Equation(s): +// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(gnd), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h3CF0; +defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N14 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~3 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[2]~3_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) + + .dataa(\uart_tx_inst|Add1~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2]~3 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N11 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y25_N31 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y24_N15 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~1_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head [0] & (\sd_ctrl_inst|sd_read_inst|byte_head [2] & (\sd_ctrl_inst|sd_read_inst|byte_head [1] & \sd_ctrl_inst|sd_read_inst|byte_head [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [2]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .lut_mask = 16'h000A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector3~0_combout = (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q & ((!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .lut_mask = 16'h3F00; +defparam \sd_ctrl_inst|sd_write_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector3~1_combout = (\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_write_inst|Equal3~2_combout & \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q )) + + .dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Selector3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .lut_mask = 16'hFFA0; +defparam \sd_ctrl_inst|sd_write_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y14_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y14_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y15_N1 +dffeas \uart_rx_inst|rx_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N11 +dffeas \uart_rx_inst|rx_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N29 +dffeas \uart_rx_inst|rx_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N23 +dffeas \uart_rx_inst|rx_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y16_N27 +dffeas \uart_rx_inst|rx_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[7]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N25 +dffeas \uart_rx_inst|rx_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N3 +dffeas \uart_rx_inst|rx_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y15_N5 +dffeas \uart_rx_inst|rx_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y27_N13 +dffeas \data_rw_ctrl_inst|tx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|tx_flag~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|tx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|tx_flag .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|tx_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N20 +cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( +// Equation(s): +// \uart_tx_inst|work_en~0_combout = (\data_rw_ctrl_inst|tx_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) + + .dataa(\data_rw_ctrl_inst|tx_flag~q ), + .datab(gnd), + .datac(\uart_tx_inst|work_en~q ), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hAAFA; +defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y28_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N1 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y27_N27 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y27_N23 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y27_N31 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~4_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [2]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [2]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~5_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [1]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [1]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~6_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [0] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~7_combout = (\sd_miso~input_o & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_miso~input_o ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_en~0_combout = (!\sd_miso~input_o & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q & \sd_ctrl_inst|sd_init_inst|miso_dly~q ))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .datac(\sd_ctrl_inst|sd_write_inst|state.CMD24_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_write_inst|ack_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_en~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & \sd_ctrl_inst|sd_write_inst|ack_en~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|ack_en~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .lut_mask = 16'h0100; +defparam \sd_ctrl_inst|sd_write_inst|ack_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N13 +dffeas \uart_rx_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N20 +cycloneive_lcell_comb \uart_rx_inst|always8~0 ( +// Equation(s): +// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always8~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always8~0 .lut_mask = 16'h8282; +defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N31 +dffeas \uart_rx_inst|rx_reg3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg3 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & !\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y16_N8 +cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( +// Equation(s): +// \uart_rx_inst|Equal2~0_combout = (!\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt [2] & \uart_rx_inst|baud_cnt [3]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h0400; +defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y10_N1 +dffeas \uart_rx_inst|rx_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~2 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~2_combout = (\data_rw_ctrl_inst|send_data_num [8] & (!\data_rw_ctrl_inst|send_data_num [10] & (!\data_rw_ctrl_inst|send_data_num [11] & !\data_rw_ctrl_inst|send_data_num [9]))) + + .dataa(\data_rw_ctrl_inst|send_data_num [8]), + .datab(\data_rw_ctrl_inst|send_data_num [10]), + .datac(\data_rw_ctrl_inst|send_data_num [11]), + .datad(\data_rw_ctrl_inst|send_data_num [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~2 .lut_mask = 16'h0002; +defparam \data_rw_ctrl_inst|always3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N30 +cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( +// Equation(s): +// \uart_rx_inst|Equal1~2_combout = (\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt [9]))) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [6]), + .datad(\uart_rx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y10_N3 +dffeas \uart_rx_inst|rx_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y16_N7 +dffeas \uart_rx_inst|start_nedge ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|start_nedge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; +defparam \uart_rx_inst|start_nedge .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N6 +cycloneive_lcell_comb \uart_rx_inst|always3~0 ( +// Equation(s): +// \uart_rx_inst|always3~0_combout = (!\uart_rx_inst|rx_reg3~q & \uart_rx_inst|rx_reg2~q ) + + .dataa(\uart_rx_inst|rx_reg3~q ), + .datab(gnd), + .datac(\uart_rx_inst|rx_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always3~0 .lut_mask = 16'h5050; +defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h0F0F; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N26 +cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( +// Equation(s): +// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|rx_reg3~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h0F0F; +defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y10_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( +// Equation(s): +// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rx~input_o ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \rx~input ( + .i(rx), + .ibar(gnd), + .o(\rx~input_o )); +// synopsys translate_off +defparam \rx~input .bus_hold = "false"; +defparam \rx~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y14_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|tx_flag~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|tx_flag~feeder_combout = \data_rw_ctrl_inst|rd_fifo_rd_en~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|tx_flag~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|tx_flag~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|tx_flag~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y14_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N16 +cycloneive_lcell_comb \uart_rx_inst|po_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[1]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N18 +cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N4 +cycloneive_lcell_comb \uart_rx_inst|rx_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[4]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N20 +cycloneive_lcell_comb \uart_rx_inst|po_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[6]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N10 +cycloneive_lcell_comb \uart_rx_inst|rx_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[5]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N8 +cycloneive_lcell_comb \uart_rx_inst|po_data[7]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[7]~feeder_combout = \uart_rx_inst|rx_data [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [7]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N28 +cycloneive_lcell_comb \uart_rx_inst|rx_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[6]~feeder_combout = \uart_rx_inst|rx_data [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [7]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N26 +cycloneive_lcell_comb \uart_rx_inst|po_data[3]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[3]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N22 +cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y15_N12 +cycloneive_lcell_comb \uart_rx_inst|po_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[0]~feeder_combout = \uart_rx_inst|rx_data [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [0]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y10_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg1~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N23 +cycloneive_io_obuf \sd_clk~output ( + .i(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sd_clk), + .obar()); +// synopsys translate_off +defparam \sd_clk~output .bus_hold = "false"; +defparam \sd_clk~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N23 +cycloneive_io_obuf \sd_cs_n~output ( + .i(\sd_ctrl_inst|sd_cs_n~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sd_cs_n), + .obar()); +// synopsys translate_off +defparam \sd_cs_n~output .bus_hold = "false"; +defparam \sd_cs_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y29_N9 +cycloneive_io_obuf \sd_mosi~output ( + .i(\sd_ctrl_inst|sd_mosi~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sd_mosi), + .obar()); +// synopsys translate_off +defparam \sd_mosi~output .bus_hold = "false"; +defparam \sd_mosi~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y9_N16 +cycloneive_io_obuf \tx~output ( + .i(!\uart_tx_inst|tx~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tx), + .obar()); +// synopsys translate_off +defparam \tx~output .bus_hold = "false"; +defparam \tx~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout = \sd_ctrl_inst|sd_read_inst|cnt_data_num [0] $ (VCC) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y1_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y1_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y1_N26 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ) # (!\sys_rst_n~input_o )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\sys_rst_n~input_o ), + .datac(gnd), + .datad(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h77FF; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N29 +cycloneive_io_ibuf \sd_miso~input ( + .i(sd_miso), + .ibar(gnd), + .o(\sd_miso~input_o )); +// synopsys translate_off +defparam \sd_miso~input .bus_hold = "false"; +defparam \sd_miso~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X16_Y24_N25 +dffeas \sd_ctrl_inst|sd_init_inst|miso_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_miso~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|miso_dly .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|miso_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_en~0_combout = (!\sd_miso~input_o & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q & (\sd_ctrl_inst|sd_init_inst|miso_dly~q & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .lut_mask = 16'h0040; +defparam \sd_ctrl_inst|sd_read_inst|ack_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N13 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_en~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|ack_en~0_combout & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .datab(\sd_ctrl_inst|sd_read_inst|ack_en~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .lut_mask = 16'h0004; +defparam \sd_ctrl_inst|sd_read_inst|ack_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N11 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal0~1_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [1]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_en~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_en~2_combout = (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout & (!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout & ((\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_read_inst|ack_en~q )))) # +// (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout & (((\sd_ctrl_inst|sd_read_inst|ack_en~q )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|ack_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .lut_mask = 16'h50F8; +defparam \sd_ctrl_inst|sd_read_inst|ack_en~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N3 +dffeas \sd_ctrl_inst|sd_read_inst|ack_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_en~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y24_N9 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N15 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N17 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout = (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N21 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout = \sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y24_N23 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y24_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal0~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [5]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [7]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal0~0_combout & \sd_ctrl_inst|sd_read_inst|ack_en~q )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_ack_bit [3]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|ack_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .lut_mask = 16'h5000; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N23 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N29 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout = \sd_ctrl_inst|sd_read_inst|ack_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N19 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N25 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout = \sd_ctrl_inst|sd_read_inst|ack_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N31 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N21 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout = \sd_ctrl_inst|sd_read_inst|ack_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y23_N27 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y23_N17 +dffeas \sd_ctrl_inst|sd_read_inst|ack_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|ack_data [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_read_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|ack_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|ack_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal3~0_combout = (!\sd_ctrl_inst|sd_read_inst|ack_data [6] & (!\sd_ctrl_inst|sd_read_inst|ack_data [5] & (!\sd_ctrl_inst|sd_read_inst|ack_data [7] & !\sd_ctrl_inst|sd_read_inst|ack_data [4]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|ack_data [6]), + .datab(\sd_ctrl_inst|sd_read_inst|ack_data [5]), + .datac(\sd_ctrl_inst|sd_read_inst|ack_data [7]), + .datad(\sd_ctrl_inst|sd_read_inst|ack_data [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal3~2_combout = (\sd_ctrl_inst|sd_read_inst|Equal3~1_combout & \sd_ctrl_inst|sd_read_inst|Equal3~0_combout ) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal3~1_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|Equal3~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|Equal3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N9 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_en~0_combout = (!\sd_miso~input_o & (\sd_ctrl_inst|sd_init_inst|miso_dly~q & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .lut_mask = 16'h0004; +defparam \sd_ctrl_inst|sd_init_inst|ack_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_en~1_combout = (!\sd_ctrl_inst|sd_init_inst|Equal6~2_combout & ((\sd_ctrl_inst|sd_init_inst|ack_en~q ) # ((\sd_ctrl_inst|sd_init_inst|ack_en~0_combout & \sd_ctrl_inst|sd_init_inst|Equal1~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|ack_en~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .lut_mask = 16'h5450; +defparam \sd_ctrl_inst|sd_init_inst|ack_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_en~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N3 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal1~1_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~0_combout & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3])) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~0_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .lut_mask = 16'h000A; +defparam \sd_ctrl_inst|sd_init_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal1~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~1_combout & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal1~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_init_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout = (\sd_ctrl_inst|sd_init_inst|ack_en~q & (((!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .lut_mask = 16'h04CC; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 )) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout = \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_init_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout = (\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7] & !\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|ack_data[39]~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [7]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .lut_mask = 16'h000C; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N21 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N19 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N23 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N3 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N31 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N27 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N15 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N5 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N1 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N25 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N13 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y24_N7 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [10]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [11] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [11]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N11 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [12] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [12]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N29 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [13] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y24_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [14] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [14]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y24_N9 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [15] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [15]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[16] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [16]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[16] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[17] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [16]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [17]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[17] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [17] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [17]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N19 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[18] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [18]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[18] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [18] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [18]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N25 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[19] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [19]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[19] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [19] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [19]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N23 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[20] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [20]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[20] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[21] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [20]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [21]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[21] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[22] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [21]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [22]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[22] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [22] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [22]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[23] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [23]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [23] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [23]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[24] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [24]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[24] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [24] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [24]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N29 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[25] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [25]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[25] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [25] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [25]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N27 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[26] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [26]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[26] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N9 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[27] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [26]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [27]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[27] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N31 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[28] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [27]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [28]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[28] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X19_Y22_N21 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[29] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [28]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [29]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[29] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [29] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [29]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N3 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[30] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [30]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[30] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X19_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [30] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [30]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X19_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[31] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [31]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[31] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N7 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[32] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [31]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[32] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [32] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N29 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[33] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [33]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[33] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [33] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N25 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[34] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [34]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[34] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[35] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [34]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [35]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[35] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal2~1_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [34] & (!\sd_ctrl_inst|sd_init_inst|ack_data [35] & !\sd_ctrl_inst|sd_init_inst|ack_data [33])) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [34]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [35]), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [33]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .lut_mask = 16'h0005; +defparam \sd_ctrl_inst|sd_init_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[36] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [35]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [36]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[36] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [36] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [36]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N3 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[37] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [37]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[37] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout = \sd_ctrl_inst|sd_init_inst|ack_data [37] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[38] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [38]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[38] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N21 +dffeas \sd_ctrl_inst|sd_init_inst|ack_data[39] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_init_inst|ack_data [38]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_init_inst|ack_data[39]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|ack_data [39]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|ack_data[39] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal2~0_combout = (!\sd_ctrl_inst|sd_init_inst|ack_data [36] & (!\sd_ctrl_inst|sd_init_inst|ack_data [38] & (!\sd_ctrl_inst|sd_init_inst|ack_data [39] & !\sd_ctrl_inst|sd_init_inst|ack_data [37]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|ack_data [36]), + .datab(\sd_ctrl_inst|sd_init_inst|ack_data [38]), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [39]), + .datad(\sd_ctrl_inst|sd_init_inst|ack_data [37]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_init_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal2~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal2~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal2~1_combout & (\sd_ctrl_inst|sd_init_inst|ack_data [32] & \sd_ctrl_inst|sd_init_inst|Equal2~0_combout )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|ack_data [32]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_init_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector0~1_combout = (\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector0~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .lut_mask = 16'hAAEA; +defparam \sd_ctrl_inst|sd_init_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [1])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[0]~10 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [2] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~12 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~14 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [4] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~16 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N19 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[4]~18 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N21 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_wait [6] & !\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 )) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[5]~20 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout = (\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & (!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7] & ((\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~22 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N25 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout = \sd_ctrl_inst|sd_init_inst|cnt_wait [8] $ (!\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_wait[7]~24 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .lut_mask = 16'hA5A5; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y20_N27 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N23 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal0~1_combout = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [5]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [6])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [4])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [7]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [7]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [4]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [6]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .lut_mask = 16'h7FFF; +defparam \sd_ctrl_inst|sd_init_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal0~2_combout = (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout & (\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .lut_mask = 16'h0030; +defparam \sd_ctrl_inst|sd_init_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N17 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N13 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_wait[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(\sd_ctrl_inst|sd_init_inst|Equal0~2_combout ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_wait[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal0~0_combout = (((!\sd_ctrl_inst|sd_init_inst|cnt_wait [1]) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [2])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [3])) # (!\sd_ctrl_inst|sd_init_inst|cnt_wait [0]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [0]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_wait [3]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_wait [2]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_wait [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .lut_mask = 16'h7FFF; +defparam \sd_ctrl_inst|sd_init_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.IDLE~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout = (\sd_ctrl_inst|sd_init_inst|state.IDLE~q ) # ((\sd_ctrl_inst|sd_init_inst|cnt_wait [8] & (!\sd_ctrl_inst|sd_init_inst|Equal0~0_combout & !\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_wait [8]), + .datab(\sd_ctrl_inst|sd_init_inst|Equal0~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .lut_mask = 16'hF0F2; +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N9 +dffeas \sd_ctrl_inst|sd_init_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|state.IDLE~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1])) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~12 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 )) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # +// (GND))) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 = CARRY((!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~14 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|Selector8~0_combout & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector8~0_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .lut_mask = 16'hFAF0; +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N27 +dffeas \sd_ctrl_inst|sd_init_inst|state.INIT_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|state.INIT_END~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.INIT_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|WideOr18 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|WideOr18~combout = (\sd_ctrl_inst|sd_init_inst|Selector14~0_combout & !\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .lut_mask = 16'h0C0C; +defparam \sd_ctrl_inst|sd_init_inst|WideOr18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~16 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~18 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N17 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 $ (GND))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 +// & VCC)) +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 = CARRY((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~20 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ), + .cout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N21 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout = \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~22 ), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y22_N23 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal5~1_combout = ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]))) # (!\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [5]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [6]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [7]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .lut_mask = 16'hFDFF; +defparam \sd_ctrl_inst|sd_init_inst|Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout = ((!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout & !\sd_ctrl_inst|sd_init_inst|Equal5~1_combout )) # (!\sd_ctrl_inst|sd_init_inst|state.IDLE~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|state.IDLE~q ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .lut_mask = 16'h333F; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N9 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y22_N11 +dffeas \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10_combout ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_init_inst|WideOr18~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal5~0_combout = (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]) # ((\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]) # (\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [1]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [3]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_cmd_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .lut_mask = 16'hFFFE; +defparam \sd_ctrl_inst|sd_init_inst|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal5~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal5~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .lut_mask = 16'hFFF0; +defparam \sd_ctrl_inst|sd_init_inst|Equal5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector2~0_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & +// ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .lut_mask = 16'h50DC; +defparam \sd_ctrl_inst|sd_init_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N27 +dffeas \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector1~0_combout = (\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & (((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal3~0_combout & +// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal2~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal3~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .lut_mask = 16'hF444; +defparam \sd_ctrl_inst|sd_init_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector1~1_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & ((\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # +// (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & \sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector1~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .lut_mask = 16'hF888; +defparam \sd_ctrl_inst|sd_init_inst|Selector1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N19 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector1~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector5~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector5~0_combout = (\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & ((!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Equal1~2_combout & +// ((\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q & !\sd_ctrl_inst|sd_init_inst|Equal5~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .lut_mask = 16'h50DC; +defparam \sd_ctrl_inst|sd_init_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector4~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # +// (!\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q & (((\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .lut_mask = 16'h22F2; +defparam \sd_ctrl_inst|sd_init_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N5 +dffeas \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector7~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector7~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )) # (!\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ))) # +// (!\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q & (((\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q & !\sd_ctrl_inst|sd_init_inst|Equal1~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .lut_mask = 16'h22F2; +defparam \sd_ctrl_inst|sd_init_inst|Selector7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N25 +dffeas \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~0_combout = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q & (!\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & !\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector3~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q & ((\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .lut_mask = 16'hFC00; +defparam \sd_ctrl_inst|sd_init_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector3~1_combout = (\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal2~2_combout & (\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q & \sd_ctrl_inst|sd_init_inst|Equal1~2_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal2~2_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector3~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .lut_mask = 16'hECCC; +defparam \sd_ctrl_inst|sd_init_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N13 +dffeas \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector15~0_combout = (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ) # ((\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ) # (\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD55~q ), + .datab(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD8~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41~q ), + .datad(\sd_ctrl_inst|sd_init_inst|state.SEND_CMD0~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .lut_mask = 16'hFFFE; +defparam \sd_ctrl_inst|sd_init_inst|Selector15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector15~1_combout = (!\sd_ctrl_inst|sd_init_inst|Equal5~0_combout & (!\sd_ctrl_inst|sd_init_inst|Equal5~1_combout & \sd_ctrl_inst|sd_init_inst|Selector15~0_combout )) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal5~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .lut_mask = 16'h1010; +defparam \sd_ctrl_inst|sd_init_inst|Selector15~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector15~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector15~2_combout = (\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q & ((\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ) # (!\sd_ctrl_inst|sd_init_inst|Selector14~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.INIT_END~q ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector15~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .lut_mask = 16'hFABA; +defparam \sd_ctrl_inst|sd_init_inst|Selector15~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|init_end ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector15~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|init_end .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|init_end .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~2_combout = (\data_rw_ctrl_inst|rd_en~q & (\sd_ctrl_inst|sd_init_inst|init_end~q & !\sd_ctrl_inst|sd_read_inst|state.IDLE~q )) + + .dataa(\data_rw_ctrl_inst|rd_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .lut_mask = 16'h00A0; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector1~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector1~3_combout = (\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ) # ((\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ) # ((!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout & \sd_ctrl_inst|sd_read_inst|Selector2~0_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Selector1~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Selector1~2_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .lut_mask = 16'hFBFA; +defparam \sd_ctrl_inst|sd_read_inst|Selector1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N17 +dffeas \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector1~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N5 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N9 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # +// (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~17 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N15 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 +// & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N17 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7] $ (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y21_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal2~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .lut_mask = 16'h0040; +defparam \sd_ctrl_inst|sd_read_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N7 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal2~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .lut_mask = 16'hA000; +defparam \sd_ctrl_inst|sd_read_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector3~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|Equal2~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal2~0_combout & \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|Equal2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|sd_read_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector3~1_combout = (\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ) # ((\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q & ((!\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal0~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Selector3~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .lut_mask = 16'hDCFC; +defparam \sd_ctrl_inst|sd_read_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N9 +dffeas \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector2~0_combout = (\sd_ctrl_inst|sd_read_inst|Equal0~1_combout & (\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q & \sd_ctrl_inst|sd_read_inst|Equal0~0_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal0~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|state.CMD17_ACK~q ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal0~0_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .lut_mask = 16'h8080; +defparam \sd_ctrl_inst|sd_read_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector2~1_combout = (\sd_ctrl_inst|sd_read_inst|Equal3~2_combout & ((\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ) # ((!\sd_ctrl_inst|sd_read_inst|always3~4_combout & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # +// (!\sd_ctrl_inst|sd_read_inst|Equal3~2_combout & (!\sd_ctrl_inst|sd_read_inst|always3~4_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .lut_mask = 16'hBA30; +defparam \sd_ctrl_inst|sd_read_inst|Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N29 +dffeas \sd_ctrl_inst|sd_read_inst|state.RD_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.RD_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 )) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~19 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N13 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [1])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~13 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N7 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~0_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [3] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [4] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [3]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [4]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_read_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout = (\sd_ctrl_inst|sd_read_inst|always3~2_combout & (\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout & (\sd_ctrl_inst|sd_read_inst|always3~0_combout & !\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .lut_mask = 16'h0080; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .lut_mask = 16'h0048; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Add3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Add3~0_combout = \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .lut_mask = 16'h5FA0; +defparam \sd_ctrl_inst|sd_read_inst|Add3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (\sd_ctrl_inst|sd_read_inst|Add3~0_combout & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|Add3~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .lut_mask = 16'h00A0; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal9~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal9~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [2])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .lut_mask = 16'hA000; +defparam \sd_ctrl_inst|sd_read_inst|Equal9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~11_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [11]), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N31 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~10_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [12]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [12]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N29 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~9_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [13]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N27 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~8_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [14]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N17 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~2_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [12] & (\sd_ctrl_inst|sd_read_inst|byte_head [13] & (\sd_ctrl_inst|sd_read_inst|byte_head [14] & \sd_ctrl_inst|sd_read_inst|byte_head [15]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [12]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [13]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [14]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [15]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~14_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [8] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [8]), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N23 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~13_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [9]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [9]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~12_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [10]) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [10]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y25_N11 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~15_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [7]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [7]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N3 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~3_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [9] & (\sd_ctrl_inst|sd_read_inst|byte_head [10] & (\sd_ctrl_inst|sd_read_inst|byte_head [11] & \sd_ctrl_inst|sd_read_inst|byte_head [8]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [9]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [10]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [11]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~4_combout = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head_en~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout = (!\sd_ctrl_inst|sd_read_inst|Equal6~4_combout & ((\sd_ctrl_inst|sd_read_inst|byte_head_en~q ) # ((\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout & \sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout +// )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~3_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal6~4_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .lut_mask = 16'h00F8; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N15 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head_en~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~1_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [5] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [5]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .lut_mask = 16'h8888; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N27 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~0_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [6]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N9 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~3_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [3] & \sd_ctrl_inst|sd_read_inst|byte_head_en~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [3]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .lut_mask = 16'h8888; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N23 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|byte_head~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|byte_head~2_combout = (\sd_ctrl_inst|sd_read_inst|byte_head_en~q & \sd_ctrl_inst|sd_read_inst|byte_head [4]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~q ), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [4]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|byte_head~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N13 +dffeas \sd_ctrl_inst|sd_read_inst|byte_head[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|byte_head~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|byte_head [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|byte_head[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Equal6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Equal6~0_combout = (\sd_ctrl_inst|sd_read_inst|byte_head [4] & (\sd_ctrl_inst|sd_read_inst|byte_head [7] & (\sd_ctrl_inst|sd_read_inst|byte_head [6] & \sd_ctrl_inst|sd_read_inst|byte_head [5]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head [4]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head [7]), + .datac(\sd_ctrl_inst|sd_read_inst|byte_head [6]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout = (\sd_ctrl_inst|sd_read_inst|Equal6~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_read_inst|Equal6~2_combout & \sd_ctrl_inst|sd_read_inst|Equal6~3_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Equal6~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal6~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|Equal6~2_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|Equal6~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout $ (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3])))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .lut_mask = 16'h0028; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N1 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_bit~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ) # ((\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))) # +// (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .lut_mask = 16'hFDF5; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y25_N5 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~15 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N9 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~21 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N15 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 $ (GND))) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & +// (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 & VCC)) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 = CARRY((\sd_ctrl_inst|sd_read_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~23 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N17 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 )) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7] & ((\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) +// # (GND))) +// \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 = CARRY((!\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ) # (!\sd_ctrl_inst|sd_read_inst|cnt_data_num [7])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~25 ), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ), + .cout(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~27 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y25_N19 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y25_N21 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~3_combout = (\sd_ctrl_inst|sd_read_inst|always3~2_combout & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~3 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_read_inst|always3~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|always3~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|always3~4_combout = (\sd_ctrl_inst|sd_read_inst|always3~1_combout & (\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & \sd_ctrl_inst|sd_read_inst|always3~3_combout )) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_read_inst|always3~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|always3~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|always3~4 .lut_mask = 16'h8800; +defparam \sd_ctrl_inst|sd_read_inst|always3~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector4~0_combout = (\sd_ctrl_inst|sd_read_inst|Selector0~0_combout & (\sd_ctrl_inst|sd_read_inst|always3~4_combout & ((\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout & +// ((\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # ((\sd_ctrl_inst|sd_read_inst|always3~4_combout & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|always3~4_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .lut_mask = 16'hDC50; +defparam \sd_ctrl_inst|sd_read_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N23 +dffeas \sd_ctrl_inst|sd_read_inst|state.RD_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.RD_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_end~1_combout = (!\sd_ctrl_inst|sd_read_inst|cnt_end [0] & \sd_ctrl_inst|sd_read_inst|state.RD_END~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N21 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cnt_end~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cnt_end~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_END~q & (\sd_ctrl_inst|sd_read_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_read_inst|cnt_end [1]))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .lut_mask = 16'h3C00; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N31 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_end[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_end~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_end[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector0~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_end [2] & (\sd_ctrl_inst|sd_read_inst|cnt_end [1] & \sd_ctrl_inst|sd_read_inst|cnt_end [0])) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_end [2]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_end [1]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_end [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .lut_mask = 16'hA000; +defparam \sd_ctrl_inst|sd_read_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|Selector0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|Selector0~1_combout = (\sd_ctrl_inst|sd_read_inst|Selector1~0_combout & (((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q )) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|sd_read_inst|Selector1~0_combout +// & (\sd_ctrl_inst|sd_read_inst|state.IDLE~q & ((!\sd_ctrl_inst|sd_read_inst|state.RD_END~q ) # (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|Selector1~0_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.RD_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .lut_mask = 16'h32FA; +defparam \sd_ctrl_inst|sd_read_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N3 +dffeas \sd_ctrl_inst|sd_read_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|Selector0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_num [0] $ (VCC) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout = \sd_ctrl_inst|sd_init_inst|miso_dly~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_init_inst|miso_dly~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0] $ (VCC) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 = CARRY(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .lut_mask = 16'h33CC; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y23_N1 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N3 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N5 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N9 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~19 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .lut_mask = 16'hA50A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout = \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] $ (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~21 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y23_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y23_N13 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal1~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [5]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [7]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal1~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal1~1_combout = (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1] & (\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_en~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_en~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal1~0_combout & (!\sd_ctrl_inst|sd_write_inst|Equal1~1_combout & ((\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ) # (\sd_ctrl_inst|sd_write_inst|ack_en~q )))) # +// (!\sd_ctrl_inst|sd_write_inst|Equal1~0_combout & (((\sd_ctrl_inst|sd_write_inst|ack_en~q )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|ack_en~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .lut_mask = 16'h30F8; +defparam \sd_ctrl_inst|sd_write_inst|ack_en~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y23_N29 +dffeas \sd_ctrl_inst|sd_write_inst|ack_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_en~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y23_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_write_inst|ack_en~q & \sd_ctrl_inst|sd_write_inst|Equal1~0_combout )) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|ack_en~q ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal1~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .lut_mask = 16'h4400; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N23 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N29 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout = \sd_ctrl_inst|sd_write_inst|ack_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N19 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N25 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal4~1_combout = (!\sd_ctrl_inst|sd_write_inst|ack_data [0] & (!\sd_ctrl_inst|sd_write_inst|ack_data [1] & (!\sd_ctrl_inst|sd_write_inst|ack_data [3] & !\sd_ctrl_inst|sd_write_inst|ack_data [2]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|ack_data [0]), + .datab(\sd_ctrl_inst|sd_write_inst|ack_data [1]), + .datac(\sd_ctrl_inst|sd_write_inst|ack_data [3]), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|Equal4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout = \sd_ctrl_inst|sd_write_inst|ack_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N31 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N21 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout = \sd_ctrl_inst|sd_write_inst|ack_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .lut_mask = 16'hFF00; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y24_N27 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y24_N1 +dffeas \sd_ctrl_inst|sd_write_inst|ack_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_write_inst|ack_data [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sd_ctrl_inst|sd_write_inst|ack_data[7]~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|ack_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|ack_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y24_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal4~0_combout = (!\sd_ctrl_inst|sd_write_inst|ack_data [6] & (!\sd_ctrl_inst|sd_write_inst|ack_data [5] & (!\sd_ctrl_inst|sd_write_inst|ack_data [7] & !\sd_ctrl_inst|sd_write_inst|ack_data [4]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|ack_data [6]), + .datab(\sd_ctrl_inst|sd_write_inst|ack_data [5]), + .datac(\sd_ctrl_inst|sd_write_inst|ack_data [7]), + .datad(\sd_ctrl_inst|sd_write_inst|ack_data [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|sd_write_inst|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal4~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal4~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal4~1_combout & \sd_ctrl_inst|sd_write_inst|Equal4~0_combout ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .lut_mask = 16'hCC00; +defparam \sd_ctrl_inst|sd_write_inst|Equal4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector2~1_combout = (\sd_ctrl_inst|sd_write_inst|Selector2~0_combout & ((\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ) # ((!\sd_ctrl_inst|sd_write_inst|always4~3_combout & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))) +// # (!\sd_ctrl_inst|sd_write_inst|Selector2~0_combout & (!\sd_ctrl_inst|sd_write_inst|always4~3_combout & (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal4~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .lut_mask = 16'hBA30; +defparam \sd_ctrl_inst|sd_write_inst|Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N1 +dffeas \sd_ctrl_inst|sd_write_inst|state.WR_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.WR_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y13_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_bit~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Add3~2_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .lut_mask = 16'h3C3C; +defparam \sd_ctrl_inst|sd_write_inst|Add3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y13_N21 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Add3~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Add3~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Add3~1_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .lut_mask = 16'h3CF0; +defparam \sd_ctrl_inst|sd_write_inst|Add3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y13_N3 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Add3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y13_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_bit +// [0] & \sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [3]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [0]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_bit [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .lut_mask = 16'hFF0F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X10_Y16_N5 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [2] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~15 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~18 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N9 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [5])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~22 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [6] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~24 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [7])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~26 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N19 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~28 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N21 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9] & +// ((\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [9])) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~30 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .lut_mask = 16'h5A5F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout = (\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~32 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N25 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X10_Y16_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout = \sd_ctrl_inst|sd_write_inst|cnt_data_num [11] $ (\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~34 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .lut_mask = 16'h5A5A; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X10_Y16_N27 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X10_Y16_N23 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout & (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [10] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [11] & !\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [11]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~2 .lut_mask = 16'h0002; +defparam \sd_ctrl_inst|sd_write_inst|always4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|always4~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|always4~3_combout = (\sd_ctrl_inst|sd_write_inst|always4~1_combout & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|cnt_data_num [0] & \sd_ctrl_inst|sd_write_inst|always4~2_combout ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|always4~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_write_inst|always4~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|always4~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|always4~3 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|always4~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector4~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector4~0_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q & ((\sd_ctrl_inst|sd_write_inst|always4~3_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout )))) # +// (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q & (((\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & !\sd_ctrl_inst|sd_write_inst|Equal6~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datab(\sd_ctrl_inst|sd_write_inst|always4~3_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .lut_mask = 16'h88F8; +defparam \sd_ctrl_inst|sd_write_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N17 +dffeas \sd_ctrl_inst|sd_write_inst|state.WR_BUSY ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.WR_BUSY .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~8_combout = (\sd_miso~input_o & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(\sd_miso~input_o ), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N27 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~7_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [0]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N9 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~6_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [1] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [1]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N31 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~5_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N13 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal6~1_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [0] & (\sd_ctrl_inst|sd_write_inst|busy_data [1] & (\sd_ctrl_inst|sd_write_inst|busy_data [2] & \sd_ctrl_inst|sd_write_inst|busy_data [3]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|busy_data [0]), + .datab(\sd_ctrl_inst|sd_write_inst|busy_data [1]), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [2]), + .datad(\sd_ctrl_inst|sd_write_inst|busy_data [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~4_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [3] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(\sd_ctrl_inst|sd_write_inst|busy_data [3]), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .lut_mask = 16'hAA00; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N25 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~3_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|busy_data [4]), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .lut_mask = 16'hCC00; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N15 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~2_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [5] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [5]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N5 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|busy_data~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|busy_data~1_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_write_inst|busy_data~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N19 +dffeas \sd_ctrl_inst|sd_write_inst|busy_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|busy_data~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|busy_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|busy_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal6~0_combout = (\sd_ctrl_inst|sd_write_inst|busy_data [4] & (\sd_ctrl_inst|sd_write_inst|busy_data [5] & (\sd_ctrl_inst|sd_write_inst|busy_data [6] & \sd_ctrl_inst|sd_write_inst|busy_data [7]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|busy_data [4]), + .datab(\sd_ctrl_inst|sd_write_inst|busy_data [5]), + .datac(\sd_ctrl_inst|sd_write_inst|busy_data [6]), + .datad(\sd_ctrl_inst|sd_write_inst|busy_data [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_write_inst|Equal6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal6~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal6~1_combout & \sd_ctrl_inst|sd_write_inst|Equal6~0_combout ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Equal6~1_combout ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|Equal6~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .lut_mask = 16'hCC00; +defparam \sd_ctrl_inst|sd_write_inst|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector5~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector5~0_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & ((\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.WR_END~q & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) # +// (!\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q & (((\sd_ctrl_inst|sd_write_inst|state.WR_END~q & !\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.WR_BUSY~q ), + .datab(\sd_ctrl_inst|sd_write_inst|Equal6~2_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .lut_mask = 16'h88F8; +defparam \sd_ctrl_inst|sd_write_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N5 +dffeas \sd_ctrl_inst|sd_write_inst|state.WR_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.WR_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_end~2_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] $ (\sd_ctrl_inst|sd_write_inst|cnt_end [1]))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .lut_mask = 16'h5A00; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_end~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_end~1_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|state.WR_END~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .lut_mask = 16'h0F00; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N23 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_end~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_end~0_combout = (\sd_ctrl_inst|sd_write_inst|state.WR_END~q & (\sd_ctrl_inst|sd_write_inst|cnt_end [2] $ (((\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [1]))))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [2]), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .lut_mask = 16'h7800; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N29 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_end[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_end~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_end [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_end[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector0~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_end [1] & (\sd_ctrl_inst|sd_write_inst|cnt_end [0] & \sd_ctrl_inst|sd_write_inst|cnt_end [2])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_end [1]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_end [0]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_end [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_write_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cs_n~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cs_n~0_combout = (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout & ((\sd_ctrl_inst|comb~2_combout ) # (\sd_ctrl_inst|sd_write_inst|cs_n~q ))) + + .dataa(\sd_ctrl_inst|comb~2_combout ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .lut_mask = 16'h00FA; +defparam \sd_ctrl_inst|sd_write_inst|cs_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N3 +dffeas \sd_ctrl_inst|sd_write_inst|cs_n ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cs_n~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cs_n~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cs_n .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cs_n .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector0~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector0~1_combout = (\sd_ctrl_inst|comb~2_combout & (((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q )) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ))) # (!\sd_ctrl_inst|comb~2_combout & +// (\sd_ctrl_inst|sd_write_inst|state.IDLE~q & ((!\sd_ctrl_inst|sd_write_inst|state.WR_END~q ) # (!\sd_ctrl_inst|sd_write_inst|Selector0~0_combout )))) + + .dataa(\sd_ctrl_inst|comb~2_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|Selector0~0_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .datad(\sd_ctrl_inst|sd_write_inst|state.WR_END~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .lut_mask = 16'h32FA; +defparam \sd_ctrl_inst|sd_write_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N9 +dffeas \sd_ctrl_inst|sd_write_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_dly~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|wr_busy_dly~feeder_combout = \sd_ctrl_inst|sd_write_inst|state.IDLE~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|wr_busy_dly~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N19 +dffeas \data_rw_ctrl_inst|wr_busy_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|wr_busy_dly~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|wr_busy_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|wr_busy_dly .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|wr_busy_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|wr_busy_fall~0 ( +// Equation(s): +// \data_rw_ctrl_inst|wr_busy_fall~0_combout = (\data_rw_ctrl_inst|wr_busy_dly~q & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|wr_busy_dly~q ), + .datac(gnd), + .datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|wr_busy_fall~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|wr_busy_fall~0 .lut_mask = 16'h00CC; +defparam \data_rw_ctrl_inst|wr_busy_fall~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N11 +dffeas \data_rw_ctrl_inst|rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|wr_busy_fall~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|rd_en .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|cs_n~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|cs_n~2_combout = (!\sd_ctrl_inst|sd_read_inst|Selector0~0_combout & ((\sd_ctrl_inst|sd_read_inst|cs_n~q ) # ((\sd_ctrl_inst|sd_init_inst|init_end~q & \data_rw_ctrl_inst|rd_en~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datab(\sd_ctrl_inst|sd_read_inst|Selector0~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cs_n~q ), + .datad(\data_rw_ctrl_inst|rd_en~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .lut_mask = 16'h3230; +defparam \sd_ctrl_inst|sd_read_inst|cs_n~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N25 +dffeas \sd_ctrl_inst|sd_read_inst|cs_n ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cs_n~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cs_n~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cs_n .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cs_n .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_cs_n~0_combout = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_write_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_read_inst|cs_n~q )) # +// (!\sd_ctrl_inst|sd_read_inst|state.IDLE~q ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .datab(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .datac(\sd_ctrl_inst|sd_write_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_read_inst|cs_n~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_cs_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_cs_n~0 .lut_mask = 16'h1B5F; +defparam \sd_ctrl_inst|sd_cs_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~1_combout = (!\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q & (!\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q & !\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q )) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.CMD0_ACK~q ), + .datab(\sd_ctrl_inst|sd_init_inst|state.CMD8_ACK~q ), + .datac(\sd_ctrl_inst|sd_init_inst|state.CMD55_ACK~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .lut_mask = 16'h0101; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y22_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal6~1_combout = (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0] & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2] & \sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [3]), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [0]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [2]), + .datad(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .lut_mask = 16'h8000; +defparam \sd_ctrl_inst|sd_init_inst|Equal6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~0_combout = ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & ((\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]) # (\sd_ctrl_inst|sd_init_inst|Equal6~1_combout )))) # (!\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ) + + .dataa(\sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK~q ), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .lut_mask = 16'hDDD5; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Equal6~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Equal6~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5] & (!\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4] & \sd_ctrl_inst|sd_init_inst|Equal6~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [5]), + .datac(\sd_ctrl_inst|sd_init_inst|cnt_ack_bit [4]), + .datad(\sd_ctrl_inst|sd_init_inst|Equal6~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .lut_mask = 16'h0800; +defparam \sd_ctrl_inst|sd_init_inst|Equal6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~2_combout = (\sd_ctrl_inst|sd_init_inst|Equal6~0_combout & (\sd_ctrl_inst|sd_init_inst|Selector13~0_combout & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # (\sd_ctrl_inst|sd_init_inst|Equal6~2_combout )))) +// # (!\sd_ctrl_inst|sd_init_inst|Equal6~0_combout & ((\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ) # ((\sd_ctrl_inst|sd_init_inst|Equal6~2_combout )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Equal6~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Selector13~1_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|Selector13~0_combout ), + .datad(\sd_ctrl_inst|sd_init_inst|Equal6~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .lut_mask = 16'hF5C4; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector13~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector13~3_combout = ((\sd_ctrl_inst|sd_init_inst|Selector15~0_combout & ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # (\sd_ctrl_inst|sd_init_inst|cs_n~q )))) # (!\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector15~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector13~2_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .lut_mask = 16'hA8FF; +defparam \sd_ctrl_inst|sd_init_inst|Selector13~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N15 +dffeas \sd_ctrl_inst|sd_init_inst|cs_n ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector13~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|cs_n~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|cs_n .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|cs_n .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_cs_n~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_cs_n~1_combout = (\sd_ctrl_inst|sd_init_inst|init_end~q & (\sd_ctrl_inst|sd_cs_n~0_combout )) # (!\sd_ctrl_inst|sd_init_inst|init_end~q & ((!\sd_ctrl_inst|sd_init_inst|cs_n~q ))) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_cs_n~0_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|cs_n~q ), + .datad(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_cs_n~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_cs_n~1 .lut_mask = 16'hCC0F; +defparam \sd_ctrl_inst|sd_cs_n~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y22_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_init_inst|Selector14~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_init_inst|Selector14~11_combout = (\sd_ctrl_inst|sd_init_inst|Selector14~10_combout & (((\sd_ctrl_inst|sd_init_inst|mosi~q & !\sd_ctrl_inst|sd_init_inst|Selector14~0_combout )))) # (!\sd_ctrl_inst|sd_init_inst|Selector14~10_combout & +// ((\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ) # ((\sd_ctrl_inst|sd_init_inst|mosi~q )))) + + .dataa(\sd_ctrl_inst|sd_init_inst|Selector14~10_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|Equal5~2_combout ), + .datac(\sd_ctrl_inst|sd_init_inst|mosi~q ), + .datad(\sd_ctrl_inst|sd_init_inst|Selector14~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .lut_mask = 16'h54F4; +defparam \sd_ctrl_inst|sd_init_inst|Selector14~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y22_N1 +dffeas \sd_ctrl_inst|sd_init_inst|mosi ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_init_inst|Selector14~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_init_inst|mosi~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_init_inst|mosi .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_init_inst|mosi .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|mosi~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]) # (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] $ (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5])))) # +// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] & \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [2]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [0]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .lut_mask = 16'hEC84; +defparam \sd_ctrl_inst|sd_read_inst|mosi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N11 +dffeas \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|mosi~1_combout = \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5] $ (((!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_read_inst|mosi~0_combout & !\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3])))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|mosi~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .lut_mask = 16'hF0B4; +defparam \sd_ctrl_inst|sd_read_inst|mosi~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|mosi~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|mosi~2_combout = (\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q & ((\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_read_inst|mosi~1_combout ) # (!\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ))) # +// (!\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4] & ((!\sd_ctrl_inst|sd_read_inst|mosi~1_combout ))))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_cmd_bit [4]), + .datab(\sd_ctrl_inst|sd_read_inst|Equal2~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|mosi~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|state.SEND_CMD17~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .lut_mask = 16'hA700; +defparam \sd_ctrl_inst|sd_read_inst|mosi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N1 +dffeas \sd_ctrl_inst|sd_read_inst|mosi ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|mosi~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|mosi~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|mosi .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|mosi .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q $ (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT = CARRY(!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .lut_mask = 16'hCC33; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h0F0F; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N8 +cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( +// Equation(s): +// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] $ (VCC))) # (!\uart_rx_inst|bit_flag~q & (\uart_rx_inst|bit_cnt [0] & VCC)) +// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [0])) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|Add1~0_combout ), + .cout(\uart_rx_inst|Add1~1 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; +defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N10 +cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( +// Equation(s): +// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) +// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~1 ), + .combout(\uart_rx_inst|Add1~2_combout ), + .cout(\uart_rx_inst|Add1~3 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N14 +cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( +// Equation(s): +// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|bit_cnt [3] $ (\uart_rx_inst|Add1~5 ) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(gnd), + .datad(gnd), + .cin(\uart_rx_inst|Add1~5 ), + .combout(\uart_rx_inst|Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h3C3C; +defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N4 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~0_combout = (\uart_rx_inst|Add1~6_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q ))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|Add1~6_combout ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h4CCC; +defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N5 +dffeas \uart_rx_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N24 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~1_combout = (\uart_rx_inst|Add1~0_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q ))) + + .dataa(\uart_rx_inst|bit_flag~q ), + .datab(\uart_rx_inst|bit_cnt [3]), + .datac(\uart_rx_inst|Add1~0_combout ), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h70F0; +defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N25 +dffeas \uart_rx_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y16_N11 +dffeas \uart_rx_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N18 +cycloneive_lcell_comb \uart_rx_inst|always4~0 ( +// Equation(s): +// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|bit_cnt [0] & !\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [2]), + .datab(\uart_rx_inst|bit_cnt [0]), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_rx_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0011; +defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N2 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) +// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_rx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N0 +cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( +// Equation(s): +// \uart_rx_inst|Equal1~0_combout = (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt [7] & (\uart_rx_inst|baud_cnt [1] & \uart_rx_inst|baud_cnt [0]))) + + .dataa(\uart_rx_inst|baud_cnt [8]), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(\uart_rx_inst|baud_cnt [1]), + .datad(\uart_rx_inst|baud_cnt [0]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h1000; +defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N12 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) + + .dataa(\uart_rx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[4]~22 ), + .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_rx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N13 +dffeas \uart_rx_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N6 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) +// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_rx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[1]~16 ), + .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_rx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N7 +dffeas \uart_rx_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y16_N10 +cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( +// Equation(s): +// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [5] & (\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt [3]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [5]), + .datac(\uart_rx_inst|baud_cnt [2]), + .datad(\uart_rx_inst|baud_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N2 +cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( +// Equation(s): +// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|Equal1~2_combout & (\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal1~1_combout ))) + + .dataa(\uart_rx_inst|Equal1~2_combout ), + .datab(\uart_rx_inst|baud_cnt [12]), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h8000; +defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N16 +cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( +// Equation(s): +// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) + + .dataa(\uart_rx_inst|start_nedge~q ), + .datab(gnd), + .datac(\uart_rx_inst|work_en~q ), + .datad(\uart_rx_inst|always4~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hAAFA; +defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N17 +dffeas \uart_rx_inst|work_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_rx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N28 +cycloneive_lcell_comb \uart_rx_inst|always5~0 ( +// Equation(s): +// \uart_rx_inst|always5~0_combout = (\uart_rx_inst|Equal1~3_combout ) # (!\uart_rx_inst|work_en~q ) + + .dataa(gnd), + .datab(\uart_rx_inst|Equal1~3_combout ), + .datac(gnd), + .datad(\uart_rx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_rx_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always5~0 .lut_mask = 16'hCCFF; +defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y16_N3 +dffeas \uart_rx_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N4 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[0]~14 ), + .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_rx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N5 +dffeas \uart_rx_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N8 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[2]~18 ), + .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_rx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N9 +dffeas \uart_rx_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N14 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) +// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[5]~24 ), + .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_rx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N15 +dffeas \uart_rx_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N16 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[6]~26 ), + .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_rx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N17 +dffeas \uart_rx_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N18 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) +// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[7]~28 ), + .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_rx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N19 +dffeas \uart_rx_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N20 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[8]~30 ), + .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_rx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N21 +dffeas \uart_rx_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N24 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[10]~34 ), + .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_rx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N25 +dffeas \uart_rx_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N26 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt [12] $ (!\uart_rx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_rx_inst|baud_cnt[11]~36 ), + .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y16_N27 +dffeas \uart_rx_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y16_N28 +cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( +// Equation(s): +// \uart_rx_inst|Equal2~1_combout = (!\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt [6] & \uart_rx_inst|baud_cnt [9]))) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [6]), + .datad(\uart_rx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0400; +defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N22 +cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( +// Equation(s): +// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal2~0_combout & (!\uart_rx_inst|baud_cnt [12] & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal2~1_combout ))) + + .dataa(\uart_rx_inst|Equal2~0_combout ), + .datab(\uart_rx_inst|baud_cnt [12]), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal2~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h2000; +defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N23 +dffeas \uart_rx_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Equal2~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y16_N0 +cycloneive_lcell_comb \uart_rx_inst|always4~1 ( +// Equation(s): +// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|always4~0_combout & (\uart_rx_inst|bit_flag~q & \uart_rx_inst|bit_cnt [3])) + + .dataa(gnd), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~1 .lut_mask = 16'hC000; +defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y16_N1 +dffeas \uart_rx_inst|rx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always4~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_flag .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y13_N1 +dffeas \uart_rx_inst|po_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_flag~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_flag .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0010; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .lut_mask = 16'h0500; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'hA5F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .lut_mask = 16'hF05A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [10]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y12_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X12_Y12_N25 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h6FF6; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N7 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_data_num [8] & (\sd_ctrl_inst|sd_write_inst|always4~2_combout & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_data_num [8]), + .datac(\sd_ctrl_inst|sd_write_inst|always4~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'h3020; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hE1F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8] = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [8]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h0040; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2] $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h3CC3; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout = !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h3333; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y13_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y13_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0])) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]) # (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0])))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout = (\uart_rx_inst|po_flag~q & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .datab(\uart_rx_inst|po_flag~q ), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hCC88; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~COUT ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .lut_mask = 16'hF0F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout & (\uart_rx_inst|po_flag~q & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ) # +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .datac(\uart_rx_inst|po_flag~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'hC080; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0100; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q $ (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q )) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h6969; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] $ +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'hF00F; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h2000; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0200; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N19 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [6]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0300; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y13_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7] & \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [7]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y13_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y13_N21 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X15_Y12_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y12_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X12_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y14_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y14_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [7]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [6]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [8]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y12_N23 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout )) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N5 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X16_Y13_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N9 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y12_N27 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [3]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [5]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y12_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y13_N31 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y13_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y13_N15 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y13_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] $ +// (((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0] & +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [0]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .lut_mask = 16'h78F0; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y13_N13 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y13_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y13_N11 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y12_N29 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y12_N1 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N17 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y12_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [0]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [1]), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a [2]), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y12_N3 +dffeas \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [1]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [1]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~1 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )))) # (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [2]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [2]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~3 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .lut_mask = 16'h964D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 )))) # (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & +// ((!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4] & +// !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [4]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [4]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~7 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .lut_mask = 16'h962B; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout = (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 & VCC)))) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & +// ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ) # (GND))) # (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )))) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [5]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [5]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~9 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .lut_mask = 16'h694D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout = ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )))) # (GND) +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 = CARRY((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6] & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6] & ((\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]) # +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 )))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [6]), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [6]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~11 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ), + .cout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~13 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .lut_mask = 16'h964D; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout = \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8] $ +// (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 $ (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8])) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a [8]), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a [8]), + .cin(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~15 ), + .combout(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .lut_mask = 16'hA55A; +defparam \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N4 +cycloneive_lcell_comb \sd_ctrl_inst|comb~1 ( +// Equation(s): +// \sd_ctrl_inst|comb~1_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout & (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8_combout ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|comb~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|comb~1 .lut_mask = 16'h0001; +defparam \sd_ctrl_inst|comb~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N0 +cycloneive_lcell_comb \sd_ctrl_inst|comb~0 ( +// Equation(s): +// \sd_ctrl_inst|comb~0_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout & (\sd_ctrl_inst|sd_init_inst|init_end~q & +// (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout & !\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0_combout ), + .datab(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datac(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|comb~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|comb~0 .lut_mask = 16'h0004; +defparam \sd_ctrl_inst|comb~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y12_N2 +cycloneive_lcell_comb \sd_ctrl_inst|comb~2 ( +// Equation(s): +// \sd_ctrl_inst|comb~2_combout = (!\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout & (\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout & +// (\sd_ctrl_inst|comb~1_combout & \sd_ctrl_inst|comb~0_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14_combout ), + .datab(\data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16_combout ), + .datac(\sd_ctrl_inst|comb~1_combout ), + .datad(\sd_ctrl_inst|comb~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|comb~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|comb~2 .lut_mask = 16'h4000; +defparam \sd_ctrl_inst|comb~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N26 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector1~2_combout = (\sd_ctrl_inst|sd_write_inst|Equal3~2_combout & (((\sd_ctrl_inst|comb~2_combout & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )))) # (!\sd_ctrl_inst|sd_write_inst|Equal3~2_combout & +// ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # ((\sd_ctrl_inst|comb~2_combout & !\sd_ctrl_inst|sd_write_inst|state.IDLE~q )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Equal3~2_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datac(\sd_ctrl_inst|comb~2_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .lut_mask = 16'h44F4; +defparam \sd_ctrl_inst|sd_write_inst|Selector1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y23_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Selector1~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Selector1~3_combout = (\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ) # ((\sd_ctrl_inst|sd_write_inst|Selector2~0_combout & ((!\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ) # (!\sd_ctrl_inst|sd_write_inst|Equal4~1_combout +// )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Selector2~0_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|Equal4~1_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|Selector1~2_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|Equal4~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .lut_mask = 16'hF2FA; +defparam \sd_ctrl_inst|sd_write_inst|Selector1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y23_N15 +dffeas \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|Selector1~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N14 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # +// (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~9 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N15 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~11 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N17 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 )) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) +// # (GND))) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 = CARRY((!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~13 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .lut_mask = 16'h3C3F; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N19 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Mux0~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Mux0~0_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]) # (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]))) # +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1])))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [0]), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .lut_mask = 16'h00E8; +defparam \sd_ctrl_inst|sd_write_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 $ (GND))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & +// (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 & VCC)) +// \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 = CARRY((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 )) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~15 ), + .combout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ), + .cout(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~17 )); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .lut_mask = 16'hC30C; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X12_Y16_N21 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X12_Y16_N23 +dffeas \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~2_combout = (!\sd_ctrl_inst|sd_write_inst|Mux0~0_combout & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & !\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|Mux0~0_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .lut_mask = 16'h0030; +defparam \sd_ctrl_inst|sd_write_inst|mosi~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|Equal3~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|Equal3~0_combout = (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2] & (\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1] & \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3])) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [2]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [1]), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .lut_mask = 16'hC000; +defparam \sd_ctrl_inst|sd_write_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y16_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~3_combout = (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5] & ((\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & ((\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ))) # (!\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4] & +// (\sd_ctrl_inst|sd_write_inst|Mux0~1_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|Mux0~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [4]), + .datac(\sd_ctrl_inst|sd_write_inst|cnt_cmd_bit [5]), + .datad(\sd_ctrl_inst|sd_write_inst|Equal3~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .lut_mask = 16'h0E02; +defparam \sd_ctrl_inst|sd_write_inst|mosi~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~4_combout = (\sd_ctrl_inst|sd_write_inst|mosi~1_combout ) # ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q & ((\sd_ctrl_inst|sd_write_inst|mosi~2_combout ) # (\sd_ctrl_inst|sd_write_inst|mosi~3_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~1_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|mosi~2_combout ), + .datac(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datad(\sd_ctrl_inst|sd_write_inst|mosi~3_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .lut_mask = 16'hFAEA; +defparam \sd_ctrl_inst|sd_write_inst|mosi~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~5_combout = (!\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q & ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]) # ((\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]) # (!\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|cnt_data_num [10]), + .datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datac(\sd_ctrl_inst|sd_write_inst|state.WR_DATA~q ), + .datad(\sd_ctrl_inst|sd_write_inst|cnt_data_num [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .lut_mask = 16'h3323; +defparam \sd_ctrl_inst|sd_write_inst|mosi~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X11_Y16_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_write_inst|mosi~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_write_inst|mosi~8_combout = (!\sd_ctrl_inst|sd_write_inst|mosi~4_combout & (!\sd_ctrl_inst|sd_write_inst|mosi~5_combout & ((\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ) # (!\sd_ctrl_inst|sd_write_inst|mosi~7_combout )))) + + .dataa(\sd_ctrl_inst|sd_write_inst|mosi~7_combout ), + .datab(\sd_ctrl_inst|sd_write_inst|state.SEND_CMD24~q ), + .datac(\sd_ctrl_inst|sd_write_inst|mosi~4_combout ), + .datad(\sd_ctrl_inst|sd_write_inst|mosi~5_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .lut_mask = 16'h000D; +defparam \sd_ctrl_inst|sd_write_inst|mosi~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X11_Y16_N17 +dffeas \sd_ctrl_inst|sd_write_inst|mosi ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_write_inst|mosi~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_write_inst|mosi~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_write_inst|mosi .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_write_inst|mosi .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_mosi~0_combout = (\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_write_inst|mosi~q )))) # (!\sd_ctrl_inst|sd_write_inst|state.IDLE~q & (((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q )) # +// (!\sd_ctrl_inst|sd_read_inst|mosi~q ))) + + .dataa(\sd_ctrl_inst|sd_write_inst|state.IDLE~q ), + .datab(\sd_ctrl_inst|sd_read_inst|mosi~q ), + .datac(\sd_ctrl_inst|sd_write_inst|mosi~q ), + .datad(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_mosi~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_mosi~0 .lut_mask = 16'h1B5F; +defparam \sd_ctrl_inst|sd_mosi~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_mosi~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_mosi~1_combout = (\sd_ctrl_inst|sd_init_inst|init_end~q & ((\sd_ctrl_inst|sd_mosi~0_combout ))) # (!\sd_ctrl_inst|sd_init_inst|init_end~q & (!\sd_ctrl_inst|sd_init_inst|mosi~q )) + + .dataa(\sd_ctrl_inst|sd_init_inst|init_end~q ), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_init_inst|mosi~q ), + .datad(\sd_ctrl_inst|sd_mosi~0_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_mosi~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_mosi~1 .lut_mask = 16'hAF05; +defparam \sd_ctrl_inst|sd_mosi~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N2 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) +// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_tx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N0 +cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( +// Equation(s): +// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt [3] & \uart_tx_inst|baud_cnt [0]))) + + .dataa(\uart_tx_inst|baud_cnt [5]), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(\uart_tx_inst|baud_cnt [3]), + .datad(\uart_tx_inst|baud_cnt [0]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0100; +defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N2 +cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( +// Equation(s): +// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|Equal1~0_combout & (!\uart_tx_inst|baud_cnt [11] & !\uart_tx_inst|baud_cnt [9]))) + + .dataa(\uart_tx_inst|baud_cnt [8]), + .datab(\uart_tx_inst|Equal1~0_combout ), + .datac(\uart_tx_inst|baud_cnt [11]), + .datad(\uart_tx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0004; +defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N10 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) +// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[3]~20 ), + .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_tx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N11 +dffeas \uart_tx_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N30 +cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( +// Equation(s): +// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [1] & \uart_tx_inst|baud_cnt [4]))) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; +defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N16 +cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( +// Equation(s): +// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [10] & \uart_tx_inst|baud_cnt [12]) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(gnd), + .datac(\uart_tx_inst|baud_cnt [12]), + .datad(gnd), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hA0A0; +defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N26 +cycloneive_lcell_comb \uart_tx_inst|always1~0 ( +// Equation(s): +// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~1_combout & (\uart_tx_inst|Equal1~2_combout & \uart_tx_inst|Equal1~3_combout ))) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|Equal1~1_combout ), + .datac(\uart_tx_inst|Equal1~2_combout ), + .datad(\uart_tx_inst|Equal1~3_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always1~0 .lut_mask = 16'hD555; +defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y26_N3 +dffeas \uart_tx_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N4 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[0]~14 ), + .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_tx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N5 +dffeas \uart_tx_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N8 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[2]~18 ), + .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_tx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N9 +dffeas \uart_tx_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N14 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) +// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[5]~24 ), + .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_tx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N15 +dffeas \uart_tx_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N16 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[6]~26 ), + .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_tx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N17 +dffeas \uart_tx_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N18 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) +// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[7]~28 ), + .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_tx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N19 +dffeas \uart_tx_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N20 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[8]~30 ), + .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_tx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N21 +dffeas \uart_tx_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N24 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[10]~34 ), + .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_tx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N25 +dffeas \uart_tx_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N26 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt [12] $ (!\uart_tx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_tx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_tx_inst|baud_cnt[11]~36 ), + .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y26_N27 +dffeas \uart_tx_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y26_N28 +cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( +// Equation(s): +// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt [1] & !\uart_tx_inst|baud_cnt [4]))) + + .dataa(\uart_tx_inst|baud_cnt [2]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [1]), + .datad(\uart_tx_inst|baud_cnt [4]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N24 +cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( +// Equation(s): +// \uart_tx_inst|Equal2~1_combout = (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt [12] & (\uart_tx_inst|Equal2~0_combout & \uart_tx_inst|Equal1~1_combout ))) + + .dataa(\uart_tx_inst|baud_cnt [10]), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(\uart_tx_inst|Equal2~0_combout ), + .datad(\uart_tx_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h1000; +defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N25 +dffeas \uart_tx_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|Equal2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N18 +cycloneive_lcell_comb \uart_tx_inst|always3~0 ( +// Equation(s): +// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|bit_flag~q ) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(gnd), + .datac(gnd), + .datad(\uart_tx_inst|bit_flag~q ), + .cin(gnd), + .combout(\uart_tx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always3~0 .lut_mask = 16'h55FF; +defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N12 +cycloneive_lcell_comb \uart_tx_inst|always0~1 ( +// Equation(s): +// \uart_tx_inst|always0~1_combout = (\uart_tx_inst|always0~0_combout & (\uart_tx_inst|bit_flag~q & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [3]))) + + .dataa(\uart_tx_inst|always0~0_combout ), + .datab(\uart_tx_inst|bit_flag~q ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_tx_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~1 .lut_mask = 16'h8000; +defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N4 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|work_en~q & \uart_tx_inst|bit_flag~q ))))) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|bit_flag~q ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h0078; +defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N5 +dffeas \uart_tx_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[0]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N0 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~4 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[1]~4_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) + + .dataa(\uart_tx_inst|always0~1_combout ), + .datab(\uart_tx_inst|bit_cnt [0]), + .datac(\uart_tx_inst|bit_cnt [1]), + .datad(\uart_tx_inst|always3~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[1]~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1]~4 .lut_mask = 16'h5014; +defparam \uart_tx_inst|bit_cnt[1]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N1 +dffeas \uart_tx_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[1]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N16 +cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( +// Equation(s): +// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [2] & (\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1])))) + + .dataa(\uart_tx_inst|bit_cnt [2]), + .datab(\uart_tx_inst|bit_cnt [3]), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h6CCC; +defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N2 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~2 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[3]~2_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & (\uart_tx_inst|bit_cnt [3])) # (!\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|Add1~0_combout ))))) + + .dataa(\uart_tx_inst|always0~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|Add1~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3]~2 .lut_mask = 16'h5140; +defparam \uart_tx_inst|bit_cnt[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N3 +dffeas \uart_tx_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[3]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[0]~16 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[0]~16_combout = \data_rw_ctrl_inst|cnt_wait [0] $ (VCC) +// \data_rw_ctrl_inst|cnt_wait[0]~17 = CARRY(\data_rw_ctrl_inst|cnt_wait [0]) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[0]~17 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|cnt_wait[0]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[3]~22 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[3]~22_combout = (\data_rw_ctrl_inst|cnt_wait [3] & (!\data_rw_ctrl_inst|cnt_wait[2]~21 )) # (!\data_rw_ctrl_inst|cnt_wait [3] & ((\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[3]~23 = CARRY((!\data_rw_ctrl_inst|cnt_wait[2]~21 ) # (!\data_rw_ctrl_inst|cnt_wait [3])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[2]~21 ), + .combout(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[3]~23 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[3]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[4]~24 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[4]~24_combout = (\data_rw_ctrl_inst|cnt_wait [4] & (\data_rw_ctrl_inst|cnt_wait[3]~23 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [4] & (!\data_rw_ctrl_inst|cnt_wait[3]~23 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[4]~25 = CARRY((\data_rw_ctrl_inst|cnt_wait [4] & !\data_rw_ctrl_inst|cnt_wait[3]~23 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [4]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[3]~23 ), + .combout(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[4]~25 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[4]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N9 +dffeas \data_rw_ctrl_inst|cnt_wait[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[4]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal3~0_combout = (\data_rw_ctrl_inst|cnt_wait [4]) # (!\data_rw_ctrl_inst|cnt_wait [5]) + + .dataa(\data_rw_ctrl_inst|cnt_wait [5]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|cnt_wait [4]), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal3~0 .lut_mask = 16'hF5F5; +defparam \data_rw_ctrl_inst|Equal3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N15 +dffeas \data_rw_ctrl_inst|rd_busy_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|rd_busy_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|rd_busy_dly .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|rd_busy_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[0]~12 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[0]~12_combout = \data_rw_ctrl_inst|send_data_num [0] $ (VCC) +// \data_rw_ctrl_inst|send_data_num[0]~13 = CARRY(\data_rw_ctrl_inst|send_data_num [0]) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_rw_ctrl_inst|send_data_num[0]~12_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[0]~13 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[0]~12 .lut_mask = 16'h33CC; +defparam \data_rw_ctrl_inst|send_data_num[0]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y26_N1 +dffeas \data_rw_ctrl_inst|send_data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[0]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[1]~14 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[1]~14_combout = (\data_rw_ctrl_inst|send_data_num [1] & (!\data_rw_ctrl_inst|send_data_num[0]~13 )) # (!\data_rw_ctrl_inst|send_data_num [1] & ((\data_rw_ctrl_inst|send_data_num[0]~13 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[1]~15 = CARRY((!\data_rw_ctrl_inst|send_data_num[0]~13 ) # (!\data_rw_ctrl_inst|send_data_num [1])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [1]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[0]~13 ), + .combout(\data_rw_ctrl_inst|send_data_num[1]~14_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[1]~15 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[1]~14 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|send_data_num[1]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N3 +dffeas \data_rw_ctrl_inst|send_data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[1]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[2]~16 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[2]~16_combout = (\data_rw_ctrl_inst|send_data_num [2] & (\data_rw_ctrl_inst|send_data_num[1]~15 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [2] & (!\data_rw_ctrl_inst|send_data_num[1]~15 & VCC)) +// \data_rw_ctrl_inst|send_data_num[2]~17 = CARRY((\data_rw_ctrl_inst|send_data_num [2] & !\data_rw_ctrl_inst|send_data_num[1]~15 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [2]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[1]~15 ), + .combout(\data_rw_ctrl_inst|send_data_num[2]~16_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[2]~17 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[2]~16 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[2]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N5 +dffeas \data_rw_ctrl_inst|send_data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[2]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~0_combout = (\data_rw_ctrl_inst|send_data_num [3] & (\data_rw_ctrl_inst|send_data_num [1] & (\data_rw_ctrl_inst|send_data_num [2] & \data_rw_ctrl_inst|send_data_num [0]))) + + .dataa(\data_rw_ctrl_inst|send_data_num [3]), + .datab(\data_rw_ctrl_inst|send_data_num [1]), + .datac(\data_rw_ctrl_inst|send_data_num [2]), + .datad(\data_rw_ctrl_inst|send_data_num [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~0 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[4]~20 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[4]~20_combout = (\data_rw_ctrl_inst|send_data_num [4] & (\data_rw_ctrl_inst|send_data_num[3]~19 $ (GND))) # (!\data_rw_ctrl_inst|send_data_num [4] & (!\data_rw_ctrl_inst|send_data_num[3]~19 & VCC)) +// \data_rw_ctrl_inst|send_data_num[4]~21 = CARRY((\data_rw_ctrl_inst|send_data_num [4] & !\data_rw_ctrl_inst|send_data_num[3]~19 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|send_data_num [4]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[3]~19 ), + .combout(\data_rw_ctrl_inst|send_data_num[4]~20_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[4]~21 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[4]~20 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|send_data_num[4]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N9 +dffeas \data_rw_ctrl_inst|send_data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[4]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_num[5]~22 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_num[5]~22_combout = (\data_rw_ctrl_inst|send_data_num [5] & (!\data_rw_ctrl_inst|send_data_num[4]~21 )) # (!\data_rw_ctrl_inst|send_data_num [5] & ((\data_rw_ctrl_inst|send_data_num[4]~21 ) # (GND))) +// \data_rw_ctrl_inst|send_data_num[5]~23 = CARRY((!\data_rw_ctrl_inst|send_data_num[4]~21 ) # (!\data_rw_ctrl_inst|send_data_num [5])) + + .dataa(\data_rw_ctrl_inst|send_data_num [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|send_data_num[4]~21 ), + .combout(\data_rw_ctrl_inst|send_data_num[5]~22_combout ), + .cout(\data_rw_ctrl_inst|send_data_num[5]~23 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[5]~22 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|send_data_num[5]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y26_N15 +dffeas \data_rw_ctrl_inst|send_data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[7]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y26_N11 +dffeas \data_rw_ctrl_inst|send_data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_num[5]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\data_rw_ctrl_inst|send_data_en~q ), + .sload(gnd), + .ena(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_num [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_num[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~1 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~1_combout = (\data_rw_ctrl_inst|send_data_num [6] & (\data_rw_ctrl_inst|send_data_num [7] & (\data_rw_ctrl_inst|send_data_num [4] & \data_rw_ctrl_inst|send_data_num [5]))) + + .dataa(\data_rw_ctrl_inst|send_data_num [6]), + .datab(\data_rw_ctrl_inst|send_data_num [7]), + .datac(\data_rw_ctrl_inst|send_data_num [4]), + .datad(\data_rw_ctrl_inst|send_data_num [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~1 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|always3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y26_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|always3~3 ( +// Equation(s): +// \data_rw_ctrl_inst|always3~3_combout = (\data_rw_ctrl_inst|always3~2_combout & (\data_rw_ctrl_inst|always3~0_combout & (\data_rw_ctrl_inst|always3~1_combout & \data_rw_ctrl_inst|Equal2~4_combout ))) + + .dataa(\data_rw_ctrl_inst|always3~2_combout ), + .datab(\data_rw_ctrl_inst|always3~0_combout ), + .datac(\data_rw_ctrl_inst|always3~1_combout ), + .datad(\data_rw_ctrl_inst|Equal2~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|always3~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|always3~3 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|always3~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|send_data_en~0 ( +// Equation(s): +// \data_rw_ctrl_inst|send_data_en~0_combout = (!\data_rw_ctrl_inst|always3~3_combout & ((\data_rw_ctrl_inst|send_data_en~q ) # ((!\sd_ctrl_inst|sd_read_inst|state.IDLE~q & \data_rw_ctrl_inst|rd_busy_dly~q )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.IDLE~q ), + .datab(\data_rw_ctrl_inst|rd_busy_dly~q ), + .datac(\data_rw_ctrl_inst|send_data_en~q ), + .datad(\data_rw_ctrl_inst|always3~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|send_data_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_en~0 .lut_mask = 16'h00F4; +defparam \data_rw_ctrl_inst|send_data_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N23 +dffeas \data_rw_ctrl_inst|send_data_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|send_data_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|send_data_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|send_data_en .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|send_data_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal3~1 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal3~1_combout = (\data_rw_ctrl_inst|cnt_wait [0]) # ((\data_rw_ctrl_inst|cnt_wait [3]) # ((\data_rw_ctrl_inst|cnt_wait [2]) # (\data_rw_ctrl_inst|cnt_wait [1]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [0]), + .datab(\data_rw_ctrl_inst|cnt_wait [3]), + .datac(\data_rw_ctrl_inst|cnt_wait [2]), + .datad(\data_rw_ctrl_inst|cnt_wait [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal3~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal3~1 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|Equal3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~26 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[13]~26_combout = ((\data_rw_ctrl_inst|Equal2~2_combout & (!\data_rw_ctrl_inst|Equal3~0_combout & !\data_rw_ctrl_inst|Equal3~1_combout ))) # (!\data_rw_ctrl_inst|send_data_en~q ) + + .dataa(\data_rw_ctrl_inst|Equal2~2_combout ), + .datab(\data_rw_ctrl_inst|Equal3~0_combout ), + .datac(\data_rw_ctrl_inst|send_data_en~q ), + .datad(\data_rw_ctrl_inst|Equal3~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .lut_mask = 16'h0F2F; +defparam \data_rw_ctrl_inst|cnt_wait[13]~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y27_N1 +dffeas \data_rw_ctrl_inst|cnt_wait[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[0]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[1]~18 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[1]~18_combout = (\data_rw_ctrl_inst|cnt_wait [1] & (!\data_rw_ctrl_inst|cnt_wait[0]~17 )) # (!\data_rw_ctrl_inst|cnt_wait [1] & ((\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[1]~19 = CARRY((!\data_rw_ctrl_inst|cnt_wait[0]~17 ) # (!\data_rw_ctrl_inst|cnt_wait [1])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [1]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[0]~17 ), + .combout(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[1]~19 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|cnt_wait[1]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N3 +dffeas \data_rw_ctrl_inst|cnt_wait[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[1]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[2]~20 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[2]~20_combout = (\data_rw_ctrl_inst|cnt_wait [2] & (\data_rw_ctrl_inst|cnt_wait[1]~19 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [2] & (!\data_rw_ctrl_inst|cnt_wait[1]~19 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[2]~21 = CARRY((\data_rw_ctrl_inst|cnt_wait [2] & !\data_rw_ctrl_inst|cnt_wait[1]~19 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [2]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[1]~19 ), + .combout(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[2]~21 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[2]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N5 +dffeas \data_rw_ctrl_inst|cnt_wait[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[2]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y27_N7 +dffeas \data_rw_ctrl_inst|cnt_wait[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[3]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~3 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~3_combout = (\data_rw_ctrl_inst|cnt_wait [0] & (\data_rw_ctrl_inst|cnt_wait [3] & (\data_rw_ctrl_inst|cnt_wait [2] & \data_rw_ctrl_inst|cnt_wait [1]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [0]), + .datab(\data_rw_ctrl_inst|cnt_wait [3]), + .datac(\data_rw_ctrl_inst|cnt_wait [2]), + .datad(\data_rw_ctrl_inst|cnt_wait [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~3 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|Equal2~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[6]~29 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[6]~29_combout = (\data_rw_ctrl_inst|cnt_wait [6] & (\data_rw_ctrl_inst|cnt_wait[5]~28 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [6] & (!\data_rw_ctrl_inst|cnt_wait[5]~28 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[6]~30 = CARRY((\data_rw_ctrl_inst|cnt_wait [6] & !\data_rw_ctrl_inst|cnt_wait[5]~28 )) + + .dataa(\data_rw_ctrl_inst|cnt_wait [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[5]~28 ), + .combout(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[6]~30 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .lut_mask = 16'hA50A; +defparam \data_rw_ctrl_inst|cnt_wait[6]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[7]~31 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[7]~31_combout = (\data_rw_ctrl_inst|cnt_wait [7] & (!\data_rw_ctrl_inst|cnt_wait[6]~30 )) # (!\data_rw_ctrl_inst|cnt_wait [7] & ((\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[7]~32 = CARRY((!\data_rw_ctrl_inst|cnt_wait[6]~30 ) # (!\data_rw_ctrl_inst|cnt_wait [7])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [7]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[6]~30 ), + .combout(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[7]~32 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|cnt_wait[7]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N15 +dffeas \data_rw_ctrl_inst|cnt_wait[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[7]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[8]~33 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[8]~33_combout = (\data_rw_ctrl_inst|cnt_wait [8] & (\data_rw_ctrl_inst|cnt_wait[7]~32 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [8] & (!\data_rw_ctrl_inst|cnt_wait[7]~32 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[8]~34 = CARRY((\data_rw_ctrl_inst|cnt_wait [8] & !\data_rw_ctrl_inst|cnt_wait[7]~32 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [8]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[7]~32 ), + .combout(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[8]~34 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[8]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N17 +dffeas \data_rw_ctrl_inst|cnt_wait[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[8]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[9]~35 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[9]~35_combout = (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait[8]~34 )) # (!\data_rw_ctrl_inst|cnt_wait [9] & ((\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[9]~36 = CARRY((!\data_rw_ctrl_inst|cnt_wait[8]~34 ) # (!\data_rw_ctrl_inst|cnt_wait [9])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [9]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[8]~34 ), + .combout(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[9]~36 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .lut_mask = 16'h3C3F; +defparam \data_rw_ctrl_inst|cnt_wait[9]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N19 +dffeas \data_rw_ctrl_inst|cnt_wait[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[9]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[10]~37 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[10]~37_combout = (\data_rw_ctrl_inst|cnt_wait [10] & (\data_rw_ctrl_inst|cnt_wait[9]~36 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait[9]~36 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[10]~38 = CARRY((\data_rw_ctrl_inst|cnt_wait [10] & !\data_rw_ctrl_inst|cnt_wait[9]~36 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [10]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[9]~36 ), + .combout(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[10]~38 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[10]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N21 +dffeas \data_rw_ctrl_inst|cnt_wait[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[10]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[10] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[11]~39 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[11]~39_combout = (\data_rw_ctrl_inst|cnt_wait [11] & (!\data_rw_ctrl_inst|cnt_wait[10]~38 )) # (!\data_rw_ctrl_inst|cnt_wait [11] & ((\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[11]~40 = CARRY((!\data_rw_ctrl_inst|cnt_wait[10]~38 ) # (!\data_rw_ctrl_inst|cnt_wait [11])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[10]~38 ), + .combout(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[11]~40 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[11]~39 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[12]~41 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[12]~41_combout = (\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait[11]~40 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [12] & (!\data_rw_ctrl_inst|cnt_wait[11]~40 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[12]~42 = CARRY((\data_rw_ctrl_inst|cnt_wait [12] & !\data_rw_ctrl_inst|cnt_wait[11]~40 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [12]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[11]~40 ), + .combout(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[12]~42 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[12]~41 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N25 +dffeas \data_rw_ctrl_inst|cnt_wait[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[12]~41_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [12]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[12] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[13]~43 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[13]~43_combout = (\data_rw_ctrl_inst|cnt_wait [13] & (!\data_rw_ctrl_inst|cnt_wait[12]~42 )) # (!\data_rw_ctrl_inst|cnt_wait [13] & ((\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (GND))) +// \data_rw_ctrl_inst|cnt_wait[13]~44 = CARRY((!\data_rw_ctrl_inst|cnt_wait[12]~42 ) # (!\data_rw_ctrl_inst|cnt_wait [13])) + + .dataa(\data_rw_ctrl_inst|cnt_wait [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[12]~42 ), + .combout(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[13]~44 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .lut_mask = 16'h5A5F; +defparam \data_rw_ctrl_inst|cnt_wait[13]~43 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[14]~45 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[14]~45_combout = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait[13]~44 $ (GND))) # (!\data_rw_ctrl_inst|cnt_wait [14] & (!\data_rw_ctrl_inst|cnt_wait[13]~44 & VCC)) +// \data_rw_ctrl_inst|cnt_wait[14]~46 = CARRY((\data_rw_ctrl_inst|cnt_wait [14] & !\data_rw_ctrl_inst|cnt_wait[13]~44 )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|cnt_wait [14]), + .datac(gnd), + .datad(vcc), + .cin(\data_rw_ctrl_inst|cnt_wait[13]~44 ), + .combout(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ), + .cout(\data_rw_ctrl_inst|cnt_wait[14]~46 )); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .lut_mask = 16'hC30C; +defparam \data_rw_ctrl_inst|cnt_wait[14]~45 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N29 +dffeas \data_rw_ctrl_inst|cnt_wait[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[14]~45_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [14]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[14] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|cnt_wait[15]~47 ( +// Equation(s): +// \data_rw_ctrl_inst|cnt_wait[15]~47_combout = \data_rw_ctrl_inst|cnt_wait [15] $ (\data_rw_ctrl_inst|cnt_wait[14]~46 ) + + .dataa(\data_rw_ctrl_inst|cnt_wait [15]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_rw_ctrl_inst|cnt_wait[14]~46 ), + .combout(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|cnt_wait[15]~47 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X14_Y27_N31 +dffeas \data_rw_ctrl_inst|cnt_wait[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[15]~47_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [15]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[15] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[15] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y27_N13 +dffeas \data_rw_ctrl_inst|cnt_wait[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[6]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~0 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~0_combout = (!\data_rw_ctrl_inst|cnt_wait [7] & (\data_rw_ctrl_inst|cnt_wait [9] & (!\data_rw_ctrl_inst|cnt_wait [8] & \data_rw_ctrl_inst|cnt_wait [6]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [7]), + .datab(\data_rw_ctrl_inst|cnt_wait [9]), + .datac(\data_rw_ctrl_inst|cnt_wait [8]), + .datad(\data_rw_ctrl_inst|cnt_wait [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~0 .lut_mask = 16'h0400; +defparam \data_rw_ctrl_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y27_N27 +dffeas \data_rw_ctrl_inst|cnt_wait[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[13]~43_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [13]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[13] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y27_N23 +dffeas \data_rw_ctrl_inst|cnt_wait[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|cnt_wait[11]~39_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\data_rw_ctrl_inst|cnt_wait[13]~26_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|cnt_wait [11]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|cnt_wait[11] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|cnt_wait[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~1 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~1_combout = (!\data_rw_ctrl_inst|cnt_wait [10] & (!\data_rw_ctrl_inst|cnt_wait [12] & (\data_rw_ctrl_inst|cnt_wait [13] & \data_rw_ctrl_inst|cnt_wait [11]))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [10]), + .datab(\data_rw_ctrl_inst|cnt_wait [12]), + .datac(\data_rw_ctrl_inst|cnt_wait [13]), + .datad(\data_rw_ctrl_inst|cnt_wait [11]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~1 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~2 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~2_combout = (\data_rw_ctrl_inst|cnt_wait [14] & (\data_rw_ctrl_inst|cnt_wait [15] & (\data_rw_ctrl_inst|Equal2~0_combout & \data_rw_ctrl_inst|Equal2~1_combout ))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [14]), + .datab(\data_rw_ctrl_inst|cnt_wait [15]), + .datac(\data_rw_ctrl_inst|Equal2~0_combout ), + .datad(\data_rw_ctrl_inst|Equal2~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~2 .lut_mask = 16'h8000; +defparam \data_rw_ctrl_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|Equal2~4 ( +// Equation(s): +// \data_rw_ctrl_inst|Equal2~4_combout = (!\data_rw_ctrl_inst|cnt_wait [5] & (\data_rw_ctrl_inst|Equal2~3_combout & (\data_rw_ctrl_inst|cnt_wait [4] & \data_rw_ctrl_inst|Equal2~2_combout ))) + + .dataa(\data_rw_ctrl_inst|cnt_wait [5]), + .datab(\data_rw_ctrl_inst|Equal2~3_combout ), + .datac(\data_rw_ctrl_inst|cnt_wait [4]), + .datad(\data_rw_ctrl_inst|Equal2~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|Equal2~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|Equal2~4 .lut_mask = 16'h4000; +defparam \data_rw_ctrl_inst|Equal2~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y27_N7 +dffeas \data_rw_ctrl_inst|rd_fifo_rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|Equal2~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|rd_fifo_rd_en .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|rd_fifo_rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0300; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h5A5A; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [1]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y25_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|LessThan2~0_combout = (\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]) # ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]) # (\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|cnt_data_num [6]), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_num [5]), + .datac(\sd_ctrl_inst|sd_read_inst|cnt_data_num [0]), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [7]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .lut_mask = 16'hFFFE; +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|LessThan2~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|LessThan2~1_combout = ((\sd_ctrl_inst|sd_read_inst|cnt_data_num [8] & ((\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ) # (!\sd_ctrl_inst|sd_read_inst|always3~0_combout )))) # (!\sd_ctrl_inst|sd_read_inst|always3~2_combout ) + + .dataa(\sd_ctrl_inst|sd_read_inst|always3~2_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|always3~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|cnt_data_num [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .lut_mask = 16'hDF55; +defparam \sd_ctrl_inst|sd_read_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_en~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .lut_mask = 16'h0080; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N9 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y28_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9] + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .lut_mask = 16'hF0F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'hEBD7; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [5]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y27_N15 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h1000; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y28_N15 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [5]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [5]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [4]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y27_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [3]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2_combout ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1_combout ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .lut_mask = 16'hF0C0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hE1F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout & +// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0020; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .lut_mask = 16'h0100; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0300; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'hC3F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h3C3C; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N10 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2] $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0])) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h3CC3; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_en~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q +// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout )))) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_en~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0_combout ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0A08; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y27_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h78F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y27_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout & +// !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0020; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hD2F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'h3CF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y27_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y27_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [8]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [9]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [8]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y28_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [7]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y27_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~q ), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y28_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [6]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y28_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y28_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [6]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [7]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .lut_mask = 16'h7DBE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N4 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N5 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X30_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [2]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X30_Y28_N1 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [3]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N7 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X30_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X30_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [2]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [3]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout = +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ) # +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3_combout ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1_combout ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .lut_mask = 16'hFFFE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout & (\data_rw_ctrl_inst|rd_fifo_rd_en~q +// & ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0_combout ), + .datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .lut_mask = 16'h8880; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N6 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h2000; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y27_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y27_N31 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N0 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout = (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2] & +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] & (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0100; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N16 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .lut_mask = 16'h5AF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .lut_mask = 16'hB4F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N20 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9] $ +// (((!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] & \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .lut_mask = 16'hC3F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N21 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [8]), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .lut_mask = 16'h55AA; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b [9]), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [5]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [7]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [4]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [6]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h6996; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N15 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N28 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [3]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [2]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h9669; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N29 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q $ (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q )) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1~q ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h3CC3; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] $ +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'hF00F; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y28_N26 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1] $ +// (((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout & (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0] & +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q )))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0_combout ), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [0]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .lut_mask = 16'h78F0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y28_N27 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N24 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h3333; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N25 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N22 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [0]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N23 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y27_N11 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N9 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [0]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X28_Y28_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y28_N17 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g [1]), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N2 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y28_N3 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .power_up = "low"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout = (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1])) # +// (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]))) # (!\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0] & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1])))) + + .dataa(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [0]), + .datab(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g [1]), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a [1]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .lut_mask = 16'h7BDE; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y28_N30 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout = (\data_rw_ctrl_inst|rd_fifo_rd_en~q & +// ((\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ) # +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ))) + + .dataa(gnd), + .datab(\data_rw_ctrl_inst|rd_fifo_rd_en~q ), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0_combout ), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5_combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hCCC0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout = (\sd_miso~input_o & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_miso~input_o ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N7 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N30 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~13_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout = ((\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3] & (\sd_ctrl_inst|sd_read_inst|Equal9~0_combout & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) # (!\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|cnt_data_bit [3]), + .datac(\sd_ctrl_inst|sd_read_inst|Equal9~0_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .lut_mask = 16'h55D5; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N31 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [0]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [0]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N1 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N12 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [1]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N13 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N19 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N17 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y24_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .lut_mask = 16'h0200; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y24_N23 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N21 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N22 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N23 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & !\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]), + .datad(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N17 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~14 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~14_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N3 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y27_N18 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .lut_mask = 16'hFF00; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y27_N19 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y27_N8 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8] = \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8] $ +// (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [8]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a [8]), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .lut_mask = 16'h0FF0; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N12 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~combout ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .lut_mask = 16'h00FF; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y28_N13 +dffeas \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .is_wysiwyg = "true"; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y28_N14 +cycloneive_lcell_comb \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell ( +// Equation(s): +// \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout = !\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~q ), + .cin(gnd), + .combout(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .lut_mask = 16'h00FF; +defparam \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N16 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~15_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [1] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(gnd), + .datab(\sd_ctrl_inst|sd_read_inst|rd_data_reg [1]), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .lut_mask = 16'hC0C0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N17 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~11 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~11_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [2]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N29 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N0 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~7 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~7_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [3]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N1 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~5 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~5_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [4]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N5 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~3_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [5]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [5]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N19 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~9 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~9_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [6]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N7 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~0 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~0_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [7] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [7]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N25 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout = (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (!\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [8]))) + + .dataa(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datab(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [8]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .lut_mask = 16'h1000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N11 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N28 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~16 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~16_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [9]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N29 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N8 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~12 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~12_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [10] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [10]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N9 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y27_N4 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~8 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~8_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [11] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [11]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y27_N5 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N6 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~6 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~6_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N7 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N20 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [12] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [12]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N21 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N10 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~4 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~4_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [13]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [13]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N11 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N2 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~10 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~10_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & \sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .lut_mask = 16'hA0A0; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N3 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[14] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N18 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout = (\sd_ctrl_inst|sd_read_inst|rd_data_reg [14] & (!\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout & (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & !\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ))) + + .dataa(\sd_ctrl_inst|sd_read_inst|rd_data_reg [14]), + .datab(\sd_ctrl_inst|sd_read_inst|byte_head_en~1_combout ), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .lut_mask = 16'h0020; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N19 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data_reg~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y27_N24 +cycloneive_lcell_comb \sd_ctrl_inst|sd_read_inst|rd_data~2 ( +// Equation(s): +// \sd_ctrl_inst|sd_read_inst|rd_data~2_combout = (\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q & \sd_ctrl_inst|sd_read_inst|rd_data_reg [15]) + + .dataa(gnd), + .datab(gnd), + .datac(\sd_ctrl_inst|sd_read_inst|state.RD_DATA~q ), + .datad(\sd_ctrl_inst|sd_read_inst|rd_data_reg [15]), + .cin(gnd), + .combout(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ), + .cout()); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .lut_mask = 16'hF000; +defparam \sd_ctrl_inst|sd_read_inst|rd_data~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y27_N25 +dffeas \sd_ctrl_inst|sd_read_inst|rd_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sd_ctrl_inst|sd_read_inst|rd_data~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sd_ctrl_inst|sd_read_inst|rd_data[6]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sd_ctrl_inst|sd_read_inst|rd_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .is_wysiwyg = "true"; +defparam \sd_ctrl_inst|sd_read_inst|rd_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N20 +cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( +// Equation(s): +// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [3] & (((\uart_tx_inst|bit_cnt [0]) # (\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7])) # (!\uart_tx_inst|always0~0_combout ))) + + .dataa(\uart_tx_inst|always0~0_combout ), + .datab(\uart_tx_inst|bit_cnt [3]), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|q_b [7]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hCCC4; +defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y27_N8 +cycloneive_lcell_comb \uart_tx_inst|tx~0 ( +// Equation(s): +// \uart_tx_inst|tx~0_combout = (\uart_tx_inst|bit_flag~q & (!\uart_tx_inst|Mux0~5_combout & ((!\uart_tx_inst|Mux0~0_combout )))) # (!\uart_tx_inst|bit_flag~q & (((\uart_tx_inst|tx~q )))) + + .dataa(\uart_tx_inst|Mux0~5_combout ), + .datab(\uart_tx_inst|bit_flag~q ), + .datac(\uart_tx_inst|tx~q ), + .datad(\uart_tx_inst|Mux0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~0 .lut_mask = 16'h3074; +defparam \uart_tx_inst|tx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y27_N9 +dffeas \uart_tx_inst|tx ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_tx_inst|tx~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|tx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|tx .is_wysiwyg = "true"; +defparam \uart_tx_inst|tx .power_up = "low"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_min_1200mv_0c_v_fast.sdo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_min_1200mv_0c_v_fast.sdo new file mode 100644 index 0000000..d3b225b --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_min_1200mv_0c_v_fast.sdo @@ -0,0 +1,19061 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Fast Corner delays for the design using part EP4CE15F23C8, +// with speed grade M, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "uart_sd") + (DATE "06/02/2023 04:03:15") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (2025:2025:2025) (2025:2025:2025)) + (PORT inclk[0] (1104:1104:1104) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (433:433:433)) + (PORT datab (303:303:303) (363:363:363)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (303:303:303) (367:367:367)) + (PORT datab (465:465:465) (550:550:550)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (257:257:257)) + (PORT datab (131:131:131) (179:179:179)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (PORT sclr (682:682:682) (644:644:644)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (874:874:874)) + (PORT sclr (1252:1252:1252) (1160:1160:1160)) + (PORT ena (488:488:488) (520:520:520)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (874:874:874)) + (PORT sclr (1252:1252:1252) (1160:1160:1160)) + (PORT ena (488:488:488) (520:520:520)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (874:874:874)) + (PORT sclr (1252:1252:1252) (1160:1160:1160)) + (PORT ena (488:488:488) (520:520:520)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (870:870:870)) + (PORT sclr (1357:1357:1357) (1249:1249:1249)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (866:866:866) (872:872:872)) + (PORT sclr (1174:1174:1174) (1088:1088:1088)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (571:571:571) (678:678:678)) + (PORT d[1] (558:558:558) (658:658:658)) + (PORT d[2] (586:586:586) (698:698:698)) + (PORT d[3] (670:670:670) (793:793:793)) + (PORT d[4] (568:568:568) (674:674:674)) + (PORT d[5] (674:674:674) (798:798:798)) + (PORT d[6] (575:575:575) (684:684:684)) + (PORT d[7] (574:574:574) (682:682:682)) + (PORT clk (1063:1063:1063) (1083:1083:1083)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (412:412:412) (491:491:491)) + (PORT d[1] (435:435:435) (517:517:517)) + (PORT d[2] (515:515:515) (602:602:602)) + (PORT d[3] (445:445:445) (522:522:522)) + (PORT d[4] (414:414:414) (494:494:494)) + (PORT d[5] (727:727:727) (853:853:853)) + (PORT d[6] (559:559:559) (667:667:667)) + (PORT d[7] (721:721:721) (835:835:835)) + (PORT d[8] (420:420:420) (506:506:506)) + (PORT d[9] (381:381:381) (439:439:439)) + (PORT clk (1061:1061:1061) (1081:1081:1081)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (527:527:527) (542:542:542)) + (PORT clk (1061:1061:1061) (1081:1081:1081)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1063:1063:1063) (1083:1083:1083)) + (PORT d[0] (811:811:811) (835:835:835)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1084:1084:1084)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1084:1084:1084)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1084:1084:1084)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1064:1064:1064) (1084:1084:1084)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (543:543:543) (629:629:629)) + (PORT d[1] (413:413:413) (490:490:490)) + (PORT d[2] (743:743:743) (863:863:863)) + (PORT d[3] (752:752:752) (870:870:870)) + (PORT d[4] (692:692:692) (822:822:822)) + (PORT d[5] (787:787:787) (921:921:921)) + (PORT d[6] (566:566:566) (657:657:657)) + (PORT d[7] (607:607:607) (712:712:712)) + (PORT d[8] (381:381:381) (447:447:447)) + (PORT clk (1020:1020:1020) (1042:1042:1042)) + (PORT stall (788:788:788) (738:738:738)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + (HOLD stall (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1020:1020:1020) (1042:1042:1042)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1021:1021:1021) (1043:1043:1043)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1021:1021:1021) (1043:1043:1043)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1021:1021:1021) (1043:1043:1043)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1019:1019:1019) (1041:1041:1041)) + (PORT ena (862:862:862) (920:920:920)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (SETUP ena (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + (HOLD ena (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (477:477:477) (549:549:549)) + (PORT d[1] (467:467:467) (537:537:537)) + (PORT d[2] (477:477:477) (547:547:547)) + (PORT d[3] (639:639:639) (731:731:731)) + (PORT d[4] (475:475:475) (551:551:551)) + (PORT d[5] (465:465:465) (539:539:539)) + (PORT d[6] (479:479:479) (552:552:552)) + (PORT d[7] (475:475:475) (548:548:548)) + (PORT d[9] (468:468:468) (541:541:541)) + (PORT d[10] (517:517:517) (596:596:596)) + (PORT d[11] (517:517:517) (586:586:586)) + (PORT d[12] (478:478:478) (554:554:554)) + (PORT d[13] (613:613:613) (703:703:703)) + (PORT d[14] (468:468:468) (538:538:538)) + (PORT d[15] (637:637:637) (721:721:721)) + (PORT d[16] (632:632:632) (726:726:726)) + (PORT clk (1070:1070:1070) (1088:1088:1088)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (548:548:548) (647:647:647)) + (PORT d[1] (510:510:510) (598:598:598)) + (PORT d[2] (659:659:659) (768:768:768)) + (PORT d[3] (477:477:477) (562:562:562)) + (PORT d[4] (402:402:402) (480:480:480)) + (PORT d[5] (705:705:705) (817:817:817)) + (PORT d[6] (681:681:681) (794:794:794)) + (PORT d[7] (386:386:386) (465:465:465)) + (PORT d[8] (626:626:626) (712:712:712)) + (PORT clk (1068:1068:1068) (1086:1086:1086)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (534:534:534) (553:553:553)) + (PORT clk (1068:1068:1068) (1086:1086:1086)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1070:1070:1070) (1088:1088:1088)) + (PORT d[0] (818:818:818) (846:846:846)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1089:1089:1089)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1089:1089:1089)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1089:1089:1089)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1071:1071:1071) (1089:1089:1089)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (522:522:522) (600:600:600)) + (PORT d[1] (753:753:753) (874:874:874)) + (PORT d[2] (611:611:611) (724:724:724)) + (PORT d[3] (414:414:414) (493:493:493)) + (PORT d[4] (428:428:428) (509:509:509)) + (PORT d[5] (655:655:655) (779:779:779)) + (PORT d[6] (402:402:402) (480:480:480)) + (PORT d[7] (548:548:548) (643:643:643)) + (PORT d[8] (527:527:527) (615:615:615)) + (PORT d[9] (672:672:672) (760:760:760)) + (PORT clk (1027:1027:1027) (1047:1047:1047)) + (PORT stall (607:607:607) (589:589:589)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + (HOLD stall (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1027:1027:1027) (1047:1047:1047)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1028:1028:1028) (1048:1048:1048)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1028:1028:1028) (1048:1048:1048)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1028:1028:1028) (1048:1048:1048)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1026:1026:1026) (1046:1046:1046)) + (PORT ena (714:714:714) (740:740:740)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (SETUP ena (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + (HOLD ena (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sclr (670:670:670) (642:642:642)) + (PORT ena (488:488:488) (518:518:518)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sclr (670:670:670) (642:642:642)) + (PORT ena (488:488:488) (518:518:518)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sclr (670:670:670) (642:642:642)) + (PORT ena (488:488:488) (518:518:518)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sclr (670:670:670) (642:642:642)) + (PORT ena (488:488:488) (518:518:518)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (PORT sload (417:417:417) (459:459:459)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (278:278:278)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (152:152:152) (211:211:211)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (866:866:866) (872:872:872)) + (PORT sclr (1174:1174:1174) (1088:1088:1088)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (866:866:866) (872:872:872)) + (PORT sclr (1174:1174:1174) (1088:1088:1088)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (PORT sclr (384:384:384) (390:390:390)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (PORT sclr (384:384:384) (390:390:390)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (203:203:203)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (201:201:201)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (546:546:546) (634:634:634)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (546:546:546) (634:634:634)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (546:546:546) (634:634:634)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (189:189:189)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (189:189:189)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (188:188:188)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (204:204:204)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (189:189:189)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (196:196:196)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0) + (DELAY + (ABSOLUTE + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (866:866:866)) + (PORT sclr (653:653:653) (627:627:627)) + (PORT ena (639:639:639) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (866:866:866)) + (PORT sclr (653:653:653) (627:627:627)) + (PORT ena (639:639:639) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (866:866:866)) + (PORT sclr (653:653:653) (627:627:627)) + (PORT ena (639:639:639) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (866:866:866)) + (PORT sclr (653:653:653) (627:627:627)) + (PORT ena (639:639:639) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (866:866:866)) + (PORT sclr (653:653:653) (627:627:627)) + (PORT ena (639:639:639) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (866:866:866)) + (PORT sclr (653:653:653) (627:627:627)) + (PORT ena (639:639:639) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (196:196:196)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (189:189:189)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (191:191:191)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (188:188:188)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT datac (306:306:306) (369:369:369)) + (PORT datad (126:126:126) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD55) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (285:285:285)) + (PORT datac (214:214:214) (267:267:267)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (PORT datab (211:211:211) (267:267:267)) + (PORT datac (120:120:120) (163:163:163)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (273:273:273)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~0) + (DELAY + (ABSOLUTE + (PORT datac (199:199:199) (248:248:248)) + (PORT datad (170:170:170) (201:201:201)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~1) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (242:242:242) (300:300:300)) + (PORT datac (825:825:825) (951:951:951)) + (PORT datad (429:429:429) (490:490:490)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (204:204:204)) + (PORT datab (146:146:146) (200:200:200)) + (PORT datac (130:130:130) (177:177:177)) + (PORT datad (131:131:131) (174:174:174)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (282:282:282)) + (PORT datab (166:166:166) (227:227:227)) + (PORT datac (389:389:389) (446:446:446)) + (PORT datad (207:207:207) (243:243:243)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (473:473:473)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (207:207:207) (247:247:247)) + (PORT datad (154:154:154) (206:206:206)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (291:291:291)) + (PORT datab (157:157:157) (211:211:211)) + (PORT datac (229:229:229) (272:272:272)) + (PORT datad (154:154:154) (207:207:207)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (140:140:140)) + (PORT datab (158:158:158) (212:212:212)) + (PORT datac (684:684:684) (777:777:777)) + (PORT datad (396:396:396) (457:457:457)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (282:282:282)) + (PORT datab (161:161:161) (222:222:222)) + (PORT datac (379:379:379) (436:436:436)) + (PORT datad (211:211:211) (247:247:247)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (407:407:407) (475:475:475)) + (PORT datab (156:156:156) (210:210:210)) + (PORT datac (161:161:161) (189:189:189)) + (PORT datad (391:391:391) (456:456:456)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (147:147:147) (200:200:200)) + (PORT datac (142:142:142) (190:190:190)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (477:477:477)) + (PORT datab (156:156:156) (210:210:210)) + (PORT datac (224:224:224) (267:267:267)) + (PORT datad (153:153:153) (205:205:205)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (468:468:468)) + (PORT datab (168:168:168) (230:230:230)) + (PORT datac (224:224:224) (267:267:267)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (151:151:151) (206:206:206)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datab (241:241:241) (299:299:299)) + (PORT datac (214:214:214) (266:266:266)) + (PORT datad (344:344:344) (401:401:401)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (501:501:501)) + (PORT datab (448:448:448) (542:542:542)) + (PORT datac (407:407:407) (489:489:489)) + (PORT datad (413:413:413) (497:497:497)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~2) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (493:493:493)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (406:406:406) (488:488:488)) + (PORT datad (392:392:392) (478:478:478)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (414:414:414) (509:509:509)) + (PORT datab (422:422:422) (508:508:508)) + (PORT datac (423:423:423) (516:516:516)) + (PORT datad (411:411:411) (495:495:495)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~3) + (DELAY + (ABSOLUTE + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (396:396:396) (472:472:472)) + (PORT datad (370:370:370) (435:435:435)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~4) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (501:501:501)) + (PORT datab (444:444:444) (538:538:538)) + (PORT datac (396:396:396) (484:484:484)) + (PORT datad (411:411:411) (495:495:495)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~5) + (DELAY + (ABSOLUTE + (PORT dataa (415:415:415) (509:509:509)) + (PORT datab (421:421:421) (508:508:508)) + (PORT datac (395:395:395) (471:471:471)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~6) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (501:501:501)) + (PORT datab (424:424:424) (510:510:510)) + (PORT datac (394:394:394) (481:481:481)) + (PORT datad (413:413:413) (496:496:496)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~7) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (492:492:492)) + (PORT datab (447:447:447) (542:542:542)) + (PORT datac (407:407:407) (489:489:489)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (159:159:159) (165:165:165)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (501:501:501)) + (PORT datab (451:451:451) (546:546:546)) + (PORT datac (408:408:408) (491:491:491)) + (PORT datad (414:414:414) (498:498:498)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~8) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (491:491:491)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (393:393:393) (480:480:480)) + (PORT datad (369:369:369) (434:434:434)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~9) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (372:372:372) (437:437:437)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~10) + (DELAY + (ABSOLUTE + (PORT dataa (420:420:420) (506:506:506)) + (PORT datab (104:104:104) (134:134:134)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (890:890:890)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (869:869:869) (873:873:873)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT datac (137:137:137) (182:182:182)) + (PORT datad (141:141:141) (191:191:191)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (439:439:439)) + (PORT datab (164:164:164) (223:223:223)) + (PORT datac (154:154:154) (212:212:212)) + (PORT datad (346:346:346) (401:401:401)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (163:163:163) (222:222:222)) + (PORT datac (345:345:345) (395:395:395)) + (PORT datad (352:352:352) (406:406:406)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (410:410:410)) + (PORT datab (170:170:170) (233:233:233)) + (PORT datac (330:330:330) (376:376:376)) + (PORT datad (148:148:148) (198:198:198)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~4) + (DELAY + (ABSOLUTE + (PORT datab (171:171:171) (235:235:235)) + (PORT datac (333:333:333) (380:380:380)) + (PORT datad (149:149:149) (199:199:199)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (138:138:138) (184:184:184)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~0) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (188:188:188)) + (PORT datab (140:140:140) (191:191:191)) + (PORT datad (200:200:200) (249:249:249)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (283:283:283)) + (PORT datab (145:145:145) (198:198:198)) + (PORT datac (130:130:130) (177:177:177)) + (PORT datad (102:102:102) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~2) + (DELAY + (ABSOLUTE + (PORT datab (225:225:225) (279:279:279)) + (PORT datac (209:209:209) (259:259:259)) + (PORT datad (197:197:197) (240:240:240)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT asdata (654:654:654) (742:742:742)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (412:412:412)) + (PORT datab (474:474:474) (569:569:569)) + (PORT datac (140:140:140) (187:187:187)) + (PORT datad (99:99:99) (121:121:121)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT datab (139:139:139) (191:191:191)) + (PORT datac (146:146:146) (190:190:190)) + (PORT datad (108:108:108) (127:127:127)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (287:287:287)) + (PORT datad (100:100:100) (121:121:121)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT datab (330:330:330) (389:389:389)) + (PORT datac (308:308:308) (362:362:362)) + (PORT datad (289:289:289) (331:331:331)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT datac (308:308:308) (363:363:363)) + (PORT datad (288:288:288) (331:331:331)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datac (497:497:497) (596:596:596)) + (PORT datad (472:472:472) (548:548:548)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (190:190:190)) + (PORT datac (127:127:127) (174:174:174)) + (PORT datad (130:130:130) (173:173:173)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (209:209:209)) + (PORT datab (144:144:144) (197:197:197)) + (PORT datac (138:138:138) (184:184:184)) + (PORT datad (129:129:129) (170:170:170)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (195:195:195)) + (PORT datab (114:114:114) (147:147:147)) + (PORT datac (321:321:321) (385:385:385)) + (PORT datad (100:100:100) (122:122:122)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (440:440:440)) + (PORT datab (221:221:221) (267:267:267)) + (PORT datac (429:429:429) (484:484:484)) + (PORT datad (139:139:139) (180:180:180)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (PORT datab (136:136:136) (187:187:187)) + (PORT datad (120:120:120) (159:159:159)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT datab (384:384:384) (449:449:449)) + (PORT datac (287:287:287) (330:330:330)) + (PORT datad (142:142:142) (184:184:184)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (196:196:196)) + (PORT datab (113:113:113) (147:147:147)) + (PORT datac (320:320:320) (385:385:385)) + (PORT datad (99:99:99) (121:121:121)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (458:458:458) (542:542:542)) + (PORT datab (149:149:149) (204:204:204)) + (PORT datac (130:130:130) (178:178:178)) + (PORT datad (179:179:179) (213:213:213)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (175:175:175) (211:211:211)) + (PORT datad (307:307:307) (361:361:361)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (214:214:214)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (185:185:185) (216:216:216)) + (PORT datad (380:380:380) (464:464:464)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (PORT datab (134:134:134) (183:183:183)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (207:207:207)) + (PORT datab (137:137:137) (187:187:187)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (132:132:132) (176:176:176)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (204:204:204)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datad (97:97:97) (118:118:118)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.CMD24_ACK) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datab (191:191:191) (229:229:229)) + (PORT datac (179:179:179) (208:208:208)) + (PORT datad (134:134:134) (172:172:172)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (269:269:269)) + (PORT datab (166:166:166) (228:228:228)) + (PORT datad (134:134:134) (179:179:179)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT asdata (520:520:520) (585:585:585)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (436:436:436)) + (PORT datab (334:334:334) (407:407:407)) + (PORT datad (347:347:347) (420:420:420)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT asdata (294:294:294) (332:332:332)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (430:430:430)) + (PORT datab (356:356:356) (429:429:429)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT asdata (294:294:294) (333:333:333)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (450:450:450)) + (PORT datab (342:342:342) (413:413:413)) + (PORT datad (341:341:341) (411:411:411)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (365:365:365) (410:410:410)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (436:436:436) (517:517:517)) + (PORT datab (338:338:338) (409:409:409)) + (PORT datad (120:120:120) (157:157:157)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (215:215:215)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (173:173:173) (204:204:204)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (446:446:446)) + (PORT datab (516:516:516) (606:606:606)) + (PORT datad (126:126:126) (168:168:168)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (703:703:703)) + (PORT datab (350:350:350) (418:418:418)) + (PORT datad (211:211:211) (255:255:255)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT ena (664:664:664) (740:740:740)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (605:605:605) (638:638:638)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[9\]) + (DELAY + (ABSOLUTE + (PORT datad (131:131:131) (168:168:168)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT ena (664:664:664) (740:740:740)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT ena (664:664:664) (740:740:740)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT asdata (299:299:299) (341:341:341)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT ena (664:664:664) (740:740:740)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT ena (664:664:664) (740:740:740)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT ena (664:664:664) (740:740:740)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT ena (664:664:664) (740:740:740)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT asdata (302:302:302) (345:345:345)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT ena (664:664:664) (740:740:740)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT asdata (497:497:497) (557:557:557)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (417:417:417)) + (PORT datab (226:226:226) (288:288:288)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (896:896:896)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (521:521:521) (555:555:555)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (888:888:888) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (888:888:888) (895:895:895)) + (PORT asdata (295:295:295) (334:334:334)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (279:279:279)) + (PORT datab (308:308:308) (375:375:375)) + (PORT datad (118:118:118) (156:156:156)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT datab (163:163:163) (225:225:225)) + (PORT datac (138:138:138) (183:183:183)) + (PORT datad (139:139:139) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (113:113:113) (146:146:146)) + (PORT datad (117:117:117) (142:142:142)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (447:447:447)) + (PORT datab (134:134:134) (184:184:184)) + (PORT datac (125:125:125) (170:170:170)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~3) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (666:666:666)) + (PORT datad (116:116:116) (137:137:137)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (294:294:294) (334:334:334)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datab (191:191:191) (228:228:228)) + (PORT datac (179:179:179) (208:208:208)) + (PORT datad (133:133:133) (171:171:171)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (924:924:924)) + (PORT datac (133:133:133) (175:175:175)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT asdata (703:703:703) (791:791:791)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT asdata (737:737:737) (840:840:840)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (310:310:310) (351:351:351)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT asdata (301:301:301) (343:343:343)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT ena (667:667:667) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT ena (667:667:667) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT ena (667:667:667) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT ena (667:667:667) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (PORT ena (434:434:434) (461:461:461)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT asdata (301:301:301) (344:344:344)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT ena (667:667:667) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT ena (667:667:667) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT ena (667:667:667) (727:727:727)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|tx_flag) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datad (430:430:430) (490:490:490)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (896:896:896)) + (PORT asdata (299:299:299) (340:340:340)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (896:896:896)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (888:888:888) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (888:888:888) (895:895:895)) + (PORT asdata (296:296:296) (335:335:335)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (583:583:583)) + (PORT datab (369:369:369) (441:441:441)) + (PORT datac (152:152:152) (198:198:198)) + (PORT datad (111:111:111) (132:132:132)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~4) + (DELAY + (ABSOLUTE + (PORT datab (177:177:177) (238:238:238)) + (PORT datac (122:122:122) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~5) + (DELAY + (ABSOLUTE + (PORT datab (177:177:177) (239:239:239)) + (PORT datac (125:125:125) (170:170:170)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~6) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (453:453:453)) + (PORT datac (162:162:162) (219:219:219)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1984:1984:1984) (2245:2245:2245)) + (PORT datad (356:356:356) (426:426:426)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (308:308:308) (348:348:348)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1797:1797:1797) (2026:2026:2026)) + (PORT datab (143:143:143) (196:196:196)) + (PORT datac (214:214:214) (267:267:267)) + (PORT datad (360:360:360) (436:436:436)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (151:151:151) (210:210:210)) + (PORT datab (143:143:143) (196:196:196)) + (PORT datac (201:201:201) (253:253:253)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (152:152:152) (209:209:209)) + (PORT datab (117:117:117) (150:150:150)) + (PORT datac (140:140:140) (186:186:186)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg3) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT asdata (878:878:878) (993:993:993)) + (PORT clrn (868:868:868) (875:875:875)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT asdata (403:403:403) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (888:888:888) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (683:683:683) (816:816:816)) + (PORT datab (516:516:516) (596:596:596)) + (PORT datac (126:126:126) (171:171:171)) + (PORT datad (470:470:470) (543:543:543)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (800:800:800)) + (PORT datab (512:512:512) (592:592:592)) + (PORT datac (120:120:120) (164:164:164)) + (PORT datad (475:475:475) (550:550:550)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (683:683:683)) + (PORT datab (355:355:355) (415:415:415)) + (PORT datac (448:448:448) (512:512:512)) + (PORT datad (121:121:121) (159:159:159)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (582:582:582)) + (PORT datab (511:511:511) (591:591:591)) + (PORT datac (648:648:648) (769:769:769)) + (PORT datad (124:124:124) (164:164:164)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~2) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (208:208:208)) + (PORT datab (153:153:153) (208:208:208)) + (PORT datac (128:128:128) (175:175:175)) + (PORT datad (125:125:125) (165:165:165)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~3) + (DELAY + (ABSOLUTE + (PORT dataa (543:543:543) (667:667:667)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (290:290:290)) + (PORT datab (324:324:324) (389:389:389)) + (PORT datac (202:202:202) (249:249:249)) + (PORT datad (200:200:200) (244:244:244)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a2) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (614:614:614) (655:655:655)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg2) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (268:268:268)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (197:197:197)) + (PORT datab (140:140:140) (192:192:192)) + (PORT datac (128:128:128) (173:173:173)) + (PORT datad (126:126:126) (167:167:167)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT datab (145:145:145) (194:194:194)) + (PORT datad (132:132:132) (169:169:169)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg1) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|start_nedge) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (193:193:193)) + (PORT datac (696:696:696) (812:812:812)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (124:124:124) (169:169:169)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (120:120:120) (164:164:164)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg1\~0) + (DELAY + (ABSOLUTE + (PORT datad (1726:1726:1726) (1921:1921:1921)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (142:142:142) (187:187:187)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rx\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (348:348:348) (728:728:728)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (209:209:209) (257:257:257)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (375:375:375) (453:453:453)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (495:495:495) (574:574:574)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (133:133:133) (170:170:170)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (205:205:205) (252:252:252)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (543:543:543) (628:628:628)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|tx_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (130:130:130) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (132:132:132) (170:170:170)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (354:354:354) (425:425:425)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (117:117:117) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (123:123:123) (162:162:162)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (120:120:120) (159:159:159)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (159:159:159)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (160:160:160)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (123:123:123) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (354:354:354) (428:428:428)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (352:352:352) (425:425:425)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (160:160:160)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (160:160:160)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (341:341:341) (411:411:411)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (300:300:300) (359:359:359)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (116:116:116) (153:153:153)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sd_clk\~output) + (DELAY + (ABSOLUTE + (PORT i (736:736:736) (766:766:766)) + (IOPATH i o (1637:1637:1637) (1617:1617:1617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sd_cs_n\~output) + (DELAY + (ABSOLUTE + (PORT i (769:769:769) (872:872:872)) + (IOPATH i o (1637:1637:1637) (1617:1617:1617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sd_mosi\~output) + (DELAY + (ABSOLUTE + (PORT i (756:756:756) (851:851:851)) + (IOPATH i o (1637:1637:1637) (1617:1617:1617)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tx\~output) + (DELAY + (ABSOLUTE + (PORT i (1453:1453:1453) (1256:1256:1256)) + (IOPATH i o (1755:1755:1755) (1782:1782:1782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (358:358:358) (738:738:738)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1120:1120:1120) (1119:1119:1119)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (150:150:150) (203:203:203)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1648:1648:1648)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2249:2249:2249) (2037:2037:2037)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1558:1558:1558) (1353:1353:1353)) + (PORT datab (1758:1758:1758) (1966:1966:1966)) + (PORT datad (120:120:120) (157:157:157)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1074:1074:1074) (1218:1218:1218)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (139:139:139) (191:191:191)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sd_miso\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|miso_dly) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT asdata (2138:2138:2138) (2396:2396:2396)) + (PORT clrn (860:860:860) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1984:1984:1984) (2245:2245:2245)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datad (202:202:202) (248:248:248)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (PORT sclr (470:470:470) (468:468:468)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (290:290:290)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (314:314:314) (369:369:369)) + (PORT datad (211:211:211) (256:256:256)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (PORT sclr (470:470:470) (468:468:468)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (271:271:271)) + (PORT datab (329:329:329) (390:390:390)) + (PORT datac (312:312:312) (367:367:367)) + (PORT datad (210:210:210) (255:255:255)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~2) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (245:245:245)) + (PORT datab (178:178:178) (219:219:219)) + (PORT datad (99:99:99) (120:120:120)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (PORT sclr (470:470:470) (468:468:468)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (191:191:191)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (PORT sclr (470:470:470) (468:468:468)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (PORT sclr (470:470:470) (468:468:468)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (PORT sclr (470:470:470) (468:468:468)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (PORT sclr (470:470:470) (468:468:468)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (PORT sclr (470:470:470) (468:468:468)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (271:271:271)) + (PORT datab (137:137:137) (187:187:187)) + (PORT datac (124:124:124) (168:168:168)) + (PORT datad (123:123:123) (163:163:163)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (282:282:282)) + (PORT datac (181:181:181) (221:221:221)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT asdata (650:650:650) (734:734:734)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (636:636:636) (690:690:690)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT asdata (299:299:299) (340:340:340)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (636:636:636) (690:690:690)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (123:123:123) (162:162:162)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (636:636:636) (690:690:690)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT asdata (375:375:375) (422:422:422)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (636:636:636) (690:690:690)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (117:117:117) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (636:636:636) (690:690:690)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT asdata (306:306:306) (346:346:346)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (636:636:636) (690:690:690)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (160:160:160)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (636:636:636) (690:690:690)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT asdata (299:299:299) (341:341:341)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (636:636:636) (690:690:690)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (190:190:190)) + (PORT datab (134:134:134) (184:184:184)) + (PORT datad (200:200:200) (243:243:243)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (300:300:300) (354:354:354)) + (PORT datac (161:161:161) (188:188:188)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (137:137:137) (189:189:189)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (139:139:139) (191:191:191)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (202:202:202)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (157:157:157) (211:211:211)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT sclr (382:382:382) (388:388:388)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (211:211:211)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT sclr (382:382:382) (388:388:388)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1856:1856:1856) (2122:2122:2122)) + (PORT datab (377:377:377) (458:458:458)) + (PORT datac (146:146:146) (195:195:195)) + (PORT datad (145:145:145) (189:189:189)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (236:236:236)) + (PORT datab (104:104:104) (134:134:134)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT sclr (382:382:382) (388:388:388)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (137:137:137) (188:188:188)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT sclr (382:382:382) (388:388:388)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT sclr (382:382:382) (388:388:388)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT sclr (382:382:382) (388:388:388)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datac (127:127:127) (174:174:174)) + (PORT datad (134:134:134) (180:180:180)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (146:146:146) (195:195:195)) + (PORT datad (145:145:145) (189:189:189)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (205:205:205)) + (PORT datab (135:135:135) (184:184:184)) + (PORT datac (143:143:143) (192:192:192)) + (PORT datad (143:143:143) (187:187:187)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (152:152:152) (206:206:206)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (152:152:152) (205:205:205)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT sclr (382:382:382) (388:388:388)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT sclr (382:382:382) (388:388:388)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (138:138:138) (184:184:184)) + (PORT datad (140:140:140) (183:183:183)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT asdata (480:480:480) (538:538:538)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT asdata (296:296:296) (335:335:335)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT asdata (293:293:293) (332:332:332)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT asdata (295:295:295) (334:334:334)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT asdata (294:294:294) (333:333:333)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT asdata (293:293:293) (332:332:332)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (124:124:124) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (123:123:123) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT asdata (377:377:377) (426:426:426)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (119:119:119) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT ena (760:760:760) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (350:350:350) (422:422:422)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (293:293:293) (332:332:332)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (296:296:296) (335:335:335)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (294:294:294) (333:333:333)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (120:120:120) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (117:117:117) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[27\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (296:296:296) (335:335:335)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[28\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (296:296:296) (336:336:336)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[29\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (294:294:294) (334:334:334)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (119:119:119) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (116:116:116) (153:153:153)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (868:868:868)) + (PORT ena (610:610:610) (650:650:650)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[32\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT asdata (470:470:470) (524:524:524)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT ena (510:510:510) (553:553:553)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (130:130:130) (172:172:172)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT ena (510:510:510) (553:553:553)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (191:191:191) (237:237:237)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT ena (510:510:510) (553:553:553)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[35\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT asdata (370:370:370) (418:418:418)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT ena (510:510:510) (553:553:553)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (266:266:266)) + (PORT datad (192:192:192) (238:238:238)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[36\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT asdata (364:364:364) (409:409:409)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT ena (510:510:510) (553:553:553)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT ena (510:510:510) (553:553:553)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (120:120:120) (159:159:159)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT ena (510:510:510) (553:553:553)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT asdata (300:300:300) (342:342:342)) + (PORT clrn (861:861:861) (867:867:867)) + (PORT ena (510:510:510) (553:553:553)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT datab (114:114:114) (147:147:147)) + (PORT datad (100:100:100) (122:122:122)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (322:322:322) (381:381:381)) + (PORT datac (132:132:132) (181:181:181)) + (PORT datad (178:178:178) (213:213:213)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD0) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (186:186:186)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (PORT sload (417:417:417) (459:459:459)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (PORT sload (417:417:417) (459:459:459)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (188:188:188)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (PORT sload (417:417:417) (459:459:459)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (195:195:195)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (PORT sload (417:417:417) (459:459:459)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (PORT sload (417:417:417) (459:459:459)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (268:268:268)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (129:129:129) (176:176:176)) + (PORT datad (97:97:97) (118:118:118)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (PORT sload (417:417:417) (459:459:459)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (PORT sload (417:417:417) (459:459:459)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (PORT sload (417:417:417) (459:459:459)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE\~0) + (DELAY + (ABSOLUTE + (PORT dataa (144:144:144) (200:200:200)) + (PORT datab (109:109:109) (140:140:140)) + (PORT datad (97:97:97) (118:118:118)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (191:191:191)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END\~0) + (DELAY + (ABSOLUTE + (PORT dataa (313:313:313) (373:373:373)) + (PORT datad (284:284:284) (330:330:330)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr18) + (DELAY + (ABSOLUTE + (PORT datab (197:197:197) (238:238:238)) + (PORT datac (125:125:125) (170:170:170)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (196:196:196)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (188:188:188)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (277:277:277)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (134:134:134) (173:173:173)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (372:372:372) (452:452:452)) + (PORT datac (354:354:354) (407:407:407)) + (PORT datad (115:115:115) (138:138:138)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (PORT ena (409:409:409) (429:429:429)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (417:417:417) (501:501:501)) + (PORT datab (450:450:450) (545:545:545)) + (PORT datac (408:408:408) (490:490:490)) + (PORT datad (414:414:414) (498:498:498)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~2) + (DELAY + (ABSOLUTE + (PORT datac (348:348:348) (400:400:400)) + (PORT datad (110:110:110) (132:132:132)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (345:345:345)) + (PORT datab (152:152:152) (203:203:203)) + (PORT datad (202:202:202) (243:243:243)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD0_ACK) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (460:460:460) (543:543:543)) + (PORT datab (145:145:145) (199:199:199)) + (PORT datac (134:134:134) (184:184:184)) + (PORT datad (176:176:176) (211:211:211)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (292:292:292) (347:347:347)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (203:203:203) (244:244:244)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD8) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (293:293:293) (348:348:348)) + (PORT datab (147:147:147) (198:198:198)) + (PORT datad (204:204:204) (245:245:245)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD8_ACK) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (152:152:152) (207:207:207)) + (PORT datab (226:226:226) (272:272:272)) + (PORT datad (307:307:307) (361:361:361)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD55_ACK) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (201:201:201)) + (PORT datab (222:222:222) (268:268:268)) + (PORT datad (301:301:301) (354:354:354)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.ACMD41_ACK) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (208:208:208)) + (PORT datab (145:145:145) (198:198:198)) + (PORT datac (130:130:130) (178:178:178)) + (PORT datad (131:131:131) (168:168:168)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datab (388:388:388) (454:454:454)) + (PORT datac (292:292:292) (336:336:336)) + (PORT datad (134:134:134) (173:173:173)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (191:191:191) (238:238:238)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (131:131:131) (179:179:179)) + (PORT datad (305:305:305) (359:359:359)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_ACMD41) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (152:152:152) (207:207:207)) + (PORT datab (149:149:149) (200:200:200)) + (PORT datac (204:204:204) (256:256:256)) + (PORT datad (139:139:139) (180:180:180)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~1) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (430:430:430)) + (PORT datab (128:128:128) (161:161:161)) + (PORT datac (188:188:188) (222:222:222)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (195:195:195)) + (PORT datab (197:197:197) (238:238:238)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|init_end) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (195:195:195)) + (PORT datac (305:305:305) (368:368:368)) + (PORT datad (139:139:139) (180:180:180)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (394:394:394)) + (PORT datab (309:309:309) (359:359:359)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (456:456:456) (528:528:528)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.SEND_CMD17) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (PORT sclr (682:682:682) (644:644:644)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (147:147:147) (197:197:197)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (PORT sclr (682:682:682) (644:644:644)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (194:194:194)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (145:145:145) (200:200:200)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (PORT sclr (682:682:682) (644:644:644)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (191:191:191)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (PORT sclr (682:682:682) (644:644:644)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (184:184:184)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (PORT sclr (682:682:682) (644:644:644)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (267:267:267)) + (PORT datab (142:142:142) (195:195:195)) + (PORT datac (131:131:131) (179:179:179)) + (PORT datad (122:122:122) (160:160:160)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (PORT sclr (682:682:682) (644:644:644)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (194:194:194)) + (PORT datac (133:133:133) (176:176:176)) + (PORT datad (125:125:125) (166:166:166)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (214:214:214)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (185:185:185) (216:216:216)) + (PORT datad (381:381:381) (464:464:464)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (246:246:246)) + (PORT datab (460:460:460) (525:525:525)) + (PORT datad (99:99:99) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.CMD17_ACK) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (149:149:149)) + (PORT datab (138:138:138) (189:189:189)) + (PORT datac (186:186:186) (228:228:228)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (309:309:309) (365:365:365)) + (PORT datab (336:336:336) (398:398:398)) + (PORT datad (456:456:456) (527:527:527)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_DATA) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (283:283:283)) + (PORT datab (147:147:147) (201:201:201)) + (PORT datac (141:141:141) (187:187:187)) + (PORT datad (130:130:130) (173:173:173)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sclr (670:670:670) (642:642:642)) + (PORT ena (488:488:488) (518:518:518)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sclr (670:670:670) (642:642:642)) + (PORT ena (488:488:488) (518:518:518)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (211:211:211) (267:267:267)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (149:149:149)) + (PORT datab (186:186:186) (223:223:223)) + (PORT datac (185:185:185) (218:218:218)) + (PORT datad (218:218:218) (267:267:267)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~2) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (204:204:204)) + (PORT datab (661:661:661) (788:788:788)) + (PORT datad (116:116:116) (138:138:138)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (152:152:152) (210:210:210)) + (PORT datac (130:130:130) (177:177:177)) + (PORT datad (126:126:126) (166:166:166)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~1) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (669:669:669)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (115:115:115) (138:138:138)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (207:207:207)) + (PORT datac (127:127:127) (173:173:173)) + (PORT datad (125:125:125) (165:165:165)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~11) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (197:197:197)) + (PORT datad (238:238:238) (295:295:295)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~10) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (321:321:321)) + (PORT datac (119:119:119) (163:163:163)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~9) + (DELAY + (ABSOLUTE + (PORT dataa (252:252:252) (320:320:320)) + (PORT datad (190:190:190) (238:238:238)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~8) + (DELAY + (ABSOLUTE + (PORT dataa (251:251:251) (319:319:319)) + (PORT datac (122:122:122) (165:165:165)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (194:194:194)) + (PORT datab (209:209:209) (267:267:267)) + (PORT datac (124:124:124) (168:168:168)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~14) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (281:281:281)) + (PORT datad (237:237:237) (293:293:293)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~13) + (DELAY + (ABSOLUTE + (PORT dataa (249:249:249) (317:317:317)) + (PORT datac (123:123:123) (167:167:167)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~12) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (318:318:318)) + (PORT datac (121:121:121) (164:164:164)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~15) + (DELAY + (ABSOLUTE + (PORT datab (178:178:178) (239:239:239)) + (PORT datac (121:121:121) (164:164:164)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datac (201:201:201) (246:246:246)) + (PORT datad (200:200:200) (252:252:252)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~4) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (243:243:243)) + (PORT datab (109:109:109) (140:140:140)) + (PORT datac (184:184:184) (224:224:224)) + (PORT datad (176:176:176) (209:209:209)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~4) + (DELAY + (ABSOLUTE + (PORT dataa (179:179:179) (216:216:216)) + (PORT datab (318:318:318) (370:370:370)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~1) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (190:190:190)) + (PORT datab (178:178:178) (241:241:241)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~0) + (DELAY + (ABSOLUTE + (PORT datab (177:177:177) (238:238:238)) + (PORT datac (123:123:123) (168:168:168)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~3) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (178:178:178) (240:240:240)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~2) + (DELAY + (ABSOLUTE + (PORT datab (176:176:176) (237:237:237)) + (PORT datac (123:123:123) (167:167:167)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (121:121:121) (165:165:165)) + (PORT datad (122:122:122) (162:162:162)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (242:242:242)) + (PORT datab (109:109:109) (139:139:139)) + (PORT datac (183:183:183) (222:222:222)) + (PORT datad (176:176:176) (209:209:209)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (665:665:665)) + (PORT datab (128:128:128) (160:160:160)) + (PORT datad (116:116:116) (138:138:138)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (670:670:670)) + (PORT datab (127:127:127) (159:159:159)) + (PORT datac (161:161:161) (193:193:193)) + (PORT datad (140:140:140) (184:184:184)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sclr (670:670:670) (642:642:642)) + (PORT ena (488:488:488) (518:518:518)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sclr (670:670:670) (642:642:642)) + (PORT ena (488:488:488) (518:518:518)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (144:144:144) (199:199:199)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sclr (670:670:670) (642:642:642)) + (PORT ena (488:488:488) (518:518:518)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sclr (670:670:670) (642:642:642)) + (PORT ena (488:488:488) (518:518:518)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (144:144:144) (197:197:197)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sclr (670:670:670) (642:642:642)) + (PORT ena (488:488:488) (518:518:518)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sclr (670:670:670) (642:642:642)) + (PORT ena (488:488:488) (518:518:518)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~3) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (154:154:154)) + (PORT datab (126:126:126) (158:158:158)) + (PORT datac (198:198:198) (245:245:245)) + (PORT datad (140:140:140) (184:184:184)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~4) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (227:227:227)) + (PORT datab (235:235:235) (291:291:291)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (228:228:228)) + (PORT datab (336:336:336) (397:397:397)) + (PORT datad (197:197:197) (246:246:246)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_END) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~1) + (DELAY + (ABSOLUTE + (PORT datad (201:201:201) (250:250:250)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~2) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (191:191:191)) + (PORT datad (200:200:200) (249:249:249)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (133:133:133) (185:185:185)) + (PORT datac (124:124:124) (169:169:169)) + (PORT datad (127:127:127) (169:169:169)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (121:121:121) (151:151:151)) + (PORT datad (203:203:203) (252:252:252)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (190:190:190)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (205:205:205) (257:257:257)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (137:137:137) (189:189:189)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (PORT sclr (384:384:384) (390:390:390)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (210:210:210) (269:269:269)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (PORT sclr (384:384:384) (390:390:390)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (139:139:139) (191:191:191)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (PORT sclr (384:384:384) (390:390:390)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (PORT sclr (384:384:384) (390:390:390)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (187:187:187)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (PORT sclr (384:384:384) (390:390:390)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (PORT sclr (384:384:384) (390:390:390)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (190:190:190)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (122:122:122) (165:165:165)) + (PORT datad (123:123:123) (163:163:163)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (208:208:208)) + (PORT datab (214:214:214) (273:273:273)) + (PORT datac (127:127:127) (173:173:173)) + (PORT datad (129:129:129) (171:171:171)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~2) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (121:121:121) (151:151:151)) + (PORT datad (104:104:104) (121:121:121)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (209:209:209)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datad (108:108:108) (127:127:127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (863:863:863)) + (PORT ena (623:623:623) (668:668:668)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (881:881:881)) + (PORT asdata (299:299:299) (340:340:340)) + (PORT clrn (860:860:860) (863:863:863)) + (PORT ena (623:623:623) (668:668:668)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (123:123:123) (162:162:162)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (863:863:863)) + (PORT ena (623:623:623) (668:668:668)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (881:881:881)) + (PORT asdata (373:373:373) (420:420:420)) + (PORT clrn (860:860:860) (863:863:863)) + (PORT ena (623:623:623) (668:668:668)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (PORT datab (134:134:134) (184:184:184)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (117:117:117) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (863:863:863)) + (PORT ena (623:623:623) (668:668:668)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (881:881:881)) + (PORT asdata (306:306:306) (346:346:346)) + (PORT clrn (860:860:860) (863:863:863)) + (PORT ena (623:623:623) (668:668:668)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (160:160:160)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (863:863:863)) + (PORT ena (623:623:623) (668:668:668)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (881:881:881)) + (PORT asdata (303:303:303) (346:346:346)) + (PORT clrn (860:860:860) (863:863:863)) + (PORT ena (623:623:623) (668:668:668)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (195:195:195)) + (PORT datab (137:137:137) (187:187:187)) + (PORT datad (203:203:203) (248:248:248)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~2) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (397:397:397)) + (PORT datad (314:314:314) (367:367:367)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (790:790:790) (907:907:907)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_DATA) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\~0) + (DELAY + (ABSOLUTE + (PORT datad (983:983:983) (1135:1135:1135)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (870:870:870)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~2) + (DELAY + (ABSOLUTE + (PORT datab (157:157:157) (212:212:212)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (870:870:870)) + (PORT sclr (1357:1357:1357) (1249:1249:1249)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~1) + (DELAY + (ABSOLUTE + (PORT datab (158:158:158) (212:212:212)) + (PORT datad (137:137:137) (181:181:181)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (870:870:870)) + (PORT sclr (1357:1357:1357) (1249:1249:1249)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (282:282:282)) + (PORT datab (160:160:160) (221:221:221)) + (PORT datac (141:141:141) (188:188:188)) + (PORT datad (135:135:135) (179:179:179)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~16) + (DELAY + (ABSOLUTE + (PORT datac (809:809:809) (942:942:942)) + (PORT datad (430:430:430) (491:491:491)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (874:874:874)) + (PORT sclr (1252:1252:1252) (1160:1160:1160)) + (PORT ena (488:488:488) (520:520:520)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (874:874:874)) + (PORT sclr (1252:1252:1252) (1160:1160:1160)) + (PORT ena (488:488:488) (520:520:520)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (874:874:874)) + (PORT sclr (1252:1252:1252) (1160:1160:1160)) + (PORT ena (488:488:488) (520:520:520)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (874:874:874)) + (PORT sclr (1252:1252:1252) (1160:1160:1160)) + (PORT ena (488:488:488) (520:520:520)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (874:874:874)) + (PORT sclr (1252:1252:1252) (1160:1160:1160)) + (PORT ena (488:488:488) (520:520:520)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (874:874:874)) + (PORT sclr (1252:1252:1252) (1160:1160:1160)) + (PORT ena (488:488:488) (520:520:520)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (874:874:874)) + (PORT sclr (1252:1252:1252) (1160:1160:1160)) + (PORT ena (488:488:488) (520:520:520)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (874:874:874)) + (PORT sclr (1252:1252:1252) (1160:1160:1160)) + (PORT ena (488:488:488) (520:520:520)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (874:874:874)) + (PORT sclr (1252:1252:1252) (1160:1160:1160)) + (PORT ena (488:488:488) (520:520:520)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (442:442:442) (515:515:515)) + (PORT datab (229:229:229) (285:285:285)) + (PORT datac (216:216:216) (268:268:268)) + (PORT datad (204:204:204) (249:249:249)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~3) + (DELAY + (ABSOLUTE + (PORT dataa (195:195:195) (233:233:233)) + (PORT datab (240:240:240) (298:298:298)) + (PORT datac (202:202:202) (251:251:251)) + (PORT datad (104:104:104) (122:122:122)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (468:468:468) (557:557:557)) + (PORT datab (681:681:681) (783:783:783)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_BUSY) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (2019:2019:2019) (2296:2296:2296)) + (PORT datad (158:158:158) (206:206:206)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~7) + (DELAY + (ABSOLUTE + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (158:158:158) (208:208:208)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~6) + (DELAY + (ABSOLUTE + (PORT datac (124:124:124) (169:169:169)) + (PORT datad (158:158:158) (207:207:207)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~5) + (DELAY + (ABSOLUTE + (PORT datac (124:124:124) (168:168:168)) + (PORT datad (157:157:157) (207:207:207)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (187:187:187)) + (PORT datab (138:138:138) (189:189:189)) + (PORT datac (119:119:119) (162:162:162)) + (PORT datad (124:124:124) (164:164:164)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~4) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (190:190:190)) + (PORT datad (158:158:158) (206:206:206)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~3) + (DELAY + (ABSOLUTE + (PORT datab (143:143:143) (192:192:192)) + (PORT datad (157:157:157) (207:207:207)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~2) + (DELAY + (ABSOLUTE + (PORT datac (122:122:122) (165:165:165)) + (PORT datad (159:159:159) (208:208:208)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~1) + (DELAY + (ABSOLUTE + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (157:157:157) (207:207:207)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (270:270:270)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (586:586:586)) + (PORT datab (456:456:456) (518:518:518)) + (PORT datad (101:101:101) (124:124:124)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_END) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~2) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (197:197:197)) + (PORT datad (201:201:201) (253:253:253)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~1) + (DELAY + (ABSOLUTE + (PORT datad (202:202:202) (254:254:254)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~0) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (196:196:196)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datad (203:203:203) (256:256:256)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (127:127:127) (172:172:172)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (702:702:702) (818:818:818)) + (PORT datad (102:102:102) (124:124:124)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (700:700:700) (817:817:817)) + (PORT datab (114:114:114) (147:147:147)) + (PORT datad (198:198:198) (250:250:250)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|wr_busy_dly\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (311:311:311) (378:378:378)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|wr_busy_dly) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|wr_busy_fall\~0) + (DELAY + (ABSOLUTE + (PORT datab (131:131:131) (180:180:180)) + (PORT datad (310:310:310) (378:378:378)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|rd_en) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n\~2) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (390:390:390)) + (PORT datab (123:123:123) (153:153:153)) + (PORT datad (128:128:128) (170:170:170)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_cs_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (404:404:404)) + (PORT datab (149:149:149) (200:200:200)) + (PORT datac (295:295:295) (354:354:354)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (204:204:204)) + (PORT datab (145:145:145) (200:200:200)) + (PORT datac (133:133:133) (181:181:181)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (207:207:207)) + (PORT datab (144:144:144) (197:197:197)) + (PORT datac (128:128:128) (174:174:174)) + (PORT datad (129:129:129) (170:170:170)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (405:405:405)) + (PORT datab (221:221:221) (279:279:279)) + (PORT datac (219:219:219) (275:275:275)) + (PORT datad (176:176:176) (209:209:209)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (149:149:149)) + (PORT datab (219:219:219) (278:278:278)) + (PORT datac (217:217:217) (272:272:272)) + (PORT datad (180:180:180) (213:213:213)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (145:145:145)) + (PORT datab (189:189:189) (226:226:226)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (105:105:105) (123:123:123)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~3) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (236:236:236)) + (PORT datab (283:283:283) (328:328:328)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cs_n) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_cs_n\~1) + (DELAY + (ABSOLUTE + (PORT datab (451:451:451) (522:522:522)) + (PORT datac (117:117:117) (158:158:158)) + (PORT datad (310:310:310) (371:371:371)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~11) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (368:368:368) (433:433:433)) + (PORT datad (350:350:350) (399:399:399)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|mosi) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (272:272:272)) + (PORT datab (142:142:142) (195:195:195)) + (PORT datac (131:131:131) (179:179:179)) + (PORT datad (128:128:128) (170:170:170)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (PORT sclr (682:682:682) (644:644:644)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~1) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (214:214:214)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (131:131:131) (179:179:179)) + (PORT datad (128:128:128) (171:171:171)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~2) + (DELAY + (ABSOLUTE + (PORT dataa (152:152:152) (211:211:211)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (375:375:375) (458:458:458)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT datab (137:137:137) (187:187:187)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0) + (DELAY + (ABSOLUTE + (PORT datac (92:92:92) (114:114:114)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (214:214:214)) + (PORT datab (137:137:137) (187:187:187)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datab (153:153:153) (207:207:207)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (156:156:156) (216:216:216)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datad (105:105:105) (130:130:130)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (151:151:151) (208:208:208)) + (PORT datab (155:155:155) (209:209:209)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (103:103:103) (127:127:127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (190:190:190)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datad (123:123:123) (163:163:163)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (269:269:269)) + (PORT datab (134:134:134) (183:183:183)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (274:274:274)) + (PORT datab (137:137:137) (187:187:187)) + (PORT datac (120:120:120) (163:163:163)) + (PORT datad (121:121:121) (160:160:160)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (289:289:289)) + (PORT datab (324:324:324) (389:389:389)) + (PORT datac (202:202:202) (249:249:249)) + (PORT datad (200:200:200) (244:244:244)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (238:238:238)) + (PORT datab (237:237:237) (295:295:295)) + (PORT datac (178:178:178) (217:217:217)) + (PORT datad (269:269:269) (308:308:308)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (184:184:184)) + (PORT datad (93:93:93) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT datab (106:106:106) (136:136:136)) + (PORT datad (130:130:130) (167:167:167)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (192:192:192)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (192:192:192)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (197:197:197)) + (PORT datab (141:141:141) (192:192:192)) + (PORT datac (128:128:128) (173:173:173)) + (PORT datad (127:127:127) (167:167:167)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (294:294:294) (342:342:342)) + (PORT datab (233:233:233) (292:292:292)) + (PORT datac (183:183:183) (222:222:222)) + (PORT datad (163:163:163) (191:191:191)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT datab (120:120:120) (154:154:154)) + (PORT datac (141:141:141) (190:190:190)) + (PORT datad (197:197:197) (243:243:243)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_flag) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (875:875:875)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_flag) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT asdata (556:556:556) (640:640:640)) + (PORT clrn (862:862:862) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (496:496:496) (549:549:549)) + (PORT ena (605:605:605) (638:638:638)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (701:701:701)) + (PORT datab (558:558:558) (667:667:667)) + (PORT datac (352:352:352) (409:409:409)) + (PORT datad (617:617:617) (729:729:729)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (92:92:92) (110:110:110)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (164:164:164)) + (PORT datad (143:143:143) (185:185:185)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (589:589:589) (701:701:701)) + (PORT datab (557:557:557) (666:666:666)) + (PORT datac (353:353:353) (409:409:409)) + (PORT datad (616:616:616) (728:728:728)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (156:156:156) (211:211:211)) + (PORT datab (220:220:220) (276:276:276)) + (PORT datad (174:174:174) (198:198:198)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (204:204:204)) + (PORT datab (159:159:159) (214:214:214)) + (PORT datac (111:111:111) (136:136:136)) + (PORT datad (143:143:143) (186:186:186)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (157:157:157) (213:213:213)) + (PORT datad (99:99:99) (120:120:120)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (210:210:210)) + (PORT datac (145:145:145) (194:194:194)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (216:216:216)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (555:555:555) (651:651:651)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (666:666:666) (726:726:726)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datad (206:206:206) (258:258:258)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (201:201:201) (247:247:247)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (605:605:605) (638:638:638)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (508:508:508) (596:596:596)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (120:120:120) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (580:580:580)) + (PORT datab (383:383:383) (460:460:460)) + (PORT datad (128:128:128) (169:169:169)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (211:211:211) (260:260:260)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (605:605:605) (638:638:638)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (498:498:498) (590:590:590)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (201:201:201) (253:253:253)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (120:120:120) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (118:118:118) (155:155:155)) + (PORT datab (151:151:151) (203:203:203)) + (PORT datad (205:205:205) (248:248:248)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (203:203:203) (256:256:256)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (605:605:605) (638:638:638)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (525:525:525) (591:591:591)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (354:354:354)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT asdata (293:293:293) (332:332:332)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (321:321:321) (368:368:368)) + (PORT ena (672:672:672) (728:728:728)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (467:467:467)) + (PORT datab (147:147:147) (197:197:197)) + (PORT datad (400:400:400) (482:482:482)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (319:319:319) (365:365:365)) + (PORT ena (672:672:672) (728:728:728)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (382:382:382) (436:436:436)) + (PORT ena (605:605:605) (638:638:638)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (336:336:336) (404:404:404)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (190:190:190) (238:238:238)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT asdata (366:366:366) (412:412:412)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (222:222:222) (270:270:270)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (605:605:605) (638:638:638)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT asdata (659:659:659) (743:743:743)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (302:302:302)) + (PORT datab (406:406:406) (487:487:487)) + (PORT datad (121:121:121) (160:160:160)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (314:314:314) (369:369:369)) + (PORT datac (159:159:159) (191:191:191)) + (PORT datad (294:294:294) (342:342:342)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (598:598:598) (703:703:703)) + (PORT datac (525:525:525) (597:597:597)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (281:281:281)) + (PORT datab (157:157:157) (210:210:210)) + (PORT datad (350:350:350) (410:410:410)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (709:709:709)) + (PORT datab (156:156:156) (210:210:210)) + (PORT datac (141:141:141) (181:181:181)) + (PORT datad (544:544:544) (638:638:638)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (666:666:666) (726:726:726)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (212:212:212)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[8\]) + (DELAY + (ABSOLUTE + (PORT datab (572:572:572) (675:675:675)) + (PORT datad (533:533:533) (619:619:619)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (666:666:666) (726:726:726)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (201:201:201)) + (PORT datab (156:156:156) (211:211:211)) + (PORT datac (114:114:114) (141:141:141)) + (PORT datad (143:143:143) (186:186:186)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (93:93:93) (111:111:111)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (156:156:156) (214:214:214)) + (PORT datab (158:158:158) (214:214:214)) + (PORT datac (143:143:143) (191:191:191)) + (PORT datad (226:226:226) (279:279:279)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (672:672:672) (728:728:728)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (131:131:131) (178:178:178)) + (PORT datac (118:118:118) (160:160:160)) + (PORT datad (541:541:541) (631:631:631)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity6) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (666:666:666) (726:726:726)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (666:666:666) (726:726:726)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (157:157:157) (211:211:211)) + (IOPATH datab combout (160:160:160) (156:156:156)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (666:666:666) (726:726:726)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (457:457:457) (541:541:541)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT asdata (366:366:366) (416:416:416)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (552:552:552) (625:625:625)) + (PORT ena (675:675:675) (751:751:751)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (315:315:315) (358:358:358)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (199:199:199) (250:250:250)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (449:449:449)) + (PORT datab (354:354:354) (424:424:424)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (130:130:130) (179:179:179)) + (PORT datad (95:95:95) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (605:605:605) (638:638:638)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0) + (DELAY + (ABSOLUTE + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (330:330:330) (388:388:388)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (406:406:406)) + (PORT datab (336:336:336) (405:405:405)) + (PORT datac (281:281:281) (316:316:316)) + (PORT datad (191:191:191) (238:238:238)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (282:282:282)) + (PORT datab (152:152:152) (203:203:203)) + (PORT datac (210:210:210) (261:261:261)) + (PORT datad (103:103:103) (126:126:126)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (159:159:159) (214:214:214)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (281:281:281)) + (PORT datab (157:157:157) (211:211:211)) + (PORT datac (147:147:147) (190:190:190)) + (PORT datad (201:201:201) (252:252:252)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a1) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (614:614:614) (655:655:655)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (409:409:409)) + (PORT datab (153:153:153) (206:206:206)) + (PORT datac (324:324:324) (388:388:388)) + (PORT datad (137:137:137) (179:179:179)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a0) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (614:614:614) (655:655:655)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (133:133:133) (184:184:184)) + (PORT datab (132:132:132) (180:180:180)) + (PORT datac (119:119:119) (160:160:160)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity8) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (614:614:614) (655:655:655)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datad (334:334:334) (401:401:401)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (531:531:531) (579:579:579)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (PORT datab (146:146:146) (197:197:197)) + (PORT datac (195:195:195) (234:234:234)) + (PORT datad (334:334:334) (401:401:401)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT datad (265:265:265) (300:300:300)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (206:206:206)) + (PORT datad (103:103:103) (127:127:127)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (282:282:282)) + (PORT datab (152:152:152) (205:205:205)) + (PORT datac (209:209:209) (260:260:260)) + (PORT datad (104:104:104) (128:128:128)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\]\~6) + (DELAY + (ABSOLUTE + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (288:288:288)) + (PORT datab (157:157:157) (212:212:212)) + (PORT datad (100:100:100) (121:121:121)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT datab (159:159:159) (213:213:213)) + (PORT datac (144:144:144) (188:188:188)) + (PORT datad (98:98:98) (118:118:118)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (221:221:221) (283:283:283)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (393:393:393) (444:444:444)) + (PORT ena (605:605:605) (638:638:638)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT asdata (641:641:641) (717:717:717)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT asdata (297:297:297) (337:337:337)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT asdata (293:293:293) (332:332:332)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datac (129:129:129) (175:175:175)) + (PORT datad (132:132:132) (175:175:175)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (152:152:152) (208:208:208)) + (PORT datab (162:162:162) (217:217:217)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT asdata (595:595:595) (668:668:668)) + (PORT ena (605:605:605) (656:656:656)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (534:534:534) (620:620:620)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (666:666:666) (726:726:726)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (519:519:519) (618:618:618)) + (PORT datac (148:148:148) (193:193:193)) + (PORT datad (471:471:471) (548:548:548)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (190:190:190)) + (PORT datab (134:134:134) (183:183:183)) + (PORT datac (124:124:124) (170:170:170)) + (PORT datad (129:129:129) (170:170:170)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (582:582:582) (686:686:686)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (675:675:675) (751:751:751)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT dataa (517:517:517) (616:616:616)) + (PORT datab (484:484:484) (570:570:570)) + (PORT datac (147:147:147) (192:192:192)) + (PORT datad (385:385:385) (464:464:464)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT datac (134:134:134) (178:178:178)) + (PORT datad (321:321:321) (374:374:374)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (705:705:705)) + (PORT datac (136:136:136) (180:180:180)) + (PORT datad (319:319:319) (372:372:372)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (736:736:736) (838:838:838)) + (PORT ena (675:675:675) (751:751:751)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (705:705:705)) + (PORT datab (654:654:654) (771:771:771)) + (PORT datac (133:133:133) (176:176:176)) + (PORT datad (319:319:319) (372:372:372)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (205:205:205) (254:254:254)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (605:605:605) (638:638:638)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (511:511:511) (580:580:580)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (299:299:299) (358:358:358)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (116:116:116) (153:153:153)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (394:394:394) (447:447:447)) + (PORT ena (605:605:605) (638:638:638)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (640:640:640) (720:720:720)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (308:308:308) (370:370:370)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT asdata (296:296:296) (335:335:335)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (PORT datab (204:204:204) (264:264:264)) + (PORT datac (132:132:132) (176:176:176)) + (PORT datad (597:597:597) (686:686:686)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT datac (335:335:335) (395:395:395)) + (PORT datad (276:276:276) (310:310:310)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT asdata (715:715:715) (808:808:808)) + (PORT ena (675:675:675) (751:751:751)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (147:147:147)) + (PORT datac (139:139:139) (185:185:185)) + (PORT datad (213:213:213) (261:261:261)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (259:259:259)) + (PORT datab (148:148:148) (199:199:199)) + (PORT datad (335:335:335) (401:401:401)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (315:315:315) (368:368:368)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (605:605:605) (638:638:638)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (456:456:456) (531:531:531)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT asdata (480:480:480) (536:536:536)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (119:119:119) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT dataa (315:315:315) (379:379:379)) + (PORT datab (141:141:141) (193:193:193)) + (PORT datac (149:149:149) (193:193:193)) + (PORT datad (106:106:106) (125:125:125)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (315:315:315) (378:378:378)) + (PORT datab (460:460:460) (544:544:544)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (425:425:425)) + (PORT datab (217:217:217) (275:275:275)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (268:268:268)) + (PORT datab (358:358:358) (437:437:437)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (280:280:280)) + (PORT datab (343:343:343) (419:419:419)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (196:196:196) (252:252:252)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (133:133:133) (184:184:184)) + (PORT datad (197:197:197) (245:245:245)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|comb\~1) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (218:218:218)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|comb\~0) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (812:812:812) (944:944:944)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (92:92:92) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|comb\~2) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (88:88:88) (110:110:110)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (928:928:928)) + (PORT datab (148:148:148) (199:199:199)) + (PORT datac (680:680:680) (787:787:787)) + (PORT datad (301:301:301) (361:361:361)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (144:144:144)) + (PORT datab (338:338:338) (398:398:398)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (317:317:317) (370:370:370)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.SEND_CMD24) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (877:877:877)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (145:145:145) (199:199:199)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (866:866:866) (872:872:872)) + (PORT sclr (1174:1174:1174) (1088:1088:1088)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (144:144:144) (199:199:199)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (866:866:866) (872:872:872)) + (PORT sclr (1174:1174:1174) (1088:1088:1088)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (143:143:143) (195:195:195)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (866:866:866) (872:872:872)) + (PORT sclr (1174:1174:1174) (1088:1088:1088)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (205:205:205)) + (PORT datab (147:147:147) (201:201:201)) + (PORT datac (131:131:131) (178:178:178)) + (PORT datad (132:132:132) (175:175:175)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (144:144:144) (196:196:196)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (866:866:866) (872:872:872)) + (PORT sclr (1174:1174:1174) (1088:1088:1088)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (866:866:866) (872:872:872)) + (PORT sclr (1174:1174:1174) (1088:1088:1088)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~2) + (DELAY + (ABSOLUTE + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (133:133:133) (182:182:182)) + (PORT datad (132:132:132) (176:176:176)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datab (144:144:144) (198:198:198)) + (PORT datac (131:131:131) (178:178:178)) + (PORT datad (129:129:129) (171:171:171)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (145:145:145) (199:199:199)) + (PORT datac (133:133:133) (182:182:182)) + (PORT datad (97:97:97) (118:118:118)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (177:177:177) (217:217:217)) + (PORT datac (826:826:826) (953:953:953)) + (PORT datad (301:301:301) (347:347:347)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (410:410:410)) + (PORT datab (839:839:839) (972:972:972)) + (PORT datac (809:809:809) (942:942:942)) + (PORT datad (205:205:205) (251:251:251)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (841:841:841) (974:974:974)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (890:890:890)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (866:866:866) (873:873:873)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_mosi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (404:404:404)) + (PORT datab (363:363:363) (440:440:440)) + (PORT datac (703:703:703) (823:823:823)) + (PORT datad (137:137:137) (178:178:178)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_mosi\~1) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (394:394:394)) + (PORT datac (365:365:365) (430:430:430)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1120:1120:1120) (1119:1119:1119)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (439:439:439)) + (PORT datab (134:134:134) (183:183:183)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (189:189:189)) + (PORT datab (136:136:136) (187:187:187)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (121:121:121) (160:160:160)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (416:416:416)) + (PORT datab (310:310:310) (364:364:364)) + (PORT datac (347:347:347) (418:418:418)) + (PORT datad (352:352:352) (421:421:421)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (192:192:192)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (546:546:546) (634:634:634)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (202:202:202)) + (PORT datab (142:142:142) (194:194:194)) + (PORT datac (130:130:130) (176:176:176)) + (PORT datad (129:129:129) (171:171:171)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (441:441:441)) + (PORT datac (351:351:351) (424:424:424)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (422:422:422)) + (PORT datab (111:111:111) (142:142:142)) + (PORT datac (307:307:307) (359:359:359)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (546:546:546) (634:634:634)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (138:138:138) (191:191:191)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (546:546:546) (634:634:634)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (546:546:546) (634:634:634)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (139:139:139) (192:192:192)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (546:546:546) (634:634:634)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (546:546:546) (634:634:634)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (546:546:546) (634:634:634)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (546:546:546) (634:634:634)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (546:546:546) (634:634:634)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (546:546:546) (634:634:634)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (202:202:202)) + (PORT datab (142:142:142) (194:194:194)) + (PORT datac (129:129:129) (176:176:176)) + (PORT datad (129:129:129) (171:171:171)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (440:440:440)) + (PORT datab (369:369:369) (445:445:445)) + (PORT datac (418:418:418) (471:471:471)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (464:464:464) (550:550:550)) + (PORT datad (461:461:461) (538:538:538)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (142:142:142)) + (PORT datab (483:483:483) (564:564:564)) + (PORT datac (148:148:148) (205:205:205)) + (PORT datad (127:127:127) (169:169:169)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (464:464:464) (551:551:551)) + (PORT datab (485:485:485) (568:568:568)) + (PORT datad (118:118:118) (142:142:142)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (890:890:890)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (869:869:869) (873:873:873)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (168:168:168)) + (PORT datab (161:161:161) (223:223:223)) + (PORT datad (103:103:103) (125:125:125)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (890:890:890)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (869:869:869) (873:873:873)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (269:269:269)) + (PORT datab (142:142:142) (194:194:194)) + (PORT datac (150:150:150) (208:208:208)) + (PORT datad (146:146:146) (195:195:195)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (168:168:168)) + (PORT datab (115:115:115) (148:148:148)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (890:890:890)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (869:869:869) (873:873:873)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (188:188:188)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (234:234:234) (292:292:292)) + (PORT datac (317:317:317) (381:381:381)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|rd_busy_dly) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT asdata (649:649:649) (731:731:731)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (132:132:132) (182:182:182)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (866:866:866)) + (PORT sclr (653:653:653) (627:627:627)) + (PORT ena (639:639:639) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (183:183:183)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (866:866:866)) + (PORT sclr (653:653:653) (627:627:627)) + (PORT ena (639:639:639) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (866:866:866)) + (PORT sclr (653:653:653) (627:627:627)) + (PORT ena (639:639:639) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (191:191:191)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datac (123:123:123) (166:166:166)) + (PORT datad (125:125:125) (164:164:164)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (866:866:866)) + (PORT sclr (653:653:653) (627:627:627)) + (PORT ena (639:639:639) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (866:866:866)) + (PORT sclr (653:653:653) (627:627:627)) + (PORT ena (639:639:639) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (866:866:866)) + (PORT sclr (653:653:653) (627:627:627)) + (PORT ena (639:639:639) (693:693:693)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (191:191:191)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (123:123:123) (166:166:166)) + (PORT datad (124:124:124) (163:163:163)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~3) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (214:214:214)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (318:318:318) (371:371:371)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (518:518:518) (620:620:620)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datad (400:400:400) (450:450:450)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_en) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (289:289:289)) + (PORT datab (217:217:217) (271:271:271)) + (PORT datac (202:202:202) (251:251:251)) + (PORT datad (211:211:211) (258:258:258)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (129:129:129) (169:169:169)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (285:285:285)) + (PORT datab (214:214:214) (268:268:268)) + (PORT datac (199:199:199) (247:247:247)) + (PORT datad (207:207:207) (255:255:255)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (269:269:269)) + (PORT datab (209:209:209) (263:263:263)) + (PORT datac (199:199:199) (243:243:243)) + (PORT datad (207:207:207) (253:253:253)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (PORT sclr (395:395:395) (458:458:458)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (314:314:314) (376:376:376)) + (PORT datab (227:227:227) (280:280:280)) + (PORT datac (298:298:298) (350:350:350)) + (PORT datad (198:198:198) (241:241:241)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (696:696:696)) + (PORT datab (209:209:209) (263:263:263)) + (PORT datac (91:91:91) (114:114:114)) + (PORT datad (90:90:90) (109:109:109)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (234:234:234) (291:291:291)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (317:317:317) (381:381:381)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|rd_fifo_rd_en) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (152:152:152) (205:205:205)) + (PORT datac (147:147:147) (196:196:196)) + (PORT datad (98:98:98) (120:120:120)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (151:151:151) (204:204:204)) + (PORT datad (94:94:94) (112:112:112)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (334:334:334) (395:395:395)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (896:896:896)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (521:521:521) (555:555:555)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (414:414:414)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (363:363:363) (437:437:437)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (452:452:452) (481:481:481)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT asdata (507:507:507) (569:569:569)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT asdata (294:294:294) (332:332:332)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT asdata (544:544:544) (617:617:617)) + (PORT ena (534:534:534) (577:577:577)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (327:327:327) (394:394:394)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (484:484:484) (576:576:576)) + (PORT datab (144:144:144) (193:193:193)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (283:283:283)) + (PORT datab (147:147:147) (201:201:201)) + (PORT datac (141:141:141) (188:188:188)) + (PORT datad (131:131:131) (174:174:174)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (153:153:153)) + (PORT datab (169:169:169) (206:206:206)) + (PORT datac (188:188:188) (221:221:221)) + (PORT datad (217:217:217) (266:266:266)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (667:667:667)) + (PORT datab (149:149:149) (204:204:204)) + (PORT datac (179:179:179) (207:207:207)) + (PORT datad (109:109:109) (129:129:129)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT asdata (551:551:551) (628:628:628)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT asdata (295:295:295) (335:335:335)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (341:341:341) (406:406:406)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (649:649:649) (691:691:691)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (897:897:897)) + (PORT asdata (308:308:308) (348:348:348)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (203:203:203) (257:257:257)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (283:283:283)) + (PORT datab (230:230:230) (287:287:287)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (364:364:364) (442:442:442)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (496:496:496) (519:519:519)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (896:896:896)) + (PORT asdata (730:730:730) (805:805:805)) + (PORT ena (521:521:521) (555:555:555)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (896:896:896)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT asdata (534:534:534) (612:612:612)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (204:204:204)) + (PORT datab (152:152:152) (204:204:204)) + (PORT datac (181:181:181) (220:220:220)) + (PORT datad (137:137:137) (179:179:179)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (582:582:582)) + (PORT datab (372:372:372) (444:444:444)) + (PORT datad (111:111:111) (131:131:131)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (223:223:223) (271:271:271)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (888:888:888) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (449:449:449) (480:480:480)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (319:319:319) (376:376:376)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (357:357:357) (433:433:433)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (435:435:435)) + (PORT datab (205:205:205) (265:265:265)) + (PORT datad (118:118:118) (156:156:156)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (310:310:310) (370:370:370)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (615:615:615) (648:648:648)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT asdata (306:306:306) (346:346:346)) + (PORT ena (534:534:534) (577:577:577)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (131:131:131) (168:168:168)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT asdata (294:294:294) (333:333:333)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (137:137:137) (176:176:176)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (534:534:534) (577:577:577)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (128:128:128) (165:165:165)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (120:120:120) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (269:269:269)) + (PORT datab (350:350:350) (424:424:424)) + (PORT datad (118:118:118) (156:156:156)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (310:310:310) (360:360:360)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT datab (110:110:110) (142:142:142)) + (PORT datac (752:752:752) (862:862:862)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a0) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (615:615:615) (648:648:648)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (413:413:413)) + (PORT datab (153:153:153) (205:205:205)) + (PORT datad (298:298:298) (335:335:335)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (447:447:447)) + (PORT datab (213:213:213) (276:276:276)) + (PORT datac (122:122:122) (145:145:145)) + (PORT datad (357:357:357) (430:430:430)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (447:447:447)) + (PORT datab (330:330:330) (401:401:401)) + (PORT datad (299:299:299) (339:339:339)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (331:331:331) (402:402:402)) + (PORT datad (299:299:299) (339:339:339)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|cntr_cout\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (313:313:313) (379:379:379)) + (PORT datab (373:373:373) (456:456:456)) + (PORT datac (327:327:327) (393:393:393)) + (PORT datad (167:167:167) (192:192:192)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6\~0) + (DELAY + (ABSOLUTE + (PORT datab (382:382:382) (464:464:464)) + (PORT datad (96:96:96) (117:117:117)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (440:440:440)) + (PORT datab (147:147:147) (202:202:202)) + (PORT datac (135:135:135) (183:183:183)) + (PORT datad (366:366:366) (445:445:445)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (496:496:496) (519:519:519)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT datab (386:386:386) (469:469:469)) + (PORT datac (135:135:135) (183:183:183)) + (PORT datad (101:101:101) (122:122:122)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9\~0) + (DELAY + (ABSOLUTE + (PORT datab (145:145:145) (198:198:198)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (PORT datac (190:190:190) (244:244:244)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (496:496:496) (519:519:519)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (446:446:446)) + (PORT datab (153:153:153) (205:205:205)) + (PORT datac (131:131:131) (173:173:173)) + (PORT datad (317:317:317) (377:377:377)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (615:615:615) (648:648:648)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (131:131:131) (179:179:179)) + (PORT datac (118:118:118) (160:160:160)) + (PORT datad (336:336:336) (406:406:406)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity9) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (496:496:496) (519:519:519)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (768:768:768) (887:887:887)) + (PORT datab (111:111:111) (143:143:143)) + (PORT datac (196:196:196) (252:252:252)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (446:446:446)) + (PORT datab (378:378:378) (458:458:458)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (201:201:201)) + (PORT datab (326:326:326) (397:397:397)) + (PORT datac (293:293:293) (328:328:328)) + (PORT datad (342:342:342) (419:419:419)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (90:90:90) (108:108:108)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (203:203:203)) + (PORT datab (383:383:383) (465:465:465)) + (PORT datad (97:97:97) (118:118:118)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8\~0) + (DELAY + (ABSOLUTE + (PORT datab (145:145:145) (198:198:198)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT asdata (369:369:369) (420:420:420)) + (PORT ena (496:496:496) (519:519:519)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT asdata (306:306:306) (345:345:345)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (888:888:888) (895:895:895)) + (PORT asdata (467:467:467) (518:518:518)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (888:888:888) (895:895:895)) + (PORT asdata (293:293:293) (332:332:332)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (124:124:124) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (496:496:496) (519:519:519)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (359:359:359)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (120:120:120) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (120:120:120) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (315:315:315) (381:381:381)) + (PORT datab (223:223:223) (276:276:276)) + (PORT datad (295:295:295) (350:350:350)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (896:896:896)) + (PORT asdata (505:505:505) (563:563:563)) + (PORT ena (521:521:521) (555:555:555)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (131:131:131) (174:174:174)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (496:496:496) (519:519:519)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (312:312:312) (373:373:373)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (896:896:896)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (117:117:117) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (896:896:896)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (896:896:896)) + (PORT asdata (295:295:295) (334:334:334)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT asdata (311:311:311) (359:359:359)) + (PORT ena (496:496:496) (519:519:519)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (311:311:311) (371:371:371)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (896:896:896)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (896:896:896)) + (PORT asdata (294:294:294) (332:332:332)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (896:896:896)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (213:213:213) (265:265:265)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (207:207:207) (254:254:254)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (380:380:380) (456:456:456)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (889:889:889)) + (PORT asdata (296:296:296) (335:335:335)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (341:341:341) (418:418:418)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (615:615:615) (648:648:648)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (889:889:889)) + (PORT asdata (611:611:611) (682:682:682)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (117:117:117) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (117:117:117) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (412:412:412)) + (PORT datab (452:452:452) (525:525:525)) + (PORT datad (119:119:119) (157:157:157)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (160:160:160) (189:189:189)) + (PORT datad (286:286:286) (333:333:333)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (412:412:412) (475:475:475)) + (PORT datab (728:728:728) (828:828:828)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (699:699:699)) + (PORT datab (383:383:383) (461:461:461)) + (PORT datac (462:462:462) (539:539:539)) + (PORT datad (314:314:314) (369:369:369)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT datad (93:93:93) (111:111:111)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (395:395:395)) + (PORT datad (131:131:131) (170:170:170)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (581:581:581)) + (PORT datab (372:372:372) (444:444:444)) + (PORT datac (148:148:148) (193:193:193)) + (PORT datad (111:111:111) (131:131:131)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (160:160:160) (219:219:219)) + (PORT datad (100:100:100) (122:122:122)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (164:164:164) (223:223:223)) + (PORT datab (153:153:153) (206:206:206)) + (PORT datad (96:96:96) (117:117:117)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (155:155:155) (208:208:208)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[9\]) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (196:196:196)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a2) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (499:499:499) (538:538:538)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (162:162:162) (221:221:221)) + (PORT datab (153:153:153) (207:207:207)) + (PORT datac (151:151:151) (196:196:196)) + (PORT datad (138:138:138) (180:180:180)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a1) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (499:499:499) (538:538:538)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (201:201:201)) + (PORT datab (369:369:369) (441:441:441)) + (PORT datac (140:140:140) (187:187:187)) + (PORT datad (469:469:469) (556:556:556)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a0) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (499:499:499) (538:538:538)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT datab (131:131:131) (179:179:179)) + (PORT datac (117:117:117) (158:158:158)) + (PORT datad (187:187:187) (233:233:233)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity5) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (499:499:499) (538:538:538)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datad (138:138:138) (179:179:179)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (499:499:499) (538:538:538)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (248:248:248)) + (PORT datab (155:155:155) (208:208:208)) + (PORT datad (137:137:137) (177:177:177)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT asdata (745:745:745) (847:847:847)) + (PORT ena (534:534:534) (577:577:577)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (152:152:152) (204:204:204)) + (IOPATH datab combout (160:160:160) (156:156:156)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (615:615:615) (648:648:648)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT asdata (295:295:295) (334:334:334)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (888:888:888) (895:895:895)) + (PORT asdata (483:483:483) (543:543:543)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (888:888:888) (895:895:895)) + (PORT asdata (485:485:485) (535:535:535)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (888:888:888) (895:895:895)) + (PORT asdata (363:363:363) (413:413:413)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (888:888:888) (895:895:895)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (400:400:400)) + (PORT datab (342:342:342) (413:413:413)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT datab (726:726:726) (825:825:825)) + (PORT datac (97:97:97) (121:121:121)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1984:1984:1984) (2245:2245:2245)) + (PORT datab (479:479:479) (552:552:552)) + (PORT datac (498:498:498) (599:599:599)) + (PORT datad (354:354:354) (409:409:409)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~13) + (DELAY + (ABSOLUTE + (PORT datac (538:538:538) (651:651:651)) + (PORT datad (370:370:370) (441:441:441)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (664:664:664)) + (PORT datab (146:146:146) (201:201:201)) + (PORT datac (179:179:179) (207:207:207)) + (PORT datad (110:110:110) (129:129:129)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (636:636:636) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (516:516:516) (624:624:624)) + (PORT datab (369:369:369) (433:433:433)) + (PORT datac (458:458:458) (531:531:531)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (622:622:622)) + (PORT datab (368:368:368) (431:431:431)) + (PORT datac (462:462:462) (534:534:534)) + (PORT datad (130:130:130) (168:168:168)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (620:620:620)) + (PORT datab (367:367:367) (430:430:430)) + (PORT datac (465:465:465) (538:538:538)) + (PORT datad (130:130:130) (167:167:167)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (513:513:513) (621:621:621)) + (PORT datab (367:367:367) (431:431:431)) + (PORT datac (464:464:464) (537:537:537)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (512:512:512) (619:619:619)) + (PORT datab (366:366:366) (430:430:430)) + (PORT datac (466:466:466) (539:539:539)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (579:579:579)) + (PORT datab (513:513:513) (593:593:593)) + (PORT datac (653:653:653) (775:775:775)) + (PORT datad (361:361:361) (434:434:434)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~0) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (580:580:580)) + (PORT datab (512:512:512) (592:592:592)) + (PORT datac (652:652:652) (774:774:774)) + (PORT datad (121:121:121) (159:159:159)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (674:674:674) (805:805:805)) + (PORT datab (513:513:513) (593:593:593)) + (PORT datac (122:122:122) (165:165:165)) + (PORT datad (473:473:473) (547:547:547)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~14) + (DELAY + (ABSOLUTE + (PORT datac (664:664:664) (787:787:787)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (754:754:754) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (135:135:135) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (615:615:615) (648:648:648)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[8\]) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0) + (DELAY + (ABSOLUTE + (PORT datad (91:91:91) (109:109:109)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0) + (DELAY + (ABSOLUTE + (PORT clk (889:889:889) (897:897:897)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (649:649:649) (691:691:691)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (162:162:162)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~15) + (DELAY + (ABSOLUTE + (PORT datab (386:386:386) (464:464:464)) + (PORT datac (544:544:544) (658:658:658)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (636:636:636) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~11) + (DELAY + (ABSOLUTE + (PORT datac (538:538:538) (652:652:652)) + (PORT datad (356:356:356) (421:421:421)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (636:636:636) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~7) + (DELAY + (ABSOLUTE + (PORT datac (552:552:552) (668:668:668)) + (PORT datad (369:369:369) (439:439:439)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (636:636:636) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~5) + (DELAY + (ABSOLUTE + (PORT datac (550:550:550) (666:666:666)) + (PORT datad (372:372:372) (445:445:445)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (636:636:636) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~3) + (DELAY + (ABSOLUTE + (PORT datac (654:654:654) (776:776:776)) + (PORT datad (361:361:361) (434:434:434)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (754:754:754) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~9) + (DELAY + (ABSOLUTE + (PORT datac (661:661:661) (784:784:784)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (754:754:754) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (PORT datac (651:651:651) (773:773:773)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (754:754:754) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (576:576:576)) + (PORT datab (514:514:514) (595:595:595)) + (PORT datac (660:660:660) (782:782:782)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~16) + (DELAY + (ABSOLUTE + (PORT datac (649:649:649) (770:770:770)) + (PORT datad (124:124:124) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (754:754:754) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (193:193:193)) + (PORT datac (661:661:661) (783:783:783)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (754:754:754) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (194:194:194)) + (PORT datac (662:662:662) (786:786:786)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (754:754:754) (819:819:819)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~6) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (412:412:412)) + (PORT datac (550:550:550) (665:665:665)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (636:636:636) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (415:415:415)) + (PORT datab (463:463:463) (533:533:533)) + (PORT datac (542:542:542) (656:656:656)) + (PORT datad (342:342:342) (392:392:392)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~4) + (DELAY + (ABSOLUTE + (PORT datac (548:548:548) (663:663:663)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (636:636:636) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~10) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (193:193:193)) + (PORT datac (551:551:551) (667:667:667)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (636:636:636) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~1) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (189:189:189)) + (PORT datab (463:463:463) (533:533:533)) + (PORT datac (543:543:543) (657:657:657)) + (PORT datad (342:342:342) (393:393:393)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~2) + (DELAY + (ABSOLUTE + (PORT datac (540:540:540) (654:654:654)) + (PORT datad (118:118:118) (154:154:154)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT ena (636:636:636) (688:688:688)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datab (142:142:142) (195:195:195)) + (PORT datac (151:151:151) (209:209:209)) + (PORT datad (344:344:344) (393:393:393)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (484:484:484) (567:567:567)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|tx) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (890:890:890)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (869:869:869) (873:873:873)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_modelsim.xrf b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_modelsim.xrf new file mode 100644 index 0000000..8521a91 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_modelsim.xrf @@ -0,0 +1,1312 @@ +vendor_name = ModelSim +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/data_rw_ctrl.v +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/uart_tx.v +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/uart_sd.v +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/uart_rx.v +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/sd_write.v +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/sd_read.v +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/sd_init.v +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/rtl/sd_ctrl.v +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.qip +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/ip_core/clk_gen/clk_gen.v +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.qip +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_wr_data/fifo_wr_data.v +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.qip +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/ip_core/fifo_rd_data/fifo_rd_data.v +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/uart_sd.cbx.xml +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_pll.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/stratixii_pll.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/cycloneii_pll.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/cbx.lst +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/clk_gen_altpll.v +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo_mixed_widths.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/dcfifo_uqf1.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/a_gray2bin_6ib.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/a_graycounter_3p6.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/a_graycounter_u6c.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/altsyncram_3011.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/dffpipe_909.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/alt_synch_pipe_b7d.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/dffpipe_a09.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/alt_synch_pipe_c7d.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/dffpipe_b09.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/cmpr_n76.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/cntr_old.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/dcfifo_h0f1.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/a_graycounter_2p6.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/a_graycounter_v6c.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/altsyncram_4011.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/alt_synch_pipe_d7d.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/dffpipe_c09.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/alt_synch_pipe_e7d.tdf +source_file = 1, E:/simiao/lc/A415/06_uart_sd/uart_sd/quartus_prj/db/dffpipe_d09.tdf +design_name = uart_sd +instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll1 , clk_gen_inst|altpll_component|auto_generated|pll1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~6, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~14, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[1] , sd_ctrl_inst|sd_write_inst|cnt_data_num[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[3] , sd_ctrl_inst|sd_write_inst|cnt_data_num[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[4] , sd_ctrl_inst|sd_write_inst|cnt_data_num[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_bit[3] , sd_ctrl_inst|sd_write_inst|cnt_data_bit[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|fifo_ram|ram_block11a0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[3] , sd_ctrl_inst|sd_read_inst|cnt_data_num[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[9] , sd_ctrl_inst|sd_read_inst|cnt_data_num[9], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[10] , sd_ctrl_inst|sd_read_inst|cnt_data_num[10], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[11] , sd_ctrl_inst|sd_read_inst|cnt_data_num[11], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[0] , sd_ctrl_inst|sd_init_inst|cnt_wait[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[2]~13, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[5]~19, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[4]~16, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14 , sd_ctrl_inst|sd_write_inst|cnt_data_num[1]~14, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19 , sd_ctrl_inst|sd_write_inst|cnt_data_num[3]~19, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21 , sd_ctrl_inst|sd_write_inst|cnt_data_num[4]~21, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[0]~8, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5]~18, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[5] , uart_tx_inst|baud_cnt[5], uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[2] , uart_tx_inst|baud_cnt[2], uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[10] , uart_tx_inst|baud_cnt[10], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18 , sd_ctrl_inst|sd_read_inst|cnt_data_num[3]~18, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28 , sd_ctrl_inst|sd_read_inst|cnt_data_num[8]~28, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32 , sd_ctrl_inst|sd_read_inst|cnt_data_num[9]~32, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34 , sd_ctrl_inst|sd_read_inst|cnt_data_num[10]~34, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36 , sd_ctrl_inst|sd_read_inst|cnt_data_num[11]~36, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9 , sd_ctrl_inst|sd_init_inst|cnt_wait[0]~9, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[6]~20, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[7]~22, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[3]~14, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[5]~18, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[2]~17 , uart_tx_inst|baud_cnt[2]~17, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[5]~23 , uart_tx_inst|baud_cnt[5]~23, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[10]~33 , uart_tx_inst|baud_cnt[10]~33, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[5] , data_rw_ctrl_inst|cnt_wait[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[5]~27 , data_rw_ctrl_inst|cnt_wait[5]~27, uart_sd, 1 +instance = comp, \uart_rx_inst|Add1~4 , uart_rx_inst|Add1~4, uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[4] , uart_rx_inst|baud_cnt[4], uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[10] , uart_rx_inst|baud_cnt[10], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[3] , data_rw_ctrl_inst|send_data_num[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[6] , data_rw_ctrl_inst|send_data_num[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[8] , data_rw_ctrl_inst|send_data_num[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[9] , data_rw_ctrl_inst|send_data_num[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[10] , data_rw_ctrl_inst|send_data_num[10], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[11] , data_rw_ctrl_inst|send_data_num[11], uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[4]~21 , uart_rx_inst|baud_cnt[4]~21, uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[10]~33 , uart_rx_inst|baud_cnt[10]~33, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[3]~18 , data_rw_ctrl_inst|send_data_num[3]~18, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[6]~24 , data_rw_ctrl_inst|send_data_num[6]~24, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[7]~26 , data_rw_ctrl_inst|send_data_num[7]~26, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[8]~28 , data_rw_ctrl_inst|send_data_num[8]~28, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[9]~30 , data_rw_ctrl_inst|send_data_num[9]~30, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[10]~32 , data_rw_ctrl_inst|send_data_num[10]~32, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[11]~34 , data_rw_ctrl_inst|send_data_num[11]~34, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_end[2] , sd_ctrl_inst|sd_read_inst|cnt_end[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Selector1~0 , sd_ctrl_inst|sd_read_inst|Selector1~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|state.SEND_CMD55 , sd_ctrl_inst|sd_init_inst|state.SEND_CMD55, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal6~0 , sd_ctrl_inst|sd_init_inst|Equal6~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|always4~0 , sd_ctrl_inst|sd_write_inst|always4~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|always4~1 , sd_ctrl_inst|sd_write_inst|always4~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~0 , sd_ctrl_inst|sd_write_inst|mosi~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~1 , sd_ctrl_inst|sd_write_inst|mosi~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Mux0~1 , sd_ctrl_inst|sd_write_inst|Mux0~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~0 , sd_ctrl_inst|sd_write_inst|Mux1~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~1 , sd_ctrl_inst|sd_write_inst|Mux1~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~2 , sd_ctrl_inst|sd_write_inst|Mux1~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~3 , sd_ctrl_inst|sd_write_inst|Mux1~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~4 , sd_ctrl_inst|sd_write_inst|Mux1~4, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~5 , sd_ctrl_inst|sd_write_inst|Mux1~5, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~6 , sd_ctrl_inst|sd_write_inst|Mux1~6, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~7 , sd_ctrl_inst|sd_write_inst|Mux1~7, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Mux1~8 , sd_ctrl_inst|sd_write_inst|Mux1~8, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~6 , sd_ctrl_inst|sd_write_inst|mosi~6, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~7 , sd_ctrl_inst|sd_write_inst|mosi~7, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~1 , sd_ctrl_inst|sd_init_inst|Selector14~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~2 , sd_ctrl_inst|sd_init_inst|Selector14~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|WideOr14~0 , sd_ctrl_inst|sd_init_inst|WideOr14~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~3 , sd_ctrl_inst|sd_init_inst|Selector14~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~4 , sd_ctrl_inst|sd_init_inst|Selector14~4, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~5 , sd_ctrl_inst|sd_init_inst|Selector14~5, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~6 , sd_ctrl_inst|sd_init_inst|Selector14~6, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~7 , sd_ctrl_inst|sd_init_inst|Selector14~7, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|WideOr12~0 , sd_ctrl_inst|sd_init_inst|WideOr12~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~8 , sd_ctrl_inst|sd_init_inst|Selector14~8, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~9 , sd_ctrl_inst|sd_init_inst|Selector14~9, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~10 , sd_ctrl_inst|sd_init_inst|Selector14~10, uart_sd, 1 +instance = comp, \uart_tx_inst|bit_cnt[2] , uart_tx_inst|bit_cnt[2], uart_sd, 1 +instance = comp, \uart_tx_inst|always0~0 , uart_tx_inst|always0~0, uart_sd, 1 +instance = comp, \uart_tx_inst|Mux0~1 , uart_tx_inst|Mux0~1, uart_sd, 1 +instance = comp, \uart_tx_inst|Mux0~2 , uart_tx_inst|Mux0~2, uart_sd, 1 +instance = comp, \uart_tx_inst|Mux0~3 , uart_tx_inst|Mux0~3, uart_sd, 1 +instance = comp, \uart_tx_inst|Mux0~4 , uart_tx_inst|Mux0~4, uart_sd, 1 +instance = comp, \uart_tx_inst|Mux0~5 , uart_tx_inst|Mux0~5, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_end~0 , sd_ctrl_inst|sd_read_inst|cnt_end~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|always3~1 , sd_ctrl_inst|sd_read_inst|always3~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit[0] , sd_ctrl_inst|sd_read_inst|cnt_data_bit[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|always3~2 , sd_ctrl_inst|sd_read_inst|always3~2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor4, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor5, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor8, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor7, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal1~0 , sd_ctrl_inst|sd_init_inst|Equal1~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector8~0 , sd_ctrl_inst|sd_init_inst|Selector8~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector0~0 , sd_ctrl_inst|sd_init_inst|Selector0~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal3~0 , sd_ctrl_inst|sd_init_inst|Equal3~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector6~0 , sd_ctrl_inst|sd_init_inst|Selector6~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector6~1 , sd_ctrl_inst|sd_init_inst|Selector6~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector6~2 , sd_ctrl_inst|sd_init_inst|Selector6~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector6~3 , sd_ctrl_inst|sd_init_inst|Selector6~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Selector1~1 , sd_ctrl_inst|sd_read_inst|Selector1~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Equal3~1 , sd_ctrl_inst|sd_read_inst|Equal3~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Equal3~1 , sd_ctrl_inst|sd_write_inst|Equal3~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Equal3~2 , sd_ctrl_inst|sd_write_inst|Equal3~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|state.CMD24_ACK , sd_ctrl_inst|sd_write_inst|state.CMD24_ACK, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Selector2~0 , sd_ctrl_inst|sd_write_inst|Selector2~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Add3~0 , sd_ctrl_inst|sd_write_inst|Add3~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4, uart_sd, 1 +instance = comp, \uart_rx_inst|po_data[1] , uart_rx_inst|po_data[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[9], uart_sd, 1 +instance = comp, \uart_rx_inst|po_data[5] , uart_rx_inst|po_data[5], uart_sd, 1 +instance = comp, \uart_rx_inst|po_data[6] , uart_rx_inst|po_data[6], uart_sd, 1 +instance = comp, \uart_rx_inst|po_data[2] , uart_rx_inst|po_data[2], uart_sd, 1 +instance = comp, \uart_rx_inst|po_data[7] , uart_rx_inst|po_data[7], uart_sd, 1 +instance = comp, \uart_rx_inst|po_data[3] , uart_rx_inst|po_data[3], uart_sd, 1 +instance = comp, \uart_rx_inst|po_data[0] , uart_rx_inst|po_data[0], uart_sd, 1 +instance = comp, \uart_rx_inst|po_data[4] , uart_rx_inst|po_data[4], uart_sd, 1 +instance = comp, \uart_tx_inst|work_en , uart_tx_inst|work_en, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3, uart_sd, 1 +instance = comp, \uart_tx_inst|Add1~1 , uart_tx_inst|Add1~1, uart_sd, 1 +instance = comp, \uart_tx_inst|bit_cnt[2]~3 , uart_tx_inst|bit_cnt[2]~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[3] , sd_ctrl_inst|sd_read_inst|byte_head[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[2] , sd_ctrl_inst|sd_read_inst|byte_head[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[1] , sd_ctrl_inst|sd_read_inst|byte_head[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[0] , sd_ctrl_inst|sd_read_inst|byte_head[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Equal6~1 , sd_ctrl_inst|sd_read_inst|Equal6~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit~3 , sd_ctrl_inst|sd_read_inst|cnt_data_bit~3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Selector3~0 , sd_ctrl_inst|sd_write_inst|Selector3~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Selector3~1 , sd_ctrl_inst|sd_write_inst|Selector3~1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[3], uart_sd, 1 +instance = comp, \uart_rx_inst|rx_data[1] , uart_rx_inst|rx_data[1], uart_sd, 1 +instance = comp, \uart_rx_inst|rx_data[5] , uart_rx_inst|rx_data[5], uart_sd, 1 +instance = comp, \uart_rx_inst|rx_data[6] , uart_rx_inst|rx_data[6], uart_sd, 1 +instance = comp, \uart_rx_inst|rx_data[2] , uart_rx_inst|rx_data[2], uart_sd, 1 +instance = comp, \uart_rx_inst|rx_data[7] , uart_rx_inst|rx_data[7], uart_sd, 1 +instance = comp, \uart_rx_inst|rx_data[3] , uart_rx_inst|rx_data[3], uart_sd, 1 +instance = comp, \uart_rx_inst|rx_data[0] , uart_rx_inst|rx_data[0], uart_sd, 1 +instance = comp, \uart_rx_inst|rx_data[4] , uart_rx_inst|rx_data[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|tx_flag , data_rw_ctrl_inst|tx_flag, uart_sd, 1 +instance = comp, \uart_tx_inst|work_en~0 , uart_tx_inst|work_en~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[12] , sd_ctrl_inst|sd_read_inst|rd_data_reg[12], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[11] , sd_ctrl_inst|sd_read_inst|rd_data_reg[11], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[14] , sd_ctrl_inst|sd_read_inst|rd_data_reg[14], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[10] , sd_ctrl_inst|sd_read_inst|rd_data_reg[10], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~4 , sd_ctrl_inst|sd_read_inst|byte_head~4, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~5 , sd_ctrl_inst|sd_read_inst|byte_head~5, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~6 , sd_ctrl_inst|sd_read_inst|byte_head~6, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~7 , sd_ctrl_inst|sd_read_inst|byte_head~7, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_en~0 , sd_ctrl_inst|sd_write_inst|ack_en~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_en~1 , sd_ctrl_inst|sd_write_inst|ack_en~1, uart_sd, 1 +instance = comp, \uart_rx_inst|bit_cnt[2] , uart_rx_inst|bit_cnt[2], uart_sd, 1 +instance = comp, \uart_rx_inst|always8~0 , uart_rx_inst|always8~0, uart_sd, 1 +instance = comp, \uart_rx_inst|rx_reg3 , uart_rx_inst|rx_reg3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~5 , sd_ctrl_inst|sd_read_inst|rd_data_reg~5, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~7 , sd_ctrl_inst|sd_read_inst|rd_data_reg~7, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~9 , sd_ctrl_inst|sd_read_inst|rd_data_reg~9, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~11 , sd_ctrl_inst|sd_read_inst|rd_data_reg~11, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head_en~2 , sd_ctrl_inst|sd_read_inst|byte_head_en~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head_en~3 , sd_ctrl_inst|sd_read_inst|byte_head_en~3, uart_sd, 1 +instance = comp, \uart_rx_inst|Equal2~0 , uart_rx_inst|Equal2~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a2, uart_sd, 1 +instance = comp, \uart_rx_inst|rx_reg2 , uart_rx_inst|rx_reg2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|always3~2 , data_rw_ctrl_inst|always3~2, uart_sd, 1 +instance = comp, \uart_rx_inst|Equal1~2 , uart_rx_inst|Equal1~2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~9, uart_sd, 1 +instance = comp, \uart_rx_inst|rx_reg1 , uart_rx_inst|rx_reg1, uart_sd, 1 +instance = comp, \uart_rx_inst|start_nedge , uart_rx_inst|start_nedge, uart_sd, 1 +instance = comp, \uart_rx_inst|always3~0 , uart_rx_inst|always3~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0, uart_sd, 1 +instance = comp, \uart_rx_inst|rx_data[7]~0 , uart_rx_inst|rx_data[7]~0, uart_sd, 1 +instance = comp, \uart_rx_inst|rx_reg1~0 , uart_rx_inst|rx_reg1~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0~_wirecell, uart_sd, 1 +instance = comp, \rx~input , rx~input, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[2]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[5]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[7]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[9]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[8]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|tx_flag~feeder , data_rw_ctrl_inst|tx_flag~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[8]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[7]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[5]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[3]~feeder, uart_sd, 1 +instance = comp, \uart_rx_inst|po_data[1]~feeder , uart_rx_inst|po_data[1]~feeder, uart_sd, 1 +instance = comp, \uart_rx_inst|rx_data[0]~feeder , uart_rx_inst|rx_data[0]~feeder, uart_sd, 1 +instance = comp, \uart_rx_inst|po_data[5]~feeder , uart_rx_inst|po_data[5]~feeder, uart_sd, 1 +instance = comp, \uart_rx_inst|rx_data[4]~feeder , uart_rx_inst|rx_data[4]~feeder, uart_sd, 1 +instance = comp, \uart_rx_inst|po_data[6]~feeder , uart_rx_inst|po_data[6]~feeder, uart_sd, 1 +instance = comp, \uart_rx_inst|rx_data[5]~feeder , uart_rx_inst|rx_data[5]~feeder, uart_sd, 1 +instance = comp, \uart_rx_inst|po_data[7]~feeder , uart_rx_inst|po_data[7]~feeder, uart_sd, 1 +instance = comp, \uart_rx_inst|rx_data[6]~feeder , uart_rx_inst|rx_data[6]~feeder, uart_sd, 1 +instance = comp, \uart_rx_inst|po_data[3]~feeder , uart_rx_inst|po_data[3]~feeder, uart_sd, 1 +instance = comp, \uart_rx_inst|rx_data[2]~feeder , uart_rx_inst|rx_data[2]~feeder, uart_sd, 1 +instance = comp, \uart_rx_inst|po_data[0]~feeder , uart_rx_inst|po_data[0]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[6]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[4]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[4]~feeder, uart_sd, 1 +instance = comp, \uart_rx_inst|rx_reg2~feeder , uart_rx_inst|rx_reg2~feeder, uart_sd, 1 +instance = comp, \sd_clk~output , sd_clk~output, uart_sd, 1 +instance = comp, \sd_cs_n~output , sd_cs_n~output, uart_sd, 1 +instance = comp, \sd_mosi~output , sd_mosi~output, uart_sd, 1 +instance = comp, \tx~output , tx~output, uart_sd, 1 +instance = comp, \sys_clk~input , sys_clk~input, uart_sd, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl , clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12 , sd_ctrl_inst|sd_read_inst|cnt_data_num[0]~12, uart_sd, 1 +instance = comp, \sys_rst_n~input , sys_rst_n~input, uart_sd, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder , clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder, uart_sd, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync , clk_gen_inst|altpll_component|auto_generated|pll_lock_sync, uart_sd, 1 +instance = comp, \rst_n~0 , rst_n~0, uart_sd, 1 +instance = comp, \rst_n~0clkctrl , rst_n~0clkctrl, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0]~8, uart_sd, 1 +instance = comp, \sd_miso~input , sd_miso~input, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|miso_dly , sd_ctrl_inst|sd_init_inst|miso_dly, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0]~8, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_en~0 , sd_ctrl_inst|sd_read_inst|ack_en~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2]~12, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_en~1 , sd_ctrl_inst|sd_read_inst|ack_en~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1]~10, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Equal0~1 , sd_ctrl_inst|sd_read_inst|Equal0~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_en~2 , sd_ctrl_inst|sd_read_inst|ack_en~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_en , sd_ctrl_inst|sd_read_inst|ack_en, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3]~14, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4]~16, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5]~18, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6]~20, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22 , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7]~22, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7] , sd_ctrl_inst|sd_read_inst|cnt_ack_bit[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Equal0~0 , sd_ctrl_inst|sd_read_inst|Equal0~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[7]~0 , sd_ctrl_inst|sd_read_inst|ack_data[7]~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[0] , sd_ctrl_inst|sd_read_inst|ack_data[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[1] , sd_ctrl_inst|sd_read_inst|ack_data[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder , sd_ctrl_inst|sd_read_inst|ack_data[2]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[2] , sd_ctrl_inst|sd_read_inst|ack_data[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[3] , sd_ctrl_inst|sd_read_inst|ack_data[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder , sd_ctrl_inst|sd_read_inst|ack_data[4]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[4] , sd_ctrl_inst|sd_read_inst|ack_data[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[5] , sd_ctrl_inst|sd_read_inst|ack_data[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder , sd_ctrl_inst|sd_read_inst|ack_data[6]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[6] , sd_ctrl_inst|sd_read_inst|ack_data[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|ack_data[7] , sd_ctrl_inst|sd_read_inst|ack_data[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Equal3~0 , sd_ctrl_inst|sd_read_inst|Equal3~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Equal3~2 , sd_ctrl_inst|sd_read_inst|Equal3~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0]~8, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2]~12, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3]~14, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4]~16, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5]~18, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_en~0 , sd_ctrl_inst|sd_init_inst|ack_en~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_en~1 , sd_ctrl_inst|sd_init_inst|ack_en~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_en , sd_ctrl_inst|sd_init_inst|ack_en, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1]~10, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal1~1 , sd_ctrl_inst|sd_init_inst|Equal1~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal1~2 , sd_ctrl_inst|sd_init_inst|Equal1~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[39]~2 , sd_ctrl_inst|sd_init_inst|ack_data[39]~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6]~20, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22 , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7]~22, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6] , sd_ctrl_inst|sd_init_inst|cnt_ack_bit[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[39]~3 , sd_ctrl_inst|sd_init_inst|ack_data[39]~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[0] , sd_ctrl_inst|sd_init_inst|ack_data[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[1]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[1] , sd_ctrl_inst|sd_init_inst|ack_data[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[2]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[2] , sd_ctrl_inst|sd_init_inst|ack_data[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[3] , sd_ctrl_inst|sd_init_inst|ack_data[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[4]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[4] , sd_ctrl_inst|sd_init_inst|ack_data[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[5] , sd_ctrl_inst|sd_init_inst|ack_data[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[6] , sd_ctrl_inst|sd_init_inst|ack_data[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[7] , sd_ctrl_inst|sd_init_inst|ack_data[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[8] , sd_ctrl_inst|sd_init_inst|ack_data[8], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[9]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[9] , sd_ctrl_inst|sd_init_inst|ack_data[9], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[10]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[10] , sd_ctrl_inst|sd_init_inst|ack_data[10], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[11] , sd_ctrl_inst|sd_init_inst|ack_data[11], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[12]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[12] , sd_ctrl_inst|sd_init_inst|ack_data[12], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[13]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[13] , sd_ctrl_inst|sd_init_inst|ack_data[13], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[14]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[14] , sd_ctrl_inst|sd_init_inst|ack_data[14], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[15]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[15] , sd_ctrl_inst|sd_init_inst|ack_data[15], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[16]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[16] , sd_ctrl_inst|sd_init_inst|ack_data[16], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[17] , sd_ctrl_inst|sd_init_inst|ack_data[17], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[18]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[18] , sd_ctrl_inst|sd_init_inst|ack_data[18], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[19]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[19] , sd_ctrl_inst|sd_init_inst|ack_data[19], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[20]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[20] , sd_ctrl_inst|sd_init_inst|ack_data[20], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[21] , sd_ctrl_inst|sd_init_inst|ack_data[21], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[22] , sd_ctrl_inst|sd_init_inst|ack_data[22], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[23]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[23] , sd_ctrl_inst|sd_init_inst|ack_data[23], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[24]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[24] , sd_ctrl_inst|sd_init_inst|ack_data[24], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[25]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[25] , sd_ctrl_inst|sd_init_inst|ack_data[25], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[26]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[26] , sd_ctrl_inst|sd_init_inst|ack_data[26], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[27] , sd_ctrl_inst|sd_init_inst|ack_data[27], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[28] , sd_ctrl_inst|sd_init_inst|ack_data[28], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[29] , sd_ctrl_inst|sd_init_inst|ack_data[29], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[30]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[30] , sd_ctrl_inst|sd_init_inst|ack_data[30], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[31]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[31] , sd_ctrl_inst|sd_init_inst|ack_data[31], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[32] , sd_ctrl_inst|sd_init_inst|ack_data[32], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[33]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[33] , sd_ctrl_inst|sd_init_inst|ack_data[33], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[34]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[34] , sd_ctrl_inst|sd_init_inst|ack_data[34], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[35] , sd_ctrl_inst|sd_init_inst|ack_data[35], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal2~1 , sd_ctrl_inst|sd_init_inst|Equal2~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[36] , sd_ctrl_inst|sd_init_inst|ack_data[36], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[37]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[37] , sd_ctrl_inst|sd_init_inst|ack_data[37], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder , sd_ctrl_inst|sd_init_inst|ack_data[38]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[38] , sd_ctrl_inst|sd_init_inst|ack_data[38], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|ack_data[39] , sd_ctrl_inst|sd_init_inst|ack_data[39], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal2~0 , sd_ctrl_inst|sd_init_inst|Equal2~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal2~2 , sd_ctrl_inst|sd_init_inst|Equal2~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector0~1 , sd_ctrl_inst|sd_init_inst|Selector0~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|state.SEND_CMD0 , sd_ctrl_inst|sd_init_inst|state.SEND_CMD0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~8, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11 , sd_ctrl_inst|sd_init_inst|cnt_wait[1]~11, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13 , sd_ctrl_inst|sd_init_inst|cnt_wait[2]~13, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15 , sd_ctrl_inst|sd_init_inst|cnt_wait[3]~15, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17 , sd_ctrl_inst|sd_init_inst|cnt_wait[4]~17, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[4] , sd_ctrl_inst|sd_init_inst|cnt_wait[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19 , sd_ctrl_inst|sd_init_inst|cnt_wait[5]~19, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[5] , sd_ctrl_inst|sd_init_inst|cnt_wait[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21 , sd_ctrl_inst|sd_init_inst|cnt_wait[6]~21, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23 , sd_ctrl_inst|sd_init_inst|cnt_wait[7]~23, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[7] , sd_ctrl_inst|sd_init_inst|cnt_wait[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25 , sd_ctrl_inst|sd_init_inst|cnt_wait[8]~25, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[8] , sd_ctrl_inst|sd_init_inst|cnt_wait[8], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[6] , sd_ctrl_inst|sd_init_inst|cnt_wait[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal0~1 , sd_ctrl_inst|sd_init_inst|Equal0~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal0~2 , sd_ctrl_inst|sd_init_inst|Equal0~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[2] , sd_ctrl_inst|sd_init_inst|cnt_wait[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[3] , sd_ctrl_inst|sd_init_inst|cnt_wait[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_wait[1] , sd_ctrl_inst|sd_init_inst|cnt_wait[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal0~0 , sd_ctrl_inst|sd_init_inst|Equal0~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|state.IDLE~0 , sd_ctrl_inst|sd_init_inst|state.IDLE~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|state.IDLE , sd_ctrl_inst|sd_init_inst|state.IDLE, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1]~11, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3]~15, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|state.INIT_END~0 , sd_ctrl_inst|sd_init_inst|state.INIT_END~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|state.INIT_END , sd_ctrl_inst|sd_init_inst|state.INIT_END, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|WideOr18 , sd_ctrl_inst|sd_init_inst|WideOr18, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4]~17, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6]~21, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7]~23, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal5~1 , sd_ctrl_inst|sd_init_inst|Equal5~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10 , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0]~10, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1] , sd_ctrl_inst|sd_init_inst|cnt_cmd_bit[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal5~0 , sd_ctrl_inst|sd_init_inst|Equal5~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal5~2 , sd_ctrl_inst|sd_init_inst|Equal5~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector2~0 , sd_ctrl_inst|sd_init_inst|Selector2~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|state.CMD0_ACK , sd_ctrl_inst|sd_init_inst|state.CMD0_ACK, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector1~0 , sd_ctrl_inst|sd_init_inst|Selector1~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector1~1 , sd_ctrl_inst|sd_init_inst|Selector1~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|state.SEND_CMD8 , sd_ctrl_inst|sd_init_inst|state.SEND_CMD8, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector5~0 , sd_ctrl_inst|sd_init_inst|Selector5~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|state.CMD8_ACK , sd_ctrl_inst|sd_init_inst|state.CMD8_ACK, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector4~0 , sd_ctrl_inst|sd_init_inst|Selector4~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|state.CMD55_ACK , sd_ctrl_inst|sd_init_inst|state.CMD55_ACK, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector7~0 , sd_ctrl_inst|sd_init_inst|Selector7~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK , sd_ctrl_inst|sd_init_inst|state.ACMD41_ACK, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~0 , sd_ctrl_inst|sd_init_inst|Selector14~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector3~0 , sd_ctrl_inst|sd_init_inst|Selector3~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector3~1 , sd_ctrl_inst|sd_init_inst|Selector3~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41 , sd_ctrl_inst|sd_init_inst|state.SEND_ACMD41, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector15~0 , sd_ctrl_inst|sd_init_inst|Selector15~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector15~1 , sd_ctrl_inst|sd_init_inst|Selector15~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector15~2 , sd_ctrl_inst|sd_init_inst|Selector15~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|init_end , sd_ctrl_inst|sd_init_inst|init_end, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Selector1~2 , sd_ctrl_inst|sd_read_inst|Selector1~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Selector1~3 , sd_ctrl_inst|sd_read_inst|Selector1~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|state.SEND_CMD17 , sd_ctrl_inst|sd_read_inst|state.SEND_CMD17, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1]~10, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2]~12, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3]~14, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5]~18, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6]~20, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22 , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7]~22, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Equal2~1 , sd_ctrl_inst|sd_read_inst|Equal2~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Equal2~0 , sd_ctrl_inst|sd_read_inst|Equal2~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Selector3~0 , sd_ctrl_inst|sd_read_inst|Selector3~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Selector3~1 , sd_ctrl_inst|sd_read_inst|Selector3~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|state.CMD17_ACK , sd_ctrl_inst|sd_read_inst|state.CMD17_ACK, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Selector2~0 , sd_ctrl_inst|sd_read_inst|Selector2~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Selector2~1 , sd_ctrl_inst|sd_read_inst|Selector2~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|state.RD_DATA , sd_ctrl_inst|sd_read_inst|state.RD_DATA, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head_en~0 , sd_ctrl_inst|sd_read_inst|byte_head_en~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20 , sd_ctrl_inst|sd_read_inst|cnt_data_num[4]~20, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[4] , sd_ctrl_inst|sd_read_inst|cnt_data_num[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14 , sd_ctrl_inst|sd_read_inst|cnt_data_num[1]~14, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[1] , sd_ctrl_inst|sd_read_inst|cnt_data_num[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|always3~0 , sd_ctrl_inst|sd_read_inst|always3~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head_en~1 , sd_ctrl_inst|sd_read_inst|byte_head_en~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit~2 , sd_ctrl_inst|sd_read_inst|cnt_data_bit~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit[1] , sd_ctrl_inst|sd_read_inst|cnt_data_bit[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Add3~0 , sd_ctrl_inst|sd_read_inst|Add3~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit~1 , sd_ctrl_inst|sd_read_inst|cnt_data_bit~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit[2] , sd_ctrl_inst|sd_read_inst|cnt_data_bit[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Equal9~0 , sd_ctrl_inst|sd_read_inst|Equal9~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~11 , sd_ctrl_inst|sd_read_inst|byte_head~11, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[12] , sd_ctrl_inst|sd_read_inst|byte_head[12], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~10 , sd_ctrl_inst|sd_read_inst|byte_head~10, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[13] , sd_ctrl_inst|sd_read_inst|byte_head[13], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~9 , sd_ctrl_inst|sd_read_inst|byte_head~9, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[14] , sd_ctrl_inst|sd_read_inst|byte_head[14], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~8 , sd_ctrl_inst|sd_read_inst|byte_head~8, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[15] , sd_ctrl_inst|sd_read_inst|byte_head[15], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Equal6~2 , sd_ctrl_inst|sd_read_inst|Equal6~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~14 , sd_ctrl_inst|sd_read_inst|byte_head~14, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[9] , sd_ctrl_inst|sd_read_inst|byte_head[9], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~13 , sd_ctrl_inst|sd_read_inst|byte_head~13, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[10] , sd_ctrl_inst|sd_read_inst|byte_head[10], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~12 , sd_ctrl_inst|sd_read_inst|byte_head~12, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[11] , sd_ctrl_inst|sd_read_inst|byte_head[11], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~15 , sd_ctrl_inst|sd_read_inst|byte_head~15, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[8] , sd_ctrl_inst|sd_read_inst|byte_head[8], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Equal6~3 , sd_ctrl_inst|sd_read_inst|Equal6~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Equal6~4 , sd_ctrl_inst|sd_read_inst|Equal6~4, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head_en~4 , sd_ctrl_inst|sd_read_inst|byte_head_en~4, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head_en , sd_ctrl_inst|sd_read_inst|byte_head_en, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~1 , sd_ctrl_inst|sd_read_inst|byte_head~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[6] , sd_ctrl_inst|sd_read_inst|byte_head[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~0 , sd_ctrl_inst|sd_read_inst|byte_head~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[7] , sd_ctrl_inst|sd_read_inst|byte_head[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~3 , sd_ctrl_inst|sd_read_inst|byte_head~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[4] , sd_ctrl_inst|sd_read_inst|byte_head[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head~2 , sd_ctrl_inst|sd_read_inst|byte_head~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|byte_head[5] , sd_ctrl_inst|sd_read_inst|byte_head[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Equal6~0 , sd_ctrl_inst|sd_read_inst|Equal6~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30 , sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~30, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit~0 , sd_ctrl_inst|sd_read_inst|cnt_data_bit~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_bit[3] , sd_ctrl_inst|sd_read_inst|cnt_data_bit[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31 , sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~31, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[0] , sd_ctrl_inst|sd_read_inst|cnt_data_num[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16 , sd_ctrl_inst|sd_read_inst|cnt_data_num[2]~16, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[2] , sd_ctrl_inst|sd_read_inst|cnt_data_num[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22 , sd_ctrl_inst|sd_read_inst|cnt_data_num[5]~22, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[5] , sd_ctrl_inst|sd_read_inst|cnt_data_num[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24 , sd_ctrl_inst|sd_read_inst|cnt_data_num[6]~24, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[6] , sd_ctrl_inst|sd_read_inst|cnt_data_num[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26 , sd_ctrl_inst|sd_read_inst|cnt_data_num[7]~26, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[7] , sd_ctrl_inst|sd_read_inst|cnt_data_num[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_data_num[8] , sd_ctrl_inst|sd_read_inst|cnt_data_num[8], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|always3~3 , sd_ctrl_inst|sd_read_inst|always3~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|always3~4 , sd_ctrl_inst|sd_read_inst|always3~4, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Selector4~0 , sd_ctrl_inst|sd_read_inst|Selector4~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|state.RD_END , sd_ctrl_inst|sd_read_inst|state.RD_END, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_end~1 , sd_ctrl_inst|sd_read_inst|cnt_end~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_end[0] , sd_ctrl_inst|sd_read_inst|cnt_end[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_end~2 , sd_ctrl_inst|sd_read_inst|cnt_end~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_end[1] , sd_ctrl_inst|sd_read_inst|cnt_end[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Selector0~0 , sd_ctrl_inst|sd_read_inst|Selector0~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|Selector0~1 , sd_ctrl_inst|sd_read_inst|Selector0~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|state.IDLE , sd_ctrl_inst|sd_read_inst|state.IDLE, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12 , sd_ctrl_inst|sd_write_inst|cnt_data_num[0]~12, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder , sd_ctrl_inst|sd_write_inst|ack_data[0]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0]~8, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1]~10, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2]~12, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4]~16, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6]~20, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22 , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7]~22, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6] , sd_ctrl_inst|sd_write_inst|cnt_ack_bit[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Equal1~0 , sd_ctrl_inst|sd_write_inst|Equal1~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Equal1~1 , sd_ctrl_inst|sd_write_inst|Equal1~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_en~2 , sd_ctrl_inst|sd_write_inst|ack_en~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_en , sd_ctrl_inst|sd_write_inst|ack_en, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[7]~0 , sd_ctrl_inst|sd_write_inst|ack_data[7]~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[0] , sd_ctrl_inst|sd_write_inst|ack_data[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[1] , sd_ctrl_inst|sd_write_inst|ack_data[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder , sd_ctrl_inst|sd_write_inst|ack_data[2]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[2] , sd_ctrl_inst|sd_write_inst|ack_data[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[3] , sd_ctrl_inst|sd_write_inst|ack_data[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Equal4~1 , sd_ctrl_inst|sd_write_inst|Equal4~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder , sd_ctrl_inst|sd_write_inst|ack_data[4]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[4] , sd_ctrl_inst|sd_write_inst|ack_data[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[5] , sd_ctrl_inst|sd_write_inst|ack_data[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder , sd_ctrl_inst|sd_write_inst|ack_data[6]~feeder, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[6] , sd_ctrl_inst|sd_write_inst|ack_data[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|ack_data[7] , sd_ctrl_inst|sd_write_inst|ack_data[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Equal4~0 , sd_ctrl_inst|sd_write_inst|Equal4~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Equal4~2 , sd_ctrl_inst|sd_write_inst|Equal4~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Selector2~1 , sd_ctrl_inst|sd_write_inst|Selector2~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|state.WR_DATA , sd_ctrl_inst|sd_write_inst|state.WR_DATA, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_bit~0 , sd_ctrl_inst|sd_write_inst|cnt_data_bit~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_bit[0] , sd_ctrl_inst|sd_write_inst|cnt_data_bit[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Add3~2 , sd_ctrl_inst|sd_write_inst|Add3~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_bit[1] , sd_ctrl_inst|sd_write_inst|cnt_data_bit[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Add3~1 , sd_ctrl_inst|sd_write_inst|Add3~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_bit[2] , sd_ctrl_inst|sd_write_inst|cnt_data_bit[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[0]~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16 , sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~16, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[0] , sd_ctrl_inst|sd_write_inst|cnt_data_num[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17 , sd_ctrl_inst|sd_write_inst|cnt_data_num[2]~17, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[2] , sd_ctrl_inst|sd_write_inst|cnt_data_num[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23 , sd_ctrl_inst|sd_write_inst|cnt_data_num[5]~23, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[5] , sd_ctrl_inst|sd_write_inst|cnt_data_num[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25 , sd_ctrl_inst|sd_write_inst|cnt_data_num[6]~25, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[6] , sd_ctrl_inst|sd_write_inst|cnt_data_num[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27 , sd_ctrl_inst|sd_write_inst|cnt_data_num[7]~27, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[7] , sd_ctrl_inst|sd_write_inst|cnt_data_num[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29 , sd_ctrl_inst|sd_write_inst|cnt_data_num[8]~29, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[8] , sd_ctrl_inst|sd_write_inst|cnt_data_num[8], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31 , sd_ctrl_inst|sd_write_inst|cnt_data_num[9]~31, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33 , sd_ctrl_inst|sd_write_inst|cnt_data_num[10]~33, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[10] , sd_ctrl_inst|sd_write_inst|cnt_data_num[10], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35 , sd_ctrl_inst|sd_write_inst|cnt_data_num[11]~35, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[11] , sd_ctrl_inst|sd_write_inst|cnt_data_num[11], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_data_num[9] , sd_ctrl_inst|sd_write_inst|cnt_data_num[9], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|always4~2 , sd_ctrl_inst|sd_write_inst|always4~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|always4~3 , sd_ctrl_inst|sd_write_inst|always4~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Selector4~0 , sd_ctrl_inst|sd_write_inst|Selector4~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|state.WR_BUSY , sd_ctrl_inst|sd_write_inst|state.WR_BUSY, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~8 , sd_ctrl_inst|sd_write_inst|busy_data~8, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[0] , sd_ctrl_inst|sd_write_inst|busy_data[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~7 , sd_ctrl_inst|sd_write_inst|busy_data~7, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[1] , sd_ctrl_inst|sd_write_inst|busy_data[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~6 , sd_ctrl_inst|sd_write_inst|busy_data~6, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[2] , sd_ctrl_inst|sd_write_inst|busy_data[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~5 , sd_ctrl_inst|sd_write_inst|busy_data~5, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[3] , sd_ctrl_inst|sd_write_inst|busy_data[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Equal6~1 , sd_ctrl_inst|sd_write_inst|Equal6~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~4 , sd_ctrl_inst|sd_write_inst|busy_data~4, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[4] , sd_ctrl_inst|sd_write_inst|busy_data[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~3 , sd_ctrl_inst|sd_write_inst|busy_data~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[5] , sd_ctrl_inst|sd_write_inst|busy_data[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~2 , sd_ctrl_inst|sd_write_inst|busy_data~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[6] , sd_ctrl_inst|sd_write_inst|busy_data[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data~1 , sd_ctrl_inst|sd_write_inst|busy_data~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|busy_data[7] , sd_ctrl_inst|sd_write_inst|busy_data[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Equal6~0 , sd_ctrl_inst|sd_write_inst|Equal6~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Equal6~2 , sd_ctrl_inst|sd_write_inst|Equal6~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Selector5~0 , sd_ctrl_inst|sd_write_inst|Selector5~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|state.WR_END , sd_ctrl_inst|sd_write_inst|state.WR_END, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_end~2 , sd_ctrl_inst|sd_write_inst|cnt_end~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_end[1] , sd_ctrl_inst|sd_write_inst|cnt_end[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_end~1 , sd_ctrl_inst|sd_write_inst|cnt_end~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_end[0] , sd_ctrl_inst|sd_write_inst|cnt_end[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_end~0 , sd_ctrl_inst|sd_write_inst|cnt_end~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_end[2] , sd_ctrl_inst|sd_write_inst|cnt_end[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Selector0~0 , sd_ctrl_inst|sd_write_inst|Selector0~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cs_n~0 , sd_ctrl_inst|sd_write_inst|cs_n~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cs_n , sd_ctrl_inst|sd_write_inst|cs_n, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Selector0~1 , sd_ctrl_inst|sd_write_inst|Selector0~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|state.IDLE , sd_ctrl_inst|sd_write_inst|state.IDLE, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|wr_busy_dly~feeder , data_rw_ctrl_inst|wr_busy_dly~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|wr_busy_dly , data_rw_ctrl_inst|wr_busy_dly, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|wr_busy_fall~0 , data_rw_ctrl_inst|wr_busy_fall~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|rd_en , data_rw_ctrl_inst|rd_en, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cs_n~2 , sd_ctrl_inst|sd_read_inst|cs_n~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cs_n , sd_ctrl_inst|sd_read_inst|cs_n, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_cs_n~0 , sd_ctrl_inst|sd_cs_n~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector13~1 , sd_ctrl_inst|sd_init_inst|Selector13~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal6~1 , sd_ctrl_inst|sd_init_inst|Equal6~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector13~0 , sd_ctrl_inst|sd_init_inst|Selector13~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Equal6~2 , sd_ctrl_inst|sd_init_inst|Equal6~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector13~2 , sd_ctrl_inst|sd_init_inst|Selector13~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector13~3 , sd_ctrl_inst|sd_init_inst|Selector13~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|cs_n , sd_ctrl_inst|sd_init_inst|cs_n, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_cs_n~1 , sd_ctrl_inst|sd_cs_n~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|Selector14~11 , sd_ctrl_inst|sd_init_inst|Selector14~11, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_init_inst|mosi , sd_ctrl_inst|sd_init_inst|mosi, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|mosi~0 , sd_ctrl_inst|sd_read_inst|mosi~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3] , sd_ctrl_inst|sd_read_inst|cnt_cmd_bit[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|mosi~1 , sd_ctrl_inst|sd_read_inst|mosi~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|mosi~2 , sd_ctrl_inst|sd_read_inst|mosi~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|mosi , sd_ctrl_inst|sd_read_inst|mosi, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0, uart_sd, 1 +instance = comp, \uart_rx_inst|Add1~0 , uart_rx_inst|Add1~0, uart_sd, 1 +instance = comp, \uart_rx_inst|Add1~2 , uart_rx_inst|Add1~2, uart_sd, 1 +instance = comp, \uart_rx_inst|Add1~6 , uart_rx_inst|Add1~6, uart_sd, 1 +instance = comp, \uart_rx_inst|bit_cnt~0 , uart_rx_inst|bit_cnt~0, uart_sd, 1 +instance = comp, \uart_rx_inst|bit_cnt[3] , uart_rx_inst|bit_cnt[3], uart_sd, 1 +instance = comp, \uart_rx_inst|bit_cnt~1 , uart_rx_inst|bit_cnt~1, uart_sd, 1 +instance = comp, \uart_rx_inst|bit_cnt[0] , uart_rx_inst|bit_cnt[0], uart_sd, 1 +instance = comp, \uart_rx_inst|bit_cnt[1] , uart_rx_inst|bit_cnt[1], uart_sd, 1 +instance = comp, \uart_rx_inst|always4~0 , uart_rx_inst|always4~0, uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[0]~13 , uart_rx_inst|baud_cnt[0]~13, uart_sd, 1 +instance = comp, \uart_rx_inst|Equal1~0 , uart_rx_inst|Equal1~0, uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[5]~23 , uart_rx_inst|baud_cnt[5]~23, uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[5] , uart_rx_inst|baud_cnt[5], uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[2]~17 , uart_rx_inst|baud_cnt[2]~17, uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[2] , uart_rx_inst|baud_cnt[2], uart_sd, 1 +instance = comp, \uart_rx_inst|Equal1~1 , uart_rx_inst|Equal1~1, uart_sd, 1 +instance = comp, \uart_rx_inst|Equal1~3 , uart_rx_inst|Equal1~3, uart_sd, 1 +instance = comp, \uart_rx_inst|work_en~0 , uart_rx_inst|work_en~0, uart_sd, 1 +instance = comp, \uart_rx_inst|work_en , uart_rx_inst|work_en, uart_sd, 1 +instance = comp, \uart_rx_inst|always5~0 , uart_rx_inst|always5~0, uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[0] , uart_rx_inst|baud_cnt[0], uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[1]~15 , uart_rx_inst|baud_cnt[1]~15, uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[1] , uart_rx_inst|baud_cnt[1], uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[3]~19 , uart_rx_inst|baud_cnt[3]~19, uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[3] , uart_rx_inst|baud_cnt[3], uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[6]~25 , uart_rx_inst|baud_cnt[6]~25, uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[6] , uart_rx_inst|baud_cnt[6], uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[7]~27 , uart_rx_inst|baud_cnt[7]~27, uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[7] , uart_rx_inst|baud_cnt[7], uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[8]~29 , uart_rx_inst|baud_cnt[8]~29, uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[8] , uart_rx_inst|baud_cnt[8], uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[9]~31 , uart_rx_inst|baud_cnt[9]~31, uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[9] , uart_rx_inst|baud_cnt[9], uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[11]~35 , uart_rx_inst|baud_cnt[11]~35, uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[11] , uart_rx_inst|baud_cnt[11], uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[12]~37 , uart_rx_inst|baud_cnt[12]~37, uart_sd, 1 +instance = comp, \uart_rx_inst|baud_cnt[12] , uart_rx_inst|baud_cnt[12], uart_sd, 1 +instance = comp, \uart_rx_inst|Equal2~1 , uart_rx_inst|Equal2~1, uart_sd, 1 +instance = comp, \uart_rx_inst|Equal2~2 , uart_rx_inst|Equal2~2, uart_sd, 1 +instance = comp, \uart_rx_inst|bit_flag , uart_rx_inst|bit_flag, uart_sd, 1 +instance = comp, \uart_rx_inst|always4~1 , uart_rx_inst|always4~1, uart_sd, 1 +instance = comp, \uart_rx_inst|rx_flag , uart_rx_inst|rx_flag, uart_sd, 1 +instance = comp, \uart_rx_inst|po_flag , uart_rx_inst|po_flag, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a4, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a6, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|cntr_cout[7]~1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a9, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9]~2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[10], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4]~5, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a8, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a5, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity7a[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity6, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0]~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe17a[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe16|dffe18a[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_comb_bita0~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6]~3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity9a0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity8, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2]~7, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3]~8, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5]~6, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7]~4, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8]~1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor8, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter5a7, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor7, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor6, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor6, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor5, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor4, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g_gray2bin|xor1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_brp|dffe12a[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1]~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter10a[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe13|dffe15a[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp_gray2bin|xor0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0] , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_bwp|dffe12a[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~4, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~8, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~10, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~12, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16 , data_rw_ctrl_inst|fifo_wr_data_inst|dcfifo_mixed_widths_component|auto_generated|op_1~16, uart_sd, 1 +instance = comp, \sd_ctrl_inst|comb~1 , sd_ctrl_inst|comb~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|comb~0 , sd_ctrl_inst|comb~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|comb~2 , sd_ctrl_inst|comb~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Selector1~2 , sd_ctrl_inst|sd_write_inst|Selector1~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Selector1~3 , sd_ctrl_inst|sd_write_inst|Selector1~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|state.SEND_CMD24 , sd_ctrl_inst|sd_write_inst|state.SEND_CMD24, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1]~10, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2]~12, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3]~14, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Mux0~0 , sd_ctrl_inst|sd_write_inst|Mux0~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16 , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4]~16, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5] , sd_ctrl_inst|sd_write_inst|cnt_cmd_bit[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~2 , sd_ctrl_inst|sd_write_inst|mosi~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|Equal3~0 , sd_ctrl_inst|sd_write_inst|Equal3~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~3 , sd_ctrl_inst|sd_write_inst|mosi~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~4 , sd_ctrl_inst|sd_write_inst|mosi~4, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~5 , sd_ctrl_inst|sd_write_inst|mosi~5, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|mosi~8 , sd_ctrl_inst|sd_write_inst|mosi~8, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_write_inst|mosi , sd_ctrl_inst|sd_write_inst|mosi, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_mosi~0 , sd_ctrl_inst|sd_mosi~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_mosi~1 , sd_ctrl_inst|sd_mosi~1, uart_sd, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl , clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[0]~13 , uart_tx_inst|baud_cnt[0]~13, uart_sd, 1 +instance = comp, \uart_tx_inst|Equal1~0 , uart_tx_inst|Equal1~0, uart_sd, 1 +instance = comp, \uart_tx_inst|Equal1~1 , uart_tx_inst|Equal1~1, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[4]~21 , uart_tx_inst|baud_cnt[4]~21, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[4] , uart_tx_inst|baud_cnt[4], uart_sd, 1 +instance = comp, \uart_tx_inst|Equal1~2 , uart_tx_inst|Equal1~2, uart_sd, 1 +instance = comp, \uart_tx_inst|Equal1~3 , uart_tx_inst|Equal1~3, uart_sd, 1 +instance = comp, \uart_tx_inst|always1~0 , uart_tx_inst|always1~0, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[0] , uart_tx_inst|baud_cnt[0], uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[1]~15 , uart_tx_inst|baud_cnt[1]~15, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[1] , uart_tx_inst|baud_cnt[1], uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[3]~19 , uart_tx_inst|baud_cnt[3]~19, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[3] , uart_tx_inst|baud_cnt[3], uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[6]~25 , uart_tx_inst|baud_cnt[6]~25, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[6] , uart_tx_inst|baud_cnt[6], uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[7]~27 , uart_tx_inst|baud_cnt[7]~27, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[7] , uart_tx_inst|baud_cnt[7], uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[8]~29 , uart_tx_inst|baud_cnt[8]~29, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[8] , uart_tx_inst|baud_cnt[8], uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[9]~31 , uart_tx_inst|baud_cnt[9]~31, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[9] , uart_tx_inst|baud_cnt[9], uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[11]~35 , uart_tx_inst|baud_cnt[11]~35, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[11] , uart_tx_inst|baud_cnt[11], uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[12]~37 , uart_tx_inst|baud_cnt[12]~37, uart_sd, 1 +instance = comp, \uart_tx_inst|baud_cnt[12] , uart_tx_inst|baud_cnt[12], uart_sd, 1 +instance = comp, \uart_tx_inst|Equal2~0 , uart_tx_inst|Equal2~0, uart_sd, 1 +instance = comp, \uart_tx_inst|Equal2~1 , uart_tx_inst|Equal2~1, uart_sd, 1 +instance = comp, \uart_tx_inst|bit_flag , uart_tx_inst|bit_flag, uart_sd, 1 +instance = comp, \uart_tx_inst|always3~0 , uart_tx_inst|always3~0, uart_sd, 1 +instance = comp, \uart_tx_inst|always0~1 , uart_tx_inst|always0~1, uart_sd, 1 +instance = comp, \uart_tx_inst|bit_cnt[0]~5 , uart_tx_inst|bit_cnt[0]~5, uart_sd, 1 +instance = comp, \uart_tx_inst|bit_cnt[0] , uart_tx_inst|bit_cnt[0], uart_sd, 1 +instance = comp, \uart_tx_inst|bit_cnt[1]~4 , uart_tx_inst|bit_cnt[1]~4, uart_sd, 1 +instance = comp, \uart_tx_inst|bit_cnt[1] , uart_tx_inst|bit_cnt[1], uart_sd, 1 +instance = comp, \uart_tx_inst|Add1~0 , uart_tx_inst|Add1~0, uart_sd, 1 +instance = comp, \uart_tx_inst|bit_cnt[3]~2 , uart_tx_inst|bit_cnt[3]~2, uart_sd, 1 +instance = comp, \uart_tx_inst|bit_cnt[3] , uart_tx_inst|bit_cnt[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[0]~16 , data_rw_ctrl_inst|cnt_wait[0]~16, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[3]~22 , data_rw_ctrl_inst|cnt_wait[3]~22, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[4]~24 , data_rw_ctrl_inst|cnt_wait[4]~24, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[4] , data_rw_ctrl_inst|cnt_wait[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|Equal3~0 , data_rw_ctrl_inst|Equal3~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|rd_busy_dly , data_rw_ctrl_inst|rd_busy_dly, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[0]~12 , data_rw_ctrl_inst|send_data_num[0]~12, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[0] , data_rw_ctrl_inst|send_data_num[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[1]~14 , data_rw_ctrl_inst|send_data_num[1]~14, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[1] , data_rw_ctrl_inst|send_data_num[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[2]~16 , data_rw_ctrl_inst|send_data_num[2]~16, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[2] , data_rw_ctrl_inst|send_data_num[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|always3~0 , data_rw_ctrl_inst|always3~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[4]~20 , data_rw_ctrl_inst|send_data_num[4]~20, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[4] , data_rw_ctrl_inst|send_data_num[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[5]~22 , data_rw_ctrl_inst|send_data_num[5]~22, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[7] , data_rw_ctrl_inst|send_data_num[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_num[5] , data_rw_ctrl_inst|send_data_num[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|always3~1 , data_rw_ctrl_inst|always3~1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|always3~3 , data_rw_ctrl_inst|always3~3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_en~0 , data_rw_ctrl_inst|send_data_en~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|send_data_en , data_rw_ctrl_inst|send_data_en, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|Equal3~1 , data_rw_ctrl_inst|Equal3~1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[13]~26 , data_rw_ctrl_inst|cnt_wait[13]~26, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[0] , data_rw_ctrl_inst|cnt_wait[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[1]~18 , data_rw_ctrl_inst|cnt_wait[1]~18, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[1] , data_rw_ctrl_inst|cnt_wait[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[2]~20 , data_rw_ctrl_inst|cnt_wait[2]~20, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[2] , data_rw_ctrl_inst|cnt_wait[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[3] , data_rw_ctrl_inst|cnt_wait[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|Equal2~3 , data_rw_ctrl_inst|Equal2~3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[6]~29 , data_rw_ctrl_inst|cnt_wait[6]~29, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[7]~31 , data_rw_ctrl_inst|cnt_wait[7]~31, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[7] , data_rw_ctrl_inst|cnt_wait[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[8]~33 , data_rw_ctrl_inst|cnt_wait[8]~33, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[8] , data_rw_ctrl_inst|cnt_wait[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[9]~35 , data_rw_ctrl_inst|cnt_wait[9]~35, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[9] , data_rw_ctrl_inst|cnt_wait[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[10]~37 , data_rw_ctrl_inst|cnt_wait[10]~37, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[10] , data_rw_ctrl_inst|cnt_wait[10], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[11]~39 , data_rw_ctrl_inst|cnt_wait[11]~39, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[12]~41 , data_rw_ctrl_inst|cnt_wait[12]~41, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[12] , data_rw_ctrl_inst|cnt_wait[12], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[13]~43 , data_rw_ctrl_inst|cnt_wait[13]~43, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[14]~45 , data_rw_ctrl_inst|cnt_wait[14]~45, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[14] , data_rw_ctrl_inst|cnt_wait[14], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[15]~47 , data_rw_ctrl_inst|cnt_wait[15]~47, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[15] , data_rw_ctrl_inst|cnt_wait[15], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[6] , data_rw_ctrl_inst|cnt_wait[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|Equal2~0 , data_rw_ctrl_inst|Equal2~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[13] , data_rw_ctrl_inst|cnt_wait[13], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|cnt_wait[11] , data_rw_ctrl_inst|cnt_wait[11], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|Equal2~1 , data_rw_ctrl_inst|Equal2~1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|Equal2~2 , data_rw_ctrl_inst|Equal2~2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|Equal2~4 , data_rw_ctrl_inst|Equal2~4, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|rd_fifo_rd_en , data_rw_ctrl_inst|rd_fifo_rd_en, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5]~4, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~5, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8]~8, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|LessThan2~0 , sd_ctrl_inst|sd_read_inst|LessThan2~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|LessThan2~1 , sd_ctrl_inst|sd_read_inst|LessThan2~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_en~0 , sd_ctrl_inst|sd_read_inst|rd_data_en~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_en , sd_ctrl_inst|sd_read_inst|rd_data_en, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[5], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4]~3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ws_dgrp|dffpipe15|dffe17a[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~4, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrfull_eq_comp|aneb_result_wire[0]~5, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_wrreq~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a4, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|cntr_cout[5]~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a6, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~7, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a9, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~6, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~8, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|sub_parity10a[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~5, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|parity9, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~4, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|_~3, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a5, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a7, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g1p|counter8a8, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~4, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~5, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|_~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2]~1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[2], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3]~2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[3], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~4, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6]~5, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[6], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7]~6, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[7], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9]~7, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_b[9], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a2, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~8, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a1, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~7, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|sub_parity6a0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~6, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|parity5, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|_~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1]~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g1p|counter7a[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdptr_g[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0]~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[0], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|delayed_wrptr_g[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe13a[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rs_dgwp|dffpipe12|dffe14a[1], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|rdempty_eq_comp|aneb_result_wire[0]~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|valid_rdreq~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~12 , sd_ctrl_inst|sd_read_inst|rd_data_reg~12, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[0] , sd_ctrl_inst|sd_read_inst|rd_data_reg[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~13 , sd_ctrl_inst|sd_read_inst|rd_data~13, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[6]~1 , sd_ctrl_inst|sd_read_inst|rd_data[6]~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[0] , sd_ctrl_inst|sd_read_inst|rd_data[0], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~14 , sd_ctrl_inst|sd_read_inst|rd_data_reg~14, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[1] , sd_ctrl_inst|sd_read_inst|rd_data_reg[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~10 , sd_ctrl_inst|sd_read_inst|rd_data_reg~10, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[2] , sd_ctrl_inst|sd_read_inst|rd_data_reg[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~6 , sd_ctrl_inst|sd_read_inst|rd_data_reg~6, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[3] , sd_ctrl_inst|sd_read_inst|rd_data_reg[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~4 , sd_ctrl_inst|sd_read_inst|rd_data_reg~4, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[4] , sd_ctrl_inst|sd_read_inst|rd_data_reg[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~2 , sd_ctrl_inst|sd_read_inst|rd_data_reg~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[5] , sd_ctrl_inst|sd_read_inst|rd_data_reg[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~8 , sd_ctrl_inst|sd_read_inst|rd_data_reg~8, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[6] , sd_ctrl_inst|sd_read_inst|rd_data_reg[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~0 , sd_ctrl_inst|sd_read_inst|rd_data_reg~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[7] , sd_ctrl_inst|sd_read_inst|rd_data_reg[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~13 , sd_ctrl_inst|sd_read_inst|rd_data_reg~13, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[8] , sd_ctrl_inst|sd_read_inst|rd_data_reg[8], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~14 , sd_ctrl_inst|sd_read_inst|rd_data~14, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[8] , sd_ctrl_inst|sd_read_inst|rd_data[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4]~feeder, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|wrptr_g[4], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8] , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|ram_address_a[8], uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0 , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0, uart_sd, 1 +instance = comp, \data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell , data_rw_ctrl_inst|fifo_rd_data_inst|dcfifo_mixed_widths_component|auto_generated|cntr_b|counter_reg_bit0~_wirecell, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~15 , sd_ctrl_inst|sd_read_inst|rd_data~15, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[1] , sd_ctrl_inst|sd_read_inst|rd_data[1], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~11 , sd_ctrl_inst|sd_read_inst|rd_data~11, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[2] , sd_ctrl_inst|sd_read_inst|rd_data[2], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~7 , sd_ctrl_inst|sd_read_inst|rd_data~7, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[3] , sd_ctrl_inst|sd_read_inst|rd_data[3], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~5 , sd_ctrl_inst|sd_read_inst|rd_data~5, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[4] , sd_ctrl_inst|sd_read_inst|rd_data[4], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~3 , sd_ctrl_inst|sd_read_inst|rd_data~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[5] , sd_ctrl_inst|sd_read_inst|rd_data[5], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~9 , sd_ctrl_inst|sd_read_inst|rd_data~9, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[6] , sd_ctrl_inst|sd_read_inst|rd_data[6], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~0 , sd_ctrl_inst|sd_read_inst|rd_data~0, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[7] , sd_ctrl_inst|sd_read_inst|rd_data[7], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~15 , sd_ctrl_inst|sd_read_inst|rd_data_reg~15, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[9] , sd_ctrl_inst|sd_read_inst|rd_data_reg[9], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~16 , sd_ctrl_inst|sd_read_inst|rd_data~16, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[9] , sd_ctrl_inst|sd_read_inst|rd_data[9], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~12 , sd_ctrl_inst|sd_read_inst|rd_data~12, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[10] , sd_ctrl_inst|sd_read_inst|rd_data[10], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~8 , sd_ctrl_inst|sd_read_inst|rd_data~8, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[11] , sd_ctrl_inst|sd_read_inst|rd_data[11], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~6 , sd_ctrl_inst|sd_read_inst|rd_data~6, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[12] , sd_ctrl_inst|sd_read_inst|rd_data[12], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~3 , sd_ctrl_inst|sd_read_inst|rd_data_reg~3, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[13] , sd_ctrl_inst|sd_read_inst|rd_data_reg[13], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~4 , sd_ctrl_inst|sd_read_inst|rd_data~4, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[13] , sd_ctrl_inst|sd_read_inst|rd_data[13], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~10 , sd_ctrl_inst|sd_read_inst|rd_data~10, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[14] , sd_ctrl_inst|sd_read_inst|rd_data[14], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg~1 , sd_ctrl_inst|sd_read_inst|rd_data_reg~1, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data_reg[15] , sd_ctrl_inst|sd_read_inst|rd_data_reg[15], uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data~2 , sd_ctrl_inst|sd_read_inst|rd_data~2, uart_sd, 1 +instance = comp, \sd_ctrl_inst|sd_read_inst|rd_data[15] , sd_ctrl_inst|sd_read_inst|rd_data[15], uart_sd, 1 +instance = comp, \uart_tx_inst|Mux0~0 , uart_tx_inst|Mux0~0, uart_sd, 1 +instance = comp, \uart_tx_inst|tx~0 , uart_tx_inst|tx~0, uart_sd, 1 +instance = comp, \uart_tx_inst|tx , uart_tx_inst|tx, uart_sd, 1 diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_v.sdo b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_v.sdo new file mode 100644 index 0000000..b378534 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/simulation/modelsim/uart_sd_v.sdo @@ -0,0 +1,19061 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "uart_sd") + (DATE "06/02/2023 04:03:15") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (4506:4506:4506) (4506:4506:4506)) + (PORT inclk[0] (2340:2340:2340) (2340:2340:2340)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (923:923:923)) + (PORT datab (808:808:808) (785:785:785)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (804:804:804)) + (PORT datab (1238:1238:1238) (1164:1164:1164)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (574:574:574)) + (PORT datab (334:334:334) (410:410:410)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1867:1867:1867)) + (PORT sclr (2890:2890:2890) (3064:3064:3064)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1396:1396:1396) (1367:1367:1367)) + (PORT d[1] (1359:1359:1359) (1335:1335:1335)) + (PORT d[2] (1452:1452:1452) (1414:1414:1414)) + (PORT d[3] (1585:1585:1585) (1553:1553:1553)) + (PORT d[4] (1387:1387:1387) (1364:1364:1364)) + (PORT d[5] (1594:1594:1594) (1561:1561:1561)) + (PORT d[6] (1414:1414:1414) (1386:1386:1386)) + (PORT d[7] (1413:1413:1413) (1374:1374:1374)) + (PORT clk (2265:2265:2265) (2302:2302:2302)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1000:1000:1000) (1004:1004:1004)) + (PORT d[1] (1057:1057:1057) (1051:1051:1051)) + (PORT d[2] (1285:1285:1285) (1234:1234:1234)) + (PORT d[3] (1146:1146:1146) (1091:1091:1091)) + (PORT d[4] (998:998:998) (1003:1003:1003)) + (PORT d[5] (1764:1764:1764) (1697:1697:1697)) + (PORT d[6] (1395:1395:1395) (1356:1356:1356)) + (PORT d[7] (1735:1735:1735) (1651:1651:1651)) + (PORT d[8] (1021:1021:1021) (1025:1025:1025)) + (PORT d[9] (923:923:923) (875:875:875)) + (PORT clk (2261:2261:2261) (2297:2297:2297)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1263:1263:1263) (1151:1151:1151)) + (PORT clk (2261:2261:2261) (2297:2297:2297)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2265:2265:2265) (2302:2302:2302)) + (PORT d[0] (1970:1970:1970) (1865:1865:1865)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2266:2266:2266) (2303:2303:2303)) + (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2266:2266:2266) (2303:2303:2303)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2266:2266:2266) (2303:2303:2303)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2266:2266:2266) (2303:2303:2303)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1346:1346:1346) (1254:1254:1254)) + (PORT d[1] (1033:1033:1033) (1026:1026:1026)) + (PORT d[2] (1785:1785:1785) (1710:1710:1710)) + (PORT d[3] (1782:1782:1782) (1727:1727:1727)) + (PORT d[4] (1630:1630:1630) (1616:1616:1616)) + (PORT d[5] (1873:1873:1873) (1814:1814:1814)) + (PORT d[6] (1365:1365:1365) (1328:1328:1328)) + (PORT d[7] (1459:1459:1459) (1427:1427:1427)) + (PORT d[8] (974:974:974) (920:920:920)) + (PORT clk (2215:2215:2215) (2211:2211:2211)) + (PORT stall (1591:1591:1591) (1712:1712:1712)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + (HOLD stall (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (2215:2215:2215) (2211:2211:2211)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2216:2216:2216) (2212:2212:2212)) + (IOPATH (posedge clk) pulse (0:0:0) (3182:3182:3182)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2216:2216:2216) (2212:2212:2212)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2216:2216:2216) (2212:2212:2212)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (2207:2207:2207) (2207:2207:2207)) + (PORT ena (2140:2140:2140) (2024:2024:2024)) + (IOPATH (posedge clk) q (392:392:392) (392:392:392)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (64:64:64)) + (SETUP ena (posedge clk) (64:64:64)) + (HOLD d (posedge clk) (211:211:211)) + (HOLD ena (posedge clk) (211:211:211)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1219:1219:1219) (1143:1143:1143)) + (PORT d[1] (1184:1184:1184) (1118:1118:1118)) + (PORT d[2] (1203:1203:1203) (1138:1138:1138)) + (PORT d[3] (1598:1598:1598) (1487:1487:1487)) + (PORT d[4] (1213:1213:1213) (1146:1146:1146)) + (PORT d[5] (1177:1177:1177) (1117:1117:1117)) + (PORT d[6] (1221:1221:1221) (1147:1147:1147)) + (PORT d[7] (1211:1211:1211) (1142:1142:1142)) + (PORT d[9] (1185:1185:1185) (1123:1123:1123)) + (PORT d[10] (1282:1282:1282) (1216:1216:1216)) + (PORT d[11] (1267:1267:1267) (1194:1194:1194)) + (PORT d[12] (1220:1220:1220) (1147:1147:1147)) + (PORT d[13] (1532:1532:1532) (1431:1431:1431)) + (PORT d[14] (1183:1183:1183) (1121:1121:1121)) + (PORT d[15] (1589:1589:1589) (1459:1459:1459)) + (PORT d[16] (1587:1587:1587) (1473:1473:1473)) + (PORT clk (2277:2277:2277) (2307:2307:2307)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1343:1343:1343) (1305:1305:1305)) + (PORT d[1] (1319:1319:1319) (1250:1250:1250)) + (PORT d[2] (1673:1673:1673) (1575:1575:1575)) + (PORT d[3] (1201:1201:1201) (1154:1154:1154)) + (PORT d[4] (1004:1004:1004) (992:992:992)) + (PORT d[5] (1807:1807:1807) (1681:1681:1681)) + (PORT d[6] (1680:1680:1680) (1599:1599:1599)) + (PORT d[7] (949:949:949) (949:949:949)) + (PORT d[8] (1566:1566:1566) (1421:1421:1421)) + (PORT clk (2273:2273:2273) (2302:2302:2302)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1282:1282:1282) (1174:1174:1174)) + (PORT clk (2273:2273:2273) (2302:2302:2302)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2277:2277:2277) (2307:2307:2307)) + (PORT d[0] (1989:1989:1989) (1888:1888:1888)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2308:2308:2308)) + (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2308:2308:2308)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2308:2308:2308)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1309:1309:1309) (1203:1203:1203)) + (PORT d[1] (1804:1804:1804) (1740:1740:1740)) + (PORT d[2] (1461:1461:1461) (1445:1445:1445)) + (PORT d[3] (1021:1021:1021) (1013:1013:1013)) + (PORT d[4] (1060:1060:1060) (1047:1047:1047)) + (PORT d[5] (1578:1578:1578) (1553:1553:1553)) + (PORT d[6] (1006:1006:1006) (992:992:992)) + (PORT d[7] (1333:1333:1333) (1307:1307:1307)) + (PORT d[8] (1312:1312:1312) (1273:1273:1273)) + (PORT d[9] (1627:1627:1627) (1511:1511:1511)) + (PORT clk (2227:2227:2227) (2216:2216:2216)) + (PORT stall (1248:1248:1248) (1359:1359:1359)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + (HOLD stall (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (2227:2227:2227) (2216:2216:2216)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2228:2228:2228) (2217:2217:2217)) + (IOPATH (posedge clk) pulse (0:0:0) (3182:3182:3182)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2228:2228:2228) (2217:2217:2217)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2228:2228:2228) (2217:2217:2217)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (2219:2219:2219) (2212:2212:2212)) + (PORT ena (1788:1788:1788) (1681:1681:1681)) + (IOPATH (posedge clk) q (392:392:392) (392:392:392)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (64:64:64)) + (SETUP ena (posedge clk) (64:64:64)) + (HOLD d (posedge clk) (211:211:211)) + (HOLD ena (posedge clk) (211:211:211)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[5\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (610:610:610)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (481:481:481)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (464:464:464)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (459:459:459)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[9\]\~32) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[10\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[11\]\~36) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (449:449:449)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (423:423:423)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (433:433:433)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (462:462:462)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (430:430:430)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[5\]\~27) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (450:450:450)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[3\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (432:432:432)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (435:435:435)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[8\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[9\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[10\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (426:426:426)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[11\]\~34) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (436:436:436)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT datac (805:805:805) (798:798:798)) + (PORT datad (312:312:312) (392:392:392)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD55) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT datab (628:628:628) (632:632:632)) + (PORT datac (580:580:580) (595:595:595)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (432:432:432)) + (PORT datab (565:565:565) (593:593:593)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (605:605:605)) + (PORT datab (342:342:342) (425:425:425)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~0) + (DELAY + (ABSOLUTE + (PORT datac (524:524:524) (558:558:558)) + (PORT datad (474:474:474) (446:446:446)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~1) + (DELAY + (ABSOLUTE + (PORT dataa (287:287:287) (326:326:326)) + (PORT datab (642:642:642) (657:657:657)) + (PORT datac (1966:1966:1966) (1886:1886:1886)) + (PORT datad (1111:1111:1111) (1012:1012:1012)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (463:463:463)) + (PORT datab (359:359:359) (454:454:454)) + (PORT datac (317:317:317) (411:411:411)) + (PORT datad (321:321:321) (404:404:404)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (627:627:627)) + (PORT datab (394:394:394) (508:508:508)) + (PORT datac (924:924:924) (871:871:871)) + (PORT datad (508:508:508) (485:485:485)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (953:953:953) (919:919:919)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (508:508:508) (494:494:494)) + (PORT datad (355:355:355) (466:466:466)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (585:585:585)) + (PORT datab (383:383:383) (479:479:479)) + (PORT datac (566:566:566) (543:543:543)) + (PORT datad (356:356:356) (467:467:467)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (315:315:315)) + (PORT datab (385:385:385) (481:481:481)) + (PORT datac (1679:1679:1679) (1549:1549:1549)) + (PORT datad (928:928:928) (884:884:884)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (628:628:628)) + (PORT datab (389:389:389) (503:503:503)) + (PORT datac (906:906:906) (851:851:851)) + (PORT datad (513:513:513) (492:492:492)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (985:985:985) (925:925:925)) + (PORT datab (384:384:384) (480:480:480)) + (PORT datac (449:449:449) (425:425:425)) + (PORT datad (943:943:943) (885:885:885)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (366:366:366) (458:458:458)) + (PORT datac (343:343:343) (439:439:439)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~7) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (926:926:926)) + (PORT datab (384:384:384) (480:480:480)) + (PORT datac (559:559:559) (534:534:534)) + (PORT datad (354:354:354) (464:464:464)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (946:946:946) (905:905:905)) + (PORT datab (398:398:398) (513:513:513)) + (PORT datac (558:558:558) (533:533:533)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~6) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (370:370:370) (462:462:462)) + (PORT datac (238:238:238) (265:265:265)) + (PORT datad (240:240:240) (258:258:258)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~7) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (327:327:327)) + (PORT datab (641:641:641) (656:656:656)) + (PORT datac (573:573:573) (592:592:592)) + (PORT datad (868:868:868) (822:822:822)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1004:1004:1004) (1026:1026:1026)) + (PORT datab (1097:1097:1097) (1105:1105:1105)) + (PORT datac (975:975:975) (1007:1007:1007)) + (PORT datad (1014:1014:1014) (1020:1020:1020)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~2) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (1013:1013:1013)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (974:974:974) (1005:1005:1005)) + (PORT datad (978:978:978) (973:973:973)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1026:1026:1026)) + (PORT datab (1018:1018:1018) (1046:1046:1046)) + (PORT datac (1038:1038:1038) (1061:1061:1061)) + (PORT datad (1012:1012:1012) (1018:1018:1018)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~3) + (DELAY + (ABSOLUTE + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (954:954:954) (967:967:967)) + (PORT datad (898:898:898) (902:902:902)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1004:1004:1004) (1026:1026:1026)) + (PORT datab (1093:1093:1093) (1100:1100:1100)) + (PORT datac (958:958:958) (977:977:977)) + (PORT datad (1013:1013:1013) (1018:1018:1018)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1027:1027:1027)) + (PORT datab (1017:1017:1017) (1045:1045:1045)) + (PORT datac (953:953:953) (966:966:966)) + (PORT datad (237:237:237) (256:256:256)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1004:1004:1004) (1026:1026:1026)) + (PORT datab (1019:1019:1019) (1048:1048:1048)) + (PORT datac (956:956:956) (975:975:975)) + (PORT datad (1014:1014:1014) (1019:1019:1019)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~7) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (1012:1012:1012)) + (PORT datab (1097:1097:1097) (1104:1104:1104)) + (PORT datac (974:974:974) (1006:1006:1006)) + (PORT datad (237:237:237) (256:256:256)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (1026:1026:1026)) + (PORT datab (1099:1099:1099) (1107:1107:1107)) + (PORT datac (975:975:975) (1008:1008:1008)) + (PORT datad (1015:1015:1015) (1021:1021:1021)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~8) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (1011:1011:1011)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (955:955:955) (974:974:974)) + (PORT datad (900:900:900) (898:898:898)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~9) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (906:906:906) (904:904:904)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1056:1056:1056) (1042:1042:1042)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT datac (335:335:335) (423:423:423)) + (PORT datad (341:341:341) (440:440:440)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (877:877:877)) + (PORT datab (392:392:392) (494:494:494)) + (PORT datac (353:353:353) (473:473:473)) + (PORT datad (867:867:867) (797:797:797)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (310:310:310)) + (PORT datab (390:390:390) (492:492:492)) + (PORT datac (851:851:851) (786:786:786)) + (PORT datad (878:878:878) (811:811:811)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (811:811:811)) + (PORT datab (397:397:397) (515:515:515)) + (PORT datac (809:809:809) (750:750:750)) + (PORT datad (348:348:348) (449:449:449)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~4) + (DELAY + (ABSOLUTE + (PORT datab (398:398:398) (515:515:515)) + (PORT datac (811:811:811) (754:754:754)) + (PORT datad (349:349:349) (450:450:450)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (337:337:337) (424:424:424)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (433:433:433)) + (PORT datab (353:353:353) (439:439:439)) + (PORT datad (531:531:531) (559:559:559)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (628:628:628)) + (PORT datab (360:360:360) (449:449:449)) + (PORT datac (316:316:316) (413:413:413)) + (PORT datad (263:263:263) (280:280:280)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~2) + (DELAY + (ABSOLUTE + (PORT datab (615:615:615) (619:619:619)) + (PORT datac (564:564:564) (579:579:579)) + (PORT datad (521:521:521) (540:540:540)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT asdata (1696:1696:1696) (1660:1660:1660)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (907:907:907)) + (PORT datab (1228:1228:1228) (1188:1188:1188)) + (PORT datac (341:341:341) (430:430:430)) + (PORT datad (254:254:254) (283:283:283)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT datab (353:353:353) (439:439:439)) + (PORT datac (354:354:354) (438:438:438)) + (PORT datad (274:274:274) (295:295:295)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT datab (595:595:595) (631:631:631)) + (PORT datad (254:254:254) (283:283:283)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT datab (883:883:883) (842:842:842)) + (PORT datac (810:810:810) (790:790:790)) + (PORT datad (764:764:764) (700:700:700)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT datac (810:810:810) (790:790:790)) + (PORT datad (764:764:764) (700:700:700)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datac (1269:1269:1269) (1235:1235:1235)) + (PORT datad (1212:1212:1212) (1150:1150:1150)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (437:437:437)) + (PORT datac (312:312:312) (400:400:400)) + (PORT datad (323:323:323) (402:402:402)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (473:473:473)) + (PORT datab (352:352:352) (442:442:442)) + (PORT datac (336:336:336) (426:426:426)) + (PORT datad (313:313:313) (393:393:393)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (445:445:445)) + (PORT datab (294:294:294) (333:333:333)) + (PORT datac (845:845:845) (833:833:833)) + (PORT datad (256:256:256) (282:282:282)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (919:919:919)) + (PORT datab (590:590:590) (574:574:574)) + (PORT datac (1103:1103:1103) (1004:1004:1004)) + (PORT datad (338:338:338) (419:419:419)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (PORT datab (343:343:343) (423:423:423)) + (PORT datad (300:300:300) (373:373:373)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT datab (976:976:976) (910:910:910)) + (PORT datac (788:788:788) (717:717:717)) + (PORT datad (340:340:340) (424:424:424)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (446:446:446)) + (PORT datab (294:294:294) (333:333:333)) + (PORT datac (845:845:845) (833:833:833)) + (PORT datad (256:256:256) (281:281:281)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1181:1181:1181) (1102:1102:1102)) + (PORT datab (362:362:362) (452:452:452)) + (PORT datac (318:318:318) (416:416:416)) + (PORT datad (482:482:482) (469:469:469)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (279:279:279) (304:304:304)) + (PORT datac (494:494:494) (468:468:468)) + (PORT datad (826:826:826) (758:758:758)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (483:483:483)) + (PORT datab (285:285:285) (317:317:317)) + (PORT datac (495:495:495) (475:475:475)) + (PORT datad (972:972:972) (966:966:966)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (432:432:432)) + (PORT datab (340:340:340) (419:419:419)) + (PORT datad (320:320:320) (390:390:390)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (462:462:462)) + (PORT datab (342:342:342) (425:425:425)) + (PORT datac (302:302:302) (386:386:386)) + (PORT datad (320:320:320) (407:407:407)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (464:464:464)) + (PORT datab (276:276:276) (300:300:300)) + (PORT datad (249:249:249) (271:271:271)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.CMD24_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datab (515:515:515) (501:501:501)) + (PORT datac (486:486:486) (463:463:463)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (603:603:603)) + (PORT datab (397:397:397) (512:512:512)) + (PORT datad (329:329:329) (420:420:420)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (1341:1341:1341) (1329:1329:1329)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (934:934:934)) + (PORT datab (867:867:867) (869:869:869)) + (PORT datad (903:903:903) (893:893:893)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (760:760:760) (830:830:830)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (941:941:941)) + (PORT datab (944:944:944) (930:930:930)) + (PORT datad (293:293:293) (363:363:363)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (760:760:760) (829:829:829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (982:982:982) (959:959:959)) + (PORT datab (888:888:888) (883:883:883)) + (PORT datad (881:881:881) (876:876:876)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (973:973:973) (988:988:988)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1189:1189:1189) (1105:1105:1105)) + (PORT datab (905:905:905) (896:896:896)) + (PORT datad (296:296:296) (365:365:365)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (471:471:471)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (482:482:482) (450:450:450)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (932:932:932)) + (PORT datab (1342:1342:1342) (1281:1281:1281)) + (PORT datad (310:310:310) (394:394:394)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1612:1612:1612) (1516:1516:1516)) + (PORT datab (921:921:921) (910:910:910)) + (PORT datad (549:549:549) (573:573:573)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[9\]) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT asdata (769:769:769) (844:844:844)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT asdata (772:772:772) (848:848:848)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1664:1664:1664)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT asdata (1327:1327:1327) (1294:1294:1294)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (912:912:912)) + (PORT datab (617:617:617) (631:631:631)) + (PORT datad (295:295:295) (365:365:365)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1347:1347:1347) (1288:1288:1288)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT asdata (761:761:761) (831:831:831)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (626:626:626)) + (PORT datab (827:827:827) (817:817:817)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT datab (391:391:391) (507:507:507)) + (PORT datac (336:336:336) (424:424:424)) + (PORT datad (340:340:340) (439:439:439)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (295:295:295) (330:330:330)) + (PORT datad (291:291:291) (325:325:325)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (936:936:936) (946:946:946)) + (PORT datab (341:341:341) (421:421:421)) + (PORT datac (305:305:305) (389:389:389)) + (PORT datad (301:301:301) (378:378:378)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1366:1366:1366) (1361:1361:1361)) + (PORT datad (291:291:291) (319:319:319)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT asdata (760:760:760) (829:829:829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datab (515:515:515) (501:501:501)) + (PORT datac (487:487:487) (463:463:463)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (2013:2013:2013) (1835:1835:1835)) + (PORT datac (330:330:330) (415:415:415)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (1740:1740:1740) (1706:1706:1706)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (1825:1825:1825) (1791:1791:1791)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (794:794:794) (869:869:869)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT asdata (771:771:771) (846:846:846)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1624:1624:1624)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1624:1624:1624)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1624:1624:1624)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1624:1624:1624)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT ena (1107:1107:1107) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT asdata (771:771:771) (846:846:846)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1624:1624:1624)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1624:1624:1624)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT ena (1710:1710:1710) (1624:1624:1624)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|tx_flag) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (424:424:424)) + (PORT datad (1118:1118:1118) (1013:1013:1013)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT asdata (768:768:768) (843:843:843)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT asdata (762:762:762) (832:832:832)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1311:1311:1311) (1233:1233:1233)) + (PORT datab (980:980:980) (943:943:943)) + (PORT datac (362:362:362) (451:451:451)) + (PORT datad (282:282:282) (306:306:306)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~4) + (DELAY + (ABSOLUTE + (PORT datab (421:421:421) (544:544:544)) + (PORT datac (303:303:303) (388:388:388)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~5) + (DELAY + (ABSOLUTE + (PORT datab (421:421:421) (544:544:544)) + (PORT datac (307:307:307) (391:391:391)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~6) + (DELAY + (ABSOLUTE + (PORT dataa (942:942:942) (953:953:953)) + (PORT datac (377:377:377) (502:502:502)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~7) + (DELAY + (ABSOLUTE + (PORT dataa (4197:4197:4197) (4406:4406:4406)) + (PORT datad (917:917:917) (911:911:911)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT asdata (789:789:789) (859:859:859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3759:3759:3759) (3988:3988:3988)) + (PORT datab (354:354:354) (440:440:440)) + (PORT datac (579:579:579) (595:595:595)) + (PORT datad (922:922:922) (922:922:922)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (468:468:468)) + (PORT datab (353:353:353) (441:441:441)) + (PORT datac (531:531:531) (562:562:562)) + (PORT datad (237:237:237) (256:256:256)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (478:478:478)) + (PORT datab (303:303:303) (340:340:340)) + (PORT datac (337:337:337) (429:429:429)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg3) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT asdata (2143:2143:2143) (2068:2068:2068)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT asdata (1042:1042:1042) (1075:1075:1075)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1685:1685:1685) (1653:1653:1653)) + (PORT datab (1310:1310:1310) (1222:1222:1222)) + (PORT datac (307:307:307) (394:394:394)) + (PORT datad (1199:1199:1199) (1130:1130:1130)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1672:1672:1672) (1637:1637:1637)) + (PORT datab (1306:1306:1306) (1218:1218:1218)) + (PORT datac (301:301:301) (386:386:386)) + (PORT datad (1203:1203:1203) (1136:1136:1136)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1389:1389:1389) (1384:1384:1384)) + (PORT datab (900:900:900) (861:861:861)) + (PORT datac (1136:1136:1136) (1066:1066:1066)) + (PORT datad (304:304:304) (377:377:377)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1275:1275:1275) (1196:1196:1196)) + (PORT datab (1307:1307:1307) (1218:1218:1218)) + (PORT datac (1621:1621:1621) (1577:1577:1577)) + (PORT datad (307:307:307) (382:382:382)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~2) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (466:466:466)) + (PORT datab (370:370:370) (466:466:466)) + (PORT datac (311:311:311) (399:399:399)) + (PORT datad (312:312:312) (388:388:388)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1367:1367:1367) (1362:1362:1362)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (645:645:645)) + (PORT datab (856:856:856) (845:845:845)) + (PORT datac (537:537:537) (560:560:560)) + (PORT datad (527:527:527) (551:551:551)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a2) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1595:1595:1595) (1481:1481:1481)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1875:1875:1875) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (599:599:599)) + (PORT datab (341:341:341) (424:424:424)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (449:449:449)) + (PORT datab (349:349:349) (438:438:438)) + (PORT datac (311:311:311) (401:401:401)) + (PORT datad (311:311:311) (391:391:391)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT datab (365:365:365) (442:442:442)) + (PORT datad (324:324:324) (395:395:395)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1875:1875:1875) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|start_nedge) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (438:438:438)) + (PORT datac (1672:1672:1672) (1604:1604:1604)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (306:306:306) (392:392:392)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (301:301:301) (386:386:386)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg1\~0) + (DELAY + (ABSOLUTE + (PORT datad (3662:3662:3662) (3834:3834:3834)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (346:346:346) (436:436:436)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rx\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (796:796:796) (842:842:842)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (550:550:550) (581:581:581)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (971:971:971) (966:966:966)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1242:1242:1242) (1210:1210:1210)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (326:326:326) (397:397:397)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (536:536:536) (568:568:568)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1468:1468:1468) (1342:1342:1342)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|tx_flag\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (325:325:325) (396:396:396)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (904:904:904) (893:893:893)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (306:306:306) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (376:376:376)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (305:305:305) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (377:377:377)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (377:377:377)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (305:305:305) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (908:908:908) (909:909:909)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (906:906:906) (907:907:907)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (378:378:378)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (305:305:305) (378:378:378)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (884:884:884) (878:878:878)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (809:809:809) (780:780:780)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (364:364:364)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sd_clk\~output) + (DELAY + (ABSOLUTE + (PORT i (1609:1609:1609) (1559:1559:1559)) + (IOPATH i o (3241:3241:3241) (3144:3144:3144)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sd_cs_n\~output) + (DELAY + (ABSOLUTE + (PORT i (1891:1891:1891) (1762:1762:1762)) + (IOPATH i o (3241:3241:3241) (3144:3144:3144)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sd_mosi\~output) + (DELAY + (ABSOLUTE + (PORT i (1825:1825:1825) (1696:1696:1696)) + (IOPATH i o (3241:3241:3241) (3144:3144:3144)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tx\~output) + (DELAY + (ABSOLUTE + (PORT i (2904:2904:2904) (3042:3042:3042)) + (IOPATH i o (3336:3336:3336) (3399:3399:3399)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (806:806:806) (852:852:852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (374:374:374) (460:460:460)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (3674:3674:3674) (3934:3934:3934)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (4634:4634:4634) (4434:4434:4434)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3009:3009:3009) (3252:3252:3252)) + (PORT datab (3770:3770:3770) (3925:3925:3925)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2603:2603:2603) (2464:2464:2464)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sd_miso\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|miso_dly) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT asdata (4598:4598:4598) (4812:4812:4812)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (4196:4196:4196) (4405:4405:4405)) + (PORT datab (344:344:344) (427:427:427)) + (PORT datad (528:528:528) (555:555:555)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (643:643:643)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (846:846:846) (813:813:813)) + (PORT datad (553:553:553) (574:574:574)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (568:568:568) (605:605:605)) + (PORT datab (891:891:891) (857:857:857)) + (PORT datac (844:844:844) (810:810:810)) + (PORT datad (552:552:552) (573:573:573)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en\~2) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (529:529:529)) + (PORT datab (491:491:491) (476:476:476)) + (PORT datad (254:254:254) (282:282:282)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_en) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (435:435:435)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_ack_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (PORT sclr (1215:1215:1215) (1257:1257:1257)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (603:603:603)) + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (303:303:303) (387:387:387)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (626:626:626)) + (PORT datac (499:499:499) (480:480:480)) + (PORT datad (320:320:320) (390:390:390)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT asdata (1676:1676:1676) (1638:1638:1638)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT asdata (768:768:768) (844:844:844)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (380:380:380)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT asdata (998:998:998) (1014:1014:1014)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (365:365:365)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT asdata (786:786:786) (856:856:856)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (380:380:380)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|ack_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT asdata (768:768:768) (844:844:844)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT ena (1644:1644:1644) (1548:1548:1548)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (432:432:432)) + (PORT datab (342:342:342) (421:421:421)) + (PORT datad (523:523:523) (549:549:549)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (774:774:774)) + (PORT datac (446:446:446) (418:418:418)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (435:435:435)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (433:433:433)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (459:459:459)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (385:385:385) (476:476:476)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (482:482:482)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3848:3848:3848) (4133:4133:4133)) + (PORT datab (949:949:949) (947:947:947)) + (PORT datac (347:347:347) (443:443:443)) + (PORT datad (349:349:349) (434:434:434)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (521:521:521)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datad (246:246:246) (271:271:271)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_en) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (430:430:430)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datac (310:310:310) (399:399:399)) + (PORT datad (320:320:320) (411:411:411)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datab (286:286:286) (314:314:314)) + (PORT datac (347:347:347) (443:443:443)) + (PORT datad (349:349:349) (433:433:433)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (462:462:462)) + (PORT datab (343:343:343) (422:422:422)) + (PORT datac (345:345:345) (440:440:440)) + (PORT datad (347:347:347) (431:431:431)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (474:474:474)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (380:380:380) (466:466:466)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_ack_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (337:337:337) (427:427:427)) + (PORT datad (338:338:338) (423:423:423)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT asdata (1262:1262:1262) (1239:1239:1239)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT asdata (762:762:762) (832:832:832)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (299:299:299) (370:370:370)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT asdata (759:759:759) (828:828:828)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT asdata (761:761:761) (830:830:830)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT asdata (761:761:761) (830:830:830)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT asdata (760:760:760) (829:829:829)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (306:306:306) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (381:381:381)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT asdata (998:998:998) (1021:1021:1021)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1853:1853:1853)) + (PORT ena (1944:1944:1944) (1786:1786:1786)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (894:894:894) (890:890:890)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT asdata (761:761:761) (830:830:830)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT asdata (762:762:762) (832:832:832)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT asdata (760:760:760) (829:829:829)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[24\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (369:369:369)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[25\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (365:365:365)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[26\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[27\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT asdata (762:762:762) (831:831:831)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[28\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT asdata (763:763:763) (833:833:833)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[29\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT asdata (760:760:760) (829:829:829)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[30\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (364:364:364)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[31\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1865:1865:1865)) + (PORT ena (1587:1587:1587) (1463:1463:1463)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[32\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (1246:1246:1246) (1218:1218:1218)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (314:314:314) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[33\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (508:508:508) (535:535:535)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[34\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[35\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (982:982:982) (1002:1002:1002)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (590:590:590)) + (PORT datad (506:506:506) (534:534:534)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[36\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (971:971:971) (986:986:986)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (380:380:380)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[37\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (302:302:302) (375:375:375)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[38\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|ack_data\[39\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (770:770:770) (846:846:846)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (PORT ena (1335:1335:1335) (1275:1275:1275)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (PORT datab (343:343:343) (424:424:424)) + (PORT datad (304:304:304) (376:376:376)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT datab (294:294:294) (333:333:333)) + (PORT datad (256:256:256) (282:282:282)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (883:883:883) (802:802:802)) + (PORT datac (320:320:320) (416:416:416)) + (PORT datad (482:482:482) (469:469:469)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD0) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\]\~13) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (433:433:433)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\]\~25) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (447:447:447)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (600:600:600)) + (PORT datab (341:341:341) (424:424:424)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (284:284:284) (315:315:315)) + (PORT datac (311:311:311) (402:402:402)) + (PORT datad (248:248:248) (270:270:270)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_wait\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT sload (1066:1066:1066) (1150:1150:1150)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (433:433:433)) + (PORT datab (342:342:342) (425:425:425)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE\~0) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (452:452:452)) + (PORT datab (286:286:286) (317:317:317)) + (PORT datad (249:249:249) (271:271:271)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END\~0) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (785:785:785)) + (PORT datad (788:788:788) (706:706:706)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.INIT_END) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|WideOr18) + (DELAY + (ABSOLUTE + (PORT datab (531:531:531) (520:520:520)) + (PORT datac (306:306:306) (392:392:392)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (369:369:369) (449:449:449)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\]\~21) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (426:426:426)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (436:436:436)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (609:609:609)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (328:328:328) (405:405:405)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (959:959:959) (947:947:947)) + (PORT datac (864:864:864) (812:812:812)) + (PORT datad (285:285:285) (313:313:313)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cnt_cmd_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (PORT sclr (903:903:903) (966:966:966)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1004:1004:1004) (1026:1026:1026)) + (PORT datab (1099:1099:1099) (1107:1107:1107)) + (PORT datac (975:975:975) (1007:1007:1007)) + (PORT datad (1015:1015:1015) (1021:1021:1021)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal5\~2) + (DELAY + (ABSOLUTE + (PORT datac (858:858:858) (805:805:805)) + (PORT datad (279:279:279) (306:306:306)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (782:782:782) (733:733:733)) + (PORT datab (381:381:381) (464:464:464)) + (PORT datad (530:530:530) (526:526:526)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD0_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1182:1182:1182) (1104:1104:1104)) + (PORT datab (359:359:359) (453:453:453)) + (PORT datac (320:320:320) (416:416:416)) + (PORT datad (479:479:479) (466:466:466)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (784:784:784) (734:734:734)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datad (531:531:531) (528:528:528)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_CMD8) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (736:736:736)) + (PORT datab (371:371:371) (455:455:455)) + (PORT datad (532:532:532) (529:529:529)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD8_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (475:475:475)) + (PORT datab (594:594:594) (578:578:578)) + (PORT datad (826:826:826) (758:758:758)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.CMD55_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (462:462:462)) + (PORT datab (591:591:591) (574:574:574)) + (PORT datad (820:820:820) (752:752:752)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.ACMD41_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (462:462:462)) + (PORT datab (359:359:359) (452:452:452)) + (PORT datac (316:316:316) (410:410:410)) + (PORT datad (321:321:321) (392:392:392)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT datab (980:980:980) (914:914:914)) + (PORT datac (793:793:793) (723:723:723)) + (PORT datad (329:329:329) (406:406:406)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (519:519:519)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (319:319:319) (413:413:413)) + (PORT datad (824:824:824) (756:756:756)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|state\.SEND_ACMD41) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (472:472:472)) + (PORT datab (370:370:370) (454:454:454)) + (PORT datac (538:538:538) (572:572:572)) + (PORT datad (338:338:338) (419:419:419)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~1) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (857:857:857)) + (PORT datab (324:324:324) (355:355:355)) + (PORT datac (522:522:522) (494:494:494)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (441:441:441)) + (PORT datab (531:531:531) (520:520:520)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|init_end) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (445:445:445)) + (PORT datac (805:805:805) (798:798:798)) + (PORT datad (338:338:338) (418:418:418)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (818:818:818)) + (PORT datab (830:830:830) (770:770:770)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (1185:1185:1185) (1096:1096:1096)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.SEND_CMD17) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (442:442:442)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (369:369:369) (450:450:450)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (450:450:450)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (599:599:599)) + (PORT datab (351:351:351) (440:440:440)) + (PORT datac (318:318:318) (413:413:413)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (444:444:444)) + (PORT datac (326:326:326) (411:411:411)) + (PORT datad (309:309:309) (389:389:389)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (483:483:483)) + (PORT datab (285:285:285) (316:316:316)) + (PORT datac (495:495:495) (475:475:475)) + (PORT datad (972:972:972) (967:967:967)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (531:531:531)) + (PORT datab (1201:1201:1201) (1076:1076:1076)) + (PORT datad (255:255:255) (283:283:283)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.CMD17_ACK) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (336:336:336)) + (PORT datab (345:345:345) (428:428:428)) + (PORT datac (504:504:504) (486:486:486)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (784:784:784)) + (PORT datab (854:854:854) (816:816:816)) + (PORT datad (1184:1184:1184) (1095:1095:1095)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_DATA) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (627:627:627)) + (PORT datab (359:359:359) (453:453:453)) + (PORT datac (338:338:338) (428:428:428)) + (PORT datad (318:318:318) (405:405:405)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (433:433:433)) + (PORT datab (565:565:565) (594:594:594)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (301:301:301) (378:378:378)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (341:341:341)) + (PORT datab (530:530:530) (492:492:492)) + (PORT datac (509:509:509) (480:480:480)) + (PORT datad (574:574:574) (595:595:595)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~2) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (464:464:464)) + (PORT datab (1663:1663:1663) (1589:1589:1589)) + (PORT datad (291:291:291) (319:319:319)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Add3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (470:470:470)) + (PORT datac (314:314:314) (403:403:403)) + (PORT datad (312:312:312) (389:389:389)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1369:1369:1369) (1364:1364:1364)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (292:292:292) (319:319:319)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (465:465:465)) + (PORT datac (310:310:310) (398:398:398)) + (PORT datad (311:311:311) (388:388:388)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~11) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (453:453:453)) + (PORT datad (601:601:601) (651:651:651)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~10) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (704:704:704)) + (PORT datac (301:301:301) (385:385:385)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~9) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (704:704:704)) + (PORT datad (506:506:506) (537:537:537)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~8) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (702:702:702)) + (PORT datac (303:303:303) (386:386:386)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (437:437:437)) + (PORT datab (550:550:550) (585:585:585)) + (PORT datac (304:304:304) (387:387:387)) + (PORT datad (295:295:295) (365:365:365)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~14) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (622:622:622)) + (PORT datad (600:600:600) (650:650:650)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~13) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (700:700:700)) + (PORT datac (304:304:304) (389:389:389)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~12) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (701:701:701)) + (PORT datac (302:302:302) (386:386:386)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~15) + (DELAY + (ABSOLUTE + (PORT datab (421:421:421) (544:544:544)) + (PORT datac (302:302:302) (387:387:387)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (431:431:431)) + (PORT datab (343:343:343) (424:424:424)) + (PORT datac (535:535:535) (553:553:553)) + (PORT datad (534:534:534) (560:560:560)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~4) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (531:531:531)) + (PORT datab (287:287:287) (319:319:319)) + (PORT datac (506:506:506) (485:485:485)) + (PORT datad (490:490:490) (461:461:461)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en\~4) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (475:475:475)) + (PORT datab (889:889:889) (798:798:798)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head_en) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~1) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (436:436:436)) + (PORT datab (422:422:422) (545:545:545)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~0) + (DELAY + (ABSOLUTE + (PORT datab (421:421:421) (544:544:544)) + (PORT datac (304:304:304) (388:388:388)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~3) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (435:435:435)) + (PORT datab (422:422:422) (545:545:545)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\~2) + (DELAY + (ABSOLUTE + (PORT datab (421:421:421) (545:545:545)) + (PORT datac (304:304:304) (389:389:389)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|byte_head\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (433:433:433)) + (PORT datab (343:343:343) (423:423:423)) + (PORT datac (300:300:300) (383:383:383)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~30) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (530:530:530)) + (PORT datab (286:286:286) (318:318:318)) + (PORT datac (505:505:505) (484:484:484)) + (PORT datad (490:490:490) (461:461:461)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1366:1366:1366) (1360:1360:1360)) + (PORT datab (323:323:323) (360:360:360)) + (PORT datad (291:291:291) (319:319:319)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (1369:1369:1369) (1364:1364:1364)) + (PORT datab (322:322:322) (359:359:359)) + (PORT datac (445:445:445) (427:427:427)) + (PORT datad (333:333:333) (427:427:427)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (453:453:453)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (449:449:449)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_data_num\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1853:1853:1853)) + (PORT sclr (1597:1597:1597) (1663:1663:1663)) + (PORT ena (1276:1276:1276) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~3) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (344:344:344)) + (PORT datab (321:321:321) (358:358:358)) + (PORT datac (518:518:518) (550:550:550)) + (PORT datad (332:332:332) (426:426:426)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|always3\~4) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (498:498:498)) + (PORT datab (634:634:634) (643:643:643)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (499:499:499)) + (PORT datab (854:854:854) (816:816:816)) + (PORT datad (516:516:516) (550:550:550)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.RD_END) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~1) + (DELAY + (ABSOLUTE + (PORT datad (531:531:531) (560:560:560)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\~2) + (DELAY + (ABSOLUTE + (PORT datab (353:353:353) (439:439:439)) + (PORT datad (531:531:531) (559:559:559)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_end\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (422:422:422)) + (PORT datac (303:303:303) (388:388:388)) + (PORT datad (311:311:311) (395:395:395)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (313:313:313) (343:343:343)) + (PORT datad (533:533:533) (562:562:562)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (550:550:550) (575:575:575)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (433:433:433)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (566:566:566) (593:593:593)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (435:435:435)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (432:432:432)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (428:428:428)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_ack_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (PORT sclr (1036:1036:1036) (1021:1021:1021)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (PORT datab (342:342:342) (425:425:425)) + (PORT datac (301:301:301) (386:386:386)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (466:466:466)) + (PORT datab (570:570:570) (598:598:598)) + (PORT datac (309:309:309) (401:401:401)) + (PORT datad (311:311:311) (395:395:395)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en\~2) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (315:315:315) (342:342:342)) + (PORT datad (266:266:266) (283:283:283)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_en) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (467:467:467)) + (PORT datab (343:343:343) (421:421:421)) + (PORT datad (274:274:274) (298:298:298)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT asdata (768:768:768) (844:844:844)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (380:380:380)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT asdata (994:994:994) (1010:1010:1010)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (432:432:432)) + (PORT datab (341:341:341) (420:420:420)) + (PORT datad (320:320:320) (391:391:391)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (365:365:365)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT asdata (786:786:786) (856:856:856)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|ack_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1861:1861:1861)) + (PORT asdata (772:772:772) (849:849:849)) + (PORT clrn (1883:1883:1883) (1852:1852:1852)) + (PORT ena (1602:1602:1602) (1501:1501:1501)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (438:438:438)) + (PORT datab (344:344:344) (424:424:424)) + (PORT datad (527:527:527) (554:554:554)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal4\~2) + (DELAY + (ABSOLUTE + (PORT datab (893:893:893) (833:833:833)) + (PORT datad (833:833:833) (773:773:773)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (326:326:326)) + (PORT datab (1925:1925:1925) (1777:1777:1777)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_DATA) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\~0) + (DELAY + (ABSOLUTE + (PORT datad (2353:2353:2353) (2234:2234:2234)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~2) + (DELAY + (ABSOLUTE + (PORT datab (388:388:388) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1867:1867:1867)) + (PORT sclr (2890:2890:2890) (3064:3064:3064)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Add3\~1) + (DELAY + (ABSOLUTE + (PORT datab (388:388:388) (480:480:480)) + (PORT datad (332:332:332) (423:423:423)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1867:1867:1867)) + (PORT sclr (2890:2890:2890) (3064:3064:3064)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (628:628:628)) + (PORT datab (388:388:388) (502:502:502)) + (PORT datac (342:342:342) (438:438:438)) + (PORT datad (328:328:328) (418:418:418)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~16) + (DELAY + (ABSOLUTE + (PORT datac (1946:1946:1946) (1865:1865:1865)) + (PORT datad (1111:1111:1111) (1012:1012:1012)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (449:449:449)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1880:1880:1880)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1871:1871:1871)) + (PORT sclr (2715:2715:2715) (2924:2924:2924)) + (PORT ena (1279:1279:1279) (1214:1214:1214)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1063:1063:1063)) + (PORT datab (622:622:622) (629:629:629)) + (PORT datac (574:574:574) (593:593:593)) + (PORT datad (536:536:536) (557:557:557)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|always4\~3) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (509:509:509)) + (PORT datab (641:641:641) (655:655:655)) + (PORT datac (527:527:527) (561:561:561)) + (PORT datad (265:265:265) (283:283:283)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1156:1156:1156)) + (PORT datab (1653:1653:1653) (1531:1531:1531)) + (PORT datad (466:466:466) (440:440:440)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_BUSY) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (4262:4262:4262) (4487:4487:4487)) + (PORT datad (382:382:382) (478:478:478)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~7) + (DELAY + (ABSOLUTE + (PORT datac (304:304:304) (389:389:389)) + (PORT datad (382:382:382) (479:479:479)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~6) + (DELAY + (ABSOLUTE + (PORT datac (306:306:306) (392:392:392)) + (PORT datad (381:381:381) (478:478:478)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~5) + (DELAY + (ABSOLUTE + (PORT datac (304:304:304) (387:387:387)) + (PORT datad (382:382:382) (479:479:479)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (430:430:430)) + (PORT datab (345:345:345) (426:426:426)) + (PORT datac (299:299:299) (380:380:380)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~4) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (437:437:437)) + (PORT datad (382:382:382) (478:478:478)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~3) + (DELAY + (ABSOLUTE + (PORT datab (364:364:364) (441:441:441)) + (PORT datad (382:382:382) (479:479:479)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~2) + (DELAY + (ABSOLUTE + (PORT datac (304:304:304) (389:389:389)) + (PORT datad (382:382:382) (479:479:479)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\~1) + (DELAY + (ABSOLUTE + (PORT datac (304:304:304) (387:387:387)) + (PORT datad (382:382:382) (478:478:478)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|busy_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (603:603:603)) + (PORT datab (343:343:343) (423:423:423)) + (PORT datac (300:300:300) (382:382:382)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT datab (277:277:277) (302:302:302)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1288:1288:1288) (1231:1231:1231)) + (PORT datab (1192:1192:1192) (1083:1083:1083)) + (PORT datad (257:257:257) (287:287:287)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.WR_END) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~2) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (451:451:451)) + (PORT datad (535:535:535) (565:565:565)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~1) + (DELAY + (ABSOLUTE + (PORT datad (536:536:536) (566:566:566)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\~0) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (450:450:450)) + (PORT datab (345:345:345) (428:428:428)) + (PORT datad (537:537:537) (568:568:568)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_end\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (310:310:310) (402:402:402)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1680:1680:1680) (1629:1629:1629)) + (PORT datad (258:258:258) (287:287:287)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cs_n) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1678:1678:1678) (1628:1628:1628)) + (PORT datab (298:298:298) (330:330:330)) + (PORT datad (532:532:532) (561:561:561)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|wr_busy_dly\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (820:820:820) (814:814:814)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|wr_busy_dly) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|wr_busy_fall\~0) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (414:414:414)) + (PORT datad (819:819:819) (814:814:814)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|rd_en) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n\~2) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (843:843:843)) + (PORT datab (315:315:315) (345:345:345)) + (PORT datad (314:314:314) (394:394:394)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cs_n) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_cs_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (868:868:868)) + (PORT datab (374:374:374) (456:456:456)) + (PORT datac (792:792:792) (770:770:770)) + (PORT datad (295:295:295) (364:364:364)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~1) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (459:459:459)) + (PORT datab (359:359:359) (453:453:453)) + (PORT datac (319:319:319) (413:413:413)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (463:463:463)) + (PORT datab (353:353:353) (442:442:442)) + (PORT datac (311:311:311) (400:400:400)) + (PORT datad (313:313:313) (393:393:393)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (878:878:878)) + (PORT datab (585:585:585) (616:616:616)) + (PORT datac (588:588:588) (606:606:606)) + (PORT datad (489:489:489) (460:460:460)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Equal6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (292:292:292) (332:332:332)) + (PORT datab (584:584:584) (615:615:615)) + (PORT datac (586:586:586) (604:604:604)) + (PORT datad (493:493:493) (465:465:465)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~2) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (327:327:327)) + (PORT datab (534:534:534) (498:498:498)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (266:266:266) (283:283:283)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector13\~3) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (522:522:522)) + (PORT datab (760:760:760) (709:709:709)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|cs_n) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1889:1889:1889) (1864:1864:1864)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_cs_n\~1) + (DELAY + (ABSOLUTE + (PORT datab (1224:1224:1224) (1093:1093:1093)) + (PORT datac (293:293:293) (370:370:370)) + (PORT datad (822:822:822) (800:800:800)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|Selector14\~11) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (926:926:926) (876:876:876)) + (PORT datad (868:868:868) (815:815:815)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_init_inst\|mosi) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1877:1877:1877)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1868:1868:1868)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (605:605:605)) + (PORT datab (351:351:351) (440:440:440)) + (PORT datac (319:319:319) (413:413:413)) + (PORT datad (312:312:312) (392:392:392)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|cnt_cmd_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (PORT sclr (1621:1621:1621) (1681:1681:1681)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~1) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (483:483:483)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (320:320:320) (414:414:414)) + (PORT datad (312:312:312) (395:395:395)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi\~2) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (482:482:482)) + (PORT datab (304:304:304) (328:328:328)) + (PORT datac (239:239:239) (266:266:266)) + (PORT datad (968:968:968) (962:962:962)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|mosi) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0) + (DELAY + (ABSOLUTE + (PORT datac (239:239:239) (266:266:266)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (480:480:480)) + (PORT datab (342:342:342) (425:425:425)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (430:430:430)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datab (377:377:377) (465:465:465)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (485:485:485)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datad (265:265:265) (301:301:301)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (480:480:480)) + (PORT datab (381:381:381) (470:470:470)) + (PORT datac (239:239:239) (266:266:266)) + (PORT datad (263:263:263) (298:298:298)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (435:435:435)) + (PORT datab (341:341:341) (423:423:423)) + (PORT datad (303:303:303) (379:379:379)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (600:600:600)) + (PORT datab (341:341:341) (420:420:420)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (606:606:606)) + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (301:301:301) (377:377:377)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (644:644:644)) + (PORT datab (855:855:855) (844:844:844)) + (PORT datac (536:536:536) (560:560:560)) + (PORT datad (527:527:527) (551:551:551)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (518:518:518)) + (PORT datab (636:636:636) (650:650:650)) + (PORT datac (501:501:501) (478:478:478)) + (PORT datad (734:734:734) (661:661:661)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (424:424:424)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT datab (280:280:280) (306:306:306)) + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (351:351:351) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (352:352:352) (435:435:435)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (351:351:351) (440:440:440)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (449:449:449)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (PORT sclr (1131:1131:1131) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (451:451:451)) + (PORT datab (351:351:351) (440:440:440)) + (PORT datac (312:312:312) (402:402:402)) + (PORT datad (312:312:312) (392:392:392)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (727:727:727)) + (PORT datab (635:635:635) (648:648:648)) + (PORT datac (506:506:506) (483:483:483)) + (PORT datad (449:449:449) (422:422:422)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT datab (306:306:306) (344:344:344)) + (PORT datac (331:331:331) (437:437:437)) + (PORT datad (527:527:527) (549:549:549)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_flag) + (DELAY + (ABSOLUTE + (PORT clk (1864:1864:1864) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1896:1896:1896) (1872:1872:1872)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_flag) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (1440:1440:1440) (1427:1427:1427)) + (PORT clrn (1883:1883:1883) (1862:1862:1862)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT asdata (1319:1319:1319) (1273:1273:1273)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1475:1475:1475) (1423:1423:1423)) + (PORT datab (1359:1359:1359) (1341:1341:1341)) + (PORT datac (864:864:864) (825:825:825)) + (PORT datad (1466:1466:1466) (1446:1446:1446)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a2) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (365:365:365)) + (PORT datad (349:349:349) (433:433:433)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a3) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1475:1475:1475) (1423:1423:1423)) + (PORT datab (1357:1357:1357) (1339:1339:1339)) + (PORT datac (864:864:864) (825:825:825)) + (PORT datad (1465:1465:1465) (1444:1444:1444)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (485:485:485)) + (PORT datab (591:591:591) (614:614:614)) + (PORT datad (465:465:465) (440:440:440)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a4) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (463:463:463)) + (PORT datab (387:387:387) (479:479:479)) + (PORT datac (279:279:279) (316:316:316)) + (PORT datad (348:348:348) (431:431:431)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (481:481:481)) + (PORT datad (255:255:255) (279:279:279)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a6) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|cntr_cout\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (477:477:477)) + (PORT datac (346:346:346) (443:443:443)) + (PORT datad (254:254:254) (279:279:279)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (485:485:485)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a9) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1326:1326:1326) (1309:1309:1309)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1681:1681:1681) (1604:1604:1604)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (287:287:287) (322:322:322)) + (PORT datad (534:534:534) (571:571:571)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (539:539:539) (558:558:558)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1319:1319:1319) (1260:1260:1260)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1218:1218:1218)) + (PORT datab (984:984:984) (967:967:967)) + (PORT datad (318:318:318) (396:396:396)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (569:569:569) (587:587:587)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1309:1309:1309) (1255:1255:1255)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (545:545:545) (568:568:568)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (348:348:348)) + (PORT datab (379:379:379) (465:465:465)) + (PORT datad (548:548:548) (559:559:559)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (550:550:550) (573:573:573)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (1365:1365:1365) (1346:1346:1346)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (792:792:792) (771:771:771)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT asdata (761:761:761) (830:830:830)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT asdata (812:812:812) (900:900:900)) + (PORT ena (1669:1669:1669) (1588:1588:1588)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (994:994:994)) + (PORT datab (367:367:367) (447:447:447)) + (PORT datad (973:973:973) (975:975:975)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT asdata (810:810:810) (898:898:898)) + (PORT ena (1669:1669:1669) (1588:1588:1588)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT asdata (1023:1023:1023) (1040:1040:1040)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (858:858:858) (861:861:861)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (507:507:507) (532:532:532)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (975:975:975) (990:990:990)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (597:597:597) (608:608:608)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (1715:1715:1715) (1669:1669:1669)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (670:670:670)) + (PORT datab (1009:1009:1009) (992:992:992)) + (PORT datad (301:301:301) (378:378:378)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (859:859:859) (797:797:797)) + (PORT datac (442:442:442) (422:422:422)) + (PORT datad (809:809:809) (756:756:756)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (1457:1457:1457) (1407:1407:1407)) + (PORT datac (1269:1269:1269) (1186:1186:1186)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (625:625:625)) + (PORT datab (388:388:388) (481:481:481)) + (PORT datad (889:889:889) (847:847:847)) + (IOPATH dataa combout (405:405:405) (407:407:407)) + (IOPATH datab combout (410:410:410) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a1) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1464:1464:1464) (1423:1423:1423)) + (PORT datab (388:388:388) (481:481:481)) + (PORT datac (346:346:346) (425:425:425)) + (PORT datad (1306:1306:1306) (1274:1274:1274)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1681:1681:1681) (1604:1604:1604)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8\~0) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (480:480:480)) + (PORT datad (246:246:246) (267:267:267)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a8) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[8\]) + (DELAY + (ABSOLUTE + (PORT datab (1385:1385:1385) (1356:1356:1356)) + (PORT datad (1284:1284:1284) (1241:1241:1241)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1681:1681:1681) (1604:1604:1604)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (461:461:461)) + (PORT datab (385:385:385) (478:478:478)) + (PORT datac (282:282:282) (320:320:320)) + (PORT datad (348:348:348) (432:432:432)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (240:240:240) (259:259:259)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a5) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (481:481:481)) + (PORT datab (387:387:387) (481:481:481)) + (PORT datac (346:346:346) (443:443:443)) + (PORT datad (578:578:578) (612:612:612)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1669:1669:1669) (1588:1588:1588)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (413:413:413)) + (PORT datac (296:296:296) (375:375:375)) + (PORT datad (1311:1311:1311) (1267:1267:1267)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity6) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1681:1681:1681) (1604:1604:1604)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a0) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1681:1681:1681) (1604:1604:1604)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (388:388:388) (481:481:481)) + (IOPATH datab combout (494:494:494) (496:496:496)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1681:1681:1681) (1604:1604:1604)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1184:1184:1184) (1141:1141:1141)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (971:971:971) (997:997:997)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (1446:1446:1446) (1416:1416:1416)) + (PORT ena (1747:1747:1747) (1669:1669:1669)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe17a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (803:803:803) (883:883:883)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (542:542:542) (562:562:562)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe16\|dffe18a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (973:973:973)) + (PORT datab (936:936:936) (925:925:925)) + (PORT datad (295:295:295) (364:364:364)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (326:326:326)) + (PORT datab (334:334:334) (410:410:410)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_comb_bita0\~0) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (287:287:287) (325:325:325)) + (PORT datab (898:898:898) (822:822:822)) + (PORT datad (246:246:246) (268:268:268)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (883:883:883)) + (PORT datab (892:892:892) (866:866:866)) + (PORT datac (752:752:752) (678:678:678)) + (PORT datad (506:506:506) (532:532:532)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (620:620:620)) + (PORT datab (377:377:377) (467:467:467)) + (PORT datac (552:552:552) (579:579:579)) + (PORT datad (263:263:263) (295:295:295)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\]\~3) + (DELAY + (ABSOLUTE + (PORT datab (389:389:389) (486:486:486)) + (PORT datad (254:254:254) (279:279:279)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (620:620:620)) + (PORT datab (387:387:387) (484:484:484)) + (PORT datac (355:355:355) (439:439:439)) + (PORT datad (528:528:528) (565:565:565)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a1) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1595:1595:1595) (1481:1481:1481)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (886:886:886)) + (PORT datab (380:380:380) (470:470:470)) + (PORT datac (855:855:855) (834:834:834)) + (PORT datad (337:337:337) (421:421:421)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity9a0) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1595:1595:1595) (1481:1481:1481)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (424:424:424)) + (PORT datab (337:337:337) (414:414:414)) + (PORT datac (297:297:297) (375:375:375)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity8) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1595:1595:1595) (1481:1481:1481)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datad (860:860:860) (862:862:862)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1377:1377:1377) (1332:1332:1332)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (448:448:448)) + (PORT datab (368:368:368) (450:450:450)) + (PORT datac (532:532:532) (516:516:516)) + (PORT datad (859:859:859) (861:861:861)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\]\~7) + (DELAY + (ABSOLUTE + (PORT datad (711:711:711) (642:642:642)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (381:381:381) (467:467:467)) + (PORT datad (263:263:263) (295:295:295)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (620:620:620)) + (PORT datab (378:378:378) (468:468:468)) + (PORT datac (552:552:552) (579:579:579)) + (PORT datad (264:264:264) (296:296:296)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\]\~6) + (DELAY + (ABSOLUTE + (PORT datad (237:237:237) (256:256:256)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (636:636:636)) + (PORT datab (387:387:387) (483:483:483)) + (PORT datad (256:256:256) (281:281:281)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT datab (387:387:387) (483:483:483)) + (PORT datac (351:351:351) (434:434:434)) + (PORT datad (254:254:254) (279:279:279)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (575:575:575) (615:615:615)) + (PORT datad (245:245:245) (270:270:270)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT asdata (1051:1051:1051) (1058:1058:1058)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (1656:1656:1656) (1603:1603:1603)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (764:764:764) (833:833:833)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (759:759:759) (828:828:828)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datac (314:314:314) (402:402:402)) + (PORT datad (324:324:324) (404:404:404)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (477:477:477)) + (PORT datab (392:392:392) (486:486:486)) + (PORT datad (254:254:254) (279:279:279)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter5a7) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (1474:1474:1474) (1459:1459:1459)) + (PORT ena (1575:1575:1575) (1483:1483:1483)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1286:1286:1286) (1243:1243:1243)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1681:1681:1681) (1604:1604:1604)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (1330:1330:1330) (1283:1283:1283)) + (PORT datac (356:356:356) (441:441:441)) + (PORT datad (1211:1211:1211) (1150:1150:1150)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (PORT datab (341:341:341) (420:420:420)) + (PORT datac (307:307:307) (394:394:394)) + (PORT datad (319:319:319) (398:398:398)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1429:1429:1429) (1386:1386:1386)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1747:1747:1747) (1669:1669:1669)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT dataa (1328:1328:1328) (1280:1280:1280)) + (PORT datab (1249:1249:1249) (1190:1190:1190)) + (PORT datac (353:353:353) (438:438:438)) + (PORT datad (946:946:946) (938:938:938)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT datac (330:330:330) (413:413:413)) + (PORT datad (829:829:829) (787:787:787)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (1457:1457:1457) (1419:1419:1419)) + (PORT datac (332:332:332) (416:416:416)) + (PORT datad (826:826:826) (784:784:784)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (1848:1848:1848) (1802:1802:1802)) + (PORT ena (1747:1747:1747) (1669:1669:1669)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT dataa (1456:1456:1456) (1418:1418:1418)) + (PORT datab (1660:1660:1660) (1584:1584:1584)) + (PORT datac (328:328:328) (411:411:411)) + (PORT datad (827:827:827) (785:785:785)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (543:543:543) (569:569:569)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (1321:1321:1321) (1319:1319:1319)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (798:798:798) (777:777:777)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (365:365:365)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT asdata (1055:1055:1055) (1064:1064:1064)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT asdata (1680:1680:1680) (1608:1608:1608)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (846:846:846) (809:809:809)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT asdata (762:762:762) (832:832:832)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (PORT datab (550:550:550) (578:578:578)) + (PORT datac (327:327:327) (411:411:411)) + (PORT datad (1572:1572:1572) (1421:1421:1421)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT datac (900:900:900) (854:854:854)) + (PORT datad (734:734:734) (669:669:669)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT asdata (1772:1772:1772) (1735:1735:1735)) + (PORT ena (1747:1747:1747) (1669:1669:1669)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (297:297:297) (335:335:335)) + (PORT datac (339:339:339) (428:428:428)) + (PORT datad (553:553:553) (586:586:586)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_brp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (566:566:566)) + (PORT datab (370:370:370) (454:454:454)) + (PORT datad (861:861:861) (863:863:863)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (833:833:833) (808:808:808)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1585:1585:1585) (1456:1456:1456)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1179:1179:1179) (1120:1120:1120)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT asdata (1284:1284:1284) (1237:1237:1237)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe15a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (826:826:826)) + (PORT datab (354:354:354) (441:441:441)) + (PORT datac (358:358:358) (443:443:443)) + (PORT datad (272:272:272) (292:292:292)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_bwp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (826:826:826)) + (PORT datab (1206:1206:1206) (1153:1153:1153)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (904:904:904)) + (PORT datab (602:602:602) (609:609:609)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (593:593:593)) + (PORT datab (955:955:955) (929:929:929)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (612:612:612) (620:620:620)) + (PORT datab (883:883:883) (885:885:885)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (419:419:419)) + (PORT datab (532:532:532) (559:559:559)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_wr_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|op_1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (421:421:421)) + (PORT datad (528:528:528) (549:549:549)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|comb\~1) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (478:478:478)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|comb\~0) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (1983:1983:1983) (1881:1881:1881)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|comb\~2) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (235:235:235) (261:261:261)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (2015:2015:2015) (1838:1838:1838)) + (PORT datab (370:370:370) (452:452:452)) + (PORT datac (1631:1631:1631) (1576:1576:1576)) + (PORT datad (826:826:826) (791:791:791)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Selector1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (327:327:327)) + (PORT datab (894:894:894) (834:834:834)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (836:836:836) (776:776:776)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|state\.SEND_CMD24) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1850:1850:1850)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (450:450:450)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (455:455:455)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (446:446:446)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (464:464:464)) + (PORT datab (359:359:359) (455:455:455)) + (PORT datac (318:318:318) (412:412:412)) + (PORT datad (321:321:321) (404:404:404)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|cnt_cmd_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (PORT sclr (2551:2551:2551) (2696:2696:2696)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~2) + (DELAY + (ABSOLUTE + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (319:319:319) (415:415:415)) + (PORT datad (320:320:320) (407:407:407)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT datab (357:357:357) (452:452:452)) + (PORT datac (317:317:317) (411:411:411)) + (PORT datad (318:318:318) (401:401:401)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~3) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (360:360:360) (449:449:449)) + (PORT datac (319:319:319) (415:415:415)) + (PORT datad (248:248:248) (271:271:271)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~4) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (490:490:490) (475:475:475)) + (PORT datac (1968:1968:1968) (1887:1887:1887)) + (PORT datad (783:783:783) (726:726:726)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~5) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (904:904:904)) + (PORT datab (2008:2008:2008) (1923:1923:1923)) + (PORT datac (1946:1946:1946) (1865:1865:1865)) + (PORT datad (539:539:539) (560:560:560)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi\~8) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (2010:2010:2010) (1925:1925:1925)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_write_inst\|mosi) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_mosi\~0) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (868:868:868)) + (PORT datab (941:941:941) (925:925:925)) + (PORT datac (1707:1707:1707) (1633:1633:1633)) + (PORT datad (334:334:334) (414:414:414)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_mosi\~1) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (846:846:846)) + (PORT datac (895:895:895) (881:881:881)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (928:928:928)) + (PORT datab (341:341:341) (420:420:420)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (PORT datab (343:343:343) (425:425:425)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (301:301:301) (376:376:376)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (888:888:888)) + (PORT datab (865:865:865) (770:770:770)) + (PORT datac (903:903:903) (887:887:887)) + (PORT datad (931:931:931) (902:902:902)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (442:442:442)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (453:453:453)) + (PORT datab (352:352:352) (442:442:442)) + (PORT datac (312:312:312) (402:402:402)) + (PORT datad (313:313:313) (394:394:394)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (944:944:944)) + (PORT datac (911:911:911) (901:901:901)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (925:925:925)) + (PORT datab (289:289:289) (318:318:318)) + (PORT datac (813:813:813) (755:755:755)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (433:433:433)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (350:350:350) (440:440:440)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (449:449:449)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1497:1497:1497) (1499:1499:1499)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (453:453:453)) + (PORT datab (352:352:352) (441:441:441)) + (PORT datac (312:312:312) (402:402:402)) + (PORT datad (313:313:313) (393:393:393)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (945:945:945)) + (PORT datab (965:965:965) (941:941:941)) + (PORT datac (1124:1124:1124) (990:990:990)) + (PORT datad (248:248:248) (275:275:275)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1146:1146:1146)) + (PORT datad (1187:1187:1187) (1123:1123:1123)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (327:327:327)) + (PORT datab (1249:1249:1249) (1173:1173:1173)) + (PORT datac (347:347:347) (466:466:466)) + (PORT datad (310:310:310) (393:393:393)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1147:1147:1147)) + (PORT datab (1252:1252:1252) (1177:1177:1177)) + (PORT datad (291:291:291) (326:326:326)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (377:377:377)) + (PORT datab (391:391:391) (507:507:507)) + (PORT datad (256:256:256) (289:289:289)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (602:602:602)) + (PORT datab (353:353:353) (439:439:439)) + (PORT datac (350:350:350) (470:470:470)) + (PORT datad (346:346:346) (446:446:446)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (377:377:377)) + (PORT datab (297:297:297) (332:332:332)) + (PORT datad (240:240:240) (258:258:258)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (648:648:648)) + (PORT datac (854:854:854) (833:833:833)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|rd_busy_dly) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1865:1865:1865)) + (PORT asdata (1677:1677:1677) (1619:1619:1619)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (418:418:418)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (421:421:421)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\]\~16) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (420:420:420)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (435:435:435)) + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (302:302:302) (386:386:386)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_num\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1855:1855:1855)) + (PORT sclr (1580:1580:1580) (1648:1648:1648)) + (PORT ena (1638:1638:1638) (1553:1553:1553)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (302:302:302) (386:386:386)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|always3\~3) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (472:472:472)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (839:839:839) (785:785:785)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|send_data_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1317:1317:1317) (1271:1271:1271)) + (PORT datab (337:337:337) (414:414:414)) + (PORT datad (1043:1043:1043) (938:938:938)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|send_data_en) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (642:642:642)) + (PORT datab (578:578:578) (602:602:602)) + (PORT datac (527:527:527) (561:561:561)) + (PORT datad (559:559:559) (579:579:579)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (324:324:324)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (320:320:320) (398:398:398)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (638:638:638)) + (PORT datab (575:575:575) (599:599:599)) + (PORT datac (524:524:524) (557:557:557)) + (PORT datad (556:556:556) (575:575:575)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\]\~29) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\]\~37) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\]\~39) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\]\~41) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]\~43) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\]\~45) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\]\~47) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (448:448:448)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (600:600:600)) + (PORT datab (559:559:559) (585:585:585)) + (PORT datac (533:533:533) (549:549:549)) + (PORT datad (552:552:552) (570:570:570)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|cnt_wait\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1855:1855:1855)) + (PORT sclr (1121:1121:1121) (1143:1143:1143)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (819:819:819)) + (PORT datab (617:617:617) (622:622:622)) + (PORT datac (787:787:787) (765:765:765)) + (PORT datad (522:522:522) (541:541:541)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1524:1524:1524) (1455:1455:1455)) + (PORT datab (558:558:558) (583:583:583)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|Equal2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (648:648:648)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (854:854:854) (833:833:833)) + (PORT datad (245:245:245) (269:269:269)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|rd_fifo_rd_en) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (379:379:379) (466:466:466)) + (PORT datac (348:348:348) (447:447:447)) + (PORT datad (254:254:254) (278:278:278)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\]\~8) + (DELAY + (ABSOLUTE + (PORT datab (377:377:377) (467:467:467)) + (PORT datad (245:245:245) (266:266:266)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (881:881:881) (867:867:867)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1347:1347:1347) (1288:1288:1288)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (886:886:886)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (916:916:916) (915:915:915)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1140:1140:1140) (1130:1130:1130)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT asdata (1322:1322:1322) (1307:1307:1307)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT asdata (760:760:760) (830:830:830)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT asdata (1407:1407:1407) (1398:1398:1398)) + (PORT ena (1387:1387:1387) (1333:1333:1333)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (865:865:865) (853:853:853)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1265:1265:1265) (1225:1225:1225)) + (PORT datab (361:361:361) (438:438:438)) + (PORT datad (295:295:295) (365:365:365)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (628:628:628)) + (PORT datab (359:359:359) (453:453:453)) + (PORT datac (339:339:339) (429:429:429)) + (PORT datad (318:318:318) (405:405:405)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (343:343:343)) + (PORT datab (472:472:472) (455:455:455)) + (PORT datac (511:511:511) (483:483:483)) + (PORT datad (573:573:573) (594:594:594)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1367:1367:1367) (1362:1362:1362)) + (PORT datab (368:368:368) (464:464:464)) + (PORT datac (484:484:484) (459:459:459)) + (PORT datad (275:275:275) (297:297:297)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_en) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT asdata (1441:1441:1441) (1423:1423:1423)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT asdata (762:762:762) (831:831:831)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (858:858:858) (857:857:857)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1875:1875:1875) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1676:1676:1676) (1565:1565:1565)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1875:1875:1875) (1890:1890:1890)) + (PORT asdata (789:789:789) (859:859:859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datac (549:549:549) (576:576:576)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (626:626:626)) + (PORT datab (631:631:631) (635:635:635)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (931:931:931) (925:925:925)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT asdata (1884:1884:1884) (1779:1779:1779)) + (PORT ena (1347:1347:1347) (1288:1288:1288)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (392:392:392)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT asdata (1410:1410:1410) (1388:1388:1388)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (462:462:462)) + (PORT datab (377:377:377) (465:465:465)) + (PORT datac (500:500:500) (480:480:480)) + (PORT datad (338:338:338) (415:415:415)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1310:1310:1310) (1232:1232:1232)) + (PORT datab (983:983:983) (947:947:947)) + (PORT datad (282:282:282) (305:305:305)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (598:598:598) (609:609:609)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1134:1134:1134) (1128:1128:1128)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (842:842:842) (825:825:825)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1875:1875:1875) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (939:939:939) (923:923:923)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (947:947:947) (937:937:937)) + (PORT datab (549:549:549) (585:585:585)) + (PORT datad (294:294:294) (363:363:363)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (810:810:810) (811:811:811)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1588:1588:1588) (1477:1477:1477)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT asdata (786:786:786) (856:856:856)) + (PORT ena (1387:1387:1387) (1333:1333:1333)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (323:323:323) (394:394:394)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT asdata (760:760:760) (829:829:829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (334:334:334) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1387:1387:1387) (1333:1333:1333)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (321:321:321) (391:391:391)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe17a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (594:594:594)) + (PORT datab (887:887:887) (893:893:893)) + (PORT datad (294:294:294) (364:364:364)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrfull_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (310:310:310)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (236:236:236) (263:263:263)) + (PORT datad (834:834:834) (764:764:764)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT datab (286:286:286) (318:318:318)) + (PORT datac (1848:1848:1848) (1742:1742:1742)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a0) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1588:1588:1588) (1477:1477:1477)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (886:886:886)) + (PORT datab (379:379:379) (470:470:470)) + (PORT datad (781:781:781) (719:719:719)) + (IOPATH dataa combout (405:405:405) (407:407:407)) + (IOPATH datab combout (410:410:410) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a1) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (954:954:954)) + (PORT datab (565:565:565) (600:600:600)) + (PORT datac (300:300:300) (330:330:330)) + (PORT datad (909:909:909) (908:908:908)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (945:945:945)) + (PORT datab (856:856:856) (861:861:861)) + (PORT datad (792:792:792) (723:723:723)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a4) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (856:856:856) (862:862:862)) + (PORT datad (792:792:792) (723:723:723)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a3) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|cntr_cout\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (826:826:826)) + (PORT datab (956:956:956) (958:958:958)) + (PORT datac (828:828:828) (828:828:828)) + (PORT datad (459:459:459) (433:433:433)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6\~0) + (DELAY + (ABSOLUTE + (PORT datab (990:990:990) (971:971:971)) + (PORT datad (252:252:252) (276:276:276)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a6) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (927:927:927)) + (PORT datab (363:363:363) (456:456:456)) + (PORT datac (324:324:324) (420:420:420)) + (PORT datad (933:933:933) (927:927:927)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT datab (993:993:993) (974:974:974)) + (PORT datac (322:322:322) (418:418:418)) + (PORT datad (256:256:256) (281:281:281)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9\~0) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (454:454:454)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a9) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT datab (344:344:344) (424:424:424)) + (PORT datac (515:515:515) (545:545:545)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (944:944:944)) + (PORT datab (380:380:380) (470:470:470)) + (PORT datac (324:324:324) (403:403:403)) + (PORT datad (817:817:817) (819:819:819)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1588:1588:1588) (1477:1477:1477)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (413:413:413)) + (PORT datac (297:297:297) (375:375:375)) + (PORT datad (863:863:863) (858:858:858)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|parity9) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1893:1893:1893) (1790:1790:1790)) + (PORT datab (288:288:288) (320:320:320)) + (PORT datac (523:523:523) (561:561:561)) + (PORT datad (248:248:248) (270:270:270)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (954:954:954)) + (PORT datab (973:973:973) (961:961:961)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a2) + (DELAY + (ABSOLUTE + (PORT clk (1861:1861:1861) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (461:461:461)) + (PORT datab (852:852:852) (856:856:856)) + (PORT datac (791:791:791) (707:707:707)) + (PORT datad (874:874:874) (886:886:886)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (237:237:237) (256:256:256)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a5) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (459:459:459)) + (PORT datab (991:991:991) (971:971:971)) + (PORT datad (253:253:253) (277:277:277)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a7) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8\~0) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (454:454:454)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g1p\|counter8a8) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT asdata (982:982:982) (1003:1003:1003)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT asdata (787:787:787) (856:856:856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT asdata (1238:1238:1238) (1206:1206:1206)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT asdata (760:760:760) (829:829:829)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (305:305:305) (382:382:382)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (802:802:802) (780:780:780)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1875:1875:1875) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (299:299:299) (369:369:369)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1875:1875:1875) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (299:299:299) (369:369:369)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1875:1875:1875) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (825:825:825)) + (PORT datab (613:613:613) (617:617:617)) + (PORT datad (791:791:791) (760:760:760)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT asdata (1332:1332:1332) (1310:1310:1310)) + (PORT ena (1347:1347:1347) (1288:1288:1288)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (319:319:319) (410:410:410)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (831:831:831) (807:807:807)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (365:365:365)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT asdata (761:761:761) (831:831:831)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1873:1873:1873)) + (PORT asdata (787:787:787) (873:873:873)) + (PORT ena (1285:1285:1285) (1213:1213:1213)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (831:831:831) (800:800:800)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT asdata (761:761:761) (830:830:830)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (431:431:431)) + (PORT datab (575:575:575) (591:591:591)) + (PORT datad (294:294:294) (363:363:363)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (537:537:537) (566:566:566)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (964:964:964) (958:958:958)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1876:1876:1876)) + (PORT asdata (763:763:763) (832:832:832)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (874:874:874) (885:885:885)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1588:1588:1588) (1477:1477:1477)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1876:1876:1876)) + (PORT asdata (1597:1597:1597) (1523:1523:1523)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (365:365:365)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (295:295:295) (365:365:365)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (883:883:883)) + (PORT datab (1184:1184:1184) (1107:1107:1107)) + (PORT datad (295:295:295) (365:365:365)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (448:448:448) (424:424:424)) + (PORT datad (770:770:770) (705:705:705)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (1020:1020:1020)) + (PORT datab (1834:1834:1834) (1684:1684:1684)) + (PORT datac (243:243:243) (274:274:274)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1419:1419:1419) (1410:1410:1410)) + (PORT datab (991:991:991) (977:977:977)) + (PORT datac (1194:1194:1194) (1158:1158:1158)) + (PORT datad (827:827:827) (769:769:769)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT datad (240:240:240) (258:258:258)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (833:833:833)) + (PORT datad (329:329:329) (402:402:402)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1309:1309:1309) (1230:1230:1230)) + (PORT datab (982:982:982) (946:946:946)) + (PORT datac (359:359:359) (447:447:447)) + (PORT datad (282:282:282) (305:305:305)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (492:492:492)) + (PORT datad (255:255:255) (280:280:280)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (498:498:498)) + (PORT datab (381:381:381) (468:468:468)) + (PORT datad (252:252:252) (277:277:277)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (380:380:380) (471:471:471)) + (PORT datad (246:246:246) (268:268:268)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_b\[9\]) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (448:448:448)) + (PORT datad (320:320:320) (391:391:391)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a2) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1293:1293:1293) (1242:1242:1242)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (494:494:494)) + (PORT datab (379:379:379) (469:469:469)) + (PORT datac (363:363:363) (451:451:451)) + (PORT datad (339:339:339) (423:423:423)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a1) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1293:1293:1293) (1242:1242:1242)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (462:462:462)) + (PORT datab (980:980:980) (943:943:943)) + (PORT datac (340:340:340) (433:433:433)) + (PORT datad (1242:1242:1242) (1176:1176:1176)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|sub_parity6a0) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1293:1293:1293) (1242:1242:1242)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (413:413:413)) + (PORT datac (296:296:296) (374:374:374)) + (PORT datad (498:498:498) (525:525:525)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|parity5) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1293:1293:1293) (1242:1242:1242)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datad (340:340:340) (417:417:417)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1293:1293:1293) (1242:1242:1242)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (533:533:533)) + (PORT datab (382:382:382) (471:471:471)) + (PORT datad (338:338:338) (415:415:415)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g1p\|counter7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1888:1888:1888)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT asdata (1840:1840:1840) (1817:1817:1817)) + (PORT ena (1387:1387:1387) (1333:1333:1333)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (379:379:379) (469:469:469)) + (IOPATH datab combout (494:494:494) (496:496:496)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1588:1588:1588) (1477:1477:1477)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (392:392:392)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT asdata (761:761:761) (831:831:831)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT asdata (1290:1290:1290) (1255:1255:1255)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT asdata (1280:1280:1280) (1245:1245:1245)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe13a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT asdata (972:972:972) (990:990:990)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rs_dgwp\|dffpipe12\|dffe14a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1873:1873:1873) (1889:1889:1889)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|rdempty_eq_comp\|aneb_result_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (869:869:869)) + (PORT datab (934:934:934) (890:890:890)) + (PORT datad (293:293:293) (362:362:362)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT datab (1832:1832:1832) (1682:1682:1682)) + (PORT datac (247:247:247) (278:278:278)) + (PORT datad (245:245:245) (267:267:267)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~12) + (DELAY + (ABSOLUTE + (PORT dataa (4197:4197:4197) (4406:4406:4406)) + (PORT datab (1234:1234:1234) (1141:1141:1141)) + (PORT datac (1266:1266:1266) (1240:1240:1240)) + (PORT datad (882:882:882) (857:857:857)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~13) + (DELAY + (ABSOLUTE + (PORT datac (1338:1338:1338) (1323:1323:1323)) + (PORT datad (928:928:928) (924:924:924)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1364:1364:1364) (1359:1359:1359)) + (PORT datab (364:364:364) (459:459:459)) + (PORT datac (484:484:484) (458:458:458)) + (PORT datad (275:275:275) (297:297:297)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~14) + (DELAY + (ABSOLUTE + (PORT dataa (1313:1313:1313) (1290:1290:1290)) + (PORT datab (926:926:926) (902:902:902)) + (PORT datac (1179:1179:1179) (1102:1102:1102)) + (PORT datad (322:322:322) (392:392:392)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~10) + (DELAY + (ABSOLUTE + (PORT dataa (1311:1311:1311) (1288:1288:1288)) + (PORT datab (925:925:925) (900:900:900)) + (PORT datac (1182:1182:1182) (1106:1106:1106)) + (PORT datad (322:322:322) (392:392:392)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1310:1310:1310) (1286:1286:1286)) + (PORT datab (924:924:924) (899:899:899)) + (PORT datac (1184:1184:1184) (1108:1108:1108)) + (PORT datad (323:323:323) (393:393:393)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1310:1310:1310) (1286:1286:1286)) + (PORT datab (924:924:924) (899:899:899)) + (PORT datac (1183:1183:1183) (1108:1108:1108)) + (PORT datad (322:322:322) (393:393:393)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1309:1309:1309) (1285:1285:1285)) + (PORT datab (923:923:923) (898:898:898)) + (PORT datac (1185:1185:1185) (1109:1109:1109)) + (PORT datad (323:323:323) (393:393:393)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1274:1274:1274) (1194:1194:1194)) + (PORT datab (1308:1308:1308) (1219:1219:1219)) + (PORT datac (1626:1626:1626) (1583:1583:1583)) + (PORT datad (911:911:911) (907:907:907)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1274:1274:1274) (1194:1194:1194)) + (PORT datab (1307:1307:1307) (1219:1219:1219)) + (PORT datac (1625:1625:1625) (1582:1582:1582)) + (PORT datad (304:304:304) (377:377:377)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1676:1676:1676) (1642:1642:1642)) + (PORT datab (1308:1308:1308) (1219:1219:1219)) + (PORT datac (304:304:304) (389:389:389)) + (PORT datad (1202:1202:1202) (1134:1134:1134)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~14) + (DELAY + (ABSOLUTE + (PORT datac (1635:1635:1635) (1594:1594:1594)) + (PORT datad (306:306:306) (380:380:380)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1940:1940:1940) (1799:1799:1799)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (331:331:331) (409:409:409)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1588:1588:1588) (1477:1477:1477)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|ram_address_a\[8\]) + (DELAY + (ABSOLUTE + (PORT datad (320:320:320) (390:390:390)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~0) + (DELAY + (ABSOLUTE + (PORT datad (239:239:239) (258:258:258)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0) + (DELAY + (ABSOLUTE + (PORT clk (1875:1875:1875) (1890:1890:1890)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1676:1676:1676) (1565:1565:1565)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_rw_ctrl_inst\|fifo_rd_data_inst\|dcfifo_mixed_widths_component\|auto_generated\|cntr_b\|counter_reg_bit0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~15) + (DELAY + (ABSOLUTE + (PORT datab (986:986:986) (971:971:971)) + (PORT datac (1344:1344:1344) (1330:1330:1330)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~11) + (DELAY + (ABSOLUTE + (PORT datac (1339:1339:1339) (1324:1324:1324)) + (PORT datad (887:887:887) (885:885:885)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~7) + (DELAY + (ABSOLUTE + (PORT datac (1352:1352:1352) (1339:1339:1339)) + (PORT datad (931:931:931) (921:921:921)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~5) + (DELAY + (ABSOLUTE + (PORT datac (1350:1350:1350) (1337:1337:1337)) + (PORT datad (944:944:944) (934:934:934)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~3) + (DELAY + (ABSOLUTE + (PORT datac (1627:1627:1627) (1584:1584:1584)) + (PORT datad (911:911:911) (908:908:908)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1940:1940:1940) (1799:1799:1799)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~9) + (DELAY + (ABSOLUTE + (PORT datac (1633:1633:1633) (1592:1592:1592)) + (PORT datad (305:305:305) (378:378:378)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1940:1940:1940) (1799:1799:1799)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (435:435:435)) + (PORT datac (1624:1624:1624) (1581:1581:1581)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1940:1940:1940) (1799:1799:1799)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~15) + (DELAY + (ABSOLUTE + (PORT dataa (1272:1272:1272) (1191:1191:1191)) + (PORT datab (1309:1309:1309) (1221:1221:1221)) + (PORT datac (1632:1632:1632) (1590:1590:1590)) + (PORT datad (305:305:305) (379:379:379)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~16) + (DELAY + (ABSOLUTE + (PORT datac (1622:1622:1622) (1578:1578:1578)) + (PORT datad (307:307:307) (381:381:381)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1940:1940:1940) (1799:1799:1799)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (438:438:438)) + (PORT datac (1632:1632:1632) (1591:1591:1591)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1940:1940:1940) (1799:1799:1799)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (440:440:440)) + (PORT datac (1634:1634:1634) (1593:1593:1593)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1940:1940:1940) (1799:1799:1799)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~6) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (907:907:907)) + (PORT datac (1349:1349:1349) (1336:1336:1336)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~3) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (911:911:911)) + (PORT datab (1178:1178:1178) (1103:1103:1103)) + (PORT datac (1342:1342:1342) (1328:1328:1328)) + (PORT datad (860:860:860) (819:819:819)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~4) + (DELAY + (ABSOLUTE + (PORT datac (1348:1348:1348) (1334:1334:1334)) + (PORT datad (305:305:305) (378:378:378)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~10) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (440:440:440)) + (PORT datac (1351:1351:1351) (1338:1338:1338)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\~1) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (438:438:438)) + (PORT datab (1177:1177:1177) (1103:1103:1103)) + (PORT datac (1343:1343:1343) (1329:1329:1329)) + (PORT datad (860:860:860) (819:819:819)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data_reg\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\~2) + (DELAY + (ABSOLUTE + (PORT datac (1341:1341:1341) (1326:1326:1326)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sd_ctrl_inst\|sd_read_inst\|rd_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT ena (1620:1620:1620) (1534:1534:1534)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (328:328:328)) + (PORT datab (353:353:353) (440:440:440)) + (PORT datac (351:351:351) (471:471:471)) + (PORT datad (842:842:842) (786:786:786)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (1251:1251:1251) (1176:1176:1176)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|tx) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/stp/clk_gen.qip b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/stp/clk_gen.qip new file mode 100644 index 0000000..e69de29 diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/stp/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/stp/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..bc30615 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/stp/greybox_tmp/cbx_args.txt @@ -0,0 +1,66 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=1 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=1 +CLK0_PHASE_SHIFT=0 +CLK1_DIVIDE_BY=1 +CLK1_DUTY_CYCLE=50 +CLK1_MULTIPLY_BY=1 +CLK1_PHASE_SHIFT=6667 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=20000 +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_USED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_USED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_USED +PORT_clk2=PORT_UNUSED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +SELF_RESET_ON_LOSS_LOCK=OFF +WIDTH_CLOCK=5 +DEVICE_FAMILY="Cyclone IV E" +CBX_AUTO_BLACKBOX=ALL +areset +inclk +inclk +clk +clk +locked diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qpf b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qpf new file mode 100644 index 0000000..f5b3989 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.0 Build 156 04/24/2013 SJ Full Version +# Date created = 16:24:33 September 05, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "16:24:33 September 05, 2019" + +# Revisions + +PROJECT_REVISION = "uart_sd" diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qsf b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qsf new file mode 100644 index 0000000..f0d56ba --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qsf @@ -0,0 +1,85 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.0 Build 156 04/24/2013 SJ Full Version +# Date created = 16:24:33 September 05, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# uart_sd_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE15F23C8 +set_global_assignment -name TOP_LEVEL_ENTITY uart_sd +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:24:33 SEPTEMBER 05, 2019" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_location_assignment PIN_F8 -to sd_clk +set_location_assignment PIN_E7 -to sd_cs_n +set_location_assignment PIN_F7 -to sd_mosi +set_location_assignment PIN_E9 -to sd_miso + +set_location_assignment PIN_T22 -to sys_clk +set_location_assignment PIN_U20 -to sys_rst_n +set_location_assignment PIN_V1 -to rx +set_location_assignment PIN_U1 -to tx +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE stp/stp1.stp +set_global_assignment -name VERILOG_FILE ../rtl/data_rw_ctrl.v +set_global_assignment -name VERILOG_FILE ../rtl/uart_tx.v +set_global_assignment -name VERILOG_FILE ../rtl/uart_sd.v +set_global_assignment -name VERILOG_FILE ../rtl/uart_rx.v +set_global_assignment -name VERILOG_FILE ../rtl/sd_write.v +set_global_assignment -name VERILOG_FILE ../rtl/sd_read.v +set_global_assignment -name VERILOG_FILE ../rtl/sd_init.v +set_global_assignment -name VERILOG_FILE ../rtl/sd_ctrl.v +set_global_assignment -name QIP_FILE ip_core/clk_gen/clk_gen.qip +set_global_assignment -name QIP_FILE ip_core/fifo_wr_data/fifo_wr_data.qip +set_global_assignment -name QIP_FILE ip_core/fifo_rd_data/fifo_rd_data.qip + +set_global_assignment -name SLD_FILE "E:/GitLib/Altera/EP4CE10/base_code/21_uart_sd/quartus_prj/stp/stp1_auto_stripped.stp" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qws b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qws new file mode 100644 index 0000000..105501c Binary files /dev/null and b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd.qws differ diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd_assignment_defaults.qdf b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd_assignment_defaults.qdf new file mode 100644 index 0000000..f091ef2 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/quartus_prj/uart_sd_assignment_defaults.qdf @@ -0,0 +1,805 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 03:53:43 June 02, 2023 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus II software and is used +# to preserve global assignments across Quartus II versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name SMART_RECOMPILE Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name DISABLE_OCP_HW_EVAL Off +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone IV GX" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria VI" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix VI" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix VI" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Cyclone +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy III" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "HardCopy IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria VI" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Arria GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Stratix +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria VI" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix VI" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name SYNTHESIS_SEED 1 +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria VI" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix VI" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000B +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix VI" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000AE +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Cyclone +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000S +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy III" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Arria VI" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX3000A +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Stratix +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto +set_global_assignment -name AUTO_PACKED_REGISTERS Off +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO +set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix VI" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "HardCopy III" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria VI" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria VI" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix VI" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II" +set_global_assignment -name USE_CONFIGURATION_DEVICE On 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DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP 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SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name 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EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/data_rw_ctrl.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/data_rw_ctrl.v new file mode 100644 index 0000000..1bb9f5e --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/data_rw_ctrl.v @@ -0,0 +1,191 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +//Create Date : 2019/09/03 +// Module Name : data_rw +// Project Name : uart_sd +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : 读写数据控制模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module data_rw_ctrl +( + input wire sys_clk , //输入工作时钟,频率50MHz + input wire sys_rst_n , //输入复位信号,低电平有效 + input wire init_end , //SD卡初始化完成信号 + + input wire rx_flag , //写fifo写入数据标志信号 + input wire [7:0] rx_data , //写fifo写入数据 + input wire wr_req , //sd卡数据写请求 + input wire wr_busy , //sd卡写数据忙信号 + + output wire wr_en , //sd卡数据写使能信号 + output wire [31:0] wr_addr , //sd卡写数据扇区地址 + output wire [15:0] wr_data , //sd卡写数据 + + input wire rd_data_en , //sd卡读出数据标志信号 + input wire [15:0] rd_data , //sd卡读出数据 + input wire rd_busy , //sd卡读数据忙信号 + output reg rd_en , //sd卡数据读使能信号 + output wire [31:0] rd_addr , //sd卡读数据扇区地址 + output reg tx_flag , //读fifo读出数据标志信号 + output wire [7:0] tx_data //读fifo读出数据 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter DATA_NUM = 12'd256 ; //读写数据个数 +parameter SECTOR_ADDR = 32'd1000 ; //读写数据扇区地址 +parameter CNT_WAIT_MAX= 16'd60000 ; //读fifo输出数据时间间隔计数最大值 + +//wire define +wire [11:0] wr_fifo_data_num ; //写fifo内数据个数 +wire wr_busy_fall ; //sd卡写数据忙信号下降沿 +wire rd_busy_fall ; //sd卡读数据忙信号下降沿 +//wire rd_fifo_rd_en ; //读fifo读使能信号 + +//reg define +reg wr_busy_dly ; //sd卡写数据忙信号打一拍 +reg rd_busy_dly ; //sd卡读数据忙信号打一拍 +reg send_data_en ; //串口发送数据使能信号 +reg [15:0] cnt_wait ; //读fifo输出数据时间间隔计数 +reg [11:0] send_data_num ; //串口发送数据字节数计数 +reg rd_fifo_rd_en ; + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//wr_en:sd卡数据写使能信号 +assign wr_en = ((wr_fifo_data_num == (DATA_NUM)) && (init_end == 1'b1)) + ? 1'b1 : 1'b0; + +//wr_addr:sd卡写数据扇区地址 +assign wr_addr = SECTOR_ADDR; + +//wr_busy_dly:sd卡写数据忙信号打一拍 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + wr_busy_dly <= 1'b0; + else + wr_busy_dly <= wr_busy; + +//wr_busy_fall:sd卡写数据忙信号下降沿 +assign wr_busy_fall = ((wr_busy == 1'b0) && (wr_busy_dly == 1'b1)) + ? 1'b1 : 1'b0; + +//rd_en:sd卡数据读使能信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rd_en <= 1'b0; + else if(wr_busy_fall == 1'b1) + rd_en <= 1'b1; + else + rd_en <= 1'b0; + +//rd_addr:sd卡读数据扇区地址 +assign rd_addr = SECTOR_ADDR; + +//rd_busy_dly:sd卡读数据忙信号打一拍 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rd_busy_dly <= 1'b0; + else + rd_busy_dly <= rd_busy; + +//rd_busy_fall:sd卡读数据忙信号下降沿 +assign rd_busy_fall = ((rd_busy == 1'b0) && (rd_busy_dly == 1'b1)) + ? 1'b1 : 1'b0; + +//send_data_en:串口发送数据使能信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + send_data_en <= 1'b0; + else if((send_data_num == (DATA_NUM * 2) - 1'b1) + && (cnt_wait == CNT_WAIT_MAX - 1'b1)) + send_data_en <= 1'b0; + else if(rd_busy_fall == 1'b1) + send_data_en <= 1'b1; + else + send_data_en <= send_data_en; + +//cnt_wait:读fifo输出数据时间间隔计数 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_wait <= 16'd0; + else if(send_data_en == 1'b1) + if(cnt_wait == CNT_WAIT_MAX) + cnt_wait <= 16'd0; + else + cnt_wait <= cnt_wait + 1'b1; + else + cnt_wait <= 16'd0; + +//send_data_num:串口发送数据字节数计数 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + send_data_num <= 12'd0; + else if(send_data_en == 1'b1) + if(cnt_wait == CNT_WAIT_MAX) + send_data_num <= send_data_num + 1'b1; + else + send_data_num <= send_data_num; + else + send_data_num <= 12'd0; + +//rd_fifo_rd_en:读fifo读使能信号 +//assign rd_fifo_rd_en = (cnt_wait == CNT_WAIT_MAX) ? 1'b1 : 1'b0; +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rd_fifo_rd_en <= 1'b0; + else if(cnt_wait == (CNT_WAIT_MAX - 1'b1)) + rd_fifo_rd_en <= 1'b1; + else + rd_fifo_rd_en <= 1'b0; + +//tx_flag:读fifo读出数据标志信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + tx_flag <= 1'b0; + else + tx_flag <= rd_fifo_rd_en; + +//********************************************************************// +//************************** Instantiation ***************************// +//********************************************************************// +//------------- fifo_wr_data_inst ------------- +fifo_wr_data fifo_wr_data_inst +( + .wrclk (sys_clk ), //数据写时钟 + .wrreq (rx_flag ), //数据写使能 + .data (rx_data ), //写入数据 + + .rdclk (sys_clk ), //数据读时钟 + .rdreq (wr_req ), //数据读使能 + .q (wr_data ), //读出数据 + .rdusedw (wr_fifo_data_num ) //fifo内剩余数据个数 +); + +//------------- fifo_rd_data_inst ------------- +fifo_rd_data fifo_rd_data_inst +( + .wrclk (sys_clk ), //数据写时钟 + .wrreq (rd_data_en ), //数据写使能 + .data (rd_data ), //写入数据 + + .rdclk (sys_clk ), //数据读时钟 + .rdreq (rd_fifo_rd_en ), //数据读使能 + .q (tx_data ) //读出数据 +); + +endmodule \ No newline at end of file diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_ctrl.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_ctrl.v new file mode 100644 index 0000000..5f58911 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_ctrl.v @@ -0,0 +1,136 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +//Create Date : 2019/09/03 +// Module Name : sd_ctrl +// Project Name : uart_sd +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SD卡控制顶层模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module sd_ctrl +( + input wire sys_clk , //输入工作时钟,频率50MHz + input wire sys_clk_shift , //输入工作时钟,频率50MHz,相位偏移90度 + input wire sys_rst_n , //输入复位信号,低电平有效 + //SD卡接口 + input wire sd_miso , //主输入从输出信号 + output wire sd_clk , //SD卡时钟信号 + output reg sd_cs_n , //片选信号 + output reg sd_mosi , //主输出从输入信号 + //写SD卡接口 + input wire wr_en , //数据写使能信号 + input wire [31:0] wr_addr , //写数据扇区地址 + input wire [15:0] wr_data , //写数据 + output wire wr_busy , //写操作忙信号 + output wire wr_req , //写数据请求信号 + //读SD卡接口 + input wire rd_en , //数据读使能信号 + input wire [31:0] rd_addr , //读数据扇区地址 + output wire rd_busy , //读操作忙信号 + output wire rd_data_en , //读数据标志信号 + output wire [15:0] rd_data , //读数据 + + output wire init_end //SD卡初始化完成信号 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//wire define +wire init_cs_n ; //初始化阶段片选信号 +wire init_mosi ; //初始化阶段主输出从输入信号 +wire wr_cs_n ; //写数据阶段片选信号 +wire wr_mosi ; //写数据阶段主输出从输入信号 +wire rd_cs_n ; //读数据阶段片选信号 +wire rd_mosi ; //读数据阶段主输出从输入信号 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//sd_clk:SD卡时钟信号 +assign sd_clk = sys_clk_shift; + +//SD卡接口信号选择 +always@(*) + if(init_end == 1'b0) + begin + sd_cs_n <= init_cs_n; + sd_mosi <= init_mosi; + end + else if(wr_busy == 1'b1) + begin + sd_cs_n <= wr_cs_n; + sd_mosi <= wr_mosi; + end + else if(rd_busy == 1'b1) + begin + sd_cs_n <= rd_cs_n; + sd_mosi <= rd_mosi; + end + else + begin + sd_cs_n <= 1'b1; + sd_mosi <= 1'b1; + end + +//********************************************************************// +//************************** Instantiation ***************************// +//********************************************************************// +//------------- sd_init_inst ------------- +sd_init sd_init_inst +( + .sys_clk (sys_clk ), //输入工作时钟,频率50MHz + .sys_clk_shift (sys_clk_shift ), //输入工作时钟,频率50MHz,相位偏移90度 + .sys_rst_n (sys_rst_n ), //输入复位信号,低电平有效 + .miso (sd_miso ), //主输入从输出信号 + + .cs_n (init_cs_n ), //输出片选信号 + .mosi (init_mosi ), //主输出从输入信号 + .init_end (init_end ) //初始化完成信号 +); + +//------------- sd_write_inst ------------- +sd_write sd_write_inst +( + .sys_clk (sys_clk ), //输入工作时钟,频率50MHz + .sys_clk_shift (sys_clk_shift ), //输入工作时钟,频率50MHz,相位偏移90度 + .sys_rst_n (sys_rst_n ), //输入复位信号,低电平有效 + .miso (sd_miso ), //主输入从输出信号 + .wr_en (wr_en && init_end ), //数据写使能信号 + .wr_addr (wr_addr ), //写数据扇区地址 + .wr_data (wr_data ), //写数据 + + .cs_n (wr_cs_n ), //输出片选信号 + .mosi (wr_mosi ), //主输出从输入信号 + .wr_busy (wr_busy ), //写操作忙信号 + .wr_req (wr_req ) //写数据请求信号 +); + +//------------- sd_read_inst ------------- +sd_read sd_read_inst +( + .sys_clk (sys_clk ), //输入工作时钟,频率50MHz + .sys_clk_shift (sys_clk_shift ), //输入工作时钟,频率50MHz,相位偏移90度 + .sys_rst_n (sys_rst_n ), //输入复位信号,低电平有效 + .miso (sd_miso ), //主输入从输出信号 + .rd_en (rd_en & init_end ), //数据读使能信号 + .rd_addr (rd_addr ), //读数据扇区地址 + + .rd_busy (rd_busy ), //读操作忙信号 + .rd_data_en (rd_data_en ), //读数据标志信号 + .rd_data (rd_data ), //读数据 + .cs_n (rd_cs_n ), //片选信号 + .mosi (rd_mosi ) //主输出从输入信号 +); + +endmodule \ No newline at end of file diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_init.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_init.v new file mode 100644 index 0000000..3092489 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_init.v @@ -0,0 +1,271 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +//Create Date : 2019/09/03 +// Module Name : sd_init +// Project Name : uart_sd +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SD卡初始化 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module sd_init +( + input wire sys_clk , //输入工作时钟,频率50MHz + input wire sys_clk_shift , //输入工作时钟,频率50MHz,相位偏移90度 + input wire sys_rst_n , //输入复位信号,低电平有效 + input wire miso , //主输入从输出信号 + + output reg cs_n , //输出片选信号 + output reg mosi , //主输出从输入信号 + output reg init_end //初始化完成信号 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter CMD0 = {8'h40,8'h00,8'h00,8'h00,8'h00,8'h95}, //复位指令 + CMD8 = {8'h48,8'h00,8'h00,8'h01,8'haa,8'h87}, //查询电压指令 + CMD55 = {8'h77,8'h00,8'h00,8'h00,8'h00,8'hff}, //应用指令告知指令 + ACMD41 = {8'h69,8'h40,8'h00,8'h00,8'h00,8'hff}; //应用指令 +parameter CNT_WAIT_MAX = 9'd511; //上电后同步过程等待时钟计数最大值 +parameter IDLE = 4'b0000, //初始状态 + SEND_CMD0 = 4'b0001, //CMD0发送状态 + CMD0_ACK = 4'b0011, //CMD0响应状态 + SEND_CMD8 = 4'b0010, //CMD8发送状态 + CMD8_ACK = 4'b0110, //CMD8响应状态 + SEND_CMD55 = 4'b0111, //CMD55发送状态 + CMD55_ACK = 4'b0101, //CMD55响应状态 + SEND_ACMD41 = 4'b0100, //ACMD41发送状态 + ACMD41_ACK = 4'b1100, //ACMD41响应状态 + INIT_END = 4'b1101; //初始化完成状态 + +//reg define +reg [8:0] cnt_wait ; //上电同步时钟计数器 +reg [3:0] state ; //状态机状态 +reg [7:0] cnt_cmd_bit ; //指令比特计数器 +reg miso_dly ; //主输入从输出信号打一拍 +reg ack_en ; //响应使能信号 +reg [39:0] ack_data ; //响应数据 +reg [7:0] cnt_ack_bit ; //响应数据字节计数 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//cnt_wait:上电同步时钟计数器 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_wait <= 9'd0; + else if(cnt_wait >= CNT_WAIT_MAX) + cnt_wait <= CNT_WAIT_MAX; + else + cnt_wait <= cnt_wait + 1'b1; + +//state:状态机状态跳转 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + state <= IDLE; + else + case(state) + IDLE: + if(cnt_wait == CNT_WAIT_MAX) + state <= SEND_CMD0; + else + state <= state; + SEND_CMD0: + if(cnt_cmd_bit == 8'd48) + state <= CMD0_ACK; + else + state <= state; + CMD0_ACK: + if(cnt_ack_bit == 8'd48) + if(ack_data[39:32] == 8'h01) + state <= SEND_CMD8; + else + state <= SEND_CMD0; + else + state <= state; + SEND_CMD8: + if(cnt_cmd_bit == 8'd48) + state <= CMD8_ACK; + else + state <= state; + CMD8_ACK: + if(cnt_ack_bit == 8'd48) + if(ack_data[11:8] == 4'b0001) + state <= SEND_CMD55; + else + state <= SEND_CMD8; + else + state <= state; + SEND_CMD55: + if(cnt_cmd_bit == 8'd48) + state <= CMD55_ACK; + else + state <= state; + CMD55_ACK: + if(cnt_ack_bit == 8'd48) + if(ack_data[39:32] == 8'h01) + state <= SEND_ACMD41; + else + state <= SEND_CMD55; + else + state <= state; + SEND_ACMD41: + if(cnt_cmd_bit == 8'd48) + state <= ACMD41_ACK; + else + state <= state; + ACMD41_ACK: + if(cnt_ack_bit == 8'd48) + if(ack_data[39:32] == 8'h00) + state <= INIT_END; + else + state <= SEND_CMD55; + else + state <= state; + INIT_END: + state <= state; + default: + state <= IDLE; + endcase + +//cs_n,mosi,init_end,cnt_cmd_bit +//片选信号,主输出从输入信号,初始化结束信号,指令比特计数器 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + cs_n <= 1'b1; + mosi <= 1'b1; + init_end <= 1'b0; + cnt_cmd_bit <= 8'd0; + end + else + case(state) + IDLE: + begin + cs_n <= 1'b1; + mosi <= 1'b1; + init_end <= 1'b0; + cnt_cmd_bit <= 8'd0; + end + SEND_CMD0: + if(cnt_cmd_bit == 8'd48) + cnt_cmd_bit <= 8'd0; + else + begin + cs_n <= 1'b0; + mosi <= CMD0[8'd47 - cnt_cmd_bit]; + init_end <= 1'b0; + cnt_cmd_bit <= cnt_cmd_bit + 8'd1; + end + CMD0_ACK: + if(cnt_ack_bit == 8'd47) + cs_n <= 1'b1; + else + cs_n <= 1'b0; + SEND_CMD8: + if(cnt_cmd_bit == 8'd48) + cnt_cmd_bit <= 8'd0; + else + begin + cs_n <= 1'b0; + mosi <= CMD8[8'd47 - cnt_cmd_bit]; + init_end <= 1'b0; + cnt_cmd_bit <= cnt_cmd_bit + 8'd1; + end + CMD8_ACK: + if(cnt_ack_bit == 8'd47) + cs_n <= 1'b1; + else + cs_n <= 1'b0; + SEND_CMD55: + if(cnt_cmd_bit == 8'd48) + cnt_cmd_bit <= 8'd0; + else + begin + cs_n <= 1'b0; + mosi <= CMD55[8'd47 - cnt_cmd_bit]; + init_end <= 1'b0; + cnt_cmd_bit <= cnt_cmd_bit + 8'd1; + end + CMD55_ACK: + if(cnt_ack_bit == 8'd47) + cs_n <= 1'b1; + else + cs_n <= 1'b0; + SEND_ACMD41: + if(cnt_cmd_bit == 8'd48) + cnt_cmd_bit <= 8'd0; + else + begin + cs_n <= 1'b0; + mosi <= ACMD41[8'd47 - cnt_cmd_bit]; + init_end <= 1'b0; + cnt_cmd_bit <= cnt_cmd_bit + 8'd1; + end + ACMD41_ACK: + if(cnt_ack_bit < 8'd47) + cs_n <= 1'b0; + else + cs_n <= 1'b1; + INIT_END: + begin + cs_n <= 1'b1; + mosi <= 1'b1; + init_end <= 1'b1; + end + default: + begin + cs_n <= 1'b1; + mosi <= 1'b1; + end + endcase + +//miso_dly:主输入从输出信号打一拍 +always@(posedge sys_clk_shift or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + miso_dly <= 1'b0; + else + miso_dly <= miso; + +//ack_en:响应使能信号 +always@(posedge sys_clk_shift or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + ack_en <= 1'b0; + else if(cnt_ack_bit == 8'd47) + ack_en <= 1'b0; + else if((miso == 1'b0) && (miso_dly == 1'b1) && (cnt_ack_bit == 8'd0)) + ack_en <= 1'b1; + else + ack_en <= ack_en; + +//ack_data:响应数据 +//cnt_ack_bit:响应数据字节计数 +always@(posedge sys_clk_shift or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + ack_data <= 8'b0; + cnt_ack_bit <= 8'd0; + end + else if(ack_en == 1'b1) + begin + cnt_ack_bit <= cnt_ack_bit + 8'd1; + if(cnt_ack_bit < 8'd40) + ack_data <= {ack_data[38:0],miso_dly}; + else + ack_data <= ack_data; + end + else + cnt_ack_bit <= 8'd0; + +endmodule diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_init.v.bak b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_init.v.bak new file mode 100644 index 0000000..50c320c --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_init.v.bak @@ -0,0 +1,271 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +//Create Date : 2019/09/03 +// Module Name : sd_init +// Project Name : uart_sd +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SD卡初始化 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module sd_init +( + input wire sys_clk , //输入工作时钟,频率50MHz + input wire sys_clk_shift , //输入工作时钟,频率50MHz,相位偏移90度 + input wire sys_rst_n , //输入复位信号,低电平有效 + input wire miso , //主输入从输出信号 + + output reg cs_n , //输出片选信号 + output reg mosi , //主输出从输入信号 + output reg init_end //初始化完成信号 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter CMD0 = {8'h40,8'h00,8'h00,8'h00,8'h00,8'h95}, //复位指令 + CMD8 = {8'h48,8'h00,8'h00,8'h01,8'haa,8'h87}, //查询电压指令 + CMD55 = {8'h77,8'h00,8'h00,8'h00,8'h00,8'hff}, //应用指令告知指令 + ACMD41 = {8'h69,8'h40,8'h00,8'h00,8'h00,8'hff}; //应用指令 +parameter CNT_WAIT_MAX = 8'd100; //上电后同步过程等待时钟计数最大值 +parameter IDLE = 4'b0000, //初始状态 + SEND_CMD0 = 4'b0001, //CMD0发送状态 + CMD0_ACK = 4'b0011, //CMD0响应状态 + SEND_CMD8 = 4'b0010, //CMD8发送状态 + CMD8_ACK = 4'b0110, //CMD8响应状态 + SEND_CMD55 = 4'b0111, //CMD55发送状态 + CMD55_ACK = 4'b0101, //CMD55响应状态 + SEND_ACMD41 = 4'b0100, //ACMD41发送状态 + ACMD41_ACK = 4'b1100, //ACMD41响应状态 + INIT_END = 4'b1101; //初始化完成状态 + +//reg define +reg [7:0] cnt_wait ; //上电同步时钟计数器 +reg [3:0] state ; //状态机状态 +reg [7:0] cnt_cmd_bit ; //指令比特计数器 +reg miso_dly ; //主输入从输出信号打一拍 +reg ack_en ; //响应使能信号 +reg [39:0] ack_data ; //响应数据 +reg [7:0] cnt_ack_bit ; //响应数据字节计数 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//cnt_wait:上电同步时钟计数器 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_wait <= 8'd0; + else if(cnt_wait >= CNT_WAIT_MAX) + cnt_wait <= CNT_WAIT_MAX; + else + cnt_wait <= cnt_wait + 1'b1; + +//state:状态机状态跳转 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + state <= IDLE; + else + case(state) + IDLE: + if(cnt_wait == CNT_WAIT_MAX) + state <= SEND_CMD0; + else + state <= state; + SEND_CMD0: + if(cnt_cmd_bit == 8'd48) + state <= CMD0_ACK; + else + state <= state; + CMD0_ACK: + if(cnt_ack_bit == 8'd48) + if(ack_data[39:32] == 8'h01) + state <= SEND_CMD8; + else + state <= SEND_CMD0; + else + state <= state; + SEND_CMD8: + if(cnt_cmd_bit == 8'd48) + state <= CMD8_ACK; + else + state <= state; + CMD8_ACK: + if(cnt_ack_bit == 8'd48) + if(ack_data[11:8] == 4'b0001) + state <= SEND_CMD55; + else + state <= SEND_CMD8; + else + state <= state; + SEND_CMD55: + if(cnt_cmd_bit == 8'd48) + state <= CMD55_ACK; + else + state <= state; + CMD55_ACK: + if(cnt_ack_bit == 8'd48) + if(ack_data[39:32] == 8'h01) + state <= SEND_ACMD41; + else + state <= SEND_CMD55; + else + state <= state; + SEND_ACMD41: + if(cnt_cmd_bit == 8'd48) + state <= ACMD41_ACK; + else + state <= state; + ACMD41_ACK: + if(cnt_ack_bit == 8'd48) + if(ack_data[39:32] == 8'h00) + state <= INIT_END; + else + state <= SEND_CMD55; + else + state <= state; + INIT_END: + state <= state; + default: + state <= IDLE; + endcase + +//cs_n,mosi,init_end,cnt_cmd_bit +//片选信号,主输出从输入信号,初始化结束信号,指令比特计数器 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + cs_n <= 1'b1; + mosi <= 1'b1; + init_end <= 1'b0; + cnt_cmd_bit <= 8'd0; + end + else + case(state) + IDLE: + begin + cs_n <= 1'b1; + mosi <= 1'b1; + init_end <= 1'b0; + cnt_cmd_bit <= 8'd0; + end + SEND_CMD0: + if(cnt_cmd_bit == 8'd48) + cnt_cmd_bit <= 8'd0; + else + begin + cs_n <= 1'b0; + mosi <= CMD0[8'd47 - cnt_cmd_bit]; + init_end <= 1'b0; + cnt_cmd_bit <= cnt_cmd_bit + 8'd1; + end + CMD0_ACK: + if(cnt_ack_bit == 8'd47) + cs_n <= 1'b1; + else + cs_n <= 1'b0; + SEND_CMD8: + if(cnt_cmd_bit == 8'd48) + cnt_cmd_bit <= 8'd0; + else + begin + cs_n <= 1'b0; + mosi <= CMD8[8'd47 - cnt_cmd_bit]; + init_end <= 1'b0; + cnt_cmd_bit <= cnt_cmd_bit + 8'd1; + end + CMD8_ACK: + if(cnt_ack_bit == 8'd47) + cs_n <= 1'b1; + else + cs_n <= 1'b0; + SEND_CMD55: + if(cnt_cmd_bit == 8'd48) + cnt_cmd_bit <= 8'd0; + else + begin + cs_n <= 1'b0; + mosi <= CMD55[8'd47 - cnt_cmd_bit]; + init_end <= 1'b0; + cnt_cmd_bit <= cnt_cmd_bit + 8'd1; + end + CMD55_ACK: + if(cnt_ack_bit == 8'd47) + cs_n <= 1'b1; + else + cs_n <= 1'b0; + SEND_ACMD41: + if(cnt_cmd_bit == 8'd48) + cnt_cmd_bit <= 8'd0; + else + begin + cs_n <= 1'b0; + mosi <= ACMD41[8'd47 - cnt_cmd_bit]; + init_end <= 1'b0; + cnt_cmd_bit <= cnt_cmd_bit + 8'd1; + end + ACMD41_ACK: + if(cnt_ack_bit < 8'd47) + cs_n <= 1'b0; + else + cs_n <= 1'b1; + INIT_END: + begin + cs_n <= 1'b1; + mosi <= 1'b1; + init_end <= 1'b1; + end + default: + begin + cs_n <= 1'b1; + mosi <= 1'b1; + end + endcase + +//miso_dly:主输入从输出信号打一拍 +always@(posedge sys_clk_shift or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + miso_dly <= 1'b0; + else + miso_dly <= miso; + +//ack_en:响应使能信号 +always@(posedge sys_clk_shift or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + ack_en <= 1'b0; + else if(cnt_ack_bit == 8'd47) + ack_en <= 1'b0; + else if((miso == 1'b0) && (miso_dly == 1'b1) && (cnt_ack_bit == 8'd0)) + ack_en <= 1'b1; + else + ack_en <= ack_en; + +//ack_data:响应数据 +//cnt_ack_bit:响应数据字节计数 +always@(posedge sys_clk_shift or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + ack_data <= 8'b0; + cnt_ack_bit <= 8'd0; + end + else if(ack_en == 1'b1) + begin + cnt_ack_bit <= cnt_ack_bit + 8'd1; + if(cnt_ack_bit < 8'd40) + ack_data <= {ack_data[38:0],miso_dly}; + else + ack_data <= ack_data; + end + else + cnt_ack_bit <= 8'd0; + +endmodule diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_read.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_read.v new file mode 100644 index 0000000..f7fc271 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_read.v @@ -0,0 +1,268 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +//Create Date : 2019/09/03 +// Module Name : sd_read +// Project Name : uart_sd +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SD卡数据读操作 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module sd_read +( + input wire sys_clk , //输入工作时钟,频率50MHz + input wire sys_clk_shift , //输入工作时钟,频率50MHz,相位偏移90度 + input wire sys_rst_n , //输入复位信号,低电平有效 + input wire miso , //主输入从输出信号 + input wire rd_en , //数据读使能信号 + input wire [31:0] rd_addr , //读数据扇区地址 + + output wire rd_busy , //读操作忙信号 + output reg rd_data_en , //读数据标志信号 + output reg [15:0] rd_data , //读数据 + output reg cs_n , //片选信号 + output reg mosi //主输出从输入信号 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter IDLE = 3'b000 , //初始状态 + SEND_CMD17 = 3'b001 , //读命令CMD17发送状态 + CMD17_ACK = 3'b011 , //CMD17响应状态 + RD_DATA = 3'b010 , //读数据状态 + RD_END = 3'b110 ; //读结束状态 +parameter DATA_NUM = 12'd256 ; //待读取数据字节数 + +//wire define +wire [47:0] cmd_rd ; //数据读指令 + +//reg define +reg [2:0] state ; //状态机状态 +reg [7:0] cnt_cmd_bit ; //指令比特计数器 +reg ack_en ; //响应使能信号 +reg [7:0] ack_data ; //响应数据 +reg [7:0] cnt_ack_bit ; //响应数据字节计数 +reg [11:0] cnt_data_num; //读出数据个数计数 +reg [3:0] cnt_data_bit; //读数据比特计数器 +reg [2:0] cnt_end ; //结束状态时钟计数 +reg miso_dly ; //主输入从输出信号打一拍 +reg [15:0] rd_data_reg ; //读出数据寄存 +reg [15:0] byte_head ; //读数据字节头 +reg byte_head_en; //读数据字节头使能 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//rd_busy:读操作忙信号 +assign rd_busy = (state != IDLE) ? 1'b1 : 1'b0; + +//cmd_rd:数据读指令 +assign cmd_rd = {8'h51,rd_addr,8'hff}; + +//miso_dly:主输入从输出信号打一拍 +always@(posedge sys_clk_shift or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + miso_dly <= 1'b0; + else + miso_dly <= miso; + +//ack_en:响应使能信号 +always@(posedge sys_clk_shift or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + ack_en <= 1'b0; + else if(cnt_ack_bit == 8'd15) + ack_en <= 1'b0; + else if((state == CMD17_ACK) && (miso == 1'b0) + && (miso_dly == 1'b1) && (cnt_ack_bit == 8'd0)) + ack_en <= 1'b1; + else + ack_en <= ack_en; + +//ack_data:响应数据 +//cnt_ack_bit:响应数据字节计数 +always@(posedge sys_clk_shift or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + ack_data <= 8'b0; + cnt_ack_bit <= 8'd0; + end + else if(ack_en == 1'b1) + begin + cnt_ack_bit <= cnt_ack_bit + 8'd1; + if(cnt_ack_bit < 8'd8) + ack_data <= {ack_data[6:0],miso_dly}; + else + ack_data <= ack_data; + end + else + cnt_ack_bit <= 8'd0; + +//state:状态机状态跳转 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + state <= IDLE; + else + case(state) + IDLE: + if(rd_en == 1'b1) + state <= SEND_CMD17; + else + state <= state; + SEND_CMD17: + if(cnt_cmd_bit == 8'd47) + state <= CMD17_ACK; + else + state <= state; + CMD17_ACK: + if(cnt_ack_bit == 8'd15) + if(ack_data == 8'h00) + state <= RD_DATA; + else + state <= SEND_CMD17; + else + state <= state; + RD_DATA: + if((cnt_data_num == (DATA_NUM + 1'b1)) + && (cnt_data_bit == 4'd15)) + state <= RD_END; + else + state <= state; + RD_END: + if(cnt_end == 3'd7) + state <= IDLE; + else + state <= state; + default:state <= IDLE; + endcase + +//cs_n:输出片选信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cs_n <= 1'b1; + else if(cnt_end == 3'd7) + cs_n <= 1'b1; + else if(rd_en == 1'b1) + cs_n <= 1'b0; + else + cs_n <= cs_n; + +//cnt_cmd_bit:指令比特计数器 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_cmd_bit <= 8'd0; + else if(state == SEND_CMD17) + cnt_cmd_bit <= cnt_cmd_bit + 8'd1; + else + cnt_cmd_bit <= 8'd0; + +//mosi:主输出从输入信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + mosi <= 1'b1; + else if(state == SEND_CMD17) + mosi <= cmd_rd[8'd47 - cnt_cmd_bit]; + else + mosi <= 1'b1; + +//byte_head:读数据字节头 +always@(posedge sys_clk_shift or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + byte_head <= 16'b0; + else if(byte_head_en == 1'b0) + byte_head <= 16'b0; + else if(byte_head_en == 1'b1) + byte_head <= {byte_head[14:0],miso}; + else + byte_head <= byte_head; + +//byte_head_en:读数据字节头使能 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + byte_head_en <= 1'b0; + else if(byte_head == 16'hfffe) + byte_head_en <= 1'b0; + else if((state == RD_DATA) && (cnt_data_num == 12'd0) + && (cnt_data_bit == 4'd0)) + byte_head_en <= 1'b1; + else + byte_head_en <= byte_head_en; + +//cnt_data_bit:读数据比特计数器 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_data_bit <= 4'd0; + else if((state == RD_DATA) && (cnt_data_num >= 12'd1)) + cnt_data_bit <= cnt_data_bit + 4'd1; + else + cnt_data_bit <= 4'd0; + +//cnt_data_num:读出数据个数计数 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_data_num <= 12'd0; + else if(state == RD_DATA) + if((cnt_data_bit == 4'd15) || (byte_head == 16'hfffe)) + cnt_data_num <= cnt_data_num + 12'd1; + else + cnt_data_num <= cnt_data_num; + else + cnt_data_num <= 12'd0; + +//rd_data_reg:读出数据寄存 +always@(posedge sys_clk_shift or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rd_data_reg <= 16'd0; + else if((state == RD_DATA) && (cnt_data_num >= 12'd1) + && (cnt_data_num <= DATA_NUM)) + rd_data_reg <= {rd_data_reg[14:0],miso}; + else + rd_data_reg <= 16'd0; + +//rd_data_en:读数据标志信号 +//rd_data:读数据 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + rd_data_en <= 1'b0; + rd_data <= 16'd0; + end + else if(state == RD_DATA) + begin + if((cnt_data_bit == 4'd15) && (cnt_data_num <= DATA_NUM)) + begin + rd_data_en <= 1'b1; + rd_data <= rd_data_reg; + end + else + begin + rd_data_en <= 1'b0; + rd_data <= rd_data; + end + end + else + begin + rd_data_en <= 1'b0; + rd_data <= 16'd0; + end + +//cnt_end:结束状态时钟计数 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_end <= 3'd0; + else if(state == RD_END) + cnt_end <= cnt_end + 3'd1; + else + cnt_end <= 3'd0; + +endmodule diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_write.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_write.v new file mode 100644 index 0000000..1b23bf1 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/sd_write.v @@ -0,0 +1,234 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +//Create Date : 2019/09/03 +// Module Name : sd_write +// Project Name : uart_sd +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SD卡数据写操作 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module sd_write +( + input wire sys_clk , //输入工作时钟,频率50MHz + input wire sys_clk_shift , //输入工作时钟,频率50MHz,相位偏移90度 + input wire sys_rst_n , //输入复位信号,低电平有效 + input wire miso , //主输入从输出信号 + input wire wr_en , //数据写使能信号 + input wire [31:0] wr_addr , //写数据扇区地址 + input wire [15:0] wr_data , //写数据 + + output reg cs_n , //输出片选信号 + output reg mosi , //主输出从输入信号 + output wire wr_busy , //写操作忙信号 + output wire wr_req //写数据请求信号 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter IDLE = 3'b000 , //初始状态 + SEND_CMD24 = 3'b001 , //写命令CMD24发送状态 + CMD24_ACK = 3'b011 , //CMD24响应状态 + WR_DATA = 3'b010 , //写数据状态 + WR_BUSY = 3'b110 , //SD卡写忙状态 + WR_END = 3'b111 ; //写结束状态 +parameter DATA_NUM = 12'd256 ; //待写入数据字节数 +parameter BYTE_HEAD = 16'hfffe; //写数据字节头 + +//wire define +wire [47:0] cmd_wr ; //数据写指令 + +//reg define +reg [2:0] state ; //状态机状态 +reg [7:0] cnt_cmd_bit ; //指令比特计数器 +reg ack_en ; //响应使能信号 +reg [7:0] ack_data ; //响应数据 +reg [7:0] cnt_ack_bit ; //响应数据字节计数 +reg [11:0] cnt_data_num; //写入数据个数计数 +reg [3:0] cnt_data_bit; //写数据比特计数器 +reg [7:0] busy_data ; //忙状态数据 +reg [2:0] cnt_end ; //结束状态时钟计数 +reg miso_dly ; //主输入从输出信号打一拍 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//wr_busy:写操作忙信号 +assign wr_busy = (state != IDLE) ? 1'b1 : 1'b0; + +//wr_req:写数据请求信号 +assign wr_req = ((cnt_data_num <= DATA_NUM - 1'b1) && (cnt_data_bit == 4'd15)) + ? 1'b1 : 1'b0; + +//cmd_wr:数据写指令 +assign cmd_wr = {8'h58,wr_addr,8'hff}; + +//miso_dly:主输入从输出信号打一拍 +always@(posedge sys_clk_shift or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + miso_dly <= 1'b0; + else + miso_dly <= miso; + +//ack_en:响应使能信号 +always@(posedge sys_clk_shift or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + ack_en <= 1'b0; + else if(cnt_ack_bit == 8'd15) + ack_en <= 1'b0; + else if((state == CMD24_ACK) && (miso == 1'b0) + && (miso_dly == 1'b1) && (cnt_ack_bit == 8'd0)) + ack_en <= 1'b1; + else + ack_en <= ack_en; + +//ack_data:响应数据 +//cnt_ack_bit:响应数据字节计数 +always@(posedge sys_clk_shift or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + ack_data <= 8'b0; + cnt_ack_bit <= 8'd0; + end + else if(ack_en == 1'b1) + begin + cnt_ack_bit <= cnt_ack_bit + 8'd1; + if(cnt_ack_bit < 8'd8) + ack_data <= {ack_data[6:0],miso_dly}; + else + ack_data <= ack_data; + end + else + cnt_ack_bit <= 8'd0; + +//busy_data:忙状态数据 +always@(posedge sys_clk_shift or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + busy_data <= 8'd0; + else if(state == WR_BUSY) + busy_data <= {busy_data[6:0],miso}; + else + busy_data <= 8'd0; + +//state:状态机状态跳转 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + state <= IDLE; + else + case(state) + IDLE: + if(wr_en == 1'b1) + state <= SEND_CMD24; + else + state <= state; + SEND_CMD24: + if(cnt_cmd_bit == 8'd47) + state <= CMD24_ACK; + else + state <= state; + CMD24_ACK: + if(cnt_ack_bit == 8'd15) + if(ack_data == 8'h00) + state <= WR_DATA; + else + state <= SEND_CMD24; + else + state <= state; + WR_DATA: + if((cnt_data_num == (DATA_NUM + 1'b1)) + && (cnt_data_bit == 4'd15)) + state <= WR_BUSY; + else + state <= state; + WR_BUSY: + if(busy_data == 8'hff) + state <= WR_END; + else + state <= state; + WR_END: + if(cnt_end == 3'd7) + state <= IDLE; + else + state <= state; + default:state <= IDLE; + endcase + +//cs_n:输出片选信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cs_n <= 1'b1; + else if(cnt_end == 3'd7) + cs_n <= 1'b1; + else if(wr_en == 1'b1) + cs_n <= 1'b0; + else + cs_n <= cs_n; + +//cnt_cmd_bit:指令比特计数器 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_cmd_bit <= 8'd0; + else if(state == SEND_CMD24) + cnt_cmd_bit <= cnt_cmd_bit + 8'd1; + else + cnt_cmd_bit <= 8'd0; + +//mosi:主输出从输入信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + mosi <= 1'b1; + else if(state == SEND_CMD24) + mosi <= cmd_wr[8'd47 - cnt_cmd_bit]; + else if(state == WR_DATA) + if(cnt_data_num == 12'd0) + mosi <= BYTE_HEAD[15 - cnt_data_bit]; + else if((cnt_data_num >= 12'd1) && (cnt_data_num <= DATA_NUM)) + mosi <= wr_data[15 - cnt_data_bit]; + else + mosi <= 1'b1; + else + mosi <= 1'b1; + +//cnt_data_bit:写数据比特计数器 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_data_bit <= 4'd0; + else if(state == WR_DATA) + cnt_data_bit <= cnt_data_bit + 4'd1; + else + cnt_data_bit <= 4'd0; + +//cnt_data_num:写入数据个数计数 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_data_num <= 12'd0; + else if(state == WR_DATA) + if(cnt_data_bit == 4'd15) + cnt_data_num <= cnt_data_num + 12'd1; + else + cnt_data_num <= cnt_data_num; + else + cnt_data_num <= 12'd0; + +//cnt_end:结束状态时钟计数 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_end <= 3'd0; + else if(state == WR_END) + cnt_end <= cnt_end + 3'd1; + else + cnt_end <= 3'd0; + +endmodule + diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_rx.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_rx.v new file mode 100644 index 0000000..ad85158 --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_rx.v @@ -0,0 +1,154 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +//Create Date : 2019/06/12 +// Module Name : uart_rx +// Project Name : uart_sd +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module uart_rx +#( + parameter UART_BPS = 'd9600, //串口波特率 + parameter CLK_FREQ = 'd50_000_000 //时钟频率 +) +( + input wire sys_clk , //系统时钟50MHz + input wire sys_rst_n , //全局复位 + input wire rx , //串口接收数据 + + output reg [7:0] po_data , //串转并后的8bit数据 + output reg po_flag //串转并后的数据有效标志信号 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//localparam define +localparam BAUD_CNT_MAX = CLK_FREQ/UART_BPS ; + +//reg define +reg rx_reg1 ; +reg rx_reg2 ; +reg rx_reg3 ; +reg start_nedge ; +reg work_en ; +reg [12:0] baud_cnt ; +reg bit_flag ; +reg [3:0] bit_cnt ; +reg [7:0] rx_data ; +reg rx_flag ; + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//插入两级寄存器进行数据同步，用来消除亚稳态 +//rx_reg1:第一级寄存器，寄存器空闲状态复位为1 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rx_reg1 <= 1'b1; + else + rx_reg1 <= rx; + +//rx_reg2:第二级寄存器，寄存器空闲状态复位为1 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rx_reg2 <= 1'b1; + else + rx_reg2 <= rx_reg1; + +//rx_reg3:第三级寄存器和第二级寄存器共同构成下降沿检测 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rx_reg3 <= 1'b1; + else + rx_reg3 <= rx_reg2; + +//start_nedge:检测到下降沿时start_nedge产生一个时钟的高电平 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + start_nedge <= 1'b0; + else if((~rx_reg2) && (rx_reg3)) + start_nedge <= 1'b1; + else + start_nedge <= 1'b0; + +//work_en:接收数据工作使能信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + work_en <= 1'b0; + else if(start_nedge == 1'b1) + work_en <= 1'b1; + else if((bit_cnt == 4'd8) && (bit_flag == 1'b1)) + work_en <= 1'b0; + +//baud_cnt:波特率计数器计数，从0计数到BAUD_CNT_MAX - 1 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + baud_cnt <= 13'b0; + else if((baud_cnt == BAUD_CNT_MAX - 1) || (work_en == 1'b0)) + baud_cnt <= 13'b0; + else if(work_en == 1'b1) + baud_cnt <= baud_cnt + 1'b1; + +//bit_flag:当baud_cnt计数器计数到中间数时采样的数据最稳定， +//此时拉高一个标志信号表示数据可以被取走 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + bit_flag <= 1'b0; + else if(baud_cnt == BAUD_CNT_MAX/2 - 1) + bit_flag <= 1'b1; + else + bit_flag <= 1'b0; + +//bit_cnt:有效数据个数计数器，当8个有效数据（不含起始位和停止位） +//都接收完成后计数器清零 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + bit_cnt <= 4'b0; + else if((bit_cnt == 4'd8) && (bit_flag == 1'b1)) + bit_cnt <= 4'b0; + else if(bit_flag ==1'b1) + bit_cnt <= bit_cnt + 1'b1; + +//rx_data:输入数据进行移位 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rx_data <= 8'b0; + else if((bit_cnt >= 4'd1)&&(bit_cnt <= 4'd8)&&(bit_flag == 1'b1)) + rx_data <= {rx_reg3, rx_data[7:1]}; + +//rx_flag:输入数据移位完成时rx_flag拉高一个时钟的高电平 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rx_flag <= 1'b0; + else if((bit_cnt == 4'd8) && (bit_flag == 1'b1)) + rx_flag <= 1'b1; + else + rx_flag <= 1'b0; + +//po_data:输出完整的8位有效数据 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + po_data <= 8'b0; + else if(rx_flag == 1'b1) + po_data <= rx_data; + +//po_flag:输出数据有效标志（比rx_flag延后一个时钟周期，为了和po_data同步） +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + po_flag <= 1'b0; + else + po_flag <= rx_flag; + +endmodule diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_sd.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_sd.v new file mode 100644 index 0000000..d85f92d --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_sd.v @@ -0,0 +1,162 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +//Create Date : 2019/09/03 +// Module Name : uart_sd +// Project Name : uart_sd +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : 串口读写SD卡顶层模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module uart_sd +( + input wire sys_clk , //输入工作时钟,频率50MHz + input wire sys_rst_n , //输入复位信号,低电平有效 + input wire rx , //串口发送数据 + input wire sd_miso , //主输入从输出信号 + + output wire sd_clk , //SD卡时钟信号 + output wire sd_cs_n , //片选信号 + output wire sd_mosi , //主输出从输入信号 + output wire tx //串口接收数据 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter UART_BPS = 14'd9600 , //比特率 + CLK_FREQ = 26'd50_000_000 ; //时钟频率 + +//wire define +wire rx_flag ; //写fifo写入数据标志信号 +wire [7:0] rx_data ; //写fifo写入数据 +wire wr_req ; //sd卡数据写请求 +wire wr_busy ; //sd卡写数据忙信号 +wire wr_en ; //sd卡数据写使能信号 +wire [31:0] wr_addr ; //sd卡写数据扇区地址 +wire [15:0] wr_data ; //sd卡写数据 +wire rd_data_en ; //sd卡读出数据标志信号 +wire [15:0] rd_data ; //sd卡读出数据 +wire rd_busy ; //sd卡读数据忙信号 +wire rd_en ; //sd卡数据读使能信号 +wire [31:0] rd_addr ; //sd卡读数据扇区地址 +wire tx_flag ; //读fifo读出数据标志信号 +wire [7:0] tx_data ; //读fifo读出数据 +wire clk_50m ; //生成50MHz时钟 +wire clk_50m_shift ; //生成50MHz时钟,相位偏移180度 +wire locked ; //时钟锁定信号 +wire rst_n ; //复位信号 +wire init_end ; //SD卡初始化完成信号 + +//rst_n:复位信号,低有效 +assign rst_n = sys_rst_n && locked; + +//********************************************************************// +//************************** Instantiation ***************************// +//********************************************************************// +//------------- clk_gen_inst ------------- +clk_gen clk_gen_inst +( + .areset (~sys_rst_n ), //复位信号,高有效 + .inclk0 (sys_clk ), //输入系统时钟,50MHz + + .c0 (clk_50m ), //生成50MHz时钟 + .c1 (clk_50m_shift ), //生成50MHz时钟,相位偏移180度 + .locked (locked ) //时钟锁定信号 + ); + +//------------- uart_rx_inst ------------- +uart_rx +#( + .UART_BPS (UART_BPS ), //串口波特率 + .CLK_FREQ (CLK_FREQ ) //时钟频率 +) +uart_rx_inst +( + .sys_clk (clk_50m ), //系统时钟50Mhz + .sys_rst_n (rst_n ), //全局复位 + .rx (rx ), //串口接收数据 + + .po_data (rx_data ), //串转并后的数据 + .po_flag (rx_flag ) //串转并后的数据有效标志信号 +); + +//------------- data_rw_ctrl_inst ------------- +data_rw_ctrl data_rw_ctrl_inst +( + .sys_clk (clk_50m ), //输入工作时钟,频率50MHz + .sys_rst_n (rst_n ), //输入复位信号,低电平有效 + .init_end (init_end ), //SD卡初始化完成信号 + + .rx_flag (rx_flag ), //写fifo写入数据标志信号 + .rx_data (rx_data ), //写fifo写入数据 + .wr_req (wr_req ), //sd卡数据写请求 + .wr_busy (wr_busy ), //sd卡写数据忙信号 + + .wr_en (wr_en ), //sd卡数据写使能信号 + .wr_addr (wr_addr ), //sd卡写数据扇区地址 + .wr_data (wr_data ), //sd卡写数据 + + .rd_data_en (rd_data_en), //sd卡读出数据标志信号 + .rd_data (rd_data ), //sd卡读出数据 + .rd_busy (rd_busy ), //sd卡读数据忙信号 + .rd_en (rd_en ), //sd卡数据读使能信号 + .rd_addr (rd_addr ), //sd卡读数据扇区地址 + .tx_flag (tx_flag ), //读fifo读出数据标志信号 + .tx_data (tx_data ) //读fifo读出数据 +); + +//------------- sd_ctrl_inst ------------- +sd_ctrl sd_ctrl_inst +( + .sys_clk (clk_50m ), //输入工作时钟,频率50MHz + .sys_clk_shift (clk_50m_shift ), //输入工作时钟,频率50MHz,相位偏移180度 + .sys_rst_n (rst_n ), //输入复位信号,低电平有效 + + .sd_miso (sd_miso ), //主输入从输出信号 + .sd_clk (sd_clk ), //SD卡时钟信号 + .sd_cs_n (sd_cs_n ), //片选信号 + .sd_mosi (sd_mosi ), //主输出从输入信号 + + .wr_en (wr_en ), //数据写使能信号 + .wr_addr (wr_addr ), //写数据扇区地址 + .wr_data (wr_data ), //写数据 + .wr_busy (wr_busy ), //写操作忙信号 + .wr_req (wr_req ), //写数据请求信号 + + .rd_en (rd_en ), //数据读使能信号 + .rd_addr (rd_addr ), //读数据扇区地址 + .rd_busy (rd_busy ), //读操作忙信号 + .rd_data_en (rd_data_en ), //读数据标志信号 + .rd_data (rd_data ), //读数据 + + .init_end (init_end ) //SD卡初始化完成信号 +); + +//------------- uart_tx_inst ------------- +uart_tx +#( + .UART_BPS (UART_BPS ), //串口波特率 + .CLK_FREQ (CLK_FREQ ) //时钟频率 +) +uart_tx_inst +( + .sys_clk (clk_50m ), //系统时钟50Mhz + .sys_rst_n (rst_n ), //全局复位 + .pi_data (tx_data ), //并行数据 + .pi_flag (tx_flag ), //并行数据有效标志信号 + + .tx (tx ) //串口发送数据 +); + +endmodule \ No newline at end of file diff --git a/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_tx.v b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_tx.v new file mode 100644 index 0000000..a1e1f2e --- /dev/null +++ b/smh-ac415-fpga/examples/06_uart_sd/uart_sd/rtl/uart_tx.v @@ -0,0 +1,104 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/06/12 +// Module Name : uart_tx +// Project Name : uart_sd +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module uart_tx +#( + parameter UART_BPS = 'd9600, //串口波特率 + parameter CLK_FREQ = 'd50_000_000 //时钟频率 +) +( + input wire sys_clk , //系统时钟50MHz + input wire sys_rst_n , //全局复位 + input wire [7:0] pi_data , //模块输入的8bit数据 + input wire pi_flag , //并行数据有效标志信号 + + output reg tx //串转并后的1bit数据 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//localparam define +localparam BAUD_CNT_MAX = CLK_FREQ/UART_BPS ; + +//reg define +reg [12:0] baud_cnt; +reg bit_flag; +reg [3:0] bit_cnt ; +reg work_en ; + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//work_en:接收数据工作使能信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + work_en <= 1'b0; + else if(pi_flag == 1'b1) + work_en <= 1'b1; + else if((bit_flag == 1'b1) && (bit_cnt == 4'd9)) + work_en <= 1'b0; + +//baud_cnt:波特率计数器计数，从0计数到BAUD_CNT_MAX - 1 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + baud_cnt <= 13'b0; + else if((baud_cnt == BAUD_CNT_MAX - 1) || (work_en == 1'b0)) + baud_cnt <= 13'b0; + else if(work_en == 1'b1) + baud_cnt <= baud_cnt + 1'b1; + +//bit_flag:当baud_cnt计数器计数到1时让bit_flag拉高一个时钟的高电平 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + bit_flag <= 1'b0; + else if(baud_cnt == 13'd1) + bit_flag <= 1'b1; + else + bit_flag <= 1'b0; + +//bit_cnt:数据位数个数计数，10个有效数据（含起始位和停止位）到来后计数器清零 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + bit_cnt <= 4'b0; + else if((bit_flag == 1'b1) && (bit_cnt == 4'd9)) + bit_cnt <= 4'b0; + else if((bit_flag == 1'b1) && (work_en == 1'b1)) + bit_cnt <= bit_cnt + 1'b1; + +//tx:输出数据在满足rs232协议（起始位为0，停止位为1）的情况下一位一位输出 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + tx <= 1'b1; //空闲状态时为高电平 + else if(bit_flag == 1'b1) + case(bit_cnt) + 0 : tx <= 1'b0; + 1 : tx <= pi_data[0]; + 2 : tx <= pi_data[1]; + 3 : tx <= pi_data[2]; + 4 : tx <= pi_data[3]; + 5 : tx <= pi_data[4]; + 6 : tx <= pi_data[5]; + 7 : tx <= pi_data[6]; + 8 : tx <= pi_data[7]; + 9 : tx <= 1'b1; + default : tx <= 1'b1; + endcase + +endmodule diff --git "a/smh-ac415-fpga/examples/06_uart_sd/\345\256\236\351\252\214\347\216\260\350\261\241.txt" "b/smh-ac415-fpga/examples/06_uart_sd/\345\256\236\351\252\214\347\216\260\350\261\241.txt" new file mode 100644 index 0000000..b3c452d --- /dev/null +++ "b/smh-ac415-fpga/examples/06_uart_sd/\345\256\236\351\252\214\347\216\260\350\261\241.txt" @@ -0,0 +1,6 @@ +现象：先把tf卡插入开发板（尽量用sandisk等大牌厂家），把usb插入电脑，预先安装ch340串口驱动，打开某个串口软件，波特率选择9600，接收发送均选择hex，发送框输入下文中512个字节数据，接收框会返回这512字节数据，此中会把这512字节先存入tf卡，在从tf卡读出。此例程参考野火fpga例程修改而来。具体可参考野火教程。 + +测试：可以测试tf卡，串口是否正常。 + + +00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F \ No newline at end of file diff --git "a/smh-ac415-fpga/examples/07_hdmi/hdmi/doc/VESA VGA\346\227\266\345\272\217\346\240\207\345\207\206.pdf" "b/smh-ac415-fpga/examples/07_hdmi/hdmi/doc/VESA VGA\346\227\266\345\272\217\346\240\207\345\207\206.pdf" new file mode 100644 index 0000000..b0b4015 Binary files /dev/null and "b/smh-ac415-fpga/examples/07_hdmi/hdmi/doc/VESA VGA\346\227\266\345\272\217\346\240\207\345\207\206.pdf" differ diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/doc/hdmi_colorbar.vsdx b/smh-ac415-fpga/examples/07_hdmi/hdmi/doc/hdmi_colorbar.vsdx new file mode 100644 index 0000000..4438105 Binary files /dev/null and b/smh-ac415-fpga/examples/07_hdmi/hdmi/doc/hdmi_colorbar.vsdx differ diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/PLLJ_PLLSPE_INFO.txt b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/PLLJ_PLLSPE_INFO.txt new file mode 100644 index 0000000..0aa6c27 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/PLLJ_PLLSPE_INFO.txt @@ -0,0 +1,5 @@ +PLL_Name clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|pll1 +PLLJITTER 35 +PLLSPEmax 84 +PLLSPEmin -53 + diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ddio_out.qip b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ddio_out.qip new file mode 100644 index 0000000..e69de29 diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..0d488fd --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/greybox_tmp/cbx_args.txt @@ -0,0 +1,13 @@ +INTENDED_DEVICE_FAMILY="Cyclone IV E" +INVERT_OUTPUT=OFF +LPM_HINT=UNUSED +LPM_TYPE=altddio_out +POWER_UP_HIGH=OFF +WIDTH=1 +DEVICE_FAMILY="Cyclone IV E" +CBX_AUTO_BLACKBOX=ALL +CBX_AUTO_BLACKBOX=ALL +datain_h +datain_l +dataout +outclock diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/hdmi_colorbar.qpf b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/hdmi_colorbar.qpf new file mode 100644 index 0000000..e0542a7 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/hdmi_colorbar.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 11:19:29 March 05, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "11:19:29 March 05, 2020" + +# Revisions + +PROJECT_REVISION = "hdmi_colorbar" diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/hdmi_colorbar.qsf b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/hdmi_colorbar.qsf new file mode 100644 index 0000000..1bf5998 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/hdmi_colorbar.qsf @@ -0,0 +1,98 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 11:19:29 March 05, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# hdmi_colorbar_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE15F23C8 +set_global_assignment -name TOP_LEVEL_ENTITY hdmi_colorbar +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:19:29 MARCH 05, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +set_location_assignment PIN_T22 -to sys_clk +set_location_assignment PIN_U20 -to sys_rst_n + +set_location_assignment PIN_H22 -to tmds_clk_n +set_location_assignment PIN_H21 -to tmds_clk_p +set_location_assignment PIN_D22 -to tmds_data_n[2] +set_location_assignment PIN_E22 -to tmds_data_n[1] +set_location_assignment PIN_F22 -to tmds_data_n[0] +set_location_assignment PIN_D21 -to tmds_data_p[2] +set_location_assignment PIN_E21 -to tmds_data_p[1] +set_location_assignment PIN_F21 -to tmds_data_p[0] + +set_location_assignment PIN_N22 -to ddc_scl +set_location_assignment PIN_R22 -to ddc_sda + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb_hdmi_colorbar -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME tb_hdmi_colorbar -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_hdmi_colorbar +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_hdmi_colorbar +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_hdmi_colorbar -section_id tb_hdmi_colorbar +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_hdmi_colorbar.v -section_id tb_hdmi_colorbar +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name VERILOG_FILE ../sim/tb_hdmi_colorbar.v +set_global_assignment -name VERILOG_FILE ../rtl/hdmi/encode.v +set_global_assignment -name VERILOG_FILE ../rtl/hdmi/par_to_ser.v +set_global_assignment -name VERILOG_FILE ../rtl/hdmi/hdmi_ctrl.v +set_global_assignment -name VERILOG_FILE ../rtl/vga_pic.v +set_global_assignment -name VERILOG_FILE ../rtl/vga_ctrl.v +set_global_assignment -name VERILOG_FILE ../rtl/hdmi_colorbar.v +set_global_assignment -name QIP_FILE ip_core/ddio_out/ddio_out.qip +set_global_assignment -name QIP_FILE ip_core/clk_gen/clk_gen.qip +set_global_assignment -name CDF_FILE output_files/Chain1.cdf +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/hdmi_colorbar.qws b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/hdmi_colorbar.qws new file mode 100644 index 0000000..27fd4ea Binary files /dev/null and b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/hdmi_colorbar.qws differ diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/hdmi_colorbar_assignment_defaults.qdf b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/hdmi_colorbar_assignment_defaults.qdf new file mode 100644 index 0000000..020bb6d --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/hdmi_colorbar_assignment_defaults.qdf @@ -0,0 +1,805 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 04:08:48 June 02, 2023 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus II software and is used +# to preserve global assignments across Quartus II versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name SMART_RECOMPILE Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name DISABLE_OCP_HW_EVAL Off +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone IV GX" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria VI" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix VI" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix VI" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Cyclone +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy III" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "HardCopy IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria VI" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Arria GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Stratix +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria VI" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix VI" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name SYNTHESIS_SEED 1 +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria VI" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix VI" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000B +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix VI" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000AE +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Cyclone +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000S +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy III" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Arria VI" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX3000A +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Stratix +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto +set_global_assignment -name AUTO_PACKED_REGISTERS Off +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO +set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix VI" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "HardCopy III" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria VI" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria VI" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix VI" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen.ppf b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen.ppf new file mode 100644 index 0000000..a0d0ea9 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen.qip b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen.qip new file mode 100644 index 0000000..ec92e56 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clk_gen.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen.ppf"] diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen.v b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen.v new file mode 100644 index 0000000..e76f314 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen.v @@ -0,0 +1,348 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module clk_gen ( + areset, + inclk0, + c0, + c1, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire5), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 2, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 1, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 2, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 5, + altpll_component.clk1_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Cyclone IV E", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clk_gen", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "125.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen_bb.v b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen_bb.v new file mode 100644 index 0000000..588471a --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen_bb.v @@ -0,0 +1,232 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module clk_gen ( + areset, + inclk0, + c0, + c1, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "125.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen_inst.v b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen_inst.v new file mode 100644 index 0000000..bad6ce7 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen_inst.v @@ -0,0 +1,7 @@ +clk_gen clk_gen_inst ( + .areset ( areset_sig ), + .inclk0 ( inclk0_sig ), + .c0 ( c0_sig ), + .c1 ( c1_sig ), + .locked ( locked_sig ) + ); diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..f6a28fe --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt @@ -0,0 +1,61 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=2 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=1 +CLK0_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=20000 +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_USED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_USED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_UNUSED +PORT_clk2=PORT_UNUSED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +SELF_RESET_ON_LOSS_LOCK=OFF +WIDTH_CLOCK=5 +DEVICE_FAMILY="Cyclone IV E" +CBX_AUTO_BLACKBOX=ALL +areset +inclk +inclk +clk +locked diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/clk_gen.qip b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/clk_gen.qip new file mode 100644 index 0000000..e69de29 diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.bsf b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.bsf new file mode 100644 index 0000000..a1a9664 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.bsf @@ -0,0 +1,64 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 192 112) + (text "ddio_out" (rect 72 -1 129 15)(font "Arial" (font_size 10))) + (text "inst" (rect 8 96 25 108)(font "Arial" )) + (port + (pt 0 48) + (input) + (text "datain_h[0]" (rect 0 0 62 14)(font "Arial" (font_size 8))) + (text "datain_h[0]" (rect 4 34 55 47)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 64 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "datain_l[0]" (rect 0 0 57 14)(font "Arial" (font_size 8))) + (text "datain_l[0]" (rect 4 50 51 63)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 64 64)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 66 42 79)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 64 80)) + ) + (port + (pt 192 48) + (output) + (text "dataout[0]" (rect 0 0 56 14)(font "Arial" (font_size 8))) + (text "dataout[0]" (rect 141 34 187 47)(font "Arial" (font_size 8))) + (line (pt 192 48)(pt 128 48)(line_width 3)) + ) + (drawing + (line (pt 64 32)(pt 128 32)) + (line (pt 128 32)(pt 128 96)) + (line (pt 64 96)(pt 128 96)) + (line (pt 64 32)(pt 64 96)) + (line (pt 0 0)(pt 192 0)) + (line (pt 192 0)(pt 192 112)) + (line (pt 0 112)(pt 192 112)) + (line (pt 0 0)(pt 0 112)) + ) +) diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.cmp b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.cmp new file mode 100644 index 0000000..8334a29 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component ddio_out + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0); + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) + ); +end component; diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.inc b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.inc new file mode 100644 index 0000000..fa5e50d --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.inc @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION ddio_out +( + datain_h[0..0], + datain_l[0..0], + outclock +) + +RETURNS ( + dataout[0..0] +); diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.ppf b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.ppf new file mode 100644 index 0000000..2eecd59 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.qip b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.qip new file mode 100644 index 0000000..6084731 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.qip @@ -0,0 +1,9 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ddio_out.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddio_out.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddio_out_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddio_out_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddio_out.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddio_out.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ddio_out.ppf"] diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.v b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.v new file mode 100644 index 0000000..5758d48 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.v @@ -0,0 +1,107 @@ +// megafunction wizard: %ALTDDIO_OUT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_OUT + +// ============================================================ +// File Name: ddio_out.v +// Megafunction Name(s): +// ALTDDIO_OUT +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module ddio_out ( + datain_h, + datain_l, + outclock, + dataout); + + input [0:0] datain_h; + input [0:0] datain_l; + input outclock; + output [0:0] dataout; + + wire [0:0] sub_wire0; + wire [0:0] dataout = sub_wire0[0:0]; + + altddio_out ALTDDIO_OUT_component ( + .datain_h (datain_h), + .datain_l (datain_l), + .outclock (outclock), + .dataout (sub_wire0), + .aclr (1'b0), + .aset (1'b0), + .oe (1'b1), + .oe_out (), + .outclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_OUT_component.extend_oe_disable = "OFF", + ALTDDIO_OUT_component.intended_device_family = "Cyclone IV E", + ALTDDIO_OUT_component.invert_output = "OFF", + ALTDDIO_OUT_component.lpm_hint = "UNUSED", + ALTDDIO_OUT_component.lpm_type = "altddio_out", + ALTDDIO_OUT_component.oe_reg = "UNREGISTERED", + ALTDDIO_OUT_component.power_up_high = "OFF", + ALTDDIO_OUT_component.width = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "1" +// Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]" +// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0 +// Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]" +// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0 +// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]" +// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.ppf TRUE FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out_bb.v b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out_bb.v new file mode 100644 index 0000000..52b2bf0 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out_bb.v @@ -0,0 +1,76 @@ +// megafunction wizard: %ALTDDIO_OUT%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_OUT + +// ============================================================ +// File Name: ddio_out.v +// Megafunction Name(s): +// ALTDDIO_OUT +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module ddio_out ( + datain_h, + datain_l, + outclock, + dataout); + + input [0:0] datain_h; + input [0:0] datain_l; + input outclock; + output [0:0] dataout; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "1" +// Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]" +// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0 +// Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]" +// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0 +// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]" +// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.bsf TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_bb.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.inc TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.cmp TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.ppf TRUE FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out_inst.v b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out_inst.v new file mode 100644 index 0000000..99572eb --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out_inst.v @@ -0,0 +1,7 @@ +ddio_out ddio_out_inst +( + .datain_h ( datain_h_sig ), + .datain_l ( datain_l_sig ), + .outclock ( outclock_sig ), + .dataout ( dataout_sig ) +); diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..19abf30 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/greybox_tmp/cbx_args.txt @@ -0,0 +1,66 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=2 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=1 +CLK0_PHASE_SHIFT=0 +CLK1_DIVIDE_BY=1 +CLK1_DUTY_CYCLE=50 +CLK1_MULTIPLY_BY=13 +CLK1_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=20000 +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_USED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_USED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_USED +PORT_clk2=PORT_UNUSED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +SELF_RESET_ON_LOSS_LOCK=OFF +WIDTH_CLOCK=5 +DEVICE_FAMILY="Cyclone IV E" +CBX_AUTO_BLACKBOX=ALL +areset +inclk +inclk +clk +clk +locked diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/pll.qip b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/pll.qip new file mode 100644 index 0000000..e69de29 diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar.sft b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar.sft new file mode 100644 index 0000000..fc8984c --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar.sft @@ -0,0 +1,6 @@ +set tool_name "ModelSim (Verilog)" +set corner_file_list { + {{"Slow -8 1.2V 85 Model"} {hdmi_colorbar_8_1200mv_85c_slow.vo hdmi_colorbar_8_1200mv_85c_v_slow.sdo}} + {{"Slow -8 1.2V 0 Model"} {hdmi_colorbar_8_1200mv_0c_slow.vo hdmi_colorbar_8_1200mv_0c_v_slow.sdo}} + {{"Fast -M 1.2V 0 Model"} {hdmi_colorbar_min_1200mv_0c_fast.vo hdmi_colorbar_min_1200mv_0c_v_fast.sdo}} +} diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar.vo b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar.vo new file mode 100644 index 0000000..cb63408 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar.vo @@ -0,0 +1,11443 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:17:19" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module hdmi_colorbar ( + sys_clk, + sys_rst_n, + ddc_scl, + ddc_sda, + tmds_clk_p, + tmds_clk_n, + tmds_data_p, + tmds_data_n); +input sys_clk; +input sys_rst_n; +output ddc_scl; +output ddc_sda; +output tmds_clk_p; +output tmds_clk_n; +output [2:0] tmds_data_p; +output [2:0] tmds_data_n; + +// Design Ports Information +// ddc_scl => Location: PIN_N22, I/O Standard: 2.5 V, Current Strength: Default +// ddc_sda => Location: PIN_R22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_clk_p => Location: PIN_H21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_clk_n => Location: PIN_H22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_p[0] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_p[1] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_p[2] => Location: PIN_D21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_n[0] => Location: PIN_F22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_n[1] => Location: PIN_E22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_n[2] => Location: PIN_D22, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("hdmi_colorbar_v.sdo"); +// synopsys translate_on + +wire \hdmi_ctrl_inst|encode_inst0|Add20~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~7 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~8_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~7 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~8_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~7 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~7 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~7 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~8_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~6_combout ; +wire \vga_ctrl_inst|Add0~2_combout ; +wire \vga_ctrl_inst|Add0~10_combout ; +wire \vga_ctrl_inst|Add1~2_combout ; +wire \vga_ctrl_inst|Add1~6_combout ; +wire \vga_ctrl_inst|Add1~8_combout ; +wire \vga_ctrl_inst|Add1~10_combout ; +wire \vga_ctrl_inst|Add1~12_combout ; +wire \vga_ctrl_inst|Add1~14_combout ; +wire \vga_ctrl_inst|Add1~16_combout ; +wire \vga_ctrl_inst|Add1~18_combout ; +wire \vga_ctrl_inst|Add1~20_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|condition_3~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_3~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~3_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~5_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~7_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~8_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~11_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~12_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~16_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add12~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~5_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~7_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~13_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~14_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~16_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~3_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~9_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~10_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~11_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~12_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~13_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~16_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add14~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~3_combout ; +wire \vga_ctrl_inst|pix_data_req~0_combout ; +wire \vga_ctrl_inst|pix_data_req~3_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~5_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~5_combout ; +wire \vga_ctrl_inst|pix_x[10]~1_combout ; +wire \vga_pic_inst|always0~1_combout ; +wire \vga_pic_inst|always0~2_combout ; +wire \vga_pic_inst|pix_data[9]~14_combout ; +wire \vga_pic_inst|pix_data~16_combout ; +wire \vga_ctrl_inst|pix_data_req~8_combout ; +wire \vga_ctrl_inst|cnt_v[10]~12_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout ; +wire \vga_pic_inst|LessThan10~0_combout ; +wire \vga_pic_inst|pix_data~22_combout ; +wire \vga_pic_inst|pix_data~23_combout ; +wire \vga_pic_inst|LessThan14~1_combout ; +wire \vga_pic_inst|pix_data[13]~24_combout ; +wire \vga_pic_inst|pix_data~25_combout ; +wire \hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~5_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~8_combout ; +wire \vga_pic_inst|pix_data~37_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~1 ; +wire \vga_ctrl_inst|Add0~3 ; +wire \vga_ctrl_inst|Add0~5 ; +wire \vga_ctrl_inst|Add0~6_combout ; +wire \vga_ctrl_inst|Add0~7 ; +wire \vga_ctrl_inst|Add0~8_combout ; +wire \vga_ctrl_inst|Add0~9 ; +wire \vga_ctrl_inst|Add0~11 ; +wire \vga_ctrl_inst|Add0~12_combout ; +wire \vga_ctrl_inst|Add0~13 ; +wire \vga_ctrl_inst|Add0~14_combout ; +wire \vga_ctrl_inst|Add0~4_combout ; +wire \vga_ctrl_inst|Equal0~0_combout ; +wire \vga_ctrl_inst|Add0~15 ; +wire \vga_ctrl_inst|Add0~16_combout ; +wire \vga_ctrl_inst|Add0~19 ; +wire \vga_ctrl_inst|Add0~20_combout ; +wire \vga_ctrl_inst|Add0~21 ; +wire \vga_ctrl_inst|Add0~22_combout ; +wire \vga_ctrl_inst|Equal0~1_combout ; +wire \vga_ctrl_inst|cnt_h~0_combout ; +wire \vga_ctrl_inst|Equal0~2_combout ; +wire \vga_ctrl_inst|cnt_h~2_combout ; +wire \vga_ctrl_inst|Add0~17 ; +wire \vga_ctrl_inst|Add0~18_combout ; +wire \vga_ctrl_inst|cnt_h~1_combout ; +wire \vga_ctrl_inst|LessThan4~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ; +wire \vga_ctrl_inst|Add2~1_cout ; +wire \vga_ctrl_inst|Add2~3_cout ; +wire \vga_ctrl_inst|Add2~5_cout ; +wire \vga_ctrl_inst|Add2~7_cout ; +wire \vga_ctrl_inst|Add2~9_cout ; +wire \vga_ctrl_inst|Add2~11 ; +wire \vga_ctrl_inst|Add2~13 ; +wire \vga_ctrl_inst|Add2~15 ; +wire \vga_ctrl_inst|Add2~17 ; +wire \vga_ctrl_inst|Add2~18_combout ; +wire \vga_ctrl_inst|Add2~16_combout ; +wire \vga_ctrl_inst|Add2~14_combout ; +wire \vga_pic_inst|pix_data~12_combout ; +wire \vga_ctrl_inst|Add2~12_combout ; +wire \vga_ctrl_inst|pix_data_req~5_combout ; +wire \vga_ctrl_inst|Equal0~3_combout ; +wire \vga_ctrl_inst|cnt_v[7]~7_combout ; +wire \vga_ctrl_inst|cnt_v[5]~10_combout ; +wire \vga_ctrl_inst|cnt_v[8]~6_combout ; +wire \vga_ctrl_inst|always1~0_combout ; +wire \vga_ctrl_inst|cnt_v[1]~1_combout ; +wire \vga_ctrl_inst|cnt_v[4]~5_combout ; +wire \vga_ctrl_inst|always1~1_combout ; +wire \vga_ctrl_inst|Add1~0_combout ; +wire \vga_ctrl_inst|cnt_v[0]~2_combout ; +wire \vga_ctrl_inst|cnt_v[3]~3_combout ; +wire \vga_ctrl_inst|always1~2_combout ; +wire \vga_ctrl_inst|cnt_v[11]~0_combout ; +wire \vga_ctrl_inst|cnt_v[9]~9_combout ; +wire \vga_ctrl_inst|cnt_v[6]~8_combout ; +wire \vga_ctrl_inst|Add1~1 ; +wire \vga_ctrl_inst|Add1~3 ; +wire \vga_ctrl_inst|Add1~4_combout ; +wire \vga_ctrl_inst|cnt_v[2]~4_combout ; +wire \vga_ctrl_inst|Add1~5 ; +wire \vga_ctrl_inst|Add1~7 ; +wire \vga_ctrl_inst|Add1~9 ; +wire \vga_ctrl_inst|Add1~11 ; +wire \vga_ctrl_inst|Add1~13 ; +wire \vga_ctrl_inst|Add1~15 ; +wire \vga_ctrl_inst|Add1~17 ; +wire \vga_ctrl_inst|Add1~19 ; +wire \vga_ctrl_inst|Add1~21 ; +wire \vga_ctrl_inst|Add1~22_combout ; +wire \vga_ctrl_inst|cnt_v[11]~11_combout ; +wire \vga_ctrl_inst|pix_data_req~2_combout ; +wire \vga_ctrl_inst|pix_data_req~4_combout ; +wire \vga_ctrl_inst|pix_data_req~6_combout ; +wire \vga_ctrl_inst|pix_data_req~7_combout ; +wire \vga_pic_inst|pix_data[13]~11_combout ; +wire \vga_pic_inst|always0~0_combout ; +wire \vga_pic_inst|pix_data~13_combout ; +wire \vga_pic_inst|pix_data~17_combout ; +wire \vga_pic_inst|pix_data~34_combout ; +wire \vga_pic_inst|pix_data[13]~8_combout ; +wire \vga_pic_inst|pix_data[13]~9_combout ; +wire \vga_pic_inst|pix_data[13]~10_combout ; +wire \vga_pic_inst|pix_data~18_combout ; +wire \vga_ctrl_inst|Add2~19 ; +wire \vga_ctrl_inst|Add2~20_combout ; +wire \vga_ctrl_inst|Add2~10_combout ; +wire \vga_pic_inst|LessThan17~4_combout ; +wire \vga_pic_inst|LessThan17~3_combout ; +wire \vga_pic_inst|LessThan14~0_combout ; +wire \vga_pic_inst|pix_data~19_combout ; +wire \vga_pic_inst|pix_data~20_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add6~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout ; +wire \vga_ctrl_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|pix_data_req~1_combout ; +wire \vga_ctrl_inst|rgb[1]~0_combout ; +wire \vga_ctrl_inst|rgb[2]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add14~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~9_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~10_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add12~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add14~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~13_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~14_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~15_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal2~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add4~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|de_reg1~q ; +wire \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|de_reg2~q ; +wire \hdmi_ctrl_inst|encode_inst0|condition_2~combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[3]~14 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout ; +wire \hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout ; +wire \vga_ctrl_inst|LessThan0~0_combout ; +wire \vga_ctrl_inst|LessThan0~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c0_reg1~q ; +wire \hdmi_ctrl_inst|encode_inst2|c0_reg2~q ; +wire \hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout ; +wire \vga_ctrl_inst|LessThan1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c1_reg1~q ; +wire \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c1_reg2~q ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~7_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout ; +wire \vga_pic_inst|LessThan17~2_combout ; +wire \vga_pic_inst|pix_data[9]~15_combout ; +wire \vga_pic_inst|pix_data~35_combout ; +wire \vga_pic_inst|pix_data~36_combout ; +wire \vga_pic_inst|pix_data~21_combout ; +wire \vga_pic_inst|pix_data~26_combout ; +wire \vga_ctrl_inst|pix_x[11]~0_combout ; +wire \vga_pic_inst|pix_data~27_combout ; +wire \vga_ctrl_inst|rgb[10]~2_combout ; +wire \vga_pic_inst|pix_data~29_combout ; +wire \vga_pic_inst|pix_data~30_combout ; +wire \vga_pic_inst|pix_data~31_combout ; +wire \vga_ctrl_inst|rgb[6]~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add5~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add14~1_combout ; +wire \vga_pic_inst|pix_data~28_combout ; +wire \vga_ctrl_inst|rgb[7]~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add13~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add13~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_3~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add14~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add14~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~9_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~10_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~15_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal1~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_2~combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~11_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~12_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[3]~14 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~7_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout ; +wire \vga_pic_inst|pix_data~33_combout ; +wire \vga_ctrl_inst|rgb[13]~6_combout ; +wire \vga_pic_inst|pix_data~32_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add6~0_combout ; +wire \vga_ctrl_inst|rgb[12]~5_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add12~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add14~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add12~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~5_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal1~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~15_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_2~combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~14_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~7_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~8_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~7 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~8_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[3]~14 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~7_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout ; +wire [9:0] \hdmi_ctrl_inst|encode_inst0|data_out ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [11:0] \vga_ctrl_inst|cnt_v ; +wire [11:0] \vga_ctrl_inst|cnt_h ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s ; +wire [7:0] \hdmi_ctrl_inst|encode_inst0|data_in_reg ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [8:0] \hdmi_ctrl_inst|encode_inst0|q_m_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst0|q_m_n1 ; +wire [15:0] \vga_pic_inst|pix_data ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [3:0] \hdmi_ctrl_inst|encode_inst0|data_in_n1 ; +wire [2:0] \hdmi_ctrl_inst|par_to_ser_inst0|cnt ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [3:0] \hdmi_ctrl_inst|encode_inst0|q_m_n0 ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [4:0] \hdmi_ctrl_inst|encode_inst0|cnt ; +wire [4:0] \hdmi_ctrl_inst|encode_inst1|cnt ; +wire [9:0] \hdmi_ctrl_inst|encode_inst1|data_out ; +wire [8:0] \hdmi_ctrl_inst|encode_inst1|q_m_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst1|q_m_n0 ; +wire [3:0] \hdmi_ctrl_inst|encode_inst1|q_m_n1 ; +wire [7:0] \hdmi_ctrl_inst|encode_inst1|data_in_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst1|data_in_n1 ; +wire [4:0] \hdmi_ctrl_inst|encode_inst2|cnt ; +wire [9:0] \hdmi_ctrl_inst|encode_inst2|data_out ; +wire [8:0] \hdmi_ctrl_inst|encode_inst2|q_m_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst2|q_m_n0 ; +wire [3:0] \hdmi_ctrl_inst|encode_inst2|q_m_n1 ; +wire [7:0] \hdmi_ctrl_inst|encode_inst2|data_in_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst2|data_in_n1 ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 10; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 10; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 5; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 10; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 6891; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 250; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: FF_X40_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N7 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N9 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y22_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y23_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y23_N13 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((GND) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add20~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add20~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~0 .lut_mask = 16'h66BB; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst0|Add20~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// ((\hdmi_ctrl_inst|encode_inst0|Add20~1 ) # (GND))))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|Add20~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst0|Add20~1 )))) +// \hdmi_ctrl_inst|encode_inst0|Add20~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((!\hdmi_ctrl_inst|encode_inst0|Add20~1 ) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst0|Add20~1 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add20~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add20~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~2 .lut_mask = 16'h692B; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~4_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst0|Add20~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst0|Add20~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add20~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst0|Add20~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add20~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add20~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~6_combout = !\hdmi_ctrl_inst|encode_inst0|Add20~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add20~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add17~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [0] & \hdmi_ctrl_inst|encode_inst0|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|Add17~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst0|Add17~1 )))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (!\hdmi_ctrl_inst|encode_inst0|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & ((\hdmi_ctrl_inst|encode_inst0|Add17~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|Add17~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & !\hdmi_ctrl_inst|encode_inst0|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & +// ((!\hdmi_ctrl_inst|encode_inst0|Add17~1 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~4_combout = ((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] $ (\hdmi_ctrl_inst|encode_inst0|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst0|Add17~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|Add17~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst0|Add17~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst0|Add17~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~6_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [3] & (!\hdmi_ctrl_inst|encode_inst0|Add17~5 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & ((\hdmi_ctrl_inst|encode_inst0|Add17~5 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add17~7 = CARRY((!\hdmi_ctrl_inst|encode_inst0|Add17~5 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~6 .lut_mask = 16'h3C3F; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~8_combout = \hdmi_ctrl_inst|encode_inst0|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst0|Add17~7 ) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~7 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~8 .lut_mask = 16'hC3C3; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]) # (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add23~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add23~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~0 .lut_mask = 16'h66DD; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst0|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// (\hdmi_ctrl_inst|encode_inst0|Add23~1 & VCC)))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst0|Add23~1 ) # (GND))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst0|Add23~1 )))) +// \hdmi_ctrl_inst|encode_inst0|Add23~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst0|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & +// ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst0|Add23~1 )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add23~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add23~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~2 .lut_mask = 16'h694D; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~4_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst0|Add23~3 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst0|Add23~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add23~5 = CARRY((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst0|Add23~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add23~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add23~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~4 .lut_mask = 16'h5A05; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~6_combout = !\hdmi_ctrl_inst|encode_inst0|Add23~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add23~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add15~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [0] & \hdmi_ctrl_inst|encode_inst0|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|Add15~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst0|Add15~1 )))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (!\hdmi_ctrl_inst|encode_inst0|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & ((\hdmi_ctrl_inst|encode_inst0|Add15~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|Add15~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & !\hdmi_ctrl_inst|encode_inst0|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & +// ((!\hdmi_ctrl_inst|encode_inst0|Add15~1 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~4_combout = ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] $ (\hdmi_ctrl_inst|encode_inst0|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst0|Add15~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|Add15~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst0|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst0|Add15~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst0|Add15~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~6_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|cnt [3] & (\hdmi_ctrl_inst|encode_inst0|Add15~5 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & +// (!\hdmi_ctrl_inst|encode_inst0|Add15~5 )))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|cnt [3] & (!\hdmi_ctrl_inst|encode_inst0|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & ((\hdmi_ctrl_inst|encode_inst0|Add15~5 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|Add15~7 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & !\hdmi_ctrl_inst|encode_inst0|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & +// ((!\hdmi_ctrl_inst|encode_inst0|Add15~5 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~6 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~8_combout = \hdmi_ctrl_inst|encode_inst0|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst0|Add15~7 ) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~7 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~8 .lut_mask = 16'hC3C3; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~4_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [3] & (\hdmi_ctrl_inst|encode_inst0|Add19~3 $ (GND))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & (!\hdmi_ctrl_inst|encode_inst0|Add19~3 & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add19~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [3] & !\hdmi_ctrl_inst|encode_inst0|Add19~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add19~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add19~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~4 .lut_mask = 16'hA50A; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~4_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst0|Add22~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & (\hdmi_ctrl_inst|encode_inst0|Add22~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add22~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [3]) # (!\hdmi_ctrl_inst|encode_inst0|Add22~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add22~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add22~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[0]~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & (\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & +// (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & +// ((\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|cnt[0]~8 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & +// ((!\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ) # (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~16_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~15_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~7 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[1]~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout = ((\hdmi_ctrl_inst|encode_inst0|Add16~12_combout $ (\hdmi_ctrl_inst|encode_inst0|Add16~14_combout $ (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|cnt[1]~10 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~12_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~14_combout ) # (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~12_combout & +// (\hdmi_ctrl_inst|encode_inst0|Add16~14_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~12_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1]~9 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[2]~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & (\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & +// (!\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & (!\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & +// ((\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|cnt[2]~12 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & +// ((!\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ) # (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2]~11 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y22_N31 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((GND) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add20~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add20~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~0 .lut_mask = 16'h66BB; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|Add20~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// ((\hdmi_ctrl_inst|encode_inst1|Add20~1 ) # (GND))))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|Add20~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst1|Add20~1 )))) +// \hdmi_ctrl_inst|encode_inst1|Add20~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((!\hdmi_ctrl_inst|encode_inst1|Add20~1 ) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst1|Add20~1 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add20~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add20~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~2 .lut_mask = 16'h692B; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~4_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst1|Add20~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst1|Add20~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add20~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst1|Add20~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add20~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add20~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~4 .lut_mask = 16'h3CCF; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~6_combout = !\hdmi_ctrl_inst|encode_inst1|Add20~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add20~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~0_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add17~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [0] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~2_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst1|Add17~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & +// (!\hdmi_ctrl_inst|encode_inst1|Add17~1 )))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst1|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & +// ((\hdmi_ctrl_inst|encode_inst1|Add17~1 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|Add17~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [1] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst1|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((!\hdmi_ctrl_inst|encode_inst1|Add17~1 ) +// # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~4_combout = ((\hdmi_ctrl_inst|encode_inst1|cnt [2] $ (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] $ (!\hdmi_ctrl_inst|encode_inst1|Add17~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|Add17~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]) # (!\hdmi_ctrl_inst|encode_inst1|Add17~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 +// [2] & !\hdmi_ctrl_inst|encode_inst1|Add17~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~6_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & (!\hdmi_ctrl_inst|encode_inst1|Add17~5 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|Add17~5 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add17~7 = CARRY((!\hdmi_ctrl_inst|encode_inst1|Add17~5 ) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~6 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~8_combout = \hdmi_ctrl_inst|encode_inst1|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst1|Add17~7 ) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~7 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~8 .lut_mask = 16'hA5A5; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]) # (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add23~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add23~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~0 .lut_mask = 16'h66DD; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~4_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst1|Add23~3 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst1|Add23~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add23~5 = CARRY((!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst1|Add23~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add23~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add23~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~4 .lut_mask = 16'h3C03; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~6_combout = !\hdmi_ctrl_inst|encode_inst1|Add23~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add23~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst1|cnt [1] & (\hdmi_ctrl_inst|encode_inst1|Add15~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst1|Add15~1 )))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst1|cnt [1] & (!\hdmi_ctrl_inst|encode_inst1|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((\hdmi_ctrl_inst|encode_inst1|Add15~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|Add15~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & !\hdmi_ctrl_inst|encode_inst1|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & +// ((!\hdmi_ctrl_inst|encode_inst1|Add15~1 ) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~6_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst1|Add15~5 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & +// (!\hdmi_ctrl_inst|encode_inst1|Add15~5 )))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst1|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & +// ((\hdmi_ctrl_inst|encode_inst1|Add15~5 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|Add15~7 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [3] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst1|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((!\hdmi_ctrl_inst|encode_inst1|Add15~5 ) +// # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~6 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~8_combout = \hdmi_ctrl_inst|encode_inst1|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst1|Add15~7 ) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~7 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~8 .lut_mask = 16'hA5A5; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|cnt [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|cnt [1] & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add19~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & \hdmi_ctrl_inst|encode_inst1|cnt [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add19~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~2_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [2] & (!\hdmi_ctrl_inst|encode_inst1|Add19~1 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & ((\hdmi_ctrl_inst|encode_inst1|Add19~1 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add19~3 = CARRY((!\hdmi_ctrl_inst|encode_inst1|Add19~1 ) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add19~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add19~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~2 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~4_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & (\hdmi_ctrl_inst|encode_inst1|Add19~3 $ (GND))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & (!\hdmi_ctrl_inst|encode_inst1|Add19~3 & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add19~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [3] & !\hdmi_ctrl_inst|encode_inst1|Add19~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add19~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add19~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~4 .lut_mask = 16'hA50A; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~6_combout = \hdmi_ctrl_inst|encode_inst1|Add19~5 $ (\hdmi_ctrl_inst|encode_inst1|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst1|Add19~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~6 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & ((\hdmi_ctrl_inst|encode_inst1|cnt [1]) # (GND))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|cnt [1] $ (VCC))) +// \hdmi_ctrl_inst|encode_inst1|Add22~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]) # (\hdmi_ctrl_inst|encode_inst1|cnt [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add22~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~0 .lut_mask = 16'h99EE; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~2_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|Add22~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & (!\hdmi_ctrl_inst|encode_inst1|Add22~1 )) +// \hdmi_ctrl_inst|encode_inst1|Add22~3 = CARRY((!\hdmi_ctrl_inst|encode_inst1|cnt [2] & !\hdmi_ctrl_inst|encode_inst1|Add22~1 )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add22~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add22~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~2 .lut_mask = 16'hA505; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~4_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst1|Add22~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & (\hdmi_ctrl_inst|encode_inst1|Add22~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add22~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [3]) # (!\hdmi_ctrl_inst|encode_inst1|Add22~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add22~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add22~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y23_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((GND) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add20~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add20~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~0 .lut_mask = 16'h66BB; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~4_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst2|Add20~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst2|Add20~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add20~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst2|Add20~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add20~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add20~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~4 .lut_mask = 16'h3CCF; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~0_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [0] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [0] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add17~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [0] & \hdmi_ctrl_inst|encode_inst2|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|Add17~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst2|Add17~1 )))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (!\hdmi_ctrl_inst|encode_inst2|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & ((\hdmi_ctrl_inst|encode_inst2|Add17~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|Add17~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & !\hdmi_ctrl_inst|encode_inst2|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & +// ((!\hdmi_ctrl_inst|encode_inst2|Add17~1 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~4_combout = ((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] $ (\hdmi_ctrl_inst|encode_inst2|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst2|Add17~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|Add17~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst2|Add17~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst2|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst2|Add17~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~6_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [3] & (!\hdmi_ctrl_inst|encode_inst2|Add17~5 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & ((\hdmi_ctrl_inst|encode_inst2|Add17~5 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add17~7 = CARRY((!\hdmi_ctrl_inst|encode_inst2|Add17~5 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~6 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]) # (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add23~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add23~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~0 .lut_mask = 16'h66DD; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~4_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst2|Add23~3 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst2|Add23~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add23~5 = CARRY((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst2|Add23~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add23~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add23~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~4 .lut_mask = 16'h3C03; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|Add15~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst2|Add15~1 )))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (!\hdmi_ctrl_inst|encode_inst2|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & ((\hdmi_ctrl_inst|encode_inst2|Add15~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|Add15~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & !\hdmi_ctrl_inst|encode_inst2|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & +// ((!\hdmi_ctrl_inst|encode_inst2|Add15~1 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~4_combout = ((\hdmi_ctrl_inst|encode_inst2|cnt [2] $ (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] $ (!\hdmi_ctrl_inst|encode_inst2|Add15~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|Add15~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst2|Add15~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 +// [2] & !\hdmi_ctrl_inst|encode_inst2|Add15~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~6_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst2|cnt [3] & (\hdmi_ctrl_inst|encode_inst2|Add15~5 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & +// (!\hdmi_ctrl_inst|encode_inst2|Add15~5 )))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst2|cnt [3] & (!\hdmi_ctrl_inst|encode_inst2|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & ((\hdmi_ctrl_inst|encode_inst2|Add15~5 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|Add15~7 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & !\hdmi_ctrl_inst|encode_inst2|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & +// ((!\hdmi_ctrl_inst|encode_inst2|Add15~5 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~6 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~8_combout = \hdmi_ctrl_inst|encode_inst2|Add15~7 $ (!\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~7 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~8 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~2_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [2] & (!\hdmi_ctrl_inst|encode_inst2|Add19~1 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2] & ((\hdmi_ctrl_inst|encode_inst2|Add19~1 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add19~3 = CARRY((!\hdmi_ctrl_inst|encode_inst2|Add19~1 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add19~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add19~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~2 .lut_mask = 16'h3C3F; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~4_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [3] & (\hdmi_ctrl_inst|encode_inst2|Add19~3 $ (GND))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & (!\hdmi_ctrl_inst|encode_inst2|Add19~3 & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add19~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [3] & !\hdmi_ctrl_inst|encode_inst2|Add19~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add19~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add19~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~4 .lut_mask = 16'hA50A; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~6_combout = \hdmi_ctrl_inst|encode_inst2|Add19~5 $ (\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add19~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~6 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~0_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [1] & ((\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]) # (GND))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] $ (VCC))) +// \hdmi_ctrl_inst|encode_inst2|Add22~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [1]) # (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add22~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~0 .lut_mask = 16'h99EE; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~2_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|Add22~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2] & (!\hdmi_ctrl_inst|encode_inst2|Add22~1 )) +// \hdmi_ctrl_inst|encode_inst2|Add22~3 = CARRY((!\hdmi_ctrl_inst|encode_inst2|cnt [2] & !\hdmi_ctrl_inst|encode_inst2|Add22~1 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add22~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add22~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~2 .lut_mask = 16'hC303; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~4_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst2|Add22~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & (\hdmi_ctrl_inst|encode_inst2|Add22~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add22~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [3]) # (!\hdmi_ctrl_inst|encode_inst2|Add22~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add22~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add22~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~6_combout = \hdmi_ctrl_inst|encode_inst2|Add22~5 $ (!\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add22~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~6 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y24_N11 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y22_N19 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [6]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y21_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [7]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~2 ( +// Equation(s): +// \vga_ctrl_inst|Add0~2_combout = (\vga_ctrl_inst|cnt_h [1] & (!\vga_ctrl_inst|Add0~1 )) # (!\vga_ctrl_inst|cnt_h [1] & ((\vga_ctrl_inst|Add0~1 ) # (GND))) +// \vga_ctrl_inst|Add0~3 = CARRY((!\vga_ctrl_inst|Add0~1 ) # (!\vga_ctrl_inst|cnt_h [1])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~1 ), + .combout(\vga_ctrl_inst|Add0~2_combout ), + .cout(\vga_ctrl_inst|Add0~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~10 ( +// Equation(s): +// \vga_ctrl_inst|Add0~10_combout = (\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|Add0~9 )) # (!\vga_ctrl_inst|cnt_h [5] & ((\vga_ctrl_inst|Add0~9 ) # (GND))) +// \vga_ctrl_inst|Add0~11 = CARRY((!\vga_ctrl_inst|Add0~9 ) # (!\vga_ctrl_inst|cnt_h [5])) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~9 ), + .combout(\vga_ctrl_inst|Add0~10_combout ), + .cout(\vga_ctrl_inst|Add0~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~2 ( +// Equation(s): +// \vga_ctrl_inst|Add1~2_combout = (\vga_ctrl_inst|cnt_v [1] & (!\vga_ctrl_inst|Add1~1 )) # (!\vga_ctrl_inst|cnt_v [1] & ((\vga_ctrl_inst|Add1~1 ) # (GND))) +// \vga_ctrl_inst|Add1~3 = CARRY((!\vga_ctrl_inst|Add1~1 ) # (!\vga_ctrl_inst|cnt_v [1])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~1 ), + .combout(\vga_ctrl_inst|Add1~2_combout ), + .cout(\vga_ctrl_inst|Add1~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~6 ( +// Equation(s): +// \vga_ctrl_inst|Add1~6_combout = (\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|Add1~5 )) # (!\vga_ctrl_inst|cnt_v [3] & ((\vga_ctrl_inst|Add1~5 ) # (GND))) +// \vga_ctrl_inst|Add1~7 = CARRY((!\vga_ctrl_inst|Add1~5 ) # (!\vga_ctrl_inst|cnt_v [3])) + + .dataa(\vga_ctrl_inst|cnt_v [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~5 ), + .combout(\vga_ctrl_inst|Add1~6_combout ), + .cout(\vga_ctrl_inst|Add1~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~6 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~8 ( +// Equation(s): +// \vga_ctrl_inst|Add1~8_combout = (\vga_ctrl_inst|cnt_v [4] & (\vga_ctrl_inst|Add1~7 $ (GND))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|Add1~7 & VCC)) +// \vga_ctrl_inst|Add1~9 = CARRY((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Add1~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~7 ), + .combout(\vga_ctrl_inst|Add1~8_combout ), + .cout(\vga_ctrl_inst|Add1~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~10 ( +// Equation(s): +// \vga_ctrl_inst|Add1~10_combout = (\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|Add1~9 )) # (!\vga_ctrl_inst|cnt_v [5] & ((\vga_ctrl_inst|Add1~9 ) # (GND))) +// \vga_ctrl_inst|Add1~11 = CARRY((!\vga_ctrl_inst|Add1~9 ) # (!\vga_ctrl_inst|cnt_v [5])) + + .dataa(\vga_ctrl_inst|cnt_v [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~9 ), + .combout(\vga_ctrl_inst|Add1~10_combout ), + .cout(\vga_ctrl_inst|Add1~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~12 ( +// Equation(s): +// \vga_ctrl_inst|Add1~12_combout = (\vga_ctrl_inst|cnt_v [6] & (\vga_ctrl_inst|Add1~11 $ (GND))) # (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|Add1~11 & VCC)) +// \vga_ctrl_inst|Add1~13 = CARRY((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Add1~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~11 ), + .combout(\vga_ctrl_inst|Add1~12_combout ), + .cout(\vga_ctrl_inst|Add1~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~14 ( +// Equation(s): +// \vga_ctrl_inst|Add1~14_combout = (\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|Add1~13 )) # (!\vga_ctrl_inst|cnt_v [7] & ((\vga_ctrl_inst|Add1~13 ) # (GND))) +// \vga_ctrl_inst|Add1~15 = CARRY((!\vga_ctrl_inst|Add1~13 ) # (!\vga_ctrl_inst|cnt_v [7])) + + .dataa(\vga_ctrl_inst|cnt_v [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~13 ), + .combout(\vga_ctrl_inst|Add1~14_combout ), + .cout(\vga_ctrl_inst|Add1~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~16 ( +// Equation(s): +// \vga_ctrl_inst|Add1~16_combout = (\vga_ctrl_inst|cnt_v [8] & (\vga_ctrl_inst|Add1~15 $ (GND))) # (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|Add1~15 & VCC)) +// \vga_ctrl_inst|Add1~17 = CARRY((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Add1~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~15 ), + .combout(\vga_ctrl_inst|Add1~16_combout ), + .cout(\vga_ctrl_inst|Add1~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~18 ( +// Equation(s): +// \vga_ctrl_inst|Add1~18_combout = (\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|Add1~17 )) # (!\vga_ctrl_inst|cnt_v [9] & ((\vga_ctrl_inst|Add1~17 ) # (GND))) +// \vga_ctrl_inst|Add1~19 = CARRY((!\vga_ctrl_inst|Add1~17 ) # (!\vga_ctrl_inst|cnt_v [9])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~17 ), + .combout(\vga_ctrl_inst|Add1~18_combout ), + .cout(\vga_ctrl_inst|Add1~19 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~18 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~20 ( +// Equation(s): +// \vga_ctrl_inst|Add1~20_combout = (\vga_ctrl_inst|cnt_v [10] & (\vga_ctrl_inst|Add1~19 $ (GND))) # (!\vga_ctrl_inst|cnt_v [10] & (!\vga_ctrl_inst|Add1~19 & VCC)) +// \vga_ctrl_inst|Add1~21 = CARRY((\vga_ctrl_inst|cnt_v [10] & !\vga_ctrl_inst|Add1~19 )) + + .dataa(\vga_ctrl_inst|cnt_v [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~19 ), + .combout(\vga_ctrl_inst|Add1~20_combout ), + .cout(\vga_ctrl_inst|Add1~21 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~20 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y20_N11 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y20_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [2] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1 .lut_mask = 16'h00F0; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N15 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add12~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_3~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_3~1_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_3~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~1 .lut_mask = 16'h0A8E; +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal1~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal1~0_combout = (!\hdmi_ctrl_inst|encode_inst0|cnt [4] & (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & (!\hdmi_ctrl_inst|encode_inst0|cnt [2] & !\hdmi_ctrl_inst|encode_inst0|cnt [0]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~0 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N27 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y24_N19 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n0[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add14~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_3~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_3~1_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & \hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]) # ((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & \hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_3~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~1 .lut_mask = 16'h4F04; +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N31 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]) # (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2 .lut_mask = 16'hFFF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~0_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst0|Add17~8_combout ) # (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add23~6_combout & ((!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add23~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add17~8_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~0 .lut_mask = 16'hCCE2; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~1_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add15~8_combout ) # ((!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~0_combout +// & (((\hdmi_ctrl_inst|encode_inst0|Add20~6_combout & \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~8_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add20~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~1 .lut_mask = 16'hD8AA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~3_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|Add17~6_combout ))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add23~4_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add23~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add17~6_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~3 .lut_mask = 16'hF2C2; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~4_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~3_combout & (((\hdmi_ctrl_inst|encode_inst0|Add15~6_combout ) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~3_combout +// & (\hdmi_ctrl_inst|encode_inst0|Add20~4_combout & ((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add20~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add16~3_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~4 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~5_combout = (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst0|Add19~4_combout ))) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst0|Add22~4_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add22~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add19~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~5 .lut_mask = 16'h3210; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~7_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst0|Add20~2_combout )) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add23~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add20~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add23~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~7 .lut_mask = 16'hFA0C; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~8_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~7_combout & ((\hdmi_ctrl_inst|encode_inst0|Add15~4_combout ) # ((!\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~7_combout +// & (((\hdmi_ctrl_inst|encode_inst0|Add17~4_combout & \hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~7_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add17~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~8 .lut_mask = 16'hD8AA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~11_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|Add17~2_combout ) # ((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst0|Add23~0_combout & !\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add17~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add23~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~11_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~11 .lut_mask = 16'hF0AC; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~12 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~12_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~11_combout & ((\hdmi_ctrl_inst|encode_inst0|Add15~2_combout ) # ((!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst0|Add16~11_combout & (((\hdmi_ctrl_inst|encode_inst0|Add20~0_combout & \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~11_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add20~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~12_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~12 .lut_mask = 16'hD8AA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~16 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~16_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|cnt [0]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .datad(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~16_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~16 .lut_mask = 16'h5F0A; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal1~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal1~1_combout = (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & \hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~1 .lut_mask = 16'h0F00; +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add12~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add12~1_combout = (!\hdmi_ctrl_inst|encode_inst0|data_in_reg [4] & \hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add12~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add12~1 .lut_mask = 16'h3300; +defparam \hdmi_ctrl_inst|encode_inst0|Add12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N7 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~2_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [3] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_reg [3]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~2 .lut_mask = 16'h995A; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [4])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [3]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out [4]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [3]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2 .lut_mask = 16'hACAC; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~0_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add17~8_combout ) # (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add23~6_combout & ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add23~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add17~8_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~0 .lut_mask = 16'hAAE4; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~1_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~0_combout & ((\hdmi_ctrl_inst|encode_inst1|Add15~8_combout ) # ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~0_combout +// & (((\hdmi_ctrl_inst|encode_inst1|Add20~6_combout & \hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add15~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add20~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~1 .lut_mask = 16'hACF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~5_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3])))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add22~4_combout & (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add22~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~5 .lut_mask = 16'hA4AE; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~6_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~5_combout ) # ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & \hdmi_ctrl_inst|encode_inst1|Add19~4_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add19~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~6 .lut_mask = 16'hF8F8; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~7_combout = (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add22~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add22~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~7 .lut_mask = 16'hAF44; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~8_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~7_combout & (((!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~7_combout & +// (\hdmi_ctrl_inst|encode_inst1|Add19~2_combout & (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add19~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~7_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~8 .lut_mask = 16'h2CEC; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~13_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add17~2_combout ) # (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add23~0_combout & ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add23~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add17~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~13_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~13 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~14 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~14_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~13_combout & (((\hdmi_ctrl_inst|encode_inst1|Add15~2_combout ) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|Add16~13_combout & (\hdmi_ctrl_inst|encode_inst1|Add20~0_combout & ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add20~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~13_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add15~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~14_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~14 .lut_mask = 16'hE2CC; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~16 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~16_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst1|cnt [0]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~16_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~16 .lut_mask = 16'h3F0C; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal2~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal2~1_combout = (\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout & !\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~1 .lut_mask = 16'h00AA; +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N31 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y21_N1 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~2_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [2] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~2 .lut_mask = 16'hA53C; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~2_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout ) # ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst2|Add19~6_combout )) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst2|Add22~6_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add19~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add22~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~2 .lut_mask = 16'hFAFC; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~3_combout = (\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|Add17~6_combout )) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|Add23~4_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add17~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|Add23~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~3 .lut_mask = 16'hE3E0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~4_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~3_combout & ((\hdmi_ctrl_inst|encode_inst2|Add15~6_combout ) # ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~3_combout +// & (((\hdmi_ctrl_inst|encode_inst2|Add20~4_combout & \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add15~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add20~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~3_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~4 .lut_mask = 16'hACF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~9_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2])))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|Add22~2_combout & ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add22~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~9_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~9 .lut_mask = 16'hAA4E; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~10 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~10_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~9_combout & (((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2])))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~9_combout & +// (\hdmi_ctrl_inst|encode_inst2|Add19~2_combout & ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add19~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~9_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~10_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~10 .lut_mask = 16'h3AF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~11_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|Add17~2_combout ) # (\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|Add23~0_combout & ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add23~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add17~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~11_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~11 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~12 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~12_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~11_combout & (((\hdmi_ctrl_inst|encode_inst2|Add15~2_combout ) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst2|Add16~11_combout & (\hdmi_ctrl_inst|encode_inst2|Add20~0_combout & ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add20~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add15~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~11_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~12_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~12 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~13_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|Add22~0_combout & !\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|Add22~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~13_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~13 .lut_mask = 16'hAA72; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~16 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~16_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|cnt [0])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~16_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~16 .lut_mask = 16'h0FCC; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal2~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal2~1_combout = (\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout & !\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~1 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add14~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add14~1_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3] & (\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] $ (!\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add14~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add14~1 .lut_mask = 16'hC00C; +defparam \hdmi_ctrl_inst|encode_inst2|Add14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N25 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~2_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [3] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~2 .lut_mask = 16'h939C; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~3_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~3 .lut_mask = 16'hF303; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~0_combout = (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|cnt_v [8]))) + + .dataa(\vga_ctrl_inst|cnt_v [9]), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|cnt_v [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N31 +dffeas \vga_ctrl_inst|cnt_v[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[10]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[10] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~3 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~3_combout = (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~2_combout & ((\vga_ctrl_inst|always1~0_combout ) # (!\vga_ctrl_inst|cnt_v [9])))) + + .dataa(\vga_ctrl_inst|pix_data_req~1_combout ), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|always1~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~3 .lut_mask = 16'hA200; +defparam \vga_ctrl_inst|pix_data_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout = \hdmi_ctrl_inst|encode_inst0|data_in_reg [3] $ (\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m[3]~0 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst0|q_m[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~5_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [4] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~5 .lut_mask = 16'h995A; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N19 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [6])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [6]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N31 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y21_N27 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [7])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [4]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [7]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [4]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N21 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~4_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [4] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_reg [4]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~4 .lut_mask = 16'hA53C; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout = \hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] $ (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m[3]~0 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst2|q_m[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N9 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~5_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [4] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~5 .lut_mask = 16'hC366; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y20_N11 +dffeas \vga_ctrl_inst|cnt_h[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|pix_x[10]~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_x[10]~1_combout = (\vga_ctrl_inst|Add2~18_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~18_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_x[10]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_x[10]~1 .lut_mask = 16'hFF0F; +defparam \vga_ctrl_inst|pix_x[10]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N10 +cycloneive_lcell_comb \vga_pic_inst|always0~1 ( +// Equation(s): +// \vga_pic_inst|always0~1_combout = (\vga_ctrl_inst|Add2~14_combout ) # ((\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout )) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|always0~1 .lut_mask = 16'hFFAF; +defparam \vga_pic_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N12 +cycloneive_lcell_comb \vga_pic_inst|always0~2 ( +// Equation(s): +// \vga_pic_inst|always0~2_combout = (\vga_pic_inst|always0~1_combout ) # ((\vga_ctrl_inst|Add2~18_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (\vga_pic_inst|LessThan17~2_combout ))) + + .dataa(\vga_pic_inst|always0~1_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|LessThan17~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|always0~2 .lut_mask = 16'hFFFE; +defparam \vga_pic_inst|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N6 +cycloneive_lcell_comb \vga_pic_inst|pix_data[9]~14 ( +// Equation(s): +// \vga_pic_inst|pix_data[9]~14_combout = (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_ctrl_inst|Add2~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[9]~14_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9]~14 .lut_mask = 16'h00F0; +defparam \vga_pic_inst|pix_data[9]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~16 ( +// Equation(s): +// \vga_pic_inst|pix_data~16_combout = (\vga_pic_inst|always0~2_combout & (!\vga_pic_inst|pix_data[9]~15_combout & (!\vga_ctrl_inst|pix_x[11]~0_combout & \vga_pic_inst|pix_data[13]~9_combout ))) + + .dataa(\vga_pic_inst|always0~2_combout ), + .datab(\vga_pic_inst|pix_data[9]~15_combout ), + .datac(\vga_ctrl_inst|pix_x[11]~0_combout ), + .datad(\vga_pic_inst|pix_data[13]~9_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~16 .lut_mask = 16'h0200; +defparam \vga_pic_inst|pix_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~8 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~8_combout = (!\vga_ctrl_inst|cnt_v [11] & !\vga_ctrl_inst|cnt_v [10]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [11]), + .datac(\vga_ctrl_inst|cnt_v [10]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~8 .lut_mask = 16'h0303; +defparam \vga_ctrl_inst|pix_data_req~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[10]~12 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[10]~12_combout = (\vga_ctrl_inst|Add1~20_combout & (((!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|cnt_v [10])) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~20_combout & (!\vga_ctrl_inst|Equal0~3_combout +// & (\vga_ctrl_inst|cnt_v [10]))) + + .dataa(\vga_ctrl_inst|Add1~20_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [10]), + .datad(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[10]~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[10]~12 .lut_mask = 16'h30BA; +defparam \vga_ctrl_inst|cnt_v[10]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m[4]~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout = \hdmi_ctrl_inst|encode_inst0|data_in_reg [4] $ (\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m[4]~2 .lut_mask = 16'h3C3C; +defparam \hdmi_ctrl_inst|encode_inst0|q_m[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[6]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6]~6 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N23 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout = (\hdmi_ctrl_inst|encode_inst0|data_out [8] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out [8]), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4 .lut_mask = 16'hA0A0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N22 +cycloneive_lcell_comb \vga_pic_inst|LessThan10~0 ( +// Equation(s): +// \vga_pic_inst|LessThan10~0_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~16_combout & ((\vga_pic_inst|LessThan17~2_combout ) # (!\vga_ctrl_inst|Add2~14_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_pic_inst|LessThan17~2_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan10~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan10~0 .lut_mask = 16'h080A; +defparam \vga_pic_inst|LessThan10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data~22 ( +// Equation(s): +// \vga_pic_inst|pix_data~22_combout = (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_ctrl_inst|Add2~10_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~22 .lut_mask = 16'h00F0; +defparam \vga_pic_inst|pix_data~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~23 ( +// Equation(s): +// \vga_pic_inst|pix_data~23_combout = (!\vga_ctrl_inst|Add2~14_combout & (\vga_pic_inst|pix_data~22_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_ctrl_inst|Add2~12_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_pic_inst|pix_data~22_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~23_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~23 .lut_mask = 16'h0400; +defparam \vga_pic_inst|pix_data~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N20 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~1 ( +// Equation(s): +// \vga_pic_inst|LessThan14~1_combout = (\vga_ctrl_inst|Add2~12_combout & \vga_ctrl_inst|Add2~10_combout ) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~1 .lut_mask = 16'hAA00; +defparam \vga_pic_inst|LessThan14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~24 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~24_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_pic_inst|LessThan14~1_combout & (!\vga_ctrl_inst|Add2~16_combout & !\vga_ctrl_inst|Add2~14_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_pic_inst|LessThan14~1_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~24_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~24 .lut_mask = 16'h0002; +defparam \vga_pic_inst|pix_data[13]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N8 +cycloneive_lcell_comb \vga_pic_inst|pix_data~25 ( +// Equation(s): +// \vga_pic_inst|pix_data~25_combout = (!\vga_ctrl_inst|pix_x[10]~1_combout & ((\vga_pic_inst|pix_data~23_combout ) # ((\vga_pic_inst|LessThan10~0_combout & !\vga_pic_inst|pix_data[13]~24_combout )))) + + .dataa(\vga_pic_inst|LessThan10~0_combout ), + .datab(\vga_ctrl_inst|pix_x[10]~1_combout ), + .datac(\vga_pic_inst|pix_data[13]~24_combout ), + .datad(\vga_pic_inst|pix_data~23_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~25_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~25 .lut_mask = 16'h3302; +defparam \vga_pic_inst|pix_data~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|q_m[5]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout = \hdmi_ctrl_inst|encode_inst1|data_in_reg [4] $ (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m[5]~0 .lut_mask = 16'hC33C; +defparam \hdmi_ctrl_inst|encode_inst1|q_m[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[7] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~5_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [7] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [7]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~5 .lut_mask = 16'h9A56; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N9 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [9]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[9] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout = (\hdmi_ctrl_inst|encode_inst1|data_out [9] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [9]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4 .lut_mask = 16'hC0C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m[4]~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout = \hdmi_ctrl_inst|encode_inst2|data_in_reg [3] $ (\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m[4]~2 .lut_mask = 16'h33CC; +defparam \hdmi_ctrl_inst|encode_inst2|q_m[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N23 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout = (\hdmi_ctrl_inst|encode_inst2|data_out [8] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [8]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4 .lut_mask = 16'h8888; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~8_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~8 .lut_mask = 16'h8D8D; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|q_m[7]~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout = \hdmi_ctrl_inst|encode_inst1|data_in_reg [7] $ (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m[7]~1 .lut_mask = 16'hC33C; +defparam \hdmi_ctrl_inst|encode_inst1|q_m[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~6_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst2|c1_reg2~q $ +// ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~6 .lut_mask = 16'hEB41; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~8_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~8 .lut_mask = 16'hB1B1; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~37 ( +// Equation(s): +// \vga_pic_inst|pix_data~37_combout = ((!\vga_ctrl_inst|Add2~18_combout & (\vga_ctrl_inst|pix_data_req~7_combout & \vga_pic_inst|pix_data~23_combout ))) # (!\vga_pic_inst|pix_data~16_combout ) + + .dataa(\vga_pic_inst|pix_data~16_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data~23_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~37_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~37 .lut_mask = 16'h7555; +defparam \vga_pic_inst|pix_data~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~2_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~2_combout + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder .lut_mask = 16'hAAAA; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~2_combout + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder .lut_mask = 16'hAAAA; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~5_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~5_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~4_combout + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out~4_combout ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder .lut_mask = 16'hCCCC; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~5_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out~5_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~5_combout + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out~5_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder .lut_mask = 16'hAAAA; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N16 +cycloneive_io_obuf \ddc_scl~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(ddc_scl), + .obar()); +// synopsys translate_off +defparam \ddc_scl~output .bus_hold = "false"; +defparam \ddc_scl~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y10_N16 +cycloneive_io_obuf \ddc_sda~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(ddc_sda), + .obar()); +// synopsys translate_off +defparam \ddc_sda~output .bus_hold = "false"; +defparam \ddc_sda~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y21_N23 +cycloneive_io_obuf \tmds_clk_p~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_clk_p), + .obar()); +// synopsys translate_off +defparam \tmds_clk_p~output .bus_hold = "false"; +defparam \tmds_clk_p~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y20_N2 +cycloneive_io_obuf \tmds_clk_n~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_clk_n), + .obar()); +// synopsys translate_off +defparam \tmds_clk_n~output .bus_hold = "false"; +defparam \tmds_clk_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y22_N16 +cycloneive_io_obuf \tmds_data_p[0]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_p[0]), + .obar()); +// synopsys translate_off +defparam \tmds_data_p[0]~output .bus_hold = "false"; +defparam \tmds_data_p[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y23_N9 +cycloneive_io_obuf \tmds_data_p[1]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_p[1]), + .obar()); +// synopsys translate_off +defparam \tmds_data_p[1]~output .bus_hold = "false"; +defparam \tmds_data_p[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y24_N2 +cycloneive_io_obuf \tmds_data_p[2]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_p[2]), + .obar()); +// synopsys translate_off +defparam \tmds_data_p[2]~output .bus_hold = "false"; +defparam \tmds_data_p[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y22_N23 +cycloneive_io_obuf \tmds_data_n[0]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_n[0]), + .obar()); +// synopsys translate_off +defparam \tmds_data_n[0]~output .bus_hold = "false"; +defparam \tmds_data_n[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y23_N16 +cycloneive_io_obuf \tmds_data_n[1]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_n[1]), + .obar()); +// synopsys translate_off +defparam \tmds_data_n[1]~output .bus_hold = "false"; +defparam \tmds_data_n[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y24_N9 +cycloneive_io_obuf \tmds_data_n[2]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_n[2]), + .obar()); +// synopsys translate_off +defparam \tmds_data_n[2]~output .bus_hold = "false"; +defparam \tmds_data_n[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout = (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0 .lut_mask = 16'h0303; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout = \hdmi_ctrl_inst|par_to_ser_inst0|cnt [1] $ (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N19 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout = \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] $ (((\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0 .lut_mask = 16'h3CF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N17 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [1] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [1]), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0 .lut_mask = 16'h00AA; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout = \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N31 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) # (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [4]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [4]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3 .lut_mask = 16'hFCFC; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N5 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2 .lut_mask = 16'h00F0; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [2] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N29 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [1] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [1]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N23 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y21_N25 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y20_N4 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~0 ( +// Equation(s): +// \vga_ctrl_inst|Add0~0_combout = \vga_ctrl_inst|cnt_h [0] $ (VCC) +// \vga_ctrl_inst|Add0~1 = CARRY(\vga_ctrl_inst|cnt_h [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add0~0_combout ), + .cout(\vga_ctrl_inst|Add0~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y26_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X40_Y26_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y26_N18 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) # (!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q )) # (!\sys_rst_n~input_o ) + + .dataa(\sys_rst_n~input_o ), + .datab(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .datac(gnd), + .datad(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h77FF; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G7 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X37_Y20_N9 +dffeas \vga_ctrl_inst|cnt_h[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~4 ( +// Equation(s): +// \vga_ctrl_inst|Add0~4_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|Add0~3 $ (GND))) # (!\vga_ctrl_inst|cnt_h [2] & (!\vga_ctrl_inst|Add0~3 & VCC)) +// \vga_ctrl_inst|Add0~5 = CARRY((\vga_ctrl_inst|cnt_h [2] & !\vga_ctrl_inst|Add0~3 )) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~3 ), + .combout(\vga_ctrl_inst|Add0~4_combout ), + .cout(\vga_ctrl_inst|Add0~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~6 ( +// Equation(s): +// \vga_ctrl_inst|Add0~6_combout = (\vga_ctrl_inst|cnt_h [3] & (!\vga_ctrl_inst|Add0~5 )) # (!\vga_ctrl_inst|cnt_h [3] & ((\vga_ctrl_inst|Add0~5 ) # (GND))) +// \vga_ctrl_inst|Add0~7 = CARRY((!\vga_ctrl_inst|Add0~5 ) # (!\vga_ctrl_inst|cnt_h [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~5 ), + .combout(\vga_ctrl_inst|Add0~6_combout ), + .cout(\vga_ctrl_inst|Add0~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N15 +dffeas \vga_ctrl_inst|cnt_h[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~8 ( +// Equation(s): +// \vga_ctrl_inst|Add0~8_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Add0~7 $ (GND))) # (!\vga_ctrl_inst|cnt_h [4] & (!\vga_ctrl_inst|Add0~7 & VCC)) +// \vga_ctrl_inst|Add0~9 = CARRY((\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add0~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~7 ), + .combout(\vga_ctrl_inst|Add0~8_combout ), + .cout(\vga_ctrl_inst|Add0~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N17 +dffeas \vga_ctrl_inst|cnt_h[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~12 ( +// Equation(s): +// \vga_ctrl_inst|Add0~12_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add0~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add0~11 & VCC)) +// \vga_ctrl_inst|Add0~13 = CARRY((\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add0~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~11 ), + .combout(\vga_ctrl_inst|Add0~12_combout ), + .cout(\vga_ctrl_inst|Add0~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N21 +dffeas \vga_ctrl_inst|cnt_h[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~14 ( +// Equation(s): +// \vga_ctrl_inst|Add0~14_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add0~13 )) # (!\vga_ctrl_inst|cnt_h [7] & ((\vga_ctrl_inst|Add0~13 ) # (GND))) +// \vga_ctrl_inst|Add0~15 = CARRY((!\vga_ctrl_inst|Add0~13 ) # (!\vga_ctrl_inst|cnt_h [7])) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~13 ), + .combout(\vga_ctrl_inst|Add0~14_combout ), + .cout(\vga_ctrl_inst|Add0~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N23 +dffeas \vga_ctrl_inst|cnt_h[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y20_N13 +dffeas \vga_ctrl_inst|cnt_h[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~0 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~0_combout = (\vga_ctrl_inst|cnt_h [1] & (\vga_ctrl_inst|cnt_h [3] & (\vga_ctrl_inst|cnt_h [0] & \vga_ctrl_inst|cnt_h [2]))) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(\vga_ctrl_inst|cnt_h [0]), + .datad(\vga_ctrl_inst|cnt_h [2]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~0 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~16 ( +// Equation(s): +// \vga_ctrl_inst|Add0~16_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add0~15 $ (GND))) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add0~15 & VCC)) +// \vga_ctrl_inst|Add0~17 = CARRY((\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add0~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~15 ), + .combout(\vga_ctrl_inst|Add0~16_combout ), + .cout(\vga_ctrl_inst|Add0~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~18 ( +// Equation(s): +// \vga_ctrl_inst|Add0~18_combout = (\vga_ctrl_inst|cnt_h [9] & (!\vga_ctrl_inst|Add0~17 )) # (!\vga_ctrl_inst|cnt_h [9] & ((\vga_ctrl_inst|Add0~17 ) # (GND))) +// \vga_ctrl_inst|Add0~19 = CARRY((!\vga_ctrl_inst|Add0~17 ) # (!\vga_ctrl_inst|cnt_h [9])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [9]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~17 ), + .combout(\vga_ctrl_inst|Add0~18_combout ), + .cout(\vga_ctrl_inst|Add0~19 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~18 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~20 ( +// Equation(s): +// \vga_ctrl_inst|Add0~20_combout = (\vga_ctrl_inst|cnt_h [10] & (\vga_ctrl_inst|Add0~19 $ (GND))) # (!\vga_ctrl_inst|cnt_h [10] & (!\vga_ctrl_inst|Add0~19 & VCC)) +// \vga_ctrl_inst|Add0~21 = CARRY((\vga_ctrl_inst|cnt_h [10] & !\vga_ctrl_inst|Add0~19 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~19 ), + .combout(\vga_ctrl_inst|Add0~20_combout ), + .cout(\vga_ctrl_inst|Add0~21 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~20 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N29 +dffeas \vga_ctrl_inst|cnt_h[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[10] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~22 ( +// Equation(s): +// \vga_ctrl_inst|Add0~22_combout = \vga_ctrl_inst|cnt_h [11] $ (\vga_ctrl_inst|Add0~21 ) + + .dataa(\vga_ctrl_inst|cnt_h [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\vga_ctrl_inst|Add0~21 ), + .combout(\vga_ctrl_inst|Add0~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~22 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N31 +dffeas \vga_ctrl_inst|cnt_h[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [11]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[11] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~1 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~1_combout = (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|cnt_h [10] & (!\vga_ctrl_inst|cnt_h [11] & \vga_ctrl_inst|cnt_h [9]))) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(\vga_ctrl_inst|cnt_h [11]), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~1 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N24 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~0_combout = (\vga_ctrl_inst|Add0~10_combout & (((!\vga_ctrl_inst|Equal0~2_combout ) # (!\vga_ctrl_inst|Equal0~1_combout )) # (!\vga_ctrl_inst|Equal0~0_combout ))) + + .dataa(\vga_ctrl_inst|Add0~10_combout ), + .datab(\vga_ctrl_inst|Equal0~0_combout ), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~0 .lut_mask = 16'h2AAA; +defparam \vga_ctrl_inst|cnt_h~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y21_N25 +dffeas \vga_ctrl_inst|cnt_h[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~2 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~2_combout = (\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|cnt_h [5] & (\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [6]))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [5]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~2 .lut_mask = 16'h0020; +defparam \vga_ctrl_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~2_combout = (\vga_ctrl_inst|Add0~16_combout & (((!\vga_ctrl_inst|Equal0~2_combout ) # (!\vga_ctrl_inst|Equal0~0_combout )) # (!\vga_ctrl_inst|Equal0~1_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|Add0~16_combout ), + .datac(\vga_ctrl_inst|Equal0~0_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~2 .lut_mask = 16'h4CCC; +defparam \vga_ctrl_inst|cnt_h~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y20_N3 +dffeas \vga_ctrl_inst|cnt_h[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~1_combout = (\vga_ctrl_inst|Add0~18_combout & (((!\vga_ctrl_inst|Equal0~2_combout ) # (!\vga_ctrl_inst|Equal0~0_combout )) # (!\vga_ctrl_inst|Equal0~1_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|Equal0~0_combout ), + .datac(\vga_ctrl_inst|Add0~18_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~1 .lut_mask = 16'h70F0; +defparam \vga_ctrl_inst|cnt_h~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y20_N1 +dffeas \vga_ctrl_inst|cnt_h[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan4~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan4~0_combout = (!\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [6])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [5]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan4~0 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add4~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add4~0_combout = (\vga_ctrl_inst|cnt_h [8] & (((!\vga_ctrl_inst|cnt_h [7] & \vga_ctrl_inst|LessThan4~0_combout )) # (!\vga_ctrl_inst|cnt_h [9]))) # (!\vga_ctrl_inst|cnt_h [8] & ((\vga_ctrl_inst|cnt_h [9]) # +// ((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|LessThan4~0_combout )))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(\vga_ctrl_inst|LessThan4~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add4~0 .lut_mask = 16'h7A5E; +defparam \hdmi_ctrl_inst|encode_inst0|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~1 ( +// Equation(s): +// \vga_ctrl_inst|Add2~1_cout = CARRY((\vga_ctrl_inst|cnt_h [1] & \vga_ctrl_inst|cnt_h [0])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\vga_ctrl_inst|Add2~1_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~1 .lut_mask = 16'h0088; +defparam \vga_ctrl_inst|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~3 ( +// Equation(s): +// \vga_ctrl_inst|Add2~3_cout = CARRY((!\vga_ctrl_inst|Add2~1_cout ) # (!\vga_ctrl_inst|cnt_h [2])) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~1_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~3_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~3 .lut_mask = 16'h005F; +defparam \vga_ctrl_inst|Add2~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~5 ( +// Equation(s): +// \vga_ctrl_inst|Add2~5_cout = CARRY((\vga_ctrl_inst|cnt_h [3] & !\vga_ctrl_inst|Add2~3_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~3_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~5_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~5 .lut_mask = 16'h000A; +defparam \vga_ctrl_inst|Add2~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~7 ( +// Equation(s): +// \vga_ctrl_inst|Add2~7_cout = CARRY((!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add2~5_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~5_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~7_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~7 .lut_mask = 16'h0005; +defparam \vga_ctrl_inst|Add2~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~9 ( +// Equation(s): +// \vga_ctrl_inst|Add2~9_cout = CARRY((\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|Add2~7_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [5]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~7_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~9_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~9 .lut_mask = 16'h00CF; +defparam \vga_ctrl_inst|Add2~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~10 ( +// Equation(s): +// \vga_ctrl_inst|Add2~10_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add2~9_cout & VCC)) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add2~9_cout )) +// \vga_ctrl_inst|Add2~11 = CARRY((!\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add2~9_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~9_cout ), + .combout(\vga_ctrl_inst|Add2~10_combout ), + .cout(\vga_ctrl_inst|Add2~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~10 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~12 ( +// Equation(s): +// \vga_ctrl_inst|Add2~12_combout = (\vga_ctrl_inst|cnt_h [7] & (\vga_ctrl_inst|Add2~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add2~11 & VCC)) +// \vga_ctrl_inst|Add2~13 = CARRY((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|Add2~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~11 ), + .combout(\vga_ctrl_inst|Add2~12_combout ), + .cout(\vga_ctrl_inst|Add2~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~14 ( +// Equation(s): +// \vga_ctrl_inst|Add2~14_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add2~13 & VCC)) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add2~13 )) +// \vga_ctrl_inst|Add2~15 = CARRY((!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add2~13 )) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~13 ), + .combout(\vga_ctrl_inst|Add2~14_combout ), + .cout(\vga_ctrl_inst|Add2~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~14 .lut_mask = 16'hA505; +defparam \vga_ctrl_inst|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~16 ( +// Equation(s): +// \vga_ctrl_inst|Add2~16_combout = (\vga_ctrl_inst|cnt_h [9] & ((GND) # (!\vga_ctrl_inst|Add2~15 ))) # (!\vga_ctrl_inst|cnt_h [9] & (\vga_ctrl_inst|Add2~15 $ (GND))) +// \vga_ctrl_inst|Add2~17 = CARRY((\vga_ctrl_inst|cnt_h [9]) # (!\vga_ctrl_inst|Add2~15 )) + + .dataa(\vga_ctrl_inst|cnt_h [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~15 ), + .combout(\vga_ctrl_inst|Add2~16_combout ), + .cout(\vga_ctrl_inst|Add2~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~16 .lut_mask = 16'h5AAF; +defparam \vga_ctrl_inst|Add2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~18 ( +// Equation(s): +// \vga_ctrl_inst|Add2~18_combout = (\vga_ctrl_inst|cnt_h [10] & (\vga_ctrl_inst|Add2~17 & VCC)) # (!\vga_ctrl_inst|cnt_h [10] & (!\vga_ctrl_inst|Add2~17 )) +// \vga_ctrl_inst|Add2~19 = CARRY((!\vga_ctrl_inst|cnt_h [10] & !\vga_ctrl_inst|Add2~17 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~17 ), + .combout(\vga_ctrl_inst|Add2~18_combout ), + .cout(\vga_ctrl_inst|Add2~19 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~18 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~12 ( +// Equation(s): +// \vga_pic_inst|pix_data~12_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~18_combout & (\vga_ctrl_inst|Add2~16_combout & !\vga_ctrl_inst|Add2~14_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~12 .lut_mask = 16'h0020; +defparam \vga_pic_inst|pix_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~5 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~5_combout = \vga_ctrl_inst|cnt_h [8] $ (\vga_ctrl_inst|cnt_h [9]) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~5 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|pix_data_req~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N2 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~3 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~3_combout = (\vga_ctrl_inst|Equal0~1_combout & (\vga_ctrl_inst|Equal0~0_combout & \vga_ctrl_inst|Equal0~2_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Equal0~1_combout ), + .datac(\vga_ctrl_inst|Equal0~0_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~3 .lut_mask = 16'hC000; +defparam \vga_ctrl_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[7]~7 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[7]~7_combout = (\vga_ctrl_inst|Add1~14_combout & (((\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~14_combout & (((\vga_ctrl_inst|cnt_v [7] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~14_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7]~7 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N21 +dffeas \vga_ctrl_inst|cnt_v[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[7]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[5]~10 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[5]~10_combout = (\vga_ctrl_inst|Add1~10_combout & (((!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|cnt_v [5])) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~10_combout & (!\vga_ctrl_inst|Equal0~3_combout +// & (\vga_ctrl_inst|cnt_v [5]))) + + .dataa(\vga_ctrl_inst|Add1~10_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5]~10 .lut_mask = 16'h30BA; +defparam \vga_ctrl_inst|cnt_v[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N27 +dffeas \vga_ctrl_inst|cnt_v[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[5]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[8]~6 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[8]~6_combout = (\vga_ctrl_inst|Add1~16_combout & (((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~16_combout & (((\vga_ctrl_inst|cnt_v [8] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~16_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [8]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[8]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8]~6 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[8]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N19 +dffeas \vga_ctrl_inst|cnt_v[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[8]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|always1~0 ( +// Equation(s): +// \vga_ctrl_inst|always1~0_combout = (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|cnt_v [5] & !\vga_ctrl_inst|cnt_v [8]))) + + .dataa(\vga_ctrl_inst|cnt_v [6]), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|cnt_v [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[1]~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[1]~1_combout = (\vga_ctrl_inst|Add1~2_combout & (((\vga_ctrl_inst|cnt_v [1] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~2_combout & (((\vga_ctrl_inst|cnt_v [1] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~2_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1]~1 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N9 +dffeas \vga_ctrl_inst|cnt_v[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[1]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[4]~5 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[4]~5_combout = (\vga_ctrl_inst|Add1~8_combout & (((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~8_combout & (((\vga_ctrl_inst|cnt_v [4] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~8_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [4]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4]~5 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N1 +dffeas \vga_ctrl_inst|cnt_v[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[4]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N24 +cycloneive_lcell_comb \vga_ctrl_inst|always1~1 ( +// Equation(s): +// \vga_ctrl_inst|always1~1_combout = (\vga_ctrl_inst|pix_data_req~8_combout & (\vga_ctrl_inst|always1~0_combout & (!\vga_ctrl_inst|cnt_v [1] & !\vga_ctrl_inst|cnt_v [4]))) + + .dataa(\vga_ctrl_inst|pix_data_req~8_combout ), + .datab(\vga_ctrl_inst|always1~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~1 .lut_mask = 16'h0008; +defparam \vga_ctrl_inst|always1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~0 ( +// Equation(s): +// \vga_ctrl_inst|Add1~0_combout = \vga_ctrl_inst|cnt_v [0] $ (VCC) +// \vga_ctrl_inst|Add1~1 = CARRY(\vga_ctrl_inst|cnt_v [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add1~0_combout ), + .cout(\vga_ctrl_inst|Add1~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[0]~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[0]~2_combout = (\vga_ctrl_inst|cnt_v[11]~0_combout & (((\vga_ctrl_inst|cnt_v [0] & !\vga_ctrl_inst|Equal0~3_combout )))) # (!\vga_ctrl_inst|cnt_v[11]~0_combout & ((\vga_ctrl_inst|Add1~0_combout ) # ((\vga_ctrl_inst|cnt_v [0] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datab(\vga_ctrl_inst|Add1~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0]~2 .lut_mask = 16'h44F4; +defparam \vga_ctrl_inst|cnt_v[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N1 +dffeas \vga_ctrl_inst|cnt_v[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[0]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[3]~3 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[3]~3_combout = (\vga_ctrl_inst|Add1~6_combout & (((\vga_ctrl_inst|cnt_v [3] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~6_combout & (((\vga_ctrl_inst|cnt_v [3] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~6_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3]~3 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N3 +dffeas \vga_ctrl_inst|cnt_v[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[3]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|always1~2 ( +// Equation(s): +// \vga_ctrl_inst|always1~2_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [0] & \vga_ctrl_inst|cnt_v [3]))) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|cnt_v [3]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~2 .lut_mask = 16'h0800; +defparam \vga_ctrl_inst|always1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[11]~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[11]~0_combout = ((\vga_ctrl_inst|always1~1_combout & \vga_ctrl_inst|always1~2_combout )) # (!\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|always1~1_combout ), + .datac(\vga_ctrl_inst|always1~2_combout ), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[11]~0 .lut_mask = 16'hC0FF; +defparam \vga_ctrl_inst|cnt_v[11]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[9]~9 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[9]~9_combout = (\vga_ctrl_inst|Add1~18_combout & (((\vga_ctrl_inst|cnt_v [9] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~18_combout & (((\vga_ctrl_inst|cnt_v [9] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~18_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9]~9 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N17 +dffeas \vga_ctrl_inst|cnt_v[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[9]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[6]~8 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[6]~8_combout = (\vga_ctrl_inst|Add1~12_combout & (((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~12_combout & (((\vga_ctrl_inst|cnt_v [6] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~12_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6]~8 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N23 +dffeas \vga_ctrl_inst|cnt_v[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[6]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~4 ( +// Equation(s): +// \vga_ctrl_inst|Add1~4_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|Add1~3 $ (GND))) # (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|Add1~3 & VCC)) +// \vga_ctrl_inst|Add1~5 = CARRY((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Add1~3 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [2]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~3 ), + .combout(\vga_ctrl_inst|Add1~4_combout ), + .cout(\vga_ctrl_inst|Add1~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~4 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[2]~4 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[2]~4_combout = (\vga_ctrl_inst|cnt_v[11]~0_combout & (((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Equal0~3_combout )))) # (!\vga_ctrl_inst|cnt_v[11]~0_combout & ((\vga_ctrl_inst|Add1~4_combout ) # ((\vga_ctrl_inst|cnt_v [2] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datab(\vga_ctrl_inst|Add1~4_combout ), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2]~4 .lut_mask = 16'h44F4; +defparam \vga_ctrl_inst|cnt_v[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N13 +dffeas \vga_ctrl_inst|cnt_v[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[2]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~22 ( +// Equation(s): +// \vga_ctrl_inst|Add1~22_combout = \vga_ctrl_inst|Add1~21 $ (\vga_ctrl_inst|cnt_v [11]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [11]), + .cin(\vga_ctrl_inst|Add1~21 ), + .combout(\vga_ctrl_inst|Add1~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~22 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add1~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[11]~11 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[11]~11_combout = (\vga_ctrl_inst|cnt_v[11]~0_combout & (((\vga_ctrl_inst|cnt_v [11] & !\vga_ctrl_inst|Equal0~3_combout )))) # (!\vga_ctrl_inst|cnt_v[11]~0_combout & ((\vga_ctrl_inst|Add1~22_combout ) # ((\vga_ctrl_inst|cnt_v [11] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datab(\vga_ctrl_inst|Add1~22_combout ), + .datac(\vga_ctrl_inst|cnt_v [11]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[11]~11 .lut_mask = 16'h44F4; +defparam \vga_ctrl_inst|cnt_v[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N29 +dffeas \vga_ctrl_inst|cnt_v[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[11]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [11]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[11] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~2 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~2_combout = (!\vga_ctrl_inst|cnt_v [10] & (!\vga_ctrl_inst|cnt_v [11] & (!\vga_ctrl_inst|cnt_h [11] & !\vga_ctrl_inst|cnt_h [10]))) + + .dataa(\vga_ctrl_inst|cnt_v [10]), + .datab(\vga_ctrl_inst|cnt_v [11]), + .datac(\vga_ctrl_inst|cnt_h [11]), + .datad(\vga_ctrl_inst|cnt_h [10]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~2 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~4 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~4_combout = (\vga_ctrl_inst|pix_data_req~2_combout & ((\vga_ctrl_inst|always1~0_combout ) # (!\vga_ctrl_inst|cnt_v [9]))) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|pix_data_req~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~4 .lut_mask = 16'hAF00; +defparam \vga_ctrl_inst|pix_data_req~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~6 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~6_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|cnt_h [9] & ((\vga_ctrl_inst|Equal0~0_combout ) # (!\vga_ctrl_inst|LessThan4~0_combout )))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Equal0~0_combout & +// (\vga_ctrl_inst|cnt_h [9] & \vga_ctrl_inst|LessThan4~0_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(\vga_ctrl_inst|LessThan4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~6 .lut_mask = 16'h180C; +defparam \vga_ctrl_inst|pix_data_req~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~7 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~7_combout = (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|pix_data_req~5_combout ) # (\vga_ctrl_inst|pix_data_req~6_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~1_combout ), + .datab(\vga_ctrl_inst|pix_data_req~5_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|pix_data_req~6_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~7 .lut_mask = 16'hA080; +defparam \vga_ctrl_inst|pix_data_req~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~11 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~11_combout = ((\vga_ctrl_inst|Add2~16_combout ) # ((\vga_ctrl_inst|Add2~14_combout & \vga_ctrl_inst|Add2~12_combout ))) # (!\vga_ctrl_inst|pix_data_req~7_combout ) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|pix_data_req~7_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~11 .lut_mask = 16'hFBF3; +defparam \vga_pic_inst|pix_data[13]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N6 +cycloneive_lcell_comb \vga_pic_inst|always0~0 ( +// Equation(s): +// \vga_pic_inst|always0~0_combout = (\vga_ctrl_inst|Add2~16_combout ) # ((\vga_ctrl_inst|Add2~18_combout ) # ((!\vga_pic_inst|pix_data[13]~11_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ))) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[13]~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|always0~0 .lut_mask = 16'hEFFF; +defparam \vga_pic_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~13 ( +// Equation(s): +// \vga_pic_inst|pix_data~13_combout = (\vga_pic_inst|LessThan14~0_combout & (((\vga_ctrl_inst|Add2~12_combout )) # (!\vga_pic_inst|pix_data~12_combout ))) # (!\vga_pic_inst|LessThan14~0_combout & (\vga_pic_inst|always0~0_combout & +// ((\vga_ctrl_inst|Add2~12_combout ) # (!\vga_pic_inst|pix_data~12_combout )))) + + .dataa(\vga_pic_inst|LessThan14~0_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_ctrl_inst|Add2~12_combout ), + .datad(\vga_pic_inst|always0~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~13 .lut_mask = 16'hF3A2; +defparam \vga_pic_inst|pix_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~17 ( +// Equation(s): +// \vga_pic_inst|pix_data~17_combout = (!\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_ctrl_inst|Add2~12_combout )) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~17_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~17 .lut_mask = 16'h0500; +defparam \vga_pic_inst|pix_data~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N10 +cycloneive_lcell_comb \vga_pic_inst|pix_data~34 ( +// Equation(s): +// \vga_pic_inst|pix_data~34_combout = ((!\vga_ctrl_inst|Add2~18_combout & (\vga_ctrl_inst|pix_data_req~7_combout & \vga_pic_inst|pix_data~17_combout ))) # (!\vga_pic_inst|pix_data~16_combout ) + + .dataa(\vga_pic_inst|pix_data~16_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data~17_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~34_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~34 .lut_mask = 16'h7555; +defparam \vga_pic_inst|pix_data~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N16 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~8 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~8_combout = (!\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|Add2~14_combout ) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~8 .lut_mask = 16'h55FF; +defparam \vga_pic_inst|pix_data[13]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~9 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~9_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~18_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_pic_inst|pix_data[13]~8_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|pix_data[13]~8_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~9 .lut_mask = 16'h0200; +defparam \vga_pic_inst|pix_data[13]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~10 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~10_combout = (!\vga_ctrl_inst|Add2~20_combout & (\vga_ctrl_inst|pix_data_req~7_combout & \vga_pic_inst|pix_data[13]~9_combout )) + + .dataa(\vga_ctrl_inst|Add2~20_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[13]~9_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~10 .lut_mask = 16'h5000; +defparam \vga_pic_inst|pix_data[13]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N8 +cycloneive_lcell_comb \vga_pic_inst|pix_data~18 ( +// Equation(s): +// \vga_pic_inst|pix_data~18_combout = ((!\vga_ctrl_inst|pix_x[11]~0_combout & (!\vga_pic_inst|pix_data~13_combout & !\vga_pic_inst|pix_data[13]~10_combout ))) # (!\vga_pic_inst|pix_data~34_combout ) + + .dataa(\vga_ctrl_inst|pix_x[11]~0_combout ), + .datab(\vga_pic_inst|pix_data~13_combout ), + .datac(\vga_pic_inst|pix_data~34_combout ), + .datad(\vga_pic_inst|pix_data[13]~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~18 .lut_mask = 16'h0F1F; +defparam \vga_pic_inst|pix_data~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N9 +dffeas \vga_pic_inst|pix_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~20 ( +// Equation(s): +// \vga_ctrl_inst|Add2~20_combout = \vga_ctrl_inst|Add2~19 $ (\vga_ctrl_inst|cnt_h [11]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [11]), + .cin(\vga_ctrl_inst|Add2~19 ), + .combout(\vga_ctrl_inst|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~20 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add2~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N28 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~4 ( +// Equation(s): +// \vga_pic_inst|LessThan17~4_combout = (!\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~10_combout & (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_ctrl_inst|Add2~12_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~4 .lut_mask = 16'h0010; +defparam \vga_pic_inst|LessThan17~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N20 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~3 ( +// Equation(s): +// \vga_pic_inst|LessThan17~3_combout = (!\vga_ctrl_inst|Add2~18_combout & (!\vga_ctrl_inst|Add2~20_combout & (\vga_ctrl_inst|Add2~16_combout & \vga_pic_inst|LessThan17~4_combout ))) + + .dataa(\vga_ctrl_inst|Add2~18_combout ), + .datab(\vga_ctrl_inst|Add2~20_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|LessThan17~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~3 .lut_mask = 16'h1000; +defparam \vga_pic_inst|LessThan17~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N14 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~0 ( +// Equation(s): +// \vga_pic_inst|LessThan14~0_combout = (\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~10_combout & \vga_ctrl_inst|Add2~12_combout )) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~10_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~0 .lut_mask = 16'hA000; +defparam \vga_pic_inst|LessThan14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~19 ( +// Equation(s): +// \vga_pic_inst|pix_data~19_combout = (\vga_pic_inst|LessThan17~3_combout ) # ((!\vga_ctrl_inst|pix_x[11]~0_combout & (!\vga_pic_inst|LessThan14~0_combout & !\vga_pic_inst|always0~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_x[11]~0_combout ), + .datab(\vga_pic_inst|LessThan17~3_combout ), + .datac(\vga_pic_inst|LessThan14~0_combout ), + .datad(\vga_pic_inst|always0~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~19_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~19 .lut_mask = 16'hCCCD; +defparam \vga_pic_inst|pix_data~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~20 ( +// Equation(s): +// \vga_pic_inst|pix_data~20_combout = ((!\vga_pic_inst|pix_data[13]~10_combout & \vga_pic_inst|pix_data~19_combout )) # (!\vga_pic_inst|pix_data~34_combout ) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data[13]~10_combout ), + .datac(\vga_pic_inst|pix_data~34_combout ), + .datad(\vga_pic_inst|pix_data~19_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~20 .lut_mask = 16'h3F0F; +defparam \vga_pic_inst|pix_data~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N19 +dffeas \vga_pic_inst|pix_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[0] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add6~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add6~0_combout = (\vga_ctrl_inst|pix_data_req~3_combout & (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_pic_inst|pix_data [4] & \vga_pic_inst|pix_data [0]))) + + .dataa(\vga_ctrl_inst|pix_data_req~3_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datac(\vga_pic_inst|pix_data [4]), + .datad(\vga_pic_inst|pix_data [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add6~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add6~0 .lut_mask = 16'h8000; +defparam \hdmi_ctrl_inst|encode_inst0|Add6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|data_in_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_in_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_in_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout = !\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0 .lut_mask = 16'h00FF; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N21 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y22_N27 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~0_combout = (!\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|cnt_v [2] & ((!\vga_ctrl_inst|cnt_v [1]) # (!\vga_ctrl_inst|cnt_v [0])))) + + .dataa(\vga_ctrl_inst|cnt_v [0]), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|cnt_v [2]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~0 .lut_mask = 16'h0013; +defparam \vga_ctrl_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~1_combout = (\vga_ctrl_inst|LessThan6~0_combout & ((\vga_ctrl_inst|cnt_v [4] & ((!\vga_ctrl_inst|always1~0_combout ))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|pix_data_req~0_combout )))) # +// (!\vga_ctrl_inst|LessThan6~0_combout & (((!\vga_ctrl_inst|always1~0_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~0_combout ), + .datab(\vga_ctrl_inst|always1~0_combout ), + .datac(\vga_ctrl_inst|LessThan6~0_combout ), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~1 .lut_mask = 16'h3353; +defparam \vga_ctrl_inst|pix_data_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N28 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[1]~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb[1]~0_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_pic_inst|pix_data [4] & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_pic_inst|pix_data [4]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[1]~0 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N29 +dffeas \hdmi_ctrl_inst|encode_inst0|data_in_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N30 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[2]~1 ( +// Equation(s): +// \vga_ctrl_inst|rgb[2]~1_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~1_combout & \vga_pic_inst|pix_data [0]))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\vga_pic_inst|pix_data [0]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[2]~1 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N31 +dffeas \hdmi_ctrl_inst|encode_inst0|data_in_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[2]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add14~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add14~0_combout = (\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]) # ((\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]) # (\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add14~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add14~0 .lut_mask = 16'hFFFC; +defparam \hdmi_ctrl_inst|encode_inst0|Add14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout = !\hdmi_ctrl_inst|encode_inst0|Add14~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|Add14~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0 .lut_mask = 16'h00FF; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N9 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n0[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add19~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [1] & \hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add19~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~2_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [2] & (!\hdmi_ctrl_inst|encode_inst0|Add19~1 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst0|Add19~1 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add19~3 = CARRY((!\hdmi_ctrl_inst|encode_inst0|Add19~1 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [2])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add19~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add19~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~2 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~6_combout = \hdmi_ctrl_inst|encode_inst0|cnt [4] $ (\hdmi_ctrl_inst|encode_inst0|Add19~5 ) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add19~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~6 .lut_mask = 16'h3C3C; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [1] & ((\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]) # (GND))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] $ (VCC))) +// \hdmi_ctrl_inst|encode_inst0|Add22~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [1]) # (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add22~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~0 .lut_mask = 16'h99EE; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~2_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|Add22~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [2] & (!\hdmi_ctrl_inst|encode_inst0|Add22~1 )) +// \hdmi_ctrl_inst|encode_inst0|Add22~3 = CARRY((!\hdmi_ctrl_inst|encode_inst0|cnt [2] & !\hdmi_ctrl_inst|encode_inst0|Add22~1 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add22~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add22~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~2 .lut_mask = 16'hA505; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~6_combout = \hdmi_ctrl_inst|encode_inst0|Add22~5 $ (!\hdmi_ctrl_inst|encode_inst0|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst0|Add22~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~6 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~2_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout ) # ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst0|Add19~6_combout )) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst0|Add22~6_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add19~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add22~6_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~2 .lut_mask = 16'hFBEA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[0]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0]~0 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N17 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n0[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add14~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~9_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add22~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add22~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~9_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~9 .lut_mask = 16'hAF44; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~10 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~10_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~9_combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2])) # (!\hdmi_ctrl_inst|encode_inst0|Add16~9_combout & +// ((\hdmi_ctrl_inst|encode_inst0|Add19~2_combout ))))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|Add16~9_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|Add19~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add16~9_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~10_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~10 .lut_mask = 16'h5FC0; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add12~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add12~0_combout = (\hdmi_ctrl_inst|encode_inst0|data_in_reg [3] & ((!\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]))) # (!\hdmi_ctrl_inst|encode_inst0|data_in_reg [3] & (\hdmi_ctrl_inst|encode_inst0|data_in_reg [4])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add12~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add12~0 .lut_mask = 16'h0CFC; +defparam \hdmi_ctrl_inst|encode_inst0|Add12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N29 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n1[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add12~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add14~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add14~1_combout = (\hdmi_ctrl_inst|encode_inst0|data_in_reg [3] & (\hdmi_ctrl_inst|encode_inst0|data_in_reg [4] $ (!\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add14~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add14~1 .lut_mask = 16'hC030; +defparam \hdmi_ctrl_inst|encode_inst0|Add14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N19 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n0[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add14~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~13_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add22~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add22~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~13_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~13 .lut_mask = 16'hAF44; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~14 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~14_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~13_combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~13_combout & +// (\hdmi_ctrl_inst|encode_inst0|Add19~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|Add16~13_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add19~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add16~13_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~14_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~14 .lut_mask = 16'h5F88; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y22_N1 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n1[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~15_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] & ((\hdmi_ctrl_inst|encode_inst0|Add17~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] & +// (\hdmi_ctrl_inst|encode_inst0|Add15~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add17~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~15 .lut_mask = 16'hA088; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal2~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])))) # +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~0 .lut_mask = 16'h8421; +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal2~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal2~1_combout = (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~1 .lut_mask = 16'h0F00; +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[0]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout = CARRY((\hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ) # (\hdmi_ctrl_inst|encode_inst0|Equal2~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Equal2~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~6 .lut_mask = 16'h00EE; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[3]~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout = ((\hdmi_ctrl_inst|encode_inst0|Add16~4_combout $ (\hdmi_ctrl_inst|encode_inst0|Add16~6_combout $ (!\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|cnt[3]~14 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~4_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~6_combout ) # (!\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~4_combout & +// (\hdmi_ctrl_inst|encode_inst0|Add16~6_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[3]~14 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3]~13 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add4~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add4~1_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout )) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add4~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add4~1 .lut_mask = 16'hA000; +defparam \hdmi_ctrl_inst|encode_inst0|Add4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N17 +dffeas \hdmi_ctrl_inst|encode_inst2|de_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add4~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|de_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|de_reg1 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|de_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout = \hdmi_ctrl_inst|encode_inst2|de_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|de_reg1~q ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N1 +dffeas \hdmi_ctrl_inst|encode_inst2|de_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N13 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_2~combout = (\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout & (((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3]))) # +// (!\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_2 .lut_mask = 16'h3B0A; +defparam \hdmi_ctrl_inst|encode_inst0|condition_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~6_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~5_combout ) # ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~5_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~6 .lut_mask = 16'hBFAA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[4]~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout = \hdmi_ctrl_inst|encode_inst0|Add16~1_combout $ (\hdmi_ctrl_inst|encode_inst0|cnt[3]~14 $ (\hdmi_ctrl_inst|encode_inst0|Add16~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|Add16~2_combout ), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[3]~14 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4]~15 .lut_mask = 16'hA55A; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X38_Y22_N15 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_3~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_3~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & \hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]))) # +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]) # ((!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & \hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~0 .lut_mask = 16'h7150; +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_3~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_3~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (((\hdmi_ctrl_inst|encode_inst0|cnt [4])))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|cnt [4] & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [4] & (\hdmi_ctrl_inst|encode_inst0|condition_3~1_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~2 .lut_mask = 16'hF2C2; +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~1_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [1] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_reg [1]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~1 .lut_mask = 16'h87D2; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~1_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~0_combout = (\vga_ctrl_inst|cnt_h [7]) # ((\vga_ctrl_inst|cnt_h [10]) # ((\vga_ctrl_inst|cnt_h [9]) # (\vga_ctrl_inst|cnt_h [11]))) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(\vga_ctrl_inst|cnt_h [11]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~0 .lut_mask = 16'hFFFE; +defparam \vga_ctrl_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~1_combout = (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|LessThan0~0_combout & ((!\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|cnt_h [6])))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|cnt_h [5]), + .datad(\vga_ctrl_inst|LessThan0~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~1 .lut_mask = 16'h0015; +defparam \vga_ctrl_inst|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y20_N27 +dffeas \hdmi_ctrl_inst|encode_inst2|c0_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|LessThan0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c0_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg1 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y20_N25 +dffeas \hdmi_ctrl_inst|encode_inst2|c0_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y22_N9 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m[7]~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout = \hdmi_ctrl_inst|encode_inst0|data_in_reg [4] $ (\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m[7]~1 .lut_mask = 16'h33CC; +defparam \hdmi_ctrl_inst|encode_inst0|q_m[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N25 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~4_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [5] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_reg [5]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~4 .lut_mask = 16'hC35A; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N29 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan1~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan1~0_combout = (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [3] & \vga_ctrl_inst|always1~1_combout ))) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|always1~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan1~0 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|LessThan1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N15 +dffeas \hdmi_ctrl_inst|encode_inst2|c1_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|LessThan1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c1_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg1 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout = \hdmi_ctrl_inst|encode_inst2|c1_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|c1_reg1~q ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N5 +dffeas \hdmi_ctrl_inst|encode_inst2|c1_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~7_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst2|c0_reg2~q $ +// (!\hdmi_ctrl_inst|encode_inst2|c1_reg2~q )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~7 .lut_mask = 16'hACA3; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N5 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [9]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[9] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout = (\hdmi_ctrl_inst|encode_inst0|data_out [9] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [9]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4 .lut_mask = 16'hC0C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N1 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [3]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N7 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out [3]), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1 .lut_mask = 16'hAFA0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [1])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [1]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y22_N25 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~3_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~3 .lut_mask = 16'hA3A3; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N17 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst0|data_out [2]))) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [2])) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1 .lut_mask = 16'hCACA; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N21 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [0])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_out [0]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0 .lut_mask = 16'hF3C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N9 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y22_N18 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N16 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~2 ( +// Equation(s): +// \vga_pic_inst|LessThan17~2_combout = (!\vga_ctrl_inst|Add2~12_combout & (!\vga_ctrl_inst|Add2~10_combout & \vga_ctrl_inst|pix_data_req~7_combout )) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~2 .lut_mask = 16'h1010; +defparam \vga_pic_inst|LessThan17~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data[9]~15 ( +// Equation(s): +// \vga_pic_inst|pix_data[9]~15_combout = (\vga_pic_inst|pix_data[9]~14_combout & (!\vga_ctrl_inst|Add2~18_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_pic_inst|LessThan17~2_combout ))) + + .dataa(\vga_pic_inst|pix_data[9]~14_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|LessThan17~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[9]~15_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9]~15 .lut_mask = 16'h0200; +defparam \vga_pic_inst|pix_data[9]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~35 ( +// Equation(s): +// \vga_pic_inst|pix_data~35_combout = (\vga_pic_inst|LessThan10~0_combout ) # ((\vga_ctrl_inst|Add2~18_combout ) # ((\vga_pic_inst|pix_data[13]~11_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ))) + + .dataa(\vga_pic_inst|LessThan10~0_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[13]~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~35_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~35 .lut_mask = 16'hFFEF; +defparam \vga_pic_inst|pix_data~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~36 ( +// Equation(s): +// \vga_pic_inst|pix_data~36_combout = (\vga_pic_inst|always0~2_combout & (!\vga_ctrl_inst|Add2~20_combout & (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_pic_inst|pix_data[9]~15_combout ))) + + .dataa(\vga_pic_inst|always0~2_combout ), + .datab(\vga_ctrl_inst|Add2~20_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[9]~15_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~36_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~36 .lut_mask = 16'h0020; +defparam \vga_pic_inst|pix_data~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N6 +cycloneive_lcell_comb \vga_pic_inst|pix_data~21 ( +// Equation(s): +// \vga_pic_inst|pix_data~21_combout = (\vga_pic_inst|pix_data~12_combout & (!\vga_ctrl_inst|Add2~12_combout & ((\vga_pic_inst|LessThan14~0_combout ) # (\vga_pic_inst|always0~0_combout )))) + + .dataa(\vga_pic_inst|LessThan14~0_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_ctrl_inst|Add2~12_combout ), + .datad(\vga_pic_inst|always0~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~21_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~21 .lut_mask = 16'h0C08; +defparam \vga_pic_inst|pix_data~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N22 +cycloneive_lcell_comb \vga_pic_inst|pix_data~26 ( +// Equation(s): +// \vga_pic_inst|pix_data~26_combout = (\vga_pic_inst|pix_data~36_combout & ((\vga_pic_inst|pix_data~25_combout ) # ((\vga_pic_inst|pix_data~35_combout & \vga_pic_inst|pix_data~21_combout )))) + + .dataa(\vga_pic_inst|pix_data~25_combout ), + .datab(\vga_pic_inst|pix_data~35_combout ), + .datac(\vga_pic_inst|pix_data~36_combout ), + .datad(\vga_pic_inst|pix_data~21_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~26_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~26 .lut_mask = 16'hE0A0; +defparam \vga_pic_inst|pix_data~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|pix_x[11]~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_x[11]~0_combout = (\vga_ctrl_inst|Add2~20_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~20_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_x[11]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_x[11]~0 .lut_mask = 16'hFF0F; +defparam \vga_ctrl_inst|pix_x[11]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N8 +cycloneive_lcell_comb \vga_pic_inst|pix_data~27 ( +// Equation(s): +// \vga_pic_inst|pix_data~27_combout = (\vga_pic_inst|pix_data~26_combout ) # ((!\vga_pic_inst|always0~2_combout & (!\vga_pic_inst|pix_data[9]~15_combout & !\vga_ctrl_inst|pix_x[11]~0_combout ))) + + .dataa(\vga_pic_inst|always0~2_combout ), + .datab(\vga_pic_inst|pix_data[9]~15_combout ), + .datac(\vga_pic_inst|pix_data~26_combout ), + .datad(\vga_ctrl_inst|pix_x[11]~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~27_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~27 .lut_mask = 16'hF0F1; +defparam \vga_pic_inst|pix_data~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y21_N9 +dffeas \vga_pic_inst|pix_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[10] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N14 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[10]~2 ( +// Equation(s): +// \vga_ctrl_inst|rgb[10]~2_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_pic_inst|pix_data [10] & \vga_ctrl_inst|pix_data_req~1_combout ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(\vga_pic_inst|pix_data [10]), + .datad(\vga_ctrl_inst|pix_data_req~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[10]~2 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N15 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[10]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[7] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~29 ( +// Equation(s): +// \vga_pic_inst|pix_data~29_combout = (\vga_ctrl_inst|pix_data_req~7_combout & ((\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~10_combout & !\vga_ctrl_inst|Add2~12_combout )) # (!\vga_ctrl_inst|Add2~14_combout & +// ((\vga_ctrl_inst|Add2~12_combout ))))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~29_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~29 .lut_mask = 16'h5020; +defparam \vga_pic_inst|pix_data~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~30 ( +// Equation(s): +// \vga_pic_inst|pix_data~30_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~20_combout & (!\vga_ctrl_inst|Add2~16_combout & !\vga_ctrl_inst|Add2~18_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_ctrl_inst|Add2~20_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~18_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~30_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~30 .lut_mask = 16'h0002; +defparam \vga_pic_inst|pix_data~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~31 ( +// Equation(s): +// \vga_pic_inst|pix_data~31_combout = (\vga_pic_inst|LessThan17~3_combout ) # ((\vga_pic_inst|pix_data~29_combout & \vga_pic_inst|pix_data~30_combout )) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data~29_combout ), + .datac(\vga_pic_inst|pix_data~30_combout ), + .datad(\vga_pic_inst|LessThan17~3_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~31_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~31 .lut_mask = 16'hFFC0; +defparam \vga_pic_inst|pix_data~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y21_N5 +dffeas \vga_pic_inst|pix_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[8] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N4 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[6]~4 ( +// Equation(s): +// \vga_ctrl_inst|rgb[6]~4_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~4_combout & \vga_pic_inst|pix_data [8]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[6]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[6]~4 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[6]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N5 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[6]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add5~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add5~0_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~1_combout & (\vga_pic_inst|pix_data [8] & ((\vga_pic_inst|pix_data [9]) # (\vga_pic_inst|pix_data [10])))) + + .dataa(\vga_pic_inst|pix_data [9]), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~1_combout ), + .datac(\vga_pic_inst|pix_data [10]), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add5~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add5~0 .lut_mask = 16'hC800; +defparam \hdmi_ctrl_inst|encode_inst1|Add5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N27 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add14~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add14~1_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])))) # +// (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add14~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add14~1 .lut_mask = 16'h6006; +defparam \hdmi_ctrl_inst|encode_inst1|Add14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N25 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n0[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add14~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~28 ( +// Equation(s): +// \vga_pic_inst|pix_data~28_combout = (\vga_pic_inst|pix_data~36_combout & ((\vga_pic_inst|pix_data~25_combout ) # ((\vga_pic_inst|pix_data~35_combout & \vga_pic_inst|pix_data~21_combout )))) + + .dataa(\vga_pic_inst|pix_data~25_combout ), + .datab(\vga_pic_inst|pix_data~35_combout ), + .datac(\vga_pic_inst|pix_data~36_combout ), + .datad(\vga_pic_inst|pix_data~21_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~28_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~28 .lut_mask = 16'hE0A0; +defparam \vga_pic_inst|pix_data~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y21_N3 +dffeas \vga_pic_inst|pix_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N8 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[7]~3 ( +// Equation(s): +// \vga_ctrl_inst|rgb[7]~3_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~4_combout & \vga_pic_inst|pix_data [9]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|pix_data [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[7]~3 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N9 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[7]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add13~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add13~0_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [4])) # (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & +// ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]))))) # (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]))) # (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & +// (\hdmi_ctrl_inst|encode_inst1|data_in_reg [4])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add13~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add13~0 .lut_mask = 16'hF690; +defparam \hdmi_ctrl_inst|encode_inst1|Add13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N13 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n1[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add13~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add13~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add13~1_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & \hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])) # (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & +// ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]) # (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add13~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add13~1 .lut_mask = 16'hF330; +defparam \hdmi_ctrl_inst|encode_inst1|Add13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N29 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add13~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_3~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_3~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & !\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~0 .lut_mask = 16'h08AE; +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_3~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_3~1_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]) # ((!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~1 .lut_mask = 16'h7510; +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add14~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add14~2_combout = (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & !\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add14~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add14~2 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst1|Add14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n0[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add14~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X33_Y21_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n1[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~0_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add15~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [0] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~4_combout = ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] $ (\hdmi_ctrl_inst|encode_inst1|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst1|Add15~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|Add15~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst1|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst1|Add15~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst1|Add15~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add14~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add14~0_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & (((!\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & !\hdmi_ctrl_inst|encode_inst1|data_in_reg [7])) # (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]) # ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]) # (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add14~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add14~0 .lut_mask = 16'h37FE; +defparam \hdmi_ctrl_inst|encode_inst1|Add14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N17 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n0[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add14~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// (\hdmi_ctrl_inst|encode_inst1|Add23~1 & VCC)))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst1|Add23~1 ) # (GND))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst1|Add23~1 )))) +// \hdmi_ctrl_inst|encode_inst1|Add23~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst1|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & +// ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst1|Add23~1 )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add23~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add23~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~2 .lut_mask = 16'h694D; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~9_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add17~4_combout ) # (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add23~2_combout & ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add23~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add17~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~9_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~9 .lut_mask = 16'hAAE4; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~10 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~10_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~9_combout & (((\hdmi_ctrl_inst|encode_inst1|Add15~4_combout ) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|Add16~9_combout & (\hdmi_ctrl_inst|encode_inst1|Add20~2_combout & ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add20~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add15~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~9_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~10_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~10 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout = !\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2] + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N23 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~15_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|Add17~0_combout )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & +// ((\hdmi_ctrl_inst|encode_inst1|Add15~0_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add17~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add15~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~15 .lut_mask = 16'hA0C0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[0]~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & (\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & +// (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & +// ((\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|cnt[0]~8 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & +// ((!\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ) # (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~16_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~15_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~7 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal1~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal1~0_combout = (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & (!\hdmi_ctrl_inst|encode_inst1|cnt [0] & (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & !\hdmi_ctrl_inst|encode_inst1|cnt [4]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .datac(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~0 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal1~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal1~1_combout = (\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout & !\hdmi_ctrl_inst|encode_inst1|cnt [3]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~1 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[0]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout = CARRY((\hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ) # (\hdmi_ctrl_inst|encode_inst1|Equal1~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Equal1~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~6 .lut_mask = 16'h00EE; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[1]~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout = ((\hdmi_ctrl_inst|encode_inst1|Add16~14_combout $ (\hdmi_ctrl_inst|encode_inst1|Add16~12_combout $ (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|cnt[1]~10 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~14_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~12_combout ) # (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~14_combout & +// (\hdmi_ctrl_inst|encode_inst1|Add16~12_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~14_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~12_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1]~9 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[2]~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & (\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & +// (!\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & (!\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & +// ((\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|cnt[2]~12 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & +// ((!\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ) # (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2]~11 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N15 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~3_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst1|Add20~4_combout )) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst1|Add23~4_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add20~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add23~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~3 .lut_mask = 16'hEE50; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~4_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~3_combout & (((\hdmi_ctrl_inst|encode_inst1|Add15~6_combout ) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~3_combout +// & (\hdmi_ctrl_inst|encode_inst1|Add17~6_combout & ((\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add17~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add15~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~3_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~4 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[3]~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout = ((\hdmi_ctrl_inst|encode_inst1|Add16~6_combout $ (\hdmi_ctrl_inst|encode_inst1|Add16~4_combout $ (!\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|cnt[3]~14 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~6_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~4_combout ) # (!\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~6_combout & +// (\hdmi_ctrl_inst|encode_inst1|Add16~4_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[3]~14 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3]~13 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N17 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal2~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal2~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] $ (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) # +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] $ (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~0 .lut_mask = 16'h8241; +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_2~combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & +// ((\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ) # ((!\hdmi_ctrl_inst|encode_inst1|cnt [3] & \hdmi_ctrl_inst|encode_inst1|Equal1~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datac(\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_2 .lut_mask = 16'h7350; +defparam \hdmi_ctrl_inst|encode_inst1|condition_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[0]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0]~0 .lut_mask = 16'h22EE; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~11_combout = (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst1|Add19~0_combout ) # (\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst1|Add22~0_combout & ((!\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add22~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add19~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~11_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~11 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~12 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~12_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~11_combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~11_combout & +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1])))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add16~11_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|Add16~11_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~12_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~12 .lut_mask = 16'h5F22; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y21_N13 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~6_combout = \hdmi_ctrl_inst|encode_inst1|Add22~5 $ (!\hdmi_ctrl_inst|encode_inst1|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst1|Add22~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~6 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~2_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout ) # ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst1|Add19~6_combout )) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst1|Add22~6_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add19~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add22~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~2 .lut_mask = 16'hFFAC; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[4]~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout = \hdmi_ctrl_inst|encode_inst1|Add16~1_combout $ (\hdmi_ctrl_inst|encode_inst1|cnt[3]~14 $ (\hdmi_ctrl_inst|encode_inst1|Add16~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|Add16~2_combout ), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[3]~14 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4]~15 .lut_mask = 16'hA55A; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N19 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_3~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_3~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (((\hdmi_ctrl_inst|encode_inst1|cnt [4])))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst1|cnt [4] & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~0_combout )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [4] & ((\hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~2 .lut_mask = 16'hEE50; +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N19 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~1_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [3] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~1 .lut_mask = 16'hA53C; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out~1_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N1 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~3_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [5] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [5]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~3 .lut_mask = 16'h9A56; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~3_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out~3_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N29 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst1|data_out [5]))) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [3])) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2 .lut_mask = 16'hCACA; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N21 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [2]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [3]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [3]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~7_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~7 .lut_mask = 16'hAF05; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N29 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout = (\hdmi_ctrl_inst|encode_inst1|data_out [8] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4 .lut_mask = 16'hCC00; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N27 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [2])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [4]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [2]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [4]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N23 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [4])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [3]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [4]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [3]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N19 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [2])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [2]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1 .lut_mask = 16'hBB88; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [0])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [1]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [0]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [1]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y23_N11 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~33 ( +// Equation(s): +// \vga_pic_inst|pix_data~33_combout = (\vga_pic_inst|pix_data~37_combout & ((\vga_pic_inst|pix_data[13]~10_combout ) # (\vga_pic_inst|pix_data~19_combout ))) + + .dataa(\vga_pic_inst|pix_data~37_combout ), + .datab(\vga_pic_inst|pix_data[13]~10_combout ), + .datac(gnd), + .datad(\vga_pic_inst|pix_data~19_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~33_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~33 .lut_mask = 16'hAA88; +defparam \vga_pic_inst|pix_data~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N15 +dffeas \vga_pic_inst|pix_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N22 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[13]~6 ( +// Equation(s): +// \vga_ctrl_inst|rgb[13]~6_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_pic_inst|pix_data [13] & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_pic_inst|pix_data [13]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[13]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[13]~6 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[13]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N23 +dffeas \hdmi_ctrl_inst|encode_inst2|data_in_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[13]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~32 ( +// Equation(s): +// \vga_pic_inst|pix_data~32_combout = (\vga_pic_inst|pix_data~37_combout & (!\vga_ctrl_inst|pix_x[11]~0_combout & ((\vga_pic_inst|pix_data[13]~9_combout ) # (!\vga_pic_inst|pix_data~13_combout )))) + + .dataa(\vga_pic_inst|pix_data~37_combout ), + .datab(\vga_pic_inst|pix_data~13_combout ), + .datac(\vga_pic_inst|pix_data[13]~9_combout ), + .datad(\vga_ctrl_inst|pix_x[11]~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~32_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~32 .lut_mask = 16'h00A2; +defparam \vga_pic_inst|pix_data~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N5 +dffeas \vga_pic_inst|pix_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~32_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[15] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add6~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add6~0_combout = (\vga_ctrl_inst|pix_data_req~3_combout & (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_pic_inst|pix_data [13] & \vga_pic_inst|pix_data [15]))) + + .dataa(\vga_ctrl_inst|pix_data_req~3_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datac(\vga_pic_inst|pix_data [13]), + .datad(\vga_pic_inst|pix_data [15]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add6~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add6~0 .lut_mask = 16'h8000; +defparam \hdmi_ctrl_inst|encode_inst2|Add6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N27 +dffeas \hdmi_ctrl_inst|encode_inst2|data_in_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_in_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_in_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N20 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[12]~5 ( +// Equation(s): +// \vga_ctrl_inst|rgb[12]~5_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_pic_inst|pix_data [15] & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_pic_inst|pix_data [15]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[12]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[12]~5 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[12]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N21 +dffeas \hdmi_ctrl_inst|encode_inst2|data_in_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[12]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add12~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add12~0_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3] & (!\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2])) # (!\hdmi_ctrl_inst|encode_inst2|data_in_reg [3] & ((\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add12~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add12~0 .lut_mask = 16'h3F0C; +defparam \hdmi_ctrl_inst|encode_inst2|Add12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N5 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n1[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add12~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add14~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add14~0_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]) # ((\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]) # (\hdmi_ctrl_inst|encode_inst2|data_in_reg [4])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add14~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add14~0 .lut_mask = 16'hFFFC; +defparam \hdmi_ctrl_inst|encode_inst2|Add14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N1 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n0[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add14~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add12~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add12~1_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] & !\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add12~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add12~1 .lut_mask = 16'h00F0; +defparam \hdmi_ctrl_inst|encode_inst2|Add12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N23 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add12~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_3~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_3~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & !\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~0 .lut_mask = 16'h20F2; +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout = !\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N7 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal2~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal2~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] $ (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2])))) # +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] $ (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~0 .lut_mask = 16'h9009; +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~0_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add19~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [1] & \hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add19~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~5_combout = (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst2|Add19~4_combout ))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst2|Add22~4_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add22~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add19~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~5 .lut_mask = 16'h0C0A; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~6_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~5_combout ) # ((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~5_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~6 .lut_mask = 16'hF7F0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal1~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal1~0_combout = (!\hdmi_ctrl_inst|encode_inst2|cnt [4] & (!\hdmi_ctrl_inst|encode_inst2|cnt [0] & (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & !\hdmi_ctrl_inst|encode_inst2|cnt [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~0 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal1~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal1~1_combout = (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & \hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~1 .lut_mask = 16'h0F00; +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[0]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout = CARRY((\hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ) # (\hdmi_ctrl_inst|encode_inst2|Equal1~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Equal1~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~6 .lut_mask = 16'h00EE; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[0]~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & (\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & +// (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & +// ((\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|cnt[0]~8 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & +// ((!\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ) # (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~16_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~15_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~7 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y24_N3 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & (\hdmi_ctrl_inst|encode_inst2|cnt [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & (\hdmi_ctrl_inst|encode_inst2|cnt [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add15~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & \hdmi_ctrl_inst|encode_inst2|cnt [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~15_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst2|Add17~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] & +// ((\hdmi_ctrl_inst|encode_inst2|Add15~0_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add17~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add15~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~15 .lut_mask = 16'hAC00; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[1]~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout = ((\hdmi_ctrl_inst|encode_inst2|Add16~12_combout $ (\hdmi_ctrl_inst|encode_inst2|Add16~14_combout $ (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|cnt[1]~10 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~12_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~14_combout ) # (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~12_combout & +// (\hdmi_ctrl_inst|encode_inst2|Add16~14_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~12_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1]~9 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[2]~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & (\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & +// (!\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & (!\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & +// ((\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|cnt[2]~12 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & +// ((!\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ) # (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~10_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~8_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2]~11 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[3]~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout = ((\hdmi_ctrl_inst|encode_inst2|Add16~4_combout $ (\hdmi_ctrl_inst|encode_inst2|Add16~6_combout $ (!\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|cnt[3]~14 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~4_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~6_combout ) # (!\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~4_combout & +// (\hdmi_ctrl_inst|encode_inst2|Add16~6_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[3]~14 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3]~13 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y24_N9 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout = !\hdmi_ctrl_inst|encode_inst2|Add14~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|Add14~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0 .lut_mask = 16'h00FF; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N3 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n0[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_2~combout = (\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout & (((\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout & !\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3]))) # +// (!\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout & (\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_2 .lut_mask = 16'h0ACE; +defparam \hdmi_ctrl_inst|encode_inst2|condition_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[0]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0]~0 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~14 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~14_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~13_combout & (((!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~13_combout +// & (\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst2|Add19~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~13_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst2|Add19~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~14_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~14 .lut_mask = 16'h6E2A; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N5 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst2|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// (\hdmi_ctrl_inst|encode_inst2|Add23~1 & VCC)))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst2|Add23~1 ) # (GND))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst2|Add23~1 )))) +// \hdmi_ctrl_inst|encode_inst2|Add23~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst2|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & +// ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst2|Add23~1 )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add23~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add23~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~2 .lut_mask = 16'h694D; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst2|Add20~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// ((\hdmi_ctrl_inst|encode_inst2|Add20~1 ) # (GND))))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst2|Add20~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst2|Add20~1 )))) +// \hdmi_ctrl_inst|encode_inst2|Add20~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((!\hdmi_ctrl_inst|encode_inst2|Add20~1 ) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst2|Add20~1 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add20~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add20~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~2 .lut_mask = 16'h692B; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~7_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst2|Add20~2_combout ))) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst2|Add23~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add23~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add20~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~7 .lut_mask = 16'hFA44; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~8_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~7_combout & (((\hdmi_ctrl_inst|encode_inst2|Add15~4_combout ) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~7_combout +// & (\hdmi_ctrl_inst|encode_inst2|Add17~4_combout & ((\hdmi_ctrl_inst|encode_inst2|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add17~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add15~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~7_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~8 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N7 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y24_N9 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n1[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~8_combout = \hdmi_ctrl_inst|encode_inst2|Add17~7 $ (!\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~7 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~8 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~6_combout = !\hdmi_ctrl_inst|encode_inst2|Add23~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst2|Add23~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~0_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|Add17~8_combout ) # ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|Add23~6_combout & !\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add17~8_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add23~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~0 .lut_mask = 16'hAAD8; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~6_combout = !\hdmi_ctrl_inst|encode_inst2|Add20~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst2|Add20~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~1_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~0_combout & ((\hdmi_ctrl_inst|encode_inst2|Add15~8_combout ) # ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~0_combout +// & (((\hdmi_ctrl_inst|encode_inst2|Add20~6_combout & \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add15~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add20~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~1 .lut_mask = 16'hB8CC; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[4]~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout = \hdmi_ctrl_inst|encode_inst2|Add16~2_combout $ (\hdmi_ctrl_inst|encode_inst2|cnt[3]~14 $ (\hdmi_ctrl_inst|encode_inst2|Add16~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|Add16~1_combout ), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[3]~14 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4]~15 .lut_mask = 16'hA55A; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y24_N11 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_3~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_3~2_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [4] & (((\hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ) # (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [4] & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~1_combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~2 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N21 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~1_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [1] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [1]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~1 .lut_mask = 16'hB41E; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out~1_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N1 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m[7]~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout = \hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] $ (\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m[7]~1 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst2|q_m[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N29 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~4_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [5] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [5]), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~4 .lut_mask = 16'h939C; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N17 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~7_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst2|c1_reg2~q $ +// ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~7 .lut_mask = 16'hEB41; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N19 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [9]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[9] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout = (\hdmi_ctrl_inst|encode_inst2|data_out [9] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [9]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4 .lut_mask = 16'hC0C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [4]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3 .lut_mask = 16'hCCF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N9 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [3]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [3]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2 .lut_mask = 16'hCCF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N5 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [3]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [1])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [1]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N21 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y24_N17 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[4]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~6 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout = !\hdmi_ctrl_inst|encode_inst2|c0_reg2~q + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N21 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [6]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[6] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst2|data_out [6]))) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [4])) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [4]), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [6]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3 .lut_mask = 16'hCCAA; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N7 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [4])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [3]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [4]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2 .lut_mask = 16'hBB88; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [2])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [2]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1 .lut_mask = 16'hBB88; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N1 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [0])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [0]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y24_N4 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y22_N25 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y23_N18 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y24_N11 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_8_1200mv_0c_slow.vo b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_8_1200mv_0c_slow.vo new file mode 100644 index 0000000..ec034b8 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_8_1200mv_0c_slow.vo @@ -0,0 +1,11443 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:17:19" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module hdmi_colorbar ( + sys_clk, + sys_rst_n, + ddc_scl, + ddc_sda, + tmds_clk_p, + tmds_clk_n, + tmds_data_p, + tmds_data_n); +input sys_clk; +input sys_rst_n; +output ddc_scl; +output ddc_sda; +output tmds_clk_p; +output tmds_clk_n; +output [2:0] tmds_data_p; +output [2:0] tmds_data_n; + +// Design Ports Information +// ddc_scl => Location: PIN_N22, I/O Standard: 2.5 V, Current Strength: Default +// ddc_sda => Location: PIN_R22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_clk_p => Location: PIN_H21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_clk_n => Location: PIN_H22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_p[0] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_p[1] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_p[2] => Location: PIN_D21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_n[0] => Location: PIN_F22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_n[1] => Location: PIN_E22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_n[2] => Location: PIN_D22, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("hdmi_colorbar_8_1200mv_0c_v_slow.sdo"); +// synopsys translate_on + +wire \hdmi_ctrl_inst|encode_inst0|Add20~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~7 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~8_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~7 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~8_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~7 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~7 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~7 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~8_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~6_combout ; +wire \vga_ctrl_inst|Add0~2_combout ; +wire \vga_ctrl_inst|Add0~10_combout ; +wire \vga_ctrl_inst|Add1~2_combout ; +wire \vga_ctrl_inst|Add1~6_combout ; +wire \vga_ctrl_inst|Add1~8_combout ; +wire \vga_ctrl_inst|Add1~10_combout ; +wire \vga_ctrl_inst|Add1~12_combout ; +wire \vga_ctrl_inst|Add1~14_combout ; +wire \vga_ctrl_inst|Add1~16_combout ; +wire \vga_ctrl_inst|Add1~18_combout ; +wire \vga_ctrl_inst|Add1~20_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|condition_3~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_3~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~3_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~5_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~7_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~8_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~11_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~12_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~16_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add12~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~5_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~7_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~13_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~14_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~16_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~3_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~9_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~10_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~11_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~12_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~13_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~16_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add14~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~3_combout ; +wire \vga_ctrl_inst|pix_data_req~0_combout ; +wire \vga_ctrl_inst|pix_data_req~3_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~5_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~5_combout ; +wire \vga_ctrl_inst|pix_x[10]~1_combout ; +wire \vga_pic_inst|always0~1_combout ; +wire \vga_pic_inst|always0~2_combout ; +wire \vga_pic_inst|pix_data[9]~14_combout ; +wire \vga_pic_inst|pix_data~16_combout ; +wire \vga_ctrl_inst|pix_data_req~8_combout ; +wire \vga_ctrl_inst|cnt_v[10]~12_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout ; +wire \vga_pic_inst|LessThan10~0_combout ; +wire \vga_pic_inst|pix_data~22_combout ; +wire \vga_pic_inst|pix_data~23_combout ; +wire \vga_pic_inst|LessThan14~1_combout ; +wire \vga_pic_inst|pix_data[13]~24_combout ; +wire \vga_pic_inst|pix_data~25_combout ; +wire \hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~5_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~8_combout ; +wire \vga_pic_inst|pix_data~37_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~1 ; +wire \vga_ctrl_inst|Add0~3 ; +wire \vga_ctrl_inst|Add0~5 ; +wire \vga_ctrl_inst|Add0~6_combout ; +wire \vga_ctrl_inst|Add0~7 ; +wire \vga_ctrl_inst|Add0~8_combout ; +wire \vga_ctrl_inst|Add0~9 ; +wire \vga_ctrl_inst|Add0~11 ; +wire \vga_ctrl_inst|Add0~12_combout ; +wire \vga_ctrl_inst|Add0~13 ; +wire \vga_ctrl_inst|Add0~14_combout ; +wire \vga_ctrl_inst|Add0~4_combout ; +wire \vga_ctrl_inst|Equal0~0_combout ; +wire \vga_ctrl_inst|Add0~15 ; +wire \vga_ctrl_inst|Add0~16_combout ; +wire \vga_ctrl_inst|Add0~19 ; +wire \vga_ctrl_inst|Add0~20_combout ; +wire \vga_ctrl_inst|Add0~21 ; +wire \vga_ctrl_inst|Add0~22_combout ; +wire \vga_ctrl_inst|Equal0~1_combout ; +wire \vga_ctrl_inst|cnt_h~0_combout ; +wire \vga_ctrl_inst|Equal0~2_combout ; +wire \vga_ctrl_inst|cnt_h~2_combout ; +wire \vga_ctrl_inst|Add0~17 ; +wire \vga_ctrl_inst|Add0~18_combout ; +wire \vga_ctrl_inst|cnt_h~1_combout ; +wire \vga_ctrl_inst|LessThan4~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ; +wire \vga_ctrl_inst|Add2~1_cout ; +wire \vga_ctrl_inst|Add2~3_cout ; +wire \vga_ctrl_inst|Add2~5_cout ; +wire \vga_ctrl_inst|Add2~7_cout ; +wire \vga_ctrl_inst|Add2~9_cout ; +wire \vga_ctrl_inst|Add2~11 ; +wire \vga_ctrl_inst|Add2~13 ; +wire \vga_ctrl_inst|Add2~15 ; +wire \vga_ctrl_inst|Add2~17 ; +wire \vga_ctrl_inst|Add2~18_combout ; +wire \vga_ctrl_inst|Add2~16_combout ; +wire \vga_ctrl_inst|Add2~14_combout ; +wire \vga_pic_inst|pix_data~12_combout ; +wire \vga_ctrl_inst|Add2~12_combout ; +wire \vga_ctrl_inst|pix_data_req~5_combout ; +wire \vga_ctrl_inst|Equal0~3_combout ; +wire \vga_ctrl_inst|cnt_v[7]~7_combout ; +wire \vga_ctrl_inst|cnt_v[5]~10_combout ; +wire \vga_ctrl_inst|cnt_v[8]~6_combout ; +wire \vga_ctrl_inst|always1~0_combout ; +wire \vga_ctrl_inst|cnt_v[1]~1_combout ; +wire \vga_ctrl_inst|cnt_v[4]~5_combout ; +wire \vga_ctrl_inst|always1~1_combout ; +wire \vga_ctrl_inst|Add1~0_combout ; +wire \vga_ctrl_inst|cnt_v[0]~2_combout ; +wire \vga_ctrl_inst|cnt_v[3]~3_combout ; +wire \vga_ctrl_inst|always1~2_combout ; +wire \vga_ctrl_inst|cnt_v[11]~0_combout ; +wire \vga_ctrl_inst|cnt_v[9]~9_combout ; +wire \vga_ctrl_inst|cnt_v[6]~8_combout ; +wire \vga_ctrl_inst|Add1~1 ; +wire \vga_ctrl_inst|Add1~3 ; +wire \vga_ctrl_inst|Add1~4_combout ; +wire \vga_ctrl_inst|cnt_v[2]~4_combout ; +wire \vga_ctrl_inst|Add1~5 ; +wire \vga_ctrl_inst|Add1~7 ; +wire \vga_ctrl_inst|Add1~9 ; +wire \vga_ctrl_inst|Add1~11 ; +wire \vga_ctrl_inst|Add1~13 ; +wire \vga_ctrl_inst|Add1~15 ; +wire \vga_ctrl_inst|Add1~17 ; +wire \vga_ctrl_inst|Add1~19 ; +wire \vga_ctrl_inst|Add1~21 ; +wire \vga_ctrl_inst|Add1~22_combout ; +wire \vga_ctrl_inst|cnt_v[11]~11_combout ; +wire \vga_ctrl_inst|pix_data_req~2_combout ; +wire \vga_ctrl_inst|pix_data_req~4_combout ; +wire \vga_ctrl_inst|pix_data_req~6_combout ; +wire \vga_ctrl_inst|pix_data_req~7_combout ; +wire \vga_pic_inst|pix_data[13]~11_combout ; +wire \vga_pic_inst|always0~0_combout ; +wire \vga_pic_inst|pix_data~13_combout ; +wire \vga_pic_inst|pix_data~17_combout ; +wire \vga_pic_inst|pix_data~34_combout ; +wire \vga_pic_inst|pix_data[13]~8_combout ; +wire \vga_pic_inst|pix_data[13]~9_combout ; +wire \vga_pic_inst|pix_data[13]~10_combout ; +wire \vga_pic_inst|pix_data~18_combout ; +wire \vga_ctrl_inst|Add2~19 ; +wire \vga_ctrl_inst|Add2~20_combout ; +wire \vga_ctrl_inst|Add2~10_combout ; +wire \vga_pic_inst|LessThan17~4_combout ; +wire \vga_pic_inst|LessThan17~3_combout ; +wire \vga_pic_inst|LessThan14~0_combout ; +wire \vga_pic_inst|pix_data~19_combout ; +wire \vga_pic_inst|pix_data~20_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add6~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout ; +wire \vga_ctrl_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|pix_data_req~1_combout ; +wire \vga_ctrl_inst|rgb[1]~0_combout ; +wire \vga_ctrl_inst|rgb[2]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add14~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~9_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~10_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add12~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add14~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~13_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~14_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~15_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal2~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add4~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|de_reg1~q ; +wire \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|de_reg2~q ; +wire \hdmi_ctrl_inst|encode_inst0|condition_2~combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[3]~14 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout ; +wire \hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout ; +wire \vga_ctrl_inst|LessThan0~0_combout ; +wire \vga_ctrl_inst|LessThan0~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c0_reg1~q ; +wire \hdmi_ctrl_inst|encode_inst2|c0_reg2~q ; +wire \hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout ; +wire \vga_ctrl_inst|LessThan1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c1_reg1~q ; +wire \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c1_reg2~q ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~7_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout ; +wire \vga_pic_inst|LessThan17~2_combout ; +wire \vga_pic_inst|pix_data[9]~15_combout ; +wire \vga_pic_inst|pix_data~35_combout ; +wire \vga_pic_inst|pix_data~36_combout ; +wire \vga_pic_inst|pix_data~21_combout ; +wire \vga_pic_inst|pix_data~26_combout ; +wire \vga_ctrl_inst|pix_x[11]~0_combout ; +wire \vga_pic_inst|pix_data~27_combout ; +wire \vga_ctrl_inst|rgb[10]~2_combout ; +wire \vga_pic_inst|pix_data~29_combout ; +wire \vga_pic_inst|pix_data~30_combout ; +wire \vga_pic_inst|pix_data~31_combout ; +wire \vga_ctrl_inst|rgb[6]~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add5~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add14~1_combout ; +wire \vga_pic_inst|pix_data~28_combout ; +wire \vga_ctrl_inst|rgb[7]~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add13~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add13~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_3~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add14~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add14~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~9_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~10_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~15_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal1~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_2~combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~11_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~12_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[3]~14 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~7_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout ; +wire \vga_pic_inst|pix_data~33_combout ; +wire \vga_ctrl_inst|rgb[13]~6_combout ; +wire \vga_pic_inst|pix_data~32_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add6~0_combout ; +wire \vga_ctrl_inst|rgb[12]~5_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add12~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add14~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add12~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~5_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal1~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~15_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_2~combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~14_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~7_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~8_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~7 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~8_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[3]~14 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~7_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout ; +wire [9:0] \hdmi_ctrl_inst|encode_inst0|data_out ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [11:0] \vga_ctrl_inst|cnt_v ; +wire [11:0] \vga_ctrl_inst|cnt_h ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s ; +wire [7:0] \hdmi_ctrl_inst|encode_inst0|data_in_reg ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [8:0] \hdmi_ctrl_inst|encode_inst0|q_m_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst0|q_m_n1 ; +wire [15:0] \vga_pic_inst|pix_data ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [3:0] \hdmi_ctrl_inst|encode_inst0|data_in_n1 ; +wire [2:0] \hdmi_ctrl_inst|par_to_ser_inst0|cnt ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [3:0] \hdmi_ctrl_inst|encode_inst0|q_m_n0 ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [4:0] \hdmi_ctrl_inst|encode_inst0|cnt ; +wire [4:0] \hdmi_ctrl_inst|encode_inst1|cnt ; +wire [9:0] \hdmi_ctrl_inst|encode_inst1|data_out ; +wire [8:0] \hdmi_ctrl_inst|encode_inst1|q_m_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst1|q_m_n0 ; +wire [3:0] \hdmi_ctrl_inst|encode_inst1|q_m_n1 ; +wire [7:0] \hdmi_ctrl_inst|encode_inst1|data_in_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst1|data_in_n1 ; +wire [4:0] \hdmi_ctrl_inst|encode_inst2|cnt ; +wire [9:0] \hdmi_ctrl_inst|encode_inst2|data_out ; +wire [8:0] \hdmi_ctrl_inst|encode_inst2|q_m_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst2|q_m_n0 ; +wire [3:0] \hdmi_ctrl_inst|encode_inst2|q_m_n1 ; +wire [7:0] \hdmi_ctrl_inst|encode_inst2|data_in_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst2|data_in_n1 ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 10; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 10; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 5; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 10; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 5989; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 250; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: FF_X40_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N7 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N9 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y22_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y23_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y23_N13 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((GND) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add20~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add20~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~0 .lut_mask = 16'h66BB; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst0|Add20~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// ((\hdmi_ctrl_inst|encode_inst0|Add20~1 ) # (GND))))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|Add20~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst0|Add20~1 )))) +// \hdmi_ctrl_inst|encode_inst0|Add20~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((!\hdmi_ctrl_inst|encode_inst0|Add20~1 ) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst0|Add20~1 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add20~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add20~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~2 .lut_mask = 16'h692B; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~4_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst0|Add20~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst0|Add20~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add20~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst0|Add20~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add20~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add20~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~6_combout = !\hdmi_ctrl_inst|encode_inst0|Add20~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add20~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add17~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [0] & \hdmi_ctrl_inst|encode_inst0|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|Add17~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst0|Add17~1 )))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (!\hdmi_ctrl_inst|encode_inst0|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & ((\hdmi_ctrl_inst|encode_inst0|Add17~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|Add17~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & !\hdmi_ctrl_inst|encode_inst0|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & +// ((!\hdmi_ctrl_inst|encode_inst0|Add17~1 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~4_combout = ((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] $ (\hdmi_ctrl_inst|encode_inst0|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst0|Add17~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|Add17~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst0|Add17~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst0|Add17~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~6_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [3] & (!\hdmi_ctrl_inst|encode_inst0|Add17~5 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & ((\hdmi_ctrl_inst|encode_inst0|Add17~5 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add17~7 = CARRY((!\hdmi_ctrl_inst|encode_inst0|Add17~5 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~6 .lut_mask = 16'h3C3F; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~8_combout = \hdmi_ctrl_inst|encode_inst0|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst0|Add17~7 ) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~7 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~8 .lut_mask = 16'hC3C3; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]) # (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add23~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add23~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~0 .lut_mask = 16'h66DD; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst0|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// (\hdmi_ctrl_inst|encode_inst0|Add23~1 & VCC)))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst0|Add23~1 ) # (GND))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst0|Add23~1 )))) +// \hdmi_ctrl_inst|encode_inst0|Add23~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst0|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & +// ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst0|Add23~1 )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add23~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add23~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~2 .lut_mask = 16'h694D; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~4_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst0|Add23~3 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst0|Add23~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add23~5 = CARRY((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst0|Add23~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add23~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add23~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~4 .lut_mask = 16'h5A05; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~6_combout = !\hdmi_ctrl_inst|encode_inst0|Add23~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add23~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add15~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [0] & \hdmi_ctrl_inst|encode_inst0|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|Add15~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst0|Add15~1 )))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (!\hdmi_ctrl_inst|encode_inst0|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & ((\hdmi_ctrl_inst|encode_inst0|Add15~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|Add15~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & !\hdmi_ctrl_inst|encode_inst0|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & +// ((!\hdmi_ctrl_inst|encode_inst0|Add15~1 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~4_combout = ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] $ (\hdmi_ctrl_inst|encode_inst0|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst0|Add15~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|Add15~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst0|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst0|Add15~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst0|Add15~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~6_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|cnt [3] & (\hdmi_ctrl_inst|encode_inst0|Add15~5 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & +// (!\hdmi_ctrl_inst|encode_inst0|Add15~5 )))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|cnt [3] & (!\hdmi_ctrl_inst|encode_inst0|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & ((\hdmi_ctrl_inst|encode_inst0|Add15~5 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|Add15~7 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & !\hdmi_ctrl_inst|encode_inst0|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & +// ((!\hdmi_ctrl_inst|encode_inst0|Add15~5 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~6 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~8_combout = \hdmi_ctrl_inst|encode_inst0|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst0|Add15~7 ) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~7 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~8 .lut_mask = 16'hC3C3; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~4_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [3] & (\hdmi_ctrl_inst|encode_inst0|Add19~3 $ (GND))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & (!\hdmi_ctrl_inst|encode_inst0|Add19~3 & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add19~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [3] & !\hdmi_ctrl_inst|encode_inst0|Add19~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add19~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add19~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~4 .lut_mask = 16'hA50A; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~4_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst0|Add22~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & (\hdmi_ctrl_inst|encode_inst0|Add22~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add22~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [3]) # (!\hdmi_ctrl_inst|encode_inst0|Add22~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add22~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add22~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[0]~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & (\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & +// (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & +// ((\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|cnt[0]~8 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & +// ((!\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ) # (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~16_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~15_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~7 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[1]~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout = ((\hdmi_ctrl_inst|encode_inst0|Add16~12_combout $ (\hdmi_ctrl_inst|encode_inst0|Add16~14_combout $ (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|cnt[1]~10 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~12_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~14_combout ) # (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~12_combout & +// (\hdmi_ctrl_inst|encode_inst0|Add16~14_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~12_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1]~9 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[2]~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & (\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & +// (!\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & (!\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & +// ((\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|cnt[2]~12 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & +// ((!\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ) # (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2]~11 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y22_N31 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((GND) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add20~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add20~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~0 .lut_mask = 16'h66BB; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|Add20~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// ((\hdmi_ctrl_inst|encode_inst1|Add20~1 ) # (GND))))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|Add20~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst1|Add20~1 )))) +// \hdmi_ctrl_inst|encode_inst1|Add20~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((!\hdmi_ctrl_inst|encode_inst1|Add20~1 ) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst1|Add20~1 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add20~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add20~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~2 .lut_mask = 16'h692B; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~4_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst1|Add20~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst1|Add20~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add20~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst1|Add20~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add20~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add20~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~4 .lut_mask = 16'h3CCF; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~6_combout = !\hdmi_ctrl_inst|encode_inst1|Add20~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add20~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~0_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add17~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [0] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~2_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst1|Add17~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & +// (!\hdmi_ctrl_inst|encode_inst1|Add17~1 )))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst1|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & +// ((\hdmi_ctrl_inst|encode_inst1|Add17~1 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|Add17~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [1] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst1|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((!\hdmi_ctrl_inst|encode_inst1|Add17~1 ) +// # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~4_combout = ((\hdmi_ctrl_inst|encode_inst1|cnt [2] $ (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] $ (!\hdmi_ctrl_inst|encode_inst1|Add17~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|Add17~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]) # (!\hdmi_ctrl_inst|encode_inst1|Add17~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 +// [2] & !\hdmi_ctrl_inst|encode_inst1|Add17~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~6_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & (!\hdmi_ctrl_inst|encode_inst1|Add17~5 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|Add17~5 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add17~7 = CARRY((!\hdmi_ctrl_inst|encode_inst1|Add17~5 ) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~6 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~8_combout = \hdmi_ctrl_inst|encode_inst1|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst1|Add17~7 ) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~7 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~8 .lut_mask = 16'hA5A5; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]) # (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add23~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add23~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~0 .lut_mask = 16'h66DD; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~4_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst1|Add23~3 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst1|Add23~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add23~5 = CARRY((!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst1|Add23~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add23~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add23~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~4 .lut_mask = 16'h3C03; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~6_combout = !\hdmi_ctrl_inst|encode_inst1|Add23~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add23~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst1|cnt [1] & (\hdmi_ctrl_inst|encode_inst1|Add15~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst1|Add15~1 )))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst1|cnt [1] & (!\hdmi_ctrl_inst|encode_inst1|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((\hdmi_ctrl_inst|encode_inst1|Add15~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|Add15~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & !\hdmi_ctrl_inst|encode_inst1|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & +// ((!\hdmi_ctrl_inst|encode_inst1|Add15~1 ) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~6_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst1|Add15~5 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & +// (!\hdmi_ctrl_inst|encode_inst1|Add15~5 )))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst1|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & +// ((\hdmi_ctrl_inst|encode_inst1|Add15~5 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|Add15~7 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [3] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst1|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((!\hdmi_ctrl_inst|encode_inst1|Add15~5 ) +// # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~6 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~8_combout = \hdmi_ctrl_inst|encode_inst1|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst1|Add15~7 ) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~7 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~8 .lut_mask = 16'hA5A5; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|cnt [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|cnt [1] & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add19~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & \hdmi_ctrl_inst|encode_inst1|cnt [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add19~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~2_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [2] & (!\hdmi_ctrl_inst|encode_inst1|Add19~1 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & ((\hdmi_ctrl_inst|encode_inst1|Add19~1 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add19~3 = CARRY((!\hdmi_ctrl_inst|encode_inst1|Add19~1 ) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add19~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add19~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~2 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~4_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & (\hdmi_ctrl_inst|encode_inst1|Add19~3 $ (GND))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & (!\hdmi_ctrl_inst|encode_inst1|Add19~3 & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add19~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [3] & !\hdmi_ctrl_inst|encode_inst1|Add19~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add19~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add19~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~4 .lut_mask = 16'hA50A; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~6_combout = \hdmi_ctrl_inst|encode_inst1|Add19~5 $ (\hdmi_ctrl_inst|encode_inst1|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst1|Add19~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~6 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & ((\hdmi_ctrl_inst|encode_inst1|cnt [1]) # (GND))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|cnt [1] $ (VCC))) +// \hdmi_ctrl_inst|encode_inst1|Add22~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]) # (\hdmi_ctrl_inst|encode_inst1|cnt [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add22~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~0 .lut_mask = 16'h99EE; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~2_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|Add22~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & (!\hdmi_ctrl_inst|encode_inst1|Add22~1 )) +// \hdmi_ctrl_inst|encode_inst1|Add22~3 = CARRY((!\hdmi_ctrl_inst|encode_inst1|cnt [2] & !\hdmi_ctrl_inst|encode_inst1|Add22~1 )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add22~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add22~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~2 .lut_mask = 16'hA505; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~4_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst1|Add22~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & (\hdmi_ctrl_inst|encode_inst1|Add22~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add22~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [3]) # (!\hdmi_ctrl_inst|encode_inst1|Add22~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add22~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add22~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y23_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((GND) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add20~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add20~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~0 .lut_mask = 16'h66BB; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~4_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst2|Add20~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst2|Add20~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add20~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst2|Add20~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add20~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add20~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~4 .lut_mask = 16'h3CCF; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~0_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [0] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [0] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add17~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [0] & \hdmi_ctrl_inst|encode_inst2|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|Add17~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst2|Add17~1 )))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (!\hdmi_ctrl_inst|encode_inst2|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & ((\hdmi_ctrl_inst|encode_inst2|Add17~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|Add17~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & !\hdmi_ctrl_inst|encode_inst2|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & +// ((!\hdmi_ctrl_inst|encode_inst2|Add17~1 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~4_combout = ((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] $ (\hdmi_ctrl_inst|encode_inst2|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst2|Add17~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|Add17~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst2|Add17~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst2|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst2|Add17~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~6_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [3] & (!\hdmi_ctrl_inst|encode_inst2|Add17~5 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & ((\hdmi_ctrl_inst|encode_inst2|Add17~5 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add17~7 = CARRY((!\hdmi_ctrl_inst|encode_inst2|Add17~5 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~6 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]) # (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add23~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add23~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~0 .lut_mask = 16'h66DD; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~4_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst2|Add23~3 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst2|Add23~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add23~5 = CARRY((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst2|Add23~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add23~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add23~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~4 .lut_mask = 16'h3C03; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|Add15~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst2|Add15~1 )))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (!\hdmi_ctrl_inst|encode_inst2|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & ((\hdmi_ctrl_inst|encode_inst2|Add15~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|Add15~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & !\hdmi_ctrl_inst|encode_inst2|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & +// ((!\hdmi_ctrl_inst|encode_inst2|Add15~1 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~4_combout = ((\hdmi_ctrl_inst|encode_inst2|cnt [2] $ (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] $ (!\hdmi_ctrl_inst|encode_inst2|Add15~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|Add15~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst2|Add15~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 +// [2] & !\hdmi_ctrl_inst|encode_inst2|Add15~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~6_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst2|cnt [3] & (\hdmi_ctrl_inst|encode_inst2|Add15~5 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & +// (!\hdmi_ctrl_inst|encode_inst2|Add15~5 )))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst2|cnt [3] & (!\hdmi_ctrl_inst|encode_inst2|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & ((\hdmi_ctrl_inst|encode_inst2|Add15~5 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|Add15~7 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & !\hdmi_ctrl_inst|encode_inst2|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & +// ((!\hdmi_ctrl_inst|encode_inst2|Add15~5 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~6 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~8_combout = \hdmi_ctrl_inst|encode_inst2|Add15~7 $ (!\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~7 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~8 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~2_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [2] & (!\hdmi_ctrl_inst|encode_inst2|Add19~1 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2] & ((\hdmi_ctrl_inst|encode_inst2|Add19~1 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add19~3 = CARRY((!\hdmi_ctrl_inst|encode_inst2|Add19~1 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add19~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add19~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~2 .lut_mask = 16'h3C3F; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~4_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [3] & (\hdmi_ctrl_inst|encode_inst2|Add19~3 $ (GND))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & (!\hdmi_ctrl_inst|encode_inst2|Add19~3 & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add19~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [3] & !\hdmi_ctrl_inst|encode_inst2|Add19~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add19~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add19~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~4 .lut_mask = 16'hA50A; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~6_combout = \hdmi_ctrl_inst|encode_inst2|Add19~5 $ (\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add19~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~6 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~0_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [1] & ((\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]) # (GND))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] $ (VCC))) +// \hdmi_ctrl_inst|encode_inst2|Add22~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [1]) # (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add22~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~0 .lut_mask = 16'h99EE; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~2_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|Add22~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2] & (!\hdmi_ctrl_inst|encode_inst2|Add22~1 )) +// \hdmi_ctrl_inst|encode_inst2|Add22~3 = CARRY((!\hdmi_ctrl_inst|encode_inst2|cnt [2] & !\hdmi_ctrl_inst|encode_inst2|Add22~1 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add22~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add22~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~2 .lut_mask = 16'hC303; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~4_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst2|Add22~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & (\hdmi_ctrl_inst|encode_inst2|Add22~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add22~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [3]) # (!\hdmi_ctrl_inst|encode_inst2|Add22~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add22~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add22~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~6_combout = \hdmi_ctrl_inst|encode_inst2|Add22~5 $ (!\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add22~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~6 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y24_N11 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y22_N19 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [6]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y21_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [7]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~2 ( +// Equation(s): +// \vga_ctrl_inst|Add0~2_combout = (\vga_ctrl_inst|cnt_h [1] & (!\vga_ctrl_inst|Add0~1 )) # (!\vga_ctrl_inst|cnt_h [1] & ((\vga_ctrl_inst|Add0~1 ) # (GND))) +// \vga_ctrl_inst|Add0~3 = CARRY((!\vga_ctrl_inst|Add0~1 ) # (!\vga_ctrl_inst|cnt_h [1])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~1 ), + .combout(\vga_ctrl_inst|Add0~2_combout ), + .cout(\vga_ctrl_inst|Add0~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~10 ( +// Equation(s): +// \vga_ctrl_inst|Add0~10_combout = (\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|Add0~9 )) # (!\vga_ctrl_inst|cnt_h [5] & ((\vga_ctrl_inst|Add0~9 ) # (GND))) +// \vga_ctrl_inst|Add0~11 = CARRY((!\vga_ctrl_inst|Add0~9 ) # (!\vga_ctrl_inst|cnt_h [5])) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~9 ), + .combout(\vga_ctrl_inst|Add0~10_combout ), + .cout(\vga_ctrl_inst|Add0~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~2 ( +// Equation(s): +// \vga_ctrl_inst|Add1~2_combout = (\vga_ctrl_inst|cnt_v [1] & (!\vga_ctrl_inst|Add1~1 )) # (!\vga_ctrl_inst|cnt_v [1] & ((\vga_ctrl_inst|Add1~1 ) # (GND))) +// \vga_ctrl_inst|Add1~3 = CARRY((!\vga_ctrl_inst|Add1~1 ) # (!\vga_ctrl_inst|cnt_v [1])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~1 ), + .combout(\vga_ctrl_inst|Add1~2_combout ), + .cout(\vga_ctrl_inst|Add1~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~6 ( +// Equation(s): +// \vga_ctrl_inst|Add1~6_combout = (\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|Add1~5 )) # (!\vga_ctrl_inst|cnt_v [3] & ((\vga_ctrl_inst|Add1~5 ) # (GND))) +// \vga_ctrl_inst|Add1~7 = CARRY((!\vga_ctrl_inst|Add1~5 ) # (!\vga_ctrl_inst|cnt_v [3])) + + .dataa(\vga_ctrl_inst|cnt_v [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~5 ), + .combout(\vga_ctrl_inst|Add1~6_combout ), + .cout(\vga_ctrl_inst|Add1~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~6 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~8 ( +// Equation(s): +// \vga_ctrl_inst|Add1~8_combout = (\vga_ctrl_inst|cnt_v [4] & (\vga_ctrl_inst|Add1~7 $ (GND))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|Add1~7 & VCC)) +// \vga_ctrl_inst|Add1~9 = CARRY((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Add1~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~7 ), + .combout(\vga_ctrl_inst|Add1~8_combout ), + .cout(\vga_ctrl_inst|Add1~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~10 ( +// Equation(s): +// \vga_ctrl_inst|Add1~10_combout = (\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|Add1~9 )) # (!\vga_ctrl_inst|cnt_v [5] & ((\vga_ctrl_inst|Add1~9 ) # (GND))) +// \vga_ctrl_inst|Add1~11 = CARRY((!\vga_ctrl_inst|Add1~9 ) # (!\vga_ctrl_inst|cnt_v [5])) + + .dataa(\vga_ctrl_inst|cnt_v [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~9 ), + .combout(\vga_ctrl_inst|Add1~10_combout ), + .cout(\vga_ctrl_inst|Add1~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~12 ( +// Equation(s): +// \vga_ctrl_inst|Add1~12_combout = (\vga_ctrl_inst|cnt_v [6] & (\vga_ctrl_inst|Add1~11 $ (GND))) # (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|Add1~11 & VCC)) +// \vga_ctrl_inst|Add1~13 = CARRY((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Add1~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~11 ), + .combout(\vga_ctrl_inst|Add1~12_combout ), + .cout(\vga_ctrl_inst|Add1~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~14 ( +// Equation(s): +// \vga_ctrl_inst|Add1~14_combout = (\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|Add1~13 )) # (!\vga_ctrl_inst|cnt_v [7] & ((\vga_ctrl_inst|Add1~13 ) # (GND))) +// \vga_ctrl_inst|Add1~15 = CARRY((!\vga_ctrl_inst|Add1~13 ) # (!\vga_ctrl_inst|cnt_v [7])) + + .dataa(\vga_ctrl_inst|cnt_v [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~13 ), + .combout(\vga_ctrl_inst|Add1~14_combout ), + .cout(\vga_ctrl_inst|Add1~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~16 ( +// Equation(s): +// \vga_ctrl_inst|Add1~16_combout = (\vga_ctrl_inst|cnt_v [8] & (\vga_ctrl_inst|Add1~15 $ (GND))) # (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|Add1~15 & VCC)) +// \vga_ctrl_inst|Add1~17 = CARRY((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Add1~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~15 ), + .combout(\vga_ctrl_inst|Add1~16_combout ), + .cout(\vga_ctrl_inst|Add1~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~18 ( +// Equation(s): +// \vga_ctrl_inst|Add1~18_combout = (\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|Add1~17 )) # (!\vga_ctrl_inst|cnt_v [9] & ((\vga_ctrl_inst|Add1~17 ) # (GND))) +// \vga_ctrl_inst|Add1~19 = CARRY((!\vga_ctrl_inst|Add1~17 ) # (!\vga_ctrl_inst|cnt_v [9])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~17 ), + .combout(\vga_ctrl_inst|Add1~18_combout ), + .cout(\vga_ctrl_inst|Add1~19 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~18 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~20 ( +// Equation(s): +// \vga_ctrl_inst|Add1~20_combout = (\vga_ctrl_inst|cnt_v [10] & (\vga_ctrl_inst|Add1~19 $ (GND))) # (!\vga_ctrl_inst|cnt_v [10] & (!\vga_ctrl_inst|Add1~19 & VCC)) +// \vga_ctrl_inst|Add1~21 = CARRY((\vga_ctrl_inst|cnt_v [10] & !\vga_ctrl_inst|Add1~19 )) + + .dataa(\vga_ctrl_inst|cnt_v [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~19 ), + .combout(\vga_ctrl_inst|Add1~20_combout ), + .cout(\vga_ctrl_inst|Add1~21 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~20 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y20_N11 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y20_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [2] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1 .lut_mask = 16'h00F0; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N15 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add12~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_3~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_3~1_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_3~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~1 .lut_mask = 16'h0A8E; +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal1~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal1~0_combout = (!\hdmi_ctrl_inst|encode_inst0|cnt [4] & (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & (!\hdmi_ctrl_inst|encode_inst0|cnt [2] & !\hdmi_ctrl_inst|encode_inst0|cnt [0]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~0 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N27 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y24_N19 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n0[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add14~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_3~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_3~1_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & \hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]) # ((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & \hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_3~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~1 .lut_mask = 16'h4F04; +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N31 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]) # (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2 .lut_mask = 16'hFFF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~0_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst0|Add17~8_combout ) # (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add23~6_combout & ((!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add23~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add17~8_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~0 .lut_mask = 16'hCCE2; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~1_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add15~8_combout ) # ((!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~0_combout +// & (((\hdmi_ctrl_inst|encode_inst0|Add20~6_combout & \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~8_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add20~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~1 .lut_mask = 16'hD8AA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~3_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|Add17~6_combout ))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add23~4_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add23~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add17~6_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~3 .lut_mask = 16'hF2C2; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~4_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~3_combout & (((\hdmi_ctrl_inst|encode_inst0|Add15~6_combout ) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~3_combout +// & (\hdmi_ctrl_inst|encode_inst0|Add20~4_combout & ((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add20~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add16~3_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~4 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~5_combout = (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst0|Add19~4_combout ))) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst0|Add22~4_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add22~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add19~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~5 .lut_mask = 16'h3210; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~7_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst0|Add20~2_combout )) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add23~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add20~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add23~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~7 .lut_mask = 16'hFA0C; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~8_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~7_combout & ((\hdmi_ctrl_inst|encode_inst0|Add15~4_combout ) # ((!\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~7_combout +// & (((\hdmi_ctrl_inst|encode_inst0|Add17~4_combout & \hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~7_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add17~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~8 .lut_mask = 16'hD8AA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~11_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|Add17~2_combout ) # ((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst0|Add23~0_combout & !\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add17~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add23~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~11_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~11 .lut_mask = 16'hF0AC; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~12 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~12_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~11_combout & ((\hdmi_ctrl_inst|encode_inst0|Add15~2_combout ) # ((!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst0|Add16~11_combout & (((\hdmi_ctrl_inst|encode_inst0|Add20~0_combout & \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~11_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add20~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~12_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~12 .lut_mask = 16'hD8AA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~16 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~16_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|cnt [0]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .datad(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~16_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~16 .lut_mask = 16'h5F0A; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal1~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal1~1_combout = (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & \hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~1 .lut_mask = 16'h0F00; +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add12~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add12~1_combout = (!\hdmi_ctrl_inst|encode_inst0|data_in_reg [4] & \hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add12~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add12~1 .lut_mask = 16'h3300; +defparam \hdmi_ctrl_inst|encode_inst0|Add12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N7 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~2_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [3] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_reg [3]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~2 .lut_mask = 16'h995A; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [4])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [3]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out [4]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [3]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2 .lut_mask = 16'hACAC; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~0_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add17~8_combout ) # (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add23~6_combout & ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add23~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add17~8_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~0 .lut_mask = 16'hAAE4; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~1_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~0_combout & ((\hdmi_ctrl_inst|encode_inst1|Add15~8_combout ) # ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~0_combout +// & (((\hdmi_ctrl_inst|encode_inst1|Add20~6_combout & \hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add15~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add20~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~1 .lut_mask = 16'hACF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~5_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3])))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add22~4_combout & (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add22~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~5 .lut_mask = 16'hA4AE; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~6_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~5_combout ) # ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & \hdmi_ctrl_inst|encode_inst1|Add19~4_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add19~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~6 .lut_mask = 16'hF8F8; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~7_combout = (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add22~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add22~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~7 .lut_mask = 16'hAF44; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~8_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~7_combout & (((!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~7_combout & +// (\hdmi_ctrl_inst|encode_inst1|Add19~2_combout & (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add19~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~7_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~8 .lut_mask = 16'h2CEC; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~13_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add17~2_combout ) # (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add23~0_combout & ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add23~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add17~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~13_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~13 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~14 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~14_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~13_combout & (((\hdmi_ctrl_inst|encode_inst1|Add15~2_combout ) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|Add16~13_combout & (\hdmi_ctrl_inst|encode_inst1|Add20~0_combout & ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add20~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~13_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add15~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~14_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~14 .lut_mask = 16'hE2CC; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~16 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~16_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst1|cnt [0]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~16_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~16 .lut_mask = 16'h3F0C; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal2~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal2~1_combout = (\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout & !\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~1 .lut_mask = 16'h00AA; +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N31 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y21_N1 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~2_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [2] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~2 .lut_mask = 16'hA53C; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~2_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout ) # ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst2|Add19~6_combout )) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst2|Add22~6_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add19~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add22~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~2 .lut_mask = 16'hFAFC; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~3_combout = (\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|Add17~6_combout )) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|Add23~4_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add17~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|Add23~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~3 .lut_mask = 16'hE3E0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~4_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~3_combout & ((\hdmi_ctrl_inst|encode_inst2|Add15~6_combout ) # ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~3_combout +// & (((\hdmi_ctrl_inst|encode_inst2|Add20~4_combout & \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add15~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add20~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~3_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~4 .lut_mask = 16'hACF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~9_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2])))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|Add22~2_combout & ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add22~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~9_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~9 .lut_mask = 16'hAA4E; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~10 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~10_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~9_combout & (((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2])))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~9_combout & +// (\hdmi_ctrl_inst|encode_inst2|Add19~2_combout & ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add19~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~9_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~10_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~10 .lut_mask = 16'h3AF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~11_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|Add17~2_combout ) # (\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|Add23~0_combout & ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add23~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add17~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~11_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~11 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~12 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~12_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~11_combout & (((\hdmi_ctrl_inst|encode_inst2|Add15~2_combout ) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst2|Add16~11_combout & (\hdmi_ctrl_inst|encode_inst2|Add20~0_combout & ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add20~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add15~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~11_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~12_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~12 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~13_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|Add22~0_combout & !\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|Add22~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~13_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~13 .lut_mask = 16'hAA72; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~16 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~16_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|cnt [0])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~16_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~16 .lut_mask = 16'h0FCC; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal2~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal2~1_combout = (\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout & !\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~1 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add14~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add14~1_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3] & (\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] $ (!\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add14~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add14~1 .lut_mask = 16'hC00C; +defparam \hdmi_ctrl_inst|encode_inst2|Add14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N25 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~2_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [3] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~2 .lut_mask = 16'h939C; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~3_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~3 .lut_mask = 16'hF303; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~0_combout = (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|cnt_v [8]))) + + .dataa(\vga_ctrl_inst|cnt_v [9]), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|cnt_v [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N31 +dffeas \vga_ctrl_inst|cnt_v[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[10]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[10] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~3 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~3_combout = (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~2_combout & ((\vga_ctrl_inst|always1~0_combout ) # (!\vga_ctrl_inst|cnt_v [9])))) + + .dataa(\vga_ctrl_inst|pix_data_req~1_combout ), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|always1~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~3 .lut_mask = 16'hA200; +defparam \vga_ctrl_inst|pix_data_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout = \hdmi_ctrl_inst|encode_inst0|data_in_reg [3] $ (\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m[3]~0 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst0|q_m[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~5_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [4] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~5 .lut_mask = 16'h995A; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N19 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [6])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [6]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N31 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y21_N27 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [7])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [4]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [7]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [4]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N21 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~4_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [4] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_reg [4]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~4 .lut_mask = 16'hA53C; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout = \hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] $ (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m[3]~0 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst2|q_m[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N9 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~5_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [4] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~5 .lut_mask = 16'hC366; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y20_N11 +dffeas \vga_ctrl_inst|cnt_h[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|pix_x[10]~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_x[10]~1_combout = (\vga_ctrl_inst|Add2~18_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~18_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_x[10]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_x[10]~1 .lut_mask = 16'hFF0F; +defparam \vga_ctrl_inst|pix_x[10]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N10 +cycloneive_lcell_comb \vga_pic_inst|always0~1 ( +// Equation(s): +// \vga_pic_inst|always0~1_combout = (\vga_ctrl_inst|Add2~14_combout ) # ((\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout )) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|always0~1 .lut_mask = 16'hFFAF; +defparam \vga_pic_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N12 +cycloneive_lcell_comb \vga_pic_inst|always0~2 ( +// Equation(s): +// \vga_pic_inst|always0~2_combout = (\vga_pic_inst|always0~1_combout ) # ((\vga_ctrl_inst|Add2~18_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (\vga_pic_inst|LessThan17~2_combout ))) + + .dataa(\vga_pic_inst|always0~1_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|LessThan17~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|always0~2 .lut_mask = 16'hFFFE; +defparam \vga_pic_inst|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N6 +cycloneive_lcell_comb \vga_pic_inst|pix_data[9]~14 ( +// Equation(s): +// \vga_pic_inst|pix_data[9]~14_combout = (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_ctrl_inst|Add2~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[9]~14_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9]~14 .lut_mask = 16'h00F0; +defparam \vga_pic_inst|pix_data[9]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~16 ( +// Equation(s): +// \vga_pic_inst|pix_data~16_combout = (\vga_pic_inst|always0~2_combout & (!\vga_pic_inst|pix_data[9]~15_combout & (!\vga_ctrl_inst|pix_x[11]~0_combout & \vga_pic_inst|pix_data[13]~9_combout ))) + + .dataa(\vga_pic_inst|always0~2_combout ), + .datab(\vga_pic_inst|pix_data[9]~15_combout ), + .datac(\vga_ctrl_inst|pix_x[11]~0_combout ), + .datad(\vga_pic_inst|pix_data[13]~9_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~16 .lut_mask = 16'h0200; +defparam \vga_pic_inst|pix_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~8 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~8_combout = (!\vga_ctrl_inst|cnt_v [11] & !\vga_ctrl_inst|cnt_v [10]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [11]), + .datac(\vga_ctrl_inst|cnt_v [10]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~8 .lut_mask = 16'h0303; +defparam \vga_ctrl_inst|pix_data_req~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[10]~12 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[10]~12_combout = (\vga_ctrl_inst|Add1~20_combout & (((!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|cnt_v [10])) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~20_combout & (!\vga_ctrl_inst|Equal0~3_combout +// & (\vga_ctrl_inst|cnt_v [10]))) + + .dataa(\vga_ctrl_inst|Add1~20_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [10]), + .datad(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[10]~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[10]~12 .lut_mask = 16'h30BA; +defparam \vga_ctrl_inst|cnt_v[10]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m[4]~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout = \hdmi_ctrl_inst|encode_inst0|data_in_reg [4] $ (\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m[4]~2 .lut_mask = 16'h3C3C; +defparam \hdmi_ctrl_inst|encode_inst0|q_m[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[6]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6]~6 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N23 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout = (\hdmi_ctrl_inst|encode_inst0|data_out [8] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out [8]), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4 .lut_mask = 16'hA0A0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N22 +cycloneive_lcell_comb \vga_pic_inst|LessThan10~0 ( +// Equation(s): +// \vga_pic_inst|LessThan10~0_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~16_combout & ((\vga_pic_inst|LessThan17~2_combout ) # (!\vga_ctrl_inst|Add2~14_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_pic_inst|LessThan17~2_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan10~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan10~0 .lut_mask = 16'h080A; +defparam \vga_pic_inst|LessThan10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data~22 ( +// Equation(s): +// \vga_pic_inst|pix_data~22_combout = (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_ctrl_inst|Add2~10_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~22 .lut_mask = 16'h00F0; +defparam \vga_pic_inst|pix_data~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~23 ( +// Equation(s): +// \vga_pic_inst|pix_data~23_combout = (!\vga_ctrl_inst|Add2~14_combout & (\vga_pic_inst|pix_data~22_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_ctrl_inst|Add2~12_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_pic_inst|pix_data~22_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~23_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~23 .lut_mask = 16'h0400; +defparam \vga_pic_inst|pix_data~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N20 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~1 ( +// Equation(s): +// \vga_pic_inst|LessThan14~1_combout = (\vga_ctrl_inst|Add2~12_combout & \vga_ctrl_inst|Add2~10_combout ) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~1 .lut_mask = 16'hAA00; +defparam \vga_pic_inst|LessThan14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~24 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~24_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_pic_inst|LessThan14~1_combout & (!\vga_ctrl_inst|Add2~16_combout & !\vga_ctrl_inst|Add2~14_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_pic_inst|LessThan14~1_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~24_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~24 .lut_mask = 16'h0002; +defparam \vga_pic_inst|pix_data[13]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N8 +cycloneive_lcell_comb \vga_pic_inst|pix_data~25 ( +// Equation(s): +// \vga_pic_inst|pix_data~25_combout = (!\vga_ctrl_inst|pix_x[10]~1_combout & ((\vga_pic_inst|pix_data~23_combout ) # ((\vga_pic_inst|LessThan10~0_combout & !\vga_pic_inst|pix_data[13]~24_combout )))) + + .dataa(\vga_pic_inst|LessThan10~0_combout ), + .datab(\vga_ctrl_inst|pix_x[10]~1_combout ), + .datac(\vga_pic_inst|pix_data[13]~24_combout ), + .datad(\vga_pic_inst|pix_data~23_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~25_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~25 .lut_mask = 16'h3302; +defparam \vga_pic_inst|pix_data~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|q_m[5]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout = \hdmi_ctrl_inst|encode_inst1|data_in_reg [4] $ (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m[5]~0 .lut_mask = 16'hC33C; +defparam \hdmi_ctrl_inst|encode_inst1|q_m[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[7] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~5_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [7] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [7]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~5 .lut_mask = 16'h9A56; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N9 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [9]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[9] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout = (\hdmi_ctrl_inst|encode_inst1|data_out [9] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [9]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4 .lut_mask = 16'hC0C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m[4]~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout = \hdmi_ctrl_inst|encode_inst2|data_in_reg [3] $ (\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m[4]~2 .lut_mask = 16'h33CC; +defparam \hdmi_ctrl_inst|encode_inst2|q_m[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N23 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout = (\hdmi_ctrl_inst|encode_inst2|data_out [8] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [8]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4 .lut_mask = 16'h8888; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~8_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~8 .lut_mask = 16'h8D8D; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|q_m[7]~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout = \hdmi_ctrl_inst|encode_inst1|data_in_reg [7] $ (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m[7]~1 .lut_mask = 16'hC33C; +defparam \hdmi_ctrl_inst|encode_inst1|q_m[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~6_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst2|c1_reg2~q $ +// ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~6 .lut_mask = 16'hEB41; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~8_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~8 .lut_mask = 16'hB1B1; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~37 ( +// Equation(s): +// \vga_pic_inst|pix_data~37_combout = ((!\vga_ctrl_inst|Add2~18_combout & (\vga_ctrl_inst|pix_data_req~7_combout & \vga_pic_inst|pix_data~23_combout ))) # (!\vga_pic_inst|pix_data~16_combout ) + + .dataa(\vga_pic_inst|pix_data~16_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data~23_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~37_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~37 .lut_mask = 16'h7555; +defparam \vga_pic_inst|pix_data~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~2_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~2_combout + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder .lut_mask = 16'hAAAA; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~2_combout + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder .lut_mask = 16'hAAAA; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~5_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~5_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~4_combout + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out~4_combout ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder .lut_mask = 16'hCCCC; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~5_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out~5_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~5_combout + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out~5_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder .lut_mask = 16'hAAAA; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N16 +cycloneive_io_obuf \ddc_scl~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(ddc_scl), + .obar()); +// synopsys translate_off +defparam \ddc_scl~output .bus_hold = "false"; +defparam \ddc_scl~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y10_N16 +cycloneive_io_obuf \ddc_sda~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(ddc_sda), + .obar()); +// synopsys translate_off +defparam \ddc_sda~output .bus_hold = "false"; +defparam \ddc_sda~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y21_N23 +cycloneive_io_obuf \tmds_clk_p~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_clk_p), + .obar()); +// synopsys translate_off +defparam \tmds_clk_p~output .bus_hold = "false"; +defparam \tmds_clk_p~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y20_N2 +cycloneive_io_obuf \tmds_clk_n~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_clk_n), + .obar()); +// synopsys translate_off +defparam \tmds_clk_n~output .bus_hold = "false"; +defparam \tmds_clk_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y22_N16 +cycloneive_io_obuf \tmds_data_p[0]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_p[0]), + .obar()); +// synopsys translate_off +defparam \tmds_data_p[0]~output .bus_hold = "false"; +defparam \tmds_data_p[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y23_N9 +cycloneive_io_obuf \tmds_data_p[1]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_p[1]), + .obar()); +// synopsys translate_off +defparam \tmds_data_p[1]~output .bus_hold = "false"; +defparam \tmds_data_p[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y24_N2 +cycloneive_io_obuf \tmds_data_p[2]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_p[2]), + .obar()); +// synopsys translate_off +defparam \tmds_data_p[2]~output .bus_hold = "false"; +defparam \tmds_data_p[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y22_N23 +cycloneive_io_obuf \tmds_data_n[0]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_n[0]), + .obar()); +// synopsys translate_off +defparam \tmds_data_n[0]~output .bus_hold = "false"; +defparam \tmds_data_n[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y23_N16 +cycloneive_io_obuf \tmds_data_n[1]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_n[1]), + .obar()); +// synopsys translate_off +defparam \tmds_data_n[1]~output .bus_hold = "false"; +defparam \tmds_data_n[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y24_N9 +cycloneive_io_obuf \tmds_data_n[2]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_n[2]), + .obar()); +// synopsys translate_off +defparam \tmds_data_n[2]~output .bus_hold = "false"; +defparam \tmds_data_n[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout = (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0 .lut_mask = 16'h0303; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout = \hdmi_ctrl_inst|par_to_ser_inst0|cnt [1] $ (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N19 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout = \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] $ (((\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0 .lut_mask = 16'h3CF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N17 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [1] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [1]), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0 .lut_mask = 16'h00AA; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout = \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N31 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) # (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [4]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [4]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3 .lut_mask = 16'hFCFC; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N5 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2 .lut_mask = 16'h00F0; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [2] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N29 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [1] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [1]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N23 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y21_N25 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y20_N4 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~0 ( +// Equation(s): +// \vga_ctrl_inst|Add0~0_combout = \vga_ctrl_inst|cnt_h [0] $ (VCC) +// \vga_ctrl_inst|Add0~1 = CARRY(\vga_ctrl_inst|cnt_h [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add0~0_combout ), + .cout(\vga_ctrl_inst|Add0~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y26_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X40_Y26_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y26_N18 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) # (!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q )) # (!\sys_rst_n~input_o ) + + .dataa(\sys_rst_n~input_o ), + .datab(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .datac(gnd), + .datad(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h77FF; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G7 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X37_Y20_N9 +dffeas \vga_ctrl_inst|cnt_h[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~4 ( +// Equation(s): +// \vga_ctrl_inst|Add0~4_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|Add0~3 $ (GND))) # (!\vga_ctrl_inst|cnt_h [2] & (!\vga_ctrl_inst|Add0~3 & VCC)) +// \vga_ctrl_inst|Add0~5 = CARRY((\vga_ctrl_inst|cnt_h [2] & !\vga_ctrl_inst|Add0~3 )) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~3 ), + .combout(\vga_ctrl_inst|Add0~4_combout ), + .cout(\vga_ctrl_inst|Add0~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~6 ( +// Equation(s): +// \vga_ctrl_inst|Add0~6_combout = (\vga_ctrl_inst|cnt_h [3] & (!\vga_ctrl_inst|Add0~5 )) # (!\vga_ctrl_inst|cnt_h [3] & ((\vga_ctrl_inst|Add0~5 ) # (GND))) +// \vga_ctrl_inst|Add0~7 = CARRY((!\vga_ctrl_inst|Add0~5 ) # (!\vga_ctrl_inst|cnt_h [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~5 ), + .combout(\vga_ctrl_inst|Add0~6_combout ), + .cout(\vga_ctrl_inst|Add0~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N15 +dffeas \vga_ctrl_inst|cnt_h[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~8 ( +// Equation(s): +// \vga_ctrl_inst|Add0~8_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Add0~7 $ (GND))) # (!\vga_ctrl_inst|cnt_h [4] & (!\vga_ctrl_inst|Add0~7 & VCC)) +// \vga_ctrl_inst|Add0~9 = CARRY((\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add0~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~7 ), + .combout(\vga_ctrl_inst|Add0~8_combout ), + .cout(\vga_ctrl_inst|Add0~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N17 +dffeas \vga_ctrl_inst|cnt_h[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~12 ( +// Equation(s): +// \vga_ctrl_inst|Add0~12_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add0~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add0~11 & VCC)) +// \vga_ctrl_inst|Add0~13 = CARRY((\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add0~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~11 ), + .combout(\vga_ctrl_inst|Add0~12_combout ), + .cout(\vga_ctrl_inst|Add0~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N21 +dffeas \vga_ctrl_inst|cnt_h[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~14 ( +// Equation(s): +// \vga_ctrl_inst|Add0~14_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add0~13 )) # (!\vga_ctrl_inst|cnt_h [7] & ((\vga_ctrl_inst|Add0~13 ) # (GND))) +// \vga_ctrl_inst|Add0~15 = CARRY((!\vga_ctrl_inst|Add0~13 ) # (!\vga_ctrl_inst|cnt_h [7])) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~13 ), + .combout(\vga_ctrl_inst|Add0~14_combout ), + .cout(\vga_ctrl_inst|Add0~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N23 +dffeas \vga_ctrl_inst|cnt_h[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y20_N13 +dffeas \vga_ctrl_inst|cnt_h[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~0 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~0_combout = (\vga_ctrl_inst|cnt_h [1] & (\vga_ctrl_inst|cnt_h [3] & (\vga_ctrl_inst|cnt_h [0] & \vga_ctrl_inst|cnt_h [2]))) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(\vga_ctrl_inst|cnt_h [0]), + .datad(\vga_ctrl_inst|cnt_h [2]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~0 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~16 ( +// Equation(s): +// \vga_ctrl_inst|Add0~16_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add0~15 $ (GND))) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add0~15 & VCC)) +// \vga_ctrl_inst|Add0~17 = CARRY((\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add0~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~15 ), + .combout(\vga_ctrl_inst|Add0~16_combout ), + .cout(\vga_ctrl_inst|Add0~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~18 ( +// Equation(s): +// \vga_ctrl_inst|Add0~18_combout = (\vga_ctrl_inst|cnt_h [9] & (!\vga_ctrl_inst|Add0~17 )) # (!\vga_ctrl_inst|cnt_h [9] & ((\vga_ctrl_inst|Add0~17 ) # (GND))) +// \vga_ctrl_inst|Add0~19 = CARRY((!\vga_ctrl_inst|Add0~17 ) # (!\vga_ctrl_inst|cnt_h [9])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [9]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~17 ), + .combout(\vga_ctrl_inst|Add0~18_combout ), + .cout(\vga_ctrl_inst|Add0~19 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~18 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~20 ( +// Equation(s): +// \vga_ctrl_inst|Add0~20_combout = (\vga_ctrl_inst|cnt_h [10] & (\vga_ctrl_inst|Add0~19 $ (GND))) # (!\vga_ctrl_inst|cnt_h [10] & (!\vga_ctrl_inst|Add0~19 & VCC)) +// \vga_ctrl_inst|Add0~21 = CARRY((\vga_ctrl_inst|cnt_h [10] & !\vga_ctrl_inst|Add0~19 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~19 ), + .combout(\vga_ctrl_inst|Add0~20_combout ), + .cout(\vga_ctrl_inst|Add0~21 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~20 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N29 +dffeas \vga_ctrl_inst|cnt_h[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[10] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~22 ( +// Equation(s): +// \vga_ctrl_inst|Add0~22_combout = \vga_ctrl_inst|cnt_h [11] $ (\vga_ctrl_inst|Add0~21 ) + + .dataa(\vga_ctrl_inst|cnt_h [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\vga_ctrl_inst|Add0~21 ), + .combout(\vga_ctrl_inst|Add0~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~22 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N31 +dffeas \vga_ctrl_inst|cnt_h[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [11]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[11] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~1 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~1_combout = (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|cnt_h [10] & (!\vga_ctrl_inst|cnt_h [11] & \vga_ctrl_inst|cnt_h [9]))) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(\vga_ctrl_inst|cnt_h [11]), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~1 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N24 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~0_combout = (\vga_ctrl_inst|Add0~10_combout & (((!\vga_ctrl_inst|Equal0~2_combout ) # (!\vga_ctrl_inst|Equal0~1_combout )) # (!\vga_ctrl_inst|Equal0~0_combout ))) + + .dataa(\vga_ctrl_inst|Add0~10_combout ), + .datab(\vga_ctrl_inst|Equal0~0_combout ), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~0 .lut_mask = 16'h2AAA; +defparam \vga_ctrl_inst|cnt_h~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y21_N25 +dffeas \vga_ctrl_inst|cnt_h[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~2 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~2_combout = (\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|cnt_h [5] & (\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [6]))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [5]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~2 .lut_mask = 16'h0020; +defparam \vga_ctrl_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~2_combout = (\vga_ctrl_inst|Add0~16_combout & (((!\vga_ctrl_inst|Equal0~2_combout ) # (!\vga_ctrl_inst|Equal0~0_combout )) # (!\vga_ctrl_inst|Equal0~1_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|Add0~16_combout ), + .datac(\vga_ctrl_inst|Equal0~0_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~2 .lut_mask = 16'h4CCC; +defparam \vga_ctrl_inst|cnt_h~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y20_N3 +dffeas \vga_ctrl_inst|cnt_h[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~1_combout = (\vga_ctrl_inst|Add0~18_combout & (((!\vga_ctrl_inst|Equal0~2_combout ) # (!\vga_ctrl_inst|Equal0~0_combout )) # (!\vga_ctrl_inst|Equal0~1_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|Equal0~0_combout ), + .datac(\vga_ctrl_inst|Add0~18_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~1 .lut_mask = 16'h70F0; +defparam \vga_ctrl_inst|cnt_h~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y20_N1 +dffeas \vga_ctrl_inst|cnt_h[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan4~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan4~0_combout = (!\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [6])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [5]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan4~0 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add4~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add4~0_combout = (\vga_ctrl_inst|cnt_h [8] & (((!\vga_ctrl_inst|cnt_h [7] & \vga_ctrl_inst|LessThan4~0_combout )) # (!\vga_ctrl_inst|cnt_h [9]))) # (!\vga_ctrl_inst|cnt_h [8] & ((\vga_ctrl_inst|cnt_h [9]) # +// ((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|LessThan4~0_combout )))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(\vga_ctrl_inst|LessThan4~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add4~0 .lut_mask = 16'h7A5E; +defparam \hdmi_ctrl_inst|encode_inst0|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~1 ( +// Equation(s): +// \vga_ctrl_inst|Add2~1_cout = CARRY((\vga_ctrl_inst|cnt_h [1] & \vga_ctrl_inst|cnt_h [0])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\vga_ctrl_inst|Add2~1_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~1 .lut_mask = 16'h0088; +defparam \vga_ctrl_inst|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~3 ( +// Equation(s): +// \vga_ctrl_inst|Add2~3_cout = CARRY((!\vga_ctrl_inst|Add2~1_cout ) # (!\vga_ctrl_inst|cnt_h [2])) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~1_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~3_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~3 .lut_mask = 16'h005F; +defparam \vga_ctrl_inst|Add2~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~5 ( +// Equation(s): +// \vga_ctrl_inst|Add2~5_cout = CARRY((\vga_ctrl_inst|cnt_h [3] & !\vga_ctrl_inst|Add2~3_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~3_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~5_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~5 .lut_mask = 16'h000A; +defparam \vga_ctrl_inst|Add2~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~7 ( +// Equation(s): +// \vga_ctrl_inst|Add2~7_cout = CARRY((!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add2~5_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~5_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~7_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~7 .lut_mask = 16'h0005; +defparam \vga_ctrl_inst|Add2~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~9 ( +// Equation(s): +// \vga_ctrl_inst|Add2~9_cout = CARRY((\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|Add2~7_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [5]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~7_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~9_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~9 .lut_mask = 16'h00CF; +defparam \vga_ctrl_inst|Add2~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~10 ( +// Equation(s): +// \vga_ctrl_inst|Add2~10_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add2~9_cout & VCC)) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add2~9_cout )) +// \vga_ctrl_inst|Add2~11 = CARRY((!\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add2~9_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~9_cout ), + .combout(\vga_ctrl_inst|Add2~10_combout ), + .cout(\vga_ctrl_inst|Add2~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~10 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~12 ( +// Equation(s): +// \vga_ctrl_inst|Add2~12_combout = (\vga_ctrl_inst|cnt_h [7] & (\vga_ctrl_inst|Add2~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add2~11 & VCC)) +// \vga_ctrl_inst|Add2~13 = CARRY((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|Add2~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~11 ), + .combout(\vga_ctrl_inst|Add2~12_combout ), + .cout(\vga_ctrl_inst|Add2~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~14 ( +// Equation(s): +// \vga_ctrl_inst|Add2~14_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add2~13 & VCC)) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add2~13 )) +// \vga_ctrl_inst|Add2~15 = CARRY((!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add2~13 )) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~13 ), + .combout(\vga_ctrl_inst|Add2~14_combout ), + .cout(\vga_ctrl_inst|Add2~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~14 .lut_mask = 16'hA505; +defparam \vga_ctrl_inst|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~16 ( +// Equation(s): +// \vga_ctrl_inst|Add2~16_combout = (\vga_ctrl_inst|cnt_h [9] & ((GND) # (!\vga_ctrl_inst|Add2~15 ))) # (!\vga_ctrl_inst|cnt_h [9] & (\vga_ctrl_inst|Add2~15 $ (GND))) +// \vga_ctrl_inst|Add2~17 = CARRY((\vga_ctrl_inst|cnt_h [9]) # (!\vga_ctrl_inst|Add2~15 )) + + .dataa(\vga_ctrl_inst|cnt_h [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~15 ), + .combout(\vga_ctrl_inst|Add2~16_combout ), + .cout(\vga_ctrl_inst|Add2~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~16 .lut_mask = 16'h5AAF; +defparam \vga_ctrl_inst|Add2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~18 ( +// Equation(s): +// \vga_ctrl_inst|Add2~18_combout = (\vga_ctrl_inst|cnt_h [10] & (\vga_ctrl_inst|Add2~17 & VCC)) # (!\vga_ctrl_inst|cnt_h [10] & (!\vga_ctrl_inst|Add2~17 )) +// \vga_ctrl_inst|Add2~19 = CARRY((!\vga_ctrl_inst|cnt_h [10] & !\vga_ctrl_inst|Add2~17 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~17 ), + .combout(\vga_ctrl_inst|Add2~18_combout ), + .cout(\vga_ctrl_inst|Add2~19 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~18 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~12 ( +// Equation(s): +// \vga_pic_inst|pix_data~12_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~18_combout & (\vga_ctrl_inst|Add2~16_combout & !\vga_ctrl_inst|Add2~14_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~12 .lut_mask = 16'h0020; +defparam \vga_pic_inst|pix_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~5 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~5_combout = \vga_ctrl_inst|cnt_h [8] $ (\vga_ctrl_inst|cnt_h [9]) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~5 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|pix_data_req~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N2 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~3 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~3_combout = (\vga_ctrl_inst|Equal0~1_combout & (\vga_ctrl_inst|Equal0~0_combout & \vga_ctrl_inst|Equal0~2_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Equal0~1_combout ), + .datac(\vga_ctrl_inst|Equal0~0_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~3 .lut_mask = 16'hC000; +defparam \vga_ctrl_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[7]~7 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[7]~7_combout = (\vga_ctrl_inst|Add1~14_combout & (((\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~14_combout & (((\vga_ctrl_inst|cnt_v [7] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~14_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7]~7 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N21 +dffeas \vga_ctrl_inst|cnt_v[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[7]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[5]~10 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[5]~10_combout = (\vga_ctrl_inst|Add1~10_combout & (((!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|cnt_v [5])) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~10_combout & (!\vga_ctrl_inst|Equal0~3_combout +// & (\vga_ctrl_inst|cnt_v [5]))) + + .dataa(\vga_ctrl_inst|Add1~10_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5]~10 .lut_mask = 16'h30BA; +defparam \vga_ctrl_inst|cnt_v[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N27 +dffeas \vga_ctrl_inst|cnt_v[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[5]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[8]~6 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[8]~6_combout = (\vga_ctrl_inst|Add1~16_combout & (((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~16_combout & (((\vga_ctrl_inst|cnt_v [8] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~16_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [8]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[8]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8]~6 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[8]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N19 +dffeas \vga_ctrl_inst|cnt_v[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[8]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|always1~0 ( +// Equation(s): +// \vga_ctrl_inst|always1~0_combout = (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|cnt_v [5] & !\vga_ctrl_inst|cnt_v [8]))) + + .dataa(\vga_ctrl_inst|cnt_v [6]), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|cnt_v [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[1]~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[1]~1_combout = (\vga_ctrl_inst|Add1~2_combout & (((\vga_ctrl_inst|cnt_v [1] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~2_combout & (((\vga_ctrl_inst|cnt_v [1] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~2_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1]~1 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N9 +dffeas \vga_ctrl_inst|cnt_v[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[1]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[4]~5 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[4]~5_combout = (\vga_ctrl_inst|Add1~8_combout & (((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~8_combout & (((\vga_ctrl_inst|cnt_v [4] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~8_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [4]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4]~5 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N1 +dffeas \vga_ctrl_inst|cnt_v[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[4]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N24 +cycloneive_lcell_comb \vga_ctrl_inst|always1~1 ( +// Equation(s): +// \vga_ctrl_inst|always1~1_combout = (\vga_ctrl_inst|pix_data_req~8_combout & (\vga_ctrl_inst|always1~0_combout & (!\vga_ctrl_inst|cnt_v [1] & !\vga_ctrl_inst|cnt_v [4]))) + + .dataa(\vga_ctrl_inst|pix_data_req~8_combout ), + .datab(\vga_ctrl_inst|always1~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~1 .lut_mask = 16'h0008; +defparam \vga_ctrl_inst|always1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~0 ( +// Equation(s): +// \vga_ctrl_inst|Add1~0_combout = \vga_ctrl_inst|cnt_v [0] $ (VCC) +// \vga_ctrl_inst|Add1~1 = CARRY(\vga_ctrl_inst|cnt_v [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add1~0_combout ), + .cout(\vga_ctrl_inst|Add1~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[0]~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[0]~2_combout = (\vga_ctrl_inst|cnt_v[11]~0_combout & (((\vga_ctrl_inst|cnt_v [0] & !\vga_ctrl_inst|Equal0~3_combout )))) # (!\vga_ctrl_inst|cnt_v[11]~0_combout & ((\vga_ctrl_inst|Add1~0_combout ) # ((\vga_ctrl_inst|cnt_v [0] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datab(\vga_ctrl_inst|Add1~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0]~2 .lut_mask = 16'h44F4; +defparam \vga_ctrl_inst|cnt_v[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N1 +dffeas \vga_ctrl_inst|cnt_v[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[0]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[3]~3 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[3]~3_combout = (\vga_ctrl_inst|Add1~6_combout & (((\vga_ctrl_inst|cnt_v [3] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~6_combout & (((\vga_ctrl_inst|cnt_v [3] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~6_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3]~3 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N3 +dffeas \vga_ctrl_inst|cnt_v[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[3]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|always1~2 ( +// Equation(s): +// \vga_ctrl_inst|always1~2_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [0] & \vga_ctrl_inst|cnt_v [3]))) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|cnt_v [3]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~2 .lut_mask = 16'h0800; +defparam \vga_ctrl_inst|always1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[11]~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[11]~0_combout = ((\vga_ctrl_inst|always1~1_combout & \vga_ctrl_inst|always1~2_combout )) # (!\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|always1~1_combout ), + .datac(\vga_ctrl_inst|always1~2_combout ), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[11]~0 .lut_mask = 16'hC0FF; +defparam \vga_ctrl_inst|cnt_v[11]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[9]~9 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[9]~9_combout = (\vga_ctrl_inst|Add1~18_combout & (((\vga_ctrl_inst|cnt_v [9] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~18_combout & (((\vga_ctrl_inst|cnt_v [9] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~18_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9]~9 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N17 +dffeas \vga_ctrl_inst|cnt_v[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[9]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[6]~8 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[6]~8_combout = (\vga_ctrl_inst|Add1~12_combout & (((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~12_combout & (((\vga_ctrl_inst|cnt_v [6] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~12_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6]~8 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N23 +dffeas \vga_ctrl_inst|cnt_v[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[6]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~4 ( +// Equation(s): +// \vga_ctrl_inst|Add1~4_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|Add1~3 $ (GND))) # (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|Add1~3 & VCC)) +// \vga_ctrl_inst|Add1~5 = CARRY((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Add1~3 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [2]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~3 ), + .combout(\vga_ctrl_inst|Add1~4_combout ), + .cout(\vga_ctrl_inst|Add1~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~4 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[2]~4 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[2]~4_combout = (\vga_ctrl_inst|cnt_v[11]~0_combout & (((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Equal0~3_combout )))) # (!\vga_ctrl_inst|cnt_v[11]~0_combout & ((\vga_ctrl_inst|Add1~4_combout ) # ((\vga_ctrl_inst|cnt_v [2] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datab(\vga_ctrl_inst|Add1~4_combout ), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2]~4 .lut_mask = 16'h44F4; +defparam \vga_ctrl_inst|cnt_v[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N13 +dffeas \vga_ctrl_inst|cnt_v[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[2]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~22 ( +// Equation(s): +// \vga_ctrl_inst|Add1~22_combout = \vga_ctrl_inst|Add1~21 $ (\vga_ctrl_inst|cnt_v [11]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [11]), + .cin(\vga_ctrl_inst|Add1~21 ), + .combout(\vga_ctrl_inst|Add1~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~22 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add1~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[11]~11 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[11]~11_combout = (\vga_ctrl_inst|cnt_v[11]~0_combout & (((\vga_ctrl_inst|cnt_v [11] & !\vga_ctrl_inst|Equal0~3_combout )))) # (!\vga_ctrl_inst|cnt_v[11]~0_combout & ((\vga_ctrl_inst|Add1~22_combout ) # ((\vga_ctrl_inst|cnt_v [11] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datab(\vga_ctrl_inst|Add1~22_combout ), + .datac(\vga_ctrl_inst|cnt_v [11]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[11]~11 .lut_mask = 16'h44F4; +defparam \vga_ctrl_inst|cnt_v[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N29 +dffeas \vga_ctrl_inst|cnt_v[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[11]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [11]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[11] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~2 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~2_combout = (!\vga_ctrl_inst|cnt_v [10] & (!\vga_ctrl_inst|cnt_v [11] & (!\vga_ctrl_inst|cnt_h [11] & !\vga_ctrl_inst|cnt_h [10]))) + + .dataa(\vga_ctrl_inst|cnt_v [10]), + .datab(\vga_ctrl_inst|cnt_v [11]), + .datac(\vga_ctrl_inst|cnt_h [11]), + .datad(\vga_ctrl_inst|cnt_h [10]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~2 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~4 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~4_combout = (\vga_ctrl_inst|pix_data_req~2_combout & ((\vga_ctrl_inst|always1~0_combout ) # (!\vga_ctrl_inst|cnt_v [9]))) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|pix_data_req~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~4 .lut_mask = 16'hAF00; +defparam \vga_ctrl_inst|pix_data_req~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~6 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~6_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|cnt_h [9] & ((\vga_ctrl_inst|Equal0~0_combout ) # (!\vga_ctrl_inst|LessThan4~0_combout )))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Equal0~0_combout & +// (\vga_ctrl_inst|cnt_h [9] & \vga_ctrl_inst|LessThan4~0_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(\vga_ctrl_inst|LessThan4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~6 .lut_mask = 16'h180C; +defparam \vga_ctrl_inst|pix_data_req~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~7 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~7_combout = (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|pix_data_req~5_combout ) # (\vga_ctrl_inst|pix_data_req~6_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~1_combout ), + .datab(\vga_ctrl_inst|pix_data_req~5_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|pix_data_req~6_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~7 .lut_mask = 16'hA080; +defparam \vga_ctrl_inst|pix_data_req~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~11 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~11_combout = ((\vga_ctrl_inst|Add2~16_combout ) # ((\vga_ctrl_inst|Add2~14_combout & \vga_ctrl_inst|Add2~12_combout ))) # (!\vga_ctrl_inst|pix_data_req~7_combout ) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|pix_data_req~7_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~11 .lut_mask = 16'hFBF3; +defparam \vga_pic_inst|pix_data[13]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N6 +cycloneive_lcell_comb \vga_pic_inst|always0~0 ( +// Equation(s): +// \vga_pic_inst|always0~0_combout = (\vga_ctrl_inst|Add2~16_combout ) # ((\vga_ctrl_inst|Add2~18_combout ) # ((!\vga_pic_inst|pix_data[13]~11_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ))) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[13]~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|always0~0 .lut_mask = 16'hEFFF; +defparam \vga_pic_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~13 ( +// Equation(s): +// \vga_pic_inst|pix_data~13_combout = (\vga_pic_inst|LessThan14~0_combout & (((\vga_ctrl_inst|Add2~12_combout )) # (!\vga_pic_inst|pix_data~12_combout ))) # (!\vga_pic_inst|LessThan14~0_combout & (\vga_pic_inst|always0~0_combout & +// ((\vga_ctrl_inst|Add2~12_combout ) # (!\vga_pic_inst|pix_data~12_combout )))) + + .dataa(\vga_pic_inst|LessThan14~0_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_ctrl_inst|Add2~12_combout ), + .datad(\vga_pic_inst|always0~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~13 .lut_mask = 16'hF3A2; +defparam \vga_pic_inst|pix_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~17 ( +// Equation(s): +// \vga_pic_inst|pix_data~17_combout = (!\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_ctrl_inst|Add2~12_combout )) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~17_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~17 .lut_mask = 16'h0500; +defparam \vga_pic_inst|pix_data~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N10 +cycloneive_lcell_comb \vga_pic_inst|pix_data~34 ( +// Equation(s): +// \vga_pic_inst|pix_data~34_combout = ((!\vga_ctrl_inst|Add2~18_combout & (\vga_ctrl_inst|pix_data_req~7_combout & \vga_pic_inst|pix_data~17_combout ))) # (!\vga_pic_inst|pix_data~16_combout ) + + .dataa(\vga_pic_inst|pix_data~16_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data~17_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~34_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~34 .lut_mask = 16'h7555; +defparam \vga_pic_inst|pix_data~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N16 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~8 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~8_combout = (!\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|Add2~14_combout ) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~8 .lut_mask = 16'h55FF; +defparam \vga_pic_inst|pix_data[13]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~9 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~9_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~18_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_pic_inst|pix_data[13]~8_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|pix_data[13]~8_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~9 .lut_mask = 16'h0200; +defparam \vga_pic_inst|pix_data[13]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~10 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~10_combout = (!\vga_ctrl_inst|Add2~20_combout & (\vga_ctrl_inst|pix_data_req~7_combout & \vga_pic_inst|pix_data[13]~9_combout )) + + .dataa(\vga_ctrl_inst|Add2~20_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[13]~9_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~10 .lut_mask = 16'h5000; +defparam \vga_pic_inst|pix_data[13]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N8 +cycloneive_lcell_comb \vga_pic_inst|pix_data~18 ( +// Equation(s): +// \vga_pic_inst|pix_data~18_combout = ((!\vga_ctrl_inst|pix_x[11]~0_combout & (!\vga_pic_inst|pix_data~13_combout & !\vga_pic_inst|pix_data[13]~10_combout ))) # (!\vga_pic_inst|pix_data~34_combout ) + + .dataa(\vga_ctrl_inst|pix_x[11]~0_combout ), + .datab(\vga_pic_inst|pix_data~13_combout ), + .datac(\vga_pic_inst|pix_data~34_combout ), + .datad(\vga_pic_inst|pix_data[13]~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~18 .lut_mask = 16'h0F1F; +defparam \vga_pic_inst|pix_data~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N9 +dffeas \vga_pic_inst|pix_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~20 ( +// Equation(s): +// \vga_ctrl_inst|Add2~20_combout = \vga_ctrl_inst|Add2~19 $ (\vga_ctrl_inst|cnt_h [11]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [11]), + .cin(\vga_ctrl_inst|Add2~19 ), + .combout(\vga_ctrl_inst|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~20 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add2~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N28 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~4 ( +// Equation(s): +// \vga_pic_inst|LessThan17~4_combout = (!\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~10_combout & (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_ctrl_inst|Add2~12_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~4 .lut_mask = 16'h0010; +defparam \vga_pic_inst|LessThan17~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N20 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~3 ( +// Equation(s): +// \vga_pic_inst|LessThan17~3_combout = (!\vga_ctrl_inst|Add2~18_combout & (!\vga_ctrl_inst|Add2~20_combout & (\vga_ctrl_inst|Add2~16_combout & \vga_pic_inst|LessThan17~4_combout ))) + + .dataa(\vga_ctrl_inst|Add2~18_combout ), + .datab(\vga_ctrl_inst|Add2~20_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|LessThan17~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~3 .lut_mask = 16'h1000; +defparam \vga_pic_inst|LessThan17~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N14 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~0 ( +// Equation(s): +// \vga_pic_inst|LessThan14~0_combout = (\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~10_combout & \vga_ctrl_inst|Add2~12_combout )) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~10_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~0 .lut_mask = 16'hA000; +defparam \vga_pic_inst|LessThan14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~19 ( +// Equation(s): +// \vga_pic_inst|pix_data~19_combout = (\vga_pic_inst|LessThan17~3_combout ) # ((!\vga_ctrl_inst|pix_x[11]~0_combout & (!\vga_pic_inst|LessThan14~0_combout & !\vga_pic_inst|always0~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_x[11]~0_combout ), + .datab(\vga_pic_inst|LessThan17~3_combout ), + .datac(\vga_pic_inst|LessThan14~0_combout ), + .datad(\vga_pic_inst|always0~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~19_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~19 .lut_mask = 16'hCCCD; +defparam \vga_pic_inst|pix_data~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~20 ( +// Equation(s): +// \vga_pic_inst|pix_data~20_combout = ((!\vga_pic_inst|pix_data[13]~10_combout & \vga_pic_inst|pix_data~19_combout )) # (!\vga_pic_inst|pix_data~34_combout ) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data[13]~10_combout ), + .datac(\vga_pic_inst|pix_data~34_combout ), + .datad(\vga_pic_inst|pix_data~19_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~20 .lut_mask = 16'h3F0F; +defparam \vga_pic_inst|pix_data~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N19 +dffeas \vga_pic_inst|pix_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[0] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add6~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add6~0_combout = (\vga_ctrl_inst|pix_data_req~3_combout & (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_pic_inst|pix_data [4] & \vga_pic_inst|pix_data [0]))) + + .dataa(\vga_ctrl_inst|pix_data_req~3_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datac(\vga_pic_inst|pix_data [4]), + .datad(\vga_pic_inst|pix_data [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add6~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add6~0 .lut_mask = 16'h8000; +defparam \hdmi_ctrl_inst|encode_inst0|Add6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|data_in_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_in_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_in_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout = !\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0 .lut_mask = 16'h00FF; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N21 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y22_N27 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~0_combout = (!\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|cnt_v [2] & ((!\vga_ctrl_inst|cnt_v [1]) # (!\vga_ctrl_inst|cnt_v [0])))) + + .dataa(\vga_ctrl_inst|cnt_v [0]), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|cnt_v [2]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~0 .lut_mask = 16'h0013; +defparam \vga_ctrl_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~1_combout = (\vga_ctrl_inst|LessThan6~0_combout & ((\vga_ctrl_inst|cnt_v [4] & ((!\vga_ctrl_inst|always1~0_combout ))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|pix_data_req~0_combout )))) # +// (!\vga_ctrl_inst|LessThan6~0_combout & (((!\vga_ctrl_inst|always1~0_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~0_combout ), + .datab(\vga_ctrl_inst|always1~0_combout ), + .datac(\vga_ctrl_inst|LessThan6~0_combout ), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~1 .lut_mask = 16'h3353; +defparam \vga_ctrl_inst|pix_data_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N28 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[1]~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb[1]~0_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_pic_inst|pix_data [4] & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_pic_inst|pix_data [4]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[1]~0 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N29 +dffeas \hdmi_ctrl_inst|encode_inst0|data_in_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N30 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[2]~1 ( +// Equation(s): +// \vga_ctrl_inst|rgb[2]~1_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~1_combout & \vga_pic_inst|pix_data [0]))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\vga_pic_inst|pix_data [0]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[2]~1 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N31 +dffeas \hdmi_ctrl_inst|encode_inst0|data_in_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[2]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add14~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add14~0_combout = (\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]) # ((\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]) # (\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add14~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add14~0 .lut_mask = 16'hFFFC; +defparam \hdmi_ctrl_inst|encode_inst0|Add14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout = !\hdmi_ctrl_inst|encode_inst0|Add14~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|Add14~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0 .lut_mask = 16'h00FF; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N9 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n0[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add19~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [1] & \hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add19~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~2_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [2] & (!\hdmi_ctrl_inst|encode_inst0|Add19~1 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst0|Add19~1 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add19~3 = CARRY((!\hdmi_ctrl_inst|encode_inst0|Add19~1 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [2])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add19~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add19~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~2 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~6_combout = \hdmi_ctrl_inst|encode_inst0|cnt [4] $ (\hdmi_ctrl_inst|encode_inst0|Add19~5 ) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add19~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~6 .lut_mask = 16'h3C3C; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [1] & ((\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]) # (GND))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] $ (VCC))) +// \hdmi_ctrl_inst|encode_inst0|Add22~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [1]) # (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add22~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~0 .lut_mask = 16'h99EE; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~2_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|Add22~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [2] & (!\hdmi_ctrl_inst|encode_inst0|Add22~1 )) +// \hdmi_ctrl_inst|encode_inst0|Add22~3 = CARRY((!\hdmi_ctrl_inst|encode_inst0|cnt [2] & !\hdmi_ctrl_inst|encode_inst0|Add22~1 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add22~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add22~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~2 .lut_mask = 16'hA505; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~6_combout = \hdmi_ctrl_inst|encode_inst0|Add22~5 $ (!\hdmi_ctrl_inst|encode_inst0|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst0|Add22~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~6 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~2_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout ) # ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst0|Add19~6_combout )) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst0|Add22~6_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add19~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add22~6_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~2 .lut_mask = 16'hFBEA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[0]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0]~0 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N17 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n0[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add14~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~9_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add22~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add22~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~9_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~9 .lut_mask = 16'hAF44; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~10 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~10_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~9_combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2])) # (!\hdmi_ctrl_inst|encode_inst0|Add16~9_combout & +// ((\hdmi_ctrl_inst|encode_inst0|Add19~2_combout ))))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|Add16~9_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|Add19~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add16~9_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~10_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~10 .lut_mask = 16'h5FC0; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add12~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add12~0_combout = (\hdmi_ctrl_inst|encode_inst0|data_in_reg [3] & ((!\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]))) # (!\hdmi_ctrl_inst|encode_inst0|data_in_reg [3] & (\hdmi_ctrl_inst|encode_inst0|data_in_reg [4])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add12~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add12~0 .lut_mask = 16'h0CFC; +defparam \hdmi_ctrl_inst|encode_inst0|Add12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N29 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n1[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add12~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add14~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add14~1_combout = (\hdmi_ctrl_inst|encode_inst0|data_in_reg [3] & (\hdmi_ctrl_inst|encode_inst0|data_in_reg [4] $ (!\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add14~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add14~1 .lut_mask = 16'hC030; +defparam \hdmi_ctrl_inst|encode_inst0|Add14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N19 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n0[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add14~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~13_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add22~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add22~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~13_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~13 .lut_mask = 16'hAF44; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~14 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~14_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~13_combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~13_combout & +// (\hdmi_ctrl_inst|encode_inst0|Add19~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|Add16~13_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add19~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add16~13_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~14_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~14 .lut_mask = 16'h5F88; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y22_N1 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n1[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~15_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] & ((\hdmi_ctrl_inst|encode_inst0|Add17~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] & +// (\hdmi_ctrl_inst|encode_inst0|Add15~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add17~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~15 .lut_mask = 16'hA088; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal2~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])))) # +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~0 .lut_mask = 16'h8421; +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal2~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal2~1_combout = (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~1 .lut_mask = 16'h0F00; +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[0]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout = CARRY((\hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ) # (\hdmi_ctrl_inst|encode_inst0|Equal2~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Equal2~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~6 .lut_mask = 16'h00EE; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[3]~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout = ((\hdmi_ctrl_inst|encode_inst0|Add16~4_combout $ (\hdmi_ctrl_inst|encode_inst0|Add16~6_combout $ (!\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|cnt[3]~14 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~4_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~6_combout ) # (!\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~4_combout & +// (\hdmi_ctrl_inst|encode_inst0|Add16~6_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[3]~14 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3]~13 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add4~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add4~1_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout )) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add4~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add4~1 .lut_mask = 16'hA000; +defparam \hdmi_ctrl_inst|encode_inst0|Add4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N17 +dffeas \hdmi_ctrl_inst|encode_inst2|de_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add4~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|de_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|de_reg1 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|de_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout = \hdmi_ctrl_inst|encode_inst2|de_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|de_reg1~q ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N1 +dffeas \hdmi_ctrl_inst|encode_inst2|de_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N13 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_2~combout = (\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout & (((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3]))) # +// (!\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_2 .lut_mask = 16'h3B0A; +defparam \hdmi_ctrl_inst|encode_inst0|condition_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~6_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~5_combout ) # ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~5_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~6 .lut_mask = 16'hBFAA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[4]~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout = \hdmi_ctrl_inst|encode_inst0|Add16~1_combout $ (\hdmi_ctrl_inst|encode_inst0|cnt[3]~14 $ (\hdmi_ctrl_inst|encode_inst0|Add16~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|Add16~2_combout ), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[3]~14 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4]~15 .lut_mask = 16'hA55A; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X38_Y22_N15 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_3~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_3~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & \hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]))) # +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]) # ((!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & \hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~0 .lut_mask = 16'h7150; +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_3~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_3~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (((\hdmi_ctrl_inst|encode_inst0|cnt [4])))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|cnt [4] & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [4] & (\hdmi_ctrl_inst|encode_inst0|condition_3~1_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~2 .lut_mask = 16'hF2C2; +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~1_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [1] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_reg [1]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~1 .lut_mask = 16'h87D2; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~1_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~0_combout = (\vga_ctrl_inst|cnt_h [7]) # ((\vga_ctrl_inst|cnt_h [10]) # ((\vga_ctrl_inst|cnt_h [9]) # (\vga_ctrl_inst|cnt_h [11]))) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(\vga_ctrl_inst|cnt_h [11]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~0 .lut_mask = 16'hFFFE; +defparam \vga_ctrl_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~1_combout = (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|LessThan0~0_combout & ((!\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|cnt_h [6])))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|cnt_h [5]), + .datad(\vga_ctrl_inst|LessThan0~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~1 .lut_mask = 16'h0015; +defparam \vga_ctrl_inst|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y20_N27 +dffeas \hdmi_ctrl_inst|encode_inst2|c0_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|LessThan0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c0_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg1 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y20_N25 +dffeas \hdmi_ctrl_inst|encode_inst2|c0_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y22_N9 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m[7]~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout = \hdmi_ctrl_inst|encode_inst0|data_in_reg [4] $ (\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m[7]~1 .lut_mask = 16'h33CC; +defparam \hdmi_ctrl_inst|encode_inst0|q_m[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N25 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~4_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [5] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_reg [5]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~4 .lut_mask = 16'hC35A; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N29 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan1~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan1~0_combout = (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [3] & \vga_ctrl_inst|always1~1_combout ))) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|always1~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan1~0 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|LessThan1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N15 +dffeas \hdmi_ctrl_inst|encode_inst2|c1_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|LessThan1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c1_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg1 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout = \hdmi_ctrl_inst|encode_inst2|c1_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|c1_reg1~q ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N5 +dffeas \hdmi_ctrl_inst|encode_inst2|c1_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~7_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst2|c0_reg2~q $ +// (!\hdmi_ctrl_inst|encode_inst2|c1_reg2~q )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~7 .lut_mask = 16'hACA3; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N5 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [9]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[9] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout = (\hdmi_ctrl_inst|encode_inst0|data_out [9] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [9]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4 .lut_mask = 16'hC0C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N1 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [3]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N7 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out [3]), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1 .lut_mask = 16'hAFA0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [1])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [1]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y22_N25 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~3_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~3 .lut_mask = 16'hA3A3; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N17 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst0|data_out [2]))) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [2])) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1 .lut_mask = 16'hCACA; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N21 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [0])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_out [0]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0 .lut_mask = 16'hF3C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N9 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y22_N18 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N16 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~2 ( +// Equation(s): +// \vga_pic_inst|LessThan17~2_combout = (!\vga_ctrl_inst|Add2~12_combout & (!\vga_ctrl_inst|Add2~10_combout & \vga_ctrl_inst|pix_data_req~7_combout )) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~2 .lut_mask = 16'h1010; +defparam \vga_pic_inst|LessThan17~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data[9]~15 ( +// Equation(s): +// \vga_pic_inst|pix_data[9]~15_combout = (\vga_pic_inst|pix_data[9]~14_combout & (!\vga_ctrl_inst|Add2~18_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_pic_inst|LessThan17~2_combout ))) + + .dataa(\vga_pic_inst|pix_data[9]~14_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|LessThan17~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[9]~15_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9]~15 .lut_mask = 16'h0200; +defparam \vga_pic_inst|pix_data[9]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~35 ( +// Equation(s): +// \vga_pic_inst|pix_data~35_combout = (\vga_pic_inst|LessThan10~0_combout ) # ((\vga_ctrl_inst|Add2~18_combout ) # ((\vga_pic_inst|pix_data[13]~11_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ))) + + .dataa(\vga_pic_inst|LessThan10~0_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[13]~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~35_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~35 .lut_mask = 16'hFFEF; +defparam \vga_pic_inst|pix_data~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~36 ( +// Equation(s): +// \vga_pic_inst|pix_data~36_combout = (\vga_pic_inst|always0~2_combout & (!\vga_ctrl_inst|Add2~20_combout & (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_pic_inst|pix_data[9]~15_combout ))) + + .dataa(\vga_pic_inst|always0~2_combout ), + .datab(\vga_ctrl_inst|Add2~20_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[9]~15_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~36_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~36 .lut_mask = 16'h0020; +defparam \vga_pic_inst|pix_data~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N6 +cycloneive_lcell_comb \vga_pic_inst|pix_data~21 ( +// Equation(s): +// \vga_pic_inst|pix_data~21_combout = (\vga_pic_inst|pix_data~12_combout & (!\vga_ctrl_inst|Add2~12_combout & ((\vga_pic_inst|LessThan14~0_combout ) # (\vga_pic_inst|always0~0_combout )))) + + .dataa(\vga_pic_inst|LessThan14~0_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_ctrl_inst|Add2~12_combout ), + .datad(\vga_pic_inst|always0~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~21_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~21 .lut_mask = 16'h0C08; +defparam \vga_pic_inst|pix_data~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N22 +cycloneive_lcell_comb \vga_pic_inst|pix_data~26 ( +// Equation(s): +// \vga_pic_inst|pix_data~26_combout = (\vga_pic_inst|pix_data~36_combout & ((\vga_pic_inst|pix_data~25_combout ) # ((\vga_pic_inst|pix_data~35_combout & \vga_pic_inst|pix_data~21_combout )))) + + .dataa(\vga_pic_inst|pix_data~25_combout ), + .datab(\vga_pic_inst|pix_data~35_combout ), + .datac(\vga_pic_inst|pix_data~36_combout ), + .datad(\vga_pic_inst|pix_data~21_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~26_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~26 .lut_mask = 16'hE0A0; +defparam \vga_pic_inst|pix_data~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|pix_x[11]~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_x[11]~0_combout = (\vga_ctrl_inst|Add2~20_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~20_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_x[11]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_x[11]~0 .lut_mask = 16'hFF0F; +defparam \vga_ctrl_inst|pix_x[11]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N8 +cycloneive_lcell_comb \vga_pic_inst|pix_data~27 ( +// Equation(s): +// \vga_pic_inst|pix_data~27_combout = (\vga_pic_inst|pix_data~26_combout ) # ((!\vga_pic_inst|always0~2_combout & (!\vga_pic_inst|pix_data[9]~15_combout & !\vga_ctrl_inst|pix_x[11]~0_combout ))) + + .dataa(\vga_pic_inst|always0~2_combout ), + .datab(\vga_pic_inst|pix_data[9]~15_combout ), + .datac(\vga_pic_inst|pix_data~26_combout ), + .datad(\vga_ctrl_inst|pix_x[11]~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~27_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~27 .lut_mask = 16'hF0F1; +defparam \vga_pic_inst|pix_data~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y21_N9 +dffeas \vga_pic_inst|pix_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[10] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N14 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[10]~2 ( +// Equation(s): +// \vga_ctrl_inst|rgb[10]~2_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_pic_inst|pix_data [10] & \vga_ctrl_inst|pix_data_req~1_combout ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(\vga_pic_inst|pix_data [10]), + .datad(\vga_ctrl_inst|pix_data_req~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[10]~2 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N15 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[10]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[7] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~29 ( +// Equation(s): +// \vga_pic_inst|pix_data~29_combout = (\vga_ctrl_inst|pix_data_req~7_combout & ((\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~10_combout & !\vga_ctrl_inst|Add2~12_combout )) # (!\vga_ctrl_inst|Add2~14_combout & +// ((\vga_ctrl_inst|Add2~12_combout ))))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~29_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~29 .lut_mask = 16'h5020; +defparam \vga_pic_inst|pix_data~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~30 ( +// Equation(s): +// \vga_pic_inst|pix_data~30_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~20_combout & (!\vga_ctrl_inst|Add2~16_combout & !\vga_ctrl_inst|Add2~18_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_ctrl_inst|Add2~20_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~18_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~30_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~30 .lut_mask = 16'h0002; +defparam \vga_pic_inst|pix_data~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~31 ( +// Equation(s): +// \vga_pic_inst|pix_data~31_combout = (\vga_pic_inst|LessThan17~3_combout ) # ((\vga_pic_inst|pix_data~29_combout & \vga_pic_inst|pix_data~30_combout )) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data~29_combout ), + .datac(\vga_pic_inst|pix_data~30_combout ), + .datad(\vga_pic_inst|LessThan17~3_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~31_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~31 .lut_mask = 16'hFFC0; +defparam \vga_pic_inst|pix_data~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y21_N5 +dffeas \vga_pic_inst|pix_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[8] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N4 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[6]~4 ( +// Equation(s): +// \vga_ctrl_inst|rgb[6]~4_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~4_combout & \vga_pic_inst|pix_data [8]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[6]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[6]~4 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[6]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N5 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[6]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add5~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add5~0_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~1_combout & (\vga_pic_inst|pix_data [8] & ((\vga_pic_inst|pix_data [9]) # (\vga_pic_inst|pix_data [10])))) + + .dataa(\vga_pic_inst|pix_data [9]), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~1_combout ), + .datac(\vga_pic_inst|pix_data [10]), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add5~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add5~0 .lut_mask = 16'hC800; +defparam \hdmi_ctrl_inst|encode_inst1|Add5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N27 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add14~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add14~1_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])))) # +// (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add14~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add14~1 .lut_mask = 16'h6006; +defparam \hdmi_ctrl_inst|encode_inst1|Add14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N25 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n0[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add14~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~28 ( +// Equation(s): +// \vga_pic_inst|pix_data~28_combout = (\vga_pic_inst|pix_data~36_combout & ((\vga_pic_inst|pix_data~25_combout ) # ((\vga_pic_inst|pix_data~35_combout & \vga_pic_inst|pix_data~21_combout )))) + + .dataa(\vga_pic_inst|pix_data~25_combout ), + .datab(\vga_pic_inst|pix_data~35_combout ), + .datac(\vga_pic_inst|pix_data~36_combout ), + .datad(\vga_pic_inst|pix_data~21_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~28_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~28 .lut_mask = 16'hE0A0; +defparam \vga_pic_inst|pix_data~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y21_N3 +dffeas \vga_pic_inst|pix_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N8 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[7]~3 ( +// Equation(s): +// \vga_ctrl_inst|rgb[7]~3_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~4_combout & \vga_pic_inst|pix_data [9]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|pix_data [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[7]~3 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N9 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[7]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add13~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add13~0_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [4])) # (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & +// ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]))))) # (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]))) # (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & +// (\hdmi_ctrl_inst|encode_inst1|data_in_reg [4])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add13~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add13~0 .lut_mask = 16'hF690; +defparam \hdmi_ctrl_inst|encode_inst1|Add13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N13 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n1[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add13~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add13~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add13~1_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & \hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])) # (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & +// ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]) # (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add13~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add13~1 .lut_mask = 16'hF330; +defparam \hdmi_ctrl_inst|encode_inst1|Add13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N29 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add13~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_3~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_3~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & !\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~0 .lut_mask = 16'h08AE; +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_3~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_3~1_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]) # ((!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~1 .lut_mask = 16'h7510; +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add14~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add14~2_combout = (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & !\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add14~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add14~2 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst1|Add14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n0[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add14~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X33_Y21_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n1[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~0_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add15~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [0] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~4_combout = ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] $ (\hdmi_ctrl_inst|encode_inst1|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst1|Add15~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|Add15~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst1|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst1|Add15~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst1|Add15~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add14~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add14~0_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & (((!\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & !\hdmi_ctrl_inst|encode_inst1|data_in_reg [7])) # (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]) # ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]) # (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add14~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add14~0 .lut_mask = 16'h37FE; +defparam \hdmi_ctrl_inst|encode_inst1|Add14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N17 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n0[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add14~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// (\hdmi_ctrl_inst|encode_inst1|Add23~1 & VCC)))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst1|Add23~1 ) # (GND))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst1|Add23~1 )))) +// \hdmi_ctrl_inst|encode_inst1|Add23~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst1|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & +// ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst1|Add23~1 )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add23~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add23~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~2 .lut_mask = 16'h694D; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~9_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add17~4_combout ) # (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add23~2_combout & ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add23~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add17~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~9_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~9 .lut_mask = 16'hAAE4; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~10 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~10_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~9_combout & (((\hdmi_ctrl_inst|encode_inst1|Add15~4_combout ) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|Add16~9_combout & (\hdmi_ctrl_inst|encode_inst1|Add20~2_combout & ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add20~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add15~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~9_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~10_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~10 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout = !\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2] + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N23 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~15_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|Add17~0_combout )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & +// ((\hdmi_ctrl_inst|encode_inst1|Add15~0_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add17~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add15~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~15 .lut_mask = 16'hA0C0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[0]~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & (\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & +// (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & +// ((\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|cnt[0]~8 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & +// ((!\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ) # (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~16_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~15_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~7 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal1~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal1~0_combout = (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & (!\hdmi_ctrl_inst|encode_inst1|cnt [0] & (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & !\hdmi_ctrl_inst|encode_inst1|cnt [4]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .datac(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~0 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal1~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal1~1_combout = (\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout & !\hdmi_ctrl_inst|encode_inst1|cnt [3]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~1 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[0]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout = CARRY((\hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ) # (\hdmi_ctrl_inst|encode_inst1|Equal1~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Equal1~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~6 .lut_mask = 16'h00EE; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[1]~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout = ((\hdmi_ctrl_inst|encode_inst1|Add16~14_combout $ (\hdmi_ctrl_inst|encode_inst1|Add16~12_combout $ (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|cnt[1]~10 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~14_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~12_combout ) # (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~14_combout & +// (\hdmi_ctrl_inst|encode_inst1|Add16~12_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~14_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~12_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1]~9 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[2]~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & (\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & +// (!\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & (!\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & +// ((\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|cnt[2]~12 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & +// ((!\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ) # (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2]~11 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N15 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~3_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst1|Add20~4_combout )) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst1|Add23~4_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add20~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add23~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~3 .lut_mask = 16'hEE50; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~4_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~3_combout & (((\hdmi_ctrl_inst|encode_inst1|Add15~6_combout ) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~3_combout +// & (\hdmi_ctrl_inst|encode_inst1|Add17~6_combout & ((\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add17~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add15~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~3_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~4 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[3]~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout = ((\hdmi_ctrl_inst|encode_inst1|Add16~6_combout $ (\hdmi_ctrl_inst|encode_inst1|Add16~4_combout $ (!\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|cnt[3]~14 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~6_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~4_combout ) # (!\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~6_combout & +// (\hdmi_ctrl_inst|encode_inst1|Add16~4_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[3]~14 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3]~13 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N17 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal2~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal2~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] $ (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) # +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] $ (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~0 .lut_mask = 16'h8241; +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_2~combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & +// ((\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ) # ((!\hdmi_ctrl_inst|encode_inst1|cnt [3] & \hdmi_ctrl_inst|encode_inst1|Equal1~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datac(\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_2 .lut_mask = 16'h7350; +defparam \hdmi_ctrl_inst|encode_inst1|condition_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[0]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0]~0 .lut_mask = 16'h22EE; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~11_combout = (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst1|Add19~0_combout ) # (\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst1|Add22~0_combout & ((!\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add22~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add19~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~11_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~11 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~12 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~12_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~11_combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~11_combout & +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1])))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add16~11_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|Add16~11_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~12_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~12 .lut_mask = 16'h5F22; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y21_N13 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~6_combout = \hdmi_ctrl_inst|encode_inst1|Add22~5 $ (!\hdmi_ctrl_inst|encode_inst1|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst1|Add22~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~6 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~2_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout ) # ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst1|Add19~6_combout )) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst1|Add22~6_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add19~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add22~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~2 .lut_mask = 16'hFFAC; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[4]~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout = \hdmi_ctrl_inst|encode_inst1|Add16~1_combout $ (\hdmi_ctrl_inst|encode_inst1|cnt[3]~14 $ (\hdmi_ctrl_inst|encode_inst1|Add16~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|Add16~2_combout ), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[3]~14 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4]~15 .lut_mask = 16'hA55A; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N19 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_3~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_3~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (((\hdmi_ctrl_inst|encode_inst1|cnt [4])))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst1|cnt [4] & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~0_combout )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [4] & ((\hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~2 .lut_mask = 16'hEE50; +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N19 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~1_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [3] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~1 .lut_mask = 16'hA53C; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out~1_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N1 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~3_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [5] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [5]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~3 .lut_mask = 16'h9A56; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~3_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out~3_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N29 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst1|data_out [5]))) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [3])) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2 .lut_mask = 16'hCACA; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N21 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [2]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [3]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [3]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~7_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~7 .lut_mask = 16'hAF05; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N29 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout = (\hdmi_ctrl_inst|encode_inst1|data_out [8] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4 .lut_mask = 16'hCC00; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N27 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [2])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [4]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [2]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [4]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N23 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [4])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [3]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [4]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [3]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N19 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [2])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [2]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1 .lut_mask = 16'hBB88; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [0])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [1]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [0]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [1]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y23_N11 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~33 ( +// Equation(s): +// \vga_pic_inst|pix_data~33_combout = (\vga_pic_inst|pix_data~37_combout & ((\vga_pic_inst|pix_data[13]~10_combout ) # (\vga_pic_inst|pix_data~19_combout ))) + + .dataa(\vga_pic_inst|pix_data~37_combout ), + .datab(\vga_pic_inst|pix_data[13]~10_combout ), + .datac(gnd), + .datad(\vga_pic_inst|pix_data~19_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~33_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~33 .lut_mask = 16'hAA88; +defparam \vga_pic_inst|pix_data~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N15 +dffeas \vga_pic_inst|pix_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N22 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[13]~6 ( +// Equation(s): +// \vga_ctrl_inst|rgb[13]~6_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_pic_inst|pix_data [13] & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_pic_inst|pix_data [13]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[13]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[13]~6 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[13]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N23 +dffeas \hdmi_ctrl_inst|encode_inst2|data_in_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[13]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~32 ( +// Equation(s): +// \vga_pic_inst|pix_data~32_combout = (\vga_pic_inst|pix_data~37_combout & (!\vga_ctrl_inst|pix_x[11]~0_combout & ((\vga_pic_inst|pix_data[13]~9_combout ) # (!\vga_pic_inst|pix_data~13_combout )))) + + .dataa(\vga_pic_inst|pix_data~37_combout ), + .datab(\vga_pic_inst|pix_data~13_combout ), + .datac(\vga_pic_inst|pix_data[13]~9_combout ), + .datad(\vga_ctrl_inst|pix_x[11]~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~32_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~32 .lut_mask = 16'h00A2; +defparam \vga_pic_inst|pix_data~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N5 +dffeas \vga_pic_inst|pix_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~32_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[15] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add6~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add6~0_combout = (\vga_ctrl_inst|pix_data_req~3_combout & (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_pic_inst|pix_data [13] & \vga_pic_inst|pix_data [15]))) + + .dataa(\vga_ctrl_inst|pix_data_req~3_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datac(\vga_pic_inst|pix_data [13]), + .datad(\vga_pic_inst|pix_data [15]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add6~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add6~0 .lut_mask = 16'h8000; +defparam \hdmi_ctrl_inst|encode_inst2|Add6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N27 +dffeas \hdmi_ctrl_inst|encode_inst2|data_in_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_in_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_in_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N20 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[12]~5 ( +// Equation(s): +// \vga_ctrl_inst|rgb[12]~5_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_pic_inst|pix_data [15] & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_pic_inst|pix_data [15]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[12]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[12]~5 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[12]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N21 +dffeas \hdmi_ctrl_inst|encode_inst2|data_in_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[12]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add12~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add12~0_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3] & (!\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2])) # (!\hdmi_ctrl_inst|encode_inst2|data_in_reg [3] & ((\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add12~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add12~0 .lut_mask = 16'h3F0C; +defparam \hdmi_ctrl_inst|encode_inst2|Add12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N5 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n1[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add12~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add14~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add14~0_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]) # ((\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]) # (\hdmi_ctrl_inst|encode_inst2|data_in_reg [4])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add14~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add14~0 .lut_mask = 16'hFFFC; +defparam \hdmi_ctrl_inst|encode_inst2|Add14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N1 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n0[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add14~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add12~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add12~1_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] & !\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add12~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add12~1 .lut_mask = 16'h00F0; +defparam \hdmi_ctrl_inst|encode_inst2|Add12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N23 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add12~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_3~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_3~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & !\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~0 .lut_mask = 16'h20F2; +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout = !\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N7 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal2~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal2~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] $ (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2])))) # +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] $ (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~0 .lut_mask = 16'h9009; +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~0_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add19~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [1] & \hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add19~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~5_combout = (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst2|Add19~4_combout ))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst2|Add22~4_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add22~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add19~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~5 .lut_mask = 16'h0C0A; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~6_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~5_combout ) # ((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~5_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~6 .lut_mask = 16'hF7F0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal1~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal1~0_combout = (!\hdmi_ctrl_inst|encode_inst2|cnt [4] & (!\hdmi_ctrl_inst|encode_inst2|cnt [0] & (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & !\hdmi_ctrl_inst|encode_inst2|cnt [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~0 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal1~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal1~1_combout = (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & \hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~1 .lut_mask = 16'h0F00; +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[0]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout = CARRY((\hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ) # (\hdmi_ctrl_inst|encode_inst2|Equal1~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Equal1~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~6 .lut_mask = 16'h00EE; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[0]~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & (\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & +// (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & +// ((\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|cnt[0]~8 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & +// ((!\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ) # (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~16_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~15_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~7 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y24_N3 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & (\hdmi_ctrl_inst|encode_inst2|cnt [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & (\hdmi_ctrl_inst|encode_inst2|cnt [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add15~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & \hdmi_ctrl_inst|encode_inst2|cnt [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~15_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst2|Add17~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] & +// ((\hdmi_ctrl_inst|encode_inst2|Add15~0_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add17~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add15~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~15 .lut_mask = 16'hAC00; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[1]~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout = ((\hdmi_ctrl_inst|encode_inst2|Add16~12_combout $ (\hdmi_ctrl_inst|encode_inst2|Add16~14_combout $ (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|cnt[1]~10 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~12_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~14_combout ) # (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~12_combout & +// (\hdmi_ctrl_inst|encode_inst2|Add16~14_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~12_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1]~9 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[2]~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & (\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & +// (!\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & (!\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & +// ((\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|cnt[2]~12 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & +// ((!\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ) # (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~10_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~8_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2]~11 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[3]~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout = ((\hdmi_ctrl_inst|encode_inst2|Add16~4_combout $ (\hdmi_ctrl_inst|encode_inst2|Add16~6_combout $ (!\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|cnt[3]~14 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~4_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~6_combout ) # (!\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~4_combout & +// (\hdmi_ctrl_inst|encode_inst2|Add16~6_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[3]~14 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3]~13 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y24_N9 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout = !\hdmi_ctrl_inst|encode_inst2|Add14~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|Add14~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0 .lut_mask = 16'h00FF; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N3 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n0[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_2~combout = (\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout & (((\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout & !\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3]))) # +// (!\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout & (\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_2 .lut_mask = 16'h0ACE; +defparam \hdmi_ctrl_inst|encode_inst2|condition_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[0]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0]~0 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~14 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~14_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~13_combout & (((!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~13_combout +// & (\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst2|Add19~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~13_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst2|Add19~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~14_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~14 .lut_mask = 16'h6E2A; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N5 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst2|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// (\hdmi_ctrl_inst|encode_inst2|Add23~1 & VCC)))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst2|Add23~1 ) # (GND))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst2|Add23~1 )))) +// \hdmi_ctrl_inst|encode_inst2|Add23~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst2|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & +// ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst2|Add23~1 )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add23~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add23~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~2 .lut_mask = 16'h694D; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst2|Add20~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// ((\hdmi_ctrl_inst|encode_inst2|Add20~1 ) # (GND))))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst2|Add20~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst2|Add20~1 )))) +// \hdmi_ctrl_inst|encode_inst2|Add20~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((!\hdmi_ctrl_inst|encode_inst2|Add20~1 ) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst2|Add20~1 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add20~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add20~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~2 .lut_mask = 16'h692B; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~7_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst2|Add20~2_combout ))) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst2|Add23~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add23~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add20~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~7 .lut_mask = 16'hFA44; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~8_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~7_combout & (((\hdmi_ctrl_inst|encode_inst2|Add15~4_combout ) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~7_combout +// & (\hdmi_ctrl_inst|encode_inst2|Add17~4_combout & ((\hdmi_ctrl_inst|encode_inst2|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add17~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add15~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~7_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~8 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N7 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y24_N9 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n1[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~8_combout = \hdmi_ctrl_inst|encode_inst2|Add17~7 $ (!\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~7 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~8 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~6_combout = !\hdmi_ctrl_inst|encode_inst2|Add23~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst2|Add23~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~0_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|Add17~8_combout ) # ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|Add23~6_combout & !\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add17~8_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add23~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~0 .lut_mask = 16'hAAD8; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~6_combout = !\hdmi_ctrl_inst|encode_inst2|Add20~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst2|Add20~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~1_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~0_combout & ((\hdmi_ctrl_inst|encode_inst2|Add15~8_combout ) # ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~0_combout +// & (((\hdmi_ctrl_inst|encode_inst2|Add20~6_combout & \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add15~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add20~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~1 .lut_mask = 16'hB8CC; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[4]~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout = \hdmi_ctrl_inst|encode_inst2|Add16~2_combout $ (\hdmi_ctrl_inst|encode_inst2|cnt[3]~14 $ (\hdmi_ctrl_inst|encode_inst2|Add16~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|Add16~1_combout ), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[3]~14 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4]~15 .lut_mask = 16'hA55A; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y24_N11 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_3~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_3~2_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [4] & (((\hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ) # (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [4] & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~1_combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~2 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N21 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~1_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [1] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [1]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~1 .lut_mask = 16'hB41E; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out~1_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N1 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m[7]~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout = \hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] $ (\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m[7]~1 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst2|q_m[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N29 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~4_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [5] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [5]), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~4 .lut_mask = 16'h939C; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N17 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~7_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst2|c1_reg2~q $ +// ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~7 .lut_mask = 16'hEB41; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N19 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [9]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[9] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout = (\hdmi_ctrl_inst|encode_inst2|data_out [9] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [9]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4 .lut_mask = 16'hC0C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [4]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3 .lut_mask = 16'hCCF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N9 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [3]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [3]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2 .lut_mask = 16'hCCF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N5 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [3]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [1])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [1]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N21 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y24_N17 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[4]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~6 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout = !\hdmi_ctrl_inst|encode_inst2|c0_reg2~q + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N21 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [6]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[6] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst2|data_out [6]))) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [4])) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [4]), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [6]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3 .lut_mask = 16'hCCAA; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N7 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [4])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [3]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [4]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2 .lut_mask = 16'hBB88; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [2])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [2]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1 .lut_mask = 16'hBB88; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N1 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [0])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [0]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y24_N4 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y22_N25 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y23_N18 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y24_N11 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_8_1200mv_0c_v_slow.sdo b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_8_1200mv_0c_v_slow.sdo new file mode 100644 index 0000000..d17b552 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_8_1200mv_0c_v_slow.sdo @@ -0,0 +1,9062 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "hdmi_colorbar") + (DATE "06/02/2023 04:17:19") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (3921:3921:3921) (3921:3921:3921)) + (PORT inclk[0] (2063:2063:2063) (2063:2063:2063)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1639:1639:1639) (1518:1518:1518)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (PORT sload (1285:1285:1285) (1355:1355:1355)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (PORT sclr (1345:1345:1345) (1474:1474:1474)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (PORT sclr (1345:1345:1345) (1474:1474:1474)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (PORT sclr (1345:1345:1345) (1474:1474:1474)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1611:1611:1611) (1507:1507:1507)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (PORT sload (1671:1671:1671) (1859:1859:1859)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1567:1567:1567) (1377:1377:1377)) + (PORT clrn (1689:1689:1689) (1643:1643:1643)) + (PORT sload (1571:1571:1571) (1688:1688:1688)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1826:1826:1826) (1644:1644:1644)) + (PORT clrn (1689:1689:1689) (1643:1643:1643)) + (PORT sload (1571:1571:1571) (1688:1688:1688)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1131:1131:1131) (958:958:958)) + (PORT datab (640:640:640) (602:602:602)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~2) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (581:581:581)) + (PORT datab (807:807:807) (737:737:737)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~4) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (550:550:550)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (566:566:566)) + (PORT datab (344:344:344) (402:402:402)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (770:770:770)) + (PORT datab (629:629:629) (593:593:593)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (773:773:773)) + (PORT datab (595:595:595) (581:581:581)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~6) + (DELAY + (ABSOLUTE + (PORT datab (654:654:654) (619:619:619)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~8) + (DELAY + (ABSOLUTE + (PORT datab (647:647:647) (607:607:607)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1130:1130:1130) (958:958:958)) + (PORT datab (642:642:642) (605:605:605)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (581:581:581) (579:579:579)) + (PORT datab (807:807:807) (738:738:738)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~4) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (548:548:548)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (569:569:569)) + (PORT datab (348:348:348) (406:406:406)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (780:780:780)) + (PORT datab (631:631:631) (595:595:595)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~4) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (728:728:728)) + (PORT datab (598:598:598) (583:583:583)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~6) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (805:805:805)) + (PORT datab (656:656:656) (621:621:621)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~8) + (DELAY + (ABSOLUTE + (PORT datab (649:649:649) (609:609:609)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (425:425:425)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~4) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (582:582:582)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (269:269:269) (276:276:276)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (653:653:653)) + (PORT datab (266:266:266) (272:272:272)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (479:479:479) (423:423:423)) + (PORT datab (266:266:266) (273:273:273)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1522:1522:1522) (1333:1333:1333)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (PORT sload (1671:1671:1671) (1859:1859:1859)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1193:1193:1193) (1015:1015:1015)) + (PORT datab (1141:1141:1141) (977:977:977)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1100:1100:1100) (951:951:951)) + (PORT datab (1807:1807:1807) (1569:1569:1569)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~4) + (DELAY + (ABSOLUTE + (PORT datab (943:943:943) (820:820:820)) + (IOPATH datab combout (423:423:423) (398:398:398)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (780:780:780)) + (PORT datab (550:550:550) (525:525:525)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (792:792:792)) + (PORT datab (1129:1129:1129) (963:963:963)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (798:798:798)) + (PORT datab (1115:1115:1115) (952:952:952)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~6) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (798:798:798)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~8) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (775:775:775)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1191:1191:1191) (1013:1013:1013)) + (PORT datab (1142:1142:1142) (978:978:978)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~4) + (DELAY + (ABSOLUTE + (PORT datab (944:944:944) (821:821:821)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1801:1801:1801) (1512:1512:1512)) + (PORT datab (898:898:898) (796:796:796)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~6) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (799:799:799)) + (PORT datab (883:883:883) (780:780:780)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~8) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (774:774:774)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (774:774:774)) + (PORT datab (624:624:624) (585:585:585)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~2) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (802:802:802)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (762:762:762)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~6) + (DELAY + (ABSOLUTE + (PORT datad (566:566:566) (551:551:551)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (775:775:775)) + (PORT datab (623:623:623) (584:584:584)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~2) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (800:800:800)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~4) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (761:761:761)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1568:1568:1568) (1378:1378:1378)) + (PORT clrn (1689:1689:1689) (1643:1643:1643)) + (PORT sload (1571:1571:1571) (1688:1688:1688)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (812:812:812)) + (PORT datab (895:895:895) (796:796:796)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~4) + (DELAY + (ABSOLUTE + (PORT datab (813:813:813) (722:722:722)) + (IOPATH datab combout (423:423:423) (398:398:398)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (735:735:735)) + (PORT datab (338:338:338) (392:392:392)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (545:545:545)) + (PORT datab (806:806:806) (720:720:720)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (PORT datab (794:794:794) (711:711:711)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~6) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (736:736:736)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~0) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (812:812:812)) + (PORT datab (891:891:891) (791:791:791)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~4) + (DELAY + (ABSOLUTE + (PORT datab (809:809:809) (719:719:719)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (813:813:813) (729:729:729)) + (PORT datab (348:348:348) (406:406:406)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~4) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (412:412:412)) + (PORT datab (853:853:853) (746:746:746)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~6) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (768:768:768)) + (PORT datab (340:340:340) (396:396:396)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~8) + (DELAY + (ABSOLUTE + (PORT datad (332:332:332) (392:392:392)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~2) + (DELAY + (ABSOLUTE + (PORT datab (560:560:560) (539:539:539)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (548:548:548)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~6) + (DELAY + (ABSOLUTE + (PORT datad (573:573:573) (549:549:549)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (804:804:804)) + (PORT datab (839:839:839) (754:754:754)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~2) + (DELAY + (ABSOLUTE + (PORT datab (562:562:562) (542:542:542)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~4) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (550:550:550)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~6) + (DELAY + (ABSOLUTE + (PORT datad (575:575:575) (551:551:551)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1601:1601:1601) (1403:1403:1403)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (PORT sload (1588:1588:1588) (1701:1701:1701)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1513:1513:1513) (1330:1330:1330)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (PORT sload (1460:1460:1460) (1597:1597:1597)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1638:1638:1638) (1517:1517:1517)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (PORT sload (1285:1285:1285) (1355:1355:1355)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (414:414:414)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (863:863:863)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (610:610:610) (563:563:563)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (556:556:556)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (611:611:611) (566:566:566)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT datab (608:608:608) (566:566:566)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (547:547:547)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT datab (608:608:608) (566:566:566)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datab (575:575:575) (560:560:560)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT datac (278:278:278) (341:341:341)) + (PORT datad (380:380:380) (465:465:465)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (581:581:581)) + (PORT datab (637:637:637) (598:598:598)) + (PORT datac (514:514:514) (502:502:502)) + (PORT datad (504:504:504) (488:488:488)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (763:763:763)) + (PORT datab (630:630:630) (594:594:594)) + (PORT datac (554:554:554) (549:549:549)) + (PORT datad (534:534:534) (525:525:525)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (812:812:812)) + (PORT datab (894:894:894) (795:795:795)) + (PORT datac (886:886:886) (787:787:787)) + (PORT datad (797:797:797) (716:716:716)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT datac (285:285:285) (351:351:351)) + (PORT datad (380:380:380) (465:465:465)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (680:680:680)) + (PORT datab (832:832:832) (728:728:728)) + (PORT datac (742:742:742) (597:597:597)) + (PORT datad (249:249:249) (256:256:256)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~1) + (DELAY + (ABSOLUTE + (PORT dataa (794:794:794) (637:637:637)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (735:735:735) (587:587:587)) + (PORT datad (746:746:746) (623:623:623)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (826:826:826) (704:704:704)) + (PORT datac (521:521:521) (459:459:459)) + (PORT datad (446:446:446) (387:387:387)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (426:426:426)) + (PORT datab (539:539:539) (447:447:447)) + (PORT datac (227:227:227) (242:242:242)) + (PORT datad (789:789:789) (672:672:672)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (865:865:865) (733:733:733)) + (PORT datab (832:832:832) (728:728:728)) + (PORT datac (227:227:227) (242:242:242)) + (PORT datad (466:466:466) (389:389:389)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (845:845:845) (669:669:669)) + (PORT datab (267:267:267) (273:273:273)) + (PORT datac (521:521:521) (458:458:458)) + (PORT datad (788:788:788) (670:670:670)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~8) + (DELAY + (ABSOLUTE + (PORT dataa (743:743:743) (611:611:611)) + (PORT datab (528:528:528) (432:432:432)) + (PORT datac (427:427:427) (368:368:368)) + (PORT datad (503:503:503) (452:452:452)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~11) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (431:431:431)) + (PORT datab (267:267:267) (274:274:274)) + (PORT datac (521:521:521) (459:459:459)) + (PORT datad (787:787:787) (670:670:670)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~12) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (751:751:751) (619:619:619)) + (PORT datac (227:227:227) (242:242:242)) + (PORT datad (785:785:785) (666:666:666)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~16) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (496:496:496)) + (PORT datac (821:821:821) (720:720:720)) + (PORT datad (301:301:301) (357:357:357)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datac (605:605:605) (588:588:588)) + (PORT datad (236:236:236) (248:248:248)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add12\~1) + (DELAY + (ABSOLUTE + (PORT datab (1321:1321:1321) (1146:1146:1146)) + (PORT datad (1229:1229:1229) (1083:1083:1083)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (785:785:785) (714:714:714)) + (PORT datab (925:925:925) (845:845:845)) + (PORT datac (821:821:821) (694:694:694)) + (PORT datad (790:790:790) (689:689:689)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (381:381:381)) + (PORT datab (321:321:321) (376:376:376)) + (PORT datac (1022:1022:1022) (988:988:988)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (763:763:763)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (486:486:486) (413:413:413)) + (PORT datad (1115:1115:1115) (916:916:916)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~1) + (DELAY + (ABSOLUTE + (PORT dataa (740:740:740) (600:600:600)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (225:225:225) (241:241:241)) + (PORT datad (1114:1114:1114) (915:915:915)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (294:294:294) (306:306:306)) + (PORT datab (727:727:727) (601:601:601)) + (PORT datac (1012:1012:1012) (820:820:820)) + (PORT datad (822:822:822) (734:734:734)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1055:1055:1055) (858:858:858)) + (PORT datab (473:473:473) (408:408:408)) + (PORT datac (224:224:224) (239:239:239)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1069:1069:1069) (876:876:876)) + (PORT datab (267:267:267) (274:274:274)) + (PORT datac (1454:1454:1454) (1280:1280:1280)) + (PORT datad (518:518:518) (456:456:456)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~8) + (DELAY + (ABSOLUTE + (PORT dataa (746:746:746) (615:615:615)) + (PORT datab (265:265:265) (272:272:272)) + (PORT datac (1026:1026:1026) (837:837:837)) + (PORT datad (831:831:831) (738:738:738)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~13) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (283:283:283)) + (PORT datab (540:540:540) (450:450:450)) + (PORT datac (848:848:848) (722:722:722)) + (PORT datad (1116:1116:1116) (917:917:917)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~14) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (281:281:281)) + (PORT datab (265:265:265) (272:272:272)) + (PORT datac (438:438:438) (385:385:385)) + (PORT datad (1116:1116:1116) (917:917:917)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~16) + (DELAY + (ABSOLUTE + (PORT datab (867:867:867) (727:727:727)) + (PORT datac (513:513:513) (498:498:498)) + (PORT datad (823:823:823) (737:737:737)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (420:420:420)) + (PORT datad (824:824:824) (736:736:736)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT asdata (754:754:754) (837:837:837)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (432:432:432)) + (PORT datab (806:806:806) (660:660:660)) + (PORT datad (757:757:757) (643:643:643)) + (IOPATH dataa combout (377:377:377) (380:380:380)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (267:267:267) (274:274:274)) + (PORT datac (823:823:823) (693:693:693)) + (PORT datad (764:764:764) (622:622:622)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (754:754:754) (617:617:617)) + (PORT datab (845:845:845) (707:707:707)) + (PORT datac (803:803:803) (669:669:669)) + (PORT datad (229:229:229) (236:236:236)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (386:386:386)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (664:664:664)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (225:225:225) (240:240:240)) + (PORT datad (786:786:786) (668:668:668)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~9) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (735:735:735)) + (PORT datab (267:267:267) (274:274:274)) + (PORT datac (756:756:756) (672:672:672)) + (PORT datad (763:763:763) (645:645:645)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~10) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (854:854:854) (756:756:756)) + (PORT datac (437:437:437) (372:372:372)) + (PORT datad (762:762:762) (644:644:644)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~11) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (281:281:281)) + (PORT datab (741:741:741) (597:597:597)) + (PORT datac (809:809:809) (675:675:675)) + (PORT datad (786:786:786) (669:669:669)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~12) + (DELAY + (ABSOLUTE + (PORT dataa (484:484:484) (415:415:415)) + (PORT datab (537:537:537) (444:444:444)) + (PORT datac (225:225:225) (240:240:240)) + (PORT datad (786:786:786) (669:669:669)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~13) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (737:737:737)) + (PORT datab (592:592:592) (552:552:552)) + (PORT datac (226:226:226) (241:241:241)) + (PORT datad (764:764:764) (646:646:646)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~16) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (423:423:423)) + (PORT datac (796:796:796) (711:711:711)) + (PORT datad (819:819:819) (679:679:679)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (832:832:832) (664:664:664)) + (PORT datad (530:530:530) (508:508:508)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add14\~1) + (DELAY + (ABSOLUTE + (PORT datab (961:961:961) (881:881:881)) + (PORT datac (984:984:984) (930:930:930)) + (PORT datad (922:922:922) (867:867:867)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (430:430:430)) + (PORT datab (317:317:317) (371:371:371)) + (PORT datac (758:758:758) (633:633:633)) + (PORT datad (807:807:807) (652:652:652)) + (IOPATH dataa combout (394:394:394) (419:419:419)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~3) + (DELAY + (ABSOLUTE + (PORT datab (1218:1218:1218) (1080:1080:1080)) + (PORT datac (924:924:924) (862:862:862)) + (PORT datad (746:746:746) (605:605:605)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (754:754:754)) + (PORT datab (346:346:346) (404:404:404)) + (PORT datac (305:305:305) (373:373:373)) + (PORT datad (305:305:305) (363:363:363)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (749:749:749) (636:636:636)) + (PORT datab (853:853:853) (787:787:787)) + (PORT datac (731:731:731) (612:612:612)) + (PORT datad (233:233:233) (243:243:243)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1135:1135:1135) (1013:1013:1013)) + (PORT datad (1227:1227:1227) (1081:1081:1081)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~5) + (DELAY + (ABSOLUTE + (PORT dataa (786:786:786) (719:719:719)) + (PORT datab (925:925:925) (846:846:846)) + (PORT datac (822:822:822) (694:694:694)) + (PORT datad (790:790:790) (688:688:688)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (526:526:526) (504:504:504)) + (PORT datac (1022:1022:1022) (987:987:987)) + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (386:386:386)) + (PORT datab (1044:1044:1044) (975:975:975)) + (PORT datac (276:276:276) (339:339:339)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT asdata (741:741:741) (810:810:810)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~4) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (428:428:428)) + (PORT datab (811:811:811) (665:665:665)) + (PORT datad (750:750:750) (636:636:636)) + (IOPATH dataa combout (377:377:377) (380:380:380)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (982:982:982) (928:928:928)) + (PORT datad (899:899:899) (839:839:839)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~5) + (DELAY + (ABSOLUTE + (PORT dataa (311:311:311) (331:331:331)) + (PORT datab (320:320:320) (374:374:374)) + (PORT datac (546:546:546) (539:539:539)) + (PORT datad (263:263:263) (277:277:277)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_x\[10\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (846:846:846) (724:724:724)) + (PORT datad (515:515:515) (459:459:459)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (804:804:804)) + (PORT datac (1156:1156:1156) (979:979:979)) + (PORT datad (901:901:901) (786:786:786)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (280:280:280)) + (PORT datab (916:916:916) (782:782:782)) + (PORT datac (1470:1470:1470) (1249:1249:1249)) + (PORT datad (256:256:256) (268:268:268)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[9\]\~14) + (DELAY + (ABSOLUTE + (PORT datac (1157:1157:1157) (980:980:980)) + (PORT datad (869:869:869) (760:760:760)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~16) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (308:308:308)) + (PORT datab (282:282:282) (294:294:294)) + (PORT datac (836:836:836) (721:721:721)) + (PORT datad (836:836:836) (720:720:720)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~8) + (DELAY + (ABSOLUTE + (PORT datab (913:913:913) (799:799:799)) + (PORT datac (830:830:830) (735:735:735)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[10\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (282:282:282)) + (PORT datab (1426:1426:1426) (1173:1173:1173)) + (PORT datad (557:557:557) (496:496:496)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (1321:1321:1321) (1146:1146:1146)) + (PORT datac (1136:1136:1136) (1013:1013:1013)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (734:734:734)) + (PORT datab (924:924:924) (844:844:844)) + (PORT datad (791:791:791) (689:689:689)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~4) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (382:382:382)) + (PORT datac (1022:1022:1022) (987:987:987)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (768:768:768)) + (PORT datab (842:842:842) (721:721:721)) + (PORT datac (509:509:509) (465:465:465)) + (PORT datad (518:518:518) (466:466:466)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~22) + (DELAY + (ABSOLUTE + (PORT datac (847:847:847) (725:725:725)) + (PORT datad (477:477:477) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~23) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (507:507:507)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (511:511:511) (467:467:467)) + (PORT datad (517:517:517) (452:452:452)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (503:503:503)) + (PORT datad (477:477:477) (406:406:406)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (765:765:765)) + (PORT datab (267:267:267) (274:274:274)) + (PORT datac (509:509:509) (465:465:465)) + (PORT datad (519:519:519) (466:466:466)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~25) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (296:296:296)) + (PORT datab (819:819:819) (640:640:640)) + (PORT datac (226:226:226) (242:242:242)) + (PORT datad (232:232:232) (243:243:243)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (362:362:362) (424:424:424)) + (PORT datac (340:340:340) (426:426:426)) + (PORT datad (551:551:551) (544:544:544)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~5) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (764:764:764)) + (PORT datab (790:790:790) (674:674:674)) + (PORT datac (972:972:972) (762:762:762)) + (PORT datad (784:784:784) (717:717:717)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (322:322:322) (377:377:377)) + (PORT datac (991:991:991) (941:941:941)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (936:936:936) (843:843:843)) + (PORT datad (891:891:891) (820:820:820)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~4) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (383:383:383)) + (PORT datab (1000:1000:1000) (948:948:948)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1134:1134:1134) (980:980:980)) + (PORT datab (873:873:873) (766:766:766)) + (PORT datac (1188:1188:1188) (1086:1086:1086)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (377:377:377) (444:444:444)) + (PORT datac (332:332:332) (417:417:417)) + (PORT datad (556:556:556) (550:550:550)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~6) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (594:594:594)) + (PORT datab (350:350:350) (408:408:408)) + (PORT datac (1213:1213:1213) (1094:1094:1094)) + (PORT datad (249:249:249) (257:257:257)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~8) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (902:902:902)) + (PORT datab (1218:1218:1218) (1081:1081:1081)) + (PORT datac (548:548:548) (541:541:541)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~37) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (744:744:744)) + (PORT datab (559:559:559) (500:500:500)) + (PORT datac (852:852:852) (730:730:730)) + (PORT datad (233:233:233) (244:244:244)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2044:2044:2044) (2012:2012:2012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (438:438:438) (363:363:363)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT dataa (1096:1096:1096) (918:918:918)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (727:727:727)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (465:465:465) (385:385:385)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datab (1152:1152:1152) (942:942:942)) + (IOPATH datab combout (437:437:437) (425:425:425)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (235:235:235)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_clk_p\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2488:2488:2488) (2436:2436:2436)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_clk_n\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2488:2488:2488) (2436:2436:2436)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_p\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2498:2498:2498) (2446:2446:2446)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_p\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2498:2498:2498) (2446:2446:2446)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_p\[2\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2498:2498:2498) (2446:2446:2446)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_n\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2488:2488:2488) (2436:2436:2436)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_n\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2508:2508:2508) (2456:2456:2456)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_n\[2\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2498:2498:2498) (2446:2446:2446)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\~0) + (DELAY + (ABSOLUTE + (PORT datab (422:422:422) (506:506:506)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|Add0\~1) + (DELAY + (ABSOLUTE + (PORT datad (285:285:285) (344:344:344)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (994:994:994) (1127:1127:1127)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (321:321:321) (375:375:375)) + (PORT datad (285:285:285) (344:344:344)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT sclr (994:994:994) (1127:1127:1127)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (382:382:382)) + (PORT datad (380:380:380) (465:465:465)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (378:378:378) (463:463:463)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (423:423:423) (508:508:508)) + (PORT datac (280:280:280) (343:343:343)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT datac (284:284:284) (350:350:350)) + (PORT datad (381:381:381) (466:466:466)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT datab (323:323:323) (378:378:378)) + (PORT datad (379:379:379) (463:463:463)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (320:320:320) (374:374:374)) + (PORT datad (379:379:379) (464:464:464)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (788:788:788) (813:813:813)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2044:2044:2044) (2012:2012:2012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1603:1603:1603) (1574:1574:1574)) + (PORT D (1225:1225:1225) (1201:1201:1201)) + (IOPATH (negedge ENA) Q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (513:513:513)) + (HOLD D (negedge ENA) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1603:1603:1603) (1575:1575:1575)) + (PORT d (1255:1255:1255) (1235:1235:1235)) + (IOPATH (posedge clk) q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1761:1761:1761) (1746:1746:1746)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (491:491:491) (503:503:503)) + ) + ) + (DELAY + (PATHPULSE datain dataout (491:491:491)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1606:1606:1606) (1577:1577:1577)) + (PORT D (808:808:808) (887:887:887)) + (IOPATH (negedge ENA) Q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (513:513:513)) + (HOLD D (negedge ENA) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1578:1578:1578)) + (PORT d (884:884:884) (970:970:970)) + (IOPATH (posedge clk) q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1764:1764:1764) (1749:1749:1749)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (491:491:491) (503:503:503)) + ) + ) + (DELAY + (PATHPULSE datain dataout (491:491:491)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (404:404:404)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (1311:1311:1311) (1435:1435:1435)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4641:4641:4641) (4614:4614:4614)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (3981:3981:3981) (3957:3957:3957)) + (PORT datab (318:318:318) (372:372:372)) + (PORT datad (652:652:652) (760:760:760)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1744:1744:1744) (1558:1558:1558)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (411:411:411)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (406:406:406)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (436:436:436)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (413:413:413)) + (PORT datab (347:347:347) (405:405:405)) + (PORT datac (304:304:304) (370:370:370)) + (PORT datad (306:306:306) (366:366:366)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (365:365:365) (420:420:420)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datab (373:373:373) (431:431:431)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~20) + (DELAY + (ABSOLUTE + (PORT datab (369:369:369) (427:427:427)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~22) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (435:435:435)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (438:438:438)) + (PORT datab (372:372:372) (429:429:429)) + (PORT datac (330:330:330) (398:398:398)) + (PORT datad (327:327:327) (386:386:386)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (904:904:904)) + (PORT datab (905:905:905) (788:788:788)) + (PORT datac (900:900:900) (772:772:772)) + (PORT datad (1117:1117:1117) (923:923:923)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (655:655:655) (609:609:609)) + (PORT datab (1236:1236:1236) (1078:1078:1078)) + (PORT datac (567:567:567) (540:540:540)) + (PORT datad (561:561:561) (539:539:539)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~2) + (DELAY + (ABSOLUTE + (PORT dataa (303:303:303) (320:320:320)) + (PORT datab (270:270:270) (277:277:277)) + (PORT datac (257:257:257) (276:276:276)) + (PORT datad (752:752:752) (608:608:608)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~1) + (DELAY + (ABSOLUTE + (PORT dataa (303:303:303) (320:320:320)) + (PORT datab (300:300:300) (310:310:310)) + (PORT datac (229:229:229) (244:244:244)) + (PORT datad (752:752:752) (608:608:608)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT datab (1233:1233:1233) (1075:1075:1075)) + (PORT datac (566:566:566) (539:539:539)) + (PORT datad (561:561:561) (539:539:539)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (582:582:582)) + (PORT datab (651:651:651) (615:615:615)) + (PORT datac (599:599:599) (581:581:581)) + (PORT datad (740:740:740) (597:597:597)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (556:556:556)) + (PORT datab (858:858:858) (750:750:750)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (556:556:556)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (531:531:531)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~7) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (581:581:581)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~9) + (DELAY + (ABSOLUTE + (PORT datab (1229:1229:1229) (1070:1070:1070)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT datab (622:622:622) (579:579:579)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT datab (564:564:564) (543:543:543)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (602:602:602)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (632:632:632) (586:586:586)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT datab (628:628:628) (578:578:578)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (779:779:779)) + (PORT datab (561:561:561) (502:502:502)) + (PORT datac (511:511:511) (467:467:467)) + (PORT datad (517:517:517) (464:464:464)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~5) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (584:584:584)) + (PORT datac (600:600:600) (583:583:583)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT datab (948:948:948) (802:802:802)) + (PORT datac (859:859:859) (751:751:751)) + (PORT datad (1120:1120:1120) (926:926:926)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (484:484:484) (417:417:417)) + (PORT datab (368:368:368) (394:394:394)) + (PORT datad (1173:1173:1173) (1001:1001:1001)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (1427:1427:1427) (1174:1174:1174)) + (PORT datad (556:556:556) (495:495:495)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (746:746:746) (616:616:616)) + (PORT datab (367:367:367) (393:393:393)) + (PORT datad (1174:1174:1174) (1001:1001:1001)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (409:409:409)) + (PORT datab (345:345:345) (403:403:403)) + (PORT datac (544:544:544) (511:511:511)) + (PORT datad (304:304:304) (362:362:362)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (748:748:748) (635:635:635)) + (PORT datab (364:364:364) (390:390:390)) + (PORT datad (1179:1179:1179) (1007:1007:1007)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (437:437:437)) + (PORT datab (362:362:362) (388:388:388)) + (PORT datad (1182:1182:1182) (1011:1011:1011)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (668:668:668)) + (PORT datab (297:297:297) (307:307:307)) + (PORT datac (307:307:307) (374:374:374)) + (PORT datad (307:307:307) (366:366:366)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (392:392:392)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (617:617:617) (537:537:537)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datad (1393:1393:1393) (1142:1142:1142)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (471:471:471) (407:407:407)) + (PORT datab (362:362:362) (388:388:388)) + (PORT datad (1181:1181:1181) (1010:1010:1010)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (427:427:427)) + (PORT datab (371:371:371) (429:429:429)) + (PORT datac (558:558:558) (529:529:529)) + (PORT datad (310:310:310) (370:370:370)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[11\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (277:277:277) (286:286:286)) + (PORT datac (228:228:228) (243:243:243)) + (PORT datad (1180:1180:1180) (1008:1008:1008)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (652:652:652)) + (PORT datab (367:367:367) (393:393:393)) + (PORT datad (1175:1175:1175) (1002:1002:1002)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (412:412:412)) + (PORT datab (368:368:368) (394:394:394)) + (PORT datad (1172:1172:1172) (1000:1000:1000)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (610:610:610) (564:564:564)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (519:519:519) (463:463:463)) + (PORT datab (477:477:477) (402:402:402)) + (PORT datad (1177:1177:1177) (1005:1005:1005)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~22) + (DELAY + (ABSOLUTE + (PORT datad (298:298:298) (354:354:354)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (545:545:545)) + (PORT datab (267:267:267) (274:274:274)) + (PORT datad (1386:1386:1386) (1136:1136:1136)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (775:775:775)) + (PORT datab (914:914:914) (801:801:801)) + (PORT datac (582:582:582) (557:557:557)) + (PORT datad (535:535:535) (523:523:523)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~4) + (DELAY + (ABSOLUTE + (PORT dataa (769:769:769) (645:645:645)) + (PORT datac (813:813:813) (740:740:740)) + (PORT datad (235:235:235) (246:246:246)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~6) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (494:494:494)) + (PORT datab (649:649:649) (614:614:614)) + (PORT datac (598:598:598) (580:580:580)) + (PORT datad (739:739:739) (596:596:596)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~7) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (640:640:640)) + (PORT datab (267:267:267) (275:275:275)) + (PORT datac (246:246:246) (261:261:261)) + (PORT datad (229:229:229) (237:237:237)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (508:508:508)) + (PORT datab (757:757:757) (638:638:638)) + (PORT datac (510:510:510) (466:466:466)) + (PORT datad (518:518:518) (453:453:453)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (508:508:508)) + (PORT datab (560:560:560) (501:501:501)) + (PORT datac (856:856:856) (734:734:734)) + (PORT datad (234:234:234) (244:244:244)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~13) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (433:433:433)) + (PORT datab (496:496:496) (435:435:435)) + (PORT datac (1492:1492:1492) (1258:1258:1258)) + (PORT datad (866:866:866) (737:737:737)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~17) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (510:510:510)) + (PORT datac (509:509:509) (465:465:465)) + (PORT datad (520:520:520) (455:455:455)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~34) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (745:745:745)) + (PORT datab (560:560:560) (501:501:501)) + (PORT datac (854:854:854) (732:732:732)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (508:508:508)) + (PORT datad (519:519:519) (453:453:453)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (770:770:770)) + (PORT datab (558:558:558) (498:498:498)) + (PORT datac (509:509:509) (466:466:466)) + (PORT datad (226:226:226) (234:234:234)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (778:778:778)) + (PORT datac (1361:1361:1361) (1088:1088:1088)) + (PORT datad (822:822:822) (703:703:703)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~18) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (751:751:751)) + (PORT datab (275:275:275) (284:284:284)) + (PORT datac (816:816:816) (698:698:698)) + (PORT datad (245:245:245) (259:259:259)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~20) + (DELAY + (ABSOLUTE + (PORT datad (530:530:530) (508:508:508)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (807:807:807)) + (PORT datab (892:892:892) (766:766:766)) + (PORT datac (1152:1152:1152) (975:975:975)) + (PORT datad (906:906:906) (792:792:792)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~3) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (770:770:770)) + (PORT datab (898:898:898) (771:771:771)) + (PORT datac (1469:1469:1469) (1249:1249:1249)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (805:805:805)) + (PORT datac (840:840:840) (733:733:733)) + (PORT datad (902:902:902) (788:788:788)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~19) + (DELAY + (ABSOLUTE + (PORT dataa (861:861:861) (751:751:751)) + (PORT datab (549:549:549) (456:456:456)) + (PORT datac (708:708:708) (560:560:560)) + (PORT datad (864:864:864) (735:735:735)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~20) + (DELAY + (ABSOLUTE + (PORT datab (283:283:283) (295:295:295)) + (PORT datac (816:816:816) (699:699:699)) + (PORT datad (234:234:234) (245:245:245)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (937:937:937)) + (PORT datab (855:855:855) (725:725:725)) + (PORT datac (285:285:285) (351:351:351)) + (PORT datad (286:286:286) (344:344:344)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_in_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[8\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (1231:1231:1231) (1086:1086:1086)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT asdata (1615:1615:1615) (1453:1453:1453)) + (PORT clrn (1685:1685:1685) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (570:570:570)) + (PORT datab (349:349:349) (407:407:407)) + (PORT datac (307:307:307) (373:373:373)) + (PORT datad (318:318:318) (383:383:383)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (280:280:280)) + (PORT datab (299:299:299) (309:309:309)) + (PORT datac (227:227:227) (242:242:242)) + (PORT datad (302:302:302) (361:361:361)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1244:1244:1244) (1043:1043:1043)) + (PORT datab (1460:1460:1460) (1204:1204:1204)) + (PORT datac (287:287:287) (353:353:353)) + (PORT datad (791:791:791) (684:684:684)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_in_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1245:1245:1245) (1044:1044:1044)) + (PORT datab (854:854:854) (724:724:724)) + (PORT datac (1416:1416:1416) (1170:1170:1170)) + (PORT datad (285:285:285) (343:343:343)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_in_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add14\~0) + (DELAY + (ABSOLUTE + (PORT datab (1320:1320:1320) (1144:1144:1144)) + (PORT datac (1136:1136:1136) (1014:1014:1014)) + (PORT datad (1230:1230:1230) (1084:1084:1084)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (228:228:228) (235:235:235)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (545:545:545)) + (PORT datab (928:928:928) (806:806:806)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~2) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (424:424:424)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~6) + (DELAY + (ABSOLUTE + (PORT datab (364:364:364) (419:419:419)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (527:527:527)) + (PORT datab (924:924:924) (845:845:845)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~2) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (578:578:578)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~6) + (DELAY + (ABSOLUTE + (PORT datad (541:541:541) (518:518:518)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (494:494:494)) + (PORT datab (493:493:493) (431:431:431)) + (PORT datac (225:225:225) (241:241:241)) + (PORT datad (446:446:446) (386:386:386)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (732:732:732)) + (PORT datab (920:920:920) (840:840:840)) + (PORT datad (790:790:790) (688:688:688)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~9) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (472:472:472)) + (PORT datab (270:270:270) (277:277:277)) + (PORT datac (814:814:814) (720:720:720)) + (PORT datad (790:790:790) (688:688:688)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~10) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (723:723:723)) + (PORT datab (477:477:477) (411:411:411)) + (PORT datac (807:807:807) (667:667:667)) + (PORT datad (479:479:479) (406:406:406)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add12\~0) + (DELAY + (ABSOLUTE + (PORT datab (1319:1319:1319) (1143:1143:1143)) + (PORT datac (1138:1138:1138) (1016:1016:1016)) + (PORT datad (1233:1233:1233) (1088:1088:1088)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add14\~1) + (DELAY + (ABSOLUTE + (PORT datab (1320:1320:1320) (1145:1145:1145)) + (PORT datac (1137:1137:1137) (1015:1015:1015)) + (PORT datad (1231:1231:1231) (1085:1085:1085)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~13) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (472:472:472)) + (PORT datab (271:271:271) (278:278:278)) + (PORT datac (862:862:862) (755:755:755)) + (PORT datad (790:790:790) (688:688:688)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~14) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (705:705:705)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (764:764:764) (687:687:687)) + (PORT datad (445:445:445) (384:384:384)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT asdata (1516:1516:1516) (1390:1390:1390)) + (PORT clrn (1686:1686:1686) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~15) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (495:495:495)) + (PORT datab (528:528:528) (432:432:432)) + (PORT datac (474:474:474) (393:393:393)) + (PORT datad (868:868:868) (766:766:766)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (582:582:582)) + (PORT datab (636:636:636) (598:598:598)) + (PORT datac (514:514:514) (502:502:502)) + (PORT datad (504:504:504) (488:488:488)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datac (842:842:842) (750:750:750)) + (PORT datad (471:471:471) (396:396:396)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (436:436:436)) + (PORT datab (472:472:472) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (645:645:645)) + (PORT datab (537:537:537) (447:447:447)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1239:1239:1239) (1038:1038:1038)) + (PORT datac (1412:1412:1412) (1167:1167:1167)) + (PORT datad (792:792:792) (684:684:684)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|de_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|de_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (279:279:279) (334:334:334)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|de_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (PORT sclr (1345:1345:1345) (1474:1474:1474)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_2) + (DELAY + (ABSOLUTE + (PORT dataa (277:277:277) (291:291:291)) + (PORT datab (880:880:880) (779:779:779)) + (PORT datac (604:604:604) (587:587:587)) + (PORT datad (473:473:473) (398:398:398)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (282:282:282)) + (PORT datab (925:925:925) (845:845:845)) + (PORT datac (768:768:768) (709:709:709)) + (PORT datad (790:790:790) (688:688:688)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (416:416:416)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (PORT sclr (1345:1345:1345) (1474:1474:1474)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (581:581:581)) + (PORT datab (637:637:637) (599:599:599)) + (PORT datac (514:514:514) (502:502:502)) + (PORT datad (504:504:504) (488:488:488)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (440:440:440)) + (PORT datab (881:881:881) (779:779:779)) + (PORT datac (597:597:597) (575:575:575)) + (PORT datad (466:466:466) (389:389:389)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (788:788:788) (659:659:659)) + (PORT datab (340:340:340) (395:395:395)) + (PORT datad (779:779:779) (640:640:640)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (727:727:727) (591:591:591)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (780:780:780)) + (PORT datab (630:630:630) (579:579:579)) + (PORT datac (581:581:581) (550:550:550)) + (PORT datad (531:531:531) (509:509:509)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (611:611:611)) + (PORT datab (626:626:626) (583:583:583)) + (PORT datac (1194:1194:1194) (1045:1045:1045)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c0_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c0_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT asdata (701:701:701) (762:762:762)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1610:1610:1610) (1507:1507:1507)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (PORT sload (1671:1671:1671) (1859:1859:1859)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (1319:1319:1319) (1144:1144:1144)) + (PORT datad (1232:1232:1232) (1087:1087:1087)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1685:1685:1685) (1640:1640:1640)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~4) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (734:734:734)) + (PORT datab (923:923:923) (843:843:843)) + (PORT datac (793:793:793) (692:692:692)) + (PORT datad (790:790:790) (689:689:689)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (668:668:668) (543:543:543)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1613:1613:1613) (1510:1510:1510)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (PORT sload (1671:1671:1671) (1859:1859:1859)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (429:429:429)) + (PORT datab (374:374:374) (433:433:433)) + (PORT datac (525:525:525) (509:509:509)) + (PORT datad (236:236:236) (247:247:247)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c1_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c1_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1353:1353:1353) (1160:1160:1160)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c1_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~7) + (DELAY + (ABSOLUTE + (PORT dataa (814:814:814) (666:666:666)) + (PORT datab (1236:1236:1236) (1115:1115:1115)) + (PORT datac (1080:1080:1080) (944:944:944)) + (PORT datad (880:880:880) (802:802:802)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (319:319:319) (374:374:374)) + (PORT datac (1021:1021:1021) (987:987:987)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (330:330:330) (388:388:388)) + (PORT datac (1022:1022:1022) (987:987:987)) + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT datab (331:331:331) (389:389:389)) + (PORT datac (1021:1021:1021) (987:987:987)) + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (382:382:382)) + (PORT datac (1021:1021:1021) (987:987:987)) + (PORT datad (277:277:277) (332:332:332)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (322:322:322) (377:377:377)) + (PORT datac (1022:1022:1022) (988:988:988)) + (PORT datad (280:280:280) (335:335:335)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1664:1664:1664)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1265:1265:1265) (1211:1211:1211)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (PORT sload (1460:1460:1460) (1597:1597:1597)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~3) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (663:663:663)) + (PORT datab (1239:1239:1239) (1118:1118:1118)) + (PORT datac (1077:1077:1077) (940:940:940)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (382:382:382)) + (PORT datab (321:321:321) (375:375:375)) + (PORT datac (1022:1022:1022) (987:987:987)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (423:423:423) (507:507:507)) + (PORT datac (884:884:884) (808:808:808)) + (PORT datad (865:865:865) (788:788:788)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1645:1645:1645) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1606:1606:1606) (1577:1577:1577)) + (PORT D (1189:1189:1189) (1160:1160:1160)) + (IOPATH (negedge ENA) Q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (513:513:513)) + (HOLD D (negedge ENA) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1578:1578:1578)) + (PORT d (899:899:899) (940:940:940)) + (IOPATH (posedge clk) q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1764:1764:1764) (1749:1749:1749)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (491:491:491) (503:503:503)) + ) + ) + (DELAY + (PATHPULSE datain dataout (491:491:491)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (970:970:970) (838:838:838)) + (PORT datab (891:891:891) (765:765:765)) + (PORT datac (1154:1154:1154) (977:977:977)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[9\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (914:914:914) (780:780:780)) + (PORT datac (1469:1469:1469) (1248:1248:1248)) + (PORT datad (256:256:256) (267:267:267)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~35) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (297:297:297)) + (PORT datab (561:561:561) (501:501:501)) + (PORT datac (856:856:856) (735:735:735)) + (PORT datad (234:234:234) (244:244:244)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~36) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (310:310:310)) + (PORT datab (900:900:900) (773:773:773)) + (PORT datac (1152:1152:1152) (975:975:975)) + (PORT datad (241:241:241) (255:255:255)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~21) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (432:432:432)) + (PORT datab (495:495:495) (434:434:434)) + (PORT datac (1491:1491:1491) (1257:1257:1257)) + (PORT datad (865:865:865) (737:737:737)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~26) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (758:758:758)) + (PORT datab (822:822:822) (717:717:717)) + (PORT datac (231:231:231) (249:249:249)) + (PORT datad (451:451:451) (393:393:393)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_x\[11\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1155:1155:1155) (960:960:960)) + (PORT datad (836:836:836) (721:721:721)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~27) + (DELAY + (ABSOLUTE + (PORT dataa (287:287:287) (307:307:307)) + (PORT datab (284:284:284) (296:296:296)) + (PORT datac (226:226:226) (241:241:241)) + (PORT datad (822:822:822) (707:707:707)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[10\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (681:681:681)) + (PORT datab (1404:1404:1404) (1153:1153:1153)) + (PORT datac (547:547:547) (523:523:523)) + (PORT datad (1627:1627:1627) (1298:1298:1298)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~29) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (804:804:804)) + (PORT datab (890:890:890) (765:765:765)) + (PORT datac (1159:1159:1159) (982:982:982)) + (PORT datad (899:899:899) (785:785:785)) + (IOPATH dataa combout (420:420:420) (392:392:392)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1198:1198:1198) (1016:1016:1016)) + (PORT datab (899:899:899) (772:772:772)) + (PORT datac (1469:1469:1469) (1249:1249:1249)) + (PORT datad (853:853:853) (740:740:740)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~31) + (DELAY + (ABSOLUTE + (PORT datab (266:266:266) (272:272:272)) + (PORT datac (227:227:227) (242:242:242)) + (PORT datad (250:250:250) (258:258:258)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[6\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (684:684:684)) + (PORT datab (1381:1381:1381) (1133:1133:1133)) + (PORT datac (1359:1359:1359) (1117:1117:1117)) + (PORT datad (536:536:536) (511:511:511)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (542:542:542)) + (PORT datab (741:741:741) (608:608:608)) + (PORT datac (549:549:549) (525:525:525)) + (PORT datad (540:540:540) (515:515:515)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (571:571:571)) + (PORT datab (378:378:378) (446:446:446)) + (PORT datac (339:339:339) (424:424:424)) + (PORT datad (552:552:552) (545:545:545)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n0\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~28) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (754:754:754)) + (PORT datab (821:821:821) (716:716:716)) + (PORT datac (236:236:236) (254:254:254)) + (PORT datad (448:448:448) (390:390:390)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (822:822:822) (683:683:683)) + (PORT datab (1382:1382:1382) (1133:1133:1133)) + (PORT datac (1359:1359:1359) (1118:1118:1118)) + (PORT datad (505:505:505) (493:493:493)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (428:428:428)) + (PORT datab (380:380:380) (455:455:455)) + (PORT datac (316:316:316) (386:386:386)) + (PORT datad (524:524:524) (501:501:501)) + (IOPATH dataa combout (394:394:394) (419:419:419)) + (IOPATH datab combout (400:400:400) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add13\~1) + (DELAY + (ABSOLUTE + (PORT datab (378:378:378) (446:446:446)) + (PORT datac (340:340:340) (425:425:425)) + (PORT datad (551:551:551) (544:544:544)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1537:1537:1537) (1369:1369:1369)) + (PORT datab (935:935:935) (821:821:821)) + (PORT datac (790:790:790) (713:713:713)) + (PORT datad (828:828:828) (735:735:735)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1539:1539:1539) (1372:1372:1372)) + (PORT datab (934:934:934) (820:820:820)) + (PORT datac (792:792:792) (715:715:715)) + (PORT datad (827:827:827) (733:733:733)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add14\~2) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (568:568:568)) + (PORT datab (380:380:380) (454:454:454)) + (PORT datac (334:334:334) (410:410:410)) + (PORT datad (556:556:556) (549:549:549)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n0\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1638:1638:1638) (1659:1659:1659)) + (PORT asdata (2045:2045:2045) (1818:1818:1818)) + (PORT clrn (1679:1679:1679) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (784:784:784)) + (PORT datab (553:553:553) (528:528:528)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1492:1492:1492) (1334:1334:1334)) + (PORT datab (894:894:894) (800:800:800)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (570:570:570)) + (PORT datab (383:383:383) (457:457:457)) + (PORT datac (334:334:334) (410:410:410)) + (PORT datad (554:554:554) (547:547:547)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n0\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1099:1099:1099) (950:950:950)) + (PORT datab (1810:1810:1810) (1571:1571:1571)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~9) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (757:757:757)) + (PORT datab (266:266:266) (273:273:273)) + (PORT datac (442:442:442) (391:391:391)) + (PORT datad (1113:1113:1113) (914:914:914)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~10) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (282:282:282)) + (PORT datab (538:538:538) (446:446:446)) + (PORT datac (228:228:228) (244:244:244)) + (PORT datad (1116:1116:1116) (917:917:917)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[8\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (316:316:316) (387:387:387)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~15) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (281:281:281)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (809:809:809) (681:681:681)) + (PORT datad (891:891:891) (781:781:781)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (663:663:663)) + (PORT datab (1504:1504:1504) (1242:1242:1242)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (PORT sclr (1329:1329:1329) (1447:1447:1447)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (400:400:400)) + (PORT datab (840:840:840) (726:726:726)) + (PORT datac (296:296:296) (360:360:360)) + (PORT datad (299:299:299) (354:354:354)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datab (279:279:279) (289:289:289)) + (PORT datad (308:308:308) (367:367:367)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (282:282:282)) + (PORT datab (269:269:269) (276:276:276)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (659:659:659)) + (PORT datab (469:469:469) (404:404:404)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (433:433:433)) + (PORT datab (736:736:736) (602:602:602)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (PORT sclr (1329:1329:1329) (1447:1447:1447)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (759:759:759)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (224:224:224) (239:239:239)) + (PORT datad (1114:1114:1114) (915:915:915)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (282:282:282)) + (PORT datab (267:267:267) (274:274:274)) + (PORT datac (693:693:693) (567:567:567)) + (PORT datad (809:809:809) (688:688:688)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (281:281:281)) + (PORT datab (792:792:792) (640:640:640)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (PORT sclr (1329:1329:1329) (1447:1447:1447)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1535:1535:1535) (1367:1367:1367)) + (PORT datab (935:935:935) (821:821:821)) + (PORT datac (789:789:789) (712:712:712)) + (PORT datad (829:829:829) (736:736:736)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_2) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (785:785:785)) + (PORT datab (346:346:346) (404:404:404)) + (PORT datac (783:783:783) (626:626:626)) + (PORT datad (238:238:238) (250:250:250)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (772:772:772)) + (PORT datab (793:793:793) (677:677:677)) + (PORT datad (786:786:786) (719:719:719)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~11) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (1024:1024:1024) (835:835:835)) + (PORT datad (514:514:514) (451:451:451)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~12) + (DELAY + (ABSOLUTE + (PORT dataa (856:856:856) (705:705:705)) + (PORT datab (936:936:936) (822:822:822)) + (PORT datac (794:794:794) (717:717:717)) + (PORT datad (225:225:225) (232:232:232)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (PORT sclr (1329:1329:1329) (1447:1447:1447)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~6) + (DELAY + (ABSOLUTE + (PORT datad (567:567:567) (552:552:552)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (600:600:600)) + (PORT datab (785:785:785) (631:631:631)) + (PORT datac (756:756:756) (628:628:628)) + (PORT datad (756:756:756) (643:643:643)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (788:788:788) (658:658:658)) + (PORT datad (444:444:444) (385:385:385)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (PORT sclr (1329:1329:1329) (1447:1447:1447)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (916:916:916) (794:794:794)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (227:227:227) (242:242:242)) + (PORT datad (566:566:566) (551:551:551)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT asdata (740:740:740) (810:810:810)) + (PORT clrn (1682:1682:1682) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (429:429:429)) + (PORT datab (810:810:810) (665:665:665)) + (PORT datad (751:751:751) (637:637:637)) + (IOPATH dataa combout (377:377:377) (380:380:380)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (767:767:767) (617:617:617)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1638:1638:1638) (1516:1516:1516)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (PORT sload (1285:1285:1285) (1355:1355:1355)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~3) + (DELAY + (ABSOLUTE + (PORT dataa (777:777:777) (690:690:690)) + (PORT datab (792:792:792) (675:675:675)) + (PORT datac (971:971:971) (761:761:761)) + (PORT datad (786:786:786) (719:719:719)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (234:234:234)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1641:1641:1641) (1520:1520:1520)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (PORT sload (1285:1285:1285) (1355:1355:1355)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (381:381:381)) + (PORT datab (320:320:320) (374:374:374)) + (PORT datac (991:991:991) (941:941:941)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (384:384:384)) + (PORT datac (989:989:989) (938:938:938)) + (PORT datad (280:280:280) (335:335:335)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (331:331:331) (389:389:389)) + (PORT datac (991:991:991) (941:941:941)) + (PORT datad (280:280:280) (335:335:335)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~7) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (882:882:882)) + (PORT datac (1399:1399:1399) (1220:1220:1220)) + (PORT datad (1212:1212:1212) (1073:1073:1073)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1643:1643:1643)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (320:320:320) (374:374:374)) + (PORT datad (996:996:996) (951:951:951)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~3) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (397:397:397)) + (PORT datab (1038:1038:1038) (991:991:991)) + (PORT datac (277:277:277) (340:340:340)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (383:383:383)) + (PORT datab (1038:1038:1038) (991:991:991)) + (PORT datac (277:277:277) (340:340:340)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (396:396:396)) + (PORT datab (1039:1039:1039) (992:992:992)) + (PORT datad (278:278:278) (333:333:333)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT dataa (971:971:971) (868:868:868)) + (PORT datab (1039:1039:1039) (992:992:992)) + (PORT datac (278:278:278) (341:341:341)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1609:1609:1609) (1580:1580:1580)) + (PORT D (819:819:819) (853:853:853)) + (IOPATH (negedge ENA) Q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (513:513:513)) + (HOLD D (negedge ENA) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1581:1581:1581)) + (PORT d (1240:1240:1240) (1235:1235:1235)) + (IOPATH (posedge clk) q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1767:1767:1767) (1752:1752:1752)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (491:491:491) (503:503:503)) + ) + ) + (DELAY + (PATHPULSE datain dataout (491:491:491)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~33) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (739:739:739)) + (PORT datab (283:283:283) (296:296:296)) + (PORT datad (234:234:234) (245:245:245)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[13\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1242:1242:1242) (1041:1041:1041)) + (PORT datab (1459:1459:1459) (1203:1203:1203)) + (PORT datac (287:287:287) (353:353:353)) + (PORT datad (791:791:791) (684:684:684)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_in_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~32) + (DELAY + (ABSOLUTE + (PORT dataa (852:852:852) (738:738:738)) + (PORT datab (274:274:274) (284:284:284)) + (PORT datac (835:835:835) (716:716:716)) + (PORT datad (821:821:821) (708:708:708)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1141:1141:1141) (936:936:936)) + (PORT datab (854:854:854) (724:724:724)) + (PORT datac (287:287:287) (353:353:353)) + (PORT datad (512:512:512) (499:499:499)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_in_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[12\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1241:1241:1241) (1040:1040:1040)) + (PORT datab (1458:1458:1458) (1203:1203:1203)) + (PORT datac (301:301:301) (365:365:365)) + (PORT datad (792:792:792) (684:684:684)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_in_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add12\~0) + (DELAY + (ABSOLUTE + (PORT datab (965:965:965) (885:885:885)) + (PORT datac (989:989:989) (936:936:936)) + (PORT datad (924:924:924) (869:869:869)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add14\~0) + (DELAY + (ABSOLUTE + (PORT datab (965:965:965) (885:885:885)) + (PORT datac (990:990:990) (937:937:937)) + (PORT datad (924:924:924) (869:869:869)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add12\~1) + (DELAY + (ABSOLUTE + (PORT datac (983:983:983) (928:928:928)) + (PORT datad (921:921:921) (866:866:866)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (811:811:811)) + (PORT datab (889:889:889) (790:790:790)) + (PORT datac (880:880:880) (781:781:781)) + (PORT datad (799:799:799) (719:719:719)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[8\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (989:989:989) (936:936:936)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (813:813:813)) + (PORT datab (896:896:896) (797:797:797)) + (PORT datac (888:888:888) (790:790:790)) + (PORT datad (796:796:796) (715:715:715)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (801:801:801)) + (PORT datab (838:838:838) (752:752:752)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (280:280:280)) + (PORT datab (270:270:270) (277:277:277)) + (PORT datac (820:820:820) (690:690:690)) + (PORT datad (762:762:762) (621:621:621)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (873:873:873) (767:767:767)) + (PORT datab (844:844:844) (759:759:759)) + (PORT datac (486:486:486) (413:413:413)) + (PORT datad (823:823:823) (682:682:682)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (432:432:432)) + (PORT datab (354:354:354) (415:415:415)) + (PORT datac (303:303:303) (370:370:370)) + (PORT datad (306:306:306) (366:366:366)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datac (829:829:829) (737:737:737)) + (PORT datad (720:720:720) (579:579:579)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1082:1082:1082) (854:854:854)) + (PORT datab (1043:1043:1043) (813:813:813)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (285:285:285)) + (PORT datab (268:268:268) (275:275:275)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (PORT sclr (1634:1634:1634) (1813:1813:1813)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (749:749:749)) + (PORT datab (357:357:357) (419:419:419)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~15) + (DELAY + (ABSOLUTE + (PORT dataa (842:842:842) (663:663:663)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (802:802:802) (726:726:726)) + (PORT datad (821:821:821) (681:681:681)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (474:474:474) (413:413:413)) + (PORT datab (537:537:537) (446:446:446)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (746:746:746) (609:609:609)) + (PORT datab (267:267:267) (274:274:274)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (419:419:419)) + (PORT datab (267:267:267) (274:274:274)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (PORT sclr (1634:1634:1634) (1813:1813:1813)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (233:233:233)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_2) + (DELAY + (ABSOLUTE + (PORT dataa (789:789:789) (632:632:632)) + (PORT datab (827:827:827) (659:659:659)) + (PORT datac (826:826:826) (735:735:735)) + (PORT datad (535:535:535) (514:514:514)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (310:310:310) (330:330:330)) + (PORT datab (586:586:586) (570:570:570)) + (PORT datad (263:263:263) (277:277:277)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~14) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (281:281:281)) + (PORT datab (804:804:804) (683:683:683)) + (PORT datac (803:803:803) (709:709:709)) + (PORT datad (434:434:434) (371:371:371)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (PORT sclr (1634:1634:1634) (1813:1813:1813)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (755:755:755)) + (PORT datab (934:934:934) (816:816:816)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~2) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (753:753:753)) + (PORT datab (938:938:938) (821:821:821)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (718:718:718)) + (PORT datab (267:267:267) (273:273:273)) + (PORT datac (227:227:227) (242:242:242)) + (PORT datad (786:786:786) (669:669:669)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~8) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (668:668:668)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (682:682:682) (564:564:564)) + (PORT datad (822:822:822) (681:681:681)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (PORT sclr (1634:1634:1634) (1813:1813:1813)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT asdata (1586:1586:1586) (1440:1440:1440)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~8) + (DELAY + (ABSOLUTE + (PORT datad (834:834:834) (739:739:739)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (887:887:887) (740:740:740)) + (PORT datab (480:480:480) (418:418:418)) + (PORT datac (734:734:734) (596:596:596)) + (PORT datad (765:765:765) (648:648:648)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~1) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (646:646:646)) + (PORT datab (266:266:266) (272:272:272)) + (PORT datac (696:696:696) (569:569:569)) + (PORT datad (765:765:765) (647:647:647)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (425:425:425)) + (PORT datad (442:442:442) (383:383:383)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (PORT sclr (1634:1634:1634) (1813:1813:1813)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (787:787:787) (640:640:640)) + (PORT datab (768:768:768) (628:628:628)) + (PORT datac (836:836:836) (735:735:735)) + (PORT datad (535:535:535) (514:514:514)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT asdata (1409:1409:1409) (1352:1352:1352)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (672:672:672)) + (PORT datab (867:867:867) (694:694:694)) + (PORT datad (319:319:319) (385:385:385)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (833:833:833) (702:702:702)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1826:1826:1826) (1645:1645:1645)) + (PORT clrn (1689:1689:1689) (1643:1643:1643)) + (PORT sload (1571:1571:1571) (1688:1688:1688)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (981:981:981) (926:926:926)) + (PORT datad (920:920:920) (865:865:865)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~4) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (431:431:431)) + (PORT datab (317:317:317) (371:371:371)) + (PORT datac (758:758:758) (632:632:632)) + (PORT datad (806:806:806) (652:652:652)) + (IOPATH dataa combout (394:394:394) (419:419:419)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (759:759:759) (600:600:600)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1825:1825:1825) (1644:1644:1644)) + (PORT clrn (1689:1689:1689) (1643:1643:1643)) + (PORT sload (1571:1571:1571) (1688:1688:1688)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~7) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (598:598:598)) + (PORT datab (352:352:352) (410:410:410)) + (PORT datac (1215:1215:1215) (1096:1096:1096)) + (PORT datad (837:837:837) (723:723:723)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1683:1683:1683) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (321:321:321) (376:376:376)) + (PORT datac (990:990:990) (940:940:940)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1641:1641:1641) (1661:1661:1661)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (330:330:330) (388:388:388)) + (PORT datac (914:914:914) (825:825:825)) + (PORT datad (997:997:997) (952:952:952)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT datab (331:331:331) (389:389:389)) + (PORT datac (277:277:277) (340:340:340)) + (PORT datad (997:997:997) (952:952:952)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (384:384:384)) + (PORT datab (1038:1038:1038) (991:991:991)) + (PORT datac (279:279:279) (343:343:343)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (322:322:322) (377:377:377)) + (PORT datac (895:895:895) (857:857:857)) + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1913:1913:1913) (1709:1709:1709)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (PORT sload (1588:1588:1588) (1701:1701:1701)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[4\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (311:311:311) (331:331:331)) + (PORT datab (590:590:590) (574:574:574)) + (PORT datad (263:263:263) (277:277:277)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c0_reg2\~_wirecell) + (DELAY + (ABSOLUTE + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT asdata (1599:1599:1599) (1401:1401:1401)) + (PORT clrn (1690:1690:1690) (1645:1645:1645)) + (PORT sload (1588:1588:1588) (1701:1701:1701)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sload (posedge clk) (195:195:195)) + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~3) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (382:382:382)) + (PORT datab (322:322:322) (377:377:377)) + (PORT datad (959:959:959) (910:910:910)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (384:384:384)) + (PORT datab (998:998:998) (946:946:946)) + (PORT datad (280:280:280) (335:335:335)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (387:387:387)) + (PORT datab (1001:1001:1001) (949:949:949)) + (PORT datad (281:281:281) (336:336:336)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (321:321:321) (376:376:376)) + (PORT datac (940:940:940) (885:885:885)) + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1649:1649:1649) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1611:1611:1611) (1583:1583:1583)) + (PORT D (821:821:821) (856:856:856)) + (IOPATH (negedge ENA) Q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (513:513:513)) + (HOLD D (negedge ENA) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1584:1584:1584)) + (PORT d (1265:1265:1265) (1258:1258:1258)) + (IOPATH (posedge clk) q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1769:1769:1769) (1755:1755:1755)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (491:491:491) (503:503:503)) + ) + ) + (DELAY + (PATHPULSE datain dataout (491:491:491)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1606:1606:1606) (1577:1577:1577)) + (PORT D (1102:1102:1102) (1247:1247:1247)) + (IOPATH (negedge ENA) Q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (513:513:513)) + (HOLD D (negedge ENA) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1606:1606:1606) (1578:1578:1578)) + (PORT d (872:872:872) (967:967:967)) + (IOPATH (posedge clk) q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1764:1764:1764) (1749:1749:1749)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (491:491:491) (503:503:503)) + ) + ) + (DELAY + (PATHPULSE datain dataout (491:491:491)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1609:1609:1609) (1580:1580:1580)) + (PORT D (795:795:795) (877:877:877)) + (IOPATH (negedge ENA) Q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (513:513:513)) + (HOLD D (negedge ENA) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1609:1609:1609) (1581:1581:1581)) + (PORT d (1167:1167:1167) (1308:1308:1308)) + (IOPATH (posedge clk) q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1767:1767:1767) (1752:1752:1752)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (491:491:491) (503:503:503)) + ) + ) + (DELAY + (PATHPULSE datain dataout (491:491:491)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1611:1611:1611) (1583:1583:1583)) + (PORT D (798:798:798) (879:879:879)) + (IOPATH (negedge ENA) Q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (513:513:513)) + (HOLD D (negedge ENA) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1611:1611:1611) (1584:1584:1584)) + (PORT d (1190:1190:1190) (1333:1333:1333)) + (IOPATH (posedge clk) q (213:213:213) (213:213:213)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (104:104:104)) + (HOLD d (posedge clk) (112:112:112)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1769:1769:1769) (1755:1755:1755)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (491:491:491) (503:503:503)) + ) + ) + (DELAY + (PATHPULSE datain dataout (491:491:491)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_8_1200mv_85c_slow.vo b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_8_1200mv_85c_slow.vo new file mode 100644 index 0000000..0315695 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_8_1200mv_85c_slow.vo @@ -0,0 +1,11443 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:17:19" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module hdmi_colorbar ( + sys_clk, + sys_rst_n, + ddc_scl, + ddc_sda, + tmds_clk_p, + tmds_clk_n, + tmds_data_p, + tmds_data_n); +input sys_clk; +input sys_rst_n; +output ddc_scl; +output ddc_sda; +output tmds_clk_p; +output tmds_clk_n; +output [2:0] tmds_data_p; +output [2:0] tmds_data_n; + +// Design Ports Information +// ddc_scl => Location: PIN_N22, I/O Standard: 2.5 V, Current Strength: Default +// ddc_sda => Location: PIN_R22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_clk_p => Location: PIN_H21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_clk_n => Location: PIN_H22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_p[0] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_p[1] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_p[2] => Location: PIN_D21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_n[0] => Location: PIN_F22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_n[1] => Location: PIN_E22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_n[2] => Location: PIN_D22, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("hdmi_colorbar_8_1200mv_85c_v_slow.sdo"); +// synopsys translate_on + +wire \hdmi_ctrl_inst|encode_inst0|Add20~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~7 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~8_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~7 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~8_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~7 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~7 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~7 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~8_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~6_combout ; +wire \vga_ctrl_inst|Add0~2_combout ; +wire \vga_ctrl_inst|Add0~10_combout ; +wire \vga_ctrl_inst|Add1~2_combout ; +wire \vga_ctrl_inst|Add1~6_combout ; +wire \vga_ctrl_inst|Add1~8_combout ; +wire \vga_ctrl_inst|Add1~10_combout ; +wire \vga_ctrl_inst|Add1~12_combout ; +wire \vga_ctrl_inst|Add1~14_combout ; +wire \vga_ctrl_inst|Add1~16_combout ; +wire \vga_ctrl_inst|Add1~18_combout ; +wire \vga_ctrl_inst|Add1~20_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|condition_3~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_3~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~3_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~5_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~7_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~8_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~11_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~12_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~16_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add12~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~5_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~7_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~13_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~14_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~16_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~3_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~9_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~10_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~11_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~12_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~13_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~16_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add14~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~3_combout ; +wire \vga_ctrl_inst|pix_data_req~0_combout ; +wire \vga_ctrl_inst|pix_data_req~3_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~5_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~5_combout ; +wire \vga_ctrl_inst|pix_x[10]~1_combout ; +wire \vga_pic_inst|always0~1_combout ; +wire \vga_pic_inst|always0~2_combout ; +wire \vga_pic_inst|pix_data[9]~14_combout ; +wire \vga_pic_inst|pix_data~16_combout ; +wire \vga_ctrl_inst|pix_data_req~8_combout ; +wire \vga_ctrl_inst|cnt_v[10]~12_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout ; +wire \vga_pic_inst|LessThan10~0_combout ; +wire \vga_pic_inst|pix_data~22_combout ; +wire \vga_pic_inst|pix_data~23_combout ; +wire \vga_pic_inst|LessThan14~1_combout ; +wire \vga_pic_inst|pix_data[13]~24_combout ; +wire \vga_pic_inst|pix_data~25_combout ; +wire \hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~5_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~8_combout ; +wire \vga_pic_inst|pix_data~37_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~1 ; +wire \vga_ctrl_inst|Add0~3 ; +wire \vga_ctrl_inst|Add0~5 ; +wire \vga_ctrl_inst|Add0~6_combout ; +wire \vga_ctrl_inst|Add0~7 ; +wire \vga_ctrl_inst|Add0~8_combout ; +wire \vga_ctrl_inst|Add0~9 ; +wire \vga_ctrl_inst|Add0~11 ; +wire \vga_ctrl_inst|Add0~12_combout ; +wire \vga_ctrl_inst|Add0~13 ; +wire \vga_ctrl_inst|Add0~14_combout ; +wire \vga_ctrl_inst|Add0~4_combout ; +wire \vga_ctrl_inst|Equal0~0_combout ; +wire \vga_ctrl_inst|Add0~15 ; +wire \vga_ctrl_inst|Add0~16_combout ; +wire \vga_ctrl_inst|Add0~19 ; +wire \vga_ctrl_inst|Add0~20_combout ; +wire \vga_ctrl_inst|Add0~21 ; +wire \vga_ctrl_inst|Add0~22_combout ; +wire \vga_ctrl_inst|Equal0~1_combout ; +wire \vga_ctrl_inst|cnt_h~0_combout ; +wire \vga_ctrl_inst|Equal0~2_combout ; +wire \vga_ctrl_inst|cnt_h~2_combout ; +wire \vga_ctrl_inst|Add0~17 ; +wire \vga_ctrl_inst|Add0~18_combout ; +wire \vga_ctrl_inst|cnt_h~1_combout ; +wire \vga_ctrl_inst|LessThan4~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ; +wire \vga_ctrl_inst|Add2~1_cout ; +wire \vga_ctrl_inst|Add2~3_cout ; +wire \vga_ctrl_inst|Add2~5_cout ; +wire \vga_ctrl_inst|Add2~7_cout ; +wire \vga_ctrl_inst|Add2~9_cout ; +wire \vga_ctrl_inst|Add2~11 ; +wire \vga_ctrl_inst|Add2~13 ; +wire \vga_ctrl_inst|Add2~15 ; +wire \vga_ctrl_inst|Add2~17 ; +wire \vga_ctrl_inst|Add2~18_combout ; +wire \vga_ctrl_inst|Add2~16_combout ; +wire \vga_ctrl_inst|Add2~14_combout ; +wire \vga_pic_inst|pix_data~12_combout ; +wire \vga_ctrl_inst|Add2~12_combout ; +wire \vga_ctrl_inst|pix_data_req~5_combout ; +wire \vga_ctrl_inst|Equal0~3_combout ; +wire \vga_ctrl_inst|cnt_v[7]~7_combout ; +wire \vga_ctrl_inst|cnt_v[5]~10_combout ; +wire \vga_ctrl_inst|cnt_v[8]~6_combout ; +wire \vga_ctrl_inst|always1~0_combout ; +wire \vga_ctrl_inst|cnt_v[1]~1_combout ; +wire \vga_ctrl_inst|cnt_v[4]~5_combout ; +wire \vga_ctrl_inst|always1~1_combout ; +wire \vga_ctrl_inst|Add1~0_combout ; +wire \vga_ctrl_inst|cnt_v[0]~2_combout ; +wire \vga_ctrl_inst|cnt_v[3]~3_combout ; +wire \vga_ctrl_inst|always1~2_combout ; +wire \vga_ctrl_inst|cnt_v[11]~0_combout ; +wire \vga_ctrl_inst|cnt_v[9]~9_combout ; +wire \vga_ctrl_inst|cnt_v[6]~8_combout ; +wire \vga_ctrl_inst|Add1~1 ; +wire \vga_ctrl_inst|Add1~3 ; +wire \vga_ctrl_inst|Add1~4_combout ; +wire \vga_ctrl_inst|cnt_v[2]~4_combout ; +wire \vga_ctrl_inst|Add1~5 ; +wire \vga_ctrl_inst|Add1~7 ; +wire \vga_ctrl_inst|Add1~9 ; +wire \vga_ctrl_inst|Add1~11 ; +wire \vga_ctrl_inst|Add1~13 ; +wire \vga_ctrl_inst|Add1~15 ; +wire \vga_ctrl_inst|Add1~17 ; +wire \vga_ctrl_inst|Add1~19 ; +wire \vga_ctrl_inst|Add1~21 ; +wire \vga_ctrl_inst|Add1~22_combout ; +wire \vga_ctrl_inst|cnt_v[11]~11_combout ; +wire \vga_ctrl_inst|pix_data_req~2_combout ; +wire \vga_ctrl_inst|pix_data_req~4_combout ; +wire \vga_ctrl_inst|pix_data_req~6_combout ; +wire \vga_ctrl_inst|pix_data_req~7_combout ; +wire \vga_pic_inst|pix_data[13]~11_combout ; +wire \vga_pic_inst|always0~0_combout ; +wire \vga_pic_inst|pix_data~13_combout ; +wire \vga_pic_inst|pix_data~17_combout ; +wire \vga_pic_inst|pix_data~34_combout ; +wire \vga_pic_inst|pix_data[13]~8_combout ; +wire \vga_pic_inst|pix_data[13]~9_combout ; +wire \vga_pic_inst|pix_data[13]~10_combout ; +wire \vga_pic_inst|pix_data~18_combout ; +wire \vga_ctrl_inst|Add2~19 ; +wire \vga_ctrl_inst|Add2~20_combout ; +wire \vga_ctrl_inst|Add2~10_combout ; +wire \vga_pic_inst|LessThan17~4_combout ; +wire \vga_pic_inst|LessThan17~3_combout ; +wire \vga_pic_inst|LessThan14~0_combout ; +wire \vga_pic_inst|pix_data~19_combout ; +wire \vga_pic_inst|pix_data~20_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add6~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout ; +wire \vga_ctrl_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|pix_data_req~1_combout ; +wire \vga_ctrl_inst|rgb[1]~0_combout ; +wire \vga_ctrl_inst|rgb[2]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add14~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~9_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~10_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add12~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add14~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~13_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~14_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~15_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal2~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add4~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|de_reg1~q ; +wire \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|de_reg2~q ; +wire \hdmi_ctrl_inst|encode_inst0|condition_2~combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[3]~14 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout ; +wire \hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout ; +wire \vga_ctrl_inst|LessThan0~0_combout ; +wire \vga_ctrl_inst|LessThan0~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c0_reg1~q ; +wire \hdmi_ctrl_inst|encode_inst2|c0_reg2~q ; +wire \hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout ; +wire \vga_ctrl_inst|LessThan1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c1_reg1~q ; +wire \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c1_reg2~q ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~7_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout ; +wire \vga_pic_inst|LessThan17~2_combout ; +wire \vga_pic_inst|pix_data[9]~15_combout ; +wire \vga_pic_inst|pix_data~35_combout ; +wire \vga_pic_inst|pix_data~36_combout ; +wire \vga_pic_inst|pix_data~21_combout ; +wire \vga_pic_inst|pix_data~26_combout ; +wire \vga_ctrl_inst|pix_x[11]~0_combout ; +wire \vga_pic_inst|pix_data~27_combout ; +wire \vga_ctrl_inst|rgb[10]~2_combout ; +wire \vga_pic_inst|pix_data~29_combout ; +wire \vga_pic_inst|pix_data~30_combout ; +wire \vga_pic_inst|pix_data~31_combout ; +wire \vga_ctrl_inst|rgb[6]~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add5~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add14~1_combout ; +wire \vga_pic_inst|pix_data~28_combout ; +wire \vga_ctrl_inst|rgb[7]~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add13~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add13~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_3~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add14~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add14~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~9_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~10_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~15_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal1~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_2~combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~11_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~12_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[3]~14 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~7_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout ; +wire \vga_pic_inst|pix_data~33_combout ; +wire \vga_ctrl_inst|rgb[13]~6_combout ; +wire \vga_pic_inst|pix_data~32_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add6~0_combout ; +wire \vga_ctrl_inst|rgb[12]~5_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add12~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add14~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add12~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~5_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal1~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~15_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_2~combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~14_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~7_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~8_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~7 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~8_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[3]~14 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~7_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout ; +wire [9:0] \hdmi_ctrl_inst|encode_inst0|data_out ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [11:0] \vga_ctrl_inst|cnt_v ; +wire [11:0] \vga_ctrl_inst|cnt_h ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s ; +wire [7:0] \hdmi_ctrl_inst|encode_inst0|data_in_reg ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [8:0] \hdmi_ctrl_inst|encode_inst0|q_m_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst0|q_m_n1 ; +wire [15:0] \vga_pic_inst|pix_data ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [3:0] \hdmi_ctrl_inst|encode_inst0|data_in_n1 ; +wire [2:0] \hdmi_ctrl_inst|par_to_ser_inst0|cnt ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [3:0] \hdmi_ctrl_inst|encode_inst0|q_m_n0 ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [4:0] \hdmi_ctrl_inst|encode_inst0|cnt ; +wire [4:0] \hdmi_ctrl_inst|encode_inst1|cnt ; +wire [9:0] \hdmi_ctrl_inst|encode_inst1|data_out ; +wire [8:0] \hdmi_ctrl_inst|encode_inst1|q_m_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst1|q_m_n0 ; +wire [3:0] \hdmi_ctrl_inst|encode_inst1|q_m_n1 ; +wire [7:0] \hdmi_ctrl_inst|encode_inst1|data_in_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst1|data_in_n1 ; +wire [4:0] \hdmi_ctrl_inst|encode_inst2|cnt ; +wire [9:0] \hdmi_ctrl_inst|encode_inst2|data_out ; +wire [8:0] \hdmi_ctrl_inst|encode_inst2|q_m_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst2|q_m_n0 ; +wire [3:0] \hdmi_ctrl_inst|encode_inst2|q_m_n1 ; +wire [7:0] \hdmi_ctrl_inst|encode_inst2|data_in_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst2|data_in_n1 ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 10; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 10; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 5; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 10; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 6891; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 250; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: FF_X40_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N7 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N9 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y22_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y23_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y23_N13 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((GND) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add20~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add20~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~0 .lut_mask = 16'h66BB; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst0|Add20~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// ((\hdmi_ctrl_inst|encode_inst0|Add20~1 ) # (GND))))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|Add20~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst0|Add20~1 )))) +// \hdmi_ctrl_inst|encode_inst0|Add20~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((!\hdmi_ctrl_inst|encode_inst0|Add20~1 ) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst0|Add20~1 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add20~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add20~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~2 .lut_mask = 16'h692B; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~4_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst0|Add20~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst0|Add20~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add20~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst0|Add20~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add20~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add20~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~6_combout = !\hdmi_ctrl_inst|encode_inst0|Add20~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add20~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add17~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [0] & \hdmi_ctrl_inst|encode_inst0|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|Add17~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst0|Add17~1 )))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (!\hdmi_ctrl_inst|encode_inst0|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & ((\hdmi_ctrl_inst|encode_inst0|Add17~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|Add17~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & !\hdmi_ctrl_inst|encode_inst0|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & +// ((!\hdmi_ctrl_inst|encode_inst0|Add17~1 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~4_combout = ((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] $ (\hdmi_ctrl_inst|encode_inst0|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst0|Add17~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|Add17~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst0|Add17~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst0|Add17~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~6_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [3] & (!\hdmi_ctrl_inst|encode_inst0|Add17~5 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & ((\hdmi_ctrl_inst|encode_inst0|Add17~5 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add17~7 = CARRY((!\hdmi_ctrl_inst|encode_inst0|Add17~5 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~6 .lut_mask = 16'h3C3F; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~8_combout = \hdmi_ctrl_inst|encode_inst0|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst0|Add17~7 ) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~7 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~8 .lut_mask = 16'hC3C3; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]) # (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add23~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add23~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~0 .lut_mask = 16'h66DD; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst0|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// (\hdmi_ctrl_inst|encode_inst0|Add23~1 & VCC)))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst0|Add23~1 ) # (GND))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst0|Add23~1 )))) +// \hdmi_ctrl_inst|encode_inst0|Add23~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst0|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & +// ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst0|Add23~1 )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add23~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add23~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~2 .lut_mask = 16'h694D; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~4_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst0|Add23~3 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst0|Add23~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add23~5 = CARRY((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst0|Add23~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add23~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add23~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~4 .lut_mask = 16'h5A05; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~6_combout = !\hdmi_ctrl_inst|encode_inst0|Add23~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add23~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add15~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [0] & \hdmi_ctrl_inst|encode_inst0|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|Add15~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst0|Add15~1 )))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (!\hdmi_ctrl_inst|encode_inst0|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & ((\hdmi_ctrl_inst|encode_inst0|Add15~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|Add15~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & !\hdmi_ctrl_inst|encode_inst0|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & +// ((!\hdmi_ctrl_inst|encode_inst0|Add15~1 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~4_combout = ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] $ (\hdmi_ctrl_inst|encode_inst0|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst0|Add15~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|Add15~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst0|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst0|Add15~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst0|Add15~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~6_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|cnt [3] & (\hdmi_ctrl_inst|encode_inst0|Add15~5 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & +// (!\hdmi_ctrl_inst|encode_inst0|Add15~5 )))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|cnt [3] & (!\hdmi_ctrl_inst|encode_inst0|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & ((\hdmi_ctrl_inst|encode_inst0|Add15~5 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|Add15~7 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & !\hdmi_ctrl_inst|encode_inst0|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & +// ((!\hdmi_ctrl_inst|encode_inst0|Add15~5 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~6 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~8_combout = \hdmi_ctrl_inst|encode_inst0|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst0|Add15~7 ) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~7 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~8 .lut_mask = 16'hC3C3; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~4_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [3] & (\hdmi_ctrl_inst|encode_inst0|Add19~3 $ (GND))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & (!\hdmi_ctrl_inst|encode_inst0|Add19~3 & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add19~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [3] & !\hdmi_ctrl_inst|encode_inst0|Add19~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add19~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add19~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~4 .lut_mask = 16'hA50A; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~4_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst0|Add22~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & (\hdmi_ctrl_inst|encode_inst0|Add22~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add22~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [3]) # (!\hdmi_ctrl_inst|encode_inst0|Add22~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add22~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add22~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[0]~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & (\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & +// (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & +// ((\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|cnt[0]~8 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & +// ((!\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ) # (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~16_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~15_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~7 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[1]~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout = ((\hdmi_ctrl_inst|encode_inst0|Add16~12_combout $ (\hdmi_ctrl_inst|encode_inst0|Add16~14_combout $ (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|cnt[1]~10 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~12_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~14_combout ) # (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~12_combout & +// (\hdmi_ctrl_inst|encode_inst0|Add16~14_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~12_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1]~9 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[2]~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & (\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & +// (!\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & (!\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & +// ((\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|cnt[2]~12 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & +// ((!\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ) # (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2]~11 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y22_N31 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((GND) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add20~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add20~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~0 .lut_mask = 16'h66BB; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|Add20~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// ((\hdmi_ctrl_inst|encode_inst1|Add20~1 ) # (GND))))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|Add20~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst1|Add20~1 )))) +// \hdmi_ctrl_inst|encode_inst1|Add20~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((!\hdmi_ctrl_inst|encode_inst1|Add20~1 ) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst1|Add20~1 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add20~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add20~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~2 .lut_mask = 16'h692B; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~4_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst1|Add20~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst1|Add20~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add20~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst1|Add20~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add20~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add20~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~4 .lut_mask = 16'h3CCF; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~6_combout = !\hdmi_ctrl_inst|encode_inst1|Add20~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add20~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~0_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add17~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [0] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~2_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst1|Add17~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & +// (!\hdmi_ctrl_inst|encode_inst1|Add17~1 )))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst1|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & +// ((\hdmi_ctrl_inst|encode_inst1|Add17~1 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|Add17~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [1] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst1|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((!\hdmi_ctrl_inst|encode_inst1|Add17~1 ) +// # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~4_combout = ((\hdmi_ctrl_inst|encode_inst1|cnt [2] $ (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] $ (!\hdmi_ctrl_inst|encode_inst1|Add17~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|Add17~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]) # (!\hdmi_ctrl_inst|encode_inst1|Add17~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 +// [2] & !\hdmi_ctrl_inst|encode_inst1|Add17~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~6_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & (!\hdmi_ctrl_inst|encode_inst1|Add17~5 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|Add17~5 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add17~7 = CARRY((!\hdmi_ctrl_inst|encode_inst1|Add17~5 ) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~6 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~8_combout = \hdmi_ctrl_inst|encode_inst1|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst1|Add17~7 ) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~7 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~8 .lut_mask = 16'hA5A5; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]) # (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add23~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add23~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~0 .lut_mask = 16'h66DD; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~4_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst1|Add23~3 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst1|Add23~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add23~5 = CARRY((!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst1|Add23~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add23~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add23~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~4 .lut_mask = 16'h3C03; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~6_combout = !\hdmi_ctrl_inst|encode_inst1|Add23~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add23~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst1|cnt [1] & (\hdmi_ctrl_inst|encode_inst1|Add15~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst1|Add15~1 )))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst1|cnt [1] & (!\hdmi_ctrl_inst|encode_inst1|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((\hdmi_ctrl_inst|encode_inst1|Add15~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|Add15~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & !\hdmi_ctrl_inst|encode_inst1|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & +// ((!\hdmi_ctrl_inst|encode_inst1|Add15~1 ) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~6_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst1|Add15~5 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & +// (!\hdmi_ctrl_inst|encode_inst1|Add15~5 )))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst1|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & +// ((\hdmi_ctrl_inst|encode_inst1|Add15~5 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|Add15~7 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [3] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst1|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((!\hdmi_ctrl_inst|encode_inst1|Add15~5 ) +// # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~6 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~8_combout = \hdmi_ctrl_inst|encode_inst1|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst1|Add15~7 ) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~7 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~8 .lut_mask = 16'hA5A5; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|cnt [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|cnt [1] & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add19~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & \hdmi_ctrl_inst|encode_inst1|cnt [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add19~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~2_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [2] & (!\hdmi_ctrl_inst|encode_inst1|Add19~1 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & ((\hdmi_ctrl_inst|encode_inst1|Add19~1 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add19~3 = CARRY((!\hdmi_ctrl_inst|encode_inst1|Add19~1 ) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add19~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add19~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~2 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~4_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & (\hdmi_ctrl_inst|encode_inst1|Add19~3 $ (GND))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & (!\hdmi_ctrl_inst|encode_inst1|Add19~3 & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add19~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [3] & !\hdmi_ctrl_inst|encode_inst1|Add19~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add19~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add19~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~4 .lut_mask = 16'hA50A; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~6_combout = \hdmi_ctrl_inst|encode_inst1|Add19~5 $ (\hdmi_ctrl_inst|encode_inst1|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst1|Add19~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~6 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & ((\hdmi_ctrl_inst|encode_inst1|cnt [1]) # (GND))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|cnt [1] $ (VCC))) +// \hdmi_ctrl_inst|encode_inst1|Add22~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]) # (\hdmi_ctrl_inst|encode_inst1|cnt [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add22~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~0 .lut_mask = 16'h99EE; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~2_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|Add22~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & (!\hdmi_ctrl_inst|encode_inst1|Add22~1 )) +// \hdmi_ctrl_inst|encode_inst1|Add22~3 = CARRY((!\hdmi_ctrl_inst|encode_inst1|cnt [2] & !\hdmi_ctrl_inst|encode_inst1|Add22~1 )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add22~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add22~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~2 .lut_mask = 16'hA505; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~4_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst1|Add22~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & (\hdmi_ctrl_inst|encode_inst1|Add22~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add22~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [3]) # (!\hdmi_ctrl_inst|encode_inst1|Add22~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add22~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add22~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y23_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((GND) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add20~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add20~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~0 .lut_mask = 16'h66BB; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~4_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst2|Add20~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst2|Add20~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add20~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst2|Add20~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add20~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add20~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~4 .lut_mask = 16'h3CCF; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~0_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [0] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [0] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add17~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [0] & \hdmi_ctrl_inst|encode_inst2|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|Add17~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst2|Add17~1 )))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (!\hdmi_ctrl_inst|encode_inst2|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & ((\hdmi_ctrl_inst|encode_inst2|Add17~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|Add17~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & !\hdmi_ctrl_inst|encode_inst2|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & +// ((!\hdmi_ctrl_inst|encode_inst2|Add17~1 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~4_combout = ((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] $ (\hdmi_ctrl_inst|encode_inst2|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst2|Add17~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|Add17~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst2|Add17~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst2|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst2|Add17~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~6_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [3] & (!\hdmi_ctrl_inst|encode_inst2|Add17~5 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & ((\hdmi_ctrl_inst|encode_inst2|Add17~5 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add17~7 = CARRY((!\hdmi_ctrl_inst|encode_inst2|Add17~5 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~6 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]) # (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add23~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add23~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~0 .lut_mask = 16'h66DD; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~4_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst2|Add23~3 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst2|Add23~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add23~5 = CARRY((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst2|Add23~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add23~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add23~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~4 .lut_mask = 16'h3C03; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|Add15~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst2|Add15~1 )))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (!\hdmi_ctrl_inst|encode_inst2|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & ((\hdmi_ctrl_inst|encode_inst2|Add15~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|Add15~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & !\hdmi_ctrl_inst|encode_inst2|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & +// ((!\hdmi_ctrl_inst|encode_inst2|Add15~1 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~4_combout = ((\hdmi_ctrl_inst|encode_inst2|cnt [2] $ (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] $ (!\hdmi_ctrl_inst|encode_inst2|Add15~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|Add15~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst2|Add15~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 +// [2] & !\hdmi_ctrl_inst|encode_inst2|Add15~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~6_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst2|cnt [3] & (\hdmi_ctrl_inst|encode_inst2|Add15~5 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & +// (!\hdmi_ctrl_inst|encode_inst2|Add15~5 )))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst2|cnt [3] & (!\hdmi_ctrl_inst|encode_inst2|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & ((\hdmi_ctrl_inst|encode_inst2|Add15~5 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|Add15~7 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & !\hdmi_ctrl_inst|encode_inst2|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & +// ((!\hdmi_ctrl_inst|encode_inst2|Add15~5 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~6 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~8_combout = \hdmi_ctrl_inst|encode_inst2|Add15~7 $ (!\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~7 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~8 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~2_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [2] & (!\hdmi_ctrl_inst|encode_inst2|Add19~1 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2] & ((\hdmi_ctrl_inst|encode_inst2|Add19~1 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add19~3 = CARRY((!\hdmi_ctrl_inst|encode_inst2|Add19~1 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add19~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add19~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~2 .lut_mask = 16'h3C3F; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~4_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [3] & (\hdmi_ctrl_inst|encode_inst2|Add19~3 $ (GND))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & (!\hdmi_ctrl_inst|encode_inst2|Add19~3 & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add19~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [3] & !\hdmi_ctrl_inst|encode_inst2|Add19~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add19~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add19~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~4 .lut_mask = 16'hA50A; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~6_combout = \hdmi_ctrl_inst|encode_inst2|Add19~5 $ (\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add19~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~6 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~0_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [1] & ((\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]) # (GND))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] $ (VCC))) +// \hdmi_ctrl_inst|encode_inst2|Add22~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [1]) # (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add22~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~0 .lut_mask = 16'h99EE; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~2_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|Add22~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2] & (!\hdmi_ctrl_inst|encode_inst2|Add22~1 )) +// \hdmi_ctrl_inst|encode_inst2|Add22~3 = CARRY((!\hdmi_ctrl_inst|encode_inst2|cnt [2] & !\hdmi_ctrl_inst|encode_inst2|Add22~1 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add22~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add22~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~2 .lut_mask = 16'hC303; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~4_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst2|Add22~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & (\hdmi_ctrl_inst|encode_inst2|Add22~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add22~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [3]) # (!\hdmi_ctrl_inst|encode_inst2|Add22~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add22~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add22~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~6_combout = \hdmi_ctrl_inst|encode_inst2|Add22~5 $ (!\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add22~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~6 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y24_N11 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y22_N19 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [6]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y21_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [7]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~2 ( +// Equation(s): +// \vga_ctrl_inst|Add0~2_combout = (\vga_ctrl_inst|cnt_h [1] & (!\vga_ctrl_inst|Add0~1 )) # (!\vga_ctrl_inst|cnt_h [1] & ((\vga_ctrl_inst|Add0~1 ) # (GND))) +// \vga_ctrl_inst|Add0~3 = CARRY((!\vga_ctrl_inst|Add0~1 ) # (!\vga_ctrl_inst|cnt_h [1])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~1 ), + .combout(\vga_ctrl_inst|Add0~2_combout ), + .cout(\vga_ctrl_inst|Add0~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~10 ( +// Equation(s): +// \vga_ctrl_inst|Add0~10_combout = (\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|Add0~9 )) # (!\vga_ctrl_inst|cnt_h [5] & ((\vga_ctrl_inst|Add0~9 ) # (GND))) +// \vga_ctrl_inst|Add0~11 = CARRY((!\vga_ctrl_inst|Add0~9 ) # (!\vga_ctrl_inst|cnt_h [5])) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~9 ), + .combout(\vga_ctrl_inst|Add0~10_combout ), + .cout(\vga_ctrl_inst|Add0~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~2 ( +// Equation(s): +// \vga_ctrl_inst|Add1~2_combout = (\vga_ctrl_inst|cnt_v [1] & (!\vga_ctrl_inst|Add1~1 )) # (!\vga_ctrl_inst|cnt_v [1] & ((\vga_ctrl_inst|Add1~1 ) # (GND))) +// \vga_ctrl_inst|Add1~3 = CARRY((!\vga_ctrl_inst|Add1~1 ) # (!\vga_ctrl_inst|cnt_v [1])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~1 ), + .combout(\vga_ctrl_inst|Add1~2_combout ), + .cout(\vga_ctrl_inst|Add1~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~6 ( +// Equation(s): +// \vga_ctrl_inst|Add1~6_combout = (\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|Add1~5 )) # (!\vga_ctrl_inst|cnt_v [3] & ((\vga_ctrl_inst|Add1~5 ) # (GND))) +// \vga_ctrl_inst|Add1~7 = CARRY((!\vga_ctrl_inst|Add1~5 ) # (!\vga_ctrl_inst|cnt_v [3])) + + .dataa(\vga_ctrl_inst|cnt_v [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~5 ), + .combout(\vga_ctrl_inst|Add1~6_combout ), + .cout(\vga_ctrl_inst|Add1~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~6 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~8 ( +// Equation(s): +// \vga_ctrl_inst|Add1~8_combout = (\vga_ctrl_inst|cnt_v [4] & (\vga_ctrl_inst|Add1~7 $ (GND))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|Add1~7 & VCC)) +// \vga_ctrl_inst|Add1~9 = CARRY((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Add1~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~7 ), + .combout(\vga_ctrl_inst|Add1~8_combout ), + .cout(\vga_ctrl_inst|Add1~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~10 ( +// Equation(s): +// \vga_ctrl_inst|Add1~10_combout = (\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|Add1~9 )) # (!\vga_ctrl_inst|cnt_v [5] & ((\vga_ctrl_inst|Add1~9 ) # (GND))) +// \vga_ctrl_inst|Add1~11 = CARRY((!\vga_ctrl_inst|Add1~9 ) # (!\vga_ctrl_inst|cnt_v [5])) + + .dataa(\vga_ctrl_inst|cnt_v [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~9 ), + .combout(\vga_ctrl_inst|Add1~10_combout ), + .cout(\vga_ctrl_inst|Add1~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~12 ( +// Equation(s): +// \vga_ctrl_inst|Add1~12_combout = (\vga_ctrl_inst|cnt_v [6] & (\vga_ctrl_inst|Add1~11 $ (GND))) # (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|Add1~11 & VCC)) +// \vga_ctrl_inst|Add1~13 = CARRY((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Add1~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~11 ), + .combout(\vga_ctrl_inst|Add1~12_combout ), + .cout(\vga_ctrl_inst|Add1~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~14 ( +// Equation(s): +// \vga_ctrl_inst|Add1~14_combout = (\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|Add1~13 )) # (!\vga_ctrl_inst|cnt_v [7] & ((\vga_ctrl_inst|Add1~13 ) # (GND))) +// \vga_ctrl_inst|Add1~15 = CARRY((!\vga_ctrl_inst|Add1~13 ) # (!\vga_ctrl_inst|cnt_v [7])) + + .dataa(\vga_ctrl_inst|cnt_v [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~13 ), + .combout(\vga_ctrl_inst|Add1~14_combout ), + .cout(\vga_ctrl_inst|Add1~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~16 ( +// Equation(s): +// \vga_ctrl_inst|Add1~16_combout = (\vga_ctrl_inst|cnt_v [8] & (\vga_ctrl_inst|Add1~15 $ (GND))) # (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|Add1~15 & VCC)) +// \vga_ctrl_inst|Add1~17 = CARRY((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Add1~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~15 ), + .combout(\vga_ctrl_inst|Add1~16_combout ), + .cout(\vga_ctrl_inst|Add1~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~18 ( +// Equation(s): +// \vga_ctrl_inst|Add1~18_combout = (\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|Add1~17 )) # (!\vga_ctrl_inst|cnt_v [9] & ((\vga_ctrl_inst|Add1~17 ) # (GND))) +// \vga_ctrl_inst|Add1~19 = CARRY((!\vga_ctrl_inst|Add1~17 ) # (!\vga_ctrl_inst|cnt_v [9])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~17 ), + .combout(\vga_ctrl_inst|Add1~18_combout ), + .cout(\vga_ctrl_inst|Add1~19 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~18 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~20 ( +// Equation(s): +// \vga_ctrl_inst|Add1~20_combout = (\vga_ctrl_inst|cnt_v [10] & (\vga_ctrl_inst|Add1~19 $ (GND))) # (!\vga_ctrl_inst|cnt_v [10] & (!\vga_ctrl_inst|Add1~19 & VCC)) +// \vga_ctrl_inst|Add1~21 = CARRY((\vga_ctrl_inst|cnt_v [10] & !\vga_ctrl_inst|Add1~19 )) + + .dataa(\vga_ctrl_inst|cnt_v [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~19 ), + .combout(\vga_ctrl_inst|Add1~20_combout ), + .cout(\vga_ctrl_inst|Add1~21 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~20 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y20_N11 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y20_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [2] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1 .lut_mask = 16'h00F0; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N15 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add12~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_3~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_3~1_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_3~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~1 .lut_mask = 16'h0A8E; +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal1~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal1~0_combout = (!\hdmi_ctrl_inst|encode_inst0|cnt [4] & (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & (!\hdmi_ctrl_inst|encode_inst0|cnt [2] & !\hdmi_ctrl_inst|encode_inst0|cnt [0]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~0 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N27 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y24_N19 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n0[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add14~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_3~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_3~1_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & \hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]) # ((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & \hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_3~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~1 .lut_mask = 16'h4F04; +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N31 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]) # (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2 .lut_mask = 16'hFFF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~0_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst0|Add17~8_combout ) # (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add23~6_combout & ((!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add23~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add17~8_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~0 .lut_mask = 16'hCCE2; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~1_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add15~8_combout ) # ((!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~0_combout +// & (((\hdmi_ctrl_inst|encode_inst0|Add20~6_combout & \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~8_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add20~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~1 .lut_mask = 16'hD8AA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~3_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|Add17~6_combout ))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add23~4_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add23~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add17~6_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~3 .lut_mask = 16'hF2C2; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~4_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~3_combout & (((\hdmi_ctrl_inst|encode_inst0|Add15~6_combout ) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~3_combout +// & (\hdmi_ctrl_inst|encode_inst0|Add20~4_combout & ((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add20~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add16~3_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~4 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~5_combout = (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst0|Add19~4_combout ))) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst0|Add22~4_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add22~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add19~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~5 .lut_mask = 16'h3210; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~7_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst0|Add20~2_combout )) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add23~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add20~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add23~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~7 .lut_mask = 16'hFA0C; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~8_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~7_combout & ((\hdmi_ctrl_inst|encode_inst0|Add15~4_combout ) # ((!\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~7_combout +// & (((\hdmi_ctrl_inst|encode_inst0|Add17~4_combout & \hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~7_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add17~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~8 .lut_mask = 16'hD8AA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~11_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|Add17~2_combout ) # ((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst0|Add23~0_combout & !\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add17~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add23~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~11_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~11 .lut_mask = 16'hF0AC; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~12 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~12_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~11_combout & ((\hdmi_ctrl_inst|encode_inst0|Add15~2_combout ) # ((!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst0|Add16~11_combout & (((\hdmi_ctrl_inst|encode_inst0|Add20~0_combout & \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~11_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add20~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~12_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~12 .lut_mask = 16'hD8AA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~16 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~16_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|cnt [0]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .datad(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~16_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~16 .lut_mask = 16'h5F0A; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal1~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal1~1_combout = (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & \hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~1 .lut_mask = 16'h0F00; +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add12~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add12~1_combout = (!\hdmi_ctrl_inst|encode_inst0|data_in_reg [4] & \hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add12~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add12~1 .lut_mask = 16'h3300; +defparam \hdmi_ctrl_inst|encode_inst0|Add12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N7 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~2_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [3] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_reg [3]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~2 .lut_mask = 16'h995A; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [4])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [3]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out [4]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [3]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2 .lut_mask = 16'hACAC; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~0_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add17~8_combout ) # (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add23~6_combout & ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add23~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add17~8_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~0 .lut_mask = 16'hAAE4; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~1_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~0_combout & ((\hdmi_ctrl_inst|encode_inst1|Add15~8_combout ) # ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~0_combout +// & (((\hdmi_ctrl_inst|encode_inst1|Add20~6_combout & \hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add15~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add20~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~1 .lut_mask = 16'hACF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~5_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3])))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add22~4_combout & (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add22~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~5 .lut_mask = 16'hA4AE; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~6_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~5_combout ) # ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & \hdmi_ctrl_inst|encode_inst1|Add19~4_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add19~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~6 .lut_mask = 16'hF8F8; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~7_combout = (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add22~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add22~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~7 .lut_mask = 16'hAF44; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~8_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~7_combout & (((!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~7_combout & +// (\hdmi_ctrl_inst|encode_inst1|Add19~2_combout & (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add19~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~7_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~8 .lut_mask = 16'h2CEC; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~13_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add17~2_combout ) # (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add23~0_combout & ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add23~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add17~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~13_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~13 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~14 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~14_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~13_combout & (((\hdmi_ctrl_inst|encode_inst1|Add15~2_combout ) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|Add16~13_combout & (\hdmi_ctrl_inst|encode_inst1|Add20~0_combout & ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add20~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~13_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add15~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~14_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~14 .lut_mask = 16'hE2CC; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~16 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~16_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst1|cnt [0]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~16_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~16 .lut_mask = 16'h3F0C; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal2~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal2~1_combout = (\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout & !\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~1 .lut_mask = 16'h00AA; +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N31 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y21_N1 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~2_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [2] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~2 .lut_mask = 16'hA53C; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~2_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout ) # ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst2|Add19~6_combout )) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst2|Add22~6_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add19~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add22~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~2 .lut_mask = 16'hFAFC; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~3_combout = (\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|Add17~6_combout )) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|Add23~4_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add17~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|Add23~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~3 .lut_mask = 16'hE3E0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~4_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~3_combout & ((\hdmi_ctrl_inst|encode_inst2|Add15~6_combout ) # ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~3_combout +// & (((\hdmi_ctrl_inst|encode_inst2|Add20~4_combout & \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add15~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add20~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~3_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~4 .lut_mask = 16'hACF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~9_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2])))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|Add22~2_combout & ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add22~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~9_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~9 .lut_mask = 16'hAA4E; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~10 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~10_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~9_combout & (((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2])))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~9_combout & +// (\hdmi_ctrl_inst|encode_inst2|Add19~2_combout & ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add19~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~9_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~10_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~10 .lut_mask = 16'h3AF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~11_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|Add17~2_combout ) # (\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|Add23~0_combout & ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add23~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add17~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~11_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~11 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~12 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~12_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~11_combout & (((\hdmi_ctrl_inst|encode_inst2|Add15~2_combout ) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst2|Add16~11_combout & (\hdmi_ctrl_inst|encode_inst2|Add20~0_combout & ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add20~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add15~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~11_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~12_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~12 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~13_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|Add22~0_combout & !\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|Add22~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~13_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~13 .lut_mask = 16'hAA72; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~16 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~16_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|cnt [0])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~16_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~16 .lut_mask = 16'h0FCC; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal2~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal2~1_combout = (\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout & !\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~1 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add14~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add14~1_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3] & (\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] $ (!\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add14~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add14~1 .lut_mask = 16'hC00C; +defparam \hdmi_ctrl_inst|encode_inst2|Add14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N25 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~2_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [3] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~2 .lut_mask = 16'h939C; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~3_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~3 .lut_mask = 16'hF303; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~0_combout = (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|cnt_v [8]))) + + .dataa(\vga_ctrl_inst|cnt_v [9]), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|cnt_v [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N31 +dffeas \vga_ctrl_inst|cnt_v[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[10]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[10] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~3 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~3_combout = (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~2_combout & ((\vga_ctrl_inst|always1~0_combout ) # (!\vga_ctrl_inst|cnt_v [9])))) + + .dataa(\vga_ctrl_inst|pix_data_req~1_combout ), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|always1~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~3 .lut_mask = 16'hA200; +defparam \vga_ctrl_inst|pix_data_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout = \hdmi_ctrl_inst|encode_inst0|data_in_reg [3] $ (\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m[3]~0 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst0|q_m[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~5_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [4] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~5 .lut_mask = 16'h995A; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N19 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [6])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [6]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N31 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y21_N27 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [7])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [4]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [7]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [4]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N21 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~4_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [4] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_reg [4]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~4 .lut_mask = 16'hA53C; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout = \hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] $ (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m[3]~0 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst2|q_m[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N9 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~5_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [4] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~5 .lut_mask = 16'hC366; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y20_N11 +dffeas \vga_ctrl_inst|cnt_h[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|pix_x[10]~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_x[10]~1_combout = (\vga_ctrl_inst|Add2~18_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~18_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_x[10]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_x[10]~1 .lut_mask = 16'hFF0F; +defparam \vga_ctrl_inst|pix_x[10]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N10 +cycloneive_lcell_comb \vga_pic_inst|always0~1 ( +// Equation(s): +// \vga_pic_inst|always0~1_combout = (\vga_ctrl_inst|Add2~14_combout ) # ((\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout )) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|always0~1 .lut_mask = 16'hFFAF; +defparam \vga_pic_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N12 +cycloneive_lcell_comb \vga_pic_inst|always0~2 ( +// Equation(s): +// \vga_pic_inst|always0~2_combout = (\vga_pic_inst|always0~1_combout ) # ((\vga_ctrl_inst|Add2~18_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (\vga_pic_inst|LessThan17~2_combout ))) + + .dataa(\vga_pic_inst|always0~1_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|LessThan17~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|always0~2 .lut_mask = 16'hFFFE; +defparam \vga_pic_inst|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N6 +cycloneive_lcell_comb \vga_pic_inst|pix_data[9]~14 ( +// Equation(s): +// \vga_pic_inst|pix_data[9]~14_combout = (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_ctrl_inst|Add2~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[9]~14_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9]~14 .lut_mask = 16'h00F0; +defparam \vga_pic_inst|pix_data[9]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~16 ( +// Equation(s): +// \vga_pic_inst|pix_data~16_combout = (\vga_pic_inst|always0~2_combout & (!\vga_pic_inst|pix_data[9]~15_combout & (!\vga_ctrl_inst|pix_x[11]~0_combout & \vga_pic_inst|pix_data[13]~9_combout ))) + + .dataa(\vga_pic_inst|always0~2_combout ), + .datab(\vga_pic_inst|pix_data[9]~15_combout ), + .datac(\vga_ctrl_inst|pix_x[11]~0_combout ), + .datad(\vga_pic_inst|pix_data[13]~9_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~16 .lut_mask = 16'h0200; +defparam \vga_pic_inst|pix_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~8 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~8_combout = (!\vga_ctrl_inst|cnt_v [11] & !\vga_ctrl_inst|cnt_v [10]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [11]), + .datac(\vga_ctrl_inst|cnt_v [10]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~8 .lut_mask = 16'h0303; +defparam \vga_ctrl_inst|pix_data_req~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[10]~12 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[10]~12_combout = (\vga_ctrl_inst|Add1~20_combout & (((!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|cnt_v [10])) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~20_combout & (!\vga_ctrl_inst|Equal0~3_combout +// & (\vga_ctrl_inst|cnt_v [10]))) + + .dataa(\vga_ctrl_inst|Add1~20_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [10]), + .datad(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[10]~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[10]~12 .lut_mask = 16'h30BA; +defparam \vga_ctrl_inst|cnt_v[10]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m[4]~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout = \hdmi_ctrl_inst|encode_inst0|data_in_reg [4] $ (\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m[4]~2 .lut_mask = 16'h3C3C; +defparam \hdmi_ctrl_inst|encode_inst0|q_m[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[6]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6]~6 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N23 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout = (\hdmi_ctrl_inst|encode_inst0|data_out [8] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out [8]), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4 .lut_mask = 16'hA0A0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N22 +cycloneive_lcell_comb \vga_pic_inst|LessThan10~0 ( +// Equation(s): +// \vga_pic_inst|LessThan10~0_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~16_combout & ((\vga_pic_inst|LessThan17~2_combout ) # (!\vga_ctrl_inst|Add2~14_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_pic_inst|LessThan17~2_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan10~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan10~0 .lut_mask = 16'h080A; +defparam \vga_pic_inst|LessThan10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data~22 ( +// Equation(s): +// \vga_pic_inst|pix_data~22_combout = (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_ctrl_inst|Add2~10_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~22 .lut_mask = 16'h00F0; +defparam \vga_pic_inst|pix_data~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~23 ( +// Equation(s): +// \vga_pic_inst|pix_data~23_combout = (!\vga_ctrl_inst|Add2~14_combout & (\vga_pic_inst|pix_data~22_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_ctrl_inst|Add2~12_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_pic_inst|pix_data~22_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~23_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~23 .lut_mask = 16'h0400; +defparam \vga_pic_inst|pix_data~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N20 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~1 ( +// Equation(s): +// \vga_pic_inst|LessThan14~1_combout = (\vga_ctrl_inst|Add2~12_combout & \vga_ctrl_inst|Add2~10_combout ) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~1 .lut_mask = 16'hAA00; +defparam \vga_pic_inst|LessThan14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~24 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~24_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_pic_inst|LessThan14~1_combout & (!\vga_ctrl_inst|Add2~16_combout & !\vga_ctrl_inst|Add2~14_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_pic_inst|LessThan14~1_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~24_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~24 .lut_mask = 16'h0002; +defparam \vga_pic_inst|pix_data[13]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N8 +cycloneive_lcell_comb \vga_pic_inst|pix_data~25 ( +// Equation(s): +// \vga_pic_inst|pix_data~25_combout = (!\vga_ctrl_inst|pix_x[10]~1_combout & ((\vga_pic_inst|pix_data~23_combout ) # ((\vga_pic_inst|LessThan10~0_combout & !\vga_pic_inst|pix_data[13]~24_combout )))) + + .dataa(\vga_pic_inst|LessThan10~0_combout ), + .datab(\vga_ctrl_inst|pix_x[10]~1_combout ), + .datac(\vga_pic_inst|pix_data[13]~24_combout ), + .datad(\vga_pic_inst|pix_data~23_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~25_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~25 .lut_mask = 16'h3302; +defparam \vga_pic_inst|pix_data~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|q_m[5]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout = \hdmi_ctrl_inst|encode_inst1|data_in_reg [4] $ (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m[5]~0 .lut_mask = 16'hC33C; +defparam \hdmi_ctrl_inst|encode_inst1|q_m[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[7] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~5_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [7] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [7]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~5 .lut_mask = 16'h9A56; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N9 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [9]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[9] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout = (\hdmi_ctrl_inst|encode_inst1|data_out [9] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [9]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4 .lut_mask = 16'hC0C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m[4]~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout = \hdmi_ctrl_inst|encode_inst2|data_in_reg [3] $ (\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m[4]~2 .lut_mask = 16'h33CC; +defparam \hdmi_ctrl_inst|encode_inst2|q_m[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N23 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout = (\hdmi_ctrl_inst|encode_inst2|data_out [8] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [8]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4 .lut_mask = 16'h8888; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~8_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~8 .lut_mask = 16'h8D8D; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|q_m[7]~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout = \hdmi_ctrl_inst|encode_inst1|data_in_reg [7] $ (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m[7]~1 .lut_mask = 16'hC33C; +defparam \hdmi_ctrl_inst|encode_inst1|q_m[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~6_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst2|c1_reg2~q $ +// ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~6 .lut_mask = 16'hEB41; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~8_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~8 .lut_mask = 16'hB1B1; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~37 ( +// Equation(s): +// \vga_pic_inst|pix_data~37_combout = ((!\vga_ctrl_inst|Add2~18_combout & (\vga_ctrl_inst|pix_data_req~7_combout & \vga_pic_inst|pix_data~23_combout ))) # (!\vga_pic_inst|pix_data~16_combout ) + + .dataa(\vga_pic_inst|pix_data~16_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data~23_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~37_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~37 .lut_mask = 16'h7555; +defparam \vga_pic_inst|pix_data~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~2_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~2_combout + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder .lut_mask = 16'hAAAA; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~2_combout + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder .lut_mask = 16'hAAAA; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~5_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~5_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~4_combout + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out~4_combout ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder .lut_mask = 16'hCCCC; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~5_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out~5_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~5_combout + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out~5_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder .lut_mask = 16'hAAAA; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N16 +cycloneive_io_obuf \ddc_scl~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(ddc_scl), + .obar()); +// synopsys translate_off +defparam \ddc_scl~output .bus_hold = "false"; +defparam \ddc_scl~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y10_N16 +cycloneive_io_obuf \ddc_sda~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(ddc_sda), + .obar()); +// synopsys translate_off +defparam \ddc_sda~output .bus_hold = "false"; +defparam \ddc_sda~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y21_N23 +cycloneive_io_obuf \tmds_clk_p~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_clk_p), + .obar()); +// synopsys translate_off +defparam \tmds_clk_p~output .bus_hold = "false"; +defparam \tmds_clk_p~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y20_N2 +cycloneive_io_obuf \tmds_clk_n~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_clk_n), + .obar()); +// synopsys translate_off +defparam \tmds_clk_n~output .bus_hold = "false"; +defparam \tmds_clk_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y22_N16 +cycloneive_io_obuf \tmds_data_p[0]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_p[0]), + .obar()); +// synopsys translate_off +defparam \tmds_data_p[0]~output .bus_hold = "false"; +defparam \tmds_data_p[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y23_N9 +cycloneive_io_obuf \tmds_data_p[1]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_p[1]), + .obar()); +// synopsys translate_off +defparam \tmds_data_p[1]~output .bus_hold = "false"; +defparam \tmds_data_p[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y24_N2 +cycloneive_io_obuf \tmds_data_p[2]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_p[2]), + .obar()); +// synopsys translate_off +defparam \tmds_data_p[2]~output .bus_hold = "false"; +defparam \tmds_data_p[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y22_N23 +cycloneive_io_obuf \tmds_data_n[0]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_n[0]), + .obar()); +// synopsys translate_off +defparam \tmds_data_n[0]~output .bus_hold = "false"; +defparam \tmds_data_n[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y23_N16 +cycloneive_io_obuf \tmds_data_n[1]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_n[1]), + .obar()); +// synopsys translate_off +defparam \tmds_data_n[1]~output .bus_hold = "false"; +defparam \tmds_data_n[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y24_N9 +cycloneive_io_obuf \tmds_data_n[2]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_n[2]), + .obar()); +// synopsys translate_off +defparam \tmds_data_n[2]~output .bus_hold = "false"; +defparam \tmds_data_n[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout = (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0 .lut_mask = 16'h0303; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout = \hdmi_ctrl_inst|par_to_ser_inst0|cnt [1] $ (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N19 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout = \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] $ (((\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0 .lut_mask = 16'h3CF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N17 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [1] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [1]), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0 .lut_mask = 16'h00AA; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout = \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N31 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) # (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [4]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [4]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3 .lut_mask = 16'hFCFC; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N5 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2 .lut_mask = 16'h00F0; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [2] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N29 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [1] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [1]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N23 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y21_N25 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y20_N4 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~0 ( +// Equation(s): +// \vga_ctrl_inst|Add0~0_combout = \vga_ctrl_inst|cnt_h [0] $ (VCC) +// \vga_ctrl_inst|Add0~1 = CARRY(\vga_ctrl_inst|cnt_h [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add0~0_combout ), + .cout(\vga_ctrl_inst|Add0~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y26_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X40_Y26_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y26_N18 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) # (!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q )) # (!\sys_rst_n~input_o ) + + .dataa(\sys_rst_n~input_o ), + .datab(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .datac(gnd), + .datad(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h77FF; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G7 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X37_Y20_N9 +dffeas \vga_ctrl_inst|cnt_h[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~4 ( +// Equation(s): +// \vga_ctrl_inst|Add0~4_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|Add0~3 $ (GND))) # (!\vga_ctrl_inst|cnt_h [2] & (!\vga_ctrl_inst|Add0~3 & VCC)) +// \vga_ctrl_inst|Add0~5 = CARRY((\vga_ctrl_inst|cnt_h [2] & !\vga_ctrl_inst|Add0~3 )) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~3 ), + .combout(\vga_ctrl_inst|Add0~4_combout ), + .cout(\vga_ctrl_inst|Add0~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~6 ( +// Equation(s): +// \vga_ctrl_inst|Add0~6_combout = (\vga_ctrl_inst|cnt_h [3] & (!\vga_ctrl_inst|Add0~5 )) # (!\vga_ctrl_inst|cnt_h [3] & ((\vga_ctrl_inst|Add0~5 ) # (GND))) +// \vga_ctrl_inst|Add0~7 = CARRY((!\vga_ctrl_inst|Add0~5 ) # (!\vga_ctrl_inst|cnt_h [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~5 ), + .combout(\vga_ctrl_inst|Add0~6_combout ), + .cout(\vga_ctrl_inst|Add0~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N15 +dffeas \vga_ctrl_inst|cnt_h[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~8 ( +// Equation(s): +// \vga_ctrl_inst|Add0~8_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Add0~7 $ (GND))) # (!\vga_ctrl_inst|cnt_h [4] & (!\vga_ctrl_inst|Add0~7 & VCC)) +// \vga_ctrl_inst|Add0~9 = CARRY((\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add0~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~7 ), + .combout(\vga_ctrl_inst|Add0~8_combout ), + .cout(\vga_ctrl_inst|Add0~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N17 +dffeas \vga_ctrl_inst|cnt_h[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~12 ( +// Equation(s): +// \vga_ctrl_inst|Add0~12_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add0~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add0~11 & VCC)) +// \vga_ctrl_inst|Add0~13 = CARRY((\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add0~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~11 ), + .combout(\vga_ctrl_inst|Add0~12_combout ), + .cout(\vga_ctrl_inst|Add0~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N21 +dffeas \vga_ctrl_inst|cnt_h[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~14 ( +// Equation(s): +// \vga_ctrl_inst|Add0~14_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add0~13 )) # (!\vga_ctrl_inst|cnt_h [7] & ((\vga_ctrl_inst|Add0~13 ) # (GND))) +// \vga_ctrl_inst|Add0~15 = CARRY((!\vga_ctrl_inst|Add0~13 ) # (!\vga_ctrl_inst|cnt_h [7])) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~13 ), + .combout(\vga_ctrl_inst|Add0~14_combout ), + .cout(\vga_ctrl_inst|Add0~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N23 +dffeas \vga_ctrl_inst|cnt_h[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y20_N13 +dffeas \vga_ctrl_inst|cnt_h[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~0 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~0_combout = (\vga_ctrl_inst|cnt_h [1] & (\vga_ctrl_inst|cnt_h [3] & (\vga_ctrl_inst|cnt_h [0] & \vga_ctrl_inst|cnt_h [2]))) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(\vga_ctrl_inst|cnt_h [0]), + .datad(\vga_ctrl_inst|cnt_h [2]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~0 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~16 ( +// Equation(s): +// \vga_ctrl_inst|Add0~16_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add0~15 $ (GND))) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add0~15 & VCC)) +// \vga_ctrl_inst|Add0~17 = CARRY((\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add0~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~15 ), + .combout(\vga_ctrl_inst|Add0~16_combout ), + .cout(\vga_ctrl_inst|Add0~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~18 ( +// Equation(s): +// \vga_ctrl_inst|Add0~18_combout = (\vga_ctrl_inst|cnt_h [9] & (!\vga_ctrl_inst|Add0~17 )) # (!\vga_ctrl_inst|cnt_h [9] & ((\vga_ctrl_inst|Add0~17 ) # (GND))) +// \vga_ctrl_inst|Add0~19 = CARRY((!\vga_ctrl_inst|Add0~17 ) # (!\vga_ctrl_inst|cnt_h [9])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [9]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~17 ), + .combout(\vga_ctrl_inst|Add0~18_combout ), + .cout(\vga_ctrl_inst|Add0~19 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~18 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~20 ( +// Equation(s): +// \vga_ctrl_inst|Add0~20_combout = (\vga_ctrl_inst|cnt_h [10] & (\vga_ctrl_inst|Add0~19 $ (GND))) # (!\vga_ctrl_inst|cnt_h [10] & (!\vga_ctrl_inst|Add0~19 & VCC)) +// \vga_ctrl_inst|Add0~21 = CARRY((\vga_ctrl_inst|cnt_h [10] & !\vga_ctrl_inst|Add0~19 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~19 ), + .combout(\vga_ctrl_inst|Add0~20_combout ), + .cout(\vga_ctrl_inst|Add0~21 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~20 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N29 +dffeas \vga_ctrl_inst|cnt_h[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[10] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~22 ( +// Equation(s): +// \vga_ctrl_inst|Add0~22_combout = \vga_ctrl_inst|cnt_h [11] $ (\vga_ctrl_inst|Add0~21 ) + + .dataa(\vga_ctrl_inst|cnt_h [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\vga_ctrl_inst|Add0~21 ), + .combout(\vga_ctrl_inst|Add0~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~22 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N31 +dffeas \vga_ctrl_inst|cnt_h[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [11]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[11] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~1 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~1_combout = (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|cnt_h [10] & (!\vga_ctrl_inst|cnt_h [11] & \vga_ctrl_inst|cnt_h [9]))) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(\vga_ctrl_inst|cnt_h [11]), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~1 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N24 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~0_combout = (\vga_ctrl_inst|Add0~10_combout & (((!\vga_ctrl_inst|Equal0~2_combout ) # (!\vga_ctrl_inst|Equal0~1_combout )) # (!\vga_ctrl_inst|Equal0~0_combout ))) + + .dataa(\vga_ctrl_inst|Add0~10_combout ), + .datab(\vga_ctrl_inst|Equal0~0_combout ), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~0 .lut_mask = 16'h2AAA; +defparam \vga_ctrl_inst|cnt_h~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y21_N25 +dffeas \vga_ctrl_inst|cnt_h[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~2 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~2_combout = (\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|cnt_h [5] & (\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [6]))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [5]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~2 .lut_mask = 16'h0020; +defparam \vga_ctrl_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~2_combout = (\vga_ctrl_inst|Add0~16_combout & (((!\vga_ctrl_inst|Equal0~2_combout ) # (!\vga_ctrl_inst|Equal0~0_combout )) # (!\vga_ctrl_inst|Equal0~1_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|Add0~16_combout ), + .datac(\vga_ctrl_inst|Equal0~0_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~2 .lut_mask = 16'h4CCC; +defparam \vga_ctrl_inst|cnt_h~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y20_N3 +dffeas \vga_ctrl_inst|cnt_h[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~1_combout = (\vga_ctrl_inst|Add0~18_combout & (((!\vga_ctrl_inst|Equal0~2_combout ) # (!\vga_ctrl_inst|Equal0~0_combout )) # (!\vga_ctrl_inst|Equal0~1_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|Equal0~0_combout ), + .datac(\vga_ctrl_inst|Add0~18_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~1 .lut_mask = 16'h70F0; +defparam \vga_ctrl_inst|cnt_h~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y20_N1 +dffeas \vga_ctrl_inst|cnt_h[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan4~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan4~0_combout = (!\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [6])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [5]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan4~0 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add4~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add4~0_combout = (\vga_ctrl_inst|cnt_h [8] & (((!\vga_ctrl_inst|cnt_h [7] & \vga_ctrl_inst|LessThan4~0_combout )) # (!\vga_ctrl_inst|cnt_h [9]))) # (!\vga_ctrl_inst|cnt_h [8] & ((\vga_ctrl_inst|cnt_h [9]) # +// ((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|LessThan4~0_combout )))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(\vga_ctrl_inst|LessThan4~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add4~0 .lut_mask = 16'h7A5E; +defparam \hdmi_ctrl_inst|encode_inst0|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~1 ( +// Equation(s): +// \vga_ctrl_inst|Add2~1_cout = CARRY((\vga_ctrl_inst|cnt_h [1] & \vga_ctrl_inst|cnt_h [0])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\vga_ctrl_inst|Add2~1_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~1 .lut_mask = 16'h0088; +defparam \vga_ctrl_inst|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~3 ( +// Equation(s): +// \vga_ctrl_inst|Add2~3_cout = CARRY((!\vga_ctrl_inst|Add2~1_cout ) # (!\vga_ctrl_inst|cnt_h [2])) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~1_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~3_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~3 .lut_mask = 16'h005F; +defparam \vga_ctrl_inst|Add2~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~5 ( +// Equation(s): +// \vga_ctrl_inst|Add2~5_cout = CARRY((\vga_ctrl_inst|cnt_h [3] & !\vga_ctrl_inst|Add2~3_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~3_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~5_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~5 .lut_mask = 16'h000A; +defparam \vga_ctrl_inst|Add2~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~7 ( +// Equation(s): +// \vga_ctrl_inst|Add2~7_cout = CARRY((!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add2~5_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~5_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~7_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~7 .lut_mask = 16'h0005; +defparam \vga_ctrl_inst|Add2~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~9 ( +// Equation(s): +// \vga_ctrl_inst|Add2~9_cout = CARRY((\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|Add2~7_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [5]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~7_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~9_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~9 .lut_mask = 16'h00CF; +defparam \vga_ctrl_inst|Add2~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~10 ( +// Equation(s): +// \vga_ctrl_inst|Add2~10_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add2~9_cout & VCC)) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add2~9_cout )) +// \vga_ctrl_inst|Add2~11 = CARRY((!\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add2~9_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~9_cout ), + .combout(\vga_ctrl_inst|Add2~10_combout ), + .cout(\vga_ctrl_inst|Add2~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~10 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~12 ( +// Equation(s): +// \vga_ctrl_inst|Add2~12_combout = (\vga_ctrl_inst|cnt_h [7] & (\vga_ctrl_inst|Add2~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add2~11 & VCC)) +// \vga_ctrl_inst|Add2~13 = CARRY((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|Add2~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~11 ), + .combout(\vga_ctrl_inst|Add2~12_combout ), + .cout(\vga_ctrl_inst|Add2~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~14 ( +// Equation(s): +// \vga_ctrl_inst|Add2~14_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add2~13 & VCC)) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add2~13 )) +// \vga_ctrl_inst|Add2~15 = CARRY((!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add2~13 )) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~13 ), + .combout(\vga_ctrl_inst|Add2~14_combout ), + .cout(\vga_ctrl_inst|Add2~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~14 .lut_mask = 16'hA505; +defparam \vga_ctrl_inst|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~16 ( +// Equation(s): +// \vga_ctrl_inst|Add2~16_combout = (\vga_ctrl_inst|cnt_h [9] & ((GND) # (!\vga_ctrl_inst|Add2~15 ))) # (!\vga_ctrl_inst|cnt_h [9] & (\vga_ctrl_inst|Add2~15 $ (GND))) +// \vga_ctrl_inst|Add2~17 = CARRY((\vga_ctrl_inst|cnt_h [9]) # (!\vga_ctrl_inst|Add2~15 )) + + .dataa(\vga_ctrl_inst|cnt_h [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~15 ), + .combout(\vga_ctrl_inst|Add2~16_combout ), + .cout(\vga_ctrl_inst|Add2~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~16 .lut_mask = 16'h5AAF; +defparam \vga_ctrl_inst|Add2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~18 ( +// Equation(s): +// \vga_ctrl_inst|Add2~18_combout = (\vga_ctrl_inst|cnt_h [10] & (\vga_ctrl_inst|Add2~17 & VCC)) # (!\vga_ctrl_inst|cnt_h [10] & (!\vga_ctrl_inst|Add2~17 )) +// \vga_ctrl_inst|Add2~19 = CARRY((!\vga_ctrl_inst|cnt_h [10] & !\vga_ctrl_inst|Add2~17 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~17 ), + .combout(\vga_ctrl_inst|Add2~18_combout ), + .cout(\vga_ctrl_inst|Add2~19 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~18 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~12 ( +// Equation(s): +// \vga_pic_inst|pix_data~12_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~18_combout & (\vga_ctrl_inst|Add2~16_combout & !\vga_ctrl_inst|Add2~14_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~12 .lut_mask = 16'h0020; +defparam \vga_pic_inst|pix_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~5 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~5_combout = \vga_ctrl_inst|cnt_h [8] $ (\vga_ctrl_inst|cnt_h [9]) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~5 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|pix_data_req~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N2 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~3 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~3_combout = (\vga_ctrl_inst|Equal0~1_combout & (\vga_ctrl_inst|Equal0~0_combout & \vga_ctrl_inst|Equal0~2_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Equal0~1_combout ), + .datac(\vga_ctrl_inst|Equal0~0_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~3 .lut_mask = 16'hC000; +defparam \vga_ctrl_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[7]~7 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[7]~7_combout = (\vga_ctrl_inst|Add1~14_combout & (((\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~14_combout & (((\vga_ctrl_inst|cnt_v [7] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~14_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7]~7 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N21 +dffeas \vga_ctrl_inst|cnt_v[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[7]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[5]~10 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[5]~10_combout = (\vga_ctrl_inst|Add1~10_combout & (((!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|cnt_v [5])) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~10_combout & (!\vga_ctrl_inst|Equal0~3_combout +// & (\vga_ctrl_inst|cnt_v [5]))) + + .dataa(\vga_ctrl_inst|Add1~10_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5]~10 .lut_mask = 16'h30BA; +defparam \vga_ctrl_inst|cnt_v[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N27 +dffeas \vga_ctrl_inst|cnt_v[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[5]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[8]~6 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[8]~6_combout = (\vga_ctrl_inst|Add1~16_combout & (((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~16_combout & (((\vga_ctrl_inst|cnt_v [8] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~16_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [8]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[8]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8]~6 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[8]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N19 +dffeas \vga_ctrl_inst|cnt_v[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[8]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|always1~0 ( +// Equation(s): +// \vga_ctrl_inst|always1~0_combout = (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|cnt_v [5] & !\vga_ctrl_inst|cnt_v [8]))) + + .dataa(\vga_ctrl_inst|cnt_v [6]), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|cnt_v [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[1]~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[1]~1_combout = (\vga_ctrl_inst|Add1~2_combout & (((\vga_ctrl_inst|cnt_v [1] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~2_combout & (((\vga_ctrl_inst|cnt_v [1] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~2_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1]~1 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N9 +dffeas \vga_ctrl_inst|cnt_v[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[1]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[4]~5 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[4]~5_combout = (\vga_ctrl_inst|Add1~8_combout & (((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~8_combout & (((\vga_ctrl_inst|cnt_v [4] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~8_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [4]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4]~5 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N1 +dffeas \vga_ctrl_inst|cnt_v[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[4]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N24 +cycloneive_lcell_comb \vga_ctrl_inst|always1~1 ( +// Equation(s): +// \vga_ctrl_inst|always1~1_combout = (\vga_ctrl_inst|pix_data_req~8_combout & (\vga_ctrl_inst|always1~0_combout & (!\vga_ctrl_inst|cnt_v [1] & !\vga_ctrl_inst|cnt_v [4]))) + + .dataa(\vga_ctrl_inst|pix_data_req~8_combout ), + .datab(\vga_ctrl_inst|always1~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~1 .lut_mask = 16'h0008; +defparam \vga_ctrl_inst|always1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~0 ( +// Equation(s): +// \vga_ctrl_inst|Add1~0_combout = \vga_ctrl_inst|cnt_v [0] $ (VCC) +// \vga_ctrl_inst|Add1~1 = CARRY(\vga_ctrl_inst|cnt_v [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add1~0_combout ), + .cout(\vga_ctrl_inst|Add1~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[0]~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[0]~2_combout = (\vga_ctrl_inst|cnt_v[11]~0_combout & (((\vga_ctrl_inst|cnt_v [0] & !\vga_ctrl_inst|Equal0~3_combout )))) # (!\vga_ctrl_inst|cnt_v[11]~0_combout & ((\vga_ctrl_inst|Add1~0_combout ) # ((\vga_ctrl_inst|cnt_v [0] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datab(\vga_ctrl_inst|Add1~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0]~2 .lut_mask = 16'h44F4; +defparam \vga_ctrl_inst|cnt_v[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N1 +dffeas \vga_ctrl_inst|cnt_v[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[0]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[3]~3 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[3]~3_combout = (\vga_ctrl_inst|Add1~6_combout & (((\vga_ctrl_inst|cnt_v [3] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~6_combout & (((\vga_ctrl_inst|cnt_v [3] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~6_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3]~3 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N3 +dffeas \vga_ctrl_inst|cnt_v[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[3]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|always1~2 ( +// Equation(s): +// \vga_ctrl_inst|always1~2_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [0] & \vga_ctrl_inst|cnt_v [3]))) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|cnt_v [3]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~2 .lut_mask = 16'h0800; +defparam \vga_ctrl_inst|always1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[11]~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[11]~0_combout = ((\vga_ctrl_inst|always1~1_combout & \vga_ctrl_inst|always1~2_combout )) # (!\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|always1~1_combout ), + .datac(\vga_ctrl_inst|always1~2_combout ), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[11]~0 .lut_mask = 16'hC0FF; +defparam \vga_ctrl_inst|cnt_v[11]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[9]~9 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[9]~9_combout = (\vga_ctrl_inst|Add1~18_combout & (((\vga_ctrl_inst|cnt_v [9] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~18_combout & (((\vga_ctrl_inst|cnt_v [9] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~18_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9]~9 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N17 +dffeas \vga_ctrl_inst|cnt_v[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[9]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[6]~8 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[6]~8_combout = (\vga_ctrl_inst|Add1~12_combout & (((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~12_combout & (((\vga_ctrl_inst|cnt_v [6] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~12_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6]~8 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N23 +dffeas \vga_ctrl_inst|cnt_v[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[6]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~4 ( +// Equation(s): +// \vga_ctrl_inst|Add1~4_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|Add1~3 $ (GND))) # (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|Add1~3 & VCC)) +// \vga_ctrl_inst|Add1~5 = CARRY((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Add1~3 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [2]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~3 ), + .combout(\vga_ctrl_inst|Add1~4_combout ), + .cout(\vga_ctrl_inst|Add1~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~4 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[2]~4 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[2]~4_combout = (\vga_ctrl_inst|cnt_v[11]~0_combout & (((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Equal0~3_combout )))) # (!\vga_ctrl_inst|cnt_v[11]~0_combout & ((\vga_ctrl_inst|Add1~4_combout ) # ((\vga_ctrl_inst|cnt_v [2] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datab(\vga_ctrl_inst|Add1~4_combout ), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2]~4 .lut_mask = 16'h44F4; +defparam \vga_ctrl_inst|cnt_v[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N13 +dffeas \vga_ctrl_inst|cnt_v[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[2]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~22 ( +// Equation(s): +// \vga_ctrl_inst|Add1~22_combout = \vga_ctrl_inst|Add1~21 $ (\vga_ctrl_inst|cnt_v [11]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [11]), + .cin(\vga_ctrl_inst|Add1~21 ), + .combout(\vga_ctrl_inst|Add1~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~22 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add1~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[11]~11 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[11]~11_combout = (\vga_ctrl_inst|cnt_v[11]~0_combout & (((\vga_ctrl_inst|cnt_v [11] & !\vga_ctrl_inst|Equal0~3_combout )))) # (!\vga_ctrl_inst|cnt_v[11]~0_combout & ((\vga_ctrl_inst|Add1~22_combout ) # ((\vga_ctrl_inst|cnt_v [11] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datab(\vga_ctrl_inst|Add1~22_combout ), + .datac(\vga_ctrl_inst|cnt_v [11]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[11]~11 .lut_mask = 16'h44F4; +defparam \vga_ctrl_inst|cnt_v[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N29 +dffeas \vga_ctrl_inst|cnt_v[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[11]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [11]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[11] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~2 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~2_combout = (!\vga_ctrl_inst|cnt_v [10] & (!\vga_ctrl_inst|cnt_v [11] & (!\vga_ctrl_inst|cnt_h [11] & !\vga_ctrl_inst|cnt_h [10]))) + + .dataa(\vga_ctrl_inst|cnt_v [10]), + .datab(\vga_ctrl_inst|cnt_v [11]), + .datac(\vga_ctrl_inst|cnt_h [11]), + .datad(\vga_ctrl_inst|cnt_h [10]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~2 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~4 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~4_combout = (\vga_ctrl_inst|pix_data_req~2_combout & ((\vga_ctrl_inst|always1~0_combout ) # (!\vga_ctrl_inst|cnt_v [9]))) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|pix_data_req~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~4 .lut_mask = 16'hAF00; +defparam \vga_ctrl_inst|pix_data_req~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~6 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~6_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|cnt_h [9] & ((\vga_ctrl_inst|Equal0~0_combout ) # (!\vga_ctrl_inst|LessThan4~0_combout )))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Equal0~0_combout & +// (\vga_ctrl_inst|cnt_h [9] & \vga_ctrl_inst|LessThan4~0_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(\vga_ctrl_inst|LessThan4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~6 .lut_mask = 16'h180C; +defparam \vga_ctrl_inst|pix_data_req~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~7 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~7_combout = (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|pix_data_req~5_combout ) # (\vga_ctrl_inst|pix_data_req~6_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~1_combout ), + .datab(\vga_ctrl_inst|pix_data_req~5_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|pix_data_req~6_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~7 .lut_mask = 16'hA080; +defparam \vga_ctrl_inst|pix_data_req~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~11 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~11_combout = ((\vga_ctrl_inst|Add2~16_combout ) # ((\vga_ctrl_inst|Add2~14_combout & \vga_ctrl_inst|Add2~12_combout ))) # (!\vga_ctrl_inst|pix_data_req~7_combout ) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|pix_data_req~7_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~11 .lut_mask = 16'hFBF3; +defparam \vga_pic_inst|pix_data[13]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N6 +cycloneive_lcell_comb \vga_pic_inst|always0~0 ( +// Equation(s): +// \vga_pic_inst|always0~0_combout = (\vga_ctrl_inst|Add2~16_combout ) # ((\vga_ctrl_inst|Add2~18_combout ) # ((!\vga_pic_inst|pix_data[13]~11_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ))) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[13]~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|always0~0 .lut_mask = 16'hEFFF; +defparam \vga_pic_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~13 ( +// Equation(s): +// \vga_pic_inst|pix_data~13_combout = (\vga_pic_inst|LessThan14~0_combout & (((\vga_ctrl_inst|Add2~12_combout )) # (!\vga_pic_inst|pix_data~12_combout ))) # (!\vga_pic_inst|LessThan14~0_combout & (\vga_pic_inst|always0~0_combout & +// ((\vga_ctrl_inst|Add2~12_combout ) # (!\vga_pic_inst|pix_data~12_combout )))) + + .dataa(\vga_pic_inst|LessThan14~0_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_ctrl_inst|Add2~12_combout ), + .datad(\vga_pic_inst|always0~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~13 .lut_mask = 16'hF3A2; +defparam \vga_pic_inst|pix_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~17 ( +// Equation(s): +// \vga_pic_inst|pix_data~17_combout = (!\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_ctrl_inst|Add2~12_combout )) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~17_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~17 .lut_mask = 16'h0500; +defparam \vga_pic_inst|pix_data~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N10 +cycloneive_lcell_comb \vga_pic_inst|pix_data~34 ( +// Equation(s): +// \vga_pic_inst|pix_data~34_combout = ((!\vga_ctrl_inst|Add2~18_combout & (\vga_ctrl_inst|pix_data_req~7_combout & \vga_pic_inst|pix_data~17_combout ))) # (!\vga_pic_inst|pix_data~16_combout ) + + .dataa(\vga_pic_inst|pix_data~16_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data~17_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~34_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~34 .lut_mask = 16'h7555; +defparam \vga_pic_inst|pix_data~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N16 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~8 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~8_combout = (!\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|Add2~14_combout ) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~8 .lut_mask = 16'h55FF; +defparam \vga_pic_inst|pix_data[13]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~9 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~9_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~18_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_pic_inst|pix_data[13]~8_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|pix_data[13]~8_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~9 .lut_mask = 16'h0200; +defparam \vga_pic_inst|pix_data[13]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~10 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~10_combout = (!\vga_ctrl_inst|Add2~20_combout & (\vga_ctrl_inst|pix_data_req~7_combout & \vga_pic_inst|pix_data[13]~9_combout )) + + .dataa(\vga_ctrl_inst|Add2~20_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[13]~9_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~10 .lut_mask = 16'h5000; +defparam \vga_pic_inst|pix_data[13]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N8 +cycloneive_lcell_comb \vga_pic_inst|pix_data~18 ( +// Equation(s): +// \vga_pic_inst|pix_data~18_combout = ((!\vga_ctrl_inst|pix_x[11]~0_combout & (!\vga_pic_inst|pix_data~13_combout & !\vga_pic_inst|pix_data[13]~10_combout ))) # (!\vga_pic_inst|pix_data~34_combout ) + + .dataa(\vga_ctrl_inst|pix_x[11]~0_combout ), + .datab(\vga_pic_inst|pix_data~13_combout ), + .datac(\vga_pic_inst|pix_data~34_combout ), + .datad(\vga_pic_inst|pix_data[13]~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~18 .lut_mask = 16'h0F1F; +defparam \vga_pic_inst|pix_data~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N9 +dffeas \vga_pic_inst|pix_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~20 ( +// Equation(s): +// \vga_ctrl_inst|Add2~20_combout = \vga_ctrl_inst|Add2~19 $ (\vga_ctrl_inst|cnt_h [11]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [11]), + .cin(\vga_ctrl_inst|Add2~19 ), + .combout(\vga_ctrl_inst|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~20 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add2~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N28 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~4 ( +// Equation(s): +// \vga_pic_inst|LessThan17~4_combout = (!\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~10_combout & (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_ctrl_inst|Add2~12_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~4 .lut_mask = 16'h0010; +defparam \vga_pic_inst|LessThan17~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N20 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~3 ( +// Equation(s): +// \vga_pic_inst|LessThan17~3_combout = (!\vga_ctrl_inst|Add2~18_combout & (!\vga_ctrl_inst|Add2~20_combout & (\vga_ctrl_inst|Add2~16_combout & \vga_pic_inst|LessThan17~4_combout ))) + + .dataa(\vga_ctrl_inst|Add2~18_combout ), + .datab(\vga_ctrl_inst|Add2~20_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|LessThan17~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~3 .lut_mask = 16'h1000; +defparam \vga_pic_inst|LessThan17~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N14 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~0 ( +// Equation(s): +// \vga_pic_inst|LessThan14~0_combout = (\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~10_combout & \vga_ctrl_inst|Add2~12_combout )) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~10_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~0 .lut_mask = 16'hA000; +defparam \vga_pic_inst|LessThan14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~19 ( +// Equation(s): +// \vga_pic_inst|pix_data~19_combout = (\vga_pic_inst|LessThan17~3_combout ) # ((!\vga_ctrl_inst|pix_x[11]~0_combout & (!\vga_pic_inst|LessThan14~0_combout & !\vga_pic_inst|always0~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_x[11]~0_combout ), + .datab(\vga_pic_inst|LessThan17~3_combout ), + .datac(\vga_pic_inst|LessThan14~0_combout ), + .datad(\vga_pic_inst|always0~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~19_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~19 .lut_mask = 16'hCCCD; +defparam \vga_pic_inst|pix_data~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~20 ( +// Equation(s): +// \vga_pic_inst|pix_data~20_combout = ((!\vga_pic_inst|pix_data[13]~10_combout & \vga_pic_inst|pix_data~19_combout )) # (!\vga_pic_inst|pix_data~34_combout ) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data[13]~10_combout ), + .datac(\vga_pic_inst|pix_data~34_combout ), + .datad(\vga_pic_inst|pix_data~19_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~20 .lut_mask = 16'h3F0F; +defparam \vga_pic_inst|pix_data~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N19 +dffeas \vga_pic_inst|pix_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[0] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add6~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add6~0_combout = (\vga_ctrl_inst|pix_data_req~3_combout & (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_pic_inst|pix_data [4] & \vga_pic_inst|pix_data [0]))) + + .dataa(\vga_ctrl_inst|pix_data_req~3_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datac(\vga_pic_inst|pix_data [4]), + .datad(\vga_pic_inst|pix_data [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add6~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add6~0 .lut_mask = 16'h8000; +defparam \hdmi_ctrl_inst|encode_inst0|Add6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|data_in_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_in_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_in_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout = !\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0 .lut_mask = 16'h00FF; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N21 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y22_N27 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~0_combout = (!\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|cnt_v [2] & ((!\vga_ctrl_inst|cnt_v [1]) # (!\vga_ctrl_inst|cnt_v [0])))) + + .dataa(\vga_ctrl_inst|cnt_v [0]), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|cnt_v [2]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~0 .lut_mask = 16'h0013; +defparam \vga_ctrl_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~1_combout = (\vga_ctrl_inst|LessThan6~0_combout & ((\vga_ctrl_inst|cnt_v [4] & ((!\vga_ctrl_inst|always1~0_combout ))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|pix_data_req~0_combout )))) # +// (!\vga_ctrl_inst|LessThan6~0_combout & (((!\vga_ctrl_inst|always1~0_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~0_combout ), + .datab(\vga_ctrl_inst|always1~0_combout ), + .datac(\vga_ctrl_inst|LessThan6~0_combout ), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~1 .lut_mask = 16'h3353; +defparam \vga_ctrl_inst|pix_data_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N28 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[1]~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb[1]~0_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_pic_inst|pix_data [4] & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_pic_inst|pix_data [4]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[1]~0 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N29 +dffeas \hdmi_ctrl_inst|encode_inst0|data_in_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N30 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[2]~1 ( +// Equation(s): +// \vga_ctrl_inst|rgb[2]~1_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~1_combout & \vga_pic_inst|pix_data [0]))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\vga_pic_inst|pix_data [0]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[2]~1 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N31 +dffeas \hdmi_ctrl_inst|encode_inst0|data_in_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[2]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add14~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add14~0_combout = (\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]) # ((\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]) # (\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add14~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add14~0 .lut_mask = 16'hFFFC; +defparam \hdmi_ctrl_inst|encode_inst0|Add14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout = !\hdmi_ctrl_inst|encode_inst0|Add14~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|Add14~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0 .lut_mask = 16'h00FF; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N9 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n0[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add19~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [1] & \hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add19~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~2_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [2] & (!\hdmi_ctrl_inst|encode_inst0|Add19~1 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst0|Add19~1 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add19~3 = CARRY((!\hdmi_ctrl_inst|encode_inst0|Add19~1 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [2])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add19~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add19~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~2 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~6_combout = \hdmi_ctrl_inst|encode_inst0|cnt [4] $ (\hdmi_ctrl_inst|encode_inst0|Add19~5 ) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add19~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~6 .lut_mask = 16'h3C3C; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [1] & ((\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]) # (GND))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] $ (VCC))) +// \hdmi_ctrl_inst|encode_inst0|Add22~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [1]) # (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add22~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~0 .lut_mask = 16'h99EE; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~2_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|Add22~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [2] & (!\hdmi_ctrl_inst|encode_inst0|Add22~1 )) +// \hdmi_ctrl_inst|encode_inst0|Add22~3 = CARRY((!\hdmi_ctrl_inst|encode_inst0|cnt [2] & !\hdmi_ctrl_inst|encode_inst0|Add22~1 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add22~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add22~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~2 .lut_mask = 16'hA505; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~6_combout = \hdmi_ctrl_inst|encode_inst0|Add22~5 $ (!\hdmi_ctrl_inst|encode_inst0|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst0|Add22~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~6 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~2_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout ) # ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst0|Add19~6_combout )) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst0|Add22~6_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add19~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add22~6_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~2 .lut_mask = 16'hFBEA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[0]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0]~0 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N17 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n0[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add14~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~9_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add22~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add22~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~9_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~9 .lut_mask = 16'hAF44; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~10 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~10_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~9_combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2])) # (!\hdmi_ctrl_inst|encode_inst0|Add16~9_combout & +// ((\hdmi_ctrl_inst|encode_inst0|Add19~2_combout ))))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|Add16~9_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|Add19~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add16~9_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~10_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~10 .lut_mask = 16'h5FC0; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add12~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add12~0_combout = (\hdmi_ctrl_inst|encode_inst0|data_in_reg [3] & ((!\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]))) # (!\hdmi_ctrl_inst|encode_inst0|data_in_reg [3] & (\hdmi_ctrl_inst|encode_inst0|data_in_reg [4])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add12~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add12~0 .lut_mask = 16'h0CFC; +defparam \hdmi_ctrl_inst|encode_inst0|Add12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N29 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n1[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add12~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add14~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add14~1_combout = (\hdmi_ctrl_inst|encode_inst0|data_in_reg [3] & (\hdmi_ctrl_inst|encode_inst0|data_in_reg [4] $ (!\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add14~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add14~1 .lut_mask = 16'hC030; +defparam \hdmi_ctrl_inst|encode_inst0|Add14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N19 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n0[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add14~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~13_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add22~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add22~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~13_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~13 .lut_mask = 16'hAF44; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~14 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~14_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~13_combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~13_combout & +// (\hdmi_ctrl_inst|encode_inst0|Add19~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|Add16~13_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add19~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add16~13_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~14_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~14 .lut_mask = 16'h5F88; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y22_N1 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n1[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~15_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] & ((\hdmi_ctrl_inst|encode_inst0|Add17~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] & +// (\hdmi_ctrl_inst|encode_inst0|Add15~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add17~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~15 .lut_mask = 16'hA088; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal2~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])))) # +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~0 .lut_mask = 16'h8421; +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal2~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal2~1_combout = (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~1 .lut_mask = 16'h0F00; +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[0]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout = CARRY((\hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ) # (\hdmi_ctrl_inst|encode_inst0|Equal2~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Equal2~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~6 .lut_mask = 16'h00EE; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[3]~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout = ((\hdmi_ctrl_inst|encode_inst0|Add16~4_combout $ (\hdmi_ctrl_inst|encode_inst0|Add16~6_combout $ (!\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|cnt[3]~14 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~4_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~6_combout ) # (!\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~4_combout & +// (\hdmi_ctrl_inst|encode_inst0|Add16~6_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[3]~14 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3]~13 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add4~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add4~1_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout )) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add4~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add4~1 .lut_mask = 16'hA000; +defparam \hdmi_ctrl_inst|encode_inst0|Add4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N17 +dffeas \hdmi_ctrl_inst|encode_inst2|de_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add4~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|de_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|de_reg1 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|de_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout = \hdmi_ctrl_inst|encode_inst2|de_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|de_reg1~q ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N1 +dffeas \hdmi_ctrl_inst|encode_inst2|de_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N13 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_2~combout = (\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout & (((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3]))) # +// (!\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_2 .lut_mask = 16'h3B0A; +defparam \hdmi_ctrl_inst|encode_inst0|condition_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~6_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~5_combout ) # ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~5_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~6 .lut_mask = 16'hBFAA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[4]~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout = \hdmi_ctrl_inst|encode_inst0|Add16~1_combout $ (\hdmi_ctrl_inst|encode_inst0|cnt[3]~14 $ (\hdmi_ctrl_inst|encode_inst0|Add16~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|Add16~2_combout ), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[3]~14 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4]~15 .lut_mask = 16'hA55A; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X38_Y22_N15 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_3~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_3~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & \hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]))) # +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]) # ((!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & \hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~0 .lut_mask = 16'h7150; +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_3~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_3~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (((\hdmi_ctrl_inst|encode_inst0|cnt [4])))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|cnt [4] & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [4] & (\hdmi_ctrl_inst|encode_inst0|condition_3~1_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~2 .lut_mask = 16'hF2C2; +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~1_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [1] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_reg [1]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~1 .lut_mask = 16'h87D2; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~1_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~0_combout = (\vga_ctrl_inst|cnt_h [7]) # ((\vga_ctrl_inst|cnt_h [10]) # ((\vga_ctrl_inst|cnt_h [9]) # (\vga_ctrl_inst|cnt_h [11]))) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(\vga_ctrl_inst|cnt_h [11]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~0 .lut_mask = 16'hFFFE; +defparam \vga_ctrl_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~1_combout = (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|LessThan0~0_combout & ((!\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|cnt_h [6])))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|cnt_h [5]), + .datad(\vga_ctrl_inst|LessThan0~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~1 .lut_mask = 16'h0015; +defparam \vga_ctrl_inst|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y20_N27 +dffeas \hdmi_ctrl_inst|encode_inst2|c0_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|LessThan0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c0_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg1 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y20_N25 +dffeas \hdmi_ctrl_inst|encode_inst2|c0_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y22_N9 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m[7]~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout = \hdmi_ctrl_inst|encode_inst0|data_in_reg [4] $ (\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m[7]~1 .lut_mask = 16'h33CC; +defparam \hdmi_ctrl_inst|encode_inst0|q_m[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N25 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~4_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [5] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_reg [5]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~4 .lut_mask = 16'hC35A; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N29 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan1~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan1~0_combout = (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [3] & \vga_ctrl_inst|always1~1_combout ))) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|always1~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan1~0 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|LessThan1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N15 +dffeas \hdmi_ctrl_inst|encode_inst2|c1_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|LessThan1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c1_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg1 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout = \hdmi_ctrl_inst|encode_inst2|c1_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|c1_reg1~q ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N5 +dffeas \hdmi_ctrl_inst|encode_inst2|c1_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~7_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst2|c0_reg2~q $ +// (!\hdmi_ctrl_inst|encode_inst2|c1_reg2~q )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~7 .lut_mask = 16'hACA3; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N5 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [9]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[9] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout = (\hdmi_ctrl_inst|encode_inst0|data_out [9] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [9]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4 .lut_mask = 16'hC0C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N1 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [3]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N7 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out [3]), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1 .lut_mask = 16'hAFA0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [1])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [1]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y22_N25 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~3_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~3 .lut_mask = 16'hA3A3; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N17 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst0|data_out [2]))) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [2])) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1 .lut_mask = 16'hCACA; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N21 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [0])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_out [0]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0 .lut_mask = 16'hF3C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N9 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y22_N18 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N16 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~2 ( +// Equation(s): +// \vga_pic_inst|LessThan17~2_combout = (!\vga_ctrl_inst|Add2~12_combout & (!\vga_ctrl_inst|Add2~10_combout & \vga_ctrl_inst|pix_data_req~7_combout )) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~2 .lut_mask = 16'h1010; +defparam \vga_pic_inst|LessThan17~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data[9]~15 ( +// Equation(s): +// \vga_pic_inst|pix_data[9]~15_combout = (\vga_pic_inst|pix_data[9]~14_combout & (!\vga_ctrl_inst|Add2~18_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_pic_inst|LessThan17~2_combout ))) + + .dataa(\vga_pic_inst|pix_data[9]~14_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|LessThan17~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[9]~15_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9]~15 .lut_mask = 16'h0200; +defparam \vga_pic_inst|pix_data[9]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~35 ( +// Equation(s): +// \vga_pic_inst|pix_data~35_combout = (\vga_pic_inst|LessThan10~0_combout ) # ((\vga_ctrl_inst|Add2~18_combout ) # ((\vga_pic_inst|pix_data[13]~11_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ))) + + .dataa(\vga_pic_inst|LessThan10~0_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[13]~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~35_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~35 .lut_mask = 16'hFFEF; +defparam \vga_pic_inst|pix_data~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~36 ( +// Equation(s): +// \vga_pic_inst|pix_data~36_combout = (\vga_pic_inst|always0~2_combout & (!\vga_ctrl_inst|Add2~20_combout & (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_pic_inst|pix_data[9]~15_combout ))) + + .dataa(\vga_pic_inst|always0~2_combout ), + .datab(\vga_ctrl_inst|Add2~20_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[9]~15_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~36_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~36 .lut_mask = 16'h0020; +defparam \vga_pic_inst|pix_data~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N6 +cycloneive_lcell_comb \vga_pic_inst|pix_data~21 ( +// Equation(s): +// \vga_pic_inst|pix_data~21_combout = (\vga_pic_inst|pix_data~12_combout & (!\vga_ctrl_inst|Add2~12_combout & ((\vga_pic_inst|LessThan14~0_combout ) # (\vga_pic_inst|always0~0_combout )))) + + .dataa(\vga_pic_inst|LessThan14~0_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_ctrl_inst|Add2~12_combout ), + .datad(\vga_pic_inst|always0~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~21_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~21 .lut_mask = 16'h0C08; +defparam \vga_pic_inst|pix_data~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N22 +cycloneive_lcell_comb \vga_pic_inst|pix_data~26 ( +// Equation(s): +// \vga_pic_inst|pix_data~26_combout = (\vga_pic_inst|pix_data~36_combout & ((\vga_pic_inst|pix_data~25_combout ) # ((\vga_pic_inst|pix_data~35_combout & \vga_pic_inst|pix_data~21_combout )))) + + .dataa(\vga_pic_inst|pix_data~25_combout ), + .datab(\vga_pic_inst|pix_data~35_combout ), + .datac(\vga_pic_inst|pix_data~36_combout ), + .datad(\vga_pic_inst|pix_data~21_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~26_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~26 .lut_mask = 16'hE0A0; +defparam \vga_pic_inst|pix_data~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|pix_x[11]~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_x[11]~0_combout = (\vga_ctrl_inst|Add2~20_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~20_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_x[11]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_x[11]~0 .lut_mask = 16'hFF0F; +defparam \vga_ctrl_inst|pix_x[11]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N8 +cycloneive_lcell_comb \vga_pic_inst|pix_data~27 ( +// Equation(s): +// \vga_pic_inst|pix_data~27_combout = (\vga_pic_inst|pix_data~26_combout ) # ((!\vga_pic_inst|always0~2_combout & (!\vga_pic_inst|pix_data[9]~15_combout & !\vga_ctrl_inst|pix_x[11]~0_combout ))) + + .dataa(\vga_pic_inst|always0~2_combout ), + .datab(\vga_pic_inst|pix_data[9]~15_combout ), + .datac(\vga_pic_inst|pix_data~26_combout ), + .datad(\vga_ctrl_inst|pix_x[11]~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~27_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~27 .lut_mask = 16'hF0F1; +defparam \vga_pic_inst|pix_data~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y21_N9 +dffeas \vga_pic_inst|pix_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[10] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N14 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[10]~2 ( +// Equation(s): +// \vga_ctrl_inst|rgb[10]~2_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_pic_inst|pix_data [10] & \vga_ctrl_inst|pix_data_req~1_combout ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(\vga_pic_inst|pix_data [10]), + .datad(\vga_ctrl_inst|pix_data_req~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[10]~2 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N15 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[10]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[7] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~29 ( +// Equation(s): +// \vga_pic_inst|pix_data~29_combout = (\vga_ctrl_inst|pix_data_req~7_combout & ((\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~10_combout & !\vga_ctrl_inst|Add2~12_combout )) # (!\vga_ctrl_inst|Add2~14_combout & +// ((\vga_ctrl_inst|Add2~12_combout ))))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~29_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~29 .lut_mask = 16'h5020; +defparam \vga_pic_inst|pix_data~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~30 ( +// Equation(s): +// \vga_pic_inst|pix_data~30_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~20_combout & (!\vga_ctrl_inst|Add2~16_combout & !\vga_ctrl_inst|Add2~18_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_ctrl_inst|Add2~20_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~18_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~30_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~30 .lut_mask = 16'h0002; +defparam \vga_pic_inst|pix_data~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~31 ( +// Equation(s): +// \vga_pic_inst|pix_data~31_combout = (\vga_pic_inst|LessThan17~3_combout ) # ((\vga_pic_inst|pix_data~29_combout & \vga_pic_inst|pix_data~30_combout )) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data~29_combout ), + .datac(\vga_pic_inst|pix_data~30_combout ), + .datad(\vga_pic_inst|LessThan17~3_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~31_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~31 .lut_mask = 16'hFFC0; +defparam \vga_pic_inst|pix_data~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y21_N5 +dffeas \vga_pic_inst|pix_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[8] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N4 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[6]~4 ( +// Equation(s): +// \vga_ctrl_inst|rgb[6]~4_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~4_combout & \vga_pic_inst|pix_data [8]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[6]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[6]~4 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[6]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N5 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[6]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add5~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add5~0_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~1_combout & (\vga_pic_inst|pix_data [8] & ((\vga_pic_inst|pix_data [9]) # (\vga_pic_inst|pix_data [10])))) + + .dataa(\vga_pic_inst|pix_data [9]), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~1_combout ), + .datac(\vga_pic_inst|pix_data [10]), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add5~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add5~0 .lut_mask = 16'hC800; +defparam \hdmi_ctrl_inst|encode_inst1|Add5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N27 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add14~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add14~1_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])))) # +// (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add14~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add14~1 .lut_mask = 16'h6006; +defparam \hdmi_ctrl_inst|encode_inst1|Add14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N25 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n0[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add14~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~28 ( +// Equation(s): +// \vga_pic_inst|pix_data~28_combout = (\vga_pic_inst|pix_data~36_combout & ((\vga_pic_inst|pix_data~25_combout ) # ((\vga_pic_inst|pix_data~35_combout & \vga_pic_inst|pix_data~21_combout )))) + + .dataa(\vga_pic_inst|pix_data~25_combout ), + .datab(\vga_pic_inst|pix_data~35_combout ), + .datac(\vga_pic_inst|pix_data~36_combout ), + .datad(\vga_pic_inst|pix_data~21_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~28_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~28 .lut_mask = 16'hE0A0; +defparam \vga_pic_inst|pix_data~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y21_N3 +dffeas \vga_pic_inst|pix_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N8 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[7]~3 ( +// Equation(s): +// \vga_ctrl_inst|rgb[7]~3_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~4_combout & \vga_pic_inst|pix_data [9]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|pix_data [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[7]~3 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N9 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[7]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add13~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add13~0_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [4])) # (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & +// ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]))))) # (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]))) # (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & +// (\hdmi_ctrl_inst|encode_inst1|data_in_reg [4])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add13~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add13~0 .lut_mask = 16'hF690; +defparam \hdmi_ctrl_inst|encode_inst1|Add13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N13 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n1[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add13~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add13~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add13~1_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & \hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])) # (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & +// ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]) # (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add13~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add13~1 .lut_mask = 16'hF330; +defparam \hdmi_ctrl_inst|encode_inst1|Add13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N29 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add13~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_3~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_3~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & !\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~0 .lut_mask = 16'h08AE; +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_3~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_3~1_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]) # ((!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~1 .lut_mask = 16'h7510; +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add14~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add14~2_combout = (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & !\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add14~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add14~2 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst1|Add14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n0[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add14~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X33_Y21_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n1[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~0_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add15~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [0] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~4_combout = ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] $ (\hdmi_ctrl_inst|encode_inst1|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst1|Add15~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|Add15~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst1|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst1|Add15~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst1|Add15~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add14~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add14~0_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & (((!\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & !\hdmi_ctrl_inst|encode_inst1|data_in_reg [7])) # (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]) # ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]) # (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add14~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add14~0 .lut_mask = 16'h37FE; +defparam \hdmi_ctrl_inst|encode_inst1|Add14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N17 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n0[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add14~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// (\hdmi_ctrl_inst|encode_inst1|Add23~1 & VCC)))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst1|Add23~1 ) # (GND))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst1|Add23~1 )))) +// \hdmi_ctrl_inst|encode_inst1|Add23~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst1|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & +// ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst1|Add23~1 )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add23~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add23~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~2 .lut_mask = 16'h694D; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~9_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add17~4_combout ) # (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add23~2_combout & ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add23~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add17~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~9_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~9 .lut_mask = 16'hAAE4; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~10 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~10_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~9_combout & (((\hdmi_ctrl_inst|encode_inst1|Add15~4_combout ) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|Add16~9_combout & (\hdmi_ctrl_inst|encode_inst1|Add20~2_combout & ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add20~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add15~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~9_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~10_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~10 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout = !\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2] + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N23 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~15_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|Add17~0_combout )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & +// ((\hdmi_ctrl_inst|encode_inst1|Add15~0_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add17~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add15~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~15 .lut_mask = 16'hA0C0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[0]~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & (\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & +// (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & +// ((\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|cnt[0]~8 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & +// ((!\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ) # (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~16_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~15_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~7 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal1~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal1~0_combout = (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & (!\hdmi_ctrl_inst|encode_inst1|cnt [0] & (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & !\hdmi_ctrl_inst|encode_inst1|cnt [4]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .datac(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~0 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal1~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal1~1_combout = (\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout & !\hdmi_ctrl_inst|encode_inst1|cnt [3]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~1 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[0]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout = CARRY((\hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ) # (\hdmi_ctrl_inst|encode_inst1|Equal1~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Equal1~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~6 .lut_mask = 16'h00EE; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[1]~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout = ((\hdmi_ctrl_inst|encode_inst1|Add16~14_combout $ (\hdmi_ctrl_inst|encode_inst1|Add16~12_combout $ (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|cnt[1]~10 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~14_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~12_combout ) # (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~14_combout & +// (\hdmi_ctrl_inst|encode_inst1|Add16~12_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~14_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~12_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1]~9 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[2]~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & (\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & +// (!\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & (!\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & +// ((\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|cnt[2]~12 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & +// ((!\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ) # (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2]~11 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N15 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~3_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst1|Add20~4_combout )) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst1|Add23~4_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add20~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add23~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~3 .lut_mask = 16'hEE50; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~4_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~3_combout & (((\hdmi_ctrl_inst|encode_inst1|Add15~6_combout ) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~3_combout +// & (\hdmi_ctrl_inst|encode_inst1|Add17~6_combout & ((\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add17~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add15~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~3_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~4 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[3]~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout = ((\hdmi_ctrl_inst|encode_inst1|Add16~6_combout $ (\hdmi_ctrl_inst|encode_inst1|Add16~4_combout $ (!\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|cnt[3]~14 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~6_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~4_combout ) # (!\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~6_combout & +// (\hdmi_ctrl_inst|encode_inst1|Add16~4_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[3]~14 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3]~13 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N17 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal2~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal2~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] $ (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) # +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] $ (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~0 .lut_mask = 16'h8241; +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_2~combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & +// ((\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ) # ((!\hdmi_ctrl_inst|encode_inst1|cnt [3] & \hdmi_ctrl_inst|encode_inst1|Equal1~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datac(\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_2 .lut_mask = 16'h7350; +defparam \hdmi_ctrl_inst|encode_inst1|condition_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[0]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0]~0 .lut_mask = 16'h22EE; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~11_combout = (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst1|Add19~0_combout ) # (\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst1|Add22~0_combout & ((!\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add22~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add19~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~11_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~11 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~12 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~12_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~11_combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~11_combout & +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1])))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add16~11_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|Add16~11_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~12_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~12 .lut_mask = 16'h5F22; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y21_N13 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~6_combout = \hdmi_ctrl_inst|encode_inst1|Add22~5 $ (!\hdmi_ctrl_inst|encode_inst1|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst1|Add22~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~6 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~2_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout ) # ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst1|Add19~6_combout )) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst1|Add22~6_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add19~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add22~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~2 .lut_mask = 16'hFFAC; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[4]~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout = \hdmi_ctrl_inst|encode_inst1|Add16~1_combout $ (\hdmi_ctrl_inst|encode_inst1|cnt[3]~14 $ (\hdmi_ctrl_inst|encode_inst1|Add16~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|Add16~2_combout ), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[3]~14 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4]~15 .lut_mask = 16'hA55A; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N19 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_3~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_3~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (((\hdmi_ctrl_inst|encode_inst1|cnt [4])))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst1|cnt [4] & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~0_combout )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [4] & ((\hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~2 .lut_mask = 16'hEE50; +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N19 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~1_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [3] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~1 .lut_mask = 16'hA53C; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out~1_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N1 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~3_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [5] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [5]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~3 .lut_mask = 16'h9A56; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~3_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out~3_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N29 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst1|data_out [5]))) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [3])) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2 .lut_mask = 16'hCACA; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N21 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [2]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [3]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [3]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~7_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~7 .lut_mask = 16'hAF05; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N29 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout = (\hdmi_ctrl_inst|encode_inst1|data_out [8] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4 .lut_mask = 16'hCC00; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N27 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [2])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [4]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [2]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [4]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N23 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [4])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [3]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [4]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [3]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N19 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [2])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [2]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1 .lut_mask = 16'hBB88; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [0])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [1]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [0]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [1]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y23_N11 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~33 ( +// Equation(s): +// \vga_pic_inst|pix_data~33_combout = (\vga_pic_inst|pix_data~37_combout & ((\vga_pic_inst|pix_data[13]~10_combout ) # (\vga_pic_inst|pix_data~19_combout ))) + + .dataa(\vga_pic_inst|pix_data~37_combout ), + .datab(\vga_pic_inst|pix_data[13]~10_combout ), + .datac(gnd), + .datad(\vga_pic_inst|pix_data~19_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~33_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~33 .lut_mask = 16'hAA88; +defparam \vga_pic_inst|pix_data~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N15 +dffeas \vga_pic_inst|pix_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N22 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[13]~6 ( +// Equation(s): +// \vga_ctrl_inst|rgb[13]~6_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_pic_inst|pix_data [13] & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_pic_inst|pix_data [13]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[13]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[13]~6 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[13]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N23 +dffeas \hdmi_ctrl_inst|encode_inst2|data_in_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[13]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~32 ( +// Equation(s): +// \vga_pic_inst|pix_data~32_combout = (\vga_pic_inst|pix_data~37_combout & (!\vga_ctrl_inst|pix_x[11]~0_combout & ((\vga_pic_inst|pix_data[13]~9_combout ) # (!\vga_pic_inst|pix_data~13_combout )))) + + .dataa(\vga_pic_inst|pix_data~37_combout ), + .datab(\vga_pic_inst|pix_data~13_combout ), + .datac(\vga_pic_inst|pix_data[13]~9_combout ), + .datad(\vga_ctrl_inst|pix_x[11]~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~32_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~32 .lut_mask = 16'h00A2; +defparam \vga_pic_inst|pix_data~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N5 +dffeas \vga_pic_inst|pix_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~32_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[15] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add6~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add6~0_combout = (\vga_ctrl_inst|pix_data_req~3_combout & (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_pic_inst|pix_data [13] & \vga_pic_inst|pix_data [15]))) + + .dataa(\vga_ctrl_inst|pix_data_req~3_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datac(\vga_pic_inst|pix_data [13]), + .datad(\vga_pic_inst|pix_data [15]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add6~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add6~0 .lut_mask = 16'h8000; +defparam \hdmi_ctrl_inst|encode_inst2|Add6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N27 +dffeas \hdmi_ctrl_inst|encode_inst2|data_in_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_in_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_in_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N20 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[12]~5 ( +// Equation(s): +// \vga_ctrl_inst|rgb[12]~5_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_pic_inst|pix_data [15] & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_pic_inst|pix_data [15]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[12]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[12]~5 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[12]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N21 +dffeas \hdmi_ctrl_inst|encode_inst2|data_in_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[12]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add12~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add12~0_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3] & (!\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2])) # (!\hdmi_ctrl_inst|encode_inst2|data_in_reg [3] & ((\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add12~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add12~0 .lut_mask = 16'h3F0C; +defparam \hdmi_ctrl_inst|encode_inst2|Add12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N5 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n1[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add12~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add14~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add14~0_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]) # ((\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]) # (\hdmi_ctrl_inst|encode_inst2|data_in_reg [4])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add14~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add14~0 .lut_mask = 16'hFFFC; +defparam \hdmi_ctrl_inst|encode_inst2|Add14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N1 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n0[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add14~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add12~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add12~1_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] & !\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add12~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add12~1 .lut_mask = 16'h00F0; +defparam \hdmi_ctrl_inst|encode_inst2|Add12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N23 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add12~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_3~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_3~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & !\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~0 .lut_mask = 16'h20F2; +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout = !\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N7 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal2~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal2~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] $ (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2])))) # +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] $ (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~0 .lut_mask = 16'h9009; +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~0_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add19~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [1] & \hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add19~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~5_combout = (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst2|Add19~4_combout ))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst2|Add22~4_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add22~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add19~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~5 .lut_mask = 16'h0C0A; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~6_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~5_combout ) # ((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~5_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~6 .lut_mask = 16'hF7F0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal1~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal1~0_combout = (!\hdmi_ctrl_inst|encode_inst2|cnt [4] & (!\hdmi_ctrl_inst|encode_inst2|cnt [0] & (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & !\hdmi_ctrl_inst|encode_inst2|cnt [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~0 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal1~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal1~1_combout = (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & \hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~1 .lut_mask = 16'h0F00; +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[0]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout = CARRY((\hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ) # (\hdmi_ctrl_inst|encode_inst2|Equal1~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Equal1~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~6 .lut_mask = 16'h00EE; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[0]~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & (\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & +// (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & +// ((\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|cnt[0]~8 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & +// ((!\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ) # (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~16_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~15_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~7 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y24_N3 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & (\hdmi_ctrl_inst|encode_inst2|cnt [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & (\hdmi_ctrl_inst|encode_inst2|cnt [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add15~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & \hdmi_ctrl_inst|encode_inst2|cnt [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~15_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst2|Add17~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] & +// ((\hdmi_ctrl_inst|encode_inst2|Add15~0_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add17~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add15~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~15 .lut_mask = 16'hAC00; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[1]~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout = ((\hdmi_ctrl_inst|encode_inst2|Add16~12_combout $ (\hdmi_ctrl_inst|encode_inst2|Add16~14_combout $ (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|cnt[1]~10 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~12_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~14_combout ) # (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~12_combout & +// (\hdmi_ctrl_inst|encode_inst2|Add16~14_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~12_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1]~9 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[2]~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & (\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & +// (!\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & (!\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & +// ((\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|cnt[2]~12 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & +// ((!\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ) # (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~10_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~8_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2]~11 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[3]~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout = ((\hdmi_ctrl_inst|encode_inst2|Add16~4_combout $ (\hdmi_ctrl_inst|encode_inst2|Add16~6_combout $ (!\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|cnt[3]~14 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~4_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~6_combout ) # (!\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~4_combout & +// (\hdmi_ctrl_inst|encode_inst2|Add16~6_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[3]~14 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3]~13 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y24_N9 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout = !\hdmi_ctrl_inst|encode_inst2|Add14~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|Add14~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0 .lut_mask = 16'h00FF; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N3 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n0[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_2~combout = (\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout & (((\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout & !\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3]))) # +// (!\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout & (\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_2 .lut_mask = 16'h0ACE; +defparam \hdmi_ctrl_inst|encode_inst2|condition_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[0]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0]~0 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~14 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~14_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~13_combout & (((!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~13_combout +// & (\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst2|Add19~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~13_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst2|Add19~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~14_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~14 .lut_mask = 16'h6E2A; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N5 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst2|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// (\hdmi_ctrl_inst|encode_inst2|Add23~1 & VCC)))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst2|Add23~1 ) # (GND))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst2|Add23~1 )))) +// \hdmi_ctrl_inst|encode_inst2|Add23~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst2|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & +// ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst2|Add23~1 )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add23~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add23~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~2 .lut_mask = 16'h694D; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst2|Add20~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// ((\hdmi_ctrl_inst|encode_inst2|Add20~1 ) # (GND))))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst2|Add20~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst2|Add20~1 )))) +// \hdmi_ctrl_inst|encode_inst2|Add20~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((!\hdmi_ctrl_inst|encode_inst2|Add20~1 ) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst2|Add20~1 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add20~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add20~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~2 .lut_mask = 16'h692B; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~7_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst2|Add20~2_combout ))) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst2|Add23~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add23~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add20~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~7 .lut_mask = 16'hFA44; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~8_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~7_combout & (((\hdmi_ctrl_inst|encode_inst2|Add15~4_combout ) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~7_combout +// & (\hdmi_ctrl_inst|encode_inst2|Add17~4_combout & ((\hdmi_ctrl_inst|encode_inst2|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add17~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add15~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~7_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~8 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N7 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y24_N9 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n1[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~8_combout = \hdmi_ctrl_inst|encode_inst2|Add17~7 $ (!\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~7 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~8 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~6_combout = !\hdmi_ctrl_inst|encode_inst2|Add23~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst2|Add23~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~0_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|Add17~8_combout ) # ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|Add23~6_combout & !\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add17~8_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add23~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~0 .lut_mask = 16'hAAD8; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~6_combout = !\hdmi_ctrl_inst|encode_inst2|Add20~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst2|Add20~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~1_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~0_combout & ((\hdmi_ctrl_inst|encode_inst2|Add15~8_combout ) # ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~0_combout +// & (((\hdmi_ctrl_inst|encode_inst2|Add20~6_combout & \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add15~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add20~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~1 .lut_mask = 16'hB8CC; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[4]~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout = \hdmi_ctrl_inst|encode_inst2|Add16~2_combout $ (\hdmi_ctrl_inst|encode_inst2|cnt[3]~14 $ (\hdmi_ctrl_inst|encode_inst2|Add16~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|Add16~1_combout ), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[3]~14 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4]~15 .lut_mask = 16'hA55A; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y24_N11 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_3~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_3~2_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [4] & (((\hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ) # (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [4] & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~1_combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~2 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N21 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~1_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [1] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [1]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~1 .lut_mask = 16'hB41E; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out~1_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N1 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m[7]~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout = \hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] $ (\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m[7]~1 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst2|q_m[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N29 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~4_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [5] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [5]), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~4 .lut_mask = 16'h939C; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N17 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~7_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst2|c1_reg2~q $ +// ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~7 .lut_mask = 16'hEB41; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N19 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [9]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[9] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout = (\hdmi_ctrl_inst|encode_inst2|data_out [9] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [9]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4 .lut_mask = 16'hC0C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [4]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3 .lut_mask = 16'hCCF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N9 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [3]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [3]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2 .lut_mask = 16'hCCF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N5 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [3]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [1])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [1]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N21 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y24_N17 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[4]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~6 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout = !\hdmi_ctrl_inst|encode_inst2|c0_reg2~q + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N21 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [6]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[6] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst2|data_out [6]))) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [4])) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [4]), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [6]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3 .lut_mask = 16'hCCAA; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N7 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [4])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [3]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [4]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2 .lut_mask = 16'hBB88; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [2])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [2]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1 .lut_mask = 16'hBB88; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N1 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [0])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [0]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y24_N4 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y22_N25 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y23_N18 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y24_N11 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_8_1200mv_85c_v_slow.sdo b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_8_1200mv_85c_v_slow.sdo new file mode 100644 index 0000000..e7677ed --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_8_1200mv_85c_v_slow.sdo @@ -0,0 +1,9062 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "hdmi_colorbar") + (DATE "06/02/2023 04:17:19") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (4503:4503:4503) (4503:4503:4503)) + (PORT inclk[0] (2340:2340:2340) (2340:2340:2340)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1720:1720:1720) (1682:1682:1682)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (PORT sload (1425:1425:1425) (1434:1434:1434)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (PORT sclr (1477:1477:1477) (1540:1540:1540)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (PORT sclr (1477:1477:1477) (1540:1540:1540)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (PORT sclr (1477:1477:1477) (1540:1540:1540)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1695:1695:1695) (1667:1667:1667)) + (PORT clrn (1887:1887:1887) (1859:1859:1859)) + (PORT sload (1861:1861:1861) (1950:1950:1950)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1638:1638:1638) (1522:1522:1522)) + (PORT clrn (1891:1891:1891) (1861:1861:1861)) + (PORT sload (1745:1745:1745) (1782:1782:1782)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1909:1909:1909) (1832:1832:1832)) + (PORT clrn (1891:1891:1891) (1861:1861:1861)) + (PORT sload (1745:1745:1745) (1782:1782:1782)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1087:1087:1087)) + (PORT datab (658:658:658) (680:680:680)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~2) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (653:653:653)) + (PORT datab (834:834:834) (829:829:829)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~4) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (619:619:619)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (632:632:632)) + (PORT datab (364:364:364) (446:446:446)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (862:862:862)) + (PORT datab (648:648:648) (666:666:666)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (872:872:872)) + (PORT datab (615:615:615) (647:647:647)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~6) + (DELAY + (ABSOLUTE + (PORT datab (676:676:676) (689:689:689)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~8) + (DELAY + (ABSOLUTE + (PORT datab (667:667:667) (676:676:676)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1151:1151:1151) (1087:1087:1087)) + (PORT datab (660:660:660) (683:683:683)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (651:651:651)) + (PORT datab (835:835:835) (829:829:829)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~4) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (617:617:617)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (635:635:635)) + (PORT datab (368:368:368) (450:450:450)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (879:879:879)) + (PORT datab (650:650:650) (669:669:669)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~4) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (820:820:820)) + (PORT datab (617:617:617) (649:649:649)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~6) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (905:905:905)) + (PORT datab (678:678:678) (691:691:691)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~8) + (DELAY + (ABSOLUTE + (PORT datab (669:669:669) (678:678:678)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (471:471:471)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~4) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (655:655:655)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (278:278:278) (303:303:303)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (739:739:739)) + (PORT datab (275:275:275) (299:299:299)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (477:477:477)) + (PORT datab (275:275:275) (299:299:299)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1593:1593:1593) (1472:1472:1472)) + (PORT clrn (1887:1887:1887) (1859:1859:1859)) + (PORT sload (1861:1861:1861) (1950:1950:1950)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1138:1138:1138)) + (PORT datab (1156:1156:1156) (1099:1099:1099)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1117:1117:1117) (1073:1073:1073)) + (PORT datab (1847:1847:1847) (1760:1760:1760)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~4) + (DELAY + (ABSOLUTE + (PORT datab (954:954:954) (924:924:924)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (878:878:878)) + (PORT datab (564:564:564) (590:590:590)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (889:889:889)) + (PORT datab (1145:1145:1145) (1082:1082:1082)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (902:902:902)) + (PORT datab (1132:1132:1132) (1072:1072:1072)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~6) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (895:895:895)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~8) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (872:872:872)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1195:1195:1195) (1136:1136:1136)) + (PORT datab (1157:1157:1157) (1100:1100:1100)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~4) + (DELAY + (ABSOLUTE + (PORT datab (955:955:955) (925:925:925)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1827:1827:1827) (1698:1698:1698)) + (PORT datab (921:921:921) (895:895:895)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~6) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (896:896:896)) + (PORT datab (901:901:901) (878:878:878)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~8) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (871:871:871)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (872:872:872)) + (PORT datab (644:644:644) (657:657:657)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~2) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (906:906:906)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (859:859:859)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~6) + (DELAY + (ABSOLUTE + (PORT datad (590:590:590) (616:616:616)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (873:873:873)) + (PORT datab (643:643:643) (656:656:656)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~2) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (904:904:904)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~4) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (859:859:859)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1639:1639:1639) (1523:1523:1523)) + (PORT clrn (1891:1891:1891) (1861:1861:1861)) + (PORT sload (1745:1745:1745) (1782:1782:1782)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (913:913:913)) + (PORT datab (912:912:912) (901:901:901)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~4) + (DELAY + (ABSOLUTE + (PORT datab (826:826:826) (816:816:816)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (829:829:829)) + (PORT datab (358:358:358) (434:434:434)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (609:609:609)) + (PORT datab (835:835:835) (807:807:807)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (445:445:445)) + (PORT datab (823:823:823) (799:799:799)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~6) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (829:829:829)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~0) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (912:912:912)) + (PORT datab (908:908:908) (897:897:897)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~4) + (DELAY + (ABSOLUTE + (PORT datab (823:823:823) (813:813:813)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (822:822:822)) + (PORT datab (368:368:368) (449:449:449)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~4) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (458:458:458)) + (PORT datab (870:870:870) (840:840:840)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~6) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (866:866:866)) + (PORT datab (360:360:360) (437:437:437)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~8) + (DELAY + (ABSOLUTE + (PORT datad (355:355:355) (432:432:432)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~2) + (DELAY + (ABSOLUTE + (PORT datab (581:581:581) (607:607:607)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (617:617:617)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~6) + (DELAY + (ABSOLUTE + (PORT datad (594:594:594) (617:617:617)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (905:905:905)) + (PORT datab (863:863:863) (851:851:851)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~2) + (DELAY + (ABSOLUTE + (PORT datab (583:583:583) (610:610:610)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~4) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (619:619:619)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~6) + (DELAY + (ABSOLUTE + (PORT datad (596:596:596) (619:619:619)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1674:1674:1674) (1551:1551:1551)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (PORT sload (1763:1763:1763) (1796:1796:1796)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1578:1578:1578) (1474:1474:1474)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (PORT sload (1624:1624:1624) (1684:1684:1684)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1720:1720:1720) (1681:1681:1681)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (PORT sload (1425:1425:1425) (1434:1434:1434)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (460:460:460)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (970:970:970)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (627:627:627) (630:630:630)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (622:622:622)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (629:629:629) (633:633:633)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT datab (625:625:625) (633:633:633)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (609:609:609)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT datab (624:624:624) (633:633:633)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datab (593:593:593) (620:620:620)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT datac (296:296:296) (374:374:374)) + (PORT datad (407:407:407) (519:519:519)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (654:654:654)) + (PORT datab (655:655:655) (676:676:676)) + (PORT datac (534:534:534) (564:564:564)) + (PORT datad (523:523:523) (548:548:548)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (858:858:858)) + (PORT datab (649:649:649) (667:667:667)) + (PORT datac (574:574:574) (610:610:610)) + (PORT datad (553:553:553) (583:583:583)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (912:912:912)) + (PORT datab (911:911:911) (901:901:901)) + (PORT datac (899:899:899) (887:887:887)) + (PORT datad (822:822:822) (805:805:805)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT datac (304:304:304) (387:387:387)) + (PORT datad (407:407:407) (519:519:519)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (770:770:770)) + (PORT datab (865:865:865) (826:826:826)) + (PORT datac (750:750:750) (670:670:670)) + (PORT datad (263:263:263) (281:281:281)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~1) + (DELAY + (ABSOLUTE + (PORT dataa (795:795:795) (721:721:721)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (745:745:745) (662:662:662)) + (PORT datad (757:757:757) (701:701:701)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (842:842:842) (796:796:796)) + (PORT datac (535:535:535) (512:512:512)) + (PORT datad (454:454:454) (434:434:434)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (480:480:480)) + (PORT datab (543:543:543) (503:503:503)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (805:805:805) (758:758:758)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (824:824:824)) + (PORT datab (866:866:866) (826:826:826)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (470:470:470) (442:442:442)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (762:762:762)) + (PORT datab (276:276:276) (300:300:300)) + (PORT datac (535:535:535) (511:511:511)) + (PORT datad (803:803:803) (756:756:756)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~8) + (DELAY + (ABSOLUTE + (PORT dataa (760:760:760) (691:691:691)) + (PORT datab (530:530:530) (493:493:493)) + (PORT datac (432:432:432) (415:415:415)) + (PORT datad (516:516:516) (508:508:508)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~11) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (484:484:484)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (535:535:535) (511:511:511)) + (PORT datad (803:803:803) (755:755:755)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~12) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (313:313:313)) + (PORT datab (755:755:755) (701:701:701)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (800:800:800) (752:752:752)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~16) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (561:561:561)) + (PORT datac (843:843:843) (804:804:804)) + (PORT datad (323:323:323) (393:393:393)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datac (627:627:627) (653:653:653)) + (PORT datad (246:246:246) (271:271:271)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add12\~1) + (DELAY + (ABSOLUTE + (PORT datab (1351:1351:1351) (1290:1290:1290)) + (PORT datad (1269:1269:1269) (1219:1219:1219)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (800:800:800)) + (PORT datab (955:955:955) (950:950:950)) + (PORT datac (833:833:833) (778:778:778)) + (PORT datad (823:823:823) (778:778:778)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (422:422:422)) + (PORT datab (338:338:338) (415:415:415)) + (PORT datac (1078:1078:1078) (1104:1104:1104)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (859:859:859)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (491:491:491) (465:465:465)) + (PORT datad (1139:1139:1139) (1035:1035:1035)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~1) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (682:682:682)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (236:236:236) (263:263:263)) + (PORT datad (1138:1138:1138) (1034:1034:1034)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (339:339:339)) + (PORT datab (740:740:740) (675:675:675)) + (PORT datac (1032:1032:1032) (927:927:927)) + (PORT datad (837:837:837) (830:830:830)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1075:1075:1075) (974:974:974)) + (PORT datab (476:476:476) (461:461:461)) + (PORT datac (235:235:235) (261:261:261)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1089:1089:1089) (992:992:992)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (1498:1498:1498) (1433:1433:1433)) + (PORT datad (535:535:535) (510:510:510)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~8) + (DELAY + (ABSOLUTE + (PORT dataa (761:761:761) (694:694:694)) + (PORT datab (274:274:274) (299:299:299)) + (PORT datac (1046:1046:1046) (946:946:946)) + (PORT datad (855:855:855) (828:828:828)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~13) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (544:544:544) (508:508:508)) + (PORT datac (852:852:852) (812:812:812)) + (PORT datad (1139:1139:1139) (1035:1035:1035)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~14) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (275:275:275) (299:299:299)) + (PORT datac (446:446:446) (428:428:428)) + (PORT datad (1139:1139:1139) (1035:1035:1035)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~16) + (DELAY + (ABSOLUTE + (PORT datab (884:884:884) (819:819:819)) + (PORT datac (527:527:527) (559:559:559)) + (PORT datad (831:831:831) (826:826:826)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (474:474:474)) + (PORT datad (839:839:839) (832:832:832)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT asdata (812:812:812) (920:920:920)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (479:479:479)) + (PORT datab (820:820:820) (746:746:746)) + (PORT datad (782:782:782) (722:722:722)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (825:825:825) (781:781:781)) + (PORT datad (771:771:771) (703:703:703)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (764:764:764) (699:699:699)) + (PORT datab (858:858:858) (804:804:804)) + (PORT datac (812:812:812) (756:756:756)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (424:424:424)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (753:753:753)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (800:800:800) (757:757:757)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~9) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (829:829:829)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (776:776:776) (757:757:757)) + (PORT datad (775:775:775) (731:731:731)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~10) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (875:875:875) (847:847:847)) + (PORT datac (444:444:444) (416:416:416)) + (PORT datad (774:774:774) (731:731:731)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~11) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (310:310:310)) + (PORT datab (749:749:749) (675:675:675)) + (PORT datac (817:817:817) (761:761:761)) + (PORT datad (800:800:800) (758:758:758)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~12) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (467:467:467)) + (PORT datab (541:541:541) (500:500:500)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (800:800:800) (758:758:758)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~13) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (831:831:831)) + (PORT datab (605:605:605) (619:619:619)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (775:775:775) (732:732:732)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~16) + (DELAY + (ABSOLUTE + (PORT datab (380:380:380) (471:471:471)) + (PORT datac (816:816:816) (798:798:798)) + (PORT datad (832:832:832) (765:765:765)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (842:842:842) (749:749:749)) + (PORT datad (546:546:546) (575:575:575)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add14\~1) + (DELAY + (ABSOLUTE + (PORT datab (989:989:989) (988:988:988)) + (PORT datac (1022:1022:1022) (1037:1037:1037)) + (PORT datad (958:958:958) (970:970:970)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (477:477:477)) + (PORT datab (333:333:333) (409:409:409)) + (PORT datac (772:772:772) (715:715:715)) + (PORT datad (817:817:817) (739:739:739)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~3) + (DELAY + (ABSOLUTE + (PORT datab (1255:1255:1255) (1209:1209:1209)) + (PORT datac (944:944:944) (966:966:966)) + (PORT datad (755:755:755) (685:685:685)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (851:851:851)) + (PORT datab (366:366:366) (449:449:449)) + (PORT datac (326:326:326) (411:411:411)) + (PORT datad (328:328:328) (401:401:401)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1839:1839:1839) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (765:765:765) (716:716:716)) + (PORT datab (889:889:889) (877:877:877)) + (PORT datac (753:753:753) (687:687:687)) + (PORT datad (245:245:245) (267:267:267)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1168:1168:1168) (1142:1142:1142)) + (PORT datad (1267:1267:1267) (1216:1216:1216)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~5) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (806:806:806)) + (PORT datab (956:956:956) (950:950:950)) + (PORT datac (833:833:833) (778:778:778)) + (PORT datad (823:823:823) (778:778:778)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (537:537:537) (565:565:565)) + (PORT datac (1078:1078:1078) (1103:1103:1103)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (426:426:426)) + (PORT datab (1095:1095:1095) (1095:1095:1095)) + (PORT datac (295:295:295) (373:373:373)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT asdata (804:804:804) (886:886:886)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~4) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (476:476:476)) + (PORT datab (825:825:825) (751:751:751)) + (PORT datad (775:775:775) (715:715:715)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1020:1020:1020) (1034:1034:1034)) + (PORT datad (928:928:928) (938:938:938)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~5) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (366:366:366)) + (PORT datab (336:336:336) (412:412:412)) + (PORT datac (569:569:569) (609:609:609)) + (PORT datad (281:281:281) (305:305:305)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_x\[10\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (854:854:854) (811:811:811)) + (PORT datad (522:522:522) (522:522:522)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (901:901:901)) + (PORT datac (1188:1188:1188) (1099:1099:1099)) + (PORT datad (929:929:929) (884:884:884)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (937:937:937) (879:879:879)) + (PORT datac (1512:1512:1512) (1404:1404:1404)) + (PORT datad (272:272:272) (294:294:294)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[9\]\~14) + (DELAY + (ABSOLUTE + (PORT datac (1188:1188:1188) (1100:1100:1100)) + (PORT datad (889:889:889) (849:849:849)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~16) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (341:341:341)) + (PORT datab (292:292:292) (326:326:326)) + (PORT datac (858:858:858) (809:809:809)) + (PORT datad (856:856:856) (807:807:807)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~8) + (DELAY + (ABSOLUTE + (PORT datab (937:937:937) (896:896:896)) + (PORT datac (854:854:854) (819:819:819)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[10\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (1456:1456:1456) (1327:1327:1327)) + (PORT datad (565:565:565) (552:552:552)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (1351:1351:1351) (1290:1290:1290)) + (PORT datac (1168:1168:1168) (1143:1143:1143)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (825:825:825)) + (PORT datab (955:955:955) (949:949:949)) + (PORT datad (823:823:823) (779:779:779)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1887:1887:1887) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~4) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (423:423:423)) + (PORT datac (1078:1078:1078) (1103:1103:1103)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (865:865:865)) + (PORT datab (867:867:867) (809:809:809)) + (PORT datac (518:518:518) (527:527:527)) + (PORT datad (531:531:531) (521:521:521)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~22) + (DELAY + (ABSOLUTE + (PORT datac (855:855:855) (812:812:812)) + (PORT datad (484:484:484) (461:461:461)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~23) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (572:572:572)) + (PORT datab (278:278:278) (304:304:304)) + (PORT datac (519:519:519) (529:529:529)) + (PORT datad (529:529:529) (511:511:511)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (571:571:571)) + (PORT datad (484:484:484) (460:460:460)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (862:862:862)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (518:518:518) (527:527:527)) + (PORT datad (531:531:531) (522:522:522)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~25) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (327:327:327)) + (PORT datab (823:823:823) (731:731:731)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (244:244:244) (266:266:266)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (382:382:382) (470:470:470)) + (PORT datac (356:356:356) (475:475:475)) + (PORT datad (580:580:580) (608:608:608)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~5) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (862:862:862)) + (PORT datab (806:806:806) (759:759:759)) + (PORT datac (987:987:987) (856:856:856)) + (PORT datad (818:818:818) (801:801:801)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (416:416:416)) + (PORT datac (1040:1040:1040) (1056:1056:1056)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (961:961:961) (944:944:944)) + (PORT datad (921:921:921) (915:915:915)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~4) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (424:424:424)) + (PORT datab (1046:1046:1046) (1067:1067:1067)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1104:1104:1104)) + (PORT datab (898:898:898) (863:863:863)) + (PORT datac (1230:1230:1230) (1212:1212:1212)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (396:396:396) (497:497:497)) + (PORT datac (348:348:348) (466:466:466)) + (PORT datad (586:586:586) (614:614:614)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~6) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (669:669:669)) + (PORT datab (370:370:370) (453:453:453)) + (PORT datac (1254:1254:1254) (1224:1224:1224)) + (PORT datad (264:264:264) (281:281:281)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1004:1004:1004) (1011:1011:1011)) + (PORT datab (1256:1256:1256) (1209:1209:1209)) + (PORT datac (571:571:571) (611:611:611)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~37) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (840:840:840)) + (PORT datab (567:567:567) (572:572:572)) + (PORT datac (860:860:860) (818:818:818)) + (PORT datad (245:245:245) (267:267:267)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (446:446:446) (409:409:409)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT dataa (1121:1121:1121) (1033:1033:1033)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (818:818:818)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (469:469:469) (437:437:437)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datab (1177:1177:1177) (1055:1055:1055)) + (IOPATH datab combout (472:472:472) (473:473:473)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_clk_p\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2838:2838:2838) (2775:2775:2775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_clk_n\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2838:2838:2838) (2775:2775:2775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_p\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2848:2848:2848) (2785:2785:2785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_p\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2848:2848:2848) (2785:2785:2785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_p\[2\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2848:2848:2848) (2785:2785:2785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_n\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2838:2838:2838) (2775:2775:2775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_n\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2858:2858:2858) (2795:2795:2795)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_n\[2\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2848:2848:2848) (2785:2785:2785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\~0) + (DELAY + (ABSOLUTE + (PORT datab (450:450:450) (567:567:567)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|Add0\~1) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (378:378:378)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1069:1069:1069) (1226:1226:1226)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (414:414:414)) + (PORT datad (305:305:305) (378:378:378)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1069:1069:1069) (1226:1226:1226)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (423:423:423)) + (PORT datad (407:407:407) (519:519:519)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (405:405:405) (517:517:517)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (452:452:452) (569:569:569)) + (PORT datac (298:298:298) (377:377:377)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT datac (302:302:302) (385:385:385)) + (PORT datad (408:408:408) (520:520:520)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (417:417:417)) + (PORT datad (406:406:406) (517:517:517)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (413:413:413)) + (PORT datad (406:406:406) (518:518:518)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (806:806:806) (852:852:852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1793:1793:1793) (1777:1777:1777)) + (PORT D (1304:1304:1304) (1328:1328:1328)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1793:1793:1793) (1777:1777:1777)) + (PORT d (1340:1340:1340) (1366:1366:1366)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1966:1966:1966) (1972:1972:1972)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1796:1796:1796) (1779:1779:1779)) + (PORT D (902:902:902) (941:941:941)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1796:1796:1796) (1779:1779:1779)) + (PORT d (989:989:989) (1033:1033:1033)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1969:1969:1969) (1974:1974:1974)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (1456:1456:1456) (1495:1495:1495)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5321:5321:5321) (5126:5126:5126)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (4410:4410:4410) (4581:4581:4581)) + (PORT datab (334:334:334) (410:410:410)) + (PORT datad (735:735:735) (769:769:769)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1831:1831:1831) (1724:1724:1724)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (456:456:456)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (450:450:450)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (484:484:484)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (459:459:459)) + (PORT datab (367:367:367) (449:449:449)) + (PORT datac (325:325:325) (410:410:410)) + (PORT datad (327:327:327) (404:404:404)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (386:386:386) (464:464:464)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datab (396:396:396) (476:476:476)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~20) + (DELAY + (ABSOLUTE + (PORT datab (391:391:391) (473:473:473)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~22) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (484:484:484)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (485:485:485)) + (PORT datab (393:393:393) (476:476:476)) + (PORT datac (353:353:353) (438:438:438)) + (PORT datad (350:350:350) (427:427:427)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1022:1022:1022)) + (PORT datab (928:928:928) (885:885:885)) + (PORT datac (921:921:921) (868:868:868)) + (PORT datad (1141:1141:1141) (1043:1043:1043)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (684:684:684)) + (PORT datab (1270:1270:1270) (1209:1209:1209)) + (PORT datac (583:583:583) (606:606:606)) + (PORT datad (581:581:581) (607:607:607)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~2) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (354:354:354)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (272:272:272) (304:304:304)) + (PORT datad (764:764:764) (688:688:688)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~1) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (354:354:354)) + (PORT datab (313:313:313) (342:342:342)) + (PORT datac (239:239:239) (266:266:266)) + (PORT datad (764:764:764) (689:689:689)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT datab (1268:1268:1268) (1206:1206:1206)) + (PORT datac (582:582:582) (606:606:606)) + (PORT datad (581:581:581) (606:606:606)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (647:647:647)) + (PORT datab (671:671:671) (687:687:687)) + (PORT datac (623:623:623) (645:645:645)) + (PORT datad (745:745:745) (678:678:678)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (627:627:627)) + (PORT datab (879:879:879) (839:839:839)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (627:627:627)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (596:596:596)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~7) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (653:653:653)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~9) + (DELAY + (ABSOLUTE + (PORT datab (1264:1264:1264) (1202:1202:1202)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT datab (640:640:640) (654:654:654)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT datab (583:583:583) (606:606:606)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (677:677:677)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (659:659:659)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT datab (645:645:645) (650:650:650)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (876:876:876)) + (PORT datab (569:569:569) (575:575:575)) + (PORT datac (520:520:520) (529:529:529)) + (PORT datad (529:529:529) (520:520:520)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~5) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (648:648:648)) + (PORT datac (625:625:625) (647:647:647)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT datab (970:970:970) (903:903:903)) + (PORT datac (883:883:883) (844:844:844)) + (PORT datad (1143:1143:1143) (1045:1045:1045)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (473:473:473)) + (PORT datab (379:379:379) (446:446:446)) + (PORT datad (1204:1204:1204) (1128:1128:1128)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (1456:1456:1456) (1328:1328:1328)) + (PORT datad (564:564:564) (551:551:551)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1839:1839:1839) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (760:760:760) (694:694:694)) + (PORT datab (379:379:379) (445:445:445)) + (PORT datad (1205:1205:1205) (1129:1129:1129)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (455:455:455)) + (PORT datab (365:365:365) (447:447:447)) + (PORT datac (560:560:560) (575:575:575)) + (PORT datad (327:327:327) (400:400:400)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (715:715:715)) + (PORT datab (376:376:376) (441:441:441)) + (PORT datad (1210:1210:1210) (1134:1134:1134)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (497:497:497)) + (PORT datab (375:375:375) (439:439:439)) + (PORT datad (1214:1214:1214) (1138:1138:1138)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (754:754:754)) + (PORT datab (310:310:310) (339:339:339)) + (PORT datac (329:329:329) (413:413:413)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT datab (357:357:357) (433:433:433)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (601:601:601)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datad (1423:1423:1423) (1292:1292:1292)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1839:1839:1839) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (475:475:475) (462:462:462)) + (PORT datab (375:375:375) (440:440:440)) + (PORT datad (1213:1213:1213) (1137:1137:1137)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (475:475:475)) + (PORT datab (393:393:393) (476:476:476)) + (PORT datac (568:568:568) (594:594:594)) + (PORT datad (331:331:331) (409:409:409)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[11\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (287:287:287) (315:315:315)) + (PORT datac (239:239:239) (265:265:265)) + (PORT datad (1212:1212:1212) (1135:1135:1135)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (737:737:737)) + (PORT datab (379:379:379) (444:444:444)) + (PORT datad (1206:1206:1206) (1129:1129:1129)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (466:466:466)) + (PORT datab (380:380:380) (446:446:446)) + (PORT datad (1203:1203:1203) (1127:1127:1127)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (627:627:627) (631:631:631)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (515:515:515)) + (PORT datab (484:484:484) (453:453:453)) + (PORT datad (1209:1209:1209) (1133:1133:1133)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~22) + (DELAY + (ABSOLUTE + (PORT datad (320:320:320) (390:390:390)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (609:609:609)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datad (1416:1416:1416) (1285:1285:1285)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1839:1839:1839) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (867:867:867)) + (PORT datab (938:938:938) (897:897:897)) + (PORT datac (601:601:601) (619:619:619)) + (PORT datad (556:556:556) (578:578:578)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~4) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (728:728:728)) + (PORT datac (851:851:851) (827:827:827)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~6) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (554:554:554)) + (PORT datab (669:669:669) (685:685:685)) + (PORT datac (622:622:622) (644:644:644)) + (PORT datad (743:743:743) (677:677:677)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~7) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (719:719:719)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (261:261:261) (286:286:286)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (573:573:573)) + (PORT datab (772:772:772) (714:714:714)) + (PORT datac (519:519:519) (528:528:528)) + (PORT datad (530:530:530) (512:512:512)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (580:580:580)) + (PORT datab (568:568:568) (574:574:574)) + (PORT datac (862:862:862) (821:821:821)) + (PORT datad (246:246:246) (268:268:268)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~13) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (490:490:490)) + (PORT datab (498:498:498) (492:492:492)) + (PORT datac (1541:1541:1541) (1408:1408:1408)) + (PORT datad (888:888:888) (834:834:834)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~17) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (574:574:574)) + (PORT datac (518:518:518) (527:527:527)) + (PORT datad (532:532:532) (514:514:514)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~34) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (841:841:841)) + (PORT datab (568:568:568) (573:573:573)) + (PORT datac (861:861:861) (820:820:820)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (573:573:573)) + (PORT datad (531:531:531) (513:513:513)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (867:867:867)) + (PORT datab (566:566:566) (570:570:570)) + (PORT datac (518:518:518) (527:527:527)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (877:877:877)) + (PORT datac (1395:1395:1395) (1222:1222:1222)) + (PORT datad (846:846:846) (790:790:790)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~18) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (843:843:843)) + (PORT datab (284:284:284) (314:314:314)) + (PORT datac (839:839:839) (785:785:785)) + (PORT datad (254:254:254) (287:287:287)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~20) + (DELAY + (ABSOLUTE + (PORT datad (552:552:552) (568:568:568)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (904:904:904)) + (PORT datab (914:914:914) (863:863:863)) + (PORT datac (1184:1184:1184) (1094:1094:1094)) + (PORT datad (934:934:934) (889:889:889)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~3) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (865:865:865)) + (PORT datab (920:920:920) (871:871:871)) + (PORT datac (1512:1512:1512) (1404:1404:1404)) + (PORT datad (236:236:236) (255:255:255)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (903:903:903)) + (PORT datac (863:863:863) (825:825:825)) + (PORT datad (930:930:930) (885:885:885)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~19) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (843:843:843)) + (PORT datab (557:557:557) (517:517:517)) + (PORT datac (713:713:713) (629:629:629)) + (PORT datad (886:886:886) (832:832:832)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~20) + (DELAY + (ABSOLUTE + (PORT datab (293:293:293) (327:327:327)) + (PORT datac (839:839:839) (786:786:786)) + (PORT datad (246:246:246) (268:268:268)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1161:1161:1161) (1056:1056:1056)) + (PORT datab (875:875:875) (820:820:820)) + (PORT datac (303:303:303) (386:386:386)) + (PORT datad (305:305:305) (379:379:379)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_in_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[8\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (1272:1272:1272) (1221:1221:1221)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT asdata (1683:1683:1683) (1621:1621:1621)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (641:641:641)) + (PORT datab (371:371:371) (451:451:451)) + (PORT datac (329:329:329) (412:412:412)) + (PORT datad (338:338:338) (422:422:422)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (312:312:312) (342:342:342)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (326:326:326) (399:399:399)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1171:1171:1171)) + (PORT datab (1498:1498:1498) (1358:1358:1358)) + (PORT datac (305:305:305) (388:388:388)) + (PORT datad (812:812:812) (770:770:770)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_in_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1264:1264:1264) (1172:1172:1172)) + (PORT datab (873:873:873) (818:818:818)) + (PORT datac (1455:1455:1455) (1319:1319:1319)) + (PORT datad (304:304:304) (378:378:378)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_in_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add14\~0) + (DELAY + (ABSOLUTE + (PORT datab (1349:1349:1349) (1288:1288:1288)) + (PORT datac (1169:1169:1169) (1143:1143:1143)) + (PORT datad (1270:1270:1270) (1219:1219:1219)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (239:239:239) (257:257:257)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (613:613:613)) + (PORT datab (954:954:954) (909:909:909)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~2) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (470:470:470)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~6) + (DELAY + (ABSOLUTE + (PORT datab (386:386:386) (463:463:463)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (592:592:592)) + (PORT datab (955:955:955) (950:950:950)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~2) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (650:650:650)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~6) + (DELAY + (ABSOLUTE + (PORT datad (565:565:565) (579:579:579)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (559:559:559)) + (PORT datab (502:502:502) (484:484:484)) + (PORT datac (236:236:236) (263:263:263)) + (PORT datad (454:454:454) (434:434:434)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (823:823:823)) + (PORT datab (950:950:950) (944:944:944)) + (PORT datad (822:822:822) (778:778:778)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~9) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (530:530:530)) + (PORT datab (279:279:279) (304:304:304)) + (PORT datac (838:838:838) (805:805:805)) + (PORT datad (822:822:822) (778:778:778)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~10) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (813:813:813)) + (PORT datab (479:479:479) (462:462:462)) + (PORT datac (816:816:816) (749:749:749)) + (PORT datad (486:486:486) (455:455:455)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add12\~0) + (DELAY + (ABSOLUTE + (PORT datab (1349:1349:1349) (1287:1287:1287)) + (PORT datac (1170:1170:1170) (1145:1145:1145)) + (PORT datad (1274:1274:1274) (1223:1223:1223)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add14\~1) + (DELAY + (ABSOLUTE + (PORT datab (1350:1350:1350) (1288:1288:1288)) + (PORT datac (1169:1169:1169) (1144:1144:1144)) + (PORT datad (1271:1271:1271) (1221:1221:1221)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~13) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (530:530:530)) + (PORT datab (280:280:280) (305:305:305)) + (PORT datac (882:882:882) (850:850:850)) + (PORT datad (822:822:822) (778:778:778)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~14) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (795:795:795)) + (PORT datab (278:278:278) (304:304:304)) + (PORT datac (793:793:793) (770:770:770)) + (PORT datad (453:453:453) (429:429:429)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (1588:1588:1588) (1540:1540:1540)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~15) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (560:560:560)) + (PORT datab (530:530:530) (493:493:493)) + (PORT datac (477:477:477) (446:446:446)) + (PORT datad (896:896:896) (862:862:862)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (654:654:654)) + (PORT datab (654:654:654) (676:676:676)) + (PORT datac (534:534:534) (564:564:564)) + (PORT datad (523:523:523) (548:548:548)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datac (866:866:866) (839:839:839)) + (PORT datad (477:477:477) (451:451:451)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (496:496:496)) + (PORT datab (475:475:475) (459:459:459)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (728:728:728)) + (PORT datab (541:541:541) (504:504:504)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1166:1166:1166)) + (PORT datac (1452:1452:1452) (1315:1315:1315)) + (PORT datad (812:812:812) (771:771:771)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|de_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|de_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (368:368:368)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|de_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (PORT sclr (1477:1477:1477) (1540:1540:1540)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_2) + (DELAY + (ABSOLUTE + (PORT dataa (287:287:287) (322:322:322)) + (PORT datab (903:903:903) (872:872:872)) + (PORT datac (626:626:626) (652:652:652)) + (PORT datad (479:479:479) (453:453:453)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (955:955:955) (950:950:950)) + (PORT datac (799:799:799) (791:791:791)) + (PORT datad (822:822:822) (778:778:778)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (472:472:472)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (PORT sclr (1477:1477:1477) (1540:1540:1540)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (653:653:653)) + (PORT datab (656:656:656) (677:677:677)) + (PORT datac (534:534:534) (564:564:564)) + (PORT datad (523:523:523) (548:548:548)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (502:502:502)) + (PORT datab (904:904:904) (872:872:872)) + (PORT datac (616:616:616) (639:639:639)) + (PORT datad (470:470:470) (442:442:442)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (747:747:747)) + (PORT datab (361:361:361) (437:437:437)) + (PORT datad (794:794:794) (719:719:719)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (738:738:738) (668:668:668)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (870:870:870)) + (PORT datab (648:648:648) (652:652:652)) + (PORT datac (594:594:594) (617:617:617)) + (PORT datad (554:554:554) (569:569:569)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (686:686:686)) + (PORT datab (645:645:645) (658:658:658)) + (PORT datac (1230:1230:1230) (1173:1173:1173)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c0_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c0_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT asdata (760:760:760) (829:829:829)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1694:1694:1694) (1667:1667:1667)) + (PORT clrn (1887:1887:1887) (1859:1859:1859)) + (PORT sload (1861:1861:1861) (1950:1950:1950)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (1349:1349:1349) (1288:1288:1288)) + (PORT datad (1273:1273:1273) (1222:1222:1222)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~4) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (825:825:825)) + (PORT datab (954:954:954) (948:948:948)) + (PORT datac (811:811:811) (773:773:773)) + (PORT datad (823:823:823) (778:778:778)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (679:679:679) (607:607:607)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1697:1697:1697) (1671:1671:1671)) + (PORT clrn (1887:1887:1887) (1859:1859:1859)) + (PORT sload (1861:1861:1861) (1950:1950:1950)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (476:476:476)) + (PORT datab (396:396:396) (480:480:480)) + (PORT datac (548:548:548) (569:569:569)) + (PORT datad (246:246:246) (271:271:271)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c1_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c1_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1396:1396:1396) (1298:1298:1298)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c1_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~7) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (749:749:749)) + (PORT datab (1282:1282:1282) (1246:1246:1246)) + (PORT datac (1097:1097:1097) (1062:1062:1062)) + (PORT datad (909:909:909) (898:898:898)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1887:1887:1887) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (412:412:412)) + (PORT datac (1077:1077:1077) (1103:1103:1103)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (346:346:346) (429:429:429)) + (PORT datac (1077:1077:1077) (1103:1103:1103)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (431:431:431)) + (PORT datac (1077:1077:1077) (1103:1103:1103)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (423:423:423)) + (PORT datac (1077:1077:1077) (1103:1103:1103)) + (PORT datad (295:295:295) (365:365:365)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (415:415:415)) + (PORT datac (1078:1078:1078) (1104:1104:1104)) + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1335:1335:1335) (1336:1336:1336)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (PORT sload (1624:1624:1624) (1684:1684:1684)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~3) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (747:747:747)) + (PORT datab (1284:1284:1284) (1249:1249:1249)) + (PORT datac (1094:1094:1094) (1058:1058:1058)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1887:1887:1887) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (423:423:423)) + (PORT datab (337:337:337) (414:414:414)) + (PORT datac (1078:1078:1078) (1104:1104:1104)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (452:452:452) (569:569:569)) + (PORT datac (911:911:911) (904:904:904)) + (PORT datad (893:893:893) (882:882:882)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1796:1796:1796) (1779:1779:1779)) + (PORT D (1266:1266:1266) (1278:1278:1278)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1796:1796:1796) (1779:1779:1779)) + (PORT d (972:972:972) (1032:1032:1032)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1969:1969:1969) (1974:1974:1974)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (944:944:944)) + (PORT datab (914:914:914) (862:862:862)) + (PORT datac (1186:1186:1186) (1097:1097:1097)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[9\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (313:313:313)) + (PORT datab (935:935:935) (877:877:877)) + (PORT datac (1511:1511:1511) (1403:1403:1403)) + (PORT datad (272:272:272) (293:293:293)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~35) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (328:328:328)) + (PORT datab (568:568:568) (574:574:574)) + (PORT datac (863:863:863) (822:822:822)) + (PORT datad (246:246:246) (268:268:268)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~36) + (DELAY + (ABSOLUTE + (PORT dataa (297:297:297) (342:342:342)) + (PORT datab (921:921:921) (872:872:872)) + (PORT datac (1184:1184:1184) (1094:1094:1094)) + (PORT datad (251:251:251) (282:282:282)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~21) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (489:489:489)) + (PORT datab (497:497:497) (491:491:491)) + (PORT datac (1540:1540:1540) (1407:1407:1407)) + (PORT datad (887:887:887) (833:833:833)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~26) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (853:853:853)) + (PORT datab (842:842:842) (807:807:807)) + (PORT datac (242:242:242) (273:273:273)) + (PORT datad (460:460:460) (440:440:440)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_x\[11\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1185:1185:1185) (1067:1067:1067)) + (PORT datad (858:858:858) (810:810:810)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~27) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (339:339:339)) + (PORT datab (294:294:294) (328:328:328)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (844:844:844) (792:792:792)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[10\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (766:766:766)) + (PORT datab (1440:1440:1440) (1301:1301:1301)) + (PORT datac (562:562:562) (583:583:583)) + (PORT datad (1670:1670:1670) (1467:1467:1467)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~29) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (901:901:901)) + (PORT datab (913:913:913) (862:862:862)) + (PORT datac (1190:1190:1190) (1102:1102:1102)) + (PORT datad (928:928:928) (882:882:882)) + (IOPATH dataa combout (453:453:453) (428:428:428)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1143:1143:1143)) + (PORT datab (920:920:920) (872:872:872)) + (PORT datac (1512:1512:1512) (1404:1404:1404)) + (PORT datad (876:876:876) (829:829:829)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~31) + (DELAY + (ABSOLUTE + (PORT datab (275:275:275) (300:300:300)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (265:265:265) (283:283:283)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[6\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (768:768:768)) + (PORT datab (1423:1423:1423) (1274:1274:1274)) + (PORT datac (1397:1397:1397) (1261:1261:1261)) + (PORT datad (552:552:552) (571:571:571)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (605:605:605)) + (PORT datab (745:745:745) (690:690:690)) + (PORT datac (564:564:564) (584:584:584)) + (PORT datad (556:556:556) (575:575:575)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (637:637:637)) + (PORT datab (397:397:397) (498:498:498)) + (PORT datac (354:354:354) (473:473:473)) + (PORT datad (582:582:582) (609:609:609)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n0\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~28) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (849:849:849)) + (PORT datab (840:840:840) (805:805:805)) + (PORT datac (247:247:247) (278:278:278)) + (PORT datad (458:458:458) (438:438:438)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (767:767:767)) + (PORT datab (1423:1423:1423) (1274:1274:1274)) + (PORT datac (1397:1397:1397) (1262:1262:1262)) + (PORT datad (521:521:521) (547:547:547)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (477:477:477)) + (PORT datab (395:395:395) (510:510:510)) + (PORT datac (338:338:338) (428:428:428)) + (PORT datad (546:546:546) (561:561:561)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add13\~1) + (DELAY + (ABSOLUTE + (PORT datab (397:397:397) (498:498:498)) + (PORT datac (355:355:355) (474:474:474)) + (PORT datad (581:581:581) (608:608:608)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1583:1583:1583) (1534:1534:1534)) + (PORT datab (949:949:949) (926:926:926)) + (PORT datac (807:807:807) (803:803:803)) + (PORT datad (852:852:852) (825:825:825)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1585:1585:1585) (1537:1537:1537)) + (PORT datab (948:948:948) (925:925:925)) + (PORT datac (808:808:808) (805:805:805)) + (PORT datad (851:851:851) (823:823:823)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add14\~2) + (DELAY + (ABSOLUTE + (PORT dataa (589:589:589) (634:634:634)) + (PORT datab (395:395:395) (509:509:509)) + (PORT datac (354:354:354) (458:458:458)) + (PORT datad (585:585:585) (613:613:613)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n0\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1850:1850:1850)) + (PORT asdata (2131:2131:2131) (2021:2021:2021)) + (PORT clrn (1882:1882:1882) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (881:881:881)) + (PORT datab (566:566:566) (593:593:593)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1536:1536:1536) (1494:1494:1494)) + (PORT datab (910:910:910) (899:899:899)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (636:636:636)) + (PORT datab (397:397:397) (512:512:512)) + (PORT datac (355:355:355) (459:459:459)) + (PORT datad (583:583:583) (611:611:611)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n0\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1072:1072:1072)) + (PORT datab (1849:1849:1849) (1763:1763:1763)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~9) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (854:854:854)) + (PORT datab (276:276:276) (300:300:300)) + (PORT datac (449:449:449) (436:436:436)) + (PORT datad (1137:1137:1137) (1033:1033:1033)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~10) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (543:543:543) (502:502:502)) + (PORT datac (239:239:239) (266:266:266)) + (PORT datad (1140:1140:1140) (1036:1036:1036)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[8\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (337:337:337) (427:427:427)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~15) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (310:310:310)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (822:822:822) (765:765:765)) + (PORT datad (912:912:912) (881:881:881)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (745:745:745)) + (PORT datab (1547:1547:1547) (1392:1392:1392)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT sclr (1457:1457:1457) (1514:1514:1514)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (444:444:444)) + (PORT datab (848:848:848) (817:817:817)) + (PORT datac (318:318:318) (396:396:396)) + (PORT datad (321:321:321) (391:391:391)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datab (289:289:289) (319:319:319)) + (PORT datad (329:329:329) (406:406:406)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (278:278:278) (303:303:303)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (745:745:745)) + (PORT datab (472:472:472) (455:455:455)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (493:493:493)) + (PORT datab (751:751:751) (678:678:678)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT sclr (1457:1457:1457) (1514:1514:1514)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (855:855:855)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (235:235:235) (261:261:261)) + (PORT datad (1138:1138:1138) (1034:1034:1034)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (277:277:277) (301:301:301)) + (PORT datac (711:711:711) (641:641:641)) + (PORT datad (826:826:826) (772:772:772)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (803:803:803) (726:726:726)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT sclr (1457:1457:1457) (1514:1514:1514)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1533:1533:1533)) + (PORT datab (949:949:949) (926:926:926)) + (PORT datac (806:806:806) (803:803:803)) + (PORT datad (853:853:853) (826:826:826)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_2) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (889:889:889)) + (PORT datab (368:368:368) (448:448:448)) + (PORT datac (793:793:793) (709:709:709)) + (PORT datad (248:248:248) (275:275:275)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (869:869:869)) + (PORT datab (809:809:809) (762:762:762)) + (PORT datad (819:819:819) (803:803:803)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~11) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (314:314:314)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (1044:1044:1044) (943:943:943)) + (PORT datad (530:530:530) (505:505:505)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~12) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (798:798:798)) + (PORT datab (950:950:950) (927:927:927)) + (PORT datac (810:810:810) (807:807:807)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT sclr (1457:1457:1457) (1514:1514:1514)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~6) + (DELAY + (ABSOLUTE + (PORT datad (591:591:591) (618:618:618)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (742:742:742) (679:679:679)) + (PORT datab (792:792:792) (710:710:710)) + (PORT datac (770:770:770) (709:709:709)) + (PORT datad (781:781:781) (721:721:721)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (737:737:737)) + (PORT datad (452:452:452) (430:430:430)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT sclr (1457:1457:1457) (1514:1514:1514)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (896:896:896)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (590:590:590) (617:617:617)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT asdata (803:803:803) (884:884:884)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (477:477:477)) + (PORT datab (824:824:824) (751:751:751)) + (PORT datad (776:776:776) (716:716:716)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (780:780:780) (695:695:695)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1719:1719:1719) (1680:1680:1680)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (PORT sload (1425:1425:1425) (1434:1434:1434)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~3) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (777:777:777)) + (PORT datab (808:808:808) (760:760:760)) + (PORT datac (986:986:986) (855:855:855)) + (PORT datad (820:820:820) (803:803:803)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1722:1722:1722) (1684:1684:1684)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (PORT sload (1425:1425:1425) (1434:1434:1434)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (422:422:422)) + (PORT datab (336:336:336) (413:413:413)) + (PORT datac (1040:1040:1040) (1056:1056:1056)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (PORT datac (1038:1038:1038) (1054:1054:1054)) + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (430:430:430)) + (PORT datac (1040:1040:1040) (1056:1056:1056)) + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~7) + (DELAY + (ABSOLUTE + (PORT dataa (987:987:987) (991:991:991)) + (PORT datac (1441:1441:1441) (1373:1373:1373)) + (PORT datad (1255:1255:1255) (1202:1202:1202)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1861:1861:1861)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (412:412:412)) + (PORT datad (1042:1042:1042) (1073:1073:1073)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~3) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (439:439:439)) + (PORT datab (1086:1086:1086) (1121:1121:1121)) + (PORT datac (295:295:295) (373:373:373)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (424:424:424)) + (PORT datab (1086:1086:1086) (1121:1121:1121)) + (PORT datac (296:296:296) (374:374:374)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (438:438:438)) + (PORT datab (1087:1087:1087) (1122:1122:1122)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (972:972:972)) + (PORT datab (1087:1087:1087) (1122:1122:1122)) + (PORT datac (296:296:296) (374:374:374)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1798:1798:1798) (1784:1784:1784)) + (PORT D (882:882:882) (936:936:936)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1798:1798:1798) (1784:1784:1784)) + (PORT d (1325:1325:1325) (1362:1362:1362)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1971:1971:1971) (1979:1979:1979)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~33) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (831:831:831)) + (PORT datab (293:293:293) (328:328:328)) + (PORT datad (246:246:246) (268:268:268)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[13\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1262:1262:1262) (1169:1169:1169)) + (PORT datab (1497:1497:1497) (1356:1356:1356)) + (PORT datac (305:305:305) (388:388:388)) + (PORT datad (812:812:812) (771:771:771)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_in_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~32) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (830:830:830)) + (PORT datab (283:283:283) (314:314:314)) + (PORT datac (857:857:857) (804:804:804)) + (PORT datad (843:843:843) (792:792:792)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1161:1161:1161) (1056:1056:1056)) + (PORT datab (873:873:873) (818:818:818)) + (PORT datac (305:305:305) (389:389:389)) + (PORT datad (532:532:532) (555:555:555)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_in_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[12\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1261:1261:1261) (1168:1168:1168)) + (PORT datab (1497:1497:1497) (1356:1356:1356)) + (PORT datac (323:323:323) (402:402:402)) + (PORT datad (812:812:812) (771:771:771)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_in_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add12\~0) + (DELAY + (ABSOLUTE + (PORT datab (993:993:993) (992:992:992)) + (PORT datac (1027:1027:1027) (1043:1043:1043)) + (PORT datad (960:960:960) (972:972:972)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add14\~0) + (DELAY + (ABSOLUTE + (PORT datab (993:993:993) (993:993:993)) + (PORT datac (1028:1028:1028) (1044:1044:1044)) + (PORT datad (960:960:960) (972:972:972)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add12\~1) + (DELAY + (ABSOLUTE + (PORT datac (1021:1021:1021) (1035:1035:1035)) + (PORT datad (957:957:957) (969:969:969)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (912:912:912)) + (PORT datab (907:907:907) (896:896:896)) + (PORT datac (894:894:894) (881:881:881)) + (PORT datad (824:824:824) (807:807:807)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[8\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1027:1027:1027) (1042:1042:1042)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (913:913:913)) + (PORT datab (913:913:913) (903:903:903)) + (PORT datac (902:902:902) (890:890:890)) + (PORT datad (821:821:821) (804:804:804)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (902:902:902)) + (PORT datab (862:862:862) (850:850:850)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (823:823:823) (779:779:779)) + (PORT datad (770:770:770) (701:701:701)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (865:865:865)) + (PORT datab (868:868:868) (856:856:856)) + (PORT datac (492:492:492) (462:462:462)) + (PORT datad (835:835:835) (769:769:769)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (480:480:480)) + (PORT datab (374:374:374) (463:463:463)) + (PORT datac (325:325:325) (410:410:410)) + (PORT datad (327:327:327) (404:404:404)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datac (854:854:854) (825:825:825)) + (PORT datad (726:726:726) (656:656:656)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (966:966:966)) + (PORT datab (1047:1047:1047) (920:920:920)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (277:277:277) (302:302:302)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT sclr (1798:1798:1798) (1895:1895:1895)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (844:844:844)) + (PORT datab (376:376:376) (466:466:466)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~15) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (751:751:751)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (828:828:828) (818:818:818)) + (PORT datad (834:834:834) (767:767:767)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (468:468:468)) + (PORT datab (541:541:541) (503:503:503)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (691:691:691)) + (PORT datab (276:276:276) (301:301:301)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (475:475:475)) + (PORT datab (276:276:276) (301:301:301)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT sclr (1798:1798:1798) (1895:1895:1895)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (237:237:237) (255:255:255)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_2) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (717:717:717)) + (PORT datab (837:837:837) (744:744:744)) + (PORT datac (851:851:851) (822:822:822)) + (PORT datad (551:551:551) (581:581:581)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (366:366:366)) + (PORT datab (608:608:608) (644:644:644)) + (PORT datad (281:281:281) (305:305:305)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~14) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (818:818:818) (775:775:775)) + (PORT datac (821:821:821) (796:796:796)) + (PORT datad (443:443:443) (415:415:415)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT sclr (1798:1798:1798) (1895:1895:1895)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (850:850:850)) + (PORT datab (949:949:949) (920:920:920)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~2) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (848:848:848)) + (PORT datab (953:953:953) (926:926:926)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (810:810:810)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (801:801:801) (758:758:758)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~8) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (759:759:759)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (690:690:690) (636:636:636)) + (PORT datad (835:835:835) (768:768:768)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT sclr (1798:1798:1798) (1895:1895:1895)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT asdata (1652:1652:1652) (1603:1603:1603)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~8) + (DELAY + (ABSOLUTE + (PORT datad (861:861:861) (829:829:829)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (834:834:834)) + (PORT datab (485:485:485) (466:466:466)) + (PORT datac (746:746:746) (671:671:671)) + (PORT datad (777:777:777) (734:734:734)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~1) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (728:728:728)) + (PORT datab (275:275:275) (299:299:299)) + (PORT datac (710:710:710) (638:638:638)) + (PORT datad (777:777:777) (734:734:734)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (476:476:476)) + (PORT datad (450:450:450) (428:428:428)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT sclr (1798:1798:1798) (1895:1895:1895)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (720:720:720)) + (PORT datab (783:783:783) (705:705:705)) + (PORT datac (859:859:859) (818:818:818)) + (PORT datad (551:551:551) (580:580:580)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT asdata (1488:1488:1488) (1493:1493:1493)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (763:763:763)) + (PORT datab (877:877:877) (788:788:788)) + (PORT datad (339:339:339) (424:424:424)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (855:855:855) (792:792:792)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1909:1909:1909) (1833:1833:1833)) + (PORT clrn (1891:1891:1891) (1861:1861:1861)) + (PORT sload (1745:1745:1745) (1782:1782:1782)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (1019:1019:1019) (1033:1033:1033)) + (PORT datad (956:956:956) (968:968:968)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~4) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (479:479:479)) + (PORT datab (333:333:333) (409:409:409)) + (PORT datac (772:772:772) (715:715:715)) + (PORT datad (817:817:817) (739:739:739)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (765:765:765) (677:677:677)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1909:1909:1909) (1832:1832:1832)) + (PORT clrn (1891:1891:1891) (1861:1861:1861)) + (PORT sload (1745:1745:1745) (1782:1782:1782)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~7) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (673:673:673)) + (PORT datab (372:372:372) (455:455:455)) + (PORT datac (1255:1255:1255) (1225:1225:1225)) + (PORT datad (859:859:859) (813:813:813)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (414:414:414)) + (PORT datac (1039:1039:1039) (1055:1055:1055)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (346:346:346) (430:430:430)) + (PORT datac (937:937:937) (927:927:927)) + (PORT datad (1043:1043:1043) (1074:1074:1074)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT datab (346:346:346) (430:430:430)) + (PORT datac (295:295:295) (373:373:373)) + (PORT datad (1043:1043:1043) (1075:1075:1075)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (424:424:424)) + (PORT datab (1086:1086:1086) (1121:1121:1121)) + (PORT datac (298:298:298) (376:376:376)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (415:415:415)) + (PORT datac (940:940:940) (953:953:953)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1999:1999:1999) (1897:1897:1897)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (PORT sload (1763:1763:1763) (1796:1796:1796)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[4\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (366:366:366)) + (PORT datab (613:613:613) (648:648:648)) + (PORT datad (281:281:281) (305:305:305)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c0_reg2\~_wirecell) + (DELAY + (ABSOLUTE + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1672:1672:1672) (1549:1549:1549)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (PORT sload (1763:1763:1763) (1796:1796:1796)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~3) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (423:423:423)) + (PORT datab (338:338:338) (415:415:415)) + (PORT datad (1006:1006:1006) (1025:1025:1025)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (425:425:425)) + (PORT datab (1044:1044:1044) (1065:1065:1065)) + (PORT datad (298:298:298) (368:368:368)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (428:428:428)) + (PORT datab (1046:1046:1046) (1068:1068:1068)) + (PORT datad (299:299:299) (369:369:369)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (414:414:414)) + (PORT datac (979:979:979) (987:987:987)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1800:1800:1800) (1786:1786:1786)) + (PORT D (884:884:884) (939:939:939)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1800:1800:1800) (1786:1786:1786)) + (PORT d (1354:1354:1354) (1392:1392:1392)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1973:1973:1973) (1981:1981:1981)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1796:1796:1796) (1779:1779:1779)) + (PORT D (1231:1231:1231) (1313:1313:1313)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1796:1796:1796) (1779:1779:1779)) + (PORT d (974:974:974) (1030:1030:1030)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1969:1969:1969) (1974:1974:1974)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1798:1798:1798) (1784:1784:1784)) + (PORT D (889:889:889) (929:929:929)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1798:1798:1798) (1784:1784:1784)) + (PORT d (1304:1304:1304) (1383:1383:1383)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1971:1971:1971) (1979:1979:1979)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1800:1800:1800) (1786:1786:1786)) + (PORT D (892:892:892) (931:931:931)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1800:1800:1800) (1786:1786:1786)) + (PORT d (1334:1334:1334) (1412:1412:1412)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1973:1973:1973) (1981:1981:1981)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_min_1200mv_0c_fast.vo b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_min_1200mv_0c_fast.vo new file mode 100644 index 0000000..62b371e --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_min_1200mv_0c_fast.vo @@ -0,0 +1,11443 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:17:19" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module hdmi_colorbar ( + sys_clk, + sys_rst_n, + ddc_scl, + ddc_sda, + tmds_clk_p, + tmds_clk_n, + tmds_data_p, + tmds_data_n); +input sys_clk; +input sys_rst_n; +output ddc_scl; +output ddc_sda; +output tmds_clk_p; +output tmds_clk_n; +output [2:0] tmds_data_p; +output [2:0] tmds_data_n; + +// Design Ports Information +// ddc_scl => Location: PIN_N22, I/O Standard: 2.5 V, Current Strength: Default +// ddc_sda => Location: PIN_R22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_clk_p => Location: PIN_H21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_clk_n => Location: PIN_H22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_p[0] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_p[1] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_p[2] => Location: PIN_D21, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_n[0] => Location: PIN_F22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_n[1] => Location: PIN_E22, I/O Standard: 2.5 V, Current Strength: Default +// tmds_data_n[2] => Location: PIN_D22, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("hdmi_colorbar_min_1200mv_0c_v_fast.sdo"); +// synopsys translate_on + +wire \hdmi_ctrl_inst|encode_inst0|Add20~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add20~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~7 ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~8_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add23~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~7 ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~8_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~7 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~7 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~7 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~8_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add22~6_combout ; +wire \vga_ctrl_inst|Add0~2_combout ; +wire \vga_ctrl_inst|Add0~10_combout ; +wire \vga_ctrl_inst|Add1~2_combout ; +wire \vga_ctrl_inst|Add1~6_combout ; +wire \vga_ctrl_inst|Add1~8_combout ; +wire \vga_ctrl_inst|Add1~10_combout ; +wire \vga_ctrl_inst|Add1~12_combout ; +wire \vga_ctrl_inst|Add1~14_combout ; +wire \vga_ctrl_inst|Add1~16_combout ; +wire \vga_ctrl_inst|Add1~18_combout ; +wire \vga_ctrl_inst|Add1~20_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|condition_3~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_3~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~3_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~5_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~7_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~8_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~11_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~12_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~16_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add12~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~5_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~7_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~13_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~14_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~16_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~3_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~9_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~10_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~11_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~12_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~13_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~16_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add14~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~3_combout ; +wire \vga_ctrl_inst|pix_data_req~0_combout ; +wire \vga_ctrl_inst|pix_data_req~3_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~5_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~5_combout ; +wire \vga_ctrl_inst|pix_x[10]~1_combout ; +wire \vga_pic_inst|always0~1_combout ; +wire \vga_pic_inst|always0~2_combout ; +wire \vga_pic_inst|pix_data[9]~14_combout ; +wire \vga_pic_inst|pix_data~16_combout ; +wire \vga_ctrl_inst|pix_data_req~8_combout ; +wire \vga_ctrl_inst|cnt_v[10]~12_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout ; +wire \vga_pic_inst|LessThan10~0_combout ; +wire \vga_pic_inst|pix_data~22_combout ; +wire \vga_pic_inst|pix_data~23_combout ; +wire \vga_pic_inst|LessThan14~1_combout ; +wire \vga_pic_inst|pix_data[13]~24_combout ; +wire \vga_pic_inst|pix_data~25_combout ; +wire \hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~5_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~8_combout ; +wire \hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~8_combout ; +wire \vga_pic_inst|pix_data~37_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~1 ; +wire \vga_ctrl_inst|Add0~3 ; +wire \vga_ctrl_inst|Add0~5 ; +wire \vga_ctrl_inst|Add0~6_combout ; +wire \vga_ctrl_inst|Add0~7 ; +wire \vga_ctrl_inst|Add0~8_combout ; +wire \vga_ctrl_inst|Add0~9 ; +wire \vga_ctrl_inst|Add0~11 ; +wire \vga_ctrl_inst|Add0~12_combout ; +wire \vga_ctrl_inst|Add0~13 ; +wire \vga_ctrl_inst|Add0~14_combout ; +wire \vga_ctrl_inst|Add0~4_combout ; +wire \vga_ctrl_inst|Equal0~0_combout ; +wire \vga_ctrl_inst|Add0~15 ; +wire \vga_ctrl_inst|Add0~16_combout ; +wire \vga_ctrl_inst|Add0~19 ; +wire \vga_ctrl_inst|Add0~20_combout ; +wire \vga_ctrl_inst|Add0~21 ; +wire \vga_ctrl_inst|Add0~22_combout ; +wire \vga_ctrl_inst|Equal0~1_combout ; +wire \vga_ctrl_inst|cnt_h~0_combout ; +wire \vga_ctrl_inst|Equal0~2_combout ; +wire \vga_ctrl_inst|cnt_h~2_combout ; +wire \vga_ctrl_inst|Add0~17 ; +wire \vga_ctrl_inst|Add0~18_combout ; +wire \vga_ctrl_inst|cnt_h~1_combout ; +wire \vga_ctrl_inst|LessThan4~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ; +wire \vga_ctrl_inst|Add2~1_cout ; +wire \vga_ctrl_inst|Add2~3_cout ; +wire \vga_ctrl_inst|Add2~5_cout ; +wire \vga_ctrl_inst|Add2~7_cout ; +wire \vga_ctrl_inst|Add2~9_cout ; +wire \vga_ctrl_inst|Add2~11 ; +wire \vga_ctrl_inst|Add2~13 ; +wire \vga_ctrl_inst|Add2~15 ; +wire \vga_ctrl_inst|Add2~17 ; +wire \vga_ctrl_inst|Add2~18_combout ; +wire \vga_ctrl_inst|Add2~16_combout ; +wire \vga_ctrl_inst|Add2~14_combout ; +wire \vga_pic_inst|pix_data~12_combout ; +wire \vga_ctrl_inst|Add2~12_combout ; +wire \vga_ctrl_inst|pix_data_req~5_combout ; +wire \vga_ctrl_inst|Equal0~3_combout ; +wire \vga_ctrl_inst|cnt_v[7]~7_combout ; +wire \vga_ctrl_inst|cnt_v[5]~10_combout ; +wire \vga_ctrl_inst|cnt_v[8]~6_combout ; +wire \vga_ctrl_inst|always1~0_combout ; +wire \vga_ctrl_inst|cnt_v[1]~1_combout ; +wire \vga_ctrl_inst|cnt_v[4]~5_combout ; +wire \vga_ctrl_inst|always1~1_combout ; +wire \vga_ctrl_inst|Add1~0_combout ; +wire \vga_ctrl_inst|cnt_v[0]~2_combout ; +wire \vga_ctrl_inst|cnt_v[3]~3_combout ; +wire \vga_ctrl_inst|always1~2_combout ; +wire \vga_ctrl_inst|cnt_v[11]~0_combout ; +wire \vga_ctrl_inst|cnt_v[9]~9_combout ; +wire \vga_ctrl_inst|cnt_v[6]~8_combout ; +wire \vga_ctrl_inst|Add1~1 ; +wire \vga_ctrl_inst|Add1~3 ; +wire \vga_ctrl_inst|Add1~4_combout ; +wire \vga_ctrl_inst|cnt_v[2]~4_combout ; +wire \vga_ctrl_inst|Add1~5 ; +wire \vga_ctrl_inst|Add1~7 ; +wire \vga_ctrl_inst|Add1~9 ; +wire \vga_ctrl_inst|Add1~11 ; +wire \vga_ctrl_inst|Add1~13 ; +wire \vga_ctrl_inst|Add1~15 ; +wire \vga_ctrl_inst|Add1~17 ; +wire \vga_ctrl_inst|Add1~19 ; +wire \vga_ctrl_inst|Add1~21 ; +wire \vga_ctrl_inst|Add1~22_combout ; +wire \vga_ctrl_inst|cnt_v[11]~11_combout ; +wire \vga_ctrl_inst|pix_data_req~2_combout ; +wire \vga_ctrl_inst|pix_data_req~4_combout ; +wire \vga_ctrl_inst|pix_data_req~6_combout ; +wire \vga_ctrl_inst|pix_data_req~7_combout ; +wire \vga_pic_inst|pix_data[13]~11_combout ; +wire \vga_pic_inst|always0~0_combout ; +wire \vga_pic_inst|pix_data~13_combout ; +wire \vga_pic_inst|pix_data~17_combout ; +wire \vga_pic_inst|pix_data~34_combout ; +wire \vga_pic_inst|pix_data[13]~8_combout ; +wire \vga_pic_inst|pix_data[13]~9_combout ; +wire \vga_pic_inst|pix_data[13]~10_combout ; +wire \vga_pic_inst|pix_data~18_combout ; +wire \vga_ctrl_inst|Add2~19 ; +wire \vga_ctrl_inst|Add2~20_combout ; +wire \vga_ctrl_inst|Add2~10_combout ; +wire \vga_pic_inst|LessThan17~4_combout ; +wire \vga_pic_inst|LessThan17~3_combout ; +wire \vga_pic_inst|LessThan14~0_combout ; +wire \vga_pic_inst|pix_data~19_combout ; +wire \vga_pic_inst|pix_data~20_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add6~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout ; +wire \vga_ctrl_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|pix_data_req~1_combout ; +wire \vga_ctrl_inst|rgb[1]~0_combout ; +wire \vga_ctrl_inst|rgb[2]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add14~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~1 ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~3 ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~5 ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~9_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~10_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add19~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add12~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add22~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add14~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~13_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~14_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add15~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add17~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~15_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Equal2~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add4~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|de_reg1~q ; +wire \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|de_reg2~q ; +wire \hdmi_ctrl_inst|encode_inst0|condition_2~combout ; +wire \hdmi_ctrl_inst|encode_inst0|Add16~6_combout ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[3]~14 ; +wire \hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout ; +wire \hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout ; +wire \vga_ctrl_inst|LessThan0~0_combout ; +wire \vga_ctrl_inst|LessThan0~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c0_reg1~q ; +wire \hdmi_ctrl_inst|encode_inst2|c0_reg2~q ; +wire \hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~4_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout ; +wire \vga_ctrl_inst|LessThan1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c1_reg1~q ; +wire \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c1_reg2~q ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~7_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|encode_inst0|data_out~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout ; +wire \vga_pic_inst|LessThan17~2_combout ; +wire \vga_pic_inst|pix_data[9]~15_combout ; +wire \vga_pic_inst|pix_data~35_combout ; +wire \vga_pic_inst|pix_data~36_combout ; +wire \vga_pic_inst|pix_data~21_combout ; +wire \vga_pic_inst|pix_data~26_combout ; +wire \vga_ctrl_inst|pix_x[11]~0_combout ; +wire \vga_pic_inst|pix_data~27_combout ; +wire \vga_ctrl_inst|rgb[10]~2_combout ; +wire \vga_pic_inst|pix_data~29_combout ; +wire \vga_pic_inst|pix_data~30_combout ; +wire \vga_pic_inst|pix_data~31_combout ; +wire \vga_ctrl_inst|rgb[6]~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add5~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add14~1_combout ; +wire \vga_pic_inst|pix_data~28_combout ; +wire \vga_ctrl_inst|rgb[7]~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add13~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add13~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_3~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add19~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add14~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add14~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add17~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~9_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~10_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~15_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal1~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add15~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add20~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add23~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~4_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_2~combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~11_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~12_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~1 ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~3 ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~5 ; +wire \hdmi_ctrl_inst|encode_inst1|Add22~6_combout ; +wire \hdmi_ctrl_inst|encode_inst1|Add16~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[3]~14 ; +wire \hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout ; +wire \hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~1_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~3_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|encode_inst1|data_out~7_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout ; +wire \vga_pic_inst|pix_data~33_combout ; +wire \vga_ctrl_inst|rgb[13]~6_combout ; +wire \vga_pic_inst|pix_data~32_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add6~0_combout ; +wire \vga_ctrl_inst|rgb[12]~5_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add12~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add14~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add12~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~5_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Equal1~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~15_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_2~combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add19~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~14_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add15~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~7_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~8_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~1 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~7 ; +wire \hdmi_ctrl_inst|encode_inst2|Add17~8_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add23~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~3 ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~5 ; +wire \hdmi_ctrl_inst|encode_inst2|Add20~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|Add16~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[3]~14 ; +wire \hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout ; +wire \hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~4_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out~7_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout ; +wire \hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout ; +wire \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout ; +wire \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout ; +wire [9:0] \hdmi_ctrl_inst|encode_inst0|data_out ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [11:0] \vga_ctrl_inst|cnt_v ; +wire [11:0] \vga_ctrl_inst|cnt_h ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s ; +wire [7:0] \hdmi_ctrl_inst|encode_inst0|data_in_reg ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [8:0] \hdmi_ctrl_inst|encode_inst0|q_m_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst0|q_m_n1 ; +wire [15:0] \vga_pic_inst|pix_data ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [3:0] \hdmi_ctrl_inst|encode_inst0|data_in_n1 ; +wire [2:0] \hdmi_ctrl_inst|par_to_ser_inst0|cnt ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [3:0] \hdmi_ctrl_inst|encode_inst0|q_m_n0 ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [4:0] \hdmi_ctrl_inst|encode_inst0|cnt ; +wire [4:0] \hdmi_ctrl_inst|encode_inst1|cnt ; +wire [9:0] \hdmi_ctrl_inst|encode_inst1|data_out ; +wire [8:0] \hdmi_ctrl_inst|encode_inst1|q_m_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst1|q_m_n0 ; +wire [3:0] \hdmi_ctrl_inst|encode_inst1|q_m_n1 ; +wire [7:0] \hdmi_ctrl_inst|encode_inst1|data_in_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst1|data_in_n1 ; +wire [4:0] \hdmi_ctrl_inst|encode_inst2|cnt ; +wire [9:0] \hdmi_ctrl_inst|encode_inst2|data_out ; +wire [8:0] \hdmi_ctrl_inst|encode_inst2|q_m_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst2|q_m_n0 ; +wire [3:0] \hdmi_ctrl_inst|encode_inst2|q_m_n1 ; +wire [7:0] \hdmi_ctrl_inst|encode_inst2|data_in_reg ; +wire [3:0] \hdmi_ctrl_inst|encode_inst2|data_in_n1 ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s ; +wire [4:0] \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s ; +wire [0:0] \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 10; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 10; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 5; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 10; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 3334; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 250; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: FF_X40_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N7 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N9 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y22_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y23_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y23_N13 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((GND) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add20~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add20~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~0 .lut_mask = 16'h66BB; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst0|Add20~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// ((\hdmi_ctrl_inst|encode_inst0|Add20~1 ) # (GND))))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|Add20~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst0|Add20~1 )))) +// \hdmi_ctrl_inst|encode_inst0|Add20~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((!\hdmi_ctrl_inst|encode_inst0|Add20~1 ) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst0|Add20~1 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add20~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add20~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~2 .lut_mask = 16'h692B; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~4_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst0|Add20~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst0|Add20~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add20~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst0|Add20~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add20~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add20~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add20~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add20~6_combout = !\hdmi_ctrl_inst|encode_inst0|Add20~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add20~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add20~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add20~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst0|Add20~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add17~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [0] & \hdmi_ctrl_inst|encode_inst0|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|Add17~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst0|Add17~1 )))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (!\hdmi_ctrl_inst|encode_inst0|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & ((\hdmi_ctrl_inst|encode_inst0|Add17~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|Add17~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & !\hdmi_ctrl_inst|encode_inst0|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & +// ((!\hdmi_ctrl_inst|encode_inst0|Add17~1 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~4_combout = ((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] $ (\hdmi_ctrl_inst|encode_inst0|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst0|Add17~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|Add17~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst0|Add17~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst0|Add17~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~6_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [3] & (!\hdmi_ctrl_inst|encode_inst0|Add17~5 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & ((\hdmi_ctrl_inst|encode_inst0|Add17~5 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add17~7 = CARRY((!\hdmi_ctrl_inst|encode_inst0|Add17~5 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add17~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~6 .lut_mask = 16'h3C3F; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add17~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add17~8_combout = \hdmi_ctrl_inst|encode_inst0|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst0|Add17~7 ) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add17~7 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add17~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add17~8 .lut_mask = 16'hC3C3; +defparam \hdmi_ctrl_inst|encode_inst0|Add17~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]) # (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add23~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add23~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~0 .lut_mask = 16'h66DD; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst0|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// (\hdmi_ctrl_inst|encode_inst0|Add23~1 & VCC)))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst0|Add23~1 ) # (GND))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst0|Add23~1 )))) +// \hdmi_ctrl_inst|encode_inst0|Add23~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst0|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & +// ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst0|Add23~1 )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add23~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add23~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~2 .lut_mask = 16'h694D; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~4_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst0|Add23~3 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst0|Add23~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add23~5 = CARRY((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst0|Add23~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add23~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add23~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~4 .lut_mask = 16'h5A05; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add23~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add23~6_combout = !\hdmi_ctrl_inst|encode_inst0|Add23~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add23~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add23~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add23~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst0|Add23~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [0] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add15~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [0] & \hdmi_ctrl_inst|encode_inst0|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|Add15~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst0|Add15~1 )))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst0|cnt [1] & (!\hdmi_ctrl_inst|encode_inst0|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & ((\hdmi_ctrl_inst|encode_inst0|Add15~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|Add15~3 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & !\hdmi_ctrl_inst|encode_inst0|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1] & +// ((!\hdmi_ctrl_inst|encode_inst0|Add15~1 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~4_combout = ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] $ (\hdmi_ctrl_inst|encode_inst0|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst0|Add15~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|Add15~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst0|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst0|Add15~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst0|Add15~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~6_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|cnt [3] & (\hdmi_ctrl_inst|encode_inst0|Add15~5 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & +// (!\hdmi_ctrl_inst|encode_inst0|Add15~5 )))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|cnt [3] & (!\hdmi_ctrl_inst|encode_inst0|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & ((\hdmi_ctrl_inst|encode_inst0|Add15~5 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|Add15~7 = CARRY((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & !\hdmi_ctrl_inst|encode_inst0|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & +// ((!\hdmi_ctrl_inst|encode_inst0|Add15~5 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add15~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~6 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add15~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add15~8_combout = \hdmi_ctrl_inst|encode_inst0|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst0|Add15~7 ) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add15~7 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add15~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add15~8 .lut_mask = 16'hC3C3; +defparam \hdmi_ctrl_inst|encode_inst0|Add15~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~4_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [3] & (\hdmi_ctrl_inst|encode_inst0|Add19~3 $ (GND))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & (!\hdmi_ctrl_inst|encode_inst0|Add19~3 & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add19~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [3] & !\hdmi_ctrl_inst|encode_inst0|Add19~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add19~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add19~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~4 .lut_mask = 16'hA50A; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~4_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst0|Add22~3 ))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & (\hdmi_ctrl_inst|encode_inst0|Add22~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add22~5 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [3]) # (!\hdmi_ctrl_inst|encode_inst0|Add22~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add22~3 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add22~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[0]~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & (\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & +// (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & +// ((\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|cnt[0]~8 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~16_combout & +// ((!\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ) # (!\hdmi_ctrl_inst|encode_inst0|Add16~15_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~16_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~15_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[0]~7_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~7 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[1]~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout = ((\hdmi_ctrl_inst|encode_inst0|Add16~12_combout $ (\hdmi_ctrl_inst|encode_inst0|Add16~14_combout $ (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|cnt[1]~10 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~12_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~14_combout ) # (!\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~12_combout & +// (\hdmi_ctrl_inst|encode_inst0|Add16~14_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~12_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[0]~8 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[1]~9_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1]~9 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[1]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[2]~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & (\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & +// (!\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & (!\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & +// ((\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst0|cnt[2]~12 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst0|Add16~8_combout & +// ((!\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ) # (!\hdmi_ctrl_inst|encode_inst0|Add16~10_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[1]~10 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[2]~11_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2]~11 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[2]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y22_N31 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((GND) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add20~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add20~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~0 .lut_mask = 16'h66BB; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|Add20~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// ((\hdmi_ctrl_inst|encode_inst1|Add20~1 ) # (GND))))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|Add20~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst1|Add20~1 )))) +// \hdmi_ctrl_inst|encode_inst1|Add20~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((!\hdmi_ctrl_inst|encode_inst1|Add20~1 ) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst1|Add20~1 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add20~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add20~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~2 .lut_mask = 16'h692B; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~4_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst1|Add20~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst1|Add20~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add20~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst1|Add20~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add20~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add20~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~4 .lut_mask = 16'h3CCF; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add20~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add20~6_combout = !\hdmi_ctrl_inst|encode_inst1|Add20~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add20~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add20~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add20~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst1|Add20~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~0_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add17~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [0] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~2_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst1|Add17~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & +// (!\hdmi_ctrl_inst|encode_inst1|Add17~1 )))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst1|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & +// ((\hdmi_ctrl_inst|encode_inst1|Add17~1 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|Add17~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [1] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst1|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((!\hdmi_ctrl_inst|encode_inst1|Add17~1 ) +// # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~4_combout = ((\hdmi_ctrl_inst|encode_inst1|cnt [2] $ (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] $ (!\hdmi_ctrl_inst|encode_inst1|Add17~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|Add17~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]) # (!\hdmi_ctrl_inst|encode_inst1|Add17~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 +// [2] & !\hdmi_ctrl_inst|encode_inst1|Add17~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~6_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & (!\hdmi_ctrl_inst|encode_inst1|Add17~5 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|Add17~5 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add17~7 = CARRY((!\hdmi_ctrl_inst|encode_inst1|Add17~5 ) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add17~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~6 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add17~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add17~8_combout = \hdmi_ctrl_inst|encode_inst1|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst1|Add17~7 ) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add17~7 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add17~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add17~8 .lut_mask = 16'hA5A5; +defparam \hdmi_ctrl_inst|encode_inst1|Add17~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]) # (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add23~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add23~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~0 .lut_mask = 16'h66DD; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~4_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst1|Add23~3 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst1|Add23~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add23~5 = CARRY((!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst1|Add23~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add23~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add23~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~4 .lut_mask = 16'h3C03; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~6_combout = !\hdmi_ctrl_inst|encode_inst1|Add23~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add23~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst1|cnt [1] & (\hdmi_ctrl_inst|encode_inst1|Add15~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst1|Add15~1 )))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst1|cnt [1] & (!\hdmi_ctrl_inst|encode_inst1|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & ((\hdmi_ctrl_inst|encode_inst1|Add15~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|Add15~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & !\hdmi_ctrl_inst|encode_inst1|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & +// ((!\hdmi_ctrl_inst|encode_inst1|Add15~1 ) # (!\hdmi_ctrl_inst|encode_inst1|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~6_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst1|Add15~5 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & +// (!\hdmi_ctrl_inst|encode_inst1|Add15~5 )))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst1|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & +// ((\hdmi_ctrl_inst|encode_inst1|Add15~5 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|Add15~7 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [3] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst1|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((!\hdmi_ctrl_inst|encode_inst1|Add15~5 ) +// # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~6 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~8_combout = \hdmi_ctrl_inst|encode_inst1|cnt [4] $ (!\hdmi_ctrl_inst|encode_inst1|Add15~7 ) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~7 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~8 .lut_mask = 16'hA5A5; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|cnt [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|cnt [1] & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add19~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & \hdmi_ctrl_inst|encode_inst1|cnt [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add19~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~2_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [2] & (!\hdmi_ctrl_inst|encode_inst1|Add19~1 )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & ((\hdmi_ctrl_inst|encode_inst1|Add19~1 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add19~3 = CARRY((!\hdmi_ctrl_inst|encode_inst1|Add19~1 ) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add19~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add19~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~2 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~4_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & (\hdmi_ctrl_inst|encode_inst1|Add19~3 $ (GND))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & (!\hdmi_ctrl_inst|encode_inst1|Add19~3 & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add19~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [3] & !\hdmi_ctrl_inst|encode_inst1|Add19~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add19~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add19~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~4 .lut_mask = 16'hA50A; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add19~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add19~6_combout = \hdmi_ctrl_inst|encode_inst1|Add19~5 $ (\hdmi_ctrl_inst|encode_inst1|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst1|Add19~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add19~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add19~6 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add19~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & ((\hdmi_ctrl_inst|encode_inst1|cnt [1]) # (GND))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|cnt [1] $ (VCC))) +// \hdmi_ctrl_inst|encode_inst1|Add22~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]) # (\hdmi_ctrl_inst|encode_inst1|cnt [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add22~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~0 .lut_mask = 16'h99EE; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~2_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|Add22~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & (!\hdmi_ctrl_inst|encode_inst1|Add22~1 )) +// \hdmi_ctrl_inst|encode_inst1|Add22~3 = CARRY((!\hdmi_ctrl_inst|encode_inst1|cnt [2] & !\hdmi_ctrl_inst|encode_inst1|Add22~1 )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add22~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add22~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~2 .lut_mask = 16'hA505; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~4_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst1|Add22~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & (\hdmi_ctrl_inst|encode_inst1|Add22~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst1|Add22~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [3]) # (!\hdmi_ctrl_inst|encode_inst1|Add22~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add22~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add22~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y23_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((GND) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add20~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add20~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~0 .lut_mask = 16'h66BB; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~4_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst2|Add20~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst2|Add20~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add20~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst2|Add20~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add20~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add20~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~4 .lut_mask = 16'h3CCF; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~0_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [0] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [0] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add17~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [0] & \hdmi_ctrl_inst|encode_inst2|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|Add17~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst2|Add17~1 )))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (!\hdmi_ctrl_inst|encode_inst2|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & ((\hdmi_ctrl_inst|encode_inst2|Add17~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|Add17~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & !\hdmi_ctrl_inst|encode_inst2|Add17~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & +// ((!\hdmi_ctrl_inst|encode_inst2|Add17~1 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~4_combout = ((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] $ (\hdmi_ctrl_inst|encode_inst2|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst2|Add17~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|Add17~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst2|Add17~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst2|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst2|Add17~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~6_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [3] & (!\hdmi_ctrl_inst|encode_inst2|Add17~5 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & ((\hdmi_ctrl_inst|encode_inst2|Add17~5 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add17~7 = CARRY((!\hdmi_ctrl_inst|encode_inst2|Add17~5 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add17~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~6 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]) # (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add23~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add23~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~0 .lut_mask = 16'h66DD; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~4_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst2|Add23~3 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (\hdmi_ctrl_inst|encode_inst2|Add23~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add23~5 = CARRY((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & !\hdmi_ctrl_inst|encode_inst2|Add23~3 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add23~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add23~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~4 .lut_mask = 16'h3C03; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|Add15~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & +// (!\hdmi_ctrl_inst|encode_inst2|Add15~1 )))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & ((\hdmi_ctrl_inst|encode_inst2|cnt [1] & (!\hdmi_ctrl_inst|encode_inst2|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & ((\hdmi_ctrl_inst|encode_inst2|Add15~1 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|Add15~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & !\hdmi_ctrl_inst|encode_inst2|Add15~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & +// ((!\hdmi_ctrl_inst|encode_inst2|Add15~1 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~2 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~4_combout = ((\hdmi_ctrl_inst|encode_inst2|cnt [2] $ (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] $ (!\hdmi_ctrl_inst|encode_inst2|Add15~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|Add15~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst2|Add15~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 +// [2] & !\hdmi_ctrl_inst|encode_inst2|Add15~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~6_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst2|cnt [3] & (\hdmi_ctrl_inst|encode_inst2|Add15~5 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & +// (!\hdmi_ctrl_inst|encode_inst2|Add15~5 )))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst2|cnt [3] & (!\hdmi_ctrl_inst|encode_inst2|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & ((\hdmi_ctrl_inst|encode_inst2|Add15~5 +// ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|Add15~7 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & !\hdmi_ctrl_inst|encode_inst2|Add15~5 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3] & +// ((!\hdmi_ctrl_inst|encode_inst2|Add15~5 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~6_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~7 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~6 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~8_combout = \hdmi_ctrl_inst|encode_inst2|Add15~7 $ (!\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add15~7 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~8 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~2_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [2] & (!\hdmi_ctrl_inst|encode_inst2|Add19~1 )) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2] & ((\hdmi_ctrl_inst|encode_inst2|Add19~1 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add19~3 = CARRY((!\hdmi_ctrl_inst|encode_inst2|Add19~1 ) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add19~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add19~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~2 .lut_mask = 16'h3C3F; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~4_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [3] & (\hdmi_ctrl_inst|encode_inst2|Add19~3 $ (GND))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & (!\hdmi_ctrl_inst|encode_inst2|Add19~3 & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add19~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [3] & !\hdmi_ctrl_inst|encode_inst2|Add19~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add19~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add19~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~4 .lut_mask = 16'hA50A; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~6_combout = \hdmi_ctrl_inst|encode_inst2|Add19~5 $ (\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add19~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~6 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~0_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [1] & ((\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]) # (GND))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] $ (VCC))) +// \hdmi_ctrl_inst|encode_inst2|Add22~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [1]) # (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add22~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~0 .lut_mask = 16'h99EE; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~2_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|Add22~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|cnt [2] & (!\hdmi_ctrl_inst|encode_inst2|Add22~1 )) +// \hdmi_ctrl_inst|encode_inst2|Add22~3 = CARRY((!\hdmi_ctrl_inst|encode_inst2|cnt [2] & !\hdmi_ctrl_inst|encode_inst2|Add22~1 )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add22~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add22~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~2 .lut_mask = 16'hC303; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~4_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [3] & ((GND) # (!\hdmi_ctrl_inst|encode_inst2|Add22~3 ))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & (\hdmi_ctrl_inst|encode_inst2|Add22~3 $ (GND))) +// \hdmi_ctrl_inst|encode_inst2|Add22~5 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [3]) # (!\hdmi_ctrl_inst|encode_inst2|Add22~3 )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add22~3 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add22~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~4 .lut_mask = 16'h5AAF; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add22~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add22~6_combout = \hdmi_ctrl_inst|encode_inst2|Add22~5 $ (!\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add22~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add22~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add22~6 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst2|Add22~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y24_N11 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y22_N19 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [6]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y21_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [7]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~2 ( +// Equation(s): +// \vga_ctrl_inst|Add0~2_combout = (\vga_ctrl_inst|cnt_h [1] & (!\vga_ctrl_inst|Add0~1 )) # (!\vga_ctrl_inst|cnt_h [1] & ((\vga_ctrl_inst|Add0~1 ) # (GND))) +// \vga_ctrl_inst|Add0~3 = CARRY((!\vga_ctrl_inst|Add0~1 ) # (!\vga_ctrl_inst|cnt_h [1])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~1 ), + .combout(\vga_ctrl_inst|Add0~2_combout ), + .cout(\vga_ctrl_inst|Add0~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~10 ( +// Equation(s): +// \vga_ctrl_inst|Add0~10_combout = (\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|Add0~9 )) # (!\vga_ctrl_inst|cnt_h [5] & ((\vga_ctrl_inst|Add0~9 ) # (GND))) +// \vga_ctrl_inst|Add0~11 = CARRY((!\vga_ctrl_inst|Add0~9 ) # (!\vga_ctrl_inst|cnt_h [5])) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~9 ), + .combout(\vga_ctrl_inst|Add0~10_combout ), + .cout(\vga_ctrl_inst|Add0~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~2 ( +// Equation(s): +// \vga_ctrl_inst|Add1~2_combout = (\vga_ctrl_inst|cnt_v [1] & (!\vga_ctrl_inst|Add1~1 )) # (!\vga_ctrl_inst|cnt_v [1] & ((\vga_ctrl_inst|Add1~1 ) # (GND))) +// \vga_ctrl_inst|Add1~3 = CARRY((!\vga_ctrl_inst|Add1~1 ) # (!\vga_ctrl_inst|cnt_v [1])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~1 ), + .combout(\vga_ctrl_inst|Add1~2_combout ), + .cout(\vga_ctrl_inst|Add1~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~6 ( +// Equation(s): +// \vga_ctrl_inst|Add1~6_combout = (\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|Add1~5 )) # (!\vga_ctrl_inst|cnt_v [3] & ((\vga_ctrl_inst|Add1~5 ) # (GND))) +// \vga_ctrl_inst|Add1~7 = CARRY((!\vga_ctrl_inst|Add1~5 ) # (!\vga_ctrl_inst|cnt_v [3])) + + .dataa(\vga_ctrl_inst|cnt_v [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~5 ), + .combout(\vga_ctrl_inst|Add1~6_combout ), + .cout(\vga_ctrl_inst|Add1~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~6 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~8 ( +// Equation(s): +// \vga_ctrl_inst|Add1~8_combout = (\vga_ctrl_inst|cnt_v [4] & (\vga_ctrl_inst|Add1~7 $ (GND))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|Add1~7 & VCC)) +// \vga_ctrl_inst|Add1~9 = CARRY((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Add1~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~7 ), + .combout(\vga_ctrl_inst|Add1~8_combout ), + .cout(\vga_ctrl_inst|Add1~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~10 ( +// Equation(s): +// \vga_ctrl_inst|Add1~10_combout = (\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|Add1~9 )) # (!\vga_ctrl_inst|cnt_v [5] & ((\vga_ctrl_inst|Add1~9 ) # (GND))) +// \vga_ctrl_inst|Add1~11 = CARRY((!\vga_ctrl_inst|Add1~9 ) # (!\vga_ctrl_inst|cnt_v [5])) + + .dataa(\vga_ctrl_inst|cnt_v [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~9 ), + .combout(\vga_ctrl_inst|Add1~10_combout ), + .cout(\vga_ctrl_inst|Add1~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~12 ( +// Equation(s): +// \vga_ctrl_inst|Add1~12_combout = (\vga_ctrl_inst|cnt_v [6] & (\vga_ctrl_inst|Add1~11 $ (GND))) # (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|Add1~11 & VCC)) +// \vga_ctrl_inst|Add1~13 = CARRY((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Add1~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~11 ), + .combout(\vga_ctrl_inst|Add1~12_combout ), + .cout(\vga_ctrl_inst|Add1~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~14 ( +// Equation(s): +// \vga_ctrl_inst|Add1~14_combout = (\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|Add1~13 )) # (!\vga_ctrl_inst|cnt_v [7] & ((\vga_ctrl_inst|Add1~13 ) # (GND))) +// \vga_ctrl_inst|Add1~15 = CARRY((!\vga_ctrl_inst|Add1~13 ) # (!\vga_ctrl_inst|cnt_v [7])) + + .dataa(\vga_ctrl_inst|cnt_v [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~13 ), + .combout(\vga_ctrl_inst|Add1~14_combout ), + .cout(\vga_ctrl_inst|Add1~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~16 ( +// Equation(s): +// \vga_ctrl_inst|Add1~16_combout = (\vga_ctrl_inst|cnt_v [8] & (\vga_ctrl_inst|Add1~15 $ (GND))) # (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|Add1~15 & VCC)) +// \vga_ctrl_inst|Add1~17 = CARRY((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Add1~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~15 ), + .combout(\vga_ctrl_inst|Add1~16_combout ), + .cout(\vga_ctrl_inst|Add1~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~18 ( +// Equation(s): +// \vga_ctrl_inst|Add1~18_combout = (\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|Add1~17 )) # (!\vga_ctrl_inst|cnt_v [9] & ((\vga_ctrl_inst|Add1~17 ) # (GND))) +// \vga_ctrl_inst|Add1~19 = CARRY((!\vga_ctrl_inst|Add1~17 ) # (!\vga_ctrl_inst|cnt_v [9])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~17 ), + .combout(\vga_ctrl_inst|Add1~18_combout ), + .cout(\vga_ctrl_inst|Add1~19 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~18 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~20 ( +// Equation(s): +// \vga_ctrl_inst|Add1~20_combout = (\vga_ctrl_inst|cnt_v [10] & (\vga_ctrl_inst|Add1~19 $ (GND))) # (!\vga_ctrl_inst|cnt_v [10] & (!\vga_ctrl_inst|Add1~19 & VCC)) +// \vga_ctrl_inst|Add1~21 = CARRY((\vga_ctrl_inst|cnt_v [10] & !\vga_ctrl_inst|Add1~19 )) + + .dataa(\vga_ctrl_inst|cnt_v [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~19 ), + .combout(\vga_ctrl_inst|Add1~20_combout ), + .cout(\vga_ctrl_inst|Add1~21 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~20 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X40_Y20_N11 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y20_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [2] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1 .lut_mask = 16'h00F0; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N15 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add12~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_3~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_3~1_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (((\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_3~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~1 .lut_mask = 16'h0A8E; +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal1~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal1~0_combout = (!\hdmi_ctrl_inst|encode_inst0|cnt [4] & (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & (!\hdmi_ctrl_inst|encode_inst0|cnt [2] & !\hdmi_ctrl_inst|encode_inst0|cnt [0]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~0 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N27 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y24_N19 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n0[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add14~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_3~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_3~1_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & \hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]) # ((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & \hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_3~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~1 .lut_mask = 16'h4F04; +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N31 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]) # (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2 .lut_mask = 16'hFFF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~0_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst0|Add17~8_combout ) # (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add23~6_combout & ((!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add23~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add17~8_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~0 .lut_mask = 16'hCCE2; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~1_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add15~8_combout ) # ((!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~0_combout +// & (((\hdmi_ctrl_inst|encode_inst0|Add20~6_combout & \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~8_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add20~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~1 .lut_mask = 16'hD8AA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~3_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|Add17~6_combout ))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add23~4_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add23~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add17~6_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~3 .lut_mask = 16'hF2C2; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~4_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~3_combout & (((\hdmi_ctrl_inst|encode_inst0|Add15~6_combout ) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~3_combout +// & (\hdmi_ctrl_inst|encode_inst0|Add20~4_combout & ((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add20~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add16~3_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~4 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~5_combout = (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst0|Add19~4_combout ))) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst0|Add22~4_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add22~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add19~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~5 .lut_mask = 16'h3210; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~7_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst0|Add20~2_combout )) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add23~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add20~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add23~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~7 .lut_mask = 16'hFA0C; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~8_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~7_combout & ((\hdmi_ctrl_inst|encode_inst0|Add15~4_combout ) # ((!\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~7_combout +// & (((\hdmi_ctrl_inst|encode_inst0|Add17~4_combout & \hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~7_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add17~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~8 .lut_mask = 16'hD8AA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~11_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|Add17~2_combout ) # ((\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst0|Add23~0_combout & !\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add17~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add23~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~11_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~11 .lut_mask = 16'hF0AC; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~12 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~12_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~11_combout & ((\hdmi_ctrl_inst|encode_inst0|Add15~2_combout ) # ((!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst0|Add16~11_combout & (((\hdmi_ctrl_inst|encode_inst0|Add20~0_combout & \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~11_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add20~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~12_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~12 .lut_mask = 16'hD8AA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~16 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~16_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|cnt [0]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .datad(\hdmi_ctrl_inst|encode_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~16_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~16 .lut_mask = 16'h5F0A; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal1~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal1~1_combout = (!\hdmi_ctrl_inst|encode_inst0|cnt [3] & \hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~1 .lut_mask = 16'h0F00; +defparam \hdmi_ctrl_inst|encode_inst0|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add12~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add12~1_combout = (!\hdmi_ctrl_inst|encode_inst0|data_in_reg [4] & \hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add12~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add12~1 .lut_mask = 16'h3300; +defparam \hdmi_ctrl_inst|encode_inst0|Add12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N7 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~2_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [3] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_reg [3]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~2 .lut_mask = 16'h995A; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [4])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [3]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out [4]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [3]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2 .lut_mask = 16'hACAC; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~0_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add17~8_combout ) # (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add23~6_combout & ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add23~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add17~8_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~0 .lut_mask = 16'hAAE4; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~1_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~0_combout & ((\hdmi_ctrl_inst|encode_inst1|Add15~8_combout ) # ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~0_combout +// & (((\hdmi_ctrl_inst|encode_inst1|Add20~6_combout & \hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add15~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add20~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~1 .lut_mask = 16'hACF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~5_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3])))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add22~4_combout & (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add22~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~5 .lut_mask = 16'hA4AE; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~6_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~5_combout ) # ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & \hdmi_ctrl_inst|encode_inst1|Add19~4_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add19~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~5_combout ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~6 .lut_mask = 16'hF8F8; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~7_combout = (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add22~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add22~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~7 .lut_mask = 16'hAF44; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~8_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~7_combout & (((!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~7_combout & +// (\hdmi_ctrl_inst|encode_inst1|Add19~2_combout & (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add19~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~7_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~8 .lut_mask = 16'h2CEC; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~13_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add17~2_combout ) # (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add23~0_combout & ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add23~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add17~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~13_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~13 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~14 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~14_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~13_combout & (((\hdmi_ctrl_inst|encode_inst1|Add15~2_combout ) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|Add16~13_combout & (\hdmi_ctrl_inst|encode_inst1|Add20~0_combout & ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add20~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~13_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add15~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~14_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~14 .lut_mask = 16'hE2CC; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~16 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~16_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst1|cnt [0]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~16_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~16 .lut_mask = 16'h3F0C; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal2~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal2~1_combout = (\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout & !\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~1 .lut_mask = 16'h00AA; +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N31 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y21_N1 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~2_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [2] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~2 .lut_mask = 16'hA53C; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~2_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout ) # ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst2|Add19~6_combout )) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst2|Add22~6_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add19~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add22~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~2 .lut_mask = 16'hFAFC; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~3_combout = (\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|Add17~6_combout )) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|Add23~4_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add17~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|Add23~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~3 .lut_mask = 16'hE3E0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~4_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~3_combout & ((\hdmi_ctrl_inst|encode_inst2|Add15~6_combout ) # ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~3_combout +// & (((\hdmi_ctrl_inst|encode_inst2|Add20~4_combout & \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add15~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add20~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~3_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~4 .lut_mask = 16'hACF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~9_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2])))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|Add22~2_combout & ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add22~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~9_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~9 .lut_mask = 16'hAA4E; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~10 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~10_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~9_combout & (((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2])))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~9_combout & +// (\hdmi_ctrl_inst|encode_inst2|Add19~2_combout & ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add19~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~9_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~10_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~10 .lut_mask = 16'h3AF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~11_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|Add17~2_combout ) # (\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|Add23~0_combout & ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add23~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add17~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~11_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~11 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~12 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~12_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~11_combout & (((\hdmi_ctrl_inst|encode_inst2|Add15~2_combout ) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst2|Add16~11_combout & (\hdmi_ctrl_inst|encode_inst2|Add20~0_combout & ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add20~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add15~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~11_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~12_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~12 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~13_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|Add22~0_combout & !\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|Add22~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~13_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~13 .lut_mask = 16'hAA72; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~16 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~16_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (\hdmi_ctrl_inst|encode_inst2|cnt [0])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~16_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~16 .lut_mask = 16'h0FCC; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal2~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal2~1_combout = (\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout & !\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~1 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add14~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add14~1_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3] & (\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] $ (!\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add14~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add14~1 .lut_mask = 16'hC00C; +defparam \hdmi_ctrl_inst|encode_inst2|Add14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N25 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~2_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [3] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~2 .lut_mask = 16'h939C; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~3_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~3 .lut_mask = 16'hF303; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~0_combout = (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|cnt_v [8]))) + + .dataa(\vga_ctrl_inst|cnt_v [9]), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|cnt_v [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N31 +dffeas \vga_ctrl_inst|cnt_v[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[10]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[10] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~3 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~3_combout = (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~2_combout & ((\vga_ctrl_inst|always1~0_combout ) # (!\vga_ctrl_inst|cnt_v [9])))) + + .dataa(\vga_ctrl_inst|pix_data_req~1_combout ), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|always1~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~3 .lut_mask = 16'hA200; +defparam \vga_ctrl_inst|pix_data_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout = \hdmi_ctrl_inst|encode_inst0|data_in_reg [3] $ (\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m[3]~0 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst0|q_m[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~5_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [4] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~5 .lut_mask = 16'h995A; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N19 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [6])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [6]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N31 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y21_N27 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [7])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [4]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [7]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [4]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N21 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~4_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [4] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_reg [4]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~4 .lut_mask = 16'hA53C; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout = \hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] $ (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m[3]~0 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst2|q_m[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N9 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~5_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [4] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~5 .lut_mask = 16'hC366; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y20_N11 +dffeas \vga_ctrl_inst|cnt_h[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|pix_x[10]~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_x[10]~1_combout = (\vga_ctrl_inst|Add2~18_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~18_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_x[10]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_x[10]~1 .lut_mask = 16'hFF0F; +defparam \vga_ctrl_inst|pix_x[10]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N10 +cycloneive_lcell_comb \vga_pic_inst|always0~1 ( +// Equation(s): +// \vga_pic_inst|always0~1_combout = (\vga_ctrl_inst|Add2~14_combout ) # ((\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout )) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|always0~1 .lut_mask = 16'hFFAF; +defparam \vga_pic_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N12 +cycloneive_lcell_comb \vga_pic_inst|always0~2 ( +// Equation(s): +// \vga_pic_inst|always0~2_combout = (\vga_pic_inst|always0~1_combout ) # ((\vga_ctrl_inst|Add2~18_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (\vga_pic_inst|LessThan17~2_combout ))) + + .dataa(\vga_pic_inst|always0~1_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|LessThan17~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|always0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|always0~2 .lut_mask = 16'hFFFE; +defparam \vga_pic_inst|always0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N6 +cycloneive_lcell_comb \vga_pic_inst|pix_data[9]~14 ( +// Equation(s): +// \vga_pic_inst|pix_data[9]~14_combout = (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_ctrl_inst|Add2~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[9]~14_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9]~14 .lut_mask = 16'h00F0; +defparam \vga_pic_inst|pix_data[9]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~16 ( +// Equation(s): +// \vga_pic_inst|pix_data~16_combout = (\vga_pic_inst|always0~2_combout & (!\vga_pic_inst|pix_data[9]~15_combout & (!\vga_ctrl_inst|pix_x[11]~0_combout & \vga_pic_inst|pix_data[13]~9_combout ))) + + .dataa(\vga_pic_inst|always0~2_combout ), + .datab(\vga_pic_inst|pix_data[9]~15_combout ), + .datac(\vga_ctrl_inst|pix_x[11]~0_combout ), + .datad(\vga_pic_inst|pix_data[13]~9_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~16 .lut_mask = 16'h0200; +defparam \vga_pic_inst|pix_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~8 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~8_combout = (!\vga_ctrl_inst|cnt_v [11] & !\vga_ctrl_inst|cnt_v [10]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [11]), + .datac(\vga_ctrl_inst|cnt_v [10]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~8 .lut_mask = 16'h0303; +defparam \vga_ctrl_inst|pix_data_req~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[10]~12 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[10]~12_combout = (\vga_ctrl_inst|Add1~20_combout & (((!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|cnt_v [10])) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~20_combout & (!\vga_ctrl_inst|Equal0~3_combout +// & (\vga_ctrl_inst|cnt_v [10]))) + + .dataa(\vga_ctrl_inst|Add1~20_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [10]), + .datad(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[10]~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[10]~12 .lut_mask = 16'h30BA; +defparam \vga_ctrl_inst|cnt_v[10]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m[4]~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout = \hdmi_ctrl_inst|encode_inst0|data_in_reg [4] $ (\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m[4]~2 .lut_mask = 16'h3C3C; +defparam \hdmi_ctrl_inst|encode_inst0|q_m[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[6]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[6]~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6]~6 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[6]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N23 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout = (\hdmi_ctrl_inst|encode_inst0|data_out [8] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out [8]), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4 .lut_mask = 16'hA0A0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N22 +cycloneive_lcell_comb \vga_pic_inst|LessThan10~0 ( +// Equation(s): +// \vga_pic_inst|LessThan10~0_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~16_combout & ((\vga_pic_inst|LessThan17~2_combout ) # (!\vga_ctrl_inst|Add2~14_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_pic_inst|LessThan17~2_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan10~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan10~0 .lut_mask = 16'h080A; +defparam \vga_pic_inst|LessThan10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data~22 ( +// Equation(s): +// \vga_pic_inst|pix_data~22_combout = (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_ctrl_inst|Add2~10_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~22 .lut_mask = 16'h00F0; +defparam \vga_pic_inst|pix_data~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~23 ( +// Equation(s): +// \vga_pic_inst|pix_data~23_combout = (!\vga_ctrl_inst|Add2~14_combout & (\vga_pic_inst|pix_data~22_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_ctrl_inst|Add2~12_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_pic_inst|pix_data~22_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~23_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~23 .lut_mask = 16'h0400; +defparam \vga_pic_inst|pix_data~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N20 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~1 ( +// Equation(s): +// \vga_pic_inst|LessThan14~1_combout = (\vga_ctrl_inst|Add2~12_combout & \vga_ctrl_inst|Add2~10_combout ) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~1 .lut_mask = 16'hAA00; +defparam \vga_pic_inst|LessThan14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~24 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~24_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_pic_inst|LessThan14~1_combout & (!\vga_ctrl_inst|Add2~16_combout & !\vga_ctrl_inst|Add2~14_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_pic_inst|LessThan14~1_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~24_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~24 .lut_mask = 16'h0002; +defparam \vga_pic_inst|pix_data[13]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N8 +cycloneive_lcell_comb \vga_pic_inst|pix_data~25 ( +// Equation(s): +// \vga_pic_inst|pix_data~25_combout = (!\vga_ctrl_inst|pix_x[10]~1_combout & ((\vga_pic_inst|pix_data~23_combout ) # ((\vga_pic_inst|LessThan10~0_combout & !\vga_pic_inst|pix_data[13]~24_combout )))) + + .dataa(\vga_pic_inst|LessThan10~0_combout ), + .datab(\vga_ctrl_inst|pix_x[10]~1_combout ), + .datac(\vga_pic_inst|pix_data[13]~24_combout ), + .datad(\vga_pic_inst|pix_data~23_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~25_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~25 .lut_mask = 16'h3302; +defparam \vga_pic_inst|pix_data~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|q_m[5]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout = \hdmi_ctrl_inst|encode_inst1|data_in_reg [4] $ (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|q_m[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m[5]~0 .lut_mask = 16'hC33C; +defparam \hdmi_ctrl_inst|encode_inst1|q_m[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[7] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~5_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [7] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [7]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~5 .lut_mask = 16'h9A56; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N9 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [9]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[9] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout = (\hdmi_ctrl_inst|encode_inst1|data_out [9] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [9]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4 .lut_mask = 16'hC0C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m[4]~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout = \hdmi_ctrl_inst|encode_inst2|data_in_reg [3] $ (\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m[4]~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m[4]~2 .lut_mask = 16'h33CC; +defparam \hdmi_ctrl_inst|encode_inst2|q_m[4]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N23 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout = (\hdmi_ctrl_inst|encode_inst2|data_out [8] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [8]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4 .lut_mask = 16'h8888; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~8_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~8 .lut_mask = 16'h8D8D; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|q_m[7]~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout = \hdmi_ctrl_inst|encode_inst1|data_in_reg [7] $ (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|q_m[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m[7]~1 .lut_mask = 16'hC33C; +defparam \hdmi_ctrl_inst|encode_inst1|q_m[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~6_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst2|c1_reg2~q $ +// ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~6 .lut_mask = 16'hEB41; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~8_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~8 .lut_mask = 16'hB1B1; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~37 ( +// Equation(s): +// \vga_pic_inst|pix_data~37_combout = ((!\vga_ctrl_inst|Add2~18_combout & (\vga_ctrl_inst|pix_data_req~7_combout & \vga_pic_inst|pix_data~23_combout ))) # (!\vga_pic_inst|pix_data~16_combout ) + + .dataa(\vga_pic_inst|pix_data~16_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data~23_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~37_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~37 .lut_mask = 16'h7555; +defparam \vga_pic_inst|pix_data~37 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~2_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~2_combout + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder .lut_mask = 16'hAAAA; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~2_combout + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder .lut_mask = 16'hAAAA; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~5_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~5_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~4_combout + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out~4_combout ), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder .lut_mask = 16'hCCCC; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~5_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out~5_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~5_combout + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out~5_combout ), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder .lut_mask = 16'hAAAA; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N16 +cycloneive_io_obuf \ddc_scl~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(ddc_scl), + .obar()); +// synopsys translate_off +defparam \ddc_scl~output .bus_hold = "false"; +defparam \ddc_scl~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y10_N16 +cycloneive_io_obuf \ddc_sda~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(ddc_sda), + .obar()); +// synopsys translate_off +defparam \ddc_sda~output .bus_hold = "false"; +defparam \ddc_sda~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y21_N23 +cycloneive_io_obuf \tmds_clk_p~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_clk_p), + .obar()); +// synopsys translate_off +defparam \tmds_clk_p~output .bus_hold = "false"; +defparam \tmds_clk_p~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y20_N2 +cycloneive_io_obuf \tmds_clk_n~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_clk_n), + .obar()); +// synopsys translate_off +defparam \tmds_clk_n~output .bus_hold = "false"; +defparam \tmds_clk_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y22_N16 +cycloneive_io_obuf \tmds_data_p[0]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_p[0]), + .obar()); +// synopsys translate_off +defparam \tmds_data_p[0]~output .bus_hold = "false"; +defparam \tmds_data_p[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y23_N9 +cycloneive_io_obuf \tmds_data_p[1]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_p[1]), + .obar()); +// synopsys translate_off +defparam \tmds_data_p[1]~output .bus_hold = "false"; +defparam \tmds_data_p[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y24_N2 +cycloneive_io_obuf \tmds_data_p[2]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_p[2]), + .obar()); +// synopsys translate_off +defparam \tmds_data_p[2]~output .bus_hold = "false"; +defparam \tmds_data_p[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y22_N23 +cycloneive_io_obuf \tmds_data_n[0]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_n[0]), + .obar()); +// synopsys translate_off +defparam \tmds_data_n[0]~output .bus_hold = "false"; +defparam \tmds_data_n[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y23_N16 +cycloneive_io_obuf \tmds_data_n[1]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_n[1]), + .obar()); +// synopsys translate_off +defparam \tmds_data_n[1]~output .bus_hold = "false"; +defparam \tmds_data_n[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y24_N9 +cycloneive_io_obuf \tmds_data_n[2]~output ( + .i(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tmds_data_n[2]), + .obar()); +// synopsys translate_off +defparam \tmds_data_n[2]~output .bus_hold = "false"; +defparam \tmds_data_n[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout = (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0 .lut_mask = 16'h0303; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|cnt~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout = \hdmi_ctrl_inst|par_to_ser_inst0|cnt [1] $ (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N19 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout = \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] $ (((\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [1]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0 .lut_mask = 16'h3CF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N17 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|Add0~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [1] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [1]), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0 .lut_mask = 16'h00AA; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout = \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N31 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) # (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [4]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [4]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3 .lut_mask = 16'hFCFC; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N5 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [3]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2 .lut_mask = 16'h00F0; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [2] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N29 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [1] & !\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [1]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N23 +dffeas \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y21_N25 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y20_N4 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~0 ( +// Equation(s): +// \vga_ctrl_inst|Add0~0_combout = \vga_ctrl_inst|cnt_h [0] $ (VCC) +// \vga_ctrl_inst|Add0~1 = CARRY(\vga_ctrl_inst|cnt_h [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add0~0_combout ), + .cout(\vga_ctrl_inst|Add0~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y26_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X40_Y26_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y26_N18 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) # (!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q )) # (!\sys_rst_n~input_o ) + + .dataa(\sys_rst_n~input_o ), + .datab(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .datac(gnd), + .datad(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h77FF; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G7 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X37_Y20_N9 +dffeas \vga_ctrl_inst|cnt_h[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~4 ( +// Equation(s): +// \vga_ctrl_inst|Add0~4_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|Add0~3 $ (GND))) # (!\vga_ctrl_inst|cnt_h [2] & (!\vga_ctrl_inst|Add0~3 & VCC)) +// \vga_ctrl_inst|Add0~5 = CARRY((\vga_ctrl_inst|cnt_h [2] & !\vga_ctrl_inst|Add0~3 )) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~3 ), + .combout(\vga_ctrl_inst|Add0~4_combout ), + .cout(\vga_ctrl_inst|Add0~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~6 ( +// Equation(s): +// \vga_ctrl_inst|Add0~6_combout = (\vga_ctrl_inst|cnt_h [3] & (!\vga_ctrl_inst|Add0~5 )) # (!\vga_ctrl_inst|cnt_h [3] & ((\vga_ctrl_inst|Add0~5 ) # (GND))) +// \vga_ctrl_inst|Add0~7 = CARRY((!\vga_ctrl_inst|Add0~5 ) # (!\vga_ctrl_inst|cnt_h [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~5 ), + .combout(\vga_ctrl_inst|Add0~6_combout ), + .cout(\vga_ctrl_inst|Add0~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N15 +dffeas \vga_ctrl_inst|cnt_h[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~8 ( +// Equation(s): +// \vga_ctrl_inst|Add0~8_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Add0~7 $ (GND))) # (!\vga_ctrl_inst|cnt_h [4] & (!\vga_ctrl_inst|Add0~7 & VCC)) +// \vga_ctrl_inst|Add0~9 = CARRY((\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add0~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~7 ), + .combout(\vga_ctrl_inst|Add0~8_combout ), + .cout(\vga_ctrl_inst|Add0~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N17 +dffeas \vga_ctrl_inst|cnt_h[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~12 ( +// Equation(s): +// \vga_ctrl_inst|Add0~12_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add0~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add0~11 & VCC)) +// \vga_ctrl_inst|Add0~13 = CARRY((\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add0~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~11 ), + .combout(\vga_ctrl_inst|Add0~12_combout ), + .cout(\vga_ctrl_inst|Add0~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N21 +dffeas \vga_ctrl_inst|cnt_h[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~14 ( +// Equation(s): +// \vga_ctrl_inst|Add0~14_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add0~13 )) # (!\vga_ctrl_inst|cnt_h [7] & ((\vga_ctrl_inst|Add0~13 ) # (GND))) +// \vga_ctrl_inst|Add0~15 = CARRY((!\vga_ctrl_inst|Add0~13 ) # (!\vga_ctrl_inst|cnt_h [7])) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~13 ), + .combout(\vga_ctrl_inst|Add0~14_combout ), + .cout(\vga_ctrl_inst|Add0~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N23 +dffeas \vga_ctrl_inst|cnt_h[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X37_Y20_N13 +dffeas \vga_ctrl_inst|cnt_h[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~0 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~0_combout = (\vga_ctrl_inst|cnt_h [1] & (\vga_ctrl_inst|cnt_h [3] & (\vga_ctrl_inst|cnt_h [0] & \vga_ctrl_inst|cnt_h [2]))) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(\vga_ctrl_inst|cnt_h [0]), + .datad(\vga_ctrl_inst|cnt_h [2]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~0 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~16 ( +// Equation(s): +// \vga_ctrl_inst|Add0~16_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add0~15 $ (GND))) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add0~15 & VCC)) +// \vga_ctrl_inst|Add0~17 = CARRY((\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add0~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~15 ), + .combout(\vga_ctrl_inst|Add0~16_combout ), + .cout(\vga_ctrl_inst|Add0~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~18 ( +// Equation(s): +// \vga_ctrl_inst|Add0~18_combout = (\vga_ctrl_inst|cnt_h [9] & (!\vga_ctrl_inst|Add0~17 )) # (!\vga_ctrl_inst|cnt_h [9] & ((\vga_ctrl_inst|Add0~17 ) # (GND))) +// \vga_ctrl_inst|Add0~19 = CARRY((!\vga_ctrl_inst|Add0~17 ) # (!\vga_ctrl_inst|cnt_h [9])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [9]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~17 ), + .combout(\vga_ctrl_inst|Add0~18_combout ), + .cout(\vga_ctrl_inst|Add0~19 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~18 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~20 ( +// Equation(s): +// \vga_ctrl_inst|Add0~20_combout = (\vga_ctrl_inst|cnt_h [10] & (\vga_ctrl_inst|Add0~19 $ (GND))) # (!\vga_ctrl_inst|cnt_h [10] & (!\vga_ctrl_inst|Add0~19 & VCC)) +// \vga_ctrl_inst|Add0~21 = CARRY((\vga_ctrl_inst|cnt_h [10] & !\vga_ctrl_inst|Add0~19 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~19 ), + .combout(\vga_ctrl_inst|Add0~20_combout ), + .cout(\vga_ctrl_inst|Add0~21 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~20 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N29 +dffeas \vga_ctrl_inst|cnt_h[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[10] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~22 ( +// Equation(s): +// \vga_ctrl_inst|Add0~22_combout = \vga_ctrl_inst|cnt_h [11] $ (\vga_ctrl_inst|Add0~21 ) + + .dataa(\vga_ctrl_inst|cnt_h [11]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\vga_ctrl_inst|Add0~21 ), + .combout(\vga_ctrl_inst|Add0~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~22 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y20_N31 +dffeas \vga_ctrl_inst|cnt_h[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [11]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[11] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~1 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~1_combout = (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|cnt_h [10] & (!\vga_ctrl_inst|cnt_h [11] & \vga_ctrl_inst|cnt_h [9]))) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(\vga_ctrl_inst|cnt_h [11]), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~1 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N24 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~0_combout = (\vga_ctrl_inst|Add0~10_combout & (((!\vga_ctrl_inst|Equal0~2_combout ) # (!\vga_ctrl_inst|Equal0~1_combout )) # (!\vga_ctrl_inst|Equal0~0_combout ))) + + .dataa(\vga_ctrl_inst|Add0~10_combout ), + .datab(\vga_ctrl_inst|Equal0~0_combout ), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~0 .lut_mask = 16'h2AAA; +defparam \vga_ctrl_inst|cnt_h~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y21_N25 +dffeas \vga_ctrl_inst|cnt_h[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~2 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~2_combout = (\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|cnt_h [5] & (\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [6]))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [5]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~2 .lut_mask = 16'h0020; +defparam \vga_ctrl_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~2_combout = (\vga_ctrl_inst|Add0~16_combout & (((!\vga_ctrl_inst|Equal0~2_combout ) # (!\vga_ctrl_inst|Equal0~0_combout )) # (!\vga_ctrl_inst|Equal0~1_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|Add0~16_combout ), + .datac(\vga_ctrl_inst|Equal0~0_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~2 .lut_mask = 16'h4CCC; +defparam \vga_ctrl_inst|cnt_h~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y20_N3 +dffeas \vga_ctrl_inst|cnt_h[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~1_combout = (\vga_ctrl_inst|Add0~18_combout & (((!\vga_ctrl_inst|Equal0~2_combout ) # (!\vga_ctrl_inst|Equal0~0_combout )) # (!\vga_ctrl_inst|Equal0~1_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|Equal0~0_combout ), + .datac(\vga_ctrl_inst|Add0~18_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~1 .lut_mask = 16'h70F0; +defparam \vga_ctrl_inst|cnt_h~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y20_N1 +dffeas \vga_ctrl_inst|cnt_h[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan4~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan4~0_combout = (!\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [6])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [5]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan4~0 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add4~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add4~0_combout = (\vga_ctrl_inst|cnt_h [8] & (((!\vga_ctrl_inst|cnt_h [7] & \vga_ctrl_inst|LessThan4~0_combout )) # (!\vga_ctrl_inst|cnt_h [9]))) # (!\vga_ctrl_inst|cnt_h [8] & ((\vga_ctrl_inst|cnt_h [9]) # +// ((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|LessThan4~0_combout )))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(\vga_ctrl_inst|LessThan4~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add4~0 .lut_mask = 16'h7A5E; +defparam \hdmi_ctrl_inst|encode_inst0|Add4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~1 ( +// Equation(s): +// \vga_ctrl_inst|Add2~1_cout = CARRY((\vga_ctrl_inst|cnt_h [1] & \vga_ctrl_inst|cnt_h [0])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\vga_ctrl_inst|Add2~1_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~1 .lut_mask = 16'h0088; +defparam \vga_ctrl_inst|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~3 ( +// Equation(s): +// \vga_ctrl_inst|Add2~3_cout = CARRY((!\vga_ctrl_inst|Add2~1_cout ) # (!\vga_ctrl_inst|cnt_h [2])) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~1_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~3_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~3 .lut_mask = 16'h005F; +defparam \vga_ctrl_inst|Add2~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~5 ( +// Equation(s): +// \vga_ctrl_inst|Add2~5_cout = CARRY((\vga_ctrl_inst|cnt_h [3] & !\vga_ctrl_inst|Add2~3_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~3_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~5_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~5 .lut_mask = 16'h000A; +defparam \vga_ctrl_inst|Add2~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~7 ( +// Equation(s): +// \vga_ctrl_inst|Add2~7_cout = CARRY((!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add2~5_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~5_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~7_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~7 .lut_mask = 16'h0005; +defparam \vga_ctrl_inst|Add2~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~9 ( +// Equation(s): +// \vga_ctrl_inst|Add2~9_cout = CARRY((\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|Add2~7_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [5]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~7_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~9_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~9 .lut_mask = 16'h00CF; +defparam \vga_ctrl_inst|Add2~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~10 ( +// Equation(s): +// \vga_ctrl_inst|Add2~10_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add2~9_cout & VCC)) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add2~9_cout )) +// \vga_ctrl_inst|Add2~11 = CARRY((!\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add2~9_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~9_cout ), + .combout(\vga_ctrl_inst|Add2~10_combout ), + .cout(\vga_ctrl_inst|Add2~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~10 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~12 ( +// Equation(s): +// \vga_ctrl_inst|Add2~12_combout = (\vga_ctrl_inst|cnt_h [7] & (\vga_ctrl_inst|Add2~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add2~11 & VCC)) +// \vga_ctrl_inst|Add2~13 = CARRY((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|Add2~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~11 ), + .combout(\vga_ctrl_inst|Add2~12_combout ), + .cout(\vga_ctrl_inst|Add2~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~14 ( +// Equation(s): +// \vga_ctrl_inst|Add2~14_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add2~13 & VCC)) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add2~13 )) +// \vga_ctrl_inst|Add2~15 = CARRY((!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add2~13 )) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~13 ), + .combout(\vga_ctrl_inst|Add2~14_combout ), + .cout(\vga_ctrl_inst|Add2~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~14 .lut_mask = 16'hA505; +defparam \vga_ctrl_inst|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~16 ( +// Equation(s): +// \vga_ctrl_inst|Add2~16_combout = (\vga_ctrl_inst|cnt_h [9] & ((GND) # (!\vga_ctrl_inst|Add2~15 ))) # (!\vga_ctrl_inst|cnt_h [9] & (\vga_ctrl_inst|Add2~15 $ (GND))) +// \vga_ctrl_inst|Add2~17 = CARRY((\vga_ctrl_inst|cnt_h [9]) # (!\vga_ctrl_inst|Add2~15 )) + + .dataa(\vga_ctrl_inst|cnt_h [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~15 ), + .combout(\vga_ctrl_inst|Add2~16_combout ), + .cout(\vga_ctrl_inst|Add2~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~16 .lut_mask = 16'h5AAF; +defparam \vga_ctrl_inst|Add2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~18 ( +// Equation(s): +// \vga_ctrl_inst|Add2~18_combout = (\vga_ctrl_inst|cnt_h [10] & (\vga_ctrl_inst|Add2~17 & VCC)) # (!\vga_ctrl_inst|cnt_h [10] & (!\vga_ctrl_inst|Add2~17 )) +// \vga_ctrl_inst|Add2~19 = CARRY((!\vga_ctrl_inst|cnt_h [10] & !\vga_ctrl_inst|Add2~17 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~17 ), + .combout(\vga_ctrl_inst|Add2~18_combout ), + .cout(\vga_ctrl_inst|Add2~19 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~18 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~12 ( +// Equation(s): +// \vga_pic_inst|pix_data~12_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~18_combout & (\vga_ctrl_inst|Add2~16_combout & !\vga_ctrl_inst|Add2~14_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~12 .lut_mask = 16'h0020; +defparam \vga_pic_inst|pix_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~5 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~5_combout = \vga_ctrl_inst|cnt_h [8] $ (\vga_ctrl_inst|cnt_h [9]) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~5 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|pix_data_req~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N2 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~3 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~3_combout = (\vga_ctrl_inst|Equal0~1_combout & (\vga_ctrl_inst|Equal0~0_combout & \vga_ctrl_inst|Equal0~2_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Equal0~1_combout ), + .datac(\vga_ctrl_inst|Equal0~0_combout ), + .datad(\vga_ctrl_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~3 .lut_mask = 16'hC000; +defparam \vga_ctrl_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[7]~7 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[7]~7_combout = (\vga_ctrl_inst|Add1~14_combout & (((\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~14_combout & (((\vga_ctrl_inst|cnt_v [7] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~14_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7]~7 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N21 +dffeas \vga_ctrl_inst|cnt_v[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[7]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[5]~10 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[5]~10_combout = (\vga_ctrl_inst|Add1~10_combout & (((!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|cnt_v [5])) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~10_combout & (!\vga_ctrl_inst|Equal0~3_combout +// & (\vga_ctrl_inst|cnt_v [5]))) + + .dataa(\vga_ctrl_inst|Add1~10_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5]~10 .lut_mask = 16'h30BA; +defparam \vga_ctrl_inst|cnt_v[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N27 +dffeas \vga_ctrl_inst|cnt_v[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[5]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N18 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[8]~6 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[8]~6_combout = (\vga_ctrl_inst|Add1~16_combout & (((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~16_combout & (((\vga_ctrl_inst|cnt_v [8] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~16_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [8]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[8]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8]~6 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[8]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N19 +dffeas \vga_ctrl_inst|cnt_v[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[8]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|always1~0 ( +// Equation(s): +// \vga_ctrl_inst|always1~0_combout = (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|cnt_v [5] & !\vga_ctrl_inst|cnt_v [8]))) + + .dataa(\vga_ctrl_inst|cnt_v [6]), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|cnt_v [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N8 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[1]~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[1]~1_combout = (\vga_ctrl_inst|Add1~2_combout & (((\vga_ctrl_inst|cnt_v [1] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~2_combout & (((\vga_ctrl_inst|cnt_v [1] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~2_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1]~1 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N9 +dffeas \vga_ctrl_inst|cnt_v[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[1]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[4]~5 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[4]~5_combout = (\vga_ctrl_inst|Add1~8_combout & (((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~8_combout & (((\vga_ctrl_inst|cnt_v [4] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~8_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [4]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4]~5 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N1 +dffeas \vga_ctrl_inst|cnt_v[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[4]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N24 +cycloneive_lcell_comb \vga_ctrl_inst|always1~1 ( +// Equation(s): +// \vga_ctrl_inst|always1~1_combout = (\vga_ctrl_inst|pix_data_req~8_combout & (\vga_ctrl_inst|always1~0_combout & (!\vga_ctrl_inst|cnt_v [1] & !\vga_ctrl_inst|cnt_v [4]))) + + .dataa(\vga_ctrl_inst|pix_data_req~8_combout ), + .datab(\vga_ctrl_inst|always1~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~1 .lut_mask = 16'h0008; +defparam \vga_ctrl_inst|always1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~0 ( +// Equation(s): +// \vga_ctrl_inst|Add1~0_combout = \vga_ctrl_inst|cnt_v [0] $ (VCC) +// \vga_ctrl_inst|Add1~1 = CARRY(\vga_ctrl_inst|cnt_v [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add1~0_combout ), + .cout(\vga_ctrl_inst|Add1~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[0]~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[0]~2_combout = (\vga_ctrl_inst|cnt_v[11]~0_combout & (((\vga_ctrl_inst|cnt_v [0] & !\vga_ctrl_inst|Equal0~3_combout )))) # (!\vga_ctrl_inst|cnt_v[11]~0_combout & ((\vga_ctrl_inst|Add1~0_combout ) # ((\vga_ctrl_inst|cnt_v [0] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datab(\vga_ctrl_inst|Add1~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0]~2 .lut_mask = 16'h44F4; +defparam \vga_ctrl_inst|cnt_v[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N1 +dffeas \vga_ctrl_inst|cnt_v[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[0]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[3]~3 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[3]~3_combout = (\vga_ctrl_inst|Add1~6_combout & (((\vga_ctrl_inst|cnt_v [3] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~6_combout & (((\vga_ctrl_inst|cnt_v [3] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~6_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3]~3 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N3 +dffeas \vga_ctrl_inst|cnt_v[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[3]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|always1~2 ( +// Equation(s): +// \vga_ctrl_inst|always1~2_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [0] & \vga_ctrl_inst|cnt_v [3]))) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|cnt_v [3]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~2 .lut_mask = 16'h0800; +defparam \vga_ctrl_inst|always1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[11]~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[11]~0_combout = ((\vga_ctrl_inst|always1~1_combout & \vga_ctrl_inst|always1~2_combout )) # (!\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|always1~1_combout ), + .datac(\vga_ctrl_inst|always1~2_combout ), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[11]~0 .lut_mask = 16'hC0FF; +defparam \vga_ctrl_inst|cnt_v[11]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N16 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[9]~9 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[9]~9_combout = (\vga_ctrl_inst|Add1~18_combout & (((\vga_ctrl_inst|cnt_v [9] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~18_combout & (((\vga_ctrl_inst|cnt_v [9] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~18_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[9]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9]~9 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[9]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N17 +dffeas \vga_ctrl_inst|cnt_v[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[9]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N22 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[6]~8 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[6]~8_combout = (\vga_ctrl_inst|Add1~12_combout & (((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Equal0~3_combout )) # (!\vga_ctrl_inst|cnt_v[11]~0_combout ))) # (!\vga_ctrl_inst|Add1~12_combout & (((\vga_ctrl_inst|cnt_v [6] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|Add1~12_combout ), + .datab(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[6]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6]~8 .lut_mask = 16'h22F2; +defparam \vga_ctrl_inst|cnt_v[6]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N23 +dffeas \vga_ctrl_inst|cnt_v[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[6]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~4 ( +// Equation(s): +// \vga_ctrl_inst|Add1~4_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|Add1~3 $ (GND))) # (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|Add1~3 & VCC)) +// \vga_ctrl_inst|Add1~5 = CARRY((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Add1~3 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [2]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~3 ), + .combout(\vga_ctrl_inst|Add1~4_combout ), + .cout(\vga_ctrl_inst|Add1~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~4 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N12 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[2]~4 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[2]~4_combout = (\vga_ctrl_inst|cnt_v[11]~0_combout & (((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Equal0~3_combout )))) # (!\vga_ctrl_inst|cnt_v[11]~0_combout & ((\vga_ctrl_inst|Add1~4_combout ) # ((\vga_ctrl_inst|cnt_v [2] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datab(\vga_ctrl_inst|Add1~4_combout ), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2]~4 .lut_mask = 16'h44F4; +defparam \vga_ctrl_inst|cnt_v[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N13 +dffeas \vga_ctrl_inst|cnt_v[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[2]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~22 ( +// Equation(s): +// \vga_ctrl_inst|Add1~22_combout = \vga_ctrl_inst|Add1~21 $ (\vga_ctrl_inst|cnt_v [11]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [11]), + .cin(\vga_ctrl_inst|Add1~21 ), + .combout(\vga_ctrl_inst|Add1~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~22 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add1~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[11]~11 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[11]~11_combout = (\vga_ctrl_inst|cnt_v[11]~0_combout & (((\vga_ctrl_inst|cnt_v [11] & !\vga_ctrl_inst|Equal0~3_combout )))) # (!\vga_ctrl_inst|cnt_v[11]~0_combout & ((\vga_ctrl_inst|Add1~22_combout ) # ((\vga_ctrl_inst|cnt_v [11] & +// !\vga_ctrl_inst|Equal0~3_combout )))) + + .dataa(\vga_ctrl_inst|cnt_v[11]~0_combout ), + .datab(\vga_ctrl_inst|Add1~22_combout ), + .datac(\vga_ctrl_inst|cnt_v [11]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[11]~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[11]~11 .lut_mask = 16'h44F4; +defparam \vga_ctrl_inst|cnt_v[11]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X32_Y20_N29 +dffeas \vga_ctrl_inst|cnt_v[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[11]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [11]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[11] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~2 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~2_combout = (!\vga_ctrl_inst|cnt_v [10] & (!\vga_ctrl_inst|cnt_v [11] & (!\vga_ctrl_inst|cnt_h [11] & !\vga_ctrl_inst|cnt_h [10]))) + + .dataa(\vga_ctrl_inst|cnt_v [10]), + .datab(\vga_ctrl_inst|cnt_v [11]), + .datac(\vga_ctrl_inst|cnt_h [11]), + .datad(\vga_ctrl_inst|cnt_h [10]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~2 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~4 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~4_combout = (\vga_ctrl_inst|pix_data_req~2_combout & ((\vga_ctrl_inst|always1~0_combout ) # (!\vga_ctrl_inst|cnt_v [9]))) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|pix_data_req~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~4 .lut_mask = 16'hAF00; +defparam \vga_ctrl_inst|pix_data_req~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N2 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~6 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~6_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|cnt_h [9] & ((\vga_ctrl_inst|Equal0~0_combout ) # (!\vga_ctrl_inst|LessThan4~0_combout )))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Equal0~0_combout & +// (\vga_ctrl_inst|cnt_h [9] & \vga_ctrl_inst|LessThan4~0_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(\vga_ctrl_inst|LessThan4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~6 .lut_mask = 16'h180C; +defparam \vga_ctrl_inst|pix_data_req~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~7 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~7_combout = (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|pix_data_req~5_combout ) # (\vga_ctrl_inst|pix_data_req~6_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~1_combout ), + .datab(\vga_ctrl_inst|pix_data_req~5_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|pix_data_req~6_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~7 .lut_mask = 16'hA080; +defparam \vga_ctrl_inst|pix_data_req~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~11 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~11_combout = ((\vga_ctrl_inst|Add2~16_combout ) # ((\vga_ctrl_inst|Add2~14_combout & \vga_ctrl_inst|Add2~12_combout ))) # (!\vga_ctrl_inst|pix_data_req~7_combout ) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|pix_data_req~7_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~11 .lut_mask = 16'hFBF3; +defparam \vga_pic_inst|pix_data[13]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N6 +cycloneive_lcell_comb \vga_pic_inst|always0~0 ( +// Equation(s): +// \vga_pic_inst|always0~0_combout = (\vga_ctrl_inst|Add2~16_combout ) # ((\vga_ctrl_inst|Add2~18_combout ) # ((!\vga_pic_inst|pix_data[13]~11_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ))) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[13]~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|always0~0 .lut_mask = 16'hEFFF; +defparam \vga_pic_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~13 ( +// Equation(s): +// \vga_pic_inst|pix_data~13_combout = (\vga_pic_inst|LessThan14~0_combout & (((\vga_ctrl_inst|Add2~12_combout )) # (!\vga_pic_inst|pix_data~12_combout ))) # (!\vga_pic_inst|LessThan14~0_combout & (\vga_pic_inst|always0~0_combout & +// ((\vga_ctrl_inst|Add2~12_combout ) # (!\vga_pic_inst|pix_data~12_combout )))) + + .dataa(\vga_pic_inst|LessThan14~0_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_ctrl_inst|Add2~12_combout ), + .datad(\vga_pic_inst|always0~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~13 .lut_mask = 16'hF3A2; +defparam \vga_pic_inst|pix_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~17 ( +// Equation(s): +// \vga_pic_inst|pix_data~17_combout = (!\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_ctrl_inst|Add2~12_combout )) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~17_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~17 .lut_mask = 16'h0500; +defparam \vga_pic_inst|pix_data~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N10 +cycloneive_lcell_comb \vga_pic_inst|pix_data~34 ( +// Equation(s): +// \vga_pic_inst|pix_data~34_combout = ((!\vga_ctrl_inst|Add2~18_combout & (\vga_ctrl_inst|pix_data_req~7_combout & \vga_pic_inst|pix_data~17_combout ))) # (!\vga_pic_inst|pix_data~16_combout ) + + .dataa(\vga_pic_inst|pix_data~16_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data~17_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~34_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~34 .lut_mask = 16'h7555; +defparam \vga_pic_inst|pix_data~34 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N16 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~8 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~8_combout = (!\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|Add2~14_combout ) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~8 .lut_mask = 16'h55FF; +defparam \vga_pic_inst|pix_data[13]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~9 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~9_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~18_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_pic_inst|pix_data[13]~8_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|pix_data[13]~8_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~9 .lut_mask = 16'h0200; +defparam \vga_pic_inst|pix_data[13]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data[13]~10 ( +// Equation(s): +// \vga_pic_inst|pix_data[13]~10_combout = (!\vga_ctrl_inst|Add2~20_combout & (\vga_ctrl_inst|pix_data_req~7_combout & \vga_pic_inst|pix_data[13]~9_combout )) + + .dataa(\vga_ctrl_inst|Add2~20_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[13]~9_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[13]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13]~10 .lut_mask = 16'h5000; +defparam \vga_pic_inst|pix_data[13]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N8 +cycloneive_lcell_comb \vga_pic_inst|pix_data~18 ( +// Equation(s): +// \vga_pic_inst|pix_data~18_combout = ((!\vga_ctrl_inst|pix_x[11]~0_combout & (!\vga_pic_inst|pix_data~13_combout & !\vga_pic_inst|pix_data[13]~10_combout ))) # (!\vga_pic_inst|pix_data~34_combout ) + + .dataa(\vga_ctrl_inst|pix_x[11]~0_combout ), + .datab(\vga_pic_inst|pix_data~13_combout ), + .datac(\vga_pic_inst|pix_data~34_combout ), + .datad(\vga_pic_inst|pix_data[13]~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~18 .lut_mask = 16'h0F1F; +defparam \vga_pic_inst|pix_data~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N9 +dffeas \vga_pic_inst|pix_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~20 ( +// Equation(s): +// \vga_ctrl_inst|Add2~20_combout = \vga_ctrl_inst|Add2~19 $ (\vga_ctrl_inst|cnt_h [11]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [11]), + .cin(\vga_ctrl_inst|Add2~19 ), + .combout(\vga_ctrl_inst|Add2~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~20 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add2~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N28 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~4 ( +// Equation(s): +// \vga_pic_inst|LessThan17~4_combout = (!\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~10_combout & (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_ctrl_inst|Add2~12_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~4 .lut_mask = 16'h0010; +defparam \vga_pic_inst|LessThan17~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N20 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~3 ( +// Equation(s): +// \vga_pic_inst|LessThan17~3_combout = (!\vga_ctrl_inst|Add2~18_combout & (!\vga_ctrl_inst|Add2~20_combout & (\vga_ctrl_inst|Add2~16_combout & \vga_pic_inst|LessThan17~4_combout ))) + + .dataa(\vga_ctrl_inst|Add2~18_combout ), + .datab(\vga_ctrl_inst|Add2~20_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|LessThan17~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~3 .lut_mask = 16'h1000; +defparam \vga_pic_inst|LessThan17~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N14 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~0 ( +// Equation(s): +// \vga_pic_inst|LessThan14~0_combout = (\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~10_combout & \vga_ctrl_inst|Add2~12_combout )) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~10_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~0 .lut_mask = 16'hA000; +defparam \vga_pic_inst|LessThan14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~19 ( +// Equation(s): +// \vga_pic_inst|pix_data~19_combout = (\vga_pic_inst|LessThan17~3_combout ) # ((!\vga_ctrl_inst|pix_x[11]~0_combout & (!\vga_pic_inst|LessThan14~0_combout & !\vga_pic_inst|always0~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_x[11]~0_combout ), + .datab(\vga_pic_inst|LessThan17~3_combout ), + .datac(\vga_pic_inst|LessThan14~0_combout ), + .datad(\vga_pic_inst|always0~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~19_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~19 .lut_mask = 16'hCCCD; +defparam \vga_pic_inst|pix_data~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~20 ( +// Equation(s): +// \vga_pic_inst|pix_data~20_combout = ((!\vga_pic_inst|pix_data[13]~10_combout & \vga_pic_inst|pix_data~19_combout )) # (!\vga_pic_inst|pix_data~34_combout ) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data[13]~10_combout ), + .datac(\vga_pic_inst|pix_data~34_combout ), + .datad(\vga_pic_inst|pix_data~19_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~20 .lut_mask = 16'h3F0F; +defparam \vga_pic_inst|pix_data~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N19 +dffeas \vga_pic_inst|pix_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[0] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add6~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add6~0_combout = (\vga_ctrl_inst|pix_data_req~3_combout & (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_pic_inst|pix_data [4] & \vga_pic_inst|pix_data [0]))) + + .dataa(\vga_ctrl_inst|pix_data_req~3_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datac(\vga_pic_inst|pix_data [4]), + .datad(\vga_pic_inst|pix_data [0]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add6~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add6~0 .lut_mask = 16'h8000; +defparam \hdmi_ctrl_inst|encode_inst0|Add6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst0|data_in_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_in_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_in_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout = !\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0 .lut_mask = 16'h00FF; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N21 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X35_Y22_N27 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N30 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~0_combout = (!\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|cnt_v [2] & ((!\vga_ctrl_inst|cnt_v [1]) # (!\vga_ctrl_inst|cnt_v [0])))) + + .dataa(\vga_ctrl_inst|cnt_v [0]), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|cnt_v [2]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~0 .lut_mask = 16'h0013; +defparam \vga_ctrl_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N6 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~1_combout = (\vga_ctrl_inst|LessThan6~0_combout & ((\vga_ctrl_inst|cnt_v [4] & ((!\vga_ctrl_inst|always1~0_combout ))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|pix_data_req~0_combout )))) # +// (!\vga_ctrl_inst|LessThan6~0_combout & (((!\vga_ctrl_inst|always1~0_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~0_combout ), + .datab(\vga_ctrl_inst|always1~0_combout ), + .datac(\vga_ctrl_inst|LessThan6~0_combout ), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~1 .lut_mask = 16'h3353; +defparam \vga_ctrl_inst|pix_data_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N28 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[1]~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb[1]~0_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_pic_inst|pix_data [4] & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_pic_inst|pix_data [4]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[1]~0 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N29 +dffeas \hdmi_ctrl_inst|encode_inst0|data_in_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N30 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[2]~1 ( +// Equation(s): +// \vga_ctrl_inst|rgb[2]~1_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~1_combout & \vga_pic_inst|pix_data [0]))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\vga_pic_inst|pix_data [0]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[2]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[2]~1 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[2]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N31 +dffeas \hdmi_ctrl_inst|encode_inst0|data_in_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[2]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_in_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add14~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add14~0_combout = (\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]) # ((\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]) # (\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add14~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add14~0 .lut_mask = 16'hFFFC; +defparam \hdmi_ctrl_inst|encode_inst0|Add14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout = !\hdmi_ctrl_inst|encode_inst0|Add14~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|Add14~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0 .lut_mask = 16'h00FF; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N9 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n0[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] & VCC)) +// \hdmi_ctrl_inst|encode_inst0|Add19~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [1] & \hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add19~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~2_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [2] & (!\hdmi_ctrl_inst|encode_inst0|Add19~1 )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst0|Add19~1 ) # (GND))) +// \hdmi_ctrl_inst|encode_inst0|Add19~3 = CARRY((!\hdmi_ctrl_inst|encode_inst0|Add19~1 ) # (!\hdmi_ctrl_inst|encode_inst0|cnt [2])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add19~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add19~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~2 .lut_mask = 16'h5A5F; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add19~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add19~6_combout = \hdmi_ctrl_inst|encode_inst0|cnt [4] $ (\hdmi_ctrl_inst|encode_inst0|Add19~5 ) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst0|Add19~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add19~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add19~6 .lut_mask = 16'h3C3C; +defparam \hdmi_ctrl_inst|encode_inst0|Add19~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~0_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [1] & ((\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]) # (GND))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] $ (VCC))) +// \hdmi_ctrl_inst|encode_inst0|Add22~1 = CARRY((\hdmi_ctrl_inst|encode_inst0|cnt [1]) # (\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add22~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~0 .lut_mask = 16'h99EE; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~2_combout = (\hdmi_ctrl_inst|encode_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|Add22~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst0|cnt [2] & (!\hdmi_ctrl_inst|encode_inst0|Add22~1 )) +// \hdmi_ctrl_inst|encode_inst0|Add22~3 = CARRY((!\hdmi_ctrl_inst|encode_inst0|cnt [2] & !\hdmi_ctrl_inst|encode_inst0|Add22~1 )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|Add22~1 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|Add22~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~2 .lut_mask = 16'hA505; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add22~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add22~6_combout = \hdmi_ctrl_inst|encode_inst0|Add22~5 $ (!\hdmi_ctrl_inst|encode_inst0|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst0|Add22~5 ), + .combout(\hdmi_ctrl_inst|encode_inst0|Add22~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add22~6 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst0|Add22~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~2_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout ) # ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst0|Add19~6_combout )) # +// (!\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst0|Add22~6_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add19~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add22~6_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~2 .lut_mask = 16'hFBEA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[0]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0]~0 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N17 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n0[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add14~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~9_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add22~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add22~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~9_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~9 .lut_mask = 16'hAF44; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~10 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~10_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~9_combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2])) # (!\hdmi_ctrl_inst|encode_inst0|Add16~9_combout & +// ((\hdmi_ctrl_inst|encode_inst0|Add19~2_combout ))))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|Add16~9_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|Add19~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add16~9_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~10_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~10 .lut_mask = 16'h5FC0; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add12~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add12~0_combout = (\hdmi_ctrl_inst|encode_inst0|data_in_reg [3] & ((!\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]))) # (!\hdmi_ctrl_inst|encode_inst0|data_in_reg [3] & (\hdmi_ctrl_inst|encode_inst0|data_in_reg [4])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add12~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add12~0 .lut_mask = 16'h0CFC; +defparam \hdmi_ctrl_inst|encode_inst0|Add12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N29 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n1[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add12~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add14~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add14~1_combout = (\hdmi_ctrl_inst|encode_inst0|data_in_reg [3] & (\hdmi_ctrl_inst|encode_inst0|data_in_reg [4] $ (!\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_in_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add14~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add14~1 .lut_mask = 16'hC030; +defparam \hdmi_ctrl_inst|encode_inst0|Add14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N19 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n0[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add14~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n0[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~13_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (\hdmi_ctrl_inst|encode_inst0|Add22~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add22~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~13_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~13 .lut_mask = 16'hAF44; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~14 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~14_combout = (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~13_combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~13_combout & +// (\hdmi_ctrl_inst|encode_inst0|Add19~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst0|Add16~13_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add19~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add16~13_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~14_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~14 .lut_mask = 16'h5F88; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y22_N1 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_n1[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_n1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~15_combout = (\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] & ((\hdmi_ctrl_inst|encode_inst0|Add17~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8] & +// (\hdmi_ctrl_inst|encode_inst0|Add15~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add15~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst0|Add17~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~15 .lut_mask = 16'hA088; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal2~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])))) # +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] $ (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~0 .lut_mask = 16'h8421; +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Equal2~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Equal2~1_combout = (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~1 .lut_mask = 16'h0F00; +defparam \hdmi_ctrl_inst|encode_inst0|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[0]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout = CARRY((\hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ) # (\hdmi_ctrl_inst|encode_inst0|Equal2~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Equal1~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Equal2~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[0]~6_cout )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~6 .lut_mask = 16'h00EE; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[3]~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout = ((\hdmi_ctrl_inst|encode_inst0|Add16~4_combout $ (\hdmi_ctrl_inst|encode_inst0|Add16~6_combout $ (!\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst0|cnt[3]~14 = CARRY((\hdmi_ctrl_inst|encode_inst0|Add16~4_combout & ((\hdmi_ctrl_inst|encode_inst0|Add16~6_combout ) # (!\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ))) # (!\hdmi_ctrl_inst|encode_inst0|Add16~4_combout & +// (\hdmi_ctrl_inst|encode_inst0|Add16~6_combout & !\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add16~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[2]~12 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout ), + .cout(\hdmi_ctrl_inst|encode_inst0|cnt[3]~14 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3]~13 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add4~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add4~1_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout )) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add4~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add4~1 .lut_mask = 16'hA000; +defparam \hdmi_ctrl_inst|encode_inst0|Add4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N17 +dffeas \hdmi_ctrl_inst|encode_inst2|de_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|Add4~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|de_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|de_reg1 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|de_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout = \hdmi_ctrl_inst|encode_inst2|de_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|de_reg1~q ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N1 +dffeas \hdmi_ctrl_inst|encode_inst2|de_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|de_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|de_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y22_N13 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[3]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_2~combout = (\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout & (((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & \hdmi_ctrl_inst|encode_inst0|Equal2~0_combout )) # (!\hdmi_ctrl_inst|encode_inst0|cnt [3]))) # +// (!\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Equal1~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|Equal2~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_2 .lut_mask = 16'h3B0A; +defparam \hdmi_ctrl_inst|encode_inst0|condition_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|Add16~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|Add16~6_combout = (\hdmi_ctrl_inst|encode_inst0|Add16~5_combout ) # ((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]) # (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~5_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|Add16~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|Add16~6 .lut_mask = 16'hBFAA; +defparam \hdmi_ctrl_inst|encode_inst0|Add16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y22_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|cnt[4]~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout = \hdmi_ctrl_inst|encode_inst0|Add16~1_combout $ (\hdmi_ctrl_inst|encode_inst0|cnt[3]~14 $ (\hdmi_ctrl_inst|encode_inst0|Add16~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add16~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|Add16~2_combout ), + .cin(\hdmi_ctrl_inst|encode_inst0|cnt[3]~14 ), + .combout(\hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4]~15 .lut_mask = 16'hA55A; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X38_Y22_N15 +dffeas \hdmi_ctrl_inst|encode_inst0|cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|cnt[4]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_3~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_3~0_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2] & \hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]))) # +// (!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]) # ((!\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1] & \hdmi_ctrl_inst|encode_inst0|q_m_n0 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~0 .lut_mask = 16'h7150; +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y22_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|condition_3~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|condition_3~2_combout = (\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & (((\hdmi_ctrl_inst|encode_inst0|cnt [4])))) # (!\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst0|cnt [4] & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst0|cnt [4] & (\hdmi_ctrl_inst|encode_inst0|condition_3~1_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_n0 [3]), + .datac(\hdmi_ctrl_inst|encode_inst0|cnt [4]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_3~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~2 .lut_mask = 16'hF2C2; +defparam \hdmi_ctrl_inst|encode_inst0|condition_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~1_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [1] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_reg [1]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~1 .lut_mask = 16'h87D2; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~1_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N28 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~0_combout = (\vga_ctrl_inst|cnt_h [7]) # ((\vga_ctrl_inst|cnt_h [10]) # ((\vga_ctrl_inst|cnt_h [9]) # (\vga_ctrl_inst|cnt_h [11]))) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [10]), + .datac(\vga_ctrl_inst|cnt_h [9]), + .datad(\vga_ctrl_inst|cnt_h [11]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~0 .lut_mask = 16'hFFFE; +defparam \vga_ctrl_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N26 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~1_combout = (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|LessThan0~0_combout & ((!\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|cnt_h [6])))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|cnt_h [5]), + .datad(\vga_ctrl_inst|LessThan0~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~1 .lut_mask = 16'h0015; +defparam \vga_ctrl_inst|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y20_N27 +dffeas \hdmi_ctrl_inst|encode_inst2|c0_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|LessThan0~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c0_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg1 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X38_Y20_N25 +dffeas \hdmi_ctrl_inst|encode_inst2|c0_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y22_N9 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|q_m[7]~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout = \hdmi_ctrl_inst|encode_inst0|data_in_reg [4] $ (\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_in_reg [4]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m[7]~1 .lut_mask = 16'h33CC; +defparam \hdmi_ctrl_inst|encode_inst0|q_m[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y22_N25 +dffeas \hdmi_ctrl_inst|encode_inst0|q_m_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|q_m[7]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|q_m_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|q_m_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~4_combout = \hdmi_ctrl_inst|encode_inst0|q_m_reg [5] $ (((\hdmi_ctrl_inst|encode_inst0|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst0|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst0|q_m_reg [5]), + .datad(\hdmi_ctrl_inst|encode_inst0|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~4 .lut_mask = 16'hC35A; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout = \hdmi_ctrl_inst|encode_inst0|data_out~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst0|data_out~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N29 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y20_N14 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan1~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan1~0_combout = (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [3] & \vga_ctrl_inst|always1~1_combout ))) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|always1~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan1~0 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|LessThan1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y20_N15 +dffeas \hdmi_ctrl_inst|encode_inst2|c1_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|LessThan1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c1_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg1 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout = \hdmi_ctrl_inst|encode_inst2|c1_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|c1_reg1~q ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N5 +dffeas \hdmi_ctrl_inst|encode_inst2|c1_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2 .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|c1_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~7_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst2|c0_reg2~q $ +// (!\hdmi_ctrl_inst|encode_inst2|c1_reg2~q )))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~7 .lut_mask = 16'hACA3; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N5 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [9]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[9] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout = (\hdmi_ctrl_inst|encode_inst0|data_out [9] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [9]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4 .lut_mask = 16'hC0C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N1 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [3]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N7 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out [3]), + .datab(gnd), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1 .lut_mask = 16'hAFA0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [1])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [1]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y22_N25 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst0|data_out~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst0|data_out~3_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|data_out[0]~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst0|data_out~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out~3 .lut_mask = 16'hA3A3; +defparam \hdmi_ctrl_inst|encode_inst0|data_out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N17 +dffeas \hdmi_ctrl_inst|encode_inst0|data_out[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst0|data_out~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst0|data_out [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst0|data_out[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst0|data_out[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y22_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst0|data_out [2]))) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [2])) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [2]), + .datab(\hdmi_ctrl_inst|encode_inst0|data_out [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1 .lut_mask = 16'hCACA; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y22_N21 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y20_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst0|data_out [0])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|encode_inst0|data_out [0]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0 .lut_mask = 16'hF3C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y20_N9 +dffeas \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y22_N18 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N16 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~2 ( +// Equation(s): +// \vga_pic_inst|LessThan17~2_combout = (!\vga_ctrl_inst|Add2~12_combout & (!\vga_ctrl_inst|Add2~10_combout & \vga_ctrl_inst|pix_data_req~7_combout )) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~2 .lut_mask = 16'h1010; +defparam \vga_pic_inst|LessThan17~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data[9]~15 ( +// Equation(s): +// \vga_pic_inst|pix_data[9]~15_combout = (\vga_pic_inst|pix_data[9]~14_combout & (!\vga_ctrl_inst|Add2~18_combout & (!\vga_ctrl_inst|Add2~16_combout & \vga_pic_inst|LessThan17~2_combout ))) + + .dataa(\vga_pic_inst|pix_data[9]~14_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|LessThan17~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[9]~15_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9]~15 .lut_mask = 16'h0200; +defparam \vga_pic_inst|pix_data[9]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y20_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~35 ( +// Equation(s): +// \vga_pic_inst|pix_data~35_combout = (\vga_pic_inst|LessThan10~0_combout ) # ((\vga_ctrl_inst|Add2~18_combout ) # ((\vga_pic_inst|pix_data[13]~11_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ))) + + .dataa(\vga_pic_inst|LessThan10~0_combout ), + .datab(\vga_ctrl_inst|Add2~18_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[13]~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~35_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~35 .lut_mask = 16'hFFEF; +defparam \vga_pic_inst|pix_data~35 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~36 ( +// Equation(s): +// \vga_pic_inst|pix_data~36_combout = (\vga_pic_inst|always0~2_combout & (!\vga_ctrl_inst|Add2~20_combout & (\vga_ctrl_inst|pix_data_req~7_combout & !\vga_pic_inst|pix_data[9]~15_combout ))) + + .dataa(\vga_pic_inst|always0~2_combout ), + .datab(\vga_ctrl_inst|Add2~20_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_pic_inst|pix_data[9]~15_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~36_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~36 .lut_mask = 16'h0020; +defparam \vga_pic_inst|pix_data~36 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N6 +cycloneive_lcell_comb \vga_pic_inst|pix_data~21 ( +// Equation(s): +// \vga_pic_inst|pix_data~21_combout = (\vga_pic_inst|pix_data~12_combout & (!\vga_ctrl_inst|Add2~12_combout & ((\vga_pic_inst|LessThan14~0_combout ) # (\vga_pic_inst|always0~0_combout )))) + + .dataa(\vga_pic_inst|LessThan14~0_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_ctrl_inst|Add2~12_combout ), + .datad(\vga_pic_inst|always0~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~21_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~21 .lut_mask = 16'h0C08; +defparam \vga_pic_inst|pix_data~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N22 +cycloneive_lcell_comb \vga_pic_inst|pix_data~26 ( +// Equation(s): +// \vga_pic_inst|pix_data~26_combout = (\vga_pic_inst|pix_data~36_combout & ((\vga_pic_inst|pix_data~25_combout ) # ((\vga_pic_inst|pix_data~35_combout & \vga_pic_inst|pix_data~21_combout )))) + + .dataa(\vga_pic_inst|pix_data~25_combout ), + .datab(\vga_pic_inst|pix_data~35_combout ), + .datac(\vga_pic_inst|pix_data~36_combout ), + .datad(\vga_pic_inst|pix_data~21_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~26_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~26 .lut_mask = 16'hE0A0; +defparam \vga_pic_inst|pix_data~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|pix_x[11]~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_x[11]~0_combout = (\vga_ctrl_inst|Add2~20_combout ) # (!\vga_ctrl_inst|pix_data_req~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~20_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_x[11]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_x[11]~0 .lut_mask = 16'hFF0F; +defparam \vga_ctrl_inst|pix_x[11]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N8 +cycloneive_lcell_comb \vga_pic_inst|pix_data~27 ( +// Equation(s): +// \vga_pic_inst|pix_data~27_combout = (\vga_pic_inst|pix_data~26_combout ) # ((!\vga_pic_inst|always0~2_combout & (!\vga_pic_inst|pix_data[9]~15_combout & !\vga_ctrl_inst|pix_x[11]~0_combout ))) + + .dataa(\vga_pic_inst|always0~2_combout ), + .datab(\vga_pic_inst|pix_data[9]~15_combout ), + .datac(\vga_pic_inst|pix_data~26_combout ), + .datad(\vga_ctrl_inst|pix_x[11]~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~27_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~27 .lut_mask = 16'hF0F1; +defparam \vga_pic_inst|pix_data~27 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y21_N9 +dffeas \vga_pic_inst|pix_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[10] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N14 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[10]~2 ( +// Equation(s): +// \vga_ctrl_inst|rgb[10]~2_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_pic_inst|pix_data [10] & \vga_ctrl_inst|pix_data_req~1_combout ))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(\vga_pic_inst|pix_data [10]), + .datad(\vga_ctrl_inst|pix_data_req~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[10]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[10]~2 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[10]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N15 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[10]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[7] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~29 ( +// Equation(s): +// \vga_pic_inst|pix_data~29_combout = (\vga_ctrl_inst|pix_data_req~7_combout & ((\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~10_combout & !\vga_ctrl_inst|Add2~12_combout )) # (!\vga_ctrl_inst|Add2~14_combout & +// ((\vga_ctrl_inst|Add2~12_combout ))))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|pix_data_req~7_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~29_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~29 .lut_mask = 16'h5020; +defparam \vga_pic_inst|pix_data~29 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~30 ( +// Equation(s): +// \vga_pic_inst|pix_data~30_combout = (\vga_ctrl_inst|pix_data_req~7_combout & (!\vga_ctrl_inst|Add2~20_combout & (!\vga_ctrl_inst|Add2~16_combout & !\vga_ctrl_inst|Add2~18_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~7_combout ), + .datab(\vga_ctrl_inst|Add2~20_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~18_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~30_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~30 .lut_mask = 16'h0002; +defparam \vga_pic_inst|pix_data~30 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~31 ( +// Equation(s): +// \vga_pic_inst|pix_data~31_combout = (\vga_pic_inst|LessThan17~3_combout ) # ((\vga_pic_inst|pix_data~29_combout & \vga_pic_inst|pix_data~30_combout )) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data~29_combout ), + .datac(\vga_pic_inst|pix_data~30_combout ), + .datad(\vga_pic_inst|LessThan17~3_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~31_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~31 .lut_mask = 16'hFFC0; +defparam \vga_pic_inst|pix_data~31 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y21_N5 +dffeas \vga_pic_inst|pix_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[8] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N4 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[6]~4 ( +// Equation(s): +// \vga_ctrl_inst|rgb[6]~4_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~4_combout & \vga_pic_inst|pix_data [8]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[6]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[6]~4 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[6]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N5 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[6]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add5~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add5~0_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~1_combout & (\vga_pic_inst|pix_data [8] & ((\vga_pic_inst|pix_data [9]) # (\vga_pic_inst|pix_data [10])))) + + .dataa(\vga_pic_inst|pix_data [9]), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~1_combout ), + .datac(\vga_pic_inst|pix_data [10]), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add5~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add5~0 .lut_mask = 16'hC800; +defparam \hdmi_ctrl_inst|encode_inst1|Add5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N27 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add14~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add14~1_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])))) # +// (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] $ (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add14~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add14~1 .lut_mask = 16'h6006; +defparam \hdmi_ctrl_inst|encode_inst1|Add14~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N25 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n0[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add14~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y21_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~28 ( +// Equation(s): +// \vga_pic_inst|pix_data~28_combout = (\vga_pic_inst|pix_data~36_combout & ((\vga_pic_inst|pix_data~25_combout ) # ((\vga_pic_inst|pix_data~35_combout & \vga_pic_inst|pix_data~21_combout )))) + + .dataa(\vga_pic_inst|pix_data~25_combout ), + .datab(\vga_pic_inst|pix_data~35_combout ), + .datac(\vga_pic_inst|pix_data~36_combout ), + .datad(\vga_pic_inst|pix_data~21_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~28_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~28 .lut_mask = 16'hE0A0; +defparam \vga_pic_inst|pix_data~28 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X38_Y21_N3 +dffeas \vga_pic_inst|pix_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N8 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[7]~3 ( +// Equation(s): +// \vga_ctrl_inst|rgb[7]~3_combout = (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_ctrl_inst|pix_data_req~4_combout & \vga_pic_inst|pix_data [9]))) + + .dataa(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|pix_data [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[7]~3 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N9 +dffeas \hdmi_ctrl_inst|encode_inst1|data_in_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[7]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_in_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add13~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add13~0_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [4])) # (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & +// ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]))))) # (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]))) # (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & +// (\hdmi_ctrl_inst|encode_inst1|data_in_reg [4])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add13~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add13~0 .lut_mask = 16'hF690; +defparam \hdmi_ctrl_inst|encode_inst1|Add13~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N13 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n1[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add13~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add13~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add13~1_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & \hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])) # (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & +// ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]) # (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add13~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add13~1 .lut_mask = 16'hF330; +defparam \hdmi_ctrl_inst|encode_inst1|Add13~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N29 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add13~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_3~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_3~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & !\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~0 .lut_mask = 16'h08AE; +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_3~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_3~1_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]) # ((!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~1 .lut_mask = 16'h7510; +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add14~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add14~2_combout = (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [7] & !\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add14~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add14~2 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst1|Add14~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n0[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add14~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X33_Y21_N7 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n1[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~0_combout = (\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst1|cnt [0] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst1|Add15~1 = CARRY((\hdmi_ctrl_inst|encode_inst1|cnt [0] & \hdmi_ctrl_inst|encode_inst1|q_m_n1 [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add15~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add15~4_combout = ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] $ (\hdmi_ctrl_inst|encode_inst1|cnt [2] $ (!\hdmi_ctrl_inst|encode_inst1|Add15~3 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|Add15~5 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst1|cnt [2]) # (!\hdmi_ctrl_inst|encode_inst1|Add15~3 ))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|cnt +// [2] & !\hdmi_ctrl_inst|encode_inst1|Add15~3 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add15~3 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add15~4_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add15~5 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add15~4 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|Add15~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add14~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add14~0_combout = (\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & (((!\hdmi_ctrl_inst|encode_inst1|data_in_reg [4] & !\hdmi_ctrl_inst|encode_inst1|data_in_reg [7])) # (!\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst1|data_in_reg [2] & ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]) # ((\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]) # (\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_in_reg [4]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_in_reg [2]), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_reg [7]), + .datad(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add14~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add14~0 .lut_mask = 16'h37FE; +defparam \hdmi_ctrl_inst|encode_inst1|Add14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N17 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_n0[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|Add14~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_n0[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add23~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add23~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// (\hdmi_ctrl_inst|encode_inst1|Add23~1 & VCC)))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst1|Add23~1 ) # (GND))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst1|Add23~1 )))) +// \hdmi_ctrl_inst|encode_inst1|Add23~3 = CARRY((\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst1|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & +// ((\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst1|Add23~1 )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|Add23~1 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add23~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|Add23~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add23~2 .lut_mask = 16'h694D; +defparam \hdmi_ctrl_inst|encode_inst1|Add23~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~9_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add17~4_combout ) # (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (\hdmi_ctrl_inst|encode_inst1|Add23~2_combout & ((!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add23~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add17~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~9_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~9 .lut_mask = 16'hAAE4; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~10 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~10_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~9_combout & (((\hdmi_ctrl_inst|encode_inst1|Add15~4_combout ) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|Add16~9_combout & (\hdmi_ctrl_inst|encode_inst1|Add20~2_combout & ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add20~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add15~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~9_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~10_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~10 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout = !\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2] + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N23 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~15_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst1|Add17~0_combout )) # (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8] & +// ((\hdmi_ctrl_inst|encode_inst1|Add15~0_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add17~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add15~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~15 .lut_mask = 16'hA0C0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[0]~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & (\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & +// (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & +// ((\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|cnt[0]~8 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~16_combout & +// ((!\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ) # (!\hdmi_ctrl_inst|encode_inst1|Add16~15_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~16_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~15_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~7 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N11 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal1~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal1~0_combout = (!\hdmi_ctrl_inst|encode_inst1|cnt [1] & (!\hdmi_ctrl_inst|encode_inst1|cnt [0] & (!\hdmi_ctrl_inst|encode_inst1|cnt [2] & !\hdmi_ctrl_inst|encode_inst1|cnt [4]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [0]), + .datac(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~0 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal1~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal1~1_combout = (\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout & !\hdmi_ctrl_inst|encode_inst1|cnt [3]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~1 .lut_mask = 16'h00CC; +defparam \hdmi_ctrl_inst|encode_inst1|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[0]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout = CARRY((\hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ) # (\hdmi_ctrl_inst|encode_inst1|Equal1~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Equal2~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Equal1~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[0]~6_cout )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~6 .lut_mask = 16'h00EE; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[1]~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout = ((\hdmi_ctrl_inst|encode_inst1|Add16~14_combout $ (\hdmi_ctrl_inst|encode_inst1|Add16~12_combout $ (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|cnt[1]~10 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~14_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~12_combout ) # (!\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~14_combout & +// (\hdmi_ctrl_inst|encode_inst1|Add16~12_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~14_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~12_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[0]~8 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1]~9 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[2]~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & (\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 & VCC)) # (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & +// (!\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & (!\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & +// ((\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst1|cnt[2]~12 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst1|Add16~8_combout & +// ((!\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ) # (!\hdmi_ctrl_inst|encode_inst1|Add16~10_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~10_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[1]~10 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2]~11 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N15 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[2]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X32_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~3_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst1|Add20~4_combout )) # (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst1|Add23~4_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add20~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add23~4_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~3 .lut_mask = 16'hEE50; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~4_combout = (\hdmi_ctrl_inst|encode_inst1|Add16~3_combout & (((\hdmi_ctrl_inst|encode_inst1|Add15~6_combout ) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~3_combout +// & (\hdmi_ctrl_inst|encode_inst1|Add17~6_combout & ((\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add17~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add15~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|Add16~3_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~4 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[3]~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout = ((\hdmi_ctrl_inst|encode_inst1|Add16~6_combout $ (\hdmi_ctrl_inst|encode_inst1|Add16~4_combout $ (!\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst1|cnt[3]~14 = CARRY((\hdmi_ctrl_inst|encode_inst1|Add16~6_combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~4_combout ) # (!\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~6_combout & +// (\hdmi_ctrl_inst|encode_inst1|Add16~4_combout & !\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add16~4_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[2]~12 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout ), + .cout(\hdmi_ctrl_inst|encode_inst1|cnt[3]~14 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3]~13 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N17 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[3]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Equal2~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Equal2~0_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] $ (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) # +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1] $ (!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1])))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [2]), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~0 .lut_mask = 16'h8241; +defparam \hdmi_ctrl_inst|encode_inst1|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_2~combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (!\hdmi_ctrl_inst|encode_inst1|cnt [3] & ((\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & +// ((\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ) # ((!\hdmi_ctrl_inst|encode_inst1|cnt [3] & \hdmi_ctrl_inst|encode_inst1|Equal1~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|cnt [3]), + .datac(\hdmi_ctrl_inst|encode_inst1|Equal2~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|Equal1~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_2 .lut_mask = 16'h7350; +defparam \hdmi_ctrl_inst|encode_inst1|condition_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[0]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0]~0 .lut_mask = 16'h22EE; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~11_combout = (\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (((\hdmi_ctrl_inst|encode_inst1|Add19~0_combout ) # (\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) # +// (!\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst1|Add22~0_combout & ((!\hdmi_ctrl_inst|encode_inst1|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add22~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add19~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|data_out[0]~0_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~11_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~11 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~12 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~12_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst1|Add16~11_combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]))) # (!\hdmi_ctrl_inst|encode_inst1|Add16~11_combout & +// (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1])))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst1|Add16~11_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [1]), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst1|Add16~11_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~12_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~12 .lut_mask = 16'h5F22; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y21_N13 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[1]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add22~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add22~6_combout = \hdmi_ctrl_inst|encode_inst1|Add22~5 $ (!\hdmi_ctrl_inst|encode_inst1|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst1|Add22~5 ), + .combout(\hdmi_ctrl_inst|encode_inst1|Add22~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add22~6 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst1|Add22~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|Add16~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|Add16~2_combout = (\hdmi_ctrl_inst|encode_inst1|condition_2~combout ) # ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst1|Add19~6_combout )) # +// (!\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst1|Add22~6_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add19~6_combout ), + .datab(\hdmi_ctrl_inst|encode_inst1|Add22~6_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|Add16~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|Add16~2 .lut_mask = 16'hFFAC; +defparam \hdmi_ctrl_inst|encode_inst1|Add16~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|cnt[4]~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout = \hdmi_ctrl_inst|encode_inst1|Add16~1_combout $ (\hdmi_ctrl_inst|encode_inst1|cnt[3]~14 $ (\hdmi_ctrl_inst|encode_inst1|Add16~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst1|Add16~1_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|Add16~2_combout ), + .cin(\hdmi_ctrl_inst|encode_inst1|cnt[3]~14 ), + .combout(\hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4]~15 .lut_mask = 16'hA55A; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X36_Y21_N19 +dffeas \hdmi_ctrl_inst|encode_inst1|cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|cnt[4]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y21_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|condition_3~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|condition_3~2_combout = (\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & (((\hdmi_ctrl_inst|encode_inst1|cnt [4])))) # (!\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3] & ((\hdmi_ctrl_inst|encode_inst1|cnt [4] & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~0_combout )) # (!\hdmi_ctrl_inst|encode_inst1|cnt [4] & ((\hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~1_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|cnt [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~2 .lut_mask = 16'hEE50; +defparam \hdmi_ctrl_inst|encode_inst1|condition_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y21_N19 +dffeas \hdmi_ctrl_inst|encode_inst1|q_m_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst1|data_in_n1 [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|q_m_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|q_m_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~1_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [3] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|q_m_reg [3]), + .datad(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~1 .lut_mask = 16'hA53C; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out~1_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N1 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~3 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~3_combout = \hdmi_ctrl_inst|encode_inst1|q_m_reg [5] $ (((\hdmi_ctrl_inst|encode_inst1|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst1|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|q_m_reg [5]), + .datab(\hdmi_ctrl_inst|encode_inst1|condition_2~combout ), + .datac(\hdmi_ctrl_inst|encode_inst1|condition_3~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~3 .lut_mask = 16'h9A56; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout = \hdmi_ctrl_inst|encode_inst1|data_out~3_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst1|data_out~3_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N29 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst1|data_out [5]))) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [3])) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [3]), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2 .lut_mask = 16'hCACA; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N21 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [2]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [3]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [3]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst1|data_out~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst1|data_out~7_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & ((\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst1|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst1|data_out~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out~7 .lut_mask = 16'hAF05; +defparam \hdmi_ctrl_inst|encode_inst1|data_out~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N29 +dffeas \hdmi_ctrl_inst|encode_inst1|data_out[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst1|data_out~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst1|data_out [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst1|data_out[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst1|data_out[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout = (\hdmi_ctrl_inst|encode_inst1|data_out [8] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst1|data_out [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4 .lut_mask = 16'hCC00; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N27 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [2])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [4]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [2]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [4]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N23 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [4])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [3]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [4]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [3]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N19 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [2])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [2]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1 .lut_mask = 16'hBB88; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst1|data_out [0])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [1]))) + + .dataa(\hdmi_ctrl_inst|encode_inst1|data_out [0]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [1]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N3 +dffeas \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y23_N11 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~33 ( +// Equation(s): +// \vga_pic_inst|pix_data~33_combout = (\vga_pic_inst|pix_data~37_combout & ((\vga_pic_inst|pix_data[13]~10_combout ) # (\vga_pic_inst|pix_data~19_combout ))) + + .dataa(\vga_pic_inst|pix_data~37_combout ), + .datab(\vga_pic_inst|pix_data[13]~10_combout ), + .datac(gnd), + .datad(\vga_pic_inst|pix_data~19_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~33_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~33 .lut_mask = 16'hAA88; +defparam \vga_pic_inst|pix_data~33 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N15 +dffeas \vga_pic_inst|pix_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N22 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[13]~6 ( +// Equation(s): +// \vga_ctrl_inst|rgb[13]~6_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_pic_inst|pix_data [13] & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_pic_inst|pix_data [13]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[13]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[13]~6 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[13]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N23 +dffeas \hdmi_ctrl_inst|encode_inst2|data_in_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[13]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~32 ( +// Equation(s): +// \vga_pic_inst|pix_data~32_combout = (\vga_pic_inst|pix_data~37_combout & (!\vga_ctrl_inst|pix_x[11]~0_combout & ((\vga_pic_inst|pix_data[13]~9_combout ) # (!\vga_pic_inst|pix_data~13_combout )))) + + .dataa(\vga_pic_inst|pix_data~37_combout ), + .datab(\vga_pic_inst|pix_data~13_combout ), + .datac(\vga_pic_inst|pix_data[13]~9_combout ), + .datad(\vga_ctrl_inst|pix_x[11]~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~32_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~32 .lut_mask = 16'h00A2; +defparam \vga_pic_inst|pix_data~32 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N5 +dffeas \vga_pic_inst|pix_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~32_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[15] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add6~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add6~0_combout = (\vga_ctrl_inst|pix_data_req~3_combout & (\hdmi_ctrl_inst|encode_inst0|Add4~0_combout & (\vga_pic_inst|pix_data [13] & \vga_pic_inst|pix_data [15]))) + + .dataa(\vga_ctrl_inst|pix_data_req~3_combout ), + .datab(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .datac(\vga_pic_inst|pix_data [13]), + .datad(\vga_pic_inst|pix_data [15]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add6~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add6~0 .lut_mask = 16'h8000; +defparam \hdmi_ctrl_inst|encode_inst2|Add6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N27 +dffeas \hdmi_ctrl_inst|encode_inst2|data_in_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_in_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_in_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y21_N20 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[12]~5 ( +// Equation(s): +// \vga_ctrl_inst|rgb[12]~5_combout = (\vga_ctrl_inst|pix_data_req~4_combout & (\vga_ctrl_inst|pix_data_req~1_combout & (\vga_pic_inst|pix_data [15] & \hdmi_ctrl_inst|encode_inst0|Add4~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_ctrl_inst|pix_data_req~1_combout ), + .datac(\vga_pic_inst|pix_data [15]), + .datad(\hdmi_ctrl_inst|encode_inst0|Add4~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[12]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[12]~5 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|rgb[12]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y21_N21 +dffeas \hdmi_ctrl_inst|encode_inst2|data_in_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|rgb[12]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_in_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add12~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add12~0_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3] & (!\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2])) # (!\hdmi_ctrl_inst|encode_inst2|data_in_reg [3] & ((\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add12~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add12~0 .lut_mask = 16'h3F0C; +defparam \hdmi_ctrl_inst|encode_inst2|Add12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N5 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n1[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add12~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add14~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add14~0_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]) # ((\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]) # (\hdmi_ctrl_inst|encode_inst2|data_in_reg [4])) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_in_reg [3]), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add14~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add14~0 .lut_mask = 16'hFFFC; +defparam \hdmi_ctrl_inst|encode_inst2|Add14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N1 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n0[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add14~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add12~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add12~1_combout = (\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] & !\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add12~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add12~1 .lut_mask = 16'h00F0; +defparam \hdmi_ctrl_inst|encode_inst2|Add12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N23 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n1[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|Add12~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_3~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_3~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & !\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]))) # +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & !\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~0 .lut_mask = 16'h20F2; +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout = !\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N7 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal2~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal2~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] $ (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2])))) # +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1] & (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] $ (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~0 .lut_mask = 16'h9009; +defparam \hdmi_ctrl_inst|encode_inst2|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add19~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add19~0_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & (\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add19~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|cnt [1] & \hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add19~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add19~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add19~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst2|Add19~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~5 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~5_combout = (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & ((\hdmi_ctrl_inst|encode_inst2|Add19~4_combout ))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout & (\hdmi_ctrl_inst|encode_inst2|Add22~4_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add22~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add19~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~5_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~5 .lut_mask = 16'h0C0A; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~6_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~5_combout ) # ((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~5_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~6 .lut_mask = 16'hF7F0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal1~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal1~0_combout = (!\hdmi_ctrl_inst|encode_inst2|cnt [4] & (!\hdmi_ctrl_inst|encode_inst2|cnt [0] & (!\hdmi_ctrl_inst|encode_inst2|cnt [1] & !\hdmi_ctrl_inst|encode_inst2|cnt [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~0 .lut_mask = 16'h0001; +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Equal1~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Equal1~1_combout = (!\hdmi_ctrl_inst|encode_inst2|cnt [3] & \hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~1 .lut_mask = 16'h0F00; +defparam \hdmi_ctrl_inst|encode_inst2|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[0]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout = CARRY((\hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ) # (\hdmi_ctrl_inst|encode_inst2|Equal1~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Equal2~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Equal1~1_combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~6 .lut_mask = 16'h00EE; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[0]~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & (\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & +// (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & +// ((\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|cnt[0]~8 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~16_combout & +// ((!\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ) # (!\hdmi_ctrl_inst|encode_inst2|Add16~15_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~16_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~15_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[0]~6_cout ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~7 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0]~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y24_N3 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add15~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add15~0_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & (\hdmi_ctrl_inst|encode_inst2|cnt [0] $ (VCC))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & (\hdmi_ctrl_inst|encode_inst2|cnt [0] & VCC)) +// \hdmi_ctrl_inst|encode_inst2|Add15~1 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0] & \hdmi_ctrl_inst|encode_inst2|cnt [0])) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .datab(\hdmi_ctrl_inst|encode_inst2|cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add15~0_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add15~1 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add15~0 .lut_mask = 16'h6688; +defparam \hdmi_ctrl_inst|encode_inst2|Add15~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~15_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] & (\hdmi_ctrl_inst|encode_inst2|Add17~0_combout )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8] & +// ((\hdmi_ctrl_inst|encode_inst2|Add15~0_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add17~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add15~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~15 .lut_mask = 16'hAC00; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[1]~9 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout = ((\hdmi_ctrl_inst|encode_inst2|Add16~12_combout $ (\hdmi_ctrl_inst|encode_inst2|Add16~14_combout $ (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|cnt[1]~10 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~12_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~14_combout ) # (!\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~12_combout & +// (\hdmi_ctrl_inst|encode_inst2|Add16~14_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~12_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~14_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[0]~8 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1]~9 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1]~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[2]~11 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & (\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & +// (!\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & (!\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & +// ((\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ) # (GND))))) +// \hdmi_ctrl_inst|encode_inst2|cnt[2]~12 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 )) # (!\hdmi_ctrl_inst|encode_inst2|Add16~10_combout & +// ((!\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ) # (!\hdmi_ctrl_inst|encode_inst2|Add16~8_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~10_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~8_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[1]~10 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2]~11 .lut_mask = 16'h9617; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2]~11 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[3]~13 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout = ((\hdmi_ctrl_inst|encode_inst2|Add16~4_combout $ (\hdmi_ctrl_inst|encode_inst2|Add16~6_combout $ (!\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 )))) # (GND) +// \hdmi_ctrl_inst|encode_inst2|cnt[3]~14 = CARRY((\hdmi_ctrl_inst|encode_inst2|Add16~4_combout & ((\hdmi_ctrl_inst|encode_inst2|Add16~6_combout ) # (!\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~4_combout & +// (\hdmi_ctrl_inst|encode_inst2|Add16~6_combout & !\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~6_combout ), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[2]~12 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|cnt[3]~14 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3]~13 .lut_mask = 16'h698E; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3]~13 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y24_N9 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[3]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout = !\hdmi_ctrl_inst|encode_inst2|Add14~0_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|Add14~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0 .lut_mask = 16'h00FF; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N3 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n0[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n0[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_2~combout = (\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout & (((\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout & !\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])) # (!\hdmi_ctrl_inst|encode_inst2|cnt [3]))) # +// (!\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout & (\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Equal1~0_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Equal2~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [3]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_2 .lut_mask = 16'h0ACE; +defparam \hdmi_ctrl_inst|encode_inst2|condition_2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[0]~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0]~0 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~14 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~14_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~13_combout & (((!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1])) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~13_combout +// & (\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst2|Add19~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~13_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [1]), + .datad(\hdmi_ctrl_inst|encode_inst2|Add19~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~14_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~14 .lut_mask = 16'h6E2A; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N5 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[1]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst2|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// (\hdmi_ctrl_inst|encode_inst2|Add23~1 & VCC)))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & ((\hdmi_ctrl_inst|encode_inst2|Add23~1 ) # (GND))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst2|Add23~1 )))) +// \hdmi_ctrl_inst|encode_inst2|Add23~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst2|Add23~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & +// ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]) # (!\hdmi_ctrl_inst|encode_inst2|Add23~1 )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add23~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add23~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~2 .lut_mask = 16'h694D; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N22 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~2_combout = (\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (!\hdmi_ctrl_inst|encode_inst2|Add20~1 )) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// ((\hdmi_ctrl_inst|encode_inst2|Add20~1 ) # (GND))))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & (\hdmi_ctrl_inst|encode_inst2|Add20~1 & VCC)) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & +// (!\hdmi_ctrl_inst|encode_inst2|Add20~1 )))) +// \hdmi_ctrl_inst|encode_inst2|Add20~3 = CARRY((\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & ((!\hdmi_ctrl_inst|encode_inst2|Add20~1 ) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]))) # (!\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2] & +// (!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2] & !\hdmi_ctrl_inst|encode_inst2|Add20~1 ))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [2]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [2]), + .datac(gnd), + .datad(vcc), + .cin(\hdmi_ctrl_inst|encode_inst2|Add20~1 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~2_combout ), + .cout(\hdmi_ctrl_inst|encode_inst2|Add20~3 )); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~2 .lut_mask = 16'h692B; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~7_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & ((\hdmi_ctrl_inst|encode_inst2|Add20~2_combout ))) # (!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout & (\hdmi_ctrl_inst|encode_inst2|Add23~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add23~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add20~2_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~7 .lut_mask = 16'hFA44; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~8_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~7_combout & (((\hdmi_ctrl_inst|encode_inst2|Add15~4_combout ) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~7_combout +// & (\hdmi_ctrl_inst|encode_inst2|Add17~4_combout & ((\hdmi_ctrl_inst|encode_inst2|condition_2~combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add17~4_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add15~4_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add16~7_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~8 .lut_mask = 16'hCAF0; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N7 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[2]~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X39_Y24_N9 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_n1[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_n1 [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_n1[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add17~8 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add17~8_combout = \hdmi_ctrl_inst|encode_inst2|Add17~7 $ (!\hdmi_ctrl_inst|encode_inst2|cnt [4]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .cin(\hdmi_ctrl_inst|encode_inst2|Add17~7 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add17~8_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add17~8 .lut_mask = 16'hF00F; +defparam \hdmi_ctrl_inst|encode_inst2|Add17~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add23~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add23~6_combout = !\hdmi_ctrl_inst|encode_inst2|Add23~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst2|Add23~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add23~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add23~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|Add23~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~0 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~0_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((\hdmi_ctrl_inst|encode_inst2|Add17~8_combout ) # ((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # +// (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (((\hdmi_ctrl_inst|encode_inst2|Add23~6_combout & !\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add17~8_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add23~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~0 .lut_mask = 16'hAAD8; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add20~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add20~6_combout = !\hdmi_ctrl_inst|encode_inst2|Add20~5 + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\hdmi_ctrl_inst|encode_inst2|Add20~5 ), + .combout(\hdmi_ctrl_inst|encode_inst2|Add20~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add20~6 .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|Add20~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y24_N2 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|Add16~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|Add16~1_combout = (\hdmi_ctrl_inst|encode_inst2|Add16~0_combout & ((\hdmi_ctrl_inst|encode_inst2|Add15~8_combout ) # ((!\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|Add16~0_combout +// & (((\hdmi_ctrl_inst|encode_inst2|Add20~6_combout & \hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add15~8_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|Add16~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|Add20~6_combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|Add16~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|Add16~1 .lut_mask = 16'hB8CC; +defparam \hdmi_ctrl_inst|encode_inst2|Add16~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N10 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|cnt[4]~15 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout = \hdmi_ctrl_inst|encode_inst2|Add16~2_combout $ (\hdmi_ctrl_inst|encode_inst2|cnt[3]~14 $ (\hdmi_ctrl_inst|encode_inst2|Add16~1_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|Add16~2_combout ), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|Add16~1_combout ), + .cin(\hdmi_ctrl_inst|encode_inst2|cnt[3]~14 ), + .combout(\hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4]~15 .lut_mask = 16'hA55A; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X37_Y24_N11 +dffeas \hdmi_ctrl_inst|encode_inst2|cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|cnt[4]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N26 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|condition_3~2 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|condition_3~2_combout = (\hdmi_ctrl_inst|encode_inst2|cnt [4] & (((\hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ) # (\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) # (!\hdmi_ctrl_inst|encode_inst2|cnt [4] & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~1_combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3])))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~1_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|condition_3~0_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|cnt [4]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_n0 [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~2 .lut_mask = 16'hF0CA; +defparam \hdmi_ctrl_inst|encode_inst2|condition_3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N21 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~1_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [1] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datac(\hdmi_ctrl_inst|encode_inst2|q_m_reg [1]), + .datad(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~1 .lut_mask = 16'hB41E; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~1_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out~1_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N1 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N28 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|q_m[7]~1 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout = \hdmi_ctrl_inst|encode_inst2|data_in_n1 [2] $ (\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|data_in_n1 [2]), + .datad(\hdmi_ctrl_inst|encode_inst2|data_in_reg [4]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m[7]~1 .lut_mask = 16'h0FF0; +defparam \hdmi_ctrl_inst|encode_inst2|q_m[7]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X39_Y24_N29 +dffeas \hdmi_ctrl_inst|encode_inst2|q_m_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|q_m[7]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|q_m_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|q_m_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X39_Y24_N30 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~4 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~4_combout = \hdmi_ctrl_inst|encode_inst2|q_m_reg [5] $ (((\hdmi_ctrl_inst|encode_inst2|condition_2~combout & (!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8])) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// ((\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ))))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [5]), + .datac(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~4 .lut_mask = 16'h939C; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N16 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout = \hdmi_ctrl_inst|encode_inst2|data_out~4_combout + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out~4_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder .lut_mask = 16'hFF00; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N17 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [5]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N18 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out~7 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out~7_combout = (\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (((\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout )))) # (!\hdmi_ctrl_inst|encode_inst2|de_reg2~q & (\hdmi_ctrl_inst|encode_inst2|c1_reg2~q $ +// ((!\hdmi_ctrl_inst|encode_inst2|c0_reg2~q )))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .datab(\hdmi_ctrl_inst|encode_inst2|c1_reg2~q ), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out~7_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out~7 .lut_mask = 16'hEB41; +defparam \hdmi_ctrl_inst|encode_inst2|data_out~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N19 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [9]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[9] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y21_N12 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout = (\hdmi_ctrl_inst|encode_inst2|data_out [9] & \hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [9]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4 .lut_mask = 16'hC0C0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y21_N13 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [4]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[4] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N8 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [4]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [4]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3 .lut_mask = 16'hCCF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N9 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N4 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [5])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [3]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [5]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [3]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2 .lut_mask = 16'hCCF0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N5 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [3])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [3]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [2]), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1 .lut_mask = 16'hB8B8; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y23_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [1])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [1]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y23_N21 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X40_Y24_N17 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[0]~0_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N20 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|data_out[4]~6 ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout = (\hdmi_ctrl_inst|encode_inst2|condition_2~combout & ((!\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]))) # (!\hdmi_ctrl_inst|encode_inst2|condition_2~combout & +// (\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout )) + + .dataa(\hdmi_ctrl_inst|encode_inst2|condition_3~2_combout ), + .datab(\hdmi_ctrl_inst|encode_inst2|q_m_reg [8]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|encode_inst2|condition_2~combout ), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~6 .lut_mask = 16'h33AA; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[4]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X38_Y20_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell ( +// Equation(s): +// \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout = !\hdmi_ctrl_inst|encode_inst2|c0_reg2~q + + .dataa(gnd), + .datab(gnd), + .datac(\hdmi_ctrl_inst|encode_inst2|c0_reg2~q ), + .datad(gnd), + .cin(gnd), + .combout(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell .lut_mask = 16'h0F0F; +defparam \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N21 +dffeas \hdmi_ctrl_inst|encode_inst2|data_out[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|encode_inst2|data_out[4]~6_combout ), + .asdata(\hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell_combout ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(!\hdmi_ctrl_inst|encode_inst2|de_reg2~q ), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|encode_inst2|data_out [6]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|encode_inst2|data_out[6] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|encode_inst2|data_out[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N6 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|encode_inst2|data_out [6]))) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [4])) + + .dataa(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [4]), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [6]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3 .lut_mask = 16'hCCAA; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N7 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [3]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[3] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N24 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [4])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [3]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [4]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [3]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2 .lut_mask = 16'hBB88; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N25 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [2]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[2] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N0 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [2])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [2]))) + + .dataa(\hdmi_ctrl_inst|encode_inst2|data_out [2]), + .datab(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datac(gnd), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [2]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1 .lut_mask = 16'hBB88; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N1 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [1]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[1] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X40_Y24_N14 +cycloneive_lcell_comb \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0 ( +// Equation(s): +// \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout = (\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & (\hdmi_ctrl_inst|encode_inst2|data_out [0])) # (!\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2] & ((\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [1]))) + + .dataa(gnd), + .datab(\hdmi_ctrl_inst|encode_inst2|data_out [0]), + .datac(\hdmi_ctrl_inst|par_to_ser_inst0|cnt [2]), + .datad(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [1]), + .cin(gnd), + .combout(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout ), + .cout()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0 .lut_mask = 16'hCFC0; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X40_Y24_N15 +dffeas \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [0]), + .prn(vcc)); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[0] .is_wysiwyg = "true"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[0] .power_up = "low"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y24_N4 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [0]), + .datainhi(\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y22_N25 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y23_N18 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +// Location: DDIOOUTCELL_X41_Y24_N11 +cycloneive_ddio_out \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] ( + .datainlo(!\hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s [0]), + .datainhi(!\hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s [0]), + .clkhi(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clklo(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .muxsel(!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk(gnd), + .ena(vcc), + .areset(gnd), + .sreset(gnd), + .devclrn(devclrn), + .devpor(devpor), + .dataout(\hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|dataout [0]), + .dfflo(), + .dffhi()); +// synopsys translate_off +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .async_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .power_up = "low"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .sync_mode = "none"; +defparam \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] .use_new_clocking_model = "true"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_min_1200mv_0c_v_fast.sdo b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_min_1200mv_0c_v_fast.sdo new file mode 100644 index 0000000..e407381 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_min_1200mv_0c_v_fast.sdo @@ -0,0 +1,9062 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Fast Corner delays for the design using part EP4CE15F23C8, +// with speed grade M, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "hdmi_colorbar") + (DATE "06/02/2023 04:17:19") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (2024:2024:2024) (2024:2024:2024)) + (PORT inclk[0] (1104:1104:1104) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (667:667:667) (769:769:769)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sload (600:600:600) (548:548:548)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT sclr (598:598:598) (581:581:581)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT sclr (598:598:598) (581:581:581)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT sclr (598:598:598) (581:581:581)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (666:666:666) (767:767:767)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT sload (815:815:815) (744:744:744)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (633:633:633) (700:700:700)) + (PORT clrn (865:865:865) (868:868:868)) + (PORT sload (767:767:767) (696:696:696)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (748:748:748) (841:841:841)) + (PORT clrn (865:865:865) (868:868:868)) + (PORT sload (767:767:767) (696:696:696)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (503:503:503)) + (PORT datab (252:252:252) (312:312:312)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~2) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (298:298:298)) + (PORT datab (313:313:313) (383:383:383)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~4) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (280:280:280)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (285:285:285)) + (PORT datab (144:144:144) (194:194:194)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (398:398:398)) + (PORT datab (241:241:241) (302:302:302)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (403:403:403)) + (PORT datab (234:234:234) (293:293:293)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~6) + (DELAY + (ABSOLUTE + (PORT datab (256:256:256) (316:316:316)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~8) + (DELAY + (ABSOLUTE + (PORT datab (250:250:250) (308:308:308)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~0) + (DELAY + (ABSOLUTE + (PORT dataa (425:425:425) (503:503:503)) + (PORT datab (255:255:255) (315:315:315)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (296:296:296)) + (PORT datab (313:313:313) (383:383:383)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~4) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (278:278:278)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (288:288:288)) + (PORT datab (148:148:148) (199:199:199)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (406:406:406)) + (PORT datab (244:244:244) (305:305:305)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~4) + (DELAY + (ABSOLUTE + (PORT dataa (313:313:313) (380:380:380)) + (PORT datab (236:236:236) (295:295:295)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~6) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (416:416:416)) + (PORT datab (258:258:258) (318:318:318)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~8) + (DELAY + (ABSOLUTE + (PORT datab (252:252:252) (310:310:310)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (206:206:206)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~4) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (293:293:293)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (139:139:139)) + (PORT datab (105:105:105) (134:134:134)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (342:342:342)) + (PORT datab (102:102:102) (131:131:131)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (216:216:216)) + (PORT datab (103:103:103) (132:132:132)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (614:614:614) (671:671:671)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT sload (815:815:815) (744:744:744)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (451:451:451) (539:539:539)) + (PORT datab (437:437:437) (522:522:522)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~2) + (DELAY + (ABSOLUTE + (PORT dataa (427:427:427) (507:507:507)) + (PORT datab (729:729:729) (860:860:860)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~4) + (DELAY + (ABSOLUTE + (PORT datab (355:355:355) (437:437:437)) + (IOPATH datab combout (188:188:188) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (408:408:408)) + (PORT datab (209:209:209) (267:267:267)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (414:414:414)) + (PORT datab (430:430:430) (513:513:513)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (420:420:420)) + (PORT datab (424:424:424) (508:508:508)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~6) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (419:419:419)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~8) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (407:407:407)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~0) + (DELAY + (ABSOLUTE + (PORT dataa (449:449:449) (537:537:537)) + (PORT datab (439:439:439) (523:523:523)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~4) + (DELAY + (ABSOLUTE + (PORT datab (356:356:356) (438:438:438)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (703:703:703) (828:828:828)) + (PORT datab (346:346:346) (419:419:419)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~6) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (420:420:420)) + (PORT datab (338:338:338) (414:414:414)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~8) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (406:406:406)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (406:406:406)) + (PORT datab (238:238:238) (297:297:297)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~2) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (418:418:418)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (397:397:397)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~6) + (DELAY + (ABSOLUTE + (PORT datad (223:223:223) (278:278:278)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (407:407:407)) + (PORT datab (238:238:238) (297:297:297)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~2) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (417:417:417)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~4) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (396:396:396)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (633:633:633) (701:701:701)) + (PORT clrn (865:865:865) (868:868:868)) + (PORT sload (767:767:767) (696:696:696)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (429:429:429)) + (PORT datab (348:348:348) (419:419:419)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~4) + (DELAY + (ABSOLUTE + (PORT datab (312:312:312) (380:380:380)) + (IOPATH datab combout (188:188:188) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (377:377:377)) + (PORT datab (141:141:141) (188:188:188)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (273:273:273)) + (PORT datab (311:311:311) (371:371:371)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (PORT datab (308:308:308) (367:367:367)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~6) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (380:380:380)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (428:428:428)) + (PORT datab (344:344:344) (415:415:415)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~4) + (DELAY + (ABSOLUTE + (PORT datab (309:309:309) (377:377:377)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (311:311:311) (378:378:378)) + (PORT datab (148:148:148) (199:199:199)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~4) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (201:201:201)) + (PORT datab (321:321:321) (390:390:390)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~6) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (404:404:404)) + (PORT datab (143:143:143) (192:192:192)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~8) + (DELAY + (ABSOLUTE + (PORT datad (148:148:148) (187:187:187)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~2) + (DELAY + (ABSOLUTE + (PORT datab (217:217:217) (273:273:273)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (278:278:278)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~6) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (277:277:277)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (415:415:415)) + (PORT datab (327:327:327) (392:392:392)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~2) + (DELAY + (ABSOLUTE + (PORT datab (220:220:220) (276:276:276)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~4) + (DELAY + (ABSOLUTE + (PORT dataa (220:220:220) (281:281:281)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~6) + (DELAY + (ABSOLUTE + (PORT datad (229:229:229) (279:279:279)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (642:642:642) (715:715:715)) + (PORT clrn (868:868:868) (872:872:872)) + (PORT sload (781:781:781) (707:707:707)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (609:609:609) (668:668:668)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT sload (693:693:693) (641:641:641)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (666:666:666) (769:769:769)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sload (600:600:600) (548:548:548)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (200:200:200)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (458:458:458)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (227:227:227) (283:283:283)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (280:280:280)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (229:229:229) (285:285:285)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (144:144:144) (195:195:195)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (285:285:285)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (273:273:273)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (284:284:284)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datab (224:224:224) (280:280:280)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT datac (117:117:117) (157:157:157)) + (PORT datad (171:171:171) (227:227:227)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (299:299:299)) + (PORT datab (249:249:249) (308:308:308)) + (PORT datac (202:202:202) (255:255:255)) + (PORT datad (197:197:197) (247:247:247)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (396:396:396)) + (PORT datab (242:242:242) (303:303:303)) + (PORT datac (220:220:220) (273:273:273)) + (PORT datad (211:211:211) (261:261:261)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (429:429:429)) + (PORT datab (347:347:347) (419:419:419)) + (PORT datac (340:340:340) (418:418:418)) + (PORT datad (314:314:314) (370:370:370)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT datac (122:122:122) (166:166:166)) + (PORT datad (170:170:170) (226:226:226)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (308:308:308) (356:356:356)) + (PORT datab (332:332:332) (388:388:388)) + (PORT datac (274:274:274) (309:309:309)) + (PORT datad (103:103:103) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~1) + (DELAY + (ABSOLUTE + (PORT dataa (287:287:287) (336:336:336)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (267:267:267) (302:302:302)) + (PORT datad (288:288:288) (326:326:326)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (322:322:322) (375:375:375)) + (PORT datac (196:196:196) (236:236:236)) + (PORT datad (166:166:166) (196:196:196)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (219:219:219)) + (PORT datab (193:193:193) (232:232:232)) + (PORT datac (92:92:92) (113:113:113)) + (PORT datad (313:313:313) (355:355:355)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (387:387:387)) + (PORT datab (332:332:332) (388:388:388)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (167:167:167) (197:197:197)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (351:351:351)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (196:196:196) (235:235:235)) + (PORT datad (312:312:312) (353:353:353)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~8) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (322:322:322)) + (PORT datab (186:186:186) (223:223:223)) + (PORT datac (158:158:158) (187:187:187)) + (PORT datad (201:201:201) (231:231:231)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~11) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (219:219:219)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (196:196:196) (235:235:235)) + (PORT datad (311:311:311) (353:353:353)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~12) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (278:278:278) (327:327:327)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (308:308:308) (349:349:349)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~16) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (261:261:261)) + (PORT datac (316:316:316) (369:369:369)) + (PORT datad (132:132:132) (169:169:169)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datac (239:239:239) (298:298:298)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add12\~1) + (DELAY + (ABSOLUTE + (PORT datab (517:517:517) (623:623:623)) + (PORT datad (487:487:487) (585:585:585)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (371:371:371)) + (PORT datab (372:372:372) (449:449:449)) + (PORT datac (319:319:319) (365:365:365)) + (PORT datad (317:317:317) (363:363:363)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (132:132:132) (180:180:180)) + (PORT datac (436:436:436) (540:540:540)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (414:414:414)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (174:174:174) (209:209:209)) + (PORT datad (433:433:433) (497:497:497)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~1) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (316:316:316)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (432:432:432) (496:496:496)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (118:118:118) (150:150:150)) + (PORT datab (269:269:269) (316:316:316)) + (PORT datac (386:386:386) (437:437:437)) + (PORT datad (312:312:312) (381:381:381)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (400:400:400) (460:460:460)) + (PORT datab (172:172:172) (210:210:210)) + (PORT datac (89:89:89) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (411:411:411) (474:474:474)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (594:594:594) (693:693:693)) + (PORT datad (200:200:200) (235:235:235)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~8) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (321:321:321)) + (PORT datab (101:101:101) (130:130:130)) + (PORT datac (396:396:396) (450:450:450)) + (PORT datad (322:322:322) (387:387:387)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~13) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (191:191:191) (231:231:231)) + (PORT datac (329:329:329) (392:392:392)) + (PORT datad (433:433:433) (498:498:498)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~14) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (162:162:162) (194:194:194)) + (PORT datad (433:433:433) (498:498:498)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~16) + (DELAY + (ABSOLUTE + (PORT datab (333:333:333) (391:391:391)) + (PORT datac (199:199:199) (251:251:251)) + (PORT datad (316:316:316) (386:386:386)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (179:179:179) (217:217:217)) + (PORT datad (314:314:314) (383:383:383)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT asdata (321:321:321) (376:376:376)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (157:157:157) (213:213:213)) + (PORT datab (301:301:301) (350:350:350)) + (PORT datad (299:299:299) (339:339:339)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (312:312:312) (369:369:369)) + (PORT datad (287:287:287) (326:326:326)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (328:328:328)) + (PORT datab (321:321:321) (381:381:381)) + (PORT datac (306:306:306) (357:357:357)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (348:348:348)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (304:304:304) (358:358:358)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~9) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (393:393:393)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (289:289:289) (346:346:346)) + (PORT datad (295:295:295) (344:344:344)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~10) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (323:323:323) (392:392:392)) + (PORT datac (160:160:160) (186:186:186)) + (PORT datad (294:294:294) (344:344:344)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~11) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (273:273:273) (318:318:318)) + (PORT datac (311:311:311) (363:363:363)) + (PORT datad (305:305:305) (359:359:359)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~12) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (212:212:212)) + (PORT datab (190:190:190) (229:229:229)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (304:304:304) (359:359:359)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~13) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (395:395:395)) + (PORT datab (221:221:221) (281:281:281)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (296:296:296) (345:345:345)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~16) + (DELAY + (ABSOLUTE + (PORT datab (156:156:156) (210:210:210)) + (PORT datac (309:309:309) (364:364:364)) + (PORT datad (309:309:309) (359:359:359)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (308:308:308) (355:355:355)) + (PORT datad (205:205:205) (257:257:257)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add14\~1) + (DELAY + (ABSOLUTE + (PORT datab (391:391:391) (478:478:478)) + (PORT datac (412:412:412) (510:510:510)) + (PORT datad (386:386:386) (471:471:471)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (156:156:156) (212:212:212)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datac (288:288:288) (331:331:331)) + (PORT datad (300:300:300) (342:342:342)) + (IOPATH dataa combout (181:181:181) (184:184:184)) + (IOPATH datab combout (192:192:192) (188:188:188)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~3) + (DELAY + (ABSOLUTE + (PORT datab (493:493:493) (588:588:588)) + (PORT datac (381:381:381) (469:469:469)) + (PORT datad (272:272:272) (316:316:316)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (390:390:390)) + (PORT datab (146:146:146) (197:197:197)) + (PORT datac (133:133:133) (177:177:177)) + (PORT datad (133:133:133) (171:171:171)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (286:286:286) (339:339:339)) + (PORT datab (342:342:342) (412:412:412)) + (PORT datac (284:284:284) (321:321:321)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (460:460:460) (544:544:544)) + (PORT datad (485:485:485) (583:583:583)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~5) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (374:374:374)) + (PORT datab (372:372:372) (450:450:450)) + (PORT datac (319:319:319) (365:365:365)) + (PORT datad (317:317:317) (363:363:363)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (198:198:198) (254:254:254)) + (PORT datac (435:435:435) (540:540:540)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (186:186:186)) + (PORT datab (429:429:429) (528:528:528)) + (PORT datac (116:116:116) (157:157:157)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT asdata (316:316:316) (361:361:361)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~4) + (DELAY + (ABSOLUTE + (PORT dataa (153:153:153) (208:208:208)) + (PORT datab (306:306:306) (356:356:356)) + (PORT datad (293:293:293) (333:333:333)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (410:410:410) (507:507:507)) + (PORT datad (371:371:371) (451:451:451)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~5) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (163:163:163)) + (PORT datab (132:132:132) (180:180:180)) + (PORT datac (219:219:219) (273:273:273)) + (PORT datad (112:112:112) (133:133:133)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_x\[10\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (328:328:328) (387:387:387)) + (PORT datad (201:201:201) (234:234:234)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (429:429:429)) + (PORT datac (463:463:463) (536:536:536)) + (PORT datad (357:357:357) (421:421:421)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (363:363:363) (422:422:422)) + (PORT datac (595:595:595) (684:684:684)) + (PORT datad (106:106:106) (125:125:125)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[9\]\~14) + (DELAY + (ABSOLUTE + (PORT datac (463:463:463) (537:537:537)) + (PORT datad (347:347:347) (404:404:404)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~16) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (150:150:150)) + (PORT datab (112:112:112) (143:143:143)) + (PORT datac (333:333:333) (393:393:393)) + (PORT datad (328:328:328) (385:385:385)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~8) + (DELAY + (ABSOLUTE + (PORT datab (349:349:349) (416:416:416)) + (PORT datac (322:322:322) (380:380:380)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[10\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (556:556:556) (639:639:639)) + (PORT datad (213:213:213) (254:254:254)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (518:518:518) (623:623:623)) + (PORT datac (461:461:461) (545:545:545)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (389:389:389)) + (PORT datab (370:370:370) (448:448:448)) + (PORT datad (317:317:317) (363:363:363)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~4) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (182:182:182)) + (PORT datac (435:435:435) (540:540:540)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (415:415:415)) + (PORT datab (333:333:333) (385:385:385)) + (PORT datac (199:199:199) (244:244:244)) + (PORT datad (204:204:204) (238:238:238)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~22) + (DELAY + (ABSOLUTE + (PORT datac (328:328:328) (388:388:388)) + (PORT datad (178:178:178) (210:210:210)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~23) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (262:262:262)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (200:200:200) (246:246:246)) + (PORT datad (198:198:198) (233:233:233)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (264:264:264)) + (PORT datad (177:177:177) (210:210:210)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (412:412:412)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (198:198:198) (244:244:244)) + (PORT datad (205:205:205) (238:238:238)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~25) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (145:145:145)) + (PORT datab (290:290:290) (339:339:339)) + (PORT datac (91:91:91) (114:114:114)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (156:156:156) (209:209:209)) + (PORT datac (154:154:154) (212:212:212)) + (PORT datad (218:218:218) (268:268:268)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~5) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (396:396:396)) + (PORT datab (308:308:308) (357:357:357)) + (PORT datac (358:358:358) (402:402:402)) + (PORT datad (310:310:310) (370:370:370)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (181:181:181)) + (PORT datac (409:409:409) (507:507:507)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (375:375:375) (455:455:455)) + (PORT datad (366:366:366) (441:441:441)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~4) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (184:184:184)) + (PORT datab (417:417:417) (514:514:514)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~8) + (DELAY + (ABSOLUTE + (PORT dataa (433:433:433) (518:518:518)) + (PORT datab (335:335:335) (398:398:398)) + (PORT datac (492:492:492) (594:594:594)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (162:162:162) (218:218:218)) + (PORT datac (146:146:146) (203:203:203)) + (PORT datad (224:224:224) (274:274:274)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~6) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (304:304:304)) + (PORT datab (147:147:147) (198:198:198)) + (PORT datac (490:490:490) (594:594:594)) + (PORT datad (103:103:103) (119:119:119)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~8) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (490:490:490)) + (PORT datab (493:493:493) (589:589:589)) + (PORT datac (220:220:220) (274:274:274)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~37) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (399:399:399)) + (PORT datab (218:218:218) (261:261:261)) + (PORT datac (334:334:334) (394:394:394)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1120:1120:1120) (1119:1119:1119)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (161:161:161) (184:184:184)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT dataa (437:437:437) (501:501:501)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (388:388:388)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (169:169:169) (198:198:198)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datab (444:444:444) (508:508:508)) + (IOPATH datab combout (168:168:168) (167:167:167)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (91:91:91) (109:109:109)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_clk_p\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1555:1555:1555) (1528:1528:1528)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_clk_n\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1555:1555:1555) (1528:1528:1528)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_p\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1565:1565:1565) (1538:1538:1538)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_p\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1565:1565:1565) (1538:1538:1538)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_p\[2\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1565:1565:1565) (1538:1538:1538)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_n\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1555:1555:1555) (1528:1528:1528)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_n\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1575:1575:1575) (1548:1548:1548)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_n\[2\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (1565:1565:1565) (1538:1538:1538)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\~0) + (DELAY + (ABSOLUTE + (PORT datab (186:186:186) (250:250:250)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|Add0\~1) + (DELAY + (ABSOLUTE + (PORT datad (122:122:122) (160:160:160)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (396:396:396) (485:485:485)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (130:130:130) (179:179:179)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT sclr (396:396:396) (485:485:485)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datad (171:171:171) (226:226:226)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (172:172:172) (226:226:226)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (188:188:188) (254:254:254)) + (PORT datac (120:120:120) (162:162:162)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT datac (120:120:120) (163:163:163)) + (PORT datad (174:174:174) (228:228:228)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (183:183:183)) + (PORT datad (171:171:171) (226:226:226)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (131:131:131) (179:179:179)) + (PORT datad (171:171:171) (225:225:225)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (358:358:358) (738:738:738)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1120:1120:1120) (1119:1119:1119)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (839:839:839) (834:834:834)) + (PORT D (525:525:525) (592:592:592)) + (IOPATH (negedge ENA) Q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (231:231:231)) + (HOLD D (negedge ENA) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (839:839:839) (834:834:834)) + (PORT d (533:533:533) (579:579:579)) + (IOPATH (posedge clk) q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (918:918:918) (937:937:937)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (243:243:243) (236:236:236)) + ) + ) + (DELAY + (PATHPULSE datain dataout (236:236:236)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (842:842:842) (837:837:837)) + (PORT D (397:397:397) (362:362:362)) + (IOPATH (negedge ENA) Q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (231:231:231)) + (HOLD D (negedge ENA) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (842:842:842) (837:837:837)) + (PORT d (424:424:424) (379:379:379)) + (IOPATH (posedge clk) q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (921:921:921) (940:940:940)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (243:243:243) (236:236:236)) + ) + ) + (DELAY + (PATHPULSE datain dataout (236:236:236)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (147:147:147) (196:196:196)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (685:685:685) (607:607:607)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2590:2590:2590) (2333:2333:2333)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2038:2038:2038) (2292:2292:2292)) + (PORT datab (132:132:132) (180:180:180)) + (PORT datad (364:364:364) (297:297:297)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (771:771:771) (835:835:835)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (197:197:197)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (196:196:196)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (160:160:160) (211:211:211)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (200:200:200)) + (PORT datab (146:146:146) (196:196:196)) + (PORT datac (132:132:132) (175:175:175)) + (PORT datad (134:134:134) (172:172:172)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (157:157:157) (205:205:205)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datab (162:162:162) (212:212:212)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~20) + (DELAY + (ABSOLUTE + (PORT datab (157:157:157) (207:207:207)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~22) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (211:211:211)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (161:161:161) (214:214:214)) + (PORT datab (161:161:161) (211:211:211)) + (PORT datac (148:148:148) (191:191:191)) + (PORT datad (144:144:144) (183:183:183)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~0) + (DELAY + (ABSOLUTE + (PORT dataa (421:421:421) (485:485:485)) + (PORT datab (356:356:356) (424:424:424)) + (PORT datac (350:350:350) (413:413:413)) + (PORT datad (438:438:438) (504:504:504)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (871:871:871)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (311:311:311)) + (PORT datab (486:486:486) (577:577:577)) + (PORT datac (219:219:219) (275:275:275)) + (PORT datad (222:222:222) (273:273:273)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~2) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (156:156:156)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (107:107:107) (130:130:130)) + (PORT datad (280:280:280) (322:322:322)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~1) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (156:156:156)) + (PORT datab (121:121:121) (151:151:151)) + (PORT datac (93:93:93) (115:115:115)) + (PORT datad (280:280:280) (322:322:322)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT datab (484:484:484) (574:574:574)) + (PORT datac (218:218:218) (274:274:274)) + (PORT datad (222:222:222) (273:273:273)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (291:291:291)) + (PORT datab (254:254:254) (315:315:315)) + (PORT datac (236:236:236) (293:293:293)) + (PORT datad (277:277:277) (318:318:318)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (279:279:279)) + (PORT datab (326:326:326) (385:385:385)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (280:280:280)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (266:266:266)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~7) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (297:297:297)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~9) + (DELAY + (ABSOLUTE + (PORT datab (480:480:480) (570:570:570)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT datab (241:241:241) (297:297:297)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT datab (220:220:220) (273:273:273)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (305:305:305)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (297:297:297)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT datab (240:240:240) (292:292:292)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (426:426:426)) + (PORT datab (220:220:220) (264:264:264)) + (PORT datac (201:201:201) (246:246:246)) + (PORT datad (203:203:203) (236:236:236)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~5) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (293:293:293)) + (PORT datac (239:239:239) (296:296:296)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT datab (365:365:365) (429:429:429)) + (PORT datac (339:339:339) (399:399:399)) + (PORT datad (441:441:441) (507:507:507)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (213:213:213)) + (PORT datab (161:161:161) (201:201:201)) + (PORT datad (465:465:465) (539:539:539)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (137:137:137)) + (PORT datab (556:556:556) (640:640:640)) + (PORT datad (212:212:212) (253:253:253)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (321:321:321)) + (PORT datab (161:161:161) (201:201:201)) + (PORT datad (466:466:466) (540:540:540)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (198:198:198)) + (PORT datab (145:145:145) (195:195:195)) + (PORT datac (206:206:206) (255:255:255)) + (PORT datad (132:132:132) (171:171:171)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (330:330:330)) + (PORT datab (158:158:158) (197:197:197)) + (PORT datad (471:471:471) (546:546:546)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (226:226:226)) + (PORT datab (155:155:155) (195:195:195)) + (PORT datad (474:474:474) (549:549:549)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (358:358:358)) + (PORT datab (119:119:119) (150:150:150)) + (PORT datac (135:135:135) (179:179:179)) + (PORT datad (136:136:136) (175:175:175)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (188:188:188)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (273:273:273)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (548:548:548) (623:623:623)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (171:171:171) (210:210:210)) + (PORT datab (156:156:156) (195:195:195)) + (PORT datad (473:473:473) (548:548:548)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (210:210:210)) + (PORT datab (159:159:159) (209:209:209)) + (PORT datac (213:213:213) (269:269:269)) + (PORT datad (137:137:137) (178:178:178)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[11\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (110:110:110) (140:140:140)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (472:472:472) (547:547:547)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (343:343:343)) + (PORT datab (161:161:161) (201:201:201)) + (PORT datad (466:466:466) (541:541:541)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (175:175:175) (212:212:212)) + (PORT datab (162:162:162) (202:202:202)) + (PORT datad (464:464:464) (539:539:539)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (284:284:284)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (233:233:233)) + (PORT datab (173:173:173) (207:207:207)) + (PORT datad (469:469:469) (544:544:544)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~22) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (282:282:282)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datad (542:542:542) (616:616:616)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (405:405:405)) + (PORT datab (351:351:351) (418:418:418)) + (PORT datac (226:226:226) (278:278:278)) + (PORT datad (213:213:213) (258:258:258)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~4) + (DELAY + (ABSOLUTE + (PORT dataa (293:293:293) (339:339:339)) + (PORT datac (328:328:328) (384:384:384)) + (PORT datad (96:96:96) (115:115:115)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~6) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (251:251:251)) + (PORT datab (253:253:253) (313:313:313)) + (PORT datac (236:236:236) (293:293:293)) + (PORT datad (276:276:276) (317:317:317)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~7) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (342:342:342)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (100:100:100) (121:121:121)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (262:262:262)) + (PORT datab (291:291:291) (342:342:342)) + (PORT datac (200:200:200) (245:245:245)) + (PORT datad (199:199:199) (235:235:235)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (270:270:270)) + (PORT datab (219:219:219) (262:262:262)) + (PORT datac (337:337:337) (397:397:397)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~13) + (DELAY + (ABSOLUTE + (PORT dataa (184:184:184) (226:226:226)) + (PORT datab (186:186:186) (227:227:227)) + (PORT datac (603:603:603) (689:689:689)) + (PORT datad (339:339:339) (400:400:400)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~17) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (264:264:264)) + (PORT datac (199:199:199) (244:244:244)) + (PORT datad (200:200:200) (236:236:236)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~34) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (400:400:400)) + (PORT datab (218:218:218) (262:262:262)) + (PORT datac (335:335:335) (395:395:395)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (263:263:263)) + (PORT datad (199:199:199) (235:235:235)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (417:417:417)) + (PORT datab (216:216:216) (259:259:259)) + (PORT datac (199:199:199) (244:244:244)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (418:418:418)) + (PORT datac (522:522:522) (589:589:589)) + (PORT datad (324:324:324) (376:376:376)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~18) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (412:412:412)) + (PORT datab (108:108:108) (138:138:138)) + (PORT datac (320:320:320) (376:376:376)) + (PORT datad (101:101:101) (124:124:124)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~20) + (DELAY + (ABSOLUTE + (PORT datad (210:210:210) (252:252:252)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (432:432:432)) + (PORT datab (354:354:354) (417:417:417)) + (PORT datac (458:458:458) (532:532:532)) + (PORT datad (362:362:362) (427:427:427)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~3) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (411:411:411)) + (PORT datab (352:352:352) (418:418:418)) + (PORT datac (595:595:595) (684:684:684)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (430:430:430)) + (PORT datac (335:335:335) (397:397:397)) + (PORT datad (358:358:358) (423:423:423)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~19) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (412:412:412)) + (PORT datab (198:198:198) (234:234:234)) + (PORT datac (253:253:253) (286:286:286)) + (PORT datad (336:336:336) (397:397:397)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~20) + (DELAY + (ABSOLUTE + (PORT datab (112:112:112) (144:144:144)) + (PORT datac (321:321:321) (377:377:377)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (441:441:441) (506:506:506)) + (PORT datab (333:333:333) (391:391:391)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_in_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[8\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (490:490:490) (587:587:587)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (874:874:874)) + (PORT asdata (642:642:642) (727:727:727)) + (PORT clrn (862:862:862) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (235:235:235) (292:292:292)) + (PORT datab (149:149:149) (200:200:200)) + (PORT datac (135:135:135) (179:179:179)) + (PORT datad (141:141:141) (183:183:183)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (122:122:122) (153:153:153)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (131:131:131) (171:171:171)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (482:482:482) (567:567:567)) + (PORT datab (574:574:574) (661:661:661)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (311:311:311) (364:364:364)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_in_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (568:568:568)) + (PORT datab (331:331:331) (389:389:389)) + (PORT datac (558:558:558) (640:640:640)) + (PORT datad (122:122:122) (160:160:160)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_in_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add14\~0) + (DELAY + (ABSOLUTE + (PORT datab (517:517:517) (622:622:622)) + (PORT datac (462:462:462) (546:546:546)) + (PORT datad (489:489:489) (586:586:586)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (91:91:91) (109:109:109)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (276:276:276)) + (PORT datab (353:353:353) (420:420:420)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~2) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (205:205:205)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~6) + (DELAY + (ABSOLUTE + (PORT datab (155:155:155) (203:203:203)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (265:265:265)) + (PORT datab (373:373:373) (451:451:451)) + (IOPATH dataa combout (172:172:172) (165:165:165)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~2) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (290:290:290)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~6) + (DELAY + (ABSOLUTE + (PORT datad (216:216:216) (258:258:258)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (260:260:260)) + (PORT datab (184:184:184) (220:220:220)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (165:165:165) (195:195:195)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (387:387:387)) + (PORT datab (368:368:368) (445:445:445)) + (PORT datad (317:317:317) (362:362:362)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~9) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (244:244:244)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (314:314:314) (372:372:372)) + (PORT datad (317:317:317) (363:363:363)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~10) + (DELAY + (ABSOLUTE + (PORT dataa (310:310:310) (377:377:377)) + (PORT datab (176:176:176) (213:213:213)) + (PORT datac (304:304:304) (350:350:350)) + (PORT datad (176:176:176) (208:208:208)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add12\~0) + (DELAY + (ABSOLUTE + (PORT datab (515:515:515) (621:621:621)) + (PORT datac (463:463:463) (547:547:547)) + (PORT datad (491:491:491) (589:589:589)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add14\~1) + (DELAY + (ABSOLUTE + (PORT datab (517:517:517) (622:622:622)) + (PORT datac (462:462:462) (546:546:546)) + (PORT datad (489:489:489) (587:587:587)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~13) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (243:243:243)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (327:327:327) (397:397:397)) + (PORT datad (317:317:317) (363:363:363)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~14) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (373:373:373)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (302:302:302) (355:355:355)) + (PORT datad (167:167:167) (196:196:196)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT asdata (612:612:612) (691:691:691)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~15) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (261:261:261)) + (PORT datab (186:186:186) (223:223:223)) + (PORT datac (171:171:171) (204:204:204)) + (PORT datad (336:336:336) (396:396:396)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (299:299:299)) + (PORT datab (249:249:249) (308:308:308)) + (PORT datac (202:202:202) (255:255:255)) + (PORT datad (197:197:197) (247:247:247)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datac (327:327:327) (386:386:386)) + (PORT datad (170:170:170) (201:201:201)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (225:225:225)) + (PORT datab (172:172:172) (210:210:210)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (292:292:292) (338:338:338)) + (PORT datab (189:189:189) (228:228:228)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (561:561:561)) + (PORT datac (555:555:555) (637:637:637)) + (PORT datad (312:312:312) (364:364:364)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|de_reg1) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|de_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|de_reg2) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT sclr (598:598:598) (581:581:581)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_2) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (141:141:141)) + (PORT datab (338:338:338) (403:403:403)) + (PORT datac (239:239:239) (298:298:298)) + (PORT datad (173:173:173) (203:203:203)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (372:372:372) (450:450:450)) + (PORT datac (306:306:306) (364:364:364)) + (PORT datad (317:317:317) (363:363:363)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (212:212:212)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT sclr (598:598:598) (581:581:581)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (299:299:299)) + (PORT datab (250:250:250) (309:309:309)) + (PORT datac (202:202:202) (255:255:255)) + (PORT datad (197:197:197) (247:247:247)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (189:189:189) (226:226:226)) + (PORT datab (339:339:339) (405:405:405)) + (PORT datac (233:233:233) (289:289:289)) + (PORT datad (167:167:167) (197:197:197)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (350:350:350)) + (PORT datab (142:142:142) (190:190:190)) + (PORT datad (295:295:295) (335:335:335)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (273:273:273) (311:311:311)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (401:401:401)) + (PORT datab (240:240:240) (293:293:293)) + (PORT datac (225:225:225) (279:279:279)) + (PORT datad (209:209:209) (252:252:252)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (250:250:250) (312:312:312)) + (PORT datab (242:242:242) (299:299:299)) + (PORT datac (470:470:470) (556:556:556)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c0_reg1) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c0_reg2) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT asdata (294:294:294) (332:332:332)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (666:666:666) (766:766:766)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT sload (815:815:815) (744:744:744)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (516:516:516) (621:621:621)) + (PORT datad (490:490:490) (588:588:588)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (869:869:869) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~4) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (388:388:388)) + (PORT datab (370:370:370) (448:448:448)) + (PORT datac (302:302:302) (356:356:356)) + (PORT datad (317:317:317) (363:363:363)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (248:248:248) (279:279:279)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (670:670:670) (770:770:770)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT sload (815:815:815) (744:744:744)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (152:152:152) (208:208:208)) + (PORT datab (159:159:159) (209:209:209)) + (PORT datac (205:205:205) (253:253:253)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c1_reg1) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c1_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (539:539:539) (618:618:618)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c1_reg2) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~7) + (DELAY + (ABSOLUTE + (PORT dataa (303:303:303) (349:349:349)) + (PORT datab (507:507:507) (611:611:611)) + (PORT datac (416:416:416) (501:501:501)) + (PORT datad (349:349:349) (420:420:420)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (130:130:130) (178:178:178)) + (PORT datac (435:435:435) (539:539:539)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (137:137:137) (189:189:189)) + (PORT datac (435:435:435) (540:540:540)) + (PORT datad (118:118:118) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT datab (138:138:138) (190:190:190)) + (PORT datac (435:435:435) (539:539:539)) + (PORT datad (118:118:118) (154:154:154)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datac (435:435:435) (539:539:539)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (132:132:132) (181:181:181)) + (PORT datac (436:436:436) (540:540:540)) + (PORT datad (120:120:120) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (523:523:523) (596:596:596)) + (PORT clrn (863:863:863) (867:867:867)) + (PORT sload (693:693:693) (641:641:641)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~3) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (346:346:346)) + (PORT datab (510:510:510) (613:613:613)) + (PORT datac (412:412:412) (497:497:497)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (867:867:867)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (182:182:182)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datac (435:435:435) (540:540:540)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (187:187:187) (253:253:253)) + (PORT datac (356:356:356) (430:430:430)) + (PORT datad (347:347:347) (417:417:417)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (842:842:842) (837:837:837)) + (PORT D (514:514:514) (571:571:571)) + (IOPATH (negedge ENA) Q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (231:231:231)) + (HOLD D (negedge ENA) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (842:842:842) (837:837:837)) + (PORT d (380:380:380) (411:411:411)) + (IOPATH (posedge clk) q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (921:921:921) (940:940:940)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (243:243:243) (236:236:236)) + ) + ) + (DELAY + (PATHPULSE datain dataout (236:236:236)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (452:452:452)) + (PORT datab (353:353:353) (416:416:416)) + (PORT datac (461:461:461) (534:534:534)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[9\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (361:361:361) (419:419:419)) + (PORT datac (594:594:594) (683:683:683)) + (PORT datad (106:106:106) (125:125:125)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~35) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datab (219:219:219) (263:263:263)) + (PORT datac (338:338:338) (397:397:397)) + (PORT datad (95:95:95) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~36) + (DELAY + (ABSOLUTE + (PORT dataa (116:116:116) (152:152:152)) + (PORT datab (354:354:354) (420:420:420)) + (PORT datac (458:458:458) (532:532:532)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~21) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (226:226:226)) + (PORT datab (185:185:185) (226:226:226)) + (PORT datac (602:602:602) (688:688:688)) + (PORT datad (338:338:338) (399:399:399)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~26) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (407:407:407)) + (PORT datab (324:324:324) (384:384:384)) + (PORT datac (93:93:93) (117:117:117)) + (PORT datad (168:168:168) (198:198:198)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_x\[11\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (459:459:459) (524:524:524)) + (PORT datad (336:336:336) (393:393:393)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~27) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (148:148:148)) + (PORT datab (114:114:114) (146:146:146)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (329:329:329) (383:383:383)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[10\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (356:356:356)) + (PORT datab (551:551:551) (628:628:628)) + (PORT datac (206:206:206) (264:264:264)) + (PORT datad (629:629:629) (700:700:700)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~29) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (429:429:429)) + (PORT datab (353:353:353) (416:416:416)) + (PORT datac (465:465:465) (539:539:539)) + (PORT datad (355:355:355) (419:419:419)) + (IOPATH dataa combout (186:186:186) (179:179:179)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~30) + (DELAY + (ABSOLUTE + (PORT dataa (476:476:476) (556:556:556)) + (PORT datab (353:353:353) (420:420:420)) + (PORT datac (594:594:594) (683:683:683)) + (PORT datad (342:342:342) (395:395:395)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~31) + (DELAY + (ABSOLUTE + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (104:104:104) (122:122:122)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[6\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (306:306:306) (358:358:358)) + (PORT datab (540:540:540) (614:614:614)) + (PORT datac (534:534:534) (605:605:605)) + (PORT datad (202:202:202) (255:255:255)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (275:275:275)) + (PORT datab (276:276:276) (323:323:323)) + (PORT datac (208:208:208) (265:265:265)) + (PORT datad (206:206:206) (258:258:258)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (290:290:290)) + (PORT datab (164:164:164) (220:220:220)) + (PORT datac (152:152:152) (210:210:210)) + (PORT datad (220:220:220) (269:269:269)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n0\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~28) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (403:403:403)) + (PORT datab (323:323:323) (383:383:383)) + (PORT datac (97:97:97) (122:122:122)) + (PORT datad (165:165:165) (196:196:196)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (306:306:306) (358:358:358)) + (PORT datab (540:540:540) (614:614:614)) + (PORT datac (535:535:535) (605:605:605)) + (PORT datad (194:194:194) (244:244:244)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (211:211:211)) + (PORT datab (166:166:166) (228:228:228)) + (PORT datac (138:138:138) (183:183:183)) + (PORT datad (205:205:205) (249:249:249)) + (IOPATH dataa combout (181:181:181) (184:184:184)) + (IOPATH datab combout (182:182:182) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add13\~1) + (DELAY + (ABSOLUTE + (PORT datab (164:164:164) (221:221:221)) + (PORT datac (153:153:153) (211:211:211)) + (PORT datad (219:219:219) (268:268:268)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (741:741:741)) + (PORT datab (357:357:357) (432:432:432)) + (PORT datac (310:310:310) (374:374:374)) + (PORT datad (320:320:320) (384:384:384)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (743:743:743)) + (PORT datab (357:357:357) (432:432:432)) + (PORT datac (311:311:311) (376:376:376)) + (PORT datad (318:318:318) (382:382:382)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add14\~2) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (286:286:286)) + (PORT datab (165:165:165) (227:227:227)) + (PORT datac (146:146:146) (195:195:195)) + (PORT datad (223:223:223) (273:273:273)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n0\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (865:865:865) (870:870:870)) + (PORT asdata (815:815:815) (930:930:930)) + (PORT clrn (858:858:858) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (412:412:412)) + (PORT datab (212:212:212) (270:270:270)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~4) + (DELAY + (ABSOLUTE + (PORT dataa (613:613:613) (728:728:728)) + (PORT datab (345:345:345) (423:423:423)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (288:288:288)) + (PORT datab (168:168:168) (231:231:231)) + (PORT datac (146:146:146) (197:197:197)) + (PORT datad (221:221:221) (271:271:271)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n0\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (426:426:426) (506:506:506)) + (PORT datab (732:732:732) (863:863:863)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~9) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (408:408:408)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (163:163:163) (197:197:197)) + (PORT datad (431:431:431) (495:495:495)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~10) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (192:192:192) (231:231:231)) + (PORT datac (93:93:93) (115:115:115)) + (PORT datad (434:434:434) (498:498:498)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[8\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (138:138:138) (184:184:184)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~15) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (314:314:314) (365:365:365)) + (PORT datad (342:342:342) (411:411:411)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (303:303:303) (352:352:352)) + (PORT datab (603:603:603) (686:686:686)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (871:871:871)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (PORT sclr (591:591:591) (572:572:572)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (PORT datab (307:307:307) (372:372:372)) + (PORT datac (128:128:128) (169:169:169)) + (PORT datad (130:130:130) (167:167:167)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datab (112:112:112) (143:143:143)) + (PORT datad (135:135:135) (174:174:174)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (136:136:136)) + (PORT datab (105:105:105) (134:134:134)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (348:348:348)) + (PORT datab (170:170:170) (207:207:207)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (187:187:187) (223:223:223)) + (PORT datab (278:278:278) (320:320:320)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (871:871:871)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (PORT sclr (591:591:591) (572:572:572)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (410:410:410)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (431:431:431) (496:496:496)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (257:257:257) (290:290:290)) + (PORT datad (317:317:317) (368:368:368)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (294:294:294) (340:340:340)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (871:871:871)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (PORT sclr (591:591:591) (572:572:572)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (740:740:740)) + (PORT datab (357:357:357) (433:433:433)) + (PORT datac (309:309:309) (374:374:374)) + (PORT datad (320:320:320) (385:385:385)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_2) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (411:411:411)) + (PORT datab (146:146:146) (196:196:196)) + (PORT datac (283:283:283) (328:328:328)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (409:409:409)) + (PORT datab (311:311:311) (360:360:360)) + (PORT datad (312:312:312) (372:372:372)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~11) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (394:394:394) (447:447:447)) + (PORT datad (195:195:195) (229:229:229)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~12) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (370:370:370)) + (PORT datab (357:357:357) (433:433:433)) + (PORT datac (313:313:313) (378:378:378)) + (PORT datad (89:89:89) (106:106:106)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (871:871:871)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (PORT sclr (591:591:591) (572:572:572)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~6) + (DELAY + (ABSOLUTE + (PORT datad (224:224:224) (279:279:279)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (315:315:315)) + (PORT datab (288:288:288) (330:330:330)) + (PORT datac (284:284:284) (332:332:332)) + (PORT datad (299:299:299) (339:339:339)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (349:349:349)) + (PORT datad (164:164:164) (194:194:194)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (866:866:866) (871:871:871)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (PORT sclr (591:591:591) (572:572:572)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (415:415:415)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (224:224:224) (279:279:279)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT asdata (316:316:316) (360:360:360)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (209:209:209)) + (PORT datab (306:306:306) (355:355:355)) + (PORT datad (294:294:294) (333:333:333)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (285:285:285) (327:327:327)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (666:666:666) (768:768:768)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sload (600:600:600) (548:548:548)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~3) + (DELAY + (ABSOLUTE + (PORT dataa (297:297:297) (358:358:358)) + (PORT datab (309:309:309) (359:359:359)) + (PORT datac (357:357:357) (401:401:401)) + (PORT datad (312:312:312) (371:371:371)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (91:91:91) (108:108:108)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (669:669:669) (772:772:772)) + (PORT clrn (860:860:860) (864:864:864)) + (PORT sload (600:600:600) (548:548:548)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (183:183:183)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datac (409:409:409) (506:506:506)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (184:184:184)) + (PORT datac (406:406:406) (504:504:504)) + (PORT datad (119:119:119) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (138:138:138) (189:189:189)) + (PORT datac (409:409:409) (507:507:507)) + (PORT datad (120:120:120) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~7) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (473:473:473)) + (PORT datac (570:570:570) (665:665:665)) + (PORT datad (487:487:487) (574:574:574)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (865:865:865) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (130:130:130) (178:178:178)) + (PORT datad (420:420:420) (513:513:513)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~3) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (191:191:191)) + (PORT datab (436:436:436) (538:538:538)) + (PORT datac (117:117:117) (158:158:158)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (184:184:184)) + (PORT datab (436:436:436) (539:539:539)) + (PORT datac (117:117:117) (157:157:157)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (190:190:190)) + (PORT datab (436:436:436) (539:539:539)) + (PORT datad (118:118:118) (155:155:155)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (462:462:462)) + (PORT datab (437:437:437) (540:540:540)) + (PORT datac (117:117:117) (158:158:158)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (844:844:844) (840:840:840)) + (PORT D (352:352:352) (394:394:394)) + (IOPATH (negedge ENA) Q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (231:231:231)) + (HOLD D (negedge ENA) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (844:844:844) (840:840:840)) + (PORT d (528:528:528) (582:582:582)) + (IOPATH (posedge clk) q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (923:923:923) (943:943:943)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (243:243:243) (236:236:236)) + ) + ) + (DELAY + (PATHPULSE datain dataout (236:236:236)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~33) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (396:396:396)) + (PORT datab (113:113:113) (146:146:146)) + (PORT datad (94:94:94) (113:113:113)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[13\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (564:564:564)) + (PORT datab (573:573:573) (659:659:659)) + (PORT datac (122:122:122) (166:166:166)) + (PORT datad (312:312:312) (364:364:364)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_in_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~32) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (395:395:395)) + (PORT datab (107:107:107) (138:138:138)) + (PORT datac (329:329:329) (386:386:386)) + (PORT datad (334:334:334) (386:386:386)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (440:440:440) (506:506:506)) + (PORT datab (331:331:331) (389:389:389)) + (PORT datac (123:123:123) (166:166:166)) + (PORT datad (201:201:201) (247:247:247)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_in_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[12\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (564:564:564)) + (PORT datab (572:572:572) (659:659:659)) + (PORT datac (130:130:130) (172:172:172)) + (PORT datad (312:312:312) (364:364:364)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_in_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add12\~0) + (DELAY + (ABSOLUTE + (PORT datab (395:395:395) (482:482:482)) + (PORT datac (418:418:418) (517:517:517)) + (PORT datad (388:388:388) (474:474:474)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add14\~0) + (DELAY + (ABSOLUTE + (PORT datab (396:396:396) (483:483:483)) + (PORT datac (420:420:420) (519:519:519)) + (PORT datad (389:389:389) (475:475:475)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add12\~1) + (DELAY + (ABSOLUTE + (PORT datac (410:410:410) (508:508:508)) + (PORT datad (385:385:385) (470:470:470)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (428:428:428)) + (PORT datab (343:343:343) (414:414:414)) + (PORT datac (334:334:334) (411:411:411)) + (PORT datad (316:316:316) (373:373:373)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[8\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (418:418:418) (516:516:516)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (429:429:429)) + (PORT datab (349:349:349) (421:421:421)) + (PORT datac (343:343:343) (421:421:421)) + (PORT datad (313:313:313) (369:369:369)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (411:411:411)) + (PORT datab (326:326:326) (391:391:391)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (310:310:310) (367:367:367)) + (PORT datad (286:286:286) (325:325:325)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (403:403:403)) + (PORT datab (331:331:331) (397:397:397)) + (PORT datac (175:175:175) (211:211:211)) + (PORT datad (313:313:313) (362:362:362)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (209:209:209)) + (PORT datab (151:151:151) (204:204:204)) + (PORT datac (132:132:132) (176:176:176)) + (PORT datad (134:134:134) (173:173:173)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datac (322:322:322) (381:381:381)) + (PORT datad (268:268:268) (304:304:304)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (454:454:454)) + (PORT datab (377:377:377) (429:429:429)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (104:104:104) (133:133:133)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (871:871:871)) + (PORT sclr (774:774:774) (735:735:735)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (387:387:387)) + (PORT datab (154:154:154) (207:207:207)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~15) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (353:353:353)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (317:317:317) (376:376:376)) + (PORT datad (311:311:311) (361:361:361)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (174:174:174) (213:213:213)) + (PORT datab (189:189:189) (228:228:228)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (321:321:321)) + (PORT datab (103:103:103) (132:132:132)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (214:214:214)) + (PORT datab (102:102:102) (130:130:130)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (191:191:191) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (871:871:871)) + (PORT sclr (774:774:774) (735:735:735)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_2) + (DELAY + (ABSOLUTE + (PORT dataa (293:293:293) (335:335:335)) + (PORT datab (303:303:303) (350:350:350)) + (PORT datac (320:320:320) (378:378:378)) + (PORT datad (210:210:210) (264:264:264)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (128:128:128) (163:163:163)) + (PORT datab (233:233:233) (293:293:293)) + (PORT datad (112:112:112) (133:133:133)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~14) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (310:310:310) (368:368:368)) + (PORT datac (304:304:304) (363:363:363)) + (PORT datad (160:160:160) (187:187:187)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (871:871:871)) + (PORT sclr (774:774:774) (735:735:735)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (394:394:394)) + (PORT datab (355:355:355) (434:434:434)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~2) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (392:392:392)) + (PORT datab (360:360:360) (440:440:440)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (387:387:387)) + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (305:305:305) (360:360:360)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~8) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (352:352:352)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (257:257:257) (293:293:293)) + (PORT datad (312:312:312) (361:361:361)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (871:871:871)) + (PORT sclr (774:774:774) (735:735:735)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT asdata (643:643:643) (728:728:728)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~8) + (DELAY + (ABSOLUTE + (PORT datad (324:324:324) (378:378:378)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (398:398:398)) + (PORT datab (175:175:175) (215:215:215)) + (PORT datac (270:270:270) (312:312:312)) + (PORT datad (297:297:297) (347:347:347)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~1) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (340:340:340)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (264:264:264) (299:299:299)) + (PORT datad (297:297:297) (347:347:347)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (218:218:218)) + (PORT datad (162:162:162) (192:192:192)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (871:871:871)) + (PORT sclr (774:774:774) (735:735:735)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (335:335:335)) + (PORT datab (287:287:287) (336:336:336)) + (PORT datac (323:323:323) (374:374:374)) + (PORT datad (210:210:210) (263:263:263)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT asdata (588:588:588) (684:684:684)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (356:356:356)) + (PORT datab (319:319:319) (367:367:367)) + (PORT datad (141:141:141) (185:185:185)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (320:320:320) (374:374:374)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (749:749:749) (842:842:842)) + (PORT clrn (865:865:865) (868:868:868)) + (PORT sload (767:767:767) (696:696:696)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (408:408:408) (506:506:506)) + (PORT datad (384:384:384) (469:469:469)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~4) + (DELAY + (ABSOLUTE + (PORT dataa (157:157:157) (214:214:214)) + (PORT datab (129:129:129) (178:178:178)) + (PORT datac (288:288:288) (330:330:330)) + (PORT datad (300:300:300) (342:342:342)) + (IOPATH dataa combout (181:181:181) (184:184:184)) + (IOPATH datab combout (192:192:192) (188:188:188)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (272:272:272) (310:310:310)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (748:748:748) (841:841:841)) + (PORT clrn (865:865:865) (868:868:868)) + (PORT sload (767:767:767) (696:696:696)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~7) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (307:307:307)) + (PORT datab (149:149:149) (200:200:200)) + (PORT datac (491:491:491) (596:596:596)) + (PORT datad (338:338:338) (394:394:394)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (860:860:860) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (131:131:131) (179:179:179)) + (PORT datac (408:408:408) (505:505:505)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (187:187:187)) + (PORT datac (359:359:359) (438:438:438)) + (PORT datad (421:421:421) (515:515:515)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT datab (137:137:137) (187:187:187)) + (PORT datac (117:117:117) (157:157:157)) + (PORT datad (422:422:422) (515:515:515)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (184:184:184)) + (PORT datab (436:436:436) (538:538:538)) + (PORT datac (119:119:119) (160:160:160)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (182:182:182)) + (PORT datac (379:379:379) (458:458:458)) + (PORT datad (118:118:118) (154:154:154)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (776:776:776) (875:875:875)) + (PORT clrn (868:868:868) (872:872:872)) + (PORT sload (781:781:781) (707:707:707)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[4\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (127:127:127) (163:163:163)) + (PORT datab (235:235:235) (296:296:296)) + (PORT datad (111:111:111) (132:132:132)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c0_reg2\~_wirecell) + (DELAY + (ABSOLUTE + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT asdata (640:640:640) (713:713:713)) + (PORT clrn (868:868:868) (872:872:872)) + (PORT sload (781:781:781) (707:707:707)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sload (posedge clk) (84:84:84)) + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~3) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (182:182:182)) + (PORT datab (132:132:132) (181:181:181)) + (PORT datad (403:403:403) (491:491:491)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (133:133:133) (184:184:184)) + (PORT datab (415:415:415) (513:513:513)) + (PORT datad (119:119:119) (157:157:157)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (PORT datab (418:418:418) (515:515:515)) + (PORT datad (120:120:120) (158:158:158)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (169:169:169) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (130:130:130) (179:179:179)) + (PORT datac (392:392:392) (478:478:478)) + (PORT datad (119:119:119) (156:156:156)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (847:847:847) (842:842:842)) + (PORT D (353:353:353) (396:396:396)) + (IOPATH (negedge ENA) Q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (231:231:231)) + (HOLD D (negedge ENA) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (847:847:847) (842:842:842)) + (PORT d (538:538:538) (592:592:592)) + (IOPATH (posedge clk) q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (926:926:926) (945:945:945)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (243:243:243) (236:236:236)) + ) + ) + (DELAY + (PATHPULSE datain dataout (236:236:236)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (842:842:842) (837:837:837)) + (PORT D (566:566:566) (519:519:519)) + (IOPATH (negedge ENA) Q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (231:231:231)) + (HOLD D (negedge ENA) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (842:842:842) (837:837:837)) + (PORT d (416:416:416) (375:375:375)) + (IOPATH (posedge clk) q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (921:921:921) (940:940:940)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (243:243:243) (236:236:236)) + ) + ) + (DELAY + (PATHPULSE datain dataout (236:236:236)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (844:844:844) (840:840:840)) + (PORT D (389:389:389) (357:357:357)) + (IOPATH (negedge ENA) Q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (231:231:231)) + (HOLD D (negedge ENA) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (844:844:844) (840:840:840)) + (PORT d (587:587:587) (523:523:523)) + (IOPATH (posedge clk) q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (923:923:923) (943:943:943)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (243:243:243) (236:236:236)) + ) + ) + (DELAY + (PATHPULSE datain dataout (236:236:236)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (847:847:847) (842:842:842)) + (PORT D (391:391:391) (358:358:358)) + (IOPATH (negedge ENA) Q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (231:231:231)) + (HOLD D (negedge ENA) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (847:847:847) (842:842:842)) + (PORT d (597:597:597) (533:533:533)) + (IOPATH (posedge clk) q (103:103:103) (103:103:103)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (40:40:40)) + (HOLD d (posedge clk) (58:58:58)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (926:926:926) (945:945:945)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (243:243:243) (236:236:236)) + ) + ) + (DELAY + (PATHPULSE datain dataout (236:236:236)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_modelsim.xrf b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_modelsim.xrf new file mode 100644 index 0000000..becb4c6 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_modelsim.xrf @@ -0,0 +1,623 @@ +vendor_name = ModelSim +source_file = 1, E:/simiao/lc/A415/07_hdmi/hdmi/sim/tb_hdmi_colorbar.v +source_file = 1, E:/simiao/lc/A415/07_hdmi/hdmi/rtl/hdmi/encode.v +source_file = 1, E:/simiao/lc/A415/07_hdmi/hdmi/rtl/hdmi/par_to_ser.v +source_file = 1, E:/simiao/lc/A415/07_hdmi/hdmi/rtl/hdmi/hdmi_ctrl.v +source_file = 1, E:/simiao/lc/A415/07_hdmi/hdmi/rtl/vga_pic.v +source_file = 1, E:/simiao/lc/A415/07_hdmi/hdmi/rtl/vga_ctrl.v +source_file = 1, E:/simiao/lc/A415/07_hdmi/hdmi/rtl/hdmi_colorbar.v +source_file = 1, E:/simiao/lc/A415/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.qip +source_file = 1, E:/simiao/lc/A415/07_hdmi/hdmi/quartus_prj/ip_core/ddio_out/ddio_out.v +source_file = 1, E:/simiao/lc/A415/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen.qip +source_file = 1, E:/simiao/lc/A415/07_hdmi/hdmi/quartus_prj/ip_core/clk_gen/clk_gen.v +source_file = 1, output_files/Chain1.cdf +source_file = 1, E:/simiao/lc/A415/07_hdmi/hdmi/quartus_prj/db/hdmi_colorbar.cbx.xml +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_pll.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/stratixii_pll.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/cycloneii_pll.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/cbx.lst +source_file = 1, E:/simiao/lc/A415/07_hdmi/hdmi/quartus_prj/db/clk_gen_altpll.v +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/altddio_out.tdf +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_ddio.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/cyclone_ddio.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_lcell.inc +source_file = 1, E:/simiao/lc/A415/07_hdmi/hdmi/quartus_prj/db/ddio_out_p9j.tdf +design_name = hdmi_colorbar +instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll1 , clk_gen_inst|altpll_component|auto_generated|pll1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out[0] , hdmi_ctrl_inst|encode_inst1|data_out[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|cnt[0] , hdmi_ctrl_inst|encode_inst0|cnt[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|cnt[1] , hdmi_ctrl_inst|encode_inst0|cnt[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|cnt[2] , hdmi_ctrl_inst|encode_inst0|cnt[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out[3] , hdmi_ctrl_inst|encode_inst0|data_out[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out[2] , hdmi_ctrl_inst|encode_inst1|data_out[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out[3] , hdmi_ctrl_inst|encode_inst2|data_out[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add20~0 , hdmi_ctrl_inst|encode_inst0|Add20~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add20~2 , hdmi_ctrl_inst|encode_inst0|Add20~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add20~4 , hdmi_ctrl_inst|encode_inst0|Add20~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add20~6 , hdmi_ctrl_inst|encode_inst0|Add20~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add17~0 , hdmi_ctrl_inst|encode_inst0|Add17~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add17~2 , hdmi_ctrl_inst|encode_inst0|Add17~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add17~4 , hdmi_ctrl_inst|encode_inst0|Add17~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add17~6 , hdmi_ctrl_inst|encode_inst0|Add17~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add17~8 , hdmi_ctrl_inst|encode_inst0|Add17~8, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add23~0 , hdmi_ctrl_inst|encode_inst0|Add23~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add23~2 , hdmi_ctrl_inst|encode_inst0|Add23~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add23~4 , hdmi_ctrl_inst|encode_inst0|Add23~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add23~6 , hdmi_ctrl_inst|encode_inst0|Add23~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add15~0 , hdmi_ctrl_inst|encode_inst0|Add15~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add15~2 , hdmi_ctrl_inst|encode_inst0|Add15~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add15~4 , hdmi_ctrl_inst|encode_inst0|Add15~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add15~6 , hdmi_ctrl_inst|encode_inst0|Add15~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add15~8 , hdmi_ctrl_inst|encode_inst0|Add15~8, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add19~4 , hdmi_ctrl_inst|encode_inst0|Add19~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add22~4 , hdmi_ctrl_inst|encode_inst0|Add22~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|cnt[0]~7 , hdmi_ctrl_inst|encode_inst0|cnt[0]~7, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|cnt[1]~9 , hdmi_ctrl_inst|encode_inst0|cnt[1]~9, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|cnt[2]~11 , hdmi_ctrl_inst|encode_inst0|cnt[2]~11, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out[4] , hdmi_ctrl_inst|encode_inst0|data_out[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add20~0 , hdmi_ctrl_inst|encode_inst1|Add20~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add20~2 , hdmi_ctrl_inst|encode_inst1|Add20~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add20~4 , hdmi_ctrl_inst|encode_inst1|Add20~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add20~6 , hdmi_ctrl_inst|encode_inst1|Add20~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add17~0 , hdmi_ctrl_inst|encode_inst1|Add17~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add17~2 , hdmi_ctrl_inst|encode_inst1|Add17~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add17~4 , hdmi_ctrl_inst|encode_inst1|Add17~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add17~6 , hdmi_ctrl_inst|encode_inst1|Add17~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add17~8 , hdmi_ctrl_inst|encode_inst1|Add17~8, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add23~0 , hdmi_ctrl_inst|encode_inst1|Add23~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add23~4 , hdmi_ctrl_inst|encode_inst1|Add23~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add23~6 , hdmi_ctrl_inst|encode_inst1|Add23~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add15~2 , hdmi_ctrl_inst|encode_inst1|Add15~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add15~6 , hdmi_ctrl_inst|encode_inst1|Add15~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add15~8 , hdmi_ctrl_inst|encode_inst1|Add15~8, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add19~0 , hdmi_ctrl_inst|encode_inst1|Add19~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add19~2 , hdmi_ctrl_inst|encode_inst1|Add19~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add19~4 , hdmi_ctrl_inst|encode_inst1|Add19~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add19~6 , hdmi_ctrl_inst|encode_inst1|Add19~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add22~0 , hdmi_ctrl_inst|encode_inst1|Add22~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add22~2 , hdmi_ctrl_inst|encode_inst1|Add22~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add22~4 , hdmi_ctrl_inst|encode_inst1|Add22~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out[4] , hdmi_ctrl_inst|encode_inst1|data_out[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add20~0 , hdmi_ctrl_inst|encode_inst2|Add20~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add20~4 , hdmi_ctrl_inst|encode_inst2|Add20~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add17~0 , hdmi_ctrl_inst|encode_inst2|Add17~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add17~2 , hdmi_ctrl_inst|encode_inst2|Add17~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add17~4 , hdmi_ctrl_inst|encode_inst2|Add17~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add17~6 , hdmi_ctrl_inst|encode_inst2|Add17~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add23~0 , hdmi_ctrl_inst|encode_inst2|Add23~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add23~4 , hdmi_ctrl_inst|encode_inst2|Add23~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add15~2 , hdmi_ctrl_inst|encode_inst2|Add15~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add15~4 , hdmi_ctrl_inst|encode_inst2|Add15~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add15~6 , hdmi_ctrl_inst|encode_inst2|Add15~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add15~8 , hdmi_ctrl_inst|encode_inst2|Add15~8, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add19~2 , hdmi_ctrl_inst|encode_inst2|Add19~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add19~4 , hdmi_ctrl_inst|encode_inst2|Add19~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add19~6 , hdmi_ctrl_inst|encode_inst2|Add19~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add22~0 , hdmi_ctrl_inst|encode_inst2|Add22~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add22~2 , hdmi_ctrl_inst|encode_inst2|Add22~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add22~4 , hdmi_ctrl_inst|encode_inst2|Add22~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add22~6 , hdmi_ctrl_inst|encode_inst2|Add22~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out[4] , hdmi_ctrl_inst|encode_inst2|data_out[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out[6] , hdmi_ctrl_inst|encode_inst0|data_out[6], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out[7] , hdmi_ctrl_inst|encode_inst1|data_out[7], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~2 , vga_ctrl_inst|Add0~2, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~10 , vga_ctrl_inst|Add0~10, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~2 , vga_ctrl_inst|Add1~2, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~6 , vga_ctrl_inst|Add1~6, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~8 , vga_ctrl_inst|Add1~8, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~10 , vga_ctrl_inst|Add1~10, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~12 , vga_ctrl_inst|Add1~12, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~14 , vga_ctrl_inst|Add1~14, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~16 , vga_ctrl_inst|Add1~16, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~18 , vga_ctrl_inst|Add1~18, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~20 , vga_ctrl_inst|Add1~20, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[1] , hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[2] , hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1 , hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m_n1[2] , hdmi_ctrl_inst|encode_inst0|q_m_n1[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|condition_3~1 , hdmi_ctrl_inst|encode_inst0|condition_3~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Equal1~0 , hdmi_ctrl_inst|encode_inst0|Equal1~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[2] , hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m_n0[1] , hdmi_ctrl_inst|encode_inst2|q_m_n0[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|condition_3~1 , hdmi_ctrl_inst|encode_inst2|condition_3~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out[2] , hdmi_ctrl_inst|encode_inst2|data_out[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2 , hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~0 , hdmi_ctrl_inst|encode_inst0|Add16~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~1 , hdmi_ctrl_inst|encode_inst0|Add16~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~3 , hdmi_ctrl_inst|encode_inst0|Add16~3, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~4 , hdmi_ctrl_inst|encode_inst0|Add16~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~5 , hdmi_ctrl_inst|encode_inst0|Add16~5, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~7 , hdmi_ctrl_inst|encode_inst0|Add16~7, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~8 , hdmi_ctrl_inst|encode_inst0|Add16~8, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~11 , hdmi_ctrl_inst|encode_inst0|Add16~11, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~12 , hdmi_ctrl_inst|encode_inst0|Add16~12, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~16 , hdmi_ctrl_inst|encode_inst0|Add16~16, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Equal1~1 , hdmi_ctrl_inst|encode_inst0|Equal1~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add12~1 , hdmi_ctrl_inst|encode_inst0|Add12~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m_reg[3] , hdmi_ctrl_inst|encode_inst0|q_m_reg[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out~2 , hdmi_ctrl_inst|encode_inst0|data_out~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[3] , hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2 , hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~0 , hdmi_ctrl_inst|encode_inst1|Add16~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~1 , hdmi_ctrl_inst|encode_inst1|Add16~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~5 , hdmi_ctrl_inst|encode_inst1|Add16~5, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~6 , hdmi_ctrl_inst|encode_inst1|Add16~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~7 , hdmi_ctrl_inst|encode_inst1|Add16~7, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~8 , hdmi_ctrl_inst|encode_inst1|Add16~8, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~13 , hdmi_ctrl_inst|encode_inst1|Add16~13, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~14 , hdmi_ctrl_inst|encode_inst1|Add16~14, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~16 , hdmi_ctrl_inst|encode_inst1|Add16~16, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Equal2~1 , hdmi_ctrl_inst|encode_inst1|Equal2~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[3] , hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|q_m_reg[2] , hdmi_ctrl_inst|encode_inst1|q_m_reg[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out~2 , hdmi_ctrl_inst|encode_inst1|data_out~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~2 , hdmi_ctrl_inst|encode_inst2|Add16~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~3 , hdmi_ctrl_inst|encode_inst2|Add16~3, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~4 , hdmi_ctrl_inst|encode_inst2|Add16~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~9 , hdmi_ctrl_inst|encode_inst2|Add16~9, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~10 , hdmi_ctrl_inst|encode_inst2|Add16~10, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~11 , hdmi_ctrl_inst|encode_inst2|Add16~11, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~12 , hdmi_ctrl_inst|encode_inst2|Add16~12, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~13 , hdmi_ctrl_inst|encode_inst2|Add16~13, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~16 , hdmi_ctrl_inst|encode_inst2|Add16~16, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Equal2~1 , hdmi_ctrl_inst|encode_inst2|Equal2~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add14~1 , hdmi_ctrl_inst|encode_inst2|Add14~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m_reg[3] , hdmi_ctrl_inst|encode_inst2|q_m_reg[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out~2 , hdmi_ctrl_inst|encode_inst2|data_out~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out~3 , hdmi_ctrl_inst|encode_inst2|data_out~3, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~0 , vga_ctrl_inst|pix_data_req~0, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[10] , vga_ctrl_inst|cnt_v[10], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~3 , vga_ctrl_inst|pix_data_req~3, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m[3]~0 , hdmi_ctrl_inst|encode_inst0|q_m[3]~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m_reg[4] , hdmi_ctrl_inst|encode_inst0|q_m_reg[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out~5 , hdmi_ctrl_inst|encode_inst0|data_out~5, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[4] , hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3 , hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~3, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|q_m_reg[5] , hdmi_ctrl_inst|encode_inst1|q_m_reg[5], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[4] , hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3 , hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~3, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|q_m_reg[4] , hdmi_ctrl_inst|encode_inst1|q_m_reg[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out~4 , hdmi_ctrl_inst|encode_inst1|data_out~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m[3]~0 , hdmi_ctrl_inst|encode_inst2|q_m[3]~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m_reg[4] , hdmi_ctrl_inst|encode_inst2|q_m_reg[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out~5 , hdmi_ctrl_inst|encode_inst2|data_out~5, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[4] , hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[4], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[1] , vga_ctrl_inst|cnt_h[1], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_x[10]~1 , vga_ctrl_inst|pix_x[10]~1, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|always0~1 , vga_pic_inst|always0~1, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|always0~2 , vga_pic_inst|always0~2, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[9]~14 , vga_pic_inst|pix_data[9]~14, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~16 , vga_pic_inst|pix_data~16, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~8 , vga_ctrl_inst|pix_data_req~8, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[10]~12 , vga_ctrl_inst|cnt_v[10]~12, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m[4]~2 , hdmi_ctrl_inst|encode_inst0|q_m[4]~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out[6]~6 , hdmi_ctrl_inst|encode_inst0|data_out[6]~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out[8] , hdmi_ctrl_inst|encode_inst0|data_out[8], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4 , hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~4, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|LessThan10~0 , vga_pic_inst|LessThan10~0, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~22 , vga_pic_inst|pix_data~22, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~23 , vga_pic_inst|pix_data~23, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|LessThan14~1 , vga_pic_inst|LessThan14~1, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[13]~24 , vga_pic_inst|pix_data[13]~24, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~25 , vga_pic_inst|pix_data~25, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|q_m[5]~0 , hdmi_ctrl_inst|encode_inst1|q_m[5]~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|q_m_reg[7] , hdmi_ctrl_inst|encode_inst1|q_m_reg[7], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out~5 , hdmi_ctrl_inst|encode_inst1|data_out~5, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out[9] , hdmi_ctrl_inst|encode_inst1|data_out[9], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4 , hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m[4]~2 , hdmi_ctrl_inst|encode_inst2|q_m[4]~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out[8] , hdmi_ctrl_inst|encode_inst2|data_out[8], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4 , hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out~8 , hdmi_ctrl_inst|encode_inst0|data_out~8, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|q_m[7]~1 , hdmi_ctrl_inst|encode_inst1|q_m[7]~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out~6 , hdmi_ctrl_inst|encode_inst1|data_out~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out~8 , hdmi_ctrl_inst|encode_inst2|data_out~8, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~37 , vga_pic_inst|pix_data~37, hdmi_colorbar, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl , clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder , hdmi_ctrl_inst|encode_inst0|data_out[3]~feeder, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder , hdmi_ctrl_inst|encode_inst1|data_out[2]~feeder, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder , hdmi_ctrl_inst|encode_inst2|data_out[3]~feeder, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder , hdmi_ctrl_inst|encode_inst0|data_out[4]~feeder, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder , hdmi_ctrl_inst|encode_inst1|data_out[4]~feeder, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder , hdmi_ctrl_inst|encode_inst2|data_out[4]~feeder, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder , hdmi_ctrl_inst|encode_inst1|data_out[7]~feeder, hdmi_colorbar, 1 +instance = comp, \ddc_scl~output , ddc_scl~output, hdmi_colorbar, 1 +instance = comp, \ddc_sda~output , ddc_sda~output, hdmi_colorbar, 1 +instance = comp, \tmds_clk_p~output , tmds_clk_p~output, hdmi_colorbar, 1 +instance = comp, \tmds_clk_n~output , tmds_clk_n~output, hdmi_colorbar, 1 +instance = comp, \tmds_data_p[0]~output , tmds_data_p[0]~output, hdmi_colorbar, 1 +instance = comp, \tmds_data_p[1]~output , tmds_data_p[1]~output, hdmi_colorbar, 1 +instance = comp, \tmds_data_p[2]~output , tmds_data_p[2]~output, hdmi_colorbar, 1 +instance = comp, \tmds_data_n[0]~output , tmds_data_n[0]~output, hdmi_colorbar, 1 +instance = comp, \tmds_data_n[1]~output , tmds_data_n[1]~output, hdmi_colorbar, 1 +instance = comp, \tmds_data_n[2]~output , tmds_data_n[2]~output, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|cnt~0 , hdmi_ctrl_inst|par_to_ser_inst0|cnt~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|cnt[0] , hdmi_ctrl_inst|par_to_ser_inst0|cnt[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|Add0~1 , hdmi_ctrl_inst|par_to_ser_inst0|Add0~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|cnt[1] , hdmi_ctrl_inst|par_to_ser_inst0|cnt[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|Add0~0 , hdmi_ctrl_inst|par_to_ser_inst0|Add0~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|cnt[2] , hdmi_ctrl_inst|par_to_ser_inst0|cnt[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0 , hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[0] , hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder , hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4]~feeder, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4] , hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3 , hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s~3, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[3] , hdmi_ctrl_inst|par_to_ser_inst3|data_fall_s[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2 , hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[2] , hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1 , hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[1] , hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0 , hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[0] , hdmi_ctrl_inst|par_to_ser_inst3|data_rise_s[0], hdmi_colorbar, 1 +instance = comp, \sys_clk~input , sys_clk~input, hdmi_colorbar, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl , clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] , hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] , hdmi_ctrl_inst|par_to_ser_inst3|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~0 , vga_ctrl_inst|Add0~0, hdmi_colorbar, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder , clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder, hdmi_colorbar, 1 +instance = comp, \sys_rst_n~input , sys_rst_n~input, hdmi_colorbar, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync , clk_gen_inst|altpll_component|auto_generated|pll_lock_sync, hdmi_colorbar, 1 +instance = comp, \rst_n~0 , rst_n~0, hdmi_colorbar, 1 +instance = comp, \rst_n~0clkctrl , rst_n~0clkctrl, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[0] , vga_ctrl_inst|cnt_h[0], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~4 , vga_ctrl_inst|Add0~4, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~6 , vga_ctrl_inst|Add0~6, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[3] , vga_ctrl_inst|cnt_h[3], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~8 , vga_ctrl_inst|Add0~8, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[4] , vga_ctrl_inst|cnt_h[4], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~12 , vga_ctrl_inst|Add0~12, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[6] , vga_ctrl_inst|cnt_h[6], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~14 , vga_ctrl_inst|Add0~14, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[7] , vga_ctrl_inst|cnt_h[7], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[2] , vga_ctrl_inst|cnt_h[2], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Equal0~0 , vga_ctrl_inst|Equal0~0, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~16 , vga_ctrl_inst|Add0~16, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~18 , vga_ctrl_inst|Add0~18, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~20 , vga_ctrl_inst|Add0~20, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[10] , vga_ctrl_inst|cnt_h[10], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~22 , vga_ctrl_inst|Add0~22, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[11] , vga_ctrl_inst|cnt_h[11], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Equal0~1 , vga_ctrl_inst|Equal0~1, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h~0 , vga_ctrl_inst|cnt_h~0, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[5] , vga_ctrl_inst|cnt_h[5], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Equal0~2 , vga_ctrl_inst|Equal0~2, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h~2 , vga_ctrl_inst|cnt_h~2, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[8] , vga_ctrl_inst|cnt_h[8], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h~1 , vga_ctrl_inst|cnt_h~1, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[9] , vga_ctrl_inst|cnt_h[9], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan4~0 , vga_ctrl_inst|LessThan4~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add4~0 , hdmi_ctrl_inst|encode_inst0|Add4~0, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~1 , vga_ctrl_inst|Add2~1, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~3 , vga_ctrl_inst|Add2~3, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~5 , vga_ctrl_inst|Add2~5, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~7 , vga_ctrl_inst|Add2~7, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~9 , vga_ctrl_inst|Add2~9, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~10 , vga_ctrl_inst|Add2~10, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~12 , vga_ctrl_inst|Add2~12, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~14 , vga_ctrl_inst|Add2~14, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~16 , vga_ctrl_inst|Add2~16, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~18 , vga_ctrl_inst|Add2~18, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~12 , vga_pic_inst|pix_data~12, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~5 , vga_ctrl_inst|pix_data_req~5, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Equal0~3 , vga_ctrl_inst|Equal0~3, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[7]~7 , vga_ctrl_inst|cnt_v[7]~7, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[7] , vga_ctrl_inst|cnt_v[7], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[5]~10 , vga_ctrl_inst|cnt_v[5]~10, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[5] , vga_ctrl_inst|cnt_v[5], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[8]~6 , vga_ctrl_inst|cnt_v[8]~6, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[8] , vga_ctrl_inst|cnt_v[8], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|always1~0 , vga_ctrl_inst|always1~0, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[1]~1 , vga_ctrl_inst|cnt_v[1]~1, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[1] , vga_ctrl_inst|cnt_v[1], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[4]~5 , vga_ctrl_inst|cnt_v[4]~5, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[4] , vga_ctrl_inst|cnt_v[4], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|always1~1 , vga_ctrl_inst|always1~1, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~0 , vga_ctrl_inst|Add1~0, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[0]~2 , vga_ctrl_inst|cnt_v[0]~2, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[0] , vga_ctrl_inst|cnt_v[0], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[3]~3 , vga_ctrl_inst|cnt_v[3]~3, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[3] , vga_ctrl_inst|cnt_v[3], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|always1~2 , vga_ctrl_inst|always1~2, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[11]~0 , vga_ctrl_inst|cnt_v[11]~0, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[9]~9 , vga_ctrl_inst|cnt_v[9]~9, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[9] , vga_ctrl_inst|cnt_v[9], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[6]~8 , vga_ctrl_inst|cnt_v[6]~8, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[6] , vga_ctrl_inst|cnt_v[6], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~4 , vga_ctrl_inst|Add1~4, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[2]~4 , vga_ctrl_inst|cnt_v[2]~4, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[2] , vga_ctrl_inst|cnt_v[2], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~22 , vga_ctrl_inst|Add1~22, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[11]~11 , vga_ctrl_inst|cnt_v[11]~11, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[11] , vga_ctrl_inst|cnt_v[11], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~2 , vga_ctrl_inst|pix_data_req~2, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~4 , vga_ctrl_inst|pix_data_req~4, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~6 , vga_ctrl_inst|pix_data_req~6, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~7 , vga_ctrl_inst|pix_data_req~7, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[13]~11 , vga_pic_inst|pix_data[13]~11, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|always0~0 , vga_pic_inst|always0~0, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~13 , vga_pic_inst|pix_data~13, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~17 , vga_pic_inst|pix_data~17, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~34 , vga_pic_inst|pix_data~34, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[13]~8 , vga_pic_inst|pix_data[13]~8, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[13]~9 , vga_pic_inst|pix_data[13]~9, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[13]~10 , vga_pic_inst|pix_data[13]~10, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~18 , vga_pic_inst|pix_data~18, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[4] , vga_pic_inst|pix_data[4], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~20 , vga_ctrl_inst|Add2~20, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|LessThan17~4 , vga_pic_inst|LessThan17~4, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|LessThan17~3 , vga_pic_inst|LessThan17~3, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|LessThan14~0 , vga_pic_inst|LessThan14~0, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~19 , vga_pic_inst|pix_data~19, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~20 , vga_pic_inst|pix_data~20, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[0] , vga_pic_inst|pix_data[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add6~0 , hdmi_ctrl_inst|encode_inst0|Add6~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_in_n1[2] , hdmi_ctrl_inst|encode_inst0|data_in_n1[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0 , hdmi_ctrl_inst|encode_inst0|q_m_reg[8]~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m_reg[8] , hdmi_ctrl_inst|encode_inst0|q_m_reg[8], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m_reg[1] , hdmi_ctrl_inst|encode_inst0|q_m_reg[1], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan6~0 , vga_ctrl_inst|LessThan6~0, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~1 , vga_ctrl_inst|pix_data_req~1, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[1]~0 , vga_ctrl_inst|rgb[1]~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_in_reg[4] , hdmi_ctrl_inst|encode_inst0|data_in_reg[4], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[2]~1 , vga_ctrl_inst|rgb[2]~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_in_reg[3] , hdmi_ctrl_inst|encode_inst0|data_in_reg[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add14~0 , hdmi_ctrl_inst|encode_inst0|Add14~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0 , hdmi_ctrl_inst|encode_inst0|q_m_n0[3]~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m_n0[3] , hdmi_ctrl_inst|encode_inst0|q_m_n0[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add19~0 , hdmi_ctrl_inst|encode_inst0|Add19~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add19~2 , hdmi_ctrl_inst|encode_inst0|Add19~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add19~6 , hdmi_ctrl_inst|encode_inst0|Add19~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add22~0 , hdmi_ctrl_inst|encode_inst0|Add22~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add22~2 , hdmi_ctrl_inst|encode_inst0|Add22~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add22~6 , hdmi_ctrl_inst|encode_inst0|Add22~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~2 , hdmi_ctrl_inst|encode_inst0|Add16~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out[0]~0 , hdmi_ctrl_inst|encode_inst0|data_out[0]~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m_n0[2] , hdmi_ctrl_inst|encode_inst0|q_m_n0[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~9 , hdmi_ctrl_inst|encode_inst0|Add16~9, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~10 , hdmi_ctrl_inst|encode_inst0|Add16~10, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add12~0 , hdmi_ctrl_inst|encode_inst0|Add12~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m_n1[1] , hdmi_ctrl_inst|encode_inst0|q_m_n1[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add14~1 , hdmi_ctrl_inst|encode_inst0|Add14~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m_n0[1] , hdmi_ctrl_inst|encode_inst0|q_m_n0[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~13 , hdmi_ctrl_inst|encode_inst0|Add16~13, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~14 , hdmi_ctrl_inst|encode_inst0|Add16~14, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m_n1[0] , hdmi_ctrl_inst|encode_inst0|q_m_n1[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~15 , hdmi_ctrl_inst|encode_inst0|Add16~15, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Equal2~0 , hdmi_ctrl_inst|encode_inst0|Equal2~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Equal2~1 , hdmi_ctrl_inst|encode_inst0|Equal2~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|cnt[0]~6 , hdmi_ctrl_inst|encode_inst0|cnt[0]~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|cnt[3]~13 , hdmi_ctrl_inst|encode_inst0|cnt[3]~13, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add4~1 , hdmi_ctrl_inst|encode_inst0|Add4~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|de_reg1 , hdmi_ctrl_inst|encode_inst2|de_reg1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|de_reg2~feeder , hdmi_ctrl_inst|encode_inst2|de_reg2~feeder, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|de_reg2 , hdmi_ctrl_inst|encode_inst2|de_reg2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|cnt[3] , hdmi_ctrl_inst|encode_inst0|cnt[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|condition_2 , hdmi_ctrl_inst|encode_inst0|condition_2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|Add16~6 , hdmi_ctrl_inst|encode_inst0|Add16~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|cnt[4]~15 , hdmi_ctrl_inst|encode_inst0|cnt[4]~15, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|cnt[4] , hdmi_ctrl_inst|encode_inst0|cnt[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|condition_3~0 , hdmi_ctrl_inst|encode_inst0|condition_3~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|condition_3~2 , hdmi_ctrl_inst|encode_inst0|condition_3~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out~1 , hdmi_ctrl_inst|encode_inst0|data_out~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder , hdmi_ctrl_inst|encode_inst0|data_out[1]~feeder, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan0~0 , vga_ctrl_inst|LessThan0~0, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan0~1 , vga_ctrl_inst|LessThan0~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|c0_reg1 , hdmi_ctrl_inst|encode_inst2|c0_reg1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|c0_reg2 , hdmi_ctrl_inst|encode_inst2|c0_reg2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out[1] , hdmi_ctrl_inst|encode_inst0|data_out[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m[7]~1 , hdmi_ctrl_inst|encode_inst0|q_m[7]~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|q_m_reg[5] , hdmi_ctrl_inst|encode_inst0|q_m_reg[5], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out~4 , hdmi_ctrl_inst|encode_inst0|data_out~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder , hdmi_ctrl_inst|encode_inst0|data_out[5]~feeder, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out[5] , hdmi_ctrl_inst|encode_inst0|data_out[5], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan1~0 , vga_ctrl_inst|LessThan1~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|c1_reg1 , hdmi_ctrl_inst|encode_inst2|c1_reg1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder , hdmi_ctrl_inst|encode_inst2|c1_reg2~feeder, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|c1_reg2 , hdmi_ctrl_inst|encode_inst2|c1_reg2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out~7 , hdmi_ctrl_inst|encode_inst0|data_out~7, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out[9] , hdmi_ctrl_inst|encode_inst0|data_out[9], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4 , hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[4] , hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3 , hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~3, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[3] , hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2 , hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[2] , hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1 , hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[1] , hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0 , hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[0] , hdmi_ctrl_inst|par_to_ser_inst0|data_fall_s[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out[0] , hdmi_ctrl_inst|encode_inst0|data_out[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out~3 , hdmi_ctrl_inst|encode_inst0|data_out~3, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst0|data_out[2] , hdmi_ctrl_inst|encode_inst0|data_out[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1 , hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[1] , hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0 , hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[0] , hdmi_ctrl_inst|par_to_ser_inst0|data_rise_s[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] , hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0], hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|LessThan17~2 , vga_pic_inst|LessThan17~2, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[9]~15 , vga_pic_inst|pix_data[9]~15, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~35 , vga_pic_inst|pix_data~35, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~36 , vga_pic_inst|pix_data~36, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~21 , vga_pic_inst|pix_data~21, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~26 , vga_pic_inst|pix_data~26, hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_x[11]~0 , vga_ctrl_inst|pix_x[11]~0, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~27 , vga_pic_inst|pix_data~27, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[10] , vga_pic_inst|pix_data[10], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[10]~2 , vga_ctrl_inst|rgb[10]~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_in_reg[7] , hdmi_ctrl_inst|encode_inst1|data_in_reg[7], hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~29 , vga_pic_inst|pix_data~29, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~30 , vga_pic_inst|pix_data~30, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~31 , vga_pic_inst|pix_data~31, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[8] , vga_pic_inst|pix_data[8], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[6]~4 , vga_ctrl_inst|rgb[6]~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_in_reg[2] , hdmi_ctrl_inst|encode_inst1|data_in_reg[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add5~0 , hdmi_ctrl_inst|encode_inst1|Add5~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_in_n1[2] , hdmi_ctrl_inst|encode_inst1|data_in_n1[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add14~1 , hdmi_ctrl_inst|encode_inst1|Add14~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|q_m_n0[1] , hdmi_ctrl_inst|encode_inst1|q_m_n0[1], hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~28 , vga_pic_inst|pix_data~28, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[9] , vga_pic_inst|pix_data[9], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[7]~3 , vga_ctrl_inst|rgb[7]~3, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_in_reg[4] , hdmi_ctrl_inst|encode_inst1|data_in_reg[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add13~0 , hdmi_ctrl_inst|encode_inst1|Add13~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|q_m_n1[1] , hdmi_ctrl_inst|encode_inst1|q_m_n1[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add13~1 , hdmi_ctrl_inst|encode_inst1|Add13~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|q_m_n1[2] , hdmi_ctrl_inst|encode_inst1|q_m_n1[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|condition_3~0 , hdmi_ctrl_inst|encode_inst1|condition_3~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|condition_3~1 , hdmi_ctrl_inst|encode_inst1|condition_3~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add14~2 , hdmi_ctrl_inst|encode_inst1|Add14~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|q_m_n0[3] , hdmi_ctrl_inst|encode_inst1|q_m_n0[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|q_m_n1[0] , hdmi_ctrl_inst|encode_inst1|q_m_n1[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add15~0 , hdmi_ctrl_inst|encode_inst1|Add15~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add15~4 , hdmi_ctrl_inst|encode_inst1|Add15~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add14~0 , hdmi_ctrl_inst|encode_inst1|Add14~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|q_m_n0[2] , hdmi_ctrl_inst|encode_inst1|q_m_n0[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add23~2 , hdmi_ctrl_inst|encode_inst1|Add23~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~9 , hdmi_ctrl_inst|encode_inst1|Add16~9, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~10 , hdmi_ctrl_inst|encode_inst1|Add16~10, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0 , hdmi_ctrl_inst|encode_inst1|q_m_reg[8]~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|q_m_reg[8] , hdmi_ctrl_inst|encode_inst1|q_m_reg[8], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~15 , hdmi_ctrl_inst|encode_inst1|Add16~15, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|cnt[0]~7 , hdmi_ctrl_inst|encode_inst1|cnt[0]~7, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|cnt[0] , hdmi_ctrl_inst|encode_inst1|cnt[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Equal1~0 , hdmi_ctrl_inst|encode_inst1|Equal1~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Equal1~1 , hdmi_ctrl_inst|encode_inst1|Equal1~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|cnt[0]~6 , hdmi_ctrl_inst|encode_inst1|cnt[0]~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|cnt[1]~9 , hdmi_ctrl_inst|encode_inst1|cnt[1]~9, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|cnt[2]~11 , hdmi_ctrl_inst|encode_inst1|cnt[2]~11, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|cnt[2] , hdmi_ctrl_inst|encode_inst1|cnt[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~3 , hdmi_ctrl_inst|encode_inst1|Add16~3, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~4 , hdmi_ctrl_inst|encode_inst1|Add16~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|cnt[3]~13 , hdmi_ctrl_inst|encode_inst1|cnt[3]~13, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|cnt[3] , hdmi_ctrl_inst|encode_inst1|cnt[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Equal2~0 , hdmi_ctrl_inst|encode_inst1|Equal2~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|condition_2 , hdmi_ctrl_inst|encode_inst1|condition_2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out[0]~0 , hdmi_ctrl_inst|encode_inst1|data_out[0]~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~11 , hdmi_ctrl_inst|encode_inst1|Add16~11, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~12 , hdmi_ctrl_inst|encode_inst1|Add16~12, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|cnt[1] , hdmi_ctrl_inst|encode_inst1|cnt[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add22~6 , hdmi_ctrl_inst|encode_inst1|Add22~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|Add16~2 , hdmi_ctrl_inst|encode_inst1|Add16~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|cnt[4]~15 , hdmi_ctrl_inst|encode_inst1|cnt[4]~15, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|cnt[4] , hdmi_ctrl_inst|encode_inst1|cnt[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|condition_3~2 , hdmi_ctrl_inst|encode_inst1|condition_3~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|q_m_reg[3] , hdmi_ctrl_inst|encode_inst1|q_m_reg[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out~1 , hdmi_ctrl_inst|encode_inst1|data_out~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder , hdmi_ctrl_inst|encode_inst1|data_out[3]~feeder, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out[3] , hdmi_ctrl_inst|encode_inst1|data_out[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out~3 , hdmi_ctrl_inst|encode_inst1|data_out~3, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder , hdmi_ctrl_inst|encode_inst1|data_out[5]~feeder, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out[5] , hdmi_ctrl_inst|encode_inst1|data_out[5], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2 , hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[2] , hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1 , hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[1] , hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0 , hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[0] , hdmi_ctrl_inst|par_to_ser_inst1|data_fall_s[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out~7 , hdmi_ctrl_inst|encode_inst1|data_out~7, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst1|data_out[8] , hdmi_ctrl_inst|encode_inst1|data_out[8], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4 , hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[4] , hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3 , hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~3, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[3] , hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2 , hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[2] , hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1 , hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[1] , hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0 , hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[0] , hdmi_ctrl_inst|par_to_ser_inst1|data_rise_s[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] , hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0], hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~33 , vga_pic_inst|pix_data~33, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[13] , vga_pic_inst|pix_data[13], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[13]~6 , vga_ctrl_inst|rgb[13]~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_in_reg[3] , hdmi_ctrl_inst|encode_inst2|data_in_reg[3], hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~32 , vga_pic_inst|pix_data~32, hdmi_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[15] , vga_pic_inst|pix_data[15], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add6~0 , hdmi_ctrl_inst|encode_inst2|Add6~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_in_n1[2] , hdmi_ctrl_inst|encode_inst2|data_in_n1[2], hdmi_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[12]~5 , vga_ctrl_inst|rgb[12]~5, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_in_reg[4] , hdmi_ctrl_inst|encode_inst2|data_in_reg[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add12~0 , hdmi_ctrl_inst|encode_inst2|Add12~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m_n1[1] , hdmi_ctrl_inst|encode_inst2|q_m_n1[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add14~0 , hdmi_ctrl_inst|encode_inst2|Add14~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m_n0[2] , hdmi_ctrl_inst|encode_inst2|q_m_n0[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add12~1 , hdmi_ctrl_inst|encode_inst2|Add12~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m_n1[2] , hdmi_ctrl_inst|encode_inst2|q_m_n1[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|condition_3~0 , hdmi_ctrl_inst|encode_inst2|condition_3~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0 , hdmi_ctrl_inst|encode_inst2|q_m_reg[8]~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m_reg[8] , hdmi_ctrl_inst|encode_inst2|q_m_reg[8], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Equal2~0 , hdmi_ctrl_inst|encode_inst2|Equal2~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add19~0 , hdmi_ctrl_inst|encode_inst2|Add19~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~5 , hdmi_ctrl_inst|encode_inst2|Add16~5, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~6 , hdmi_ctrl_inst|encode_inst2|Add16~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Equal1~0 , hdmi_ctrl_inst|encode_inst2|Equal1~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Equal1~1 , hdmi_ctrl_inst|encode_inst2|Equal1~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|cnt[0]~6 , hdmi_ctrl_inst|encode_inst2|cnt[0]~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|cnt[0]~7 , hdmi_ctrl_inst|encode_inst2|cnt[0]~7, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|cnt[0] , hdmi_ctrl_inst|encode_inst2|cnt[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add15~0 , hdmi_ctrl_inst|encode_inst2|Add15~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~15 , hdmi_ctrl_inst|encode_inst2|Add16~15, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|cnt[1]~9 , hdmi_ctrl_inst|encode_inst2|cnt[1]~9, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|cnt[2]~11 , hdmi_ctrl_inst|encode_inst2|cnt[2]~11, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|cnt[3]~13 , hdmi_ctrl_inst|encode_inst2|cnt[3]~13, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|cnt[3] , hdmi_ctrl_inst|encode_inst2|cnt[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0 , hdmi_ctrl_inst|encode_inst2|q_m_n0[3]~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m_n0[3] , hdmi_ctrl_inst|encode_inst2|q_m_n0[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|condition_2 , hdmi_ctrl_inst|encode_inst2|condition_2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out[0]~0 , hdmi_ctrl_inst|encode_inst2|data_out[0]~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~14 , hdmi_ctrl_inst|encode_inst2|Add16~14, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|cnt[1] , hdmi_ctrl_inst|encode_inst2|cnt[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add23~2 , hdmi_ctrl_inst|encode_inst2|Add23~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add20~2 , hdmi_ctrl_inst|encode_inst2|Add20~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~7 , hdmi_ctrl_inst|encode_inst2|Add16~7, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~8 , hdmi_ctrl_inst|encode_inst2|Add16~8, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|cnt[2] , hdmi_ctrl_inst|encode_inst2|cnt[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m_n1[0] , hdmi_ctrl_inst|encode_inst2|q_m_n1[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add17~8 , hdmi_ctrl_inst|encode_inst2|Add17~8, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add23~6 , hdmi_ctrl_inst|encode_inst2|Add23~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~0 , hdmi_ctrl_inst|encode_inst2|Add16~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add20~6 , hdmi_ctrl_inst|encode_inst2|Add20~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|Add16~1 , hdmi_ctrl_inst|encode_inst2|Add16~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|cnt[4]~15 , hdmi_ctrl_inst|encode_inst2|cnt[4]~15, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|cnt[4] , hdmi_ctrl_inst|encode_inst2|cnt[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|condition_3~2 , hdmi_ctrl_inst|encode_inst2|condition_3~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m_reg[1] , hdmi_ctrl_inst|encode_inst2|q_m_reg[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out~1 , hdmi_ctrl_inst|encode_inst2|data_out~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder , hdmi_ctrl_inst|encode_inst2|data_out[1]~feeder, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out[1] , hdmi_ctrl_inst|encode_inst2|data_out[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m[7]~1 , hdmi_ctrl_inst|encode_inst2|q_m[7]~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|q_m_reg[5] , hdmi_ctrl_inst|encode_inst2|q_m_reg[5], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out~4 , hdmi_ctrl_inst|encode_inst2|data_out~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder , hdmi_ctrl_inst|encode_inst2|data_out[5]~feeder, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out[5] , hdmi_ctrl_inst|encode_inst2|data_out[5], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out~7 , hdmi_ctrl_inst|encode_inst2|data_out~7, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out[9] , hdmi_ctrl_inst|encode_inst2|data_out[9], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4 , hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~4, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[4] , hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[4], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3 , hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~3, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[3] , hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2 , hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[2] , hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1 , hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[1] , hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0 , hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[0] , hdmi_ctrl_inst|par_to_ser_inst2|data_fall_s[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out[0] , hdmi_ctrl_inst|encode_inst2|data_out[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out[4]~6 , hdmi_ctrl_inst|encode_inst2|data_out[4]~6, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell , hdmi_ctrl_inst|encode_inst2|c0_reg2~_wirecell, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|encode_inst2|data_out[6] , hdmi_ctrl_inst|encode_inst2|data_out[6], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3 , hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~3, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[3] , hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[3], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2 , hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~2, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[2] , hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[2], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1 , hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~1, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[1] , hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[1], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0 , hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s~0, hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[0] , hdmi_ctrl_inst|par_to_ser_inst2|data_rise_s[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] , hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst0|ALTDDIO_OUT_component|auto_generated|ddio_outa[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] , hdmi_ctrl_inst|par_to_ser_inst0|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] , hdmi_ctrl_inst|par_to_ser_inst1|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0], hdmi_colorbar, 1 +instance = comp, \hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0] , hdmi_ctrl_inst|par_to_ser_inst2|ddio_out_inst1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0], hdmi_colorbar, 1 diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_v.sdo b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_v.sdo new file mode 100644 index 0000000..e7677ed --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/quartus_prj/simulation/modelsim/hdmi_colorbar_v.sdo @@ -0,0 +1,9062 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "hdmi_colorbar") + (DATE "06/02/2023 04:17:19") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (4503:4503:4503) (4503:4503:4503)) + (PORT inclk[0] (2340:2340:2340) (2340:2340:2340)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1720:1720:1720) (1682:1682:1682)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (PORT sload (1425:1425:1425) (1434:1434:1434)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (PORT sclr (1477:1477:1477) (1540:1540:1540)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (PORT sclr (1477:1477:1477) (1540:1540:1540)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (PORT sclr (1477:1477:1477) (1540:1540:1540)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1695:1695:1695) (1667:1667:1667)) + (PORT clrn (1887:1887:1887) (1859:1859:1859)) + (PORT sload (1861:1861:1861) (1950:1950:1950)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1638:1638:1638) (1522:1522:1522)) + (PORT clrn (1891:1891:1891) (1861:1861:1861)) + (PORT sload (1745:1745:1745) (1782:1782:1782)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1909:1909:1909) (1832:1832:1832)) + (PORT clrn (1891:1891:1891) (1861:1861:1861)) + (PORT sload (1745:1745:1745) (1782:1782:1782)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (1087:1087:1087)) + (PORT datab (658:658:658) (680:680:680)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~2) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (653:653:653)) + (PORT datab (834:834:834) (829:829:829)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~4) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (619:619:619)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add20\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (632:632:632)) + (PORT datab (364:364:364) (446:446:446)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (894:894:894) (862:862:862)) + (PORT datab (648:648:648) (666:666:666)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (872:872:872)) + (PORT datab (615:615:615) (647:647:647)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~6) + (DELAY + (ABSOLUTE + (PORT datab (676:676:676) (689:689:689)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add17\~8) + (DELAY + (ABSOLUTE + (PORT datab (667:667:667) (676:676:676)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1151:1151:1151) (1087:1087:1087)) + (PORT datab (660:660:660) (683:683:683)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (651:651:651)) + (PORT datab (835:835:835) (829:829:829)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~4) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (617:617:617)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add23\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (635:635:635)) + (PORT datab (368:368:368) (450:450:450)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (879:879:879)) + (PORT datab (650:650:650) (669:669:669)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~4) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (820:820:820)) + (PORT datab (617:617:617) (649:649:649)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~6) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (905:905:905)) + (PORT datab (678:678:678) (691:691:691)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add15\~8) + (DELAY + (ABSOLUTE + (PORT datab (669:669:669) (678:678:678)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (471:471:471)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~4) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (655:655:655)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (278:278:278) (303:303:303)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (739:739:739)) + (PORT datab (275:275:275) (299:299:299)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (477:477:477)) + (PORT datab (275:275:275) (299:299:299)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1593:1593:1593) (1472:1472:1472)) + (PORT clrn (1887:1887:1887) (1859:1859:1859)) + (PORT sload (1861:1861:1861) (1950:1950:1950)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1138:1138:1138)) + (PORT datab (1156:1156:1156) (1099:1099:1099)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1117:1117:1117) (1073:1073:1073)) + (PORT datab (1847:1847:1847) (1760:1760:1760)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~4) + (DELAY + (ABSOLUTE + (PORT datab (954:954:954) (924:924:924)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add20\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (878:878:878)) + (PORT datab (564:564:564) (590:590:590)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (889:889:889)) + (PORT datab (1145:1145:1145) (1082:1082:1082)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (902:902:902)) + (PORT datab (1132:1132:1132) (1072:1072:1072)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~6) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (895:895:895)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add17\~8) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (872:872:872)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1195:1195:1195) (1136:1136:1136)) + (PORT datab (1157:1157:1157) (1100:1100:1100)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~4) + (DELAY + (ABSOLUTE + (PORT datab (955:955:955) (925:925:925)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1827:1827:1827) (1698:1698:1698)) + (PORT datab (921:921:921) (895:895:895)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~6) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (896:896:896)) + (PORT datab (901:901:901) (878:878:878)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~8) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (871:871:871)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (872:872:872)) + (PORT datab (644:644:644) (657:657:657)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~2) + (DELAY + (ABSOLUTE + (PORT dataa (924:924:924) (906:906:906)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (859:859:859)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add19\~6) + (DELAY + (ABSOLUTE + (PORT datad (590:590:590) (616:616:616)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (873:873:873)) + (PORT datab (643:643:643) (656:656:656)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~2) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (904:904:904)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~4) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (859:859:859)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1639:1639:1639) (1523:1523:1523)) + (PORT clrn (1891:1891:1891) (1861:1861:1861)) + (PORT sload (1745:1745:1745) (1782:1782:1782)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~0) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (913:913:913)) + (PORT datab (912:912:912) (901:901:901)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~4) + (DELAY + (ABSOLUTE + (PORT datab (826:826:826) (816:816:816)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (864:864:864) (829:829:829)) + (PORT datab (358:358:358) (434:434:434)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (572:572:572) (609:609:609)) + (PORT datab (835:835:835) (807:807:807)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (445:445:445)) + (PORT datab (823:823:823) (799:799:799)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~6) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (829:829:829)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~0) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (912:912:912)) + (PORT datab (908:908:908) (897:897:897)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~4) + (DELAY + (ABSOLUTE + (PORT datab (823:823:823) (813:813:813)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~2) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (822:822:822)) + (PORT datab (368:368:368) (449:449:449)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~4) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (458:458:458)) + (PORT datab (870:870:870) (840:840:840)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~6) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (866:866:866)) + (PORT datab (360:360:360) (437:437:437)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~8) + (DELAY + (ABSOLUTE + (PORT datad (355:355:355) (432:432:432)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~2) + (DELAY + (ABSOLUTE + (PORT datab (581:581:581) (607:607:607)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~4) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (617:617:617)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~6) + (DELAY + (ABSOLUTE + (PORT datad (594:594:594) (617:617:617)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (905:905:905)) + (PORT datab (863:863:863) (851:851:851)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~2) + (DELAY + (ABSOLUTE + (PORT datab (583:583:583) (610:610:610)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~4) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (619:619:619)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add22\~6) + (DELAY + (ABSOLUTE + (PORT datad (596:596:596) (619:619:619)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1674:1674:1674) (1551:1551:1551)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (PORT sload (1763:1763:1763) (1796:1796:1796)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1578:1578:1578) (1474:1474:1474)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (PORT sload (1624:1624:1624) (1684:1684:1684)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1720:1720:1720) (1681:1681:1681)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (PORT sload (1425:1425:1425) (1434:1434:1434)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (460:460:460)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (970:970:970)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (627:627:627) (630:630:630)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (585:585:585) (622:622:622)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (629:629:629) (633:633:633)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT datab (625:625:625) (633:633:633)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (609:609:609)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT datab (624:624:624) (633:633:633)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datab (593:593:593) (620:620:620)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT datac (296:296:296) (374:374:374)) + (PORT datad (407:407:407) (519:519:519)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (654:654:654)) + (PORT datab (655:655:655) (676:676:676)) + (PORT datac (534:534:534) (564:564:564)) + (PORT datad (523:523:523) (548:548:548)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (858:858:858)) + (PORT datab (649:649:649) (667:667:667)) + (PORT datac (574:574:574) (610:610:610)) + (PORT datad (553:553:553) (583:583:583)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (912:912:912)) + (PORT datab (911:911:911) (901:901:901)) + (PORT datac (899:899:899) (887:887:887)) + (PORT datad (822:822:822) (805:805:805)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT datac (304:304:304) (387:387:387)) + (PORT datad (407:407:407) (519:519:519)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (770:770:770)) + (PORT datab (865:865:865) (826:826:826)) + (PORT datac (750:750:750) (670:670:670)) + (PORT datad (263:263:263) (281:281:281)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~1) + (DELAY + (ABSOLUTE + (PORT dataa (795:795:795) (721:721:721)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (745:745:745) (662:662:662)) + (PORT datad (757:757:757) (701:701:701)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (842:842:842) (796:796:796)) + (PORT datac (535:535:535) (512:512:512)) + (PORT datad (454:454:454) (434:434:434)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (480:480:480)) + (PORT datab (543:543:543) (503:503:503)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (805:805:805) (758:758:758)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (877:877:877) (824:824:824)) + (PORT datab (866:866:866) (826:826:826)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (470:470:470) (442:442:442)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (762:762:762)) + (PORT datab (276:276:276) (300:300:300)) + (PORT datac (535:535:535) (511:511:511)) + (PORT datad (803:803:803) (756:756:756)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~8) + (DELAY + (ABSOLUTE + (PORT dataa (760:760:760) (691:691:691)) + (PORT datab (530:530:530) (493:493:493)) + (PORT datac (432:432:432) (415:415:415)) + (PORT datad (516:516:516) (508:508:508)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~11) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (484:484:484)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (535:535:535) (511:511:511)) + (PORT datad (803:803:803) (755:755:755)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~12) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (313:313:313)) + (PORT datab (755:755:755) (701:701:701)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (800:800:800) (752:752:752)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~16) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (561:561:561)) + (PORT datac (843:843:843) (804:804:804)) + (PORT datad (323:323:323) (393:393:393)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datac (627:627:627) (653:653:653)) + (PORT datad (246:246:246) (271:271:271)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add12\~1) + (DELAY + (ABSOLUTE + (PORT datab (1351:1351:1351) (1290:1290:1290)) + (PORT datad (1269:1269:1269) (1219:1219:1219)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (800:800:800)) + (PORT datab (955:955:955) (950:950:950)) + (PORT datac (833:833:833) (778:778:778)) + (PORT datad (823:823:823) (778:778:778)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (422:422:422)) + (PORT datab (338:338:338) (415:415:415)) + (PORT datac (1078:1078:1078) (1104:1104:1104)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (859:859:859)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (491:491:491) (465:465:465)) + (PORT datad (1139:1139:1139) (1035:1035:1035)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~1) + (DELAY + (ABSOLUTE + (PORT dataa (747:747:747) (682:682:682)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (236:236:236) (263:263:263)) + (PORT datad (1138:1138:1138) (1034:1034:1034)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (339:339:339)) + (PORT datab (740:740:740) (675:675:675)) + (PORT datac (1032:1032:1032) (927:927:927)) + (PORT datad (837:837:837) (830:830:830)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1075:1075:1075) (974:974:974)) + (PORT datab (476:476:476) (461:461:461)) + (PORT datac (235:235:235) (261:261:261)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (1089:1089:1089) (992:992:992)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (1498:1498:1498) (1433:1433:1433)) + (PORT datad (535:535:535) (510:510:510)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~8) + (DELAY + (ABSOLUTE + (PORT dataa (761:761:761) (694:694:694)) + (PORT datab (274:274:274) (299:299:299)) + (PORT datac (1046:1046:1046) (946:946:946)) + (PORT datad (855:855:855) (828:828:828)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~13) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (544:544:544) (508:508:508)) + (PORT datac (852:852:852) (812:812:812)) + (PORT datad (1139:1139:1139) (1035:1035:1035)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~14) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (275:275:275) (299:299:299)) + (PORT datac (446:446:446) (428:428:428)) + (PORT datad (1139:1139:1139) (1035:1035:1035)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~16) + (DELAY + (ABSOLUTE + (PORT datab (884:884:884) (819:819:819)) + (PORT datac (527:527:527) (559:559:559)) + (PORT datad (831:831:831) (826:826:826)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (474:474:474)) + (PORT datad (839:839:839) (832:832:832)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT asdata (812:812:812) (920:920:920)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (479:479:479)) + (PORT datab (820:820:820) (746:746:746)) + (PORT datad (782:782:782) (722:722:722)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (825:825:825) (781:781:781)) + (PORT datad (771:771:771) (703:703:703)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (764:764:764) (699:699:699)) + (PORT datab (858:858:858) (804:804:804)) + (PORT datac (812:812:812) (756:756:756)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (424:424:424)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (753:753:753)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (800:800:800) (757:757:757)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~9) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (829:829:829)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (776:776:776) (757:757:757)) + (PORT datad (775:775:775) (731:731:731)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~10) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (875:875:875) (847:847:847)) + (PORT datac (444:444:444) (416:416:416)) + (PORT datad (774:774:774) (731:731:731)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~11) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (310:310:310)) + (PORT datab (749:749:749) (675:675:675)) + (PORT datac (817:817:817) (761:761:761)) + (PORT datad (800:800:800) (758:758:758)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~12) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (467:467:467)) + (PORT datab (541:541:541) (500:500:500)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (800:800:800) (758:758:758)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~13) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (831:831:831)) + (PORT datab (605:605:605) (619:619:619)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (775:775:775) (732:732:732)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~16) + (DELAY + (ABSOLUTE + (PORT datab (380:380:380) (471:471:471)) + (PORT datac (816:816:816) (798:798:798)) + (PORT datad (832:832:832) (765:765:765)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datab (842:842:842) (749:749:749)) + (PORT datad (546:546:546) (575:575:575)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add14\~1) + (DELAY + (ABSOLUTE + (PORT datab (989:989:989) (988:988:988)) + (PORT datac (1022:1022:1022) (1037:1037:1037)) + (PORT datad (958:958:958) (970:970:970)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~2) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (477:477:477)) + (PORT datab (333:333:333) (409:409:409)) + (PORT datac (772:772:772) (715:715:715)) + (PORT datad (817:817:817) (739:739:739)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~3) + (DELAY + (ABSOLUTE + (PORT datab (1255:1255:1255) (1209:1209:1209)) + (PORT datac (944:944:944) (966:966:966)) + (PORT datad (755:755:755) (685:685:685)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (851:851:851)) + (PORT datab (366:366:366) (449:449:449)) + (PORT datac (326:326:326) (411:411:411)) + (PORT datad (328:328:328) (401:401:401)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1839:1839:1839) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (765:765:765) (716:716:716)) + (PORT datab (889:889:889) (877:877:877)) + (PORT datac (753:753:753) (687:687:687)) + (PORT datad (245:245:245) (267:267:267)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1168:1168:1168) (1142:1142:1142)) + (PORT datad (1267:1267:1267) (1216:1216:1216)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~5) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (806:806:806)) + (PORT datab (956:956:956) (950:950:950)) + (PORT datac (833:833:833) (778:778:778)) + (PORT datad (823:823:823) (778:778:778)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (537:537:537) (565:565:565)) + (PORT datac (1078:1078:1078) (1103:1103:1103)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (426:426:426)) + (PORT datab (1095:1095:1095) (1095:1095:1095)) + (PORT datac (295:295:295) (373:373:373)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT asdata (804:804:804) (886:886:886)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~4) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (476:476:476)) + (PORT datab (825:825:825) (751:751:751)) + (PORT datad (775:775:775) (715:715:715)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1020:1020:1020) (1034:1034:1034)) + (PORT datad (928:928:928) (938:938:938)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~5) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (366:366:366)) + (PORT datab (336:336:336) (412:412:412)) + (PORT datac (569:569:569) (609:609:609)) + (PORT datad (281:281:281) (305:305:305)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_x\[10\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (854:854:854) (811:811:811)) + (PORT datad (522:522:522) (522:522:522)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (901:901:901)) + (PORT datac (1188:1188:1188) (1099:1099:1099)) + (PORT datad (929:929:929) (884:884:884)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|always0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (937:937:937) (879:879:879)) + (PORT datac (1512:1512:1512) (1404:1404:1404)) + (PORT datad (272:272:272) (294:294:294)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[9\]\~14) + (DELAY + (ABSOLUTE + (PORT datac (1188:1188:1188) (1100:1100:1100)) + (PORT datad (889:889:889) (849:849:849)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~16) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (341:341:341)) + (PORT datab (292:292:292) (326:326:326)) + (PORT datac (858:858:858) (809:809:809)) + (PORT datad (856:856:856) (807:807:807)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~8) + (DELAY + (ABSOLUTE + (PORT datab (937:937:937) (896:896:896)) + (PORT datac (854:854:854) (819:819:819)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[10\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (1456:1456:1456) (1327:1327:1327)) + (PORT datad (565:565:565) (552:552:552)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (1351:1351:1351) (1290:1290:1290)) + (PORT datac (1168:1168:1168) (1143:1143:1143)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[6\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (825:825:825)) + (PORT datab (955:955:955) (949:949:949)) + (PORT datad (823:823:823) (779:779:779)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1887:1887:1887) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~4) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (423:423:423)) + (PORT datac (1078:1078:1078) (1103:1103:1103)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (865:865:865)) + (PORT datab (867:867:867) (809:809:809)) + (PORT datac (518:518:518) (527:527:527)) + (PORT datad (531:531:531) (521:521:521)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~22) + (DELAY + (ABSOLUTE + (PORT datac (855:855:855) (812:812:812)) + (PORT datad (484:484:484) (461:461:461)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~23) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (572:572:572)) + (PORT datab (278:278:278) (304:304:304)) + (PORT datac (519:519:519) (529:529:529)) + (PORT datad (529:529:529) (511:511:511)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (602:602:602) (571:571:571)) + (PORT datad (484:484:484) (460:460:460)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (900:900:900) (862:862:862)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (518:518:518) (527:527:527)) + (PORT datad (531:531:531) (522:522:522)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~25) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (327:327:327)) + (PORT datab (823:823:823) (731:731:731)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (244:244:244) (266:266:266)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (382:382:382) (470:470:470)) + (PORT datac (356:356:356) (475:475:475)) + (PORT datad (580:580:580) (608:608:608)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~5) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (862:862:862)) + (PORT datab (806:806:806) (759:759:759)) + (PORT datac (987:987:987) (856:856:856)) + (PORT datad (818:818:818) (801:801:801)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (416:416:416)) + (PORT datac (1040:1040:1040) (1056:1056:1056)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m\[4\]\~2) + (DELAY + (ABSOLUTE + (PORT datab (961:961:961) (944:944:944)) + (PORT datad (921:921:921) (915:915:915)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~4) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (424:424:424)) + (PORT datab (1046:1046:1046) (1067:1067:1067)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1154:1154:1154) (1104:1104:1104)) + (PORT datab (898:898:898) (863:863:863)) + (PORT datac (1230:1230:1230) (1212:1212:1212)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (396:396:396) (497:497:497)) + (PORT datac (348:348:348) (466:466:466)) + (PORT datad (586:586:586) (614:614:614)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~6) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (669:669:669)) + (PORT datab (370:370:370) (453:453:453)) + (PORT datac (1254:1254:1254) (1224:1224:1224)) + (PORT datad (264:264:264) (281:281:281)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1004:1004:1004) (1011:1011:1011)) + (PORT datab (1256:1256:1256) (1209:1209:1209)) + (PORT datac (571:571:571) (611:611:611)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~37) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (840:840:840)) + (PORT datab (567:567:567) (572:572:572)) + (PORT datac (860:860:860) (818:818:818)) + (PORT datad (245:245:245) (267:267:267)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (446:446:446) (409:409:409)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT dataa (1121:1121:1121) (1033:1033:1033)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (818:818:818)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (469:469:469) (437:437:437)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datab (1177:1177:1177) (1055:1055:1055)) + (IOPATH datab combout (472:472:472) (473:473:473)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_clk_p\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2838:2838:2838) (2775:2775:2775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_clk_n\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2838:2838:2838) (2775:2775:2775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_p\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2848:2848:2848) (2785:2785:2785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_p\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2848:2848:2848) (2785:2785:2785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_p\[2\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2848:2848:2848) (2785:2785:2785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_n\[0\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2838:2838:2838) (2775:2775:2775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_n\[1\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2858:2858:2858) (2795:2795:2795)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tmds_data_n\[2\]\~output) + (DELAY + (ABSOLUTE + (IOPATH i o (2848:2848:2848) (2785:2785:2785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\~0) + (DELAY + (ABSOLUTE + (PORT datab (450:450:450) (567:567:567)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|Add0\~1) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (378:378:378)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1069:1069:1069) (1226:1226:1226)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (414:414:414)) + (PORT datad (305:305:305) (378:378:378)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT sclr (1069:1069:1069) (1226:1226:1226)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (423:423:423)) + (PORT datad (407:407:407) (519:519:519)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (405:405:405) (517:517:517)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (452:452:452) (569:569:569)) + (PORT datac (298:298:298) (377:377:377)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT datac (302:302:302) (385:385:385)) + (PORT datad (408:408:408) (520:520:520)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (417:417:417)) + (PORT datad (406:406:406) (517:517:517)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (413:413:413)) + (PORT datad (406:406:406) (518:518:518)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (806:806:806) (852:852:852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1793:1793:1793) (1777:1777:1777)) + (PORT D (1304:1304:1304) (1328:1328:1328)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1793:1793:1793) (1777:1777:1777)) + (PORT d (1340:1340:1340) (1366:1366:1366)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1966:1966:1966) (1972:1972:1972)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1796:1796:1796) (1779:1779:1779)) + (PORT D (902:902:902) (941:941:941)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1796:1796:1796) (1779:1779:1779)) + (PORT d (989:989:989) (1033:1033:1033)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1969:1969:1969) (1974:1974:1974)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst3\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (1456:1456:1456) (1495:1495:1495)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5321:5321:5321) (5126:5126:5126)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (4410:4410:4410) (4581:4581:4581)) + (PORT datab (334:334:334) (410:410:410)) + (PORT datad (735:735:735) (769:769:769)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1831:1831:1831) (1724:1724:1724)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (456:456:456)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (450:450:450)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (484:484:484)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (459:459:459)) + (PORT datab (367:367:367) (449:449:449)) + (PORT datac (325:325:325) (410:410:410)) + (PORT datad (327:327:327) (404:404:404)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (386:386:386) (464:464:464)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datab (396:396:396) (476:476:476)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~20) + (DELAY + (ABSOLUTE + (PORT datab (391:391:391) (473:473:473)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~22) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (484:484:484)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (485:485:485)) + (PORT datab (393:393:393) (476:476:476)) + (PORT datac (353:353:353) (438:438:438)) + (PORT datad (350:350:350) (427:427:427)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1109:1109:1109) (1022:1022:1022)) + (PORT datab (928:928:928) (885:885:885)) + (PORT datac (921:921:921) (868:868:868)) + (PORT datad (1141:1141:1141) (1043:1043:1043)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (664:664:664) (684:684:684)) + (PORT datab (1270:1270:1270) (1209:1209:1209)) + (PORT datac (583:583:583) (606:606:606)) + (PORT datad (581:581:581) (607:607:607)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~2) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (354:354:354)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (272:272:272) (304:304:304)) + (PORT datad (764:764:764) (688:688:688)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~1) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (354:354:354)) + (PORT datab (313:313:313) (342:342:342)) + (PORT datac (239:239:239) (266:266:266)) + (PORT datad (764:764:764) (689:689:689)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT datab (1268:1268:1268) (1206:1206:1206)) + (PORT datac (582:582:582) (606:606:606)) + (PORT datad (581:581:581) (606:606:606)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (610:610:610) (647:647:647)) + (PORT datab (671:671:671) (687:687:687)) + (PORT datac (623:623:623) (645:645:645)) + (PORT datad (745:745:745) (678:678:678)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (627:627:627)) + (PORT datab (879:879:879) (839:839:839)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (627:627:627)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (596:596:596)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~7) + (DELAY + (ABSOLUTE + (PORT dataa (642:642:642) (653:653:653)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~9) + (DELAY + (ABSOLUTE + (PORT datab (1264:1264:1264) (1202:1202:1202)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT datab (640:640:640) (654:654:654)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT datab (583:583:583) (606:606:606)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (659:659:659) (677:677:677)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (650:650:650) (659:659:659)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~18) + (DELAY + (ABSOLUTE + (PORT datab (645:645:645) (650:650:650)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (911:911:911) (876:876:876)) + (PORT datab (569:569:569) (575:575:575)) + (PORT datac (520:520:520) (529:529:529)) + (PORT datad (529:529:529) (520:520:520)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~5) + (DELAY + (ABSOLUTE + (PORT dataa (611:611:611) (648:648:648)) + (PORT datac (625:625:625) (647:647:647)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT datab (970:970:970) (903:903:903)) + (PORT datac (883:883:883) (844:844:844)) + (PORT datad (1143:1143:1143) (1045:1045:1045)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (473:473:473)) + (PORT datab (379:379:379) (446:446:446)) + (PORT datad (1204:1204:1204) (1128:1128:1128)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (1456:1456:1456) (1328:1328:1328)) + (PORT datad (564:564:564) (551:551:551)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1839:1839:1839) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (760:760:760) (694:694:694)) + (PORT datab (379:379:379) (445:445:445)) + (PORT datad (1205:1205:1205) (1129:1129:1129)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (455:455:455)) + (PORT datab (365:365:365) (447:447:447)) + (PORT datac (560:560:560) (575:575:575)) + (PORT datad (327:327:327) (400:400:400)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (763:763:763) (715:715:715)) + (PORT datab (376:376:376) (441:441:441)) + (PORT datad (1210:1210:1210) (1134:1134:1134)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (497:497:497)) + (PORT datab (375:375:375) (439:439:439)) + (PORT datad (1214:1214:1214) (1138:1138:1138)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (812:812:812) (754:754:754)) + (PORT datab (310:310:310) (339:339:339)) + (PORT datac (329:329:329) (413:413:413)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT datab (357:357:357) (433:433:433)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (601:601:601)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datad (1423:1423:1423) (1292:1292:1292)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1839:1839:1839) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (475:475:475) (462:462:462)) + (PORT datab (375:375:375) (440:440:440)) + (PORT datad (1213:1213:1213) (1137:1137:1137)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (381:381:381) (475:475:475)) + (PORT datab (393:393:393) (476:476:476)) + (PORT datac (568:568:568) (594:594:594)) + (PORT datad (331:331:331) (409:409:409)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[11\]\~0) + (DELAY + (ABSOLUTE + (PORT datab (287:287:287) (315:315:315)) + (PORT datac (239:239:239) (265:265:265)) + (PORT datad (1212:1212:1212) (1135:1135:1135)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (737:737:737)) + (PORT datab (379:379:379) (444:444:444)) + (PORT datad (1206:1206:1206) (1129:1129:1129)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (489:489:489) (466:466:466)) + (PORT datab (380:380:380) (446:446:446)) + (PORT datad (1203:1203:1203) (1127:1127:1127)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (627:627:627) (631:631:631)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (515:515:515)) + (PORT datab (484:484:484) (453:453:453)) + (PORT datad (1209:1209:1209) (1133:1133:1133)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~22) + (DELAY + (ABSOLUTE + (PORT datad (320:320:320) (390:390:390)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[11\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (609:609:609)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datad (1416:1416:1416) (1285:1285:1285)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1839:1839:1839) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (867:867:867)) + (PORT datab (938:938:938) (897:897:897)) + (PORT datac (601:601:601) (619:619:619)) + (PORT datad (556:556:556) (578:578:578)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~4) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (728:728:728)) + (PORT datac (851:851:851) (827:827:827)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~6) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (554:554:554)) + (PORT datab (669:669:669) (685:685:685)) + (PORT datac (622:622:622) (644:644:644)) + (PORT datad (743:743:743) (677:677:677)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~7) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (719:719:719)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (261:261:261) (286:286:286)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (573:573:573)) + (PORT datab (772:772:772) (714:714:714)) + (PORT datac (519:519:519) (528:528:528)) + (PORT datad (530:530:530) (512:512:512)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (580:580:580)) + (PORT datab (568:568:568) (574:574:574)) + (PORT datac (862:862:862) (821:821:821)) + (PORT datad (246:246:246) (268:268:268)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~13) + (DELAY + (ABSOLUTE + (PORT dataa (495:495:495) (490:490:490)) + (PORT datab (498:498:498) (492:492:492)) + (PORT datac (1541:1541:1541) (1408:1408:1408)) + (PORT datad (888:888:888) (834:834:834)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~17) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (574:574:574)) + (PORT datac (518:518:518) (527:527:527)) + (PORT datad (532:532:532) (514:514:514)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~34) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (841:841:841)) + (PORT datab (568:568:568) (573:573:573)) + (PORT datac (861:861:861) (820:820:820)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (573:573:573)) + (PORT datad (531:531:531) (513:513:513)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (867:867:867)) + (PORT datab (566:566:566) (570:570:570)) + (PORT datac (518:518:518) (527:527:527)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[13\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (877:877:877)) + (PORT datac (1395:1395:1395) (1222:1222:1222)) + (PORT datad (846:846:846) (790:790:790)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~18) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (843:843:843)) + (PORT datab (284:284:284) (314:314:314)) + (PORT datac (839:839:839) (785:785:785)) + (PORT datad (254:254:254) (287:287:287)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~20) + (DELAY + (ABSOLUTE + (PORT datad (552:552:552) (568:568:568)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~4) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (904:904:904)) + (PORT datab (914:914:914) (863:863:863)) + (PORT datac (1184:1184:1184) (1094:1094:1094)) + (PORT datad (934:934:934) (889:889:889)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~3) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (865:865:865)) + (PORT datab (920:920:920) (871:871:871)) + (PORT datac (1512:1512:1512) (1404:1404:1404)) + (PORT datad (236:236:236) (255:255:255)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (903:903:903)) + (PORT datac (863:863:863) (825:825:825)) + (PORT datad (930:930:930) (885:885:885)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~19) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (843:843:843)) + (PORT datab (557:557:557) (517:517:517)) + (PORT datac (713:713:713) (629:629:629)) + (PORT datad (886:886:886) (832:832:832)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~20) + (DELAY + (ABSOLUTE + (PORT datab (293:293:293) (327:327:327)) + (PORT datac (839:839:839) (786:786:786)) + (PORT datad (246:246:246) (268:268:268)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1161:1161:1161) (1056:1056:1056)) + (PORT datab (875:875:875) (820:820:820)) + (PORT datac (303:303:303) (386:386:386)) + (PORT datad (305:305:305) (379:379:379)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_in_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[8\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (1272:1272:1272) (1221:1221:1221)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT asdata (1683:1683:1683) (1621:1621:1621)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (629:629:629) (641:641:641)) + (PORT datab (371:371:371) (451:451:451)) + (PORT datac (329:329:329) (412:412:412)) + (PORT datad (338:338:338) (422:422:422)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (312:312:312) (342:342:342)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (326:326:326) (399:399:399)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1171:1171:1171)) + (PORT datab (1498:1498:1498) (1358:1358:1358)) + (PORT datac (305:305:305) (388:388:388)) + (PORT datad (812:812:812) (770:770:770)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_in_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[2\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1264:1264:1264) (1172:1172:1172)) + (PORT datab (873:873:873) (818:818:818)) + (PORT datac (1455:1455:1455) (1319:1319:1319)) + (PORT datad (304:304:304) (378:378:378)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_in_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add14\~0) + (DELAY + (ABSOLUTE + (PORT datab (1349:1349:1349) (1288:1288:1288)) + (PORT datac (1169:1169:1169) (1143:1143:1143)) + (PORT datad (1270:1270:1270) (1219:1219:1219)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (239:239:239) (257:257:257)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (613:613:613)) + (PORT datab (954:954:954) (909:909:909)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~2) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (470:470:470)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add19\~6) + (DELAY + (ABSOLUTE + (PORT datab (386:386:386) (463:463:463)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (592:592:592)) + (PORT datab (955:955:955) (950:950:950)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~2) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (650:650:650)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add22\~6) + (DELAY + (ABSOLUTE + (PORT datad (565:565:565) (579:579:579)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (559:559:559)) + (PORT datab (502:502:502) (484:484:484)) + (PORT datac (236:236:236) (263:263:263)) + (PORT datad (454:454:454) (434:434:434)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (823:823:823)) + (PORT datab (950:950:950) (944:944:944)) + (PORT datad (822:822:822) (778:778:778)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~9) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (530:530:530)) + (PORT datab (279:279:279) (304:304:304)) + (PORT datac (838:838:838) (805:805:805)) + (PORT datad (822:822:822) (778:778:778)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~10) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (813:813:813)) + (PORT datab (479:479:479) (462:462:462)) + (PORT datac (816:816:816) (749:749:749)) + (PORT datad (486:486:486) (455:455:455)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add12\~0) + (DELAY + (ABSOLUTE + (PORT datab (1349:1349:1349) (1287:1287:1287)) + (PORT datac (1170:1170:1170) (1145:1145:1145)) + (PORT datad (1274:1274:1274) (1223:1223:1223)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add14\~1) + (DELAY + (ABSOLUTE + (PORT datab (1350:1350:1350) (1288:1288:1288)) + (PORT datac (1169:1169:1169) (1144:1144:1144)) + (PORT datad (1271:1271:1271) (1221:1221:1221)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n0\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~13) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (530:530:530)) + (PORT datab (280:280:280) (305:305:305)) + (PORT datac (882:882:882) (850:850:850)) + (PORT datad (822:822:822) (778:778:778)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~14) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (795:795:795)) + (PORT datab (278:278:278) (304:304:304)) + (PORT datac (793:793:793) (770:770:770)) + (PORT datad (453:453:453) (429:429:429)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_n1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (1588:1588:1588) (1540:1540:1540)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~15) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (560:560:560)) + (PORT datab (530:530:530) (493:493:493)) + (PORT datac (477:477:477) (446:446:446)) + (PORT datad (896:896:896) (862:862:862)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (654:654:654)) + (PORT datab (654:654:654) (676:676:676)) + (PORT datac (534:534:534) (564:564:564)) + (PORT datad (523:523:523) (548:548:548)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT datac (866:866:866) (839:839:839)) + (PORT datad (477:477:477) (451:451:451)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (496:496:496)) + (PORT datab (475:475:475) (459:459:459)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (728:728:728)) + (PORT datab (541:541:541) (504:504:504)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1166:1166:1166)) + (PORT datac (1452:1452:1452) (1315:1315:1315)) + (PORT datad (812:812:812) (771:771:771)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|de_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|de_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (368:368:368)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|de_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (PORT sclr (1477:1477:1477) (1540:1540:1540)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_2) + (DELAY + (ABSOLUTE + (PORT dataa (287:287:287) (322:322:322)) + (PORT datab (903:903:903) (872:872:872)) + (PORT datac (626:626:626) (652:652:652)) + (PORT datad (479:479:479) (453:453:453)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|Add16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (955:955:955) (950:950:950)) + (PORT datac (799:799:799) (791:791:791)) + (PORT datad (822:822:822) (778:778:778)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (472:472:472)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (PORT sclr (1477:1477:1477) (1540:1540:1540)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (653:653:653)) + (PORT datab (656:656:656) (677:677:677)) + (PORT datac (534:534:534) (564:564:564)) + (PORT datad (523:523:523) (548:548:548)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|condition_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (502:502:502)) + (PORT datab (904:904:904) (872:872:872)) + (PORT datac (616:616:616) (639:639:639)) + (PORT datad (470:470:470) (442:442:442)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (804:804:804) (747:747:747)) + (PORT datab (361:361:361) (437:437:437)) + (PORT datad (794:794:794) (719:719:719)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (738:738:738) (668:668:668)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (870:870:870)) + (PORT datab (648:648:648) (652:652:652)) + (PORT datac (594:594:594) (617:617:617)) + (PORT datad (554:554:554) (569:569:569)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (667:667:667) (686:686:686)) + (PORT datab (645:645:645) (658:658:658)) + (PORT datac (1230:1230:1230) (1173:1173:1173)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c0_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c0_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT asdata (760:760:760) (829:829:829)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1694:1694:1694) (1667:1667:1667)) + (PORT clrn (1887:1887:1887) (1859:1859:1859)) + (PORT sload (1861:1861:1861) (1950:1950:1950)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT datab (1349:1349:1349) (1288:1288:1288)) + (PORT datad (1273:1273:1273) (1222:1222:1222)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|q_m_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~4) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (825:825:825)) + (PORT datab (954:954:954) (948:948:948)) + (PORT datac (811:811:811) (773:773:773)) + (PORT datad (823:823:823) (778:778:778)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (679:679:679) (607:607:607)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1697:1697:1697) (1671:1671:1671)) + (PORT clrn (1887:1887:1887) (1859:1859:1859)) + (PORT sload (1861:1861:1861) (1950:1950:1950)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (476:476:476)) + (PORT datab (396:396:396) (480:480:480)) + (PORT datac (548:548:548) (569:569:569)) + (PORT datad (246:246:246) (271:271:271)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c1_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c1_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1396:1396:1396) (1298:1298:1298)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c1_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~7) + (DELAY + (ABSOLUTE + (PORT dataa (821:821:821) (749:749:749)) + (PORT datab (1282:1282:1282) (1246:1246:1246)) + (PORT datac (1097:1097:1097) (1062:1062:1062)) + (PORT datad (909:909:909) (898:898:898)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1887:1887:1887) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (412:412:412)) + (PORT datac (1077:1077:1077) (1103:1103:1103)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (346:346:346) (429:429:429)) + (PORT datac (1077:1077:1077) (1103:1103:1103)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (431:431:431)) + (PORT datac (1077:1077:1077) (1103:1103:1103)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (423:423:423)) + (PORT datac (1077:1077:1077) (1103:1103:1103)) + (PORT datad (295:295:295) (365:365:365)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (415:415:415)) + (PORT datac (1078:1078:1078) (1104:1104:1104)) + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1335:1335:1335) (1336:1336:1336)) + (PORT clrn (1886:1886:1886) (1859:1859:1859)) + (PORT sload (1624:1624:1624) (1684:1684:1684)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\~3) + (DELAY + (ABSOLUTE + (PORT dataa (819:819:819) (747:747:747)) + (PORT datab (1284:1284:1284) (1249:1249:1249)) + (PORT datac (1094:1094:1094) (1058:1058:1058)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst0\|data_out\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1887:1887:1887) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (423:423:423)) + (PORT datab (337:337:337) (414:414:414)) + (PORT datac (1078:1078:1078) (1104:1104:1104)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (452:452:452) (569:569:569)) + (PORT datac (911:911:911) (904:904:904)) + (PORT datad (893:893:893) (882:882:882)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1796:1796:1796) (1779:1779:1779)) + (PORT D (1266:1266:1266) (1278:1278:1278)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1796:1796:1796) (1779:1779:1779)) + (PORT d (972:972:972) (1032:1032:1032)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1969:1969:1969) (1974:1974:1974)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (944:944:944)) + (PORT datab (914:914:914) (862:862:862)) + (PORT datac (1186:1186:1186) (1097:1097:1097)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[9\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (313:313:313)) + (PORT datab (935:935:935) (877:877:877)) + (PORT datac (1511:1511:1511) (1403:1403:1403)) + (PORT datad (272:272:272) (293:293:293)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~35) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (328:328:328)) + (PORT datab (568:568:568) (574:574:574)) + (PORT datac (863:863:863) (822:822:822)) + (PORT datad (246:246:246) (268:268:268)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~36) + (DELAY + (ABSOLUTE + (PORT dataa (297:297:297) (342:342:342)) + (PORT datab (921:921:921) (872:872:872)) + (PORT datac (1184:1184:1184) (1094:1094:1094)) + (PORT datad (251:251:251) (282:282:282)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~21) + (DELAY + (ABSOLUTE + (PORT dataa (494:494:494) (489:489:489)) + (PORT datab (497:497:497) (491:491:491)) + (PORT datac (1540:1540:1540) (1407:1407:1407)) + (PORT datad (887:887:887) (833:833:833)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~26) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (853:853:853)) + (PORT datab (842:842:842) (807:807:807)) + (PORT datac (242:242:242) (273:273:273)) + (PORT datad (460:460:460) (440:440:440)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_x\[11\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1185:1185:1185) (1067:1067:1067)) + (PORT datad (858:858:858) (810:810:810)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~27) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (339:339:339)) + (PORT datab (294:294:294) (328:328:328)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (844:844:844) (792:792:792)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[10\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (766:766:766)) + (PORT datab (1440:1440:1440) (1301:1301:1301)) + (PORT datac (562:562:562) (583:583:583)) + (PORT datad (1670:1670:1670) (1467:1467:1467)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~29) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (901:901:901)) + (PORT datab (913:913:913) (862:862:862)) + (PORT datac (1190:1190:1190) (1102:1102:1102)) + (PORT datad (928:928:928) (882:882:882)) + (IOPATH dataa combout (453:453:453) (428:428:428)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~30) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1143:1143:1143)) + (PORT datab (920:920:920) (872:872:872)) + (PORT datac (1512:1512:1512) (1404:1404:1404)) + (PORT datad (876:876:876) (829:829:829)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~31) + (DELAY + (ABSOLUTE + (PORT datab (275:275:275) (300:300:300)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (265:265:265) (283:283:283)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[6\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (830:830:830) (768:768:768)) + (PORT datab (1423:1423:1423) (1274:1274:1274)) + (PORT datac (1397:1397:1397) (1261:1261:1261)) + (PORT datad (552:552:552) (571:571:571)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (605:605:605)) + (PORT datab (745:745:745) (690:690:690)) + (PORT datac (564:564:564) (584:584:584)) + (PORT datad (556:556:556) (575:575:575)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add14\~1) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (637:637:637)) + (PORT datab (397:397:397) (498:498:498)) + (PORT datac (354:354:354) (473:473:473)) + (PORT datad (582:582:582) (609:609:609)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n0\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~28) + (DELAY + (ABSOLUTE + (PORT dataa (885:885:885) (849:849:849)) + (PORT datab (840:840:840) (805:805:805)) + (PORT datac (247:247:247) (278:278:278)) + (PORT datad (458:458:458) (438:438:438)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (829:829:829) (767:767:767)) + (PORT datab (1423:1423:1423) (1274:1274:1274)) + (PORT datac (1397:1397:1397) (1262:1262:1262)) + (PORT datad (521:521:521) (547:547:547)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_in_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add13\~0) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (477:477:477)) + (PORT datab (395:395:395) (510:510:510)) + (PORT datac (338:338:338) (428:428:428)) + (PORT datad (546:546:546) (561:561:561)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add13\~1) + (DELAY + (ABSOLUTE + (PORT datab (397:397:397) (498:498:498)) + (PORT datac (355:355:355) (474:474:474)) + (PORT datad (581:581:581) (608:608:608)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1583:1583:1583) (1534:1534:1534)) + (PORT datab (949:949:949) (926:926:926)) + (PORT datac (807:807:807) (803:803:803)) + (PORT datad (852:852:852) (825:825:825)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1585:1585:1585) (1537:1537:1537)) + (PORT datab (948:948:948) (925:925:925)) + (PORT datac (808:808:808) (805:805:805)) + (PORT datad (851:851:851) (823:823:823)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add14\~2) + (DELAY + (ABSOLUTE + (PORT dataa (589:589:589) (634:634:634)) + (PORT datab (395:395:395) (509:509:509)) + (PORT datac (354:354:354) (458:458:458)) + (PORT datad (585:585:585) (613:613:613)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n0\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1838:1838:1838) (1850:1850:1850)) + (PORT asdata (2131:2131:2131) (2021:2021:2021)) + (PORT clrn (1882:1882:1882) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (881:881:881)) + (PORT datab (566:566:566) (593:593:593)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add15\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1536:1536:1536) (1494:1494:1494)) + (PORT datab (910:910:910) (899:899:899)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add14\~0) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (636:636:636)) + (PORT datab (397:397:397) (512:512:512)) + (PORT datac (355:355:355) (459:459:459)) + (PORT datad (583:583:583) (611:611:611)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_n0\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (1072:1072:1072)) + (PORT datab (1849:1849:1849) (1763:1763:1763)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~9) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (854:854:854)) + (PORT datab (276:276:276) (300:300:300)) + (PORT datac (449:449:449) (436:436:436)) + (PORT datad (1137:1137:1137) (1033:1033:1033)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~10) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (543:543:543) (502:502:502)) + (PORT datac (239:239:239) (266:266:266)) + (PORT datad (1140:1140:1140) (1036:1036:1036)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[8\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (337:337:337) (427:427:427)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~15) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (310:310:310)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (822:822:822) (765:765:765)) + (PORT datad (912:912:912) (881:881:881)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (745:745:745)) + (PORT datab (1547:1547:1547) (1392:1392:1392)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT sclr (1457:1457:1457) (1514:1514:1514)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (444:444:444)) + (PORT datab (848:848:848) (817:817:817)) + (PORT datac (318:318:318) (396:396:396)) + (PORT datad (321:321:321) (391:391:391)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datab (289:289:289) (319:319:319)) + (PORT datad (329:329:329) (406:406:406)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (278:278:278) (303:303:303)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (745:745:745)) + (PORT datab (472:472:472) (455:455:455)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (493:493:493)) + (PORT datab (751:751:751) (678:678:678)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT sclr (1457:1457:1457) (1514:1514:1514)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~3) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (855:855:855)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (235:235:235) (261:261:261)) + (PORT datad (1138:1138:1138) (1034:1034:1034)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~4) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (277:277:277) (301:301:301)) + (PORT datac (711:711:711) (641:641:641)) + (PORT datad (826:826:826) (772:772:772)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (803:803:803) (726:726:726)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT sclr (1457:1457:1457) (1514:1514:1514)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1533:1533:1533)) + (PORT datab (949:949:949) (926:926:926)) + (PORT datac (806:806:806) (803:803:803)) + (PORT datad (853:853:853) (826:826:826)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_2) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (889:889:889)) + (PORT datab (368:368:368) (448:448:448)) + (PORT datac (793:793:793) (709:709:709)) + (PORT datad (248:248:248) (275:275:275)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (869:869:869)) + (PORT datab (809:809:809) (762:762:762)) + (PORT datad (819:819:819) (803:803:803)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~11) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (314:314:314)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (1044:1044:1044) (943:943:943)) + (PORT datad (530:530:530) (505:505:505)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~12) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (798:798:798)) + (PORT datab (950:950:950) (927:927:927)) + (PORT datac (810:810:810) (807:807:807)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT sclr (1457:1457:1457) (1514:1514:1514)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add22\~6) + (DELAY + (ABSOLUTE + (PORT datad (591:591:591) (618:618:618)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|Add16\~2) + (DELAY + (ABSOLUTE + (PORT dataa (742:742:742) (679:679:679)) + (PORT datab (792:792:792) (710:710:710)) + (PORT datac (770:770:770) (709:709:709)) + (PORT datad (781:781:781) (721:721:721)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (803:803:803) (737:737:737)) + (PORT datad (452:452:452) (430:430:430)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1851:1851:1851)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (PORT sclr (1457:1457:1457) (1514:1514:1514)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|condition_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (896:896:896)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (590:590:590) (617:617:617)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|q_m_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT asdata (803:803:803) (884:884:884)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (477:477:477)) + (PORT datab (824:824:824) (751:751:751)) + (PORT datad (776:776:776) (716:716:716)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (780:780:780) (695:695:695)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1719:1719:1719) (1680:1680:1680)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (PORT sload (1425:1425:1425) (1434:1434:1434)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~3) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (777:777:777)) + (PORT datab (808:808:808) (760:760:760)) + (PORT datac (986:986:986) (855:855:855)) + (PORT datad (820:820:820) (803:803:803)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1722:1722:1722) (1684:1684:1684)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (PORT sload (1425:1425:1425) (1434:1434:1434)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (422:422:422)) + (PORT datab (336:336:336) (413:413:413)) + (PORT datac (1040:1040:1040) (1056:1056:1056)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (PORT datac (1038:1038:1038) (1054:1054:1054)) + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (430:430:430)) + (PORT datac (1040:1040:1040) (1056:1056:1056)) + (PORT datad (298:298:298) (368:368:368)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\~7) + (DELAY + (ABSOLUTE + (PORT dataa (987:987:987) (991:991:991)) + (PORT datac (1441:1441:1441) (1373:1373:1373)) + (PORT datad (1255:1255:1255) (1202:1202:1202)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst1\|data_out\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1861:1861:1861)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (412:412:412)) + (PORT datad (1042:1042:1042) (1073:1073:1073)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~3) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (439:439:439)) + (PORT datab (1086:1086:1086) (1121:1121:1121)) + (PORT datac (295:295:295) (373:373:373)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (424:424:424)) + (PORT datab (1086:1086:1086) (1121:1121:1121)) + (PORT datac (296:296:296) (374:374:374)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (438:438:438)) + (PORT datab (1087:1087:1087) (1122:1122:1122)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT dataa (996:996:996) (972:972:972)) + (PORT datab (1087:1087:1087) (1122:1122:1122)) + (PORT datac (296:296:296) (374:374:374)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1798:1798:1798) (1784:1784:1784)) + (PORT D (882:882:882) (936:936:936)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1798:1798:1798) (1784:1784:1784)) + (PORT d (1325:1325:1325) (1362:1362:1362)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1971:1971:1971) (1979:1979:1979)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~33) + (DELAY + (ABSOLUTE + (PORT dataa (870:870:870) (831:831:831)) + (PORT datab (293:293:293) (328:328:328)) + (PORT datad (246:246:246) (268:268:268)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[13\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1262:1262:1262) (1169:1169:1169)) + (PORT datab (1497:1497:1497) (1356:1356:1356)) + (PORT datac (305:305:305) (388:388:388)) + (PORT datad (812:812:812) (771:771:771)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_in_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~32) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (830:830:830)) + (PORT datab (283:283:283) (314:314:314)) + (PORT datac (857:857:857) (804:804:804)) + (PORT datad (843:843:843) (792:792:792)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1161:1161:1161) (1056:1056:1056)) + (PORT datab (873:873:873) (818:818:818)) + (PORT datac (305:305:305) (389:389:389)) + (PORT datad (532:532:532) (555:555:555)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_in_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[12\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1261:1261:1261) (1168:1168:1168)) + (PORT datab (1497:1497:1497) (1356:1356:1356)) + (PORT datac (323:323:323) (402:402:402)) + (PORT datad (812:812:812) (771:771:771)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_in_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add12\~0) + (DELAY + (ABSOLUTE + (PORT datab (993:993:993) (992:992:992)) + (PORT datac (1027:1027:1027) (1043:1043:1043)) + (PORT datad (960:960:960) (972:972:972)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n1\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add14\~0) + (DELAY + (ABSOLUTE + (PORT datab (993:993:993) (993:993:993)) + (PORT datac (1028:1028:1028) (1044:1044:1044)) + (PORT datad (960:960:960) (972:972:972)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add12\~1) + (DELAY + (ABSOLUTE + (PORT datac (1021:1021:1021) (1035:1035:1035)) + (PORT datad (957:957:957) (969:969:969)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n1\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (912:912:912)) + (PORT datab (907:907:907) (896:896:896)) + (PORT datac (894:894:894) (881:881:881)) + (PORT datad (824:824:824) (807:807:807)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[8\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1027:1027:1027) (1042:1042:1042)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (913:913:913)) + (PORT datab (913:913:913) (903:903:903)) + (PORT datac (902:902:902) (890:890:890)) + (PORT datad (821:821:821) (804:804:804)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add19\~0) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (902:902:902)) + (PORT datab (862:862:862) (850:850:850)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~5) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (823:823:823) (779:779:779)) + (PORT datad (770:770:770) (701:701:701)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~6) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (865:865:865)) + (PORT datab (868:868:868) (856:856:856)) + (PORT datac (492:492:492) (462:462:462)) + (PORT datad (835:835:835) (769:769:769)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (394:394:394) (480:480:480)) + (PORT datab (374:374:374) (463:463:463)) + (PORT datac (325:325:325) (410:410:410)) + (PORT datad (327:327:327) (404:404:404)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT datac (854:854:854) (825:825:825)) + (PORT datad (726:726:726) (656:656:656)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1087:1087:1087) (966:966:966)) + (PORT datab (1047:1047:1047) (920:920:920)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (277:277:277) (302:302:302)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT sclr (1798:1798:1798) (1895:1895:1895)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add15\~0) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (844:844:844)) + (PORT datab (376:376:376) (466:466:466)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~15) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (751:751:751)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (828:828:828) (818:818:818)) + (PORT datad (834:834:834) (767:767:767)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[1\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (478:478:478) (468:468:468)) + (PORT datab (541:541:541) (503:503:503)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[2\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (752:752:752) (691:691:691)) + (PORT datab (276:276:276) (301:301:301)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[3\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (475:475:475)) + (PORT datab (276:276:276) (301:301:301)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT sclr (1798:1798:1798) (1895:1895:1895)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[3\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (237:237:237) (255:255:255)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n0\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_2) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (717:717:717)) + (PORT datab (837:837:837) (744:744:744)) + (PORT datac (851:851:851) (822:822:822)) + (PORT datad (551:551:551) (581:581:581)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (366:366:366)) + (PORT datab (608:608:608) (644:644:644)) + (PORT datad (281:281:281) (305:305:305)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~14) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (818:818:818) (775:775:775)) + (PORT datac (821:821:821) (796:796:796)) + (PORT datad (443:443:443) (415:415:415)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT sclr (1798:1798:1798) (1895:1895:1895)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~2) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (850:850:850)) + (PORT datab (949:949:949) (920:920:920)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~2) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (848:848:848)) + (PORT datab (953:953:953) (926:926:926)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~7) + (DELAY + (ABSOLUTE + (PORT dataa (878:878:878) (810:810:810)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (801:801:801) (758:758:758)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~8) + (DELAY + (ABSOLUTE + (PORT dataa (848:848:848) (759:759:759)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (690:690:690) (636:636:636)) + (PORT datad (835:835:835) (768:768:768)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT sclr (1798:1798:1798) (1895:1895:1895)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_n1\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT asdata (1652:1652:1652) (1603:1603:1603)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add17\~8) + (DELAY + (ABSOLUTE + (PORT datad (861:861:861) (829:829:829)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add23\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~0) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (834:834:834)) + (PORT datab (485:485:485) (466:466:466)) + (PORT datac (746:746:746) (671:671:671)) + (PORT datad (777:777:777) (734:734:734)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add20\~6) + (DELAY + (ABSOLUTE + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|Add16\~1) + (DELAY + (ABSOLUTE + (PORT dataa (810:810:810) (728:728:728)) + (PORT datab (275:275:275) (299:299:299)) + (PORT datac (710:710:710) (638:638:638)) + (PORT datad (777:777:777) (734:734:734)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[4\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (488:488:488) (476:476:476)) + (PORT datad (450:450:450) (428:428:428)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT sclr (1798:1798:1798) (1895:1895:1895)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|condition_3\~2) + (DELAY + (ABSOLUTE + (PORT dataa (796:796:796) (720:720:720)) + (PORT datab (783:783:783) (705:705:705)) + (PORT datac (859:859:859) (818:818:818)) + (PORT datad (551:551:551) (580:580:580)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT asdata (1488:1488:1488) (1493:1493:1493)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~1) + (DELAY + (ABSOLUTE + (PORT dataa (817:817:817) (763:763:763)) + (PORT datab (877:877:877) (788:788:788)) + (PORT datad (339:339:339) (424:424:424)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (855:855:855) (792:792:792)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1909:1909:1909) (1833:1833:1833)) + (PORT clrn (1891:1891:1891) (1861:1861:1861)) + (PORT sload (1745:1745:1745) (1782:1782:1782)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m\[7\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (1019:1019:1019) (1033:1033:1033)) + (PORT datad (956:956:956) (968:968:968)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|q_m_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~4) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (479:479:479)) + (PORT datab (333:333:333) (409:409:409)) + (PORT datac (772:772:772) (715:715:715)) + (PORT datad (817:817:817) (739:739:739)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (765:765:765) (677:677:677)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1909:1909:1909) (1832:1832:1832)) + (PORT clrn (1891:1891:1891) (1861:1861:1861)) + (PORT sload (1745:1745:1745) (1782:1782:1782)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\~7) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (673:673:673)) + (PORT datab (372:372:372) (455:455:455)) + (PORT datac (1255:1255:1255) (1225:1225:1225)) + (PORT datad (859:859:859) (813:813:813)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1885:1885:1885) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~4) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (414:414:414)) + (PORT datac (1039:1039:1039) (1055:1055:1055)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1840:1840:1840) (1852:1852:1852)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~3) + (DELAY + (ABSOLUTE + (PORT datab (346:346:346) (430:430:430)) + (PORT datac (937:937:937) (927:927:927)) + (PORT datad (1043:1043:1043) (1074:1074:1074)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~2) + (DELAY + (ABSOLUTE + (PORT datab (346:346:346) (430:430:430)) + (PORT datac (295:295:295) (373:373:373)) + (PORT datad (1043:1043:1043) (1075:1075:1075)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (424:424:424)) + (PORT datab (1086:1086:1086) (1121:1121:1121)) + (PORT datac (298:298:298) (376:376:376)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (415:415:415)) + (PORT datac (940:940:940) (953:953:953)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_fall_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1999:1999:1999) (1897:1897:1897)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (PORT sload (1763:1763:1763) (1796:1796:1796)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[4\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (366:366:366)) + (PORT datab (613:613:613) (648:648:648)) + (PORT datad (281:281:281) (305:305:305)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|c0_reg2\~_wirecell) + (DELAY + (ABSOLUTE + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|encode_inst2\|data_out\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (PORT asdata (1672:1672:1672) (1549:1549:1549)) + (PORT clrn (1893:1893:1893) (1863:1863:1863)) + (PORT sload (1763:1763:1763) (1796:1796:1796)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sload (posedge clk) (212:212:212)) + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~3) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (423:423:423)) + (PORT datab (338:338:338) (415:415:415)) + (PORT datad (1006:1006:1006) (1025:1025:1025)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~2) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (425:425:425)) + (PORT datab (1044:1044:1044) (1065:1065:1065)) + (PORT datad (298:298:298) (368:368:368)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~1) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (428:428:428)) + (PORT datab (1046:1046:1046) (1068:1068:1068)) + (PORT datad (299:299:299) (369:369:369)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\~0) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (414:414:414)) + (PORT datac (979:979:979) (987:987:987)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|data_rise_s\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1859:1859:1859)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1800:1800:1800) (1786:1786:1786)) + (PORT D (884:884:884) (939:939:939)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1800:1800:1800) (1786:1786:1786)) + (PORT d (1354:1354:1354) (1392:1392:1392)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1973:1973:1973) (1981:1981:1981)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst0\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1796:1796:1796) (1779:1779:1779)) + (PORT D (1231:1231:1231) (1313:1313:1313)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1796:1796:1796) (1779:1779:1779)) + (PORT d (974:974:974) (1030:1030:1030)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1969:1969:1969) (1974:1974:1974)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst0\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1798:1798:1798) (1784:1784:1784)) + (PORT D (889:889:889) (929:929:929)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1798:1798:1798) (1784:1784:1784)) + (PORT d (1304:1304:1304) (1383:1383:1383)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1971:1971:1971) (1979:1979:1979)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst1\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) + (CELL + (CELLTYPE "cycloneive_latch") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_hi) + (DELAY + (ABSOLUTE + (PORT ENA (1800:1800:1800) (1786:1786:1786)) + (PORT D (892:892:892) (931:931:931)) + (IOPATH (negedge ENA) Q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP D (negedge ENA) (565:565:565)) + (HOLD D (negedge ENA) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].ddioreg_lo) + (DELAY + (ABSOLUTE + (PORT clk (1800:1800:1800) (1786:1786:1786)) + (PORT d (1334:1334:1334) (1412:1412:1412)) + (IOPATH (posedge clk) q (234:234:234) (234:234:234)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (109:109:109)) + (HOLD d (posedge clk) (126:126:126)) + ) + ) + (CELL + (CELLTYPE "cycloneive_mux21") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].sel_mux) + (DELAY + (ABSOLUTE + (PORT A (0:0:0) (0:0:0)) + (PORT B (0:0:0) (0:0:0)) + (PORT S (1973:1973:1973) (1981:1981:1981)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_routing_wire") + (INSTANCE hdmi_ctrl_inst\|par_to_ser_inst2\|ddio_out_inst1\|ALTDDIO_OUT_component\|auto_generated\|ddio_outa\[0\].wire_delay) + (DELAY + (ABSOLUTE + (IOPATH datain dataout (548:548:548) (549:549:549)) + ) + ) + (DELAY + (PATHPULSE datain dataout (548:548:548)) + ) + ) +) diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/hdmi/encode.v b/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/hdmi/encode.v new file mode 100644 index 0000000..5fd4449 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/hdmi/encode.v @@ -0,0 +1,190 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/11/01 +// Module Name : encode +// Project Name : hdmi_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : 8b转10b编码模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + + +module encode +( + input wire sys_clk , //时钟信号 + input wire sys_rst_n , //复位信号,低有效 + input wire [7:0] data_in , //输入8bit待编码数据 + input wire c0 , //控制信号c0 + input wire c1 , //控制信号c1 + input wire de , //使能信号 + + output reg [9:0] data_out //输出编码后的10bit数据 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter DATA_OUT0 = 10'b1101010100, + DATA_OUT1 = 10'b0010101011, + DATA_OUT2 = 10'b0101010100, + DATA_OUT3 = 10'b1010101011; + +//wire define +wire condition_1 ; //条件1 +wire condition_2 ; //条件2 +wire condition_3 ; //条件3 +wire [8:0] q_m ; //第一阶段转换后的9bit数据 + +//reg define +reg [3:0] data_in_n1 ; //待编码数据中1的个数 +reg [7:0] data_in_reg ; //待编码数据打一拍 +reg [3:0] q_m_n1 ; //转换后9bit数据中1的个数 +reg [3:0] q_m_n0 ; //转换后9bit数据中0的个数 +reg [4:0] cnt ; //视差计数器,0-1个数差别,最高位为符号位 +reg de_reg1 ; //使能信号打一拍 +reg de_reg2 ; //使能信号打两拍 +reg c0_reg1 ; //控制信号c0打一拍 +reg c0_reg2 ; //控制信号c0打两拍 +reg c1_reg1 ; //控制信号c1打一拍 +reg c1_reg2 ; //控制信号c1打两拍 +reg [8:0] q_m_reg ; //q_m信号打一拍 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//data_in_n1:待编码数据中1的个数 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + data_in_n1 <= 4'd0; + else + data_in_n1 <= data_in[0] + data_in[1] + data_in[2] + + data_in[3] + data_in[4] + data_in[5] + + data_in[6] + data_in[7]; + +//data_in_reg:待编码数据打一拍 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + data_in_reg <= 8'b0; + else + data_in_reg <= data_in; + +//condition_1:条件1 +assign condition_1 = ((data_in_n1 > 4'd4) || ((data_in_n1 == 4'd4) + && (data_in_reg[0] == 1'b0))); + +//q_m:第一阶段转换后的9bit数据 +assign q_m[0] = data_in_reg[0]; +assign q_m[1] = (condition_1) ? (q_m[0] ^~ data_in_reg[1]) : (q_m[0] ^ data_in_reg[1]); +assign q_m[2] = (condition_1) ? (q_m[1] ^~ data_in_reg[2]) : (q_m[1] ^ data_in_reg[2]); +assign q_m[3] = (condition_1) ? (q_m[2] ^~ data_in_reg[3]) : (q_m[2] ^ data_in_reg[3]); +assign q_m[4] = (condition_1) ? (q_m[3] ^~ data_in_reg[4]) : (q_m[3] ^ data_in_reg[4]); +assign q_m[5] = (condition_1) ? (q_m[4] ^~ data_in_reg[5]) : (q_m[4] ^ data_in_reg[5]); +assign q_m[6] = (condition_1) ? (q_m[5] ^~ data_in_reg[6]) : (q_m[5] ^ data_in_reg[6]); +assign q_m[7] = (condition_1) ? (q_m[6] ^~ data_in_reg[7]) : (q_m[6] ^ data_in_reg[7]); +assign q_m[8] = (condition_1) ? 1'b0 : 1'b1; + +//q_m_n1:转换后9bit数据中1的个数 +//q_m_n0:转换后9bit数据中0的个数 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + q_m_n1 <= 4'd0; + q_m_n0 <= 4'd0; + end + else + begin + q_m_n1 <= q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7]; + q_m_n0 <= 4'd8 - (q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7]); + end + +//condition_2:条件2 +assign condition_2 = ((cnt == 5'd0) || (q_m_n1 == q_m_n0)); + +//condition_3:条件3 +assign condition_3 = (((~cnt[4] == 1'b1) && (q_m_n1 > q_m_n0)) + || ((cnt[4] == 1'b1) && (q_m_n0 > q_m_n1))); + +//数据打拍,为了各数据同步 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + de_reg1 <= 1'b0; + de_reg2 <= 1'b0; + c0_reg1 <= 1'b0; + c0_reg2 <= 1'b0; + c1_reg1 <= 1'b0; + c1_reg2 <= 1'b0; + q_m_reg <= 9'b0; + end + else + begin + de_reg1 <= de; + de_reg2 <= de_reg1; + c0_reg1 <= c0; + c0_reg2 <= c0_reg1; + c1_reg1 <= c1; + c1_reg2 <= c1_reg1; + q_m_reg <= q_m; + end + +//data_out:输出编码后的10bit数据 +//cnt:视差计数器,0-1个数差别,最高位为符号位 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + data_out <= 10'b0; + cnt <= 5'b0; + end + else + begin + if(de_reg2 == 1'b1) + begin + if(condition_2 == 1'b1) + begin + data_out[9] <= ~q_m_reg[8]; + data_out[8] <= q_m_reg[8]; + data_out[7:0] <= (q_m_reg[8]) ? q_m_reg[7:0] : ~q_m_reg[7:0]; + cnt <= (~q_m_reg[8]) ? (cnt + q_m_n0 - q_m_n1) : (cnt + q_m_n1 - q_m_n0); + end + else + begin + if(condition_3 == 1'b1) + begin + data_out[9] <= 1'b1; + data_out[8] <= q_m_reg[8]; + data_out[7:0] <= ~q_m_reg[7:0]; + cnt <= cnt + {q_m_reg[8], 1'b0} + (q_m_n0 - q_m_n1); + end + else + begin + data_out[9] <= 1'b0; + data_out[8] <= q_m_reg[8]; + data_out[7:0] <= q_m_reg[7:0]; + cnt <= cnt - {~q_m_reg[8], 1'b0} + (q_m_n1 - q_m_n0); + end + + end + end + else + begin + case ({c1_reg2, c0_reg2}) + 2'b00: data_out <= DATA_OUT0; + 2'b01: data_out <= DATA_OUT1; + 2'b10: data_out <= DATA_OUT2; + default:data_out <= DATA_OUT3; + endcase + cnt <= 5'b0; + end + end + +endmodule \ No newline at end of file diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/hdmi/hdmi_ctrl.v b/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/hdmi/hdmi_ctrl.v new file mode 100644 index 0000000..d0b2a50 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/hdmi/hdmi_ctrl.v @@ -0,0 +1,129 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/11/01 +// Module Name : hdmi_ctrl +// Project Name : hdmi_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : HDMI控制模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + + +module hdmi_ctrl +( + input wire clk_1x , //输入系统时钟 + input wire clk_5x , //输入5倍系统时钟 + input wire sys_rst_n , //复位信号,低有效 + input wire [7:0] rgb_blue , //蓝色分量 + input wire [7:0] rgb_green , //绿色分量 + input wire [7:0] rgb_red , //红色分量 + input wire hsync , //行同步信号 + input wire vsync , //场同步信号 + input wire de , //使能信号 + + output wire hdmi_clk_p , + output wire hdmi_clk_n , //时钟差分信号 + output wire hdmi_r_p , + output wire hdmi_r_n , //红色分量差分信号 + output wire hdmi_g_p , + output wire hdmi_g_n , //绿色分量差分信号 + output wire hdmi_b_p , + output wire hdmi_b_n //蓝色分量差分信号 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +wire [9:0] red ; //8b转10b后的红色分量 +wire [9:0] green ; //8b转10b后的绿色分量 +wire [9:0] blue ; //8b转10b后的蓝色分量 + +//********************************************************************// +//**************************** Instantiate ***************************// +//********************************************************************// +//------------- encode_inst0 ------------- +encode encode_inst0 +( + .sys_clk (clk_1x ), + .sys_rst_n (sys_rst_n ), + .data_in (rgb_blue ), + .c0 (hsync ), + .c1 (vsync ), + .de (de ), + .data_out (blue ) +); + +//------------- encode_inst1 ------------- +encode encode_inst1 +( + .sys_clk (clk_1x ), + .sys_rst_n (sys_rst_n ), + .data_in (rgb_green ), + .c0 (hsync ), + .c1 (vsync ), + .de (de ), + .data_out (green ) +); + +//------------- encode_inst2 ------------- +encode encode_inst2 +( + .sys_clk (clk_1x ), + .sys_rst_n (sys_rst_n ), + .data_in (rgb_red ), + .c0 (hsync ), + .c1 (vsync ), + .de (de ), + .data_out (red ) +); + +//------------- par_to_ser_inst0 ------------- +par_to_ser par_to_ser_inst0 +( + .clk_5x (clk_5x ), + .par_data (blue ), + + .ser_data_p (hdmi_b_p ), + .ser_data_n (hdmi_b_n ) +); + +//------------- par_to_ser_inst1 ------------- +par_to_ser par_to_ser_inst1 +( + .clk_5x (clk_5x ), + .par_data (green ), + + .ser_data_p (hdmi_g_p ), + .ser_data_n (hdmi_g_n ) +); + +//------------- par_to_ser_inst2 ------------- +par_to_ser par_to_ser_inst2 +( + .clk_5x (clk_5x ), + .par_data (red ), + + .ser_data_p (hdmi_r_p ), + .ser_data_n (hdmi_r_n ) +); + +//------------- par_to_ser_inst3 ------------- +par_to_ser par_to_ser_inst3 +( + .clk_5x (clk_5x ), + .par_data (10'b1111100000), + + .ser_data_p (hdmi_clk_p ), + .ser_data_n (hdmi_clk_n ) +); + +endmodule diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/hdmi/par_to_ser.v b/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/hdmi/par_to_ser.v new file mode 100644 index 0000000..3d08083 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/hdmi/par_to_ser.v @@ -0,0 +1,73 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/11/01 +// Module Name : par_to_ser +// Project Name : hdmi_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : 并行转串行、单端转差分、单沿转双沿 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module par_to_ser +( + input wire clk_5x , //输入系统时钟 + input wire [9:0] par_data , //输入并行数据 + + output wire ser_data_p , //输出串行差分数据 + output wire ser_data_n //输出串行差分数据 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//wire define +wire [4:0] data_rise = {par_data[8],par_data[6], + par_data[4],par_data[2],par_data[0]}; +wire [4:0] data_fall = {par_data[9],par_data[7], + par_data[5],par_data[3],par_data[1]}; + +//reg define +reg [4:0] data_rise_s = 0; +reg [4:0] data_fall_s = 0; +reg [2:0] cnt = 0; + + +always @ (posedge clk_5x) + begin + cnt <= (cnt[2]) ? 3'd0 : cnt + 3'd1; + data_rise_s <= cnt[2] ? data_rise : data_rise_s[4:1]; + data_fall_s <= cnt[2] ? data_fall : data_fall_s[4:1]; + + end + +//********************************************************************// +//**************************** Instantiate ***************************// +//********************************************************************// +//------------- ddio_out_inst0 ------------- +ddio_out ddio_out_inst0 +( + .datain_h (data_rise_s[0] ), + .datain_l (data_fall_s[0] ), + .outclock (~clk_5x ), + .dataout (ser_data_p ) +); + +//------------- ddio_out_inst1 ------------- +ddio_out ddio_out_inst1 +( + .datain_h (~data_rise_s[0]), + .datain_l (~data_fall_s[0]), + .outclock (~clk_5x ), + .dataout (ser_data_n ) +); + +endmodule diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/hdmi_colorbar.v b/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/hdmi_colorbar.v new file mode 100644 index 0000000..861f8b1 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/hdmi_colorbar.v @@ -0,0 +1,118 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/11/01 +// Module Name : hdmi_colorbar +// Project Name : hdmi_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : hdmi_colorbar顶层模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module hdmi_colorbar +( + input wire sys_clk , //输入工作时钟,频率50MHz + input wire sys_rst_n , //输入复位信号,低电平有效 + + output wire ddc_scl , + output wire ddc_sda , + output wire tmds_clk_p , + output wire tmds_clk_n , //HDMI时钟差分信号 + output wire [2:0] tmds_data_p , + output wire [2:0] tmds_data_n //HDMI图像差分信号 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//wire define +wire vga_clk ; //VGA工作时钟,频率25MHz +wire clk_5x ; +wire locked ; //PLL locked信号 +wire rst_n ; //VGA模块复位信号 +wire [11:0] pix_x ; //VGA有效显示区域X轴坐标 +wire [11:0] pix_y ; //VGA有效显示区域Y轴坐标 +wire [15:0] pix_data; //VGA像素点色彩信息 +wire hsync ; //输出行同步信号 +wire vsync ; //输出场同步信号 +wire [15:0] rgb ; //输出像素信息 +wire rgb_valid; + +//rst_n:VGA模块复位信号 +assign rst_n = (sys_rst_n & locked); +assign ddc_scl = 1'b1; +assign ddc_sda = 1'b1; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- clk_gen_inst ------------- +clk_gen clk_gen_inst +( + .areset (~sys_rst_n ), //输入复位信号,高电平有效,1bit + .inclk0 (sys_clk ), //输入50MHz晶振时钟,1bit + + .c0 (vga_clk ), //输出VGA工作时钟,频率25Mhz,1bit + .c1 (clk_5x ), + .locked (locked ) //输出pll locked信号,1bit +); + +//------------- vga_ctrl_inst ------------- +vga_ctrl vga_ctrl_inst +( + .vga_clk (vga_clk ), //输入工作时钟,频率25MHz,1bit + .sys_rst_n (rst_n ), //输入复位信号,低电平有效,1bit + .pix_data (pix_data ), //输入像素点色彩信息,16bit + + .pix_x (pix_x ), //输出VGA有效显示区域像素点X轴坐标,10bit + .pix_y (pix_y ), //输出VGA有效显示区域像素点Y轴坐标,10bit + .hsync (hsync ), //输出行同步信号,1bit + .vsync (vsync ), //输出场同步信号,1bit + .rgb_valid (rgb_valid ), + .rgb (rgb ) //输出像素点色彩信息,16bit +); + +//------------- vga_pic_inst ------------- +vga_pic vga_pic_inst +( + .vga_clk (vga_clk ), //输入工作时钟,频率25MHz,1bit + .sys_rst_n (rst_n ), //输入复位信号,低电平有效,1bit + .pix_x (pix_x ), //输入VGA有效显示区域像素点X轴坐标,10bit + .pix_y (pix_y ), //输入VGA有效显示区域像素点Y轴坐标,10bit + + .pix_data (pix_data ) //输出像素点色彩信息,16bit + +); + +//------------- hdmi_ctrl_inst ------------- +hdmi_ctrl hdmi_ctrl_inst +( + .clk_1x (vga_clk ), //输入系统时钟 + .clk_5x (clk_5x ), //输入5倍系统时钟 + .sys_rst_n (rst_n ), //复位信号,低有效 + .rgb_blue ({rgb[4:0],3'b0} ), //蓝色分量 + .rgb_green ({rgb[10:5],2'b0} ), //绿色分量 + .rgb_red ({rgb[15:11],3'b0} ), //红色分量 + .hsync (hsync ), //行同步信号 + .vsync (vsync ), //场同步信号 + .de (rgb_valid ), //使能信号 + .hdmi_clk_p (tmds_clk_p ), + .hdmi_clk_n (tmds_clk_n ), //时钟差分信号 + .hdmi_r_p (tmds_data_p[2] ), + .hdmi_r_n (tmds_data_n[2] ), //红色分量差分信号 + .hdmi_g_p (tmds_data_p[1] ), + .hdmi_g_n (tmds_data_n[1] ), //绿色分量差分信号 + .hdmi_b_p (tmds_data_p[0] ), + .hdmi_b_n (tmds_data_n[0] ) //蓝色分量差分信号 +); + +endmodule diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/vga_ctrl.v b/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/vga_ctrl.v new file mode 100644 index 0000000..d6b6ed1 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/vga_ctrl.v @@ -0,0 +1,113 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/03/12 +// Module Name : vga_ctrl +// Project Name : hdmi_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : VGA控制模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module vga_ctrl +( + input wire vga_clk , //输入工作时钟,频率25MHz + input wire sys_rst_n , //输入复位信号,低电平有效 + input wire [15:0] pix_data , //输入像素点色彩信息 + + output wire [11:0] pix_x , //输出VGA有效显示区域像素点X轴坐标 + output wire [11:0] pix_y , //输出VGA有效显示区域像素点Y轴坐标 + output wire hsync , //输出行同步信号 + output wire vsync , //输出场同步信号 + output wire rgb_valid , + output wire [15:0] rgb //输出像素点色彩信息 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter H_SYNC = 10'd96 , //行同步 + H_BACK = 10'd40 , //行时序后沿 + H_LEFT = 10'd8 , //行时序左边框 + H_VALID = 10'd640 , //行有效数据 + H_RIGHT = 10'd8 , //行时序右边框 + H_FRONT = 10'd8 , //行时序前沿 + H_TOTAL = 10'd800 ; //行扫描周期 +parameter V_SYNC = 10'd2 , //场同步 + V_BACK = 10'd25 , //场时序后沿 + V_TOP = 10'd8 , //场时序上边框 + V_VALID = 10'd480 , //场有效数据 + V_BOTTOM = 10'd8 , //场时序下边框 + V_FRONT = 10'd2 , //场时序前沿 + V_TOTAL = 10'd525 ; //场扫描周期 + +//wire define +wire pix_data_req ; //像素点色彩信息请求信号 + +//reg define +reg [11:0] cnt_h ; //行同步信号计数器 +reg [11:0] cnt_v ; //场同步信号计数器 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +//cnt_h:行同步信号计数器 +always@(posedge vga_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_h <= 12'd0 ; + else if(cnt_h == H_TOTAL - 1'd1) + cnt_h <= 12'd0 ; + else + cnt_h <= cnt_h + 1'd1 ; + +//hsync:行同步信号 +assign hsync = (cnt_h <= H_SYNC - 1'd1) ? 1'b1 : 1'b0 ; + +//cnt_v:场同步信号计数器 +always@(posedge vga_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_v <= 12'd0 ; + else if((cnt_v == V_TOTAL - 1'd1) && (cnt_h == H_TOTAL-1'd1)) + cnt_v <= 12'd0 ; + else if(cnt_h == H_TOTAL - 1'd1) + cnt_v <= cnt_v + 1'd1 ; + else + cnt_v <= cnt_v ; + +//vsync:场同步信号 +assign vsync = (cnt_v <= V_SYNC - 1'd1) ? 1'b1 : 1'b0 ; + +//rgb_valid:VGA有效显示区域 +assign rgb_valid = (((cnt_h >= H_SYNC + H_BACK + H_LEFT) + && (cnt_h < H_SYNC + H_BACK + H_LEFT + H_VALID)) + &&((cnt_v >= V_SYNC + V_BACK + V_TOP) + && (cnt_v < V_SYNC + V_BACK + V_TOP + V_VALID))) + ? 1'b1 : 1'b0; + +//pix_data_req:像素点色彩信息请求信号,超前rgb_valid信号一个时钟周期 +assign pix_data_req = (((cnt_h >= H_SYNC + H_BACK + H_LEFT - 1'b1) + && (cnt_h < H_SYNC + H_BACK + H_LEFT + H_VALID - 1'b1)) + &&((cnt_v >= V_SYNC + V_BACK + V_TOP) + && (cnt_v < V_SYNC + V_BACK + V_TOP + V_VALID))) + ? 1'b1 : 1'b0; + +//pix_x,pix_y:VGA有效显示区域像素点坐标 +assign pix_x = (pix_data_req == 1'b1) + ? (cnt_h - (H_SYNC + H_BACK + H_LEFT - 1'b1)) : 12'hfff; +assign pix_y = (pix_data_req == 1'b1) + ? (cnt_v - (V_SYNC + V_BACK + V_TOP)) : 12'hfff; + +//rgb:输出像素点色彩信息 +assign rgb = (rgb_valid == 1'b1) ? pix_data : 16'b0 ; + +endmodule diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/vga_pic.v b/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/vga_pic.v new file mode 100644 index 0000000..05965da --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/rtl/vga_pic.v @@ -0,0 +1,78 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/03/12 +// Module Name : vga_pic +// Project Name : hdmi_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : 图像数据生成模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module vga_pic +( + input wire vga_clk , //输入工作时钟,频率25MHz + input wire sys_rst_n , //输入复位信号,低电平有效 + input wire [11:0] pix_x , //输入VGA有效显示区域像素点X轴坐标 + input wire [11:0] pix_y , //输入VGA有效显示区域像素点Y轴坐标 + + output reg [15:0] pix_data //输出像素点色彩信息 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter H_VALID = 12'd640 , //行有效数据 + V_VALID = 12'd480 ; //场有效数据 + +parameter RED = 16'hF800, //红色 + ORANGE = 16'hFC00, //橙色 + YELLOW = 16'hFFE0, //黄色 + GREEN = 16'h07E0, //绿色 + CYAN = 16'h07FF, //青色 + BLUE = 16'h001F, //蓝色 + PURPPLE = 16'hF81F, //紫色 + BLACK = 16'h0000, //黑色 + WHITE = 16'hFFFF, //白色 + GRAY = 16'hD69A; //灰色 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//pix_data:输出像素点色彩信息,根据当前像素点坐标指定当前像素点颜色数据 +always@(posedge vga_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + pix_data <= 16'd0; + else if((pix_x >= 0) && (pix_x < (H_VALID/10)*1)) + pix_data <= RED; + else if((pix_x >= (H_VALID/10)*1) && (pix_x < (H_VALID/10)*2)) + pix_data <= ORANGE; + else if((pix_x >= (H_VALID/10)*2) && (pix_x < (H_VALID/10)*3)) + pix_data <= YELLOW; + else if((pix_x >= (H_VALID/10)*3) && (pix_x < (H_VALID/10)*4)) + pix_data <= GREEN; + else if((pix_x >= (H_VALID/10)*4) && (pix_x < (H_VALID/10)*5)) + pix_data <= CYAN; + else if((pix_x >= (H_VALID/10)*5) && (pix_x < (H_VALID/10)*6)) + pix_data <= BLUE; + else if((pix_x >= (H_VALID/10)*6) && (pix_x < (H_VALID/10)*7)) + pix_data <= PURPPLE; + else if((pix_x >= (H_VALID/10)*7) && (pix_x < (H_VALID/10)*8)) + pix_data <= BLACK; + else if((pix_x >= (H_VALID/10)*8) && (pix_x < (H_VALID/10)*9)) + pix_data <= WHITE; + else if((pix_x >= (H_VALID/10)*9) && (pix_x < H_VALID)) + pix_data <= GRAY; + else + pix_data <= BLACK; + +endmodule diff --git a/smh-ac415-fpga/examples/07_hdmi/hdmi/sim/tb_hdmi_colorbar.v b/smh-ac415-fpga/examples/07_hdmi/hdmi/sim/tb_hdmi_colorbar.v new file mode 100644 index 0000000..77885f8 --- /dev/null +++ b/smh-ac415-fpga/examples/07_hdmi/hdmi/sim/tb_hdmi_colorbar.v @@ -0,0 +1,72 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/11/01 +// Module Name : tb_hdmi_colorbar +// Project Name : hdmi_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : hdmi_colorbar仿真文件 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + + +module tb_hdmi_colorbar(); +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//wire define +wire ddc_scl ; +wire ddc_sda ; +wire tmds_clk_p ; +wire tmds_clk_n ; +wire [2:0] tmds_data_p ; +wire [2:0] tmds_data_n ; + +//reg define +reg sys_clk ; +reg sys_rst_n ; + +//********************************************************************// +//**************************** Clk And Rst ***************************// +//********************************************************************// + +//sys_clk,sys_rst_n初始赋值 +initial + begin + sys_clk = 1'b1; + sys_rst_n <= 1'b0; + #200 + sys_rst_n <= 1'b1; + end + +//sys_clk：产生时钟 +always #10 sys_clk = ~sys_clk ; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- hdmi_colorbar_inst ------------- +hdmi_colorbar hdmi_colorbar_inst +( + .sys_clk (sys_clk ), //输入工作时钟,频率50MHz + .sys_rst_n (sys_rst_n ), //输入复位信号,低电平有效 + + .ddc_scl (ddc_scl ), + .ddc_sda (ddc_sda ), + .tmds_clk_p (tmds_clk_p ), + .tmds_clk_n (tmds_clk_n ), //HDMI时钟差分信号 + .tmds_data_p (tmds_data_p), + .tmds_data_n (tmds_data_n) //HDMI图像差分信号 +); + +endmodule + diff --git "a/smh-ac415-fpga/examples/07_hdmi/\345\256\236\351\252\214\347\216\260\350\261\241.txt" "b/smh-ac415-fpga/examples/07_hdmi/\345\256\236\351\252\214\347\216\260\350\261\241.txt" new file mode 100644 index 0000000..6b1e0c5 --- /dev/null +++ "b/smh-ac415-fpga/examples/07_hdmi/\345\256\236\351\252\214\347\216\260\350\261\241.txt" @@ -0,0 +1,5 @@ +现象：用hdmi线连接显示器，可以显示色条colorbar。此例程参考野火fpga例程修改而来。具体可参考野火教程。 + +测试：可以测试hdmi接口是否正常。 + + diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/doc/IS42S116160.pdf b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/doc/IS42S116160.pdf new file mode 100644 index 0000000..4cf210a Binary files /dev/null and b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/doc/IS42S116160.pdf differ diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/doc/ML0006 0012-2.pdf b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/doc/ML0006 0012-2.pdf new file mode 100644 index 0000000..2a88800 Binary files /dev/null and b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/doc/ML0006 0012-2.pdf differ diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/doc/W9825G6DH-6-datasheet.pdf b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/doc/W9825G6DH-6-datasheet.pdf new file mode 100644 index 0000000..dcc2dbd Binary files /dev/null and b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/doc/W9825G6DH-6-datasheet.pdf differ diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/doc/uart_sdram.vsdx b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/doc/uart_sdram.vsdx new file mode 100644 index 0000000..42f175a Binary files /dev/null and b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/doc/uart_sdram.vsdx differ diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/matlab/tast_data.m b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/matlab/tast_data.m new file mode 100644 index 0000000..ee3a0d3 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/matlab/tast_data.m @@ -0,0 +1,7 @@ +fid=fopen('test_data.txt','w+'); +%for i =1:16 + for j = 1:100 + fprintf(fid,'%02x ',j); + end +%end +fclose(fid); diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/matlab/test_data.txt b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/matlab/test_data.txt new file mode 100644 index 0000000..f81cb6e --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/matlab/test_data.txt @@ -0,0 +1 @@ +01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 \ No newline at end of file diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/PLLJ_PLLSPE_INFO.txt b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/PLLJ_PLLSPE_INFO.txt new file mode 100644 index 0000000..790cae7 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/PLLJ_PLLSPE_INFO.txt @@ -0,0 +1,5 @@ +PLL_Name clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|pll1 +PLLJITTER 30 +PLLSPEmax 84 +PLLSPEmin -53 + diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen.ppf b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen.ppf new file mode 100644 index 0000000..4ef1af0 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen.ppf @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen.qip b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen.qip new file mode 100644 index 0000000..433e305 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clk_gen.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen.ppf"] diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen.v new file mode 100644 index 0000000..7f4e3ca --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen.v @@ -0,0 +1,376 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module clk_gen ( + areset, + inclk0, + c0, + c1, + c2, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output c2; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; + wire [0:0] sub_wire3 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire6), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 1, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 1, + altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 1, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 2, + altpll_component.clk1_phase_shift = "0", + altpll_component.clk2_divide_by = 1, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 2, + altpll_component.clk2_phase_shift = "-833", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Cyclone IV E", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clk_gen", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_USED", + altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "100.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-30.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-833" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen_bb.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen_bb.v new file mode 100644 index 0000000..9101d97 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen_bb.v @@ -0,0 +1,254 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module clk_gen ( + areset, + inclk0, + c0, + c1, + c2, + locked); + + input areset; + input inclk0; + output c0; + output c1; + output c2; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "100.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-30.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-833" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen_inst.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen_inst.v new file mode 100644 index 0000000..ee1b2f9 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen_inst.v @@ -0,0 +1,8 @@ +clk_gen clk_gen_inst ( + .areset ( areset_sig ), + .inclk0 ( inclk0_sig ), + .c0 ( c0_sig ), + .c1 ( c1_sig ), + .c2 ( c2_sig ), + .locked ( locked_sig ) + ); diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..687e8e2 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/greybox_tmp/cbx_args.txt @@ -0,0 +1,63 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=50 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=9 +CLK0_PHASE_SHIFT=0 +CLK1_DIVIDE_BY=1 +CLK1_DUTY_CYCLE=50 +CLK1_MULTIPLY_BY=2 +CLK1_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=20000 +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_UNUSED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_UNUSED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_USED +PORT_clk2=PORT_UNUSED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +WIDTH_CLOCK=5 +DEVICE_FAMILY="Cyclone IV E" +CBX_AUTO_BLACKBOX=ALL +inclk +inclk +clk +clk diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/fifo_data.qip b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/fifo_data.qip new file mode 100644 index 0000000..fffcf83 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/fifo_data.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "FIFO" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fifo_data.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_data_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_data_bb.v"] diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/fifo_data.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/fifo_data.v new file mode 100644 index 0000000..7031dc3 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/fifo_data.v @@ -0,0 +1,179 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_data.v +// Megafunction Name(s): +// dcfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_data ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdusedw, + wrusedw); + + input aclr; + input [15:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [15:0] q; + output [9:0] rdusedw; + output [9:0] wrusedw; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 aclr; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [15:0] sub_wire0; + wire [9:0] sub_wire1; + wire [9:0] sub_wire2; + wire [15:0] q = sub_wire0[15:0]; + wire [9:0] wrusedw = sub_wire1[9:0]; + wire [9:0] rdusedw = sub_wire2[9:0]; + + dcfifo dcfifo_component ( + .rdclk (rdclk), + .wrclk (wrclk), + .wrreq (wrreq), + .aclr (aclr), + .data (data), + .rdreq (rdreq), + .q (sub_wire0), + .wrusedw (sub_wire1), + .rdusedw (sub_wire2), + .rdempty (), + .rdfull (), + .wrempty (), + .wrfull ()); + defparam + dcfifo_component.intended_device_family = "Cyclone IV E", + dcfifo_component.lpm_numwords = 1024, + dcfifo_component.lpm_showahead = "OFF", + dcfifo_component.lpm_type = "dcfifo", + dcfifo_component.lpm_width = 16, + dcfifo_component.lpm_widthu = 10, + dcfifo_component.overflow_checking = "ON", + dcfifo_component.rdsync_delaypipe = 3, + dcfifo_component.read_aclr_synch = "OFF", + dcfifo_component.underflow_checking = "ON", + dcfifo_component.use_eab = "ON", + dcfifo_component.write_aclr_synch = "OFF", + dcfifo_component.wrsync_delaypipe = 3; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "1024" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "16" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "0" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "3" +// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" +// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "3" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL "rdusedw[9..0]" +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0 +// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/fifo_data_bb.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/fifo_data_bb.v new file mode 100644 index 0000000..771b984 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/fifo_data_bb.v @@ -0,0 +1,137 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: dcfifo + +// ============================================================ +// File Name: fifo_data.v +// Megafunction Name(s): +// dcfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_data ( + aclr, + data, + rdclk, + rdreq, + wrclk, + wrreq, + q, + rdusedw, + wrusedw); + + input aclr; + input [15:0] data; + input rdclk; + input rdreq; + input wrclk; + input wrreq; + output [15:0] q; + output [9:0] rdusedw; + output [9:0] wrusedw; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 aclr; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" +// Retrieval info: PRIVATE: Clock NUMERIC "4" +// Retrieval info: PRIVATE: Depth NUMERIC "1024" +// Retrieval info: PRIVATE: Empty NUMERIC "1" +// Retrieval info: PRIVATE: Full NUMERIC "1" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "2" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "16" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "16" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "0" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "3" +// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" +// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "3" +// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" +// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" +// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" +// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL "rdusedw[9..0]" +// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]" +// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +// Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0 +// Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_data_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/fifo_data_inst.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/fifo_data_inst.v new file mode 100644 index 0000000..20d52aa --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/fifo_data_inst.v @@ -0,0 +1,11 @@ +fifo_data fifo_data_inst ( + .aclr ( aclr_sig ), + .data ( data_sig ), + .rdclk ( rdclk_sig ), + .rdreq ( rdreq_sig ), + .wrclk ( wrclk_sig ), + .wrreq ( wrreq_sig ), + .q ( q_sig ), + .rdusedw ( rdusedw_sig ), + .wrusedw ( wrusedw_sig ) + ); diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..a65cfa1 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/greybox_tmp/cbx_args.txt @@ -0,0 +1,23 @@ +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_NUMWORDS=1024 +LPM_SHOWAHEAD=OFF +LPM_TYPE=dcfifo +LPM_WIDTH=16 +LPM_WIDTHU=10 +OVERFLOW_CHECKING=ON +RDSYNC_DELAYPIPE=3 +READ_ACLR_SYNCH=OFF +UNDERFLOW_CHECKING=ON +USE_EAB=ON +WRITE_ACLR_SYNCH=OFF +WRSYNC_DELAYPIPE=3 +DEVICE_FAMILY="Cyclone IV E" +aclr +data +rdclk +rdreq +wrclk +wrreq +q +rdusedw +wrusedw diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_read/fifo_read.qip b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_read/fifo_read.qip new file mode 100644 index 0000000..aaada86 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_read/fifo_read.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "FIFO" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fifo_read.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_read_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_read_bb.v"] diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_read/fifo_read.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_read/fifo_read.v new file mode 100644 index 0000000..af4ca89 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_read/fifo_read.v @@ -0,0 +1,151 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: fifo_read.v +// Megafunction Name(s): +// scfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module fifo_read ( + clock, + data, + rdreq, + wrreq, + q, + usedw); + + input clock; + input [7:0] data; + input rdreq; + input wrreq; + output [7:0] q; + output [9:0] usedw; + + wire [9:0] sub_wire0; + wire [7:0] sub_wire1; + wire [9:0] usedw = sub_wire0[9:0]; + wire [7:0] q = sub_wire1[7:0]; + + scfifo scfifo_component ( + .clock (clock), + .data (data), + .rdreq (rdreq), + .wrreq (wrreq), + .usedw (sub_wire0), + .q (sub_wire1), + .aclr (), + .almost_empty (), + .almost_full (), + .empty (), + .full (), + .sclr ()); + defparam + scfifo_component.add_ram_output_register = "OFF", + scfifo_component.intended_device_family = "Cyclone IV E", + scfifo_component.lpm_numwords = 1024, + scfifo_component.lpm_showahead = "OFF", + scfifo_component.lpm_type = "scfifo", + scfifo_component.lpm_width = 8, + scfifo_component.lpm_widthu = 10, + scfifo_component.overflow_checking = "ON", + scfifo_component.underflow_checking = "ON", + scfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "1024" +// Retrieval info: PRIVATE: Empty NUMERIC "0" +// Retrieval info: PRIVATE: Full NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "8" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "8" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL "usedw[9..0]" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_read.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_read.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_read.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_read.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_read_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_read_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_read/fifo_read_bb.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_read/fifo_read_bb.v new file mode 100644 index 0000000..878b924 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_read/fifo_read_bb.v @@ -0,0 +1,115 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: fifo_read.v +// Megafunction Name(s): +// scfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module fifo_read ( + clock, + data, + rdreq, + wrreq, + q, + usedw); + + input clock; + input [7:0] data; + input rdreq; + input wrreq; + output [7:0] q; + output [9:0] usedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "1024" +// Retrieval info: PRIVATE: Empty NUMERIC "0" +// Retrieval info: PRIVATE: Full NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "8" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "8" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL "usedw[9..0]" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_read.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_read.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_read.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_read.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_read_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_read_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_read/fifo_read_inst.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_read/fifo_read_inst.v new file mode 100644 index 0000000..108f8fa --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_read/fifo_read_inst.v @@ -0,0 +1,8 @@ +fifo_read fifo_read_inst ( + .clock ( clock_sig ), + .data ( data_sig ), + .rdreq ( rdreq_sig ), + .wrreq ( wrreq_sig ), + .q ( q_sig ), + .usedw ( usedw_sig ) + ); diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_read/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_read/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..6491690 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/fifo_read/greybox_tmp/cbx_args.txt @@ -0,0 +1,17 @@ +ADD_RAM_OUTPUT_REGISTER=OFF +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_NUMWORDS=1024 +LPM_SHOWAHEAD=OFF +LPM_TYPE=scfifo +LPM_WIDTH=8 +LPM_WIDTHU=10 +OVERFLOW_CHECKING=ON +UNDERFLOW_CHECKING=ON +USE_EAB=ON +DEVICE_FAMILY="Cyclone IV E" +clock +data +rdreq +wrreq +q +usedw diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..6491690 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/greybox_tmp/cbx_args.txt @@ -0,0 +1,17 @@ +ADD_RAM_OUTPUT_REGISTER=OFF +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_NUMWORDS=1024 +LPM_SHOWAHEAD=OFF +LPM_TYPE=scfifo +LPM_WIDTH=8 +LPM_WIDTHU=10 +OVERFLOW_CHECKING=ON +UNDERFLOW_CHECKING=ON +USE_EAB=ON +DEVICE_FAMILY="Cyclone IV E" +clock +data +rdreq +wrreq +q +usedw diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/read_fifo.qip b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/read_fifo.qip new file mode 100644 index 0000000..5c08e23 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/read_fifo.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "FIFO" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "read_fifo.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "read_fifo_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "read_fifo_bb.v"] diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/read_fifo.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/read_fifo.v new file mode 100644 index 0000000..c0f7b23 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/read_fifo.v @@ -0,0 +1,151 @@ +// megafunction wizard: %FIFO% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: read_fifo.v +// Megafunction Name(s): +// scfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module read_fifo ( + clock, + data, + rdreq, + wrreq, + q, + usedw); + + input clock; + input [7:0] data; + input rdreq; + input wrreq; + output [7:0] q; + output [9:0] usedw; + + wire [9:0] sub_wire0; + wire [7:0] sub_wire1; + wire [9:0] usedw = sub_wire0[9:0]; + wire [7:0] q = sub_wire1[7:0]; + + scfifo scfifo_component ( + .clock (clock), + .data (data), + .rdreq (rdreq), + .wrreq (wrreq), + .usedw (sub_wire0), + .q (sub_wire1), + .aclr (), + .almost_empty (), + .almost_full (), + .empty (), + .full (), + .sclr ()); + defparam + scfifo_component.add_ram_output_register = "OFF", + scfifo_component.intended_device_family = "Cyclone IV E", + scfifo_component.lpm_numwords = 1024, + scfifo_component.lpm_showahead = "OFF", + scfifo_component.lpm_type = "scfifo", + scfifo_component.lpm_width = 8, + scfifo_component.lpm_widthu = 10, + scfifo_component.overflow_checking = "ON", + scfifo_component.underflow_checking = "ON", + scfifo_component.use_eab = "ON"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "1024" +// Retrieval info: PRIVATE: Empty NUMERIC "0" +// Retrieval info: PRIVATE: Full NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "8" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "8" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL "usedw[9..0]" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL read_fifo.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL read_fifo.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL read_fifo.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL read_fifo.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL read_fifo_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL read_fifo_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/read_fifo_bb.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/read_fifo_bb.v new file mode 100644 index 0000000..ebea1f2 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/read_fifo_bb.v @@ -0,0 +1,115 @@ +// megafunction wizard: %FIFO%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: scfifo + +// ============================================================ +// File Name: read_fifo.v +// Megafunction Name(s): +// scfifo +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module read_fifo ( + clock, + data, + rdreq, + wrreq, + q, + usedw); + + input clock; + input [7:0] data; + input rdreq; + input wrreq; + output [7:0] q; + output [9:0] usedw; + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +// Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" +// Retrieval info: PRIVATE: Clock NUMERIC "0" +// Retrieval info: PRIVATE: Depth NUMERIC "1024" +// Retrieval info: PRIVATE: Empty NUMERIC "0" +// Retrieval info: PRIVATE: Full NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: Optimize NUMERIC "0" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +// Retrieval info: PRIVATE: UsedW NUMERIC "1" +// Retrieval info: PRIVATE: Width NUMERIC "8" +// Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: diff_widths NUMERIC "0" +// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +// Retrieval info: PRIVATE: output_width NUMERIC "8" +// Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +// Retrieval info: PRIVATE: rsFull NUMERIC "0" +// Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +// Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +// Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +// Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +// Retrieval info: PRIVATE: wsFull NUMERIC "1" +// Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +// Retrieval info: CONSTANT: USE_EAB STRING "ON" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL "usedw[9..0]" +// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL read_fifo.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL read_fifo.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL read_fifo.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL read_fifo.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL read_fifo_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL read_fifo_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/read_fifo_inst.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/read_fifo_inst.v new file mode 100644 index 0000000..58e24fa --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/read_fifo_inst.v @@ -0,0 +1,8 @@ +read_fifo read_fifo_inst ( + .clock ( clock_sig ), + .data ( data_sig ), + .rdreq ( rdreq_sig ), + .wrreq ( wrreq_sig ), + .q ( q_sig ), + .usedw ( usedw_sig ) + ); diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram.sft b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram.sft new file mode 100644 index 0000000..5b18e2c --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram.sft @@ -0,0 +1,6 @@ +set tool_name "ModelSim (Verilog)" +set corner_file_list { + {{"Slow -8 1.2V 85 Model"} {uart_sdram_8_1200mv_85c_slow.vo uart_sdram_8_1200mv_85c_v_slow.sdo}} + {{"Slow -8 1.2V 0 Model"} {uart_sdram_8_1200mv_0c_slow.vo uart_sdram_8_1200mv_0c_v_slow.sdo}} + {{"Fast -M 1.2V 0 Model"} {uart_sdram_min_1200mv_0c_fast.vo uart_sdram_min_1200mv_0c_v_fast.sdo}} +} diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram.vo b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram.vo new file mode 100644 index 0000000..43c9473 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram.vo @@ -0,0 +1,24917 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:26:31" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module uart_sdram ( + sys_clk, + sys_rst_n, + rx, + tx, + sdram_clk, + sdram_cke, + sdram_cs_n, + sdram_cas_n, + sdram_ras_n, + sdram_we_n, + sdram_ba, + sdram_addr, + sdram_dqm, + sdram_dq); +input sys_clk; +input sys_rst_n; +input rx; +output tx; +output sdram_clk; +output sdram_cke; +output sdram_cs_n; +output sdram_cas_n; +output sdram_ras_n; +output sdram_we_n; +output [1:0] sdram_ba; +output [12:0] sdram_addr; +output [1:0] sdram_dqm; +inout [15:0] sdram_dq; + +// Design Ports Information +// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_clk => Location: PIN_E5, I/O Standard: 2.5 V, Current Strength: Default +// sdram_cke => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_cs_n => Location: PIN_A4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_cas_n => Location: PIN_B5, I/O Standard: 2.5 V, Current Strength: Default +// sdram_ras_n => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_we_n => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default +// sdram_ba[0] => Location: PIN_B4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_ba[1] => Location: PIN_C4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[0] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[1] => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[2] => Location: PIN_B2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[3] => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[4] => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[5] => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[6] => Location: PIN_F1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[7] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[8] => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[9] => Location: PIN_N2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[10] => Location: PIN_A3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[11] => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[12] => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dqm[0] => Location: PIN_C6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dqm[1] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[0] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[1] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[2] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[3] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[4] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[5] => Location: PIN_C7, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[6] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[7] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[8] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[9] => Location: PIN_C3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[10] => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[11] => Location: PIN_E3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[12] => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[13] => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[14] => Location: PIN_J3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[15] => Location: PIN_J4, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("uart_sdram_v.sdo"); +// synopsys translate_on + +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout ; +wire \uart_tx_inst|baud_cnt[3]~19_combout ; +wire \uart_tx_inst|baud_cnt[4]~21_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout ; +wire \fifo_read_inst|Add2~4_combout ; +wire \Add1~1 ; +wire \Add1~0_combout ; +wire \Add1~3 ; +wire \Add1~2_combout ; +wire \Add1~5 ; +wire \Add1~4_combout ; +wire \Add1~7 ; +wire \Add1~6_combout ; +wire \Add1~9 ; +wire \Add1~8_combout ; +wire \Add1~11 ; +wire \Add1~10_combout ; +wire \Add1~13 ; +wire \Add1~12_combout ; +wire \Add1~15 ; +wire \Add1~14_combout ; +wire \Add1~17 ; +wire \Add1~16_combout ; +wire \Add1~19 ; +wire \Add1~18_combout ; +wire \Add1~21 ; +wire \Add1~20_combout ; +wire \Add1~23 ; +wire \Add1~22_combout ; +wire \Add1~25 ; +wire \Add1~24_combout ; +wire \Add1~27 ; +wire \Add1~26_combout ; +wire \Add1~29 ; +wire \Add1~28_combout ; +wire \Add1~30_combout ; +wire \fifo_read_inst|baud_cnt[1]~15_combout ; +wire \fifo_read_inst|baud_cnt[4]~21_combout ; +wire \fifo_read_inst|baud_cnt[9]~31_combout ; +wire \fifo_read_inst|baud_cnt[11]~35_combout ; +wire \data_num[0]~25 ; +wire \data_num[0]~24_combout ; +wire \data_num[1]~27 ; +wire \data_num[1]~26_combout ; +wire \data_num[2]~29 ; +wire \data_num[2]~28_combout ; +wire \data_num[3]~31 ; +wire \data_num[3]~30_combout ; +wire \data_num[4]~33 ; +wire \data_num[4]~32_combout ; +wire \data_num[5]~35 ; +wire \data_num[5]~34_combout ; +wire \data_num[6]~37 ; +wire \data_num[6]~36_combout ; +wire \data_num[7]~39 ; +wire \data_num[7]~38_combout ; +wire \data_num[8]~41 ; +wire \data_num[8]~40_combout ; +wire \data_num[9]~43 ; +wire \data_num[9]~42_combout ; +wire \data_num[10]~45 ; +wire \data_num[10]~44_combout ; +wire \data_num[11]~47 ; +wire \data_num[11]~46_combout ; +wire \data_num[12]~49 ; +wire \data_num[12]~48_combout ; +wire \data_num[13]~51 ; +wire \data_num[13]~50_combout ; +wire \data_num[14]~53 ; +wire \data_num[14]~52_combout ; +wire \data_num[15]~55 ; +wire \data_num[15]~54_combout ; +wire \data_num[16]~57 ; +wire \data_num[16]~56_combout ; +wire \data_num[17]~59 ; +wire \data_num[17]~58_combout ; +wire \data_num[18]~61 ; +wire \data_num[18]~60_combout ; +wire \data_num[19]~63 ; +wire \data_num[19]~62_combout ; +wire \data_num[20]~65 ; +wire \data_num[20]~64_combout ; +wire \data_num[21]~67 ; +wire \data_num[21]~66_combout ; +wire \data_num[22]~69 ; +wire \data_num[22]~68_combout ; +wire \data_num[23]~70_combout ; +wire \uart_rx_inst|Add1~0_combout ; +wire \uart_rx_inst|Add1~5 ; +wire \uart_rx_inst|Add1~6_combout ; +wire \fifo_read_inst|cnt_read[0]~11 ; +wire \fifo_read_inst|cnt_read[0]~10_combout ; +wire \fifo_read_inst|cnt_read[1]~13 ; +wire \fifo_read_inst|cnt_read[1]~12_combout ; +wire \fifo_read_inst|cnt_read[2]~15 ; +wire \fifo_read_inst|cnt_read[2]~14_combout ; +wire \fifo_read_inst|cnt_read[3]~17 ; +wire \fifo_read_inst|cnt_read[3]~16_combout ; +wire \fifo_read_inst|cnt_read[4]~19 ; +wire \fifo_read_inst|cnt_read[4]~18_combout ; +wire \fifo_read_inst|cnt_read[5]~21 ; +wire \fifo_read_inst|cnt_read[5]~20_combout ; +wire \fifo_read_inst|cnt_read[6]~23 ; +wire \fifo_read_inst|cnt_read[6]~22_combout ; +wire \fifo_read_inst|cnt_read[7]~25 ; +wire \fifo_read_inst|cnt_read[7]~24_combout ; +wire \fifo_read_inst|cnt_read[8]~27 ; +wire \fifo_read_inst|cnt_read[8]~26_combout ; +wire \fifo_read_inst|cnt_read[9]~28_combout ; +wire \uart_rx_inst|baud_cnt[4]~21_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout ; +wire \uart_tx_inst|Mux0~0_combout ; +wire \uart_tx_inst|Mux0~1_combout ; +wire \uart_tx_inst|tx~0_combout ; +wire \uart_tx_inst|tx~1_combout ; +wire \uart_tx_inst|tx~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout ; +wire \uart_tx_inst|Add1~0_combout ; +wire \uart_tx_inst|Add1~1_combout ; +wire \uart_tx_inst|bit_cnt[3]~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout ; +wire \read_valid~q ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout ; +wire \uart_tx_inst|Equal1~3_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ; +wire \fifo_read_inst|Equal1~0_combout ; +wire \fifo_read_inst|Equal1~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout ; +wire \Equal0~0_combout ; +wire \Equal0~1_combout ; +wire \Equal0~2_combout ; +wire \Equal0~3_combout ; +wire \Equal0~4_combout ; +wire \read_valid~0_combout ; +wire \read_valid~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ; +wire \fifo_read_inst|Equal1~2_combout ; +wire \fifo_read_inst|Equal5~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \Equal1~0_combout ; +wire \Equal1~1_combout ; +wire \Equal1~2_combout ; +wire \Equal1~3_combout ; +wire \Equal1~4_combout ; +wire \Equal1~5_combout ; +wire \Equal1~6_combout ; +wire \cnt_wait[8]~0_combout ; +wire \cnt_wait[15]~1_combout ; +wire \cnt_wait[15]~2_combout ; +wire \cnt_wait[14]~3_combout ; +wire \cnt_wait[13]~4_combout ; +wire \cnt_wait[12]~5_combout ; +wire \cnt_wait[9]~6_combout ; +wire \cnt_wait[11]~7_combout ; +wire \cnt_wait[10]~8_combout ; +wire \cnt_wait[8]~9_combout ; +wire \cnt_wait[7]~10_combout ; +wire \cnt_wait[6]~11_combout ; +wire \cnt_wait[5]~12_combout ; +wire \cnt_wait[4]~13_combout ; +wire \cnt_wait[3]~14_combout ; +wire \cnt_wait[2]~15_combout ; +wire \cnt_wait[1]~16_combout ; +wire \cnt_wait[0]~17_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \fifo_read_inst|rd_flag~q ; +wire \fifo_read_inst|Equal4~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ; +wire \fifo_read_inst|Equal2~0_combout ; +wire \fifo_read_inst|Equal2~1_combout ; +wire \fifo_read_inst|Equal2~2_combout ; +wire \fifo_read_inst|rd_flag~0_combout ; +wire \uart_rx_inst|bit_cnt~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout ; +wire \uart_rx_inst|work_en~q ; +wire \uart_rx_inst|start_nedge~q ; +wire \uart_rx_inst|work_en~0_combout ; +wire \uart_rx_inst|always3~0_combout ; +wire \uart_tx_inst|bit_cnt[0]~5_combout ; +wire \sdram_dq[8]~input_o ; +wire \sdram_dq[9]~input_o ; +wire \sdram_dq[10]~input_o ; +wire \sdram_dq[11]~input_o ; +wire \sdram_dq[12]~input_o ; +wire \sdram_dq[13]~input_o ; +wire \sdram_dq[14]~input_o ; +wire \sdram_dq[15]~input_o ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout ; +wire \uart_rx_inst|baud_cnt[0]~13_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \uart_rx_inst|baud_cnt[2]~18 ; +wire \uart_rx_inst|baud_cnt[3]~19_combout ; +wire \uart_rx_inst|baud_cnt[3]~20 ; +wire \uart_rx_inst|baud_cnt[4]~22 ; +wire \uart_rx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|Equal1~1_combout ; +wire \uart_rx_inst|baud_cnt[5]~24 ; +wire \uart_rx_inst|baud_cnt[6]~25_combout ; +wire \uart_rx_inst|baud_cnt[6]~26 ; +wire \uart_rx_inst|baud_cnt[7]~27_combout ; +wire \uart_rx_inst|baud_cnt[7]~28 ; +wire \uart_rx_inst|baud_cnt[8]~29_combout ; +wire \uart_rx_inst|Equal1~0_combout ; +wire \uart_rx_inst|baud_cnt[8]~30 ; +wire \uart_rx_inst|baud_cnt[9]~31_combout ; +wire \uart_rx_inst|baud_cnt[9]~32 ; +wire \uart_rx_inst|baud_cnt[10]~34 ; +wire \uart_rx_inst|baud_cnt[11]~35_combout ; +wire \uart_rx_inst|Equal1~2_combout ; +wire \uart_rx_inst|baud_cnt[10]~33_combout ; +wire \uart_rx_inst|Equal1~3_combout ; +wire \uart_rx_inst|always5~0_combout ; +wire \uart_rx_inst|baud_cnt[0]~14 ; +wire \uart_rx_inst|baud_cnt[1]~15_combout ; +wire \uart_rx_inst|baud_cnt[1]~16 ; +wire \uart_rx_inst|baud_cnt[2]~17_combout ; +wire \uart_rx_inst|Equal2~0_combout ; +wire \uart_rx_inst|baud_cnt[11]~36 ; +wire \uart_rx_inst|baud_cnt[12]~37_combout ; +wire \uart_rx_inst|Equal2~1_combout ; +wire \uart_rx_inst|Equal2~2_combout ; +wire \uart_rx_inst|bit_flag~q ; +wire \uart_rx_inst|Add1~1 ; +wire \uart_rx_inst|Add1~3 ; +wire \uart_rx_inst|Add1~4_combout ; +wire \uart_rx_inst|Add1~2_combout ; +wire \uart_rx_inst|always4~0_combout ; +wire \uart_rx_inst|always4~1_combout ; +wire \uart_rx_inst|rx_flag~q ; +wire \uart_rx_inst|po_flag~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ; +wire \fifo_read_inst|read_en_dly~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout ; +wire \fifo_read_inst|Add2~0_combout ; +wire \fifo_read_inst|Add2~1 ; +wire \fifo_read_inst|Add2~3 ; +wire \fifo_read_inst|Add2~5 ; +wire \fifo_read_inst|Add2~6_combout ; +wire \fifo_read_inst|bit_cnt~0_combout ; +wire \fifo_read_inst|baud_cnt[0]~13_combout ; +wire \fifo_read_inst|baud_cnt[5]~24 ; +wire \fifo_read_inst|baud_cnt[6]~25_combout ; +wire \fifo_read_inst|baud_cnt[6]~26 ; +wire \fifo_read_inst|baud_cnt[7]~27_combout ; +wire \fifo_read_inst|baud_cnt[7]~28 ; +wire \fifo_read_inst|baud_cnt[8]~29_combout ; +wire \fifo_read_inst|Equal4~0_combout ; +wire \fifo_read_inst|baud_cnt[3]~19_combout ; +wire \fifo_read_inst|Equal4~1_combout ; +wire \fifo_read_inst|baud_cnt[8]~30 ; +wire \fifo_read_inst|baud_cnt[9]~32 ; +wire \fifo_read_inst|baud_cnt[10]~33_combout ; +wire \fifo_read_inst|baud_cnt[10]~34 ; +wire \fifo_read_inst|baud_cnt[11]~36 ; +wire \fifo_read_inst|baud_cnt[12]~37_combout ; +wire \fifo_read_inst|Equal4~3_combout ; +wire \fifo_read_inst|baud_cnt[0]~14 ; +wire \fifo_read_inst|baud_cnt[1]~16 ; +wire \fifo_read_inst|baud_cnt[2]~17_combout ; +wire \fifo_read_inst|baud_cnt[2]~18 ; +wire \fifo_read_inst|baud_cnt[3]~20 ; +wire \fifo_read_inst|baud_cnt[4]~22 ; +wire \fifo_read_inst|baud_cnt[5]~23_combout ; +wire \fifo_read_inst|Equal5~0_combout ; +wire \fifo_read_inst|Equal5~2_combout ; +wire \fifo_read_inst|bit_flag~q ; +wire \fifo_read_inst|Add2~2_combout ; +wire \fifo_read_inst|bit_cnt~1_combout ; +wire \fifo_read_inst|always5~0_combout ; +wire \fifo_read_inst|always5~1_combout ; +wire \fifo_read_inst|rd_en~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ; +wire \Equal2~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ; +wire \fifo_read_inst|read_en~0_combout ; +wire \fifo_read_inst|read_en~1_combout ; +wire \fifo_read_inst|read_en~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ; +wire \Equal2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \rx~input_o ; +wire \uart_rx_inst|rx_reg1~0_combout ; +wire \uart_rx_inst|rx_reg1~q ; +wire \uart_rx_inst|rx_reg2~feeder_combout ; +wire \uart_rx_inst|rx_reg2~q ; +wire \uart_rx_inst|rx_reg3~feeder_combout ; +wire \uart_rx_inst|rx_reg3~q ; +wire \uart_rx_inst|rx_data[7]~0_combout ; +wire \uart_rx_inst|bit_cnt~0_combout ; +wire \uart_rx_inst|always8~0_combout ; +wire \uart_rx_inst|rx_data[5]~feeder_combout ; +wire \uart_rx_inst|rx_data[4]~feeder_combout ; +wire \uart_rx_inst|rx_data[3]~feeder_combout ; +wire \uart_rx_inst|rx_data[2]~feeder_combout ; +wire \uart_rx_inst|rx_data[1]~feeder_combout ; +wire \uart_rx_inst|rx_data[0]~feeder_combout ; +wire \uart_rx_inst|po_data[0]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \uart_rx_inst|po_data[1]~feeder_combout ; +wire \uart_rx_inst|po_data[2]~feeder_combout ; +wire \uart_rx_inst|po_data[3]~feeder_combout ; +wire \uart_rx_inst|po_data[4]~feeder_combout ; +wire \uart_rx_inst|po_data[5]~feeder_combout ; +wire \uart_rx_inst|po_data[6]~feeder_combout ; +wire \~GND~combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ; +wire \sys_clk~inputclkctrl_outclk ; +wire \uart_tx_inst|baud_cnt[0]~13_combout ; +wire \uart_tx_inst|baud_cnt[11]~35_combout ; +wire \uart_tx_inst|Equal1~0_combout ; +wire \uart_tx_inst|baud_cnt[9]~31_combout ; +wire \uart_tx_inst|Equal1~1_combout ; +wire \uart_tx_inst|baud_cnt[1]~15_combout ; +wire \uart_tx_inst|Equal1~2_combout ; +wire \fifo_read_inst|tx_flag~q ; +wire \uart_tx_inst|always3~0_combout ; +wire \uart_tx_inst|bit_cnt[1]~2_combout ; +wire \uart_tx_inst|bit_cnt[2]~3_combout ; +wire \uart_tx_inst|always0~1_combout ; +wire \uart_tx_inst|work_en~0_combout ; +wire \uart_tx_inst|work_en~q ; +wire \uart_tx_inst|always1~0_combout ; +wire \uart_tx_inst|baud_cnt[0]~14 ; +wire \uart_tx_inst|baud_cnt[1]~16 ; +wire \uart_tx_inst|baud_cnt[2]~17_combout ; +wire \uart_tx_inst|baud_cnt[2]~18 ; +wire \uart_tx_inst|baud_cnt[3]~20 ; +wire \uart_tx_inst|baud_cnt[4]~22 ; +wire \uart_tx_inst|baud_cnt[5]~23_combout ; +wire \uart_tx_inst|baud_cnt[5]~24 ; +wire \uart_tx_inst|baud_cnt[6]~25_combout ; +wire \uart_tx_inst|baud_cnt[6]~26 ; +wire \uart_tx_inst|baud_cnt[7]~27_combout ; +wire \uart_tx_inst|baud_cnt[7]~28 ; +wire \uart_tx_inst|baud_cnt[8]~29_combout ; +wire \uart_tx_inst|baud_cnt[8]~30 ; +wire \uart_tx_inst|baud_cnt[9]~32 ; +wire \uart_tx_inst|baud_cnt[10]~33_combout ; +wire \uart_tx_inst|baud_cnt[10]~34 ; +wire \uart_tx_inst|baud_cnt[11]~36 ; +wire \uart_tx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal2~0_combout ; +wire \uart_tx_inst|Equal2~1_combout ; +wire \uart_tx_inst|bit_flag~q ; +wire \uart_tx_inst|always0~0_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ; +wire \sdram_dq[0]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \sdram_dq[1]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout ; +wire \sdram_dq[2]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout ; +wire \sdram_dq[3]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout ; +wire \sdram_dq[4]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout ; +wire \sdram_dq[5]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout ; +wire \sdram_dq[6]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout ; +wire \sdram_dq[7]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout ; +wire \uart_tx_inst|tx~4_combout ; +wire \uart_tx_inst|tx~3_combout ; +wire \uart_tx_inst|tx~5_combout ; +wire \uart_tx_inst|tx~q ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a ; +wire [15:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a ; +wire [9:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit ; +wire [23:0] data_num; +wire [15:0] cnt_wait; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \uart_rx_inst|rx_data ; +wire [7:0] \uart_rx_inst|po_data ; +wire [3:0] \uart_rx_inst|bit_cnt ; +wire [12:0] \uart_rx_inst|baud_cnt ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g ; +wire [9:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a ; +wire [15:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd ; +wire [1:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref ; +wire [2:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk ; +wire [14:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us ; +wire [2:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk ; +wire [1:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref ; +wire [9:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd ; +wire [1:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba ; +wire [12:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr ; +wire [9:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd ; +wire [12:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr ; +wire [15:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg ; +wire [9:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk ; +wire [9:0] \fifo_read_inst|cnt_read ; +wire [3:0] \fifo_read_inst|bit_cnt ; +wire [12:0] \fifo_read_inst|baud_cnt ; +wire [9:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit ; +wire [7:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b ; +wire [9:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit ; +wire [3:0] \uart_tx_inst|bit_cnt ; +wire [12:0] \uart_tx_inst|baud_cnt ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; +wire [8:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus ; +wire [8:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; +wire [8:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; +wire [8:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [0] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [0]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [1] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [1]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [2] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [2]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [3] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [3]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [4] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [4]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [5] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [5]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [6] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [6]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [7] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [7]; + +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; + +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [8] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [8]; + +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [9] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [0]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [10] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [1]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [11] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [2]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [12] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [3]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [13] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [4]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [14] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [5]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [15] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [6]; + +// Location: M9K_X25_Y18_N0 +cycloneive_ram_block \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 ( + .portawe(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .ena1(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({gnd,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0]}), + .portaaddr({\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .clk0_core_clock_enable = "ena0"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .clk1_core_clock_enable = "ena1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .clk1_input_clock_enable = "ena1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .data_interleave_offset_in_bits = 1; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .data_interleave_width_in_bits = 1; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .logical_ram_name = "fifo_read:fifo_read_inst|read_fifo:read_fifo_inst|scfifo:scfifo_component|scfifo_un21:auto_generated|a_dpfifo_5u21:dpfifo|dpram_d811:FIFOram|altsyncram_c3k1:altsyncram1|ALTSYNCRAM"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .operation_mode = "dual_port"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_address_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_address_width = 10; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_byte_enable_clock = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_data_out_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_data_out_clock = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_data_width = 9; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_first_address = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_first_bit_number = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_last_address = 1023; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_logical_ram_depth = 1024; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_logical_ram_width = 8; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_address_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_address_clock = "clock1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_address_width = 10; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_data_out_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_data_out_clock = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_data_width = 9; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_first_address = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_first_bit_number = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_last_address = 1023; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_logical_ram_depth = 1024; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_logical_ram_width = 8; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_read_enable_clock = "clock1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: FF_X24_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y21_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y23_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y23_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y18_N11 +dffeas \uart_tx_inst|baud_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y18_N13 +dffeas \uart_tx_inst|baud_cnt[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0] & ((GND) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0]))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0] $ (GND))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0 .lut_mask = 16'h66BB; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N10 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) + + .dataa(\uart_tx_inst|baud_cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[2]~18 ), + .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_tx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N12 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) +// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[3]~20 ), + .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_tx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [13] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N8 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N10 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N14 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N18 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT ) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N7 +dffeas \fifo_read_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N13 +dffeas \fifo_read_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N23 +dffeas \fifo_read_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N27 +dffeas \fifo_read_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N12 +cycloneive_lcell_comb \fifo_read_inst|Add2~4 ( +// Equation(s): +// \fifo_read_inst|Add2~4_combout = (\fifo_read_inst|bit_cnt [2] & (\fifo_read_inst|Add2~3 $ (GND))) # (!\fifo_read_inst|bit_cnt [2] & (!\fifo_read_inst|Add2~3 & VCC)) +// \fifo_read_inst|Add2~5 = CARRY((\fifo_read_inst|bit_cnt [2] & !\fifo_read_inst|Add2~3 )) + + .dataa(\fifo_read_inst|bit_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|Add2~3 ), + .combout(\fifo_read_inst|Add2~4_combout ), + .cout(\fifo_read_inst|Add2~5 )); +// synopsys translate_off +defparam \fifo_read_inst|Add2~4 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|Add2~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y24_N9 +dffeas \data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[0]~24_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[0] .is_wysiwyg = "true"; +defparam \data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N13 +dffeas \data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[2]~28_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[2] .is_wysiwyg = "true"; +defparam \data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N11 +dffeas \data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[1]~26_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[1] .is_wysiwyg = "true"; +defparam \data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N15 +dffeas \data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[3]~30_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[3] .is_wysiwyg = "true"; +defparam \data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N17 +dffeas \data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[4]~32_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[4] .is_wysiwyg = "true"; +defparam \data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N19 +dffeas \data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[5]~34_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[5] .is_wysiwyg = "true"; +defparam \data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N21 +dffeas \data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[6]~36_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[6] .is_wysiwyg = "true"; +defparam \data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N23 +dffeas \data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[7]~38_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[7] .is_wysiwyg = "true"; +defparam \data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N25 +dffeas \data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[8]~40_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[8] .is_wysiwyg = "true"; +defparam \data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N27 +dffeas \data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[9]~42_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[9] .is_wysiwyg = "true"; +defparam \data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N29 +dffeas \data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[10]~44_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[10] .is_wysiwyg = "true"; +defparam \data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N31 +dffeas \data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[11]~46_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[11]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[11] .is_wysiwyg = "true"; +defparam \data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N1 +dffeas \data_num[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[12]~48_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[12]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[12] .is_wysiwyg = "true"; +defparam \data_num[12] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N3 +dffeas \data_num[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[13]~50_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[13]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[13] .is_wysiwyg = "true"; +defparam \data_num[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N5 +dffeas \data_num[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[14]~52_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[14]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[14] .is_wysiwyg = "true"; +defparam \data_num[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N7 +dffeas \data_num[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[15]~54_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[15]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[15] .is_wysiwyg = "true"; +defparam \data_num[15] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N9 +dffeas \data_num[16] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[16]~56_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[16]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[16] .is_wysiwyg = "true"; +defparam \data_num[16] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N11 +dffeas \data_num[17] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[17]~58_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[17]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[17] .is_wysiwyg = "true"; +defparam \data_num[17] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N13 +dffeas \data_num[18] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[18]~60_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[18]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[18] .is_wysiwyg = "true"; +defparam \data_num[18] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N15 +dffeas \data_num[19] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[19]~62_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[19]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[19] .is_wysiwyg = "true"; +defparam \data_num[19] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N17 +dffeas \data_num[20] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[20]~64_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[20]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[20] .is_wysiwyg = "true"; +defparam \data_num[20] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N19 +dffeas \data_num[21] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[21]~66_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[21]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[21] .is_wysiwyg = "true"; +defparam \data_num[21] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N21 +dffeas \data_num[22] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[22]~68_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[22]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[22] .is_wysiwyg = "true"; +defparam \data_num[22] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N23 +dffeas \data_num[23] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[23]~70_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[23]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[23] .is_wysiwyg = "true"; +defparam \data_num[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N0 +cycloneive_lcell_comb \Add1~0 ( +// Equation(s): +// \Add1~0_combout = cnt_wait[0] $ (VCC) +// \Add1~1 = CARRY(cnt_wait[0]) + + .dataa(gnd), + .datab(cnt_wait[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Add1~0_combout ), + .cout(\Add1~1 )); +// synopsys translate_off +defparam \Add1~0 .lut_mask = 16'h33CC; +defparam \Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N2 +cycloneive_lcell_comb \Add1~2 ( +// Equation(s): +// \Add1~2_combout = (cnt_wait[1] & (!\Add1~1 )) # (!cnt_wait[1] & ((\Add1~1 ) # (GND))) +// \Add1~3 = CARRY((!\Add1~1 ) # (!cnt_wait[1])) + + .dataa(cnt_wait[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~1 ), + .combout(\Add1~2_combout ), + .cout(\Add1~3 )); +// synopsys translate_off +defparam \Add1~2 .lut_mask = 16'h5A5F; +defparam \Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N4 +cycloneive_lcell_comb \Add1~4 ( +// Equation(s): +// \Add1~4_combout = (cnt_wait[2] & (\Add1~3 $ (GND))) # (!cnt_wait[2] & (!\Add1~3 & VCC)) +// \Add1~5 = CARRY((cnt_wait[2] & !\Add1~3 )) + + .dataa(gnd), + .datab(cnt_wait[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~3 ), + .combout(\Add1~4_combout ), + .cout(\Add1~5 )); +// synopsys translate_off +defparam \Add1~4 .lut_mask = 16'hC30C; +defparam \Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N6 +cycloneive_lcell_comb \Add1~6 ( +// Equation(s): +// \Add1~6_combout = (cnt_wait[3] & (!\Add1~5 )) # (!cnt_wait[3] & ((\Add1~5 ) # (GND))) +// \Add1~7 = CARRY((!\Add1~5 ) # (!cnt_wait[3])) + + .dataa(gnd), + .datab(cnt_wait[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~5 ), + .combout(\Add1~6_combout ), + .cout(\Add1~7 )); +// synopsys translate_off +defparam \Add1~6 .lut_mask = 16'h3C3F; +defparam \Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N8 +cycloneive_lcell_comb \Add1~8 ( +// Equation(s): +// \Add1~8_combout = (cnt_wait[4] & (\Add1~7 $ (GND))) # (!cnt_wait[4] & (!\Add1~7 & VCC)) +// \Add1~9 = CARRY((cnt_wait[4] & !\Add1~7 )) + + .dataa(cnt_wait[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~7 ), + .combout(\Add1~8_combout ), + .cout(\Add1~9 )); +// synopsys translate_off +defparam \Add1~8 .lut_mask = 16'hA50A; +defparam \Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N10 +cycloneive_lcell_comb \Add1~10 ( +// Equation(s): +// \Add1~10_combout = (cnt_wait[5] & (!\Add1~9 )) # (!cnt_wait[5] & ((\Add1~9 ) # (GND))) +// \Add1~11 = CARRY((!\Add1~9 ) # (!cnt_wait[5])) + + .dataa(cnt_wait[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~9 ), + .combout(\Add1~10_combout ), + .cout(\Add1~11 )); +// synopsys translate_off +defparam \Add1~10 .lut_mask = 16'h5A5F; +defparam \Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N12 +cycloneive_lcell_comb \Add1~12 ( +// Equation(s): +// \Add1~12_combout = (cnt_wait[6] & (\Add1~11 $ (GND))) # (!cnt_wait[6] & (!\Add1~11 & VCC)) +// \Add1~13 = CARRY((cnt_wait[6] & !\Add1~11 )) + + .dataa(cnt_wait[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~11 ), + .combout(\Add1~12_combout ), + .cout(\Add1~13 )); +// synopsys translate_off +defparam \Add1~12 .lut_mask = 16'hA50A; +defparam \Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N14 +cycloneive_lcell_comb \Add1~14 ( +// Equation(s): +// \Add1~14_combout = (cnt_wait[7] & (!\Add1~13 )) # (!cnt_wait[7] & ((\Add1~13 ) # (GND))) +// \Add1~15 = CARRY((!\Add1~13 ) # (!cnt_wait[7])) + + .dataa(cnt_wait[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~13 ), + .combout(\Add1~14_combout ), + .cout(\Add1~15 )); +// synopsys translate_off +defparam \Add1~14 .lut_mask = 16'h5A5F; +defparam \Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N16 +cycloneive_lcell_comb \Add1~16 ( +// Equation(s): +// \Add1~16_combout = (cnt_wait[8] & (\Add1~15 $ (GND))) # (!cnt_wait[8] & (!\Add1~15 & VCC)) +// \Add1~17 = CARRY((cnt_wait[8] & !\Add1~15 )) + + .dataa(cnt_wait[8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~15 ), + .combout(\Add1~16_combout ), + .cout(\Add1~17 )); +// synopsys translate_off +defparam \Add1~16 .lut_mask = 16'hA50A; +defparam \Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N18 +cycloneive_lcell_comb \Add1~18 ( +// Equation(s): +// \Add1~18_combout = (cnt_wait[9] & (!\Add1~17 )) # (!cnt_wait[9] & ((\Add1~17 ) # (GND))) +// \Add1~19 = CARRY((!\Add1~17 ) # (!cnt_wait[9])) + + .dataa(gnd), + .datab(cnt_wait[9]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~17 ), + .combout(\Add1~18_combout ), + .cout(\Add1~19 )); +// synopsys translate_off +defparam \Add1~18 .lut_mask = 16'h3C3F; +defparam \Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N20 +cycloneive_lcell_comb \Add1~20 ( +// Equation(s): +// \Add1~20_combout = (cnt_wait[10] & (\Add1~19 $ (GND))) # (!cnt_wait[10] & (!\Add1~19 & VCC)) +// \Add1~21 = CARRY((cnt_wait[10] & !\Add1~19 )) + + .dataa(cnt_wait[10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~19 ), + .combout(\Add1~20_combout ), + .cout(\Add1~21 )); +// synopsys translate_off +defparam \Add1~20 .lut_mask = 16'hA50A; +defparam \Add1~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N22 +cycloneive_lcell_comb \Add1~22 ( +// Equation(s): +// \Add1~22_combout = (cnt_wait[11] & (!\Add1~21 )) # (!cnt_wait[11] & ((\Add1~21 ) # (GND))) +// \Add1~23 = CARRY((!\Add1~21 ) # (!cnt_wait[11])) + + .dataa(gnd), + .datab(cnt_wait[11]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~21 ), + .combout(\Add1~22_combout ), + .cout(\Add1~23 )); +// synopsys translate_off +defparam \Add1~22 .lut_mask = 16'h3C3F; +defparam \Add1~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N24 +cycloneive_lcell_comb \Add1~24 ( +// Equation(s): +// \Add1~24_combout = (cnt_wait[12] & (\Add1~23 $ (GND))) # (!cnt_wait[12] & (!\Add1~23 & VCC)) +// \Add1~25 = CARRY((cnt_wait[12] & !\Add1~23 )) + + .dataa(gnd), + .datab(cnt_wait[12]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~23 ), + .combout(\Add1~24_combout ), + .cout(\Add1~25 )); +// synopsys translate_off +defparam \Add1~24 .lut_mask = 16'hC30C; +defparam \Add1~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N26 +cycloneive_lcell_comb \Add1~26 ( +// Equation(s): +// \Add1~26_combout = (cnt_wait[13] & (!\Add1~25 )) # (!cnt_wait[13] & ((\Add1~25 ) # (GND))) +// \Add1~27 = CARRY((!\Add1~25 ) # (!cnt_wait[13])) + + .dataa(gnd), + .datab(cnt_wait[13]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~25 ), + .combout(\Add1~26_combout ), + .cout(\Add1~27 )); +// synopsys translate_off +defparam \Add1~26 .lut_mask = 16'h3C3F; +defparam \Add1~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N28 +cycloneive_lcell_comb \Add1~28 ( +// Equation(s): +// \Add1~28_combout = (cnt_wait[14] & (\Add1~27 $ (GND))) # (!cnt_wait[14] & (!\Add1~27 & VCC)) +// \Add1~29 = CARRY((cnt_wait[14] & !\Add1~27 )) + + .dataa(cnt_wait[14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~27 ), + .combout(\Add1~28_combout ), + .cout(\Add1~29 )); +// synopsys translate_off +defparam \Add1~28 .lut_mask = 16'hA50A; +defparam \Add1~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N30 +cycloneive_lcell_comb \Add1~30 ( +// Equation(s): +// \Add1~30_combout = \Add1~29 $ (cnt_wait[15]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(cnt_wait[15]), + .cin(\Add1~29 ), + .combout(\Add1~30_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~30 .lut_mask = 16'h0FF0; +defparam \Add1~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N6 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[1]~15 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[1]~15_combout = (\fifo_read_inst|baud_cnt [1] & (!\fifo_read_inst|baud_cnt[0]~14 )) # (!\fifo_read_inst|baud_cnt [1] & ((\fifo_read_inst|baud_cnt[0]~14 ) # (GND))) +// \fifo_read_inst|baud_cnt[1]~16 = CARRY((!\fifo_read_inst|baud_cnt[0]~14 ) # (!\fifo_read_inst|baud_cnt [1])) + + .dataa(\fifo_read_inst|baud_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[0]~14 ), + .combout(\fifo_read_inst|baud_cnt[1]~15_combout ), + .cout(\fifo_read_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N12 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[4]~21 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[4]~21_combout = (\fifo_read_inst|baud_cnt [4] & (\fifo_read_inst|baud_cnt[3]~20 $ (GND))) # (!\fifo_read_inst|baud_cnt [4] & (!\fifo_read_inst|baud_cnt[3]~20 & VCC)) +// \fifo_read_inst|baud_cnt[4]~22 = CARRY((\fifo_read_inst|baud_cnt [4] & !\fifo_read_inst|baud_cnt[3]~20 )) + + .dataa(\fifo_read_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[3]~20 ), + .combout(\fifo_read_inst|baud_cnt[4]~21_combout ), + .cout(\fifo_read_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N22 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[9]~31 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[9]~31_combout = (\fifo_read_inst|baud_cnt [9] & (!\fifo_read_inst|baud_cnt[8]~30 )) # (!\fifo_read_inst|baud_cnt [9] & ((\fifo_read_inst|baud_cnt[8]~30 ) # (GND))) +// \fifo_read_inst|baud_cnt[9]~32 = CARRY((!\fifo_read_inst|baud_cnt[8]~30 ) # (!\fifo_read_inst|baud_cnt [9])) + + .dataa(\fifo_read_inst|baud_cnt [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[8]~30 ), + .combout(\fifo_read_inst|baud_cnt[9]~31_combout ), + .cout(\fifo_read_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[9]~31 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N26 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[11]~35 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[11]~35_combout = (\fifo_read_inst|baud_cnt [11] & (!\fifo_read_inst|baud_cnt[10]~34 )) # (!\fifo_read_inst|baud_cnt [11] & ((\fifo_read_inst|baud_cnt[10]~34 ) # (GND))) +// \fifo_read_inst|baud_cnt[11]~36 = CARRY((!\fifo_read_inst|baud_cnt[10]~34 ) # (!\fifo_read_inst|baud_cnt [11])) + + .dataa(\fifo_read_inst|baud_cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[10]~34 ), + .combout(\fifo_read_inst|baud_cnt[11]~35_combout ), + .cout(\fifo_read_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N8 +cycloneive_lcell_comb \data_num[0]~24 ( +// Equation(s): +// \data_num[0]~24_combout = (\uart_rx_inst|po_flag~q & (data_num[0] $ (VCC))) # (!\uart_rx_inst|po_flag~q & (data_num[0] & VCC)) +// \data_num[0]~25 = CARRY((\uart_rx_inst|po_flag~q & data_num[0])) + + .dataa(\uart_rx_inst|po_flag~q ), + .datab(data_num[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_num[0]~24_combout ), + .cout(\data_num[0]~25 )); +// synopsys translate_off +defparam \data_num[0]~24 .lut_mask = 16'h6688; +defparam \data_num[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N10 +cycloneive_lcell_comb \data_num[1]~26 ( +// Equation(s): +// \data_num[1]~26_combout = (data_num[1] & (!\data_num[0]~25 )) # (!data_num[1] & ((\data_num[0]~25 ) # (GND))) +// \data_num[1]~27 = CARRY((!\data_num[0]~25 ) # (!data_num[1])) + + .dataa(data_num[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[0]~25 ), + .combout(\data_num[1]~26_combout ), + .cout(\data_num[1]~27 )); +// synopsys translate_off +defparam \data_num[1]~26 .lut_mask = 16'h5A5F; +defparam \data_num[1]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N12 +cycloneive_lcell_comb \data_num[2]~28 ( +// Equation(s): +// \data_num[2]~28_combout = (data_num[2] & (\data_num[1]~27 $ (GND))) # (!data_num[2] & (!\data_num[1]~27 & VCC)) +// \data_num[2]~29 = CARRY((data_num[2] & !\data_num[1]~27 )) + + .dataa(data_num[2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[1]~27 ), + .combout(\data_num[2]~28_combout ), + .cout(\data_num[2]~29 )); +// synopsys translate_off +defparam \data_num[2]~28 .lut_mask = 16'hA50A; +defparam \data_num[2]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N14 +cycloneive_lcell_comb \data_num[3]~30 ( +// Equation(s): +// \data_num[3]~30_combout = (data_num[3] & (!\data_num[2]~29 )) # (!data_num[3] & ((\data_num[2]~29 ) # (GND))) +// \data_num[3]~31 = CARRY((!\data_num[2]~29 ) # (!data_num[3])) + + .dataa(gnd), + .datab(data_num[3]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[2]~29 ), + .combout(\data_num[3]~30_combout ), + .cout(\data_num[3]~31 )); +// synopsys translate_off +defparam \data_num[3]~30 .lut_mask = 16'h3C3F; +defparam \data_num[3]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N16 +cycloneive_lcell_comb \data_num[4]~32 ( +// Equation(s): +// \data_num[4]~32_combout = (data_num[4] & (\data_num[3]~31 $ (GND))) # (!data_num[4] & (!\data_num[3]~31 & VCC)) +// \data_num[4]~33 = CARRY((data_num[4] & !\data_num[3]~31 )) + + .dataa(gnd), + .datab(data_num[4]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[3]~31 ), + .combout(\data_num[4]~32_combout ), + .cout(\data_num[4]~33 )); +// synopsys translate_off +defparam \data_num[4]~32 .lut_mask = 16'hC30C; +defparam \data_num[4]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N18 +cycloneive_lcell_comb \data_num[5]~34 ( +// Equation(s): +// \data_num[5]~34_combout = (data_num[5] & (!\data_num[4]~33 )) # (!data_num[5] & ((\data_num[4]~33 ) # (GND))) +// \data_num[5]~35 = CARRY((!\data_num[4]~33 ) # (!data_num[5])) + + .dataa(gnd), + .datab(data_num[5]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[4]~33 ), + .combout(\data_num[5]~34_combout ), + .cout(\data_num[5]~35 )); +// synopsys translate_off +defparam \data_num[5]~34 .lut_mask = 16'h3C3F; +defparam \data_num[5]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N20 +cycloneive_lcell_comb \data_num[6]~36 ( +// Equation(s): +// \data_num[6]~36_combout = (data_num[6] & (\data_num[5]~35 $ (GND))) # (!data_num[6] & (!\data_num[5]~35 & VCC)) +// \data_num[6]~37 = CARRY((data_num[6] & !\data_num[5]~35 )) + + .dataa(gnd), + .datab(data_num[6]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[5]~35 ), + .combout(\data_num[6]~36_combout ), + .cout(\data_num[6]~37 )); +// synopsys translate_off +defparam \data_num[6]~36 .lut_mask = 16'hC30C; +defparam \data_num[6]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N22 +cycloneive_lcell_comb \data_num[7]~38 ( +// Equation(s): +// \data_num[7]~38_combout = (data_num[7] & (!\data_num[6]~37 )) # (!data_num[7] & ((\data_num[6]~37 ) # (GND))) +// \data_num[7]~39 = CARRY((!\data_num[6]~37 ) # (!data_num[7])) + + .dataa(data_num[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[6]~37 ), + .combout(\data_num[7]~38_combout ), + .cout(\data_num[7]~39 )); +// synopsys translate_off +defparam \data_num[7]~38 .lut_mask = 16'h5A5F; +defparam \data_num[7]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N24 +cycloneive_lcell_comb \data_num[8]~40 ( +// Equation(s): +// \data_num[8]~40_combout = (data_num[8] & (\data_num[7]~39 $ (GND))) # (!data_num[8] & (!\data_num[7]~39 & VCC)) +// \data_num[8]~41 = CARRY((data_num[8] & !\data_num[7]~39 )) + + .dataa(gnd), + .datab(data_num[8]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[7]~39 ), + .combout(\data_num[8]~40_combout ), + .cout(\data_num[8]~41 )); +// synopsys translate_off +defparam \data_num[8]~40 .lut_mask = 16'hC30C; +defparam \data_num[8]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N26 +cycloneive_lcell_comb \data_num[9]~42 ( +// Equation(s): +// \data_num[9]~42_combout = (data_num[9] & (!\data_num[8]~41 )) # (!data_num[9] & ((\data_num[8]~41 ) # (GND))) +// \data_num[9]~43 = CARRY((!\data_num[8]~41 ) # (!data_num[9])) + + .dataa(data_num[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[8]~41 ), + .combout(\data_num[9]~42_combout ), + .cout(\data_num[9]~43 )); +// synopsys translate_off +defparam \data_num[9]~42 .lut_mask = 16'h5A5F; +defparam \data_num[9]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N28 +cycloneive_lcell_comb \data_num[10]~44 ( +// Equation(s): +// \data_num[10]~44_combout = (data_num[10] & (\data_num[9]~43 $ (GND))) # (!data_num[10] & (!\data_num[9]~43 & VCC)) +// \data_num[10]~45 = CARRY((data_num[10] & !\data_num[9]~43 )) + + .dataa(gnd), + .datab(data_num[10]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[9]~43 ), + .combout(\data_num[10]~44_combout ), + .cout(\data_num[10]~45 )); +// synopsys translate_off +defparam \data_num[10]~44 .lut_mask = 16'hC30C; +defparam \data_num[10]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N30 +cycloneive_lcell_comb \data_num[11]~46 ( +// Equation(s): +// \data_num[11]~46_combout = (data_num[11] & (!\data_num[10]~45 )) # (!data_num[11] & ((\data_num[10]~45 ) # (GND))) +// \data_num[11]~47 = CARRY((!\data_num[10]~45 ) # (!data_num[11])) + + .dataa(data_num[11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[10]~45 ), + .combout(\data_num[11]~46_combout ), + .cout(\data_num[11]~47 )); +// synopsys translate_off +defparam \data_num[11]~46 .lut_mask = 16'h5A5F; +defparam \data_num[11]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N0 +cycloneive_lcell_comb \data_num[12]~48 ( +// Equation(s): +// \data_num[12]~48_combout = (data_num[12] & (\data_num[11]~47 $ (GND))) # (!data_num[12] & (!\data_num[11]~47 & VCC)) +// \data_num[12]~49 = CARRY((data_num[12] & !\data_num[11]~47 )) + + .dataa(gnd), + .datab(data_num[12]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[11]~47 ), + .combout(\data_num[12]~48_combout ), + .cout(\data_num[12]~49 )); +// synopsys translate_off +defparam \data_num[12]~48 .lut_mask = 16'hC30C; +defparam \data_num[12]~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N2 +cycloneive_lcell_comb \data_num[13]~50 ( +// Equation(s): +// \data_num[13]~50_combout = (data_num[13] & (!\data_num[12]~49 )) # (!data_num[13] & ((\data_num[12]~49 ) # (GND))) +// \data_num[13]~51 = CARRY((!\data_num[12]~49 ) # (!data_num[13])) + + .dataa(gnd), + .datab(data_num[13]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[12]~49 ), + .combout(\data_num[13]~50_combout ), + .cout(\data_num[13]~51 )); +// synopsys translate_off +defparam \data_num[13]~50 .lut_mask = 16'h3C3F; +defparam \data_num[13]~50 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N4 +cycloneive_lcell_comb \data_num[14]~52 ( +// Equation(s): +// \data_num[14]~52_combout = (data_num[14] & (\data_num[13]~51 $ (GND))) # (!data_num[14] & (!\data_num[13]~51 & VCC)) +// \data_num[14]~53 = CARRY((data_num[14] & !\data_num[13]~51 )) + + .dataa(gnd), + .datab(data_num[14]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[13]~51 ), + .combout(\data_num[14]~52_combout ), + .cout(\data_num[14]~53 )); +// synopsys translate_off +defparam \data_num[14]~52 .lut_mask = 16'hC30C; +defparam \data_num[14]~52 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N6 +cycloneive_lcell_comb \data_num[15]~54 ( +// Equation(s): +// \data_num[15]~54_combout = (data_num[15] & (!\data_num[14]~53 )) # (!data_num[15] & ((\data_num[14]~53 ) # (GND))) +// \data_num[15]~55 = CARRY((!\data_num[14]~53 ) # (!data_num[15])) + + .dataa(data_num[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[14]~53 ), + .combout(\data_num[15]~54_combout ), + .cout(\data_num[15]~55 )); +// synopsys translate_off +defparam \data_num[15]~54 .lut_mask = 16'h5A5F; +defparam \data_num[15]~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N8 +cycloneive_lcell_comb \data_num[16]~56 ( +// Equation(s): +// \data_num[16]~56_combout = (data_num[16] & (\data_num[15]~55 $ (GND))) # (!data_num[16] & (!\data_num[15]~55 & VCC)) +// \data_num[16]~57 = CARRY((data_num[16] & !\data_num[15]~55 )) + + .dataa(gnd), + .datab(data_num[16]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[15]~55 ), + .combout(\data_num[16]~56_combout ), + .cout(\data_num[16]~57 )); +// synopsys translate_off +defparam \data_num[16]~56 .lut_mask = 16'hC30C; +defparam \data_num[16]~56 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N10 +cycloneive_lcell_comb \data_num[17]~58 ( +// Equation(s): +// \data_num[17]~58_combout = (data_num[17] & (!\data_num[16]~57 )) # (!data_num[17] & ((\data_num[16]~57 ) # (GND))) +// \data_num[17]~59 = CARRY((!\data_num[16]~57 ) # (!data_num[17])) + + .dataa(data_num[17]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[16]~57 ), + .combout(\data_num[17]~58_combout ), + .cout(\data_num[17]~59 )); +// synopsys translate_off +defparam \data_num[17]~58 .lut_mask = 16'h5A5F; +defparam \data_num[17]~58 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N12 +cycloneive_lcell_comb \data_num[18]~60 ( +// Equation(s): +// \data_num[18]~60_combout = (data_num[18] & (\data_num[17]~59 $ (GND))) # (!data_num[18] & (!\data_num[17]~59 & VCC)) +// \data_num[18]~61 = CARRY((data_num[18] & !\data_num[17]~59 )) + + .dataa(data_num[18]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[17]~59 ), + .combout(\data_num[18]~60_combout ), + .cout(\data_num[18]~61 )); +// synopsys translate_off +defparam \data_num[18]~60 .lut_mask = 16'hA50A; +defparam \data_num[18]~60 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N14 +cycloneive_lcell_comb \data_num[19]~62 ( +// Equation(s): +// \data_num[19]~62_combout = (data_num[19] & (!\data_num[18]~61 )) # (!data_num[19] & ((\data_num[18]~61 ) # (GND))) +// \data_num[19]~63 = CARRY((!\data_num[18]~61 ) # (!data_num[19])) + + .dataa(gnd), + .datab(data_num[19]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[18]~61 ), + .combout(\data_num[19]~62_combout ), + .cout(\data_num[19]~63 )); +// synopsys translate_off +defparam \data_num[19]~62 .lut_mask = 16'h3C3F; +defparam \data_num[19]~62 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N16 +cycloneive_lcell_comb \data_num[20]~64 ( +// Equation(s): +// \data_num[20]~64_combout = (data_num[20] & (\data_num[19]~63 $ (GND))) # (!data_num[20] & (!\data_num[19]~63 & VCC)) +// \data_num[20]~65 = CARRY((data_num[20] & !\data_num[19]~63 )) + + .dataa(gnd), + .datab(data_num[20]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[19]~63 ), + .combout(\data_num[20]~64_combout ), + .cout(\data_num[20]~65 )); +// synopsys translate_off +defparam \data_num[20]~64 .lut_mask = 16'hC30C; +defparam \data_num[20]~64 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N18 +cycloneive_lcell_comb \data_num[21]~66 ( +// Equation(s): +// \data_num[21]~66_combout = (data_num[21] & (!\data_num[20]~65 )) # (!data_num[21] & ((\data_num[20]~65 ) # (GND))) +// \data_num[21]~67 = CARRY((!\data_num[20]~65 ) # (!data_num[21])) + + .dataa(gnd), + .datab(data_num[21]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[20]~65 ), + .combout(\data_num[21]~66_combout ), + .cout(\data_num[21]~67 )); +// synopsys translate_off +defparam \data_num[21]~66 .lut_mask = 16'h3C3F; +defparam \data_num[21]~66 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N20 +cycloneive_lcell_comb \data_num[22]~68 ( +// Equation(s): +// \data_num[22]~68_combout = (data_num[22] & (\data_num[21]~67 $ (GND))) # (!data_num[22] & (!\data_num[21]~67 & VCC)) +// \data_num[22]~69 = CARRY((data_num[22] & !\data_num[21]~67 )) + + .dataa(gnd), + .datab(data_num[22]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[21]~67 ), + .combout(\data_num[22]~68_combout ), + .cout(\data_num[22]~69 )); +// synopsys translate_off +defparam \data_num[22]~68 .lut_mask = 16'hC30C; +defparam \data_num[22]~68 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N22 +cycloneive_lcell_comb \data_num[23]~70 ( +// Equation(s): +// \data_num[23]~70_combout = data_num[23] $ (\data_num[22]~69 ) + + .dataa(data_num[23]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_num[22]~69 ), + .combout(\data_num[23]~70_combout ), + .cout()); +// synopsys translate_off +defparam \data_num[23]~70 .lut_mask = 16'h5A5A; +defparam \data_num[23]~70 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y26_N3 +dffeas \fifo_read_inst|cnt_read[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[1]~12_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N7 +dffeas \fifo_read_inst|cnt_read[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[3]~16_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N1 +dffeas \fifo_read_inst|cnt_read[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[0]~10_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N5 +dffeas \fifo_read_inst|cnt_read[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[2]~14_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N9 +dffeas \fifo_read_inst|cnt_read[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[4]~18_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N11 +dffeas \fifo_read_inst|cnt_read[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[5]~20_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N13 +dffeas \fifo_read_inst|cnt_read[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[6]~22_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N15 +dffeas \fifo_read_inst|cnt_read[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[7]~24_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N17 +dffeas \fifo_read_inst|cnt_read[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[8]~26_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N19 +dffeas \fifo_read_inst|cnt_read[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[9]~28_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N24 +cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( +// Equation(s): +// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_cnt [0] & (\uart_rx_inst|bit_flag~q $ (VCC))) # (!\uart_rx_inst|bit_cnt [0] & (\uart_rx_inst|bit_flag~q & VCC)) +// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_cnt [0] & \uart_rx_inst|bit_flag~q )) + + .dataa(\uart_rx_inst|bit_cnt [0]), + .datab(\uart_rx_inst|bit_flag~q ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|Add1~0_combout ), + .cout(\uart_rx_inst|Add1~1 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; +defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N28 +cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( +// Equation(s): +// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) +// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~3 ), + .combout(\uart_rx_inst|Add1~4_combout ), + .cout(\uart_rx_inst|Add1~5 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N30 +cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( +// Equation(s): +// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|Add1~5 $ (\uart_rx_inst|bit_cnt [3]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(\uart_rx_inst|Add1~5 ), + .combout(\uart_rx_inst|Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h0FF0; +defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N11 +dffeas \uart_rx_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N0 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[0]~10 ( +// Equation(s): +// \fifo_read_inst|cnt_read[0]~10_combout = (\fifo_read_inst|rd_en~q & (\fifo_read_inst|cnt_read [0] $ (VCC))) # (!\fifo_read_inst|rd_en~q & (\fifo_read_inst|cnt_read [0] & VCC)) +// \fifo_read_inst|cnt_read[0]~11 = CARRY((\fifo_read_inst|rd_en~q & \fifo_read_inst|cnt_read [0])) + + .dataa(\fifo_read_inst|rd_en~q ), + .datab(\fifo_read_inst|cnt_read [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|cnt_read[0]~10_combout ), + .cout(\fifo_read_inst|cnt_read[0]~11 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[0]~10 .lut_mask = 16'h6688; +defparam \fifo_read_inst|cnt_read[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N2 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[1]~12 ( +// Equation(s): +// \fifo_read_inst|cnt_read[1]~12_combout = (\fifo_read_inst|cnt_read [1] & (!\fifo_read_inst|cnt_read[0]~11 )) # (!\fifo_read_inst|cnt_read [1] & ((\fifo_read_inst|cnt_read[0]~11 ) # (GND))) +// \fifo_read_inst|cnt_read[1]~13 = CARRY((!\fifo_read_inst|cnt_read[0]~11 ) # (!\fifo_read_inst|cnt_read [1])) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [1]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[0]~11 ), + .combout(\fifo_read_inst|cnt_read[1]~12_combout ), + .cout(\fifo_read_inst|cnt_read[1]~13 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[1]~12 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|cnt_read[1]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N4 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[2]~14 ( +// Equation(s): +// \fifo_read_inst|cnt_read[2]~14_combout = (\fifo_read_inst|cnt_read [2] & (\fifo_read_inst|cnt_read[1]~13 $ (GND))) # (!\fifo_read_inst|cnt_read [2] & (!\fifo_read_inst|cnt_read[1]~13 & VCC)) +// \fifo_read_inst|cnt_read[2]~15 = CARRY((\fifo_read_inst|cnt_read [2] & !\fifo_read_inst|cnt_read[1]~13 )) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [2]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[1]~13 ), + .combout(\fifo_read_inst|cnt_read[2]~14_combout ), + .cout(\fifo_read_inst|cnt_read[2]~15 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[2]~14 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|cnt_read[2]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N6 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[3]~16 ( +// Equation(s): +// \fifo_read_inst|cnt_read[3]~16_combout = (\fifo_read_inst|cnt_read [3] & (!\fifo_read_inst|cnt_read[2]~15 )) # (!\fifo_read_inst|cnt_read [3] & ((\fifo_read_inst|cnt_read[2]~15 ) # (GND))) +// \fifo_read_inst|cnt_read[3]~17 = CARRY((!\fifo_read_inst|cnt_read[2]~15 ) # (!\fifo_read_inst|cnt_read [3])) + + .dataa(\fifo_read_inst|cnt_read [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[2]~15 ), + .combout(\fifo_read_inst|cnt_read[3]~16_combout ), + .cout(\fifo_read_inst|cnt_read[3]~17 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[3]~16 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|cnt_read[3]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N8 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[4]~18 ( +// Equation(s): +// \fifo_read_inst|cnt_read[4]~18_combout = (\fifo_read_inst|cnt_read [4] & (\fifo_read_inst|cnt_read[3]~17 $ (GND))) # (!\fifo_read_inst|cnt_read [4] & (!\fifo_read_inst|cnt_read[3]~17 & VCC)) +// \fifo_read_inst|cnt_read[4]~19 = CARRY((\fifo_read_inst|cnt_read [4] & !\fifo_read_inst|cnt_read[3]~17 )) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [4]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[3]~17 ), + .combout(\fifo_read_inst|cnt_read[4]~18_combout ), + .cout(\fifo_read_inst|cnt_read[4]~19 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[4]~18 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|cnt_read[4]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N10 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[5]~20 ( +// Equation(s): +// \fifo_read_inst|cnt_read[5]~20_combout = (\fifo_read_inst|cnt_read [5] & (!\fifo_read_inst|cnt_read[4]~19 )) # (!\fifo_read_inst|cnt_read [5] & ((\fifo_read_inst|cnt_read[4]~19 ) # (GND))) +// \fifo_read_inst|cnt_read[5]~21 = CARRY((!\fifo_read_inst|cnt_read[4]~19 ) # (!\fifo_read_inst|cnt_read [5])) + + .dataa(\fifo_read_inst|cnt_read [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[4]~19 ), + .combout(\fifo_read_inst|cnt_read[5]~20_combout ), + .cout(\fifo_read_inst|cnt_read[5]~21 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[5]~20 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|cnt_read[5]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N12 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[6]~22 ( +// Equation(s): +// \fifo_read_inst|cnt_read[6]~22_combout = (\fifo_read_inst|cnt_read [6] & (\fifo_read_inst|cnt_read[5]~21 $ (GND))) # (!\fifo_read_inst|cnt_read [6] & (!\fifo_read_inst|cnt_read[5]~21 & VCC)) +// \fifo_read_inst|cnt_read[6]~23 = CARRY((\fifo_read_inst|cnt_read [6] & !\fifo_read_inst|cnt_read[5]~21 )) + + .dataa(\fifo_read_inst|cnt_read [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[5]~21 ), + .combout(\fifo_read_inst|cnt_read[6]~22_combout ), + .cout(\fifo_read_inst|cnt_read[6]~23 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[6]~22 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|cnt_read[6]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N14 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[7]~24 ( +// Equation(s): +// \fifo_read_inst|cnt_read[7]~24_combout = (\fifo_read_inst|cnt_read [7] & (!\fifo_read_inst|cnt_read[6]~23 )) # (!\fifo_read_inst|cnt_read [7] & ((\fifo_read_inst|cnt_read[6]~23 ) # (GND))) +// \fifo_read_inst|cnt_read[7]~25 = CARRY((!\fifo_read_inst|cnt_read[6]~23 ) # (!\fifo_read_inst|cnt_read [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[6]~23 ), + .combout(\fifo_read_inst|cnt_read[7]~24_combout ), + .cout(\fifo_read_inst|cnt_read[7]~25 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[7]~24 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|cnt_read[7]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N16 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[8]~26 ( +// Equation(s): +// \fifo_read_inst|cnt_read[8]~26_combout = (\fifo_read_inst|cnt_read [8] & (\fifo_read_inst|cnt_read[7]~25 $ (GND))) # (!\fifo_read_inst|cnt_read [8] & (!\fifo_read_inst|cnt_read[7]~25 & VCC)) +// \fifo_read_inst|cnt_read[8]~27 = CARRY((\fifo_read_inst|cnt_read [8] & !\fifo_read_inst|cnt_read[7]~25 )) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [8]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[7]~25 ), + .combout(\fifo_read_inst|cnt_read[8]~26_combout ), + .cout(\fifo_read_inst|cnt_read[8]~27 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[8]~26 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|cnt_read[8]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N18 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[9]~28 ( +// Equation(s): +// \fifo_read_inst|cnt_read[9]~28_combout = \fifo_read_inst|cnt_read [9] $ (\fifo_read_inst|cnt_read[8]~27 ) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [9]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|cnt_read[8]~27 ), + .combout(\fifo_read_inst|cnt_read[9]~28_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[9]~28 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|cnt_read[9]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N10 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) +// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[3]~20 ), + .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_rx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X22_Y22_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y22_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y22_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [0])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [0]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0 .lut_mask = 16'h8C9D; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N13 +dffeas \uart_tx_inst|bit_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[0]~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( +// Equation(s): +// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b +// [4])) # (!\uart_tx_inst|bit_cnt [0] & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [3]))))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [4]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [3]), + .datad(\uart_tx_inst|bit_cnt [0]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hEE30; +defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N8 +cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( +// Equation(s): +// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|Mux0~0_combout & (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [6]) # (!\uart_tx_inst|bit_cnt [1])))) # (!\uart_tx_inst|Mux0~0_combout & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [5] & ((\uart_tx_inst|bit_cnt [1])))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [5]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [6]), + .datac(\uart_tx_inst|Mux0~0_combout ), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hCAF0; +defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \uart_tx_inst|tx~0 ( +// Equation(s): +// \uart_tx_inst|tx~0_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [2]))) # (!\uart_tx_inst|bit_cnt [1] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [0])))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [0]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~0 .lut_mask = 16'hA088; +defparam \uart_tx_inst|tx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \uart_tx_inst|tx~1 ( +// Equation(s): +// \uart_tx_inst|tx~1_combout = (\uart_tx_inst|tx~0_combout ) # ((!\uart_tx_inst|bit_cnt [0] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [1] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|tx~0_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [1]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~1 .lut_mask = 16'hDCCC; +defparam \uart_tx_inst|tx~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \uart_tx_inst|tx~2 ( +// Equation(s): +// \uart_tx_inst|tx~2_combout = (\uart_tx_inst|bit_flag~q & ((\uart_tx_inst|bit_cnt [2] & (\uart_tx_inst|Mux0~1_combout )) # (!\uart_tx_inst|bit_cnt [2] & ((\uart_tx_inst|tx~1_combout ))))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\uart_tx_inst|Mux0~1_combout ), + .datad(\uart_tx_inst|tx~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~2 .lut_mask = 16'hA280; +defparam \uart_tx_inst|tx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N27 +dffeas \uart_tx_inst|bit_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[3]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y21_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0 .lut_mask = 16'hFFAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0 .lut_mask = 16'h3111; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ) # (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1 .lut_mask = 16'hAFEF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0 .lut_mask = 16'h0CAE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( +// Equation(s): +// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(gnd), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h5AF0; +defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( +// Equation(s): +// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [0] & (\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|bit_cnt [1])))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h78F0; +defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~4 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[3]~4_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [3]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) + + .dataa(\uart_tx_inst|Add1~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3]~4 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0 .lut_mask = 16'h0400; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y22_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y22_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y20_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y20_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N29 +dffeas read_valid( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\read_valid~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\read_valid~q ), + .prn(vcc)); +// synopsys translate_off +defparam read_valid.is_wysiwyg = "true"; +defparam read_valid.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0 .lut_mask = 16'h000F; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout = (\read_valid~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & ((\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout )))) + + .dataa(\read_valid~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1 .lut_mask = 16'h8088; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0 .lut_mask = 16'hFAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[13] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N12 +cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( +// Equation(s): +// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [12] & \uart_tx_inst|baud_cnt [10]) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(gnd), + .datad(\uart_tx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hCC00; +defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N25 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N2 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout = (\fifo_read_inst|read_en_dly~q & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9] & !\fifo_read_inst|rd_en~q ))) + + .dataa(\fifo_read_inst|read_en_dly~q ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .lut_mask = 16'h0080; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N23 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N21 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N19 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N17 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N0 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] & +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .lut_mask = 16'h8000; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N15 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N11 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N26 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] & +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .lut_mask = 16'h8000; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] & +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .lut_mask = 16'h8000; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N13 +dffeas \fifo_read_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|Add2~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N28 +cycloneive_lcell_comb \fifo_read_inst|Equal1~0 ( +// Equation(s): +// \fifo_read_inst|Equal1~0_combout = (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] & (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .cin(gnd), + .combout(\fifo_read_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal1~0 .lut_mask = 16'h0001; +defparam \fifo_read_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N2 +cycloneive_lcell_comb \fifo_read_inst|Equal1~1 ( +// Equation(s): +// \fifo_read_inst|Equal1~1_combout = (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] & (\fifo_read_inst|Equal1~0_combout & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] & !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .datab(\fifo_read_inst|Equal1~0_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .cin(gnd), + .combout(\fifo_read_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal1~1 .lut_mask = 16'h0004; +defparam \fifo_read_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .lut_mask = 16'h50F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y23_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5 .lut_mask = 16'h9966; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y20_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2 .lut_mask = 16'h9696; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y26_N25 +dffeas \cnt_wait[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[15]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[15]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[15] .is_wysiwyg = "true"; +defparam \cnt_wait[15] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N27 +dffeas \cnt_wait[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[14]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[14]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[14] .is_wysiwyg = "true"; +defparam \cnt_wait[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N21 +dffeas \cnt_wait[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[13]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[13]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[13] .is_wysiwyg = "true"; +defparam \cnt_wait[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N23 +dffeas \cnt_wait[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[12]~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[12]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[12] .is_wysiwyg = "true"; +defparam \cnt_wait[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N8 +cycloneive_lcell_comb \Equal0~0 ( +// Equation(s): +// \Equal0~0_combout = (!cnt_wait[12] & (!cnt_wait[15] & (!cnt_wait[14] & !cnt_wait[13]))) + + .dataa(cnt_wait[12]), + .datab(cnt_wait[15]), + .datac(cnt_wait[14]), + .datad(cnt_wait[13]), + .cin(gnd), + .combout(\Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~0 .lut_mask = 16'h0001; +defparam \Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y26_N23 +dffeas \cnt_wait[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[9]~6_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[9]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[9] .is_wysiwyg = "true"; +defparam \cnt_wait[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N9 +dffeas \cnt_wait[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[11]~7_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[11]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[11] .is_wysiwyg = "true"; +defparam \cnt_wait[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N11 +dffeas \cnt_wait[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[10]~8_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[10]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[10] .is_wysiwyg = "true"; +defparam \cnt_wait[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N5 +dffeas \cnt_wait[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[8]~9_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[8]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[8] .is_wysiwyg = "true"; +defparam \cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N14 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (!cnt_wait[10] & (!cnt_wait[8] & (cnt_wait[9] & !cnt_wait[11]))) + + .dataa(cnt_wait[10]), + .datab(cnt_wait[8]), + .datac(cnt_wait[9]), + .datad(cnt_wait[11]), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0010; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y26_N3 +dffeas \cnt_wait[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[7]~10_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[7]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[7] .is_wysiwyg = "true"; +defparam \cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N13 +dffeas \cnt_wait[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[6]~11_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[6]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[6] .is_wysiwyg = "true"; +defparam \cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N15 +dffeas \cnt_wait[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[5]~12_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[5]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[5] .is_wysiwyg = "true"; +defparam \cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N17 +dffeas \cnt_wait[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[4]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[4]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[4] .is_wysiwyg = "true"; +defparam \cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N10 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (cnt_wait[6] & (cnt_wait[7] & (cnt_wait[5] & !cnt_wait[4]))) + + .dataa(cnt_wait[6]), + .datab(cnt_wait[7]), + .datac(cnt_wait[5]), + .datad(cnt_wait[4]), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0080; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y26_N5 +dffeas \cnt_wait[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[3]~14_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[3]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[3] .is_wysiwyg = "true"; +defparam \cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N7 +dffeas \cnt_wait[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[2]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[2]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[2] .is_wysiwyg = "true"; +defparam \cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N1 +dffeas \cnt_wait[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[1]~16_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[1]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[1] .is_wysiwyg = "true"; +defparam \cnt_wait[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N19 +dffeas \cnt_wait[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[0]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[0]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[0] .is_wysiwyg = "true"; +defparam \cnt_wait[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N28 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (!cnt_wait[0] & (cnt_wait[1] & (cnt_wait[3] & cnt_wait[2]))) + + .dataa(cnt_wait[0]), + .datab(cnt_wait[1]), + .datac(cnt_wait[3]), + .datad(cnt_wait[2]), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h4000; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N30 +cycloneive_lcell_comb \Equal0~4 ( +// Equation(s): +// \Equal0~4_combout = (\Equal0~2_combout & (\Equal0~3_combout & (\Equal0~0_combout & \Equal0~1_combout ))) + + .dataa(\Equal0~2_combout ), + .datab(\Equal0~3_combout ), + .datac(\Equal0~0_combout ), + .datad(\Equal0~1_combout ), + .cin(gnd), + .combout(\Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~4 .lut_mask = 16'h8000; +defparam \Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N16 +cycloneive_lcell_comb \read_valid~0 ( +// Equation(s): +// \read_valid~0_combout = (\Equal0~4_combout ) # ((\read_valid~q & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ) # (!\Equal2~1_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\Equal0~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .datad(\read_valid~q ), + .cin(gnd), + .combout(\read_valid~0_combout ), + .cout()); +// synopsys translate_off +defparam \read_valid~0 .lut_mask = 16'hFDCC; +defparam \read_valid~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N28 +cycloneive_lcell_comb \read_valid~1 ( +// Equation(s): +// \read_valid~1_combout = (\read_valid~0_combout ) # ((\read_valid~q & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ) # (!\Equal2~0_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .datab(\Equal2~0_combout ), + .datac(\read_valid~q ), + .datad(\read_valid~0_combout ), + .cin(gnd), + .combout(\read_valid~1_combout ), + .cout()); +// synopsys translate_off +defparam \read_valid~1 .lut_mask = 16'hFFB0; +defparam \read_valid~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0 .lut_mask = 16'hECFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk +// [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3] $ (((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0 .lut_mask = 16'h6AAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2 .lut_mask = 16'hC0C0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N10 +cycloneive_lcell_comb \fifo_read_inst|Equal1~2 ( +// Equation(s): +// \fifo_read_inst|Equal1~2_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] & \fifo_read_inst|Equal1~1_combout )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datac(gnd), + .datad(\fifo_read_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\fifo_read_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal1~2 .lut_mask = 16'h2200; +defparam \fifo_read_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N2 +cycloneive_lcell_comb \fifo_read_inst|Equal5~1 ( +// Equation(s): +// \fifo_read_inst|Equal5~1_combout = (\fifo_read_inst|baud_cnt [11] & (!\fifo_read_inst|baud_cnt [10] & (\fifo_read_inst|baud_cnt [9] & !\fifo_read_inst|baud_cnt [6]))) + + .dataa(\fifo_read_inst|baud_cnt [11]), + .datab(\fifo_read_inst|baud_cnt [10]), + .datac(\fifo_read_inst|baud_cnt [9]), + .datad(\fifo_read_inst|baud_cnt [6]), + .cin(gnd), + .combout(\fifo_read_inst|Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal5~1 .lut_mask = 16'h0020; +defparam \fifo_read_inst|Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h4182; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'hF000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'hC000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout +// )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8 .lut_mask = 16'hCA0A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'h4812; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'h8008; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h2814; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'h8200; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout )) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'hF5A0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h2814; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'hE0C2; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h0004; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N0 +cycloneive_lcell_comb \Equal1~0 ( +// Equation(s): +// \Equal1~0_combout = (data_num[2]) # (((data_num[0]) # (!data_num[1])) # (!data_num[3])) + + .dataa(data_num[2]), + .datab(data_num[3]), + .datac(data_num[0]), + .datad(data_num[1]), + .cin(gnd), + .combout(\Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~0 .lut_mask = 16'hFBFF; +defparam \Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N2 +cycloneive_lcell_comb \Equal1~1 ( +// Equation(s): +// \Equal1~1_combout = (data_num[6]) # ((data_num[5]) # ((data_num[7]) # (data_num[4]))) + + .dataa(data_num[6]), + .datab(data_num[5]), + .datac(data_num[7]), + .datad(data_num[4]), + .cin(gnd), + .combout(\Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~1 .lut_mask = 16'hFFFE; +defparam \Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N4 +cycloneive_lcell_comb \Equal1~2 ( +// Equation(s): +// \Equal1~2_combout = (data_num[11]) # ((data_num[10]) # ((data_num[9]) # (data_num[8]))) + + .dataa(data_num[11]), + .datab(data_num[10]), + .datac(data_num[9]), + .datad(data_num[8]), + .cin(gnd), + .combout(\Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~2 .lut_mask = 16'hFFFE; +defparam \Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N24 +cycloneive_lcell_comb \Equal1~3 ( +// Equation(s): +// \Equal1~3_combout = (data_num[15]) # ((data_num[13]) # ((data_num[14]) # (data_num[12]))) + + .dataa(data_num[15]), + .datab(data_num[13]), + .datac(data_num[14]), + .datad(data_num[12]), + .cin(gnd), + .combout(\Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~3 .lut_mask = 16'hFFFE; +defparam \Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N6 +cycloneive_lcell_comb \Equal1~4 ( +// Equation(s): +// \Equal1~4_combout = (\Equal1~3_combout ) # ((\Equal1~1_combout ) # ((\Equal1~2_combout ) # (\Equal1~0_combout ))) + + .dataa(\Equal1~3_combout ), + .datab(\Equal1~1_combout ), + .datac(\Equal1~2_combout ), + .datad(\Equal1~0_combout ), + .cin(gnd), + .combout(\Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~4 .lut_mask = 16'hFFFE; +defparam \Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N26 +cycloneive_lcell_comb \Equal1~5 ( +// Equation(s): +// \Equal1~5_combout = (data_num[18]) # ((data_num[19]) # ((data_num[16]) # (data_num[17]))) + + .dataa(data_num[18]), + .datab(data_num[19]), + .datac(data_num[16]), + .datad(data_num[17]), + .cin(gnd), + .combout(\Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~5 .lut_mask = 16'hFFFE; +defparam \Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N28 +cycloneive_lcell_comb \Equal1~6 ( +// Equation(s): +// \Equal1~6_combout = (data_num[22]) # ((data_num[21]) # ((data_num[23]) # (data_num[20]))) + + .dataa(data_num[22]), + .datab(data_num[21]), + .datac(data_num[23]), + .datad(data_num[20]), + .cin(gnd), + .combout(\Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~6 .lut_mask = 16'hFFFE; +defparam \Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N18 +cycloneive_lcell_comb \cnt_wait[8]~0 ( +// Equation(s): +// \cnt_wait[8]~0_combout = (!\Equal0~4_combout & ((\Equal1~4_combout ) # ((\Equal1~5_combout ) # (\Equal1~6_combout )))) + + .dataa(\Equal1~4_combout ), + .datab(\Equal0~4_combout ), + .datac(\Equal1~5_combout ), + .datad(\Equal1~6_combout ), + .cin(gnd), + .combout(\cnt_wait[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[8]~0 .lut_mask = 16'h3332; +defparam \cnt_wait[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N12 +cycloneive_lcell_comb \cnt_wait[15]~1 ( +// Equation(s): +// \cnt_wait[15]~1_combout = (\Equal1~4_combout ) # ((\Equal0~4_combout ) # ((\Equal1~5_combout ) # (\Equal1~6_combout ))) + + .dataa(\Equal1~4_combout ), + .datab(\Equal0~4_combout ), + .datac(\Equal1~5_combout ), + .datad(\Equal1~6_combout ), + .cin(gnd), + .combout(\cnt_wait[15]~1_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[15]~1 .lut_mask = 16'hFFFE; +defparam \cnt_wait[15]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N24 +cycloneive_lcell_comb \cnt_wait[15]~2 ( +// Equation(s): +// \cnt_wait[15]~2_combout = (\Add1~30_combout & (((\cnt_wait[8]~0_combout & cnt_wait[15])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~30_combout & (\cnt_wait[8]~0_combout & (cnt_wait[15]))) + + .dataa(\Add1~30_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[15]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[15]~2_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[15]~2 .lut_mask = 16'hC0EA; +defparam \cnt_wait[15]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N26 +cycloneive_lcell_comb \cnt_wait[14]~3 ( +// Equation(s): +// \cnt_wait[14]~3_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[14] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~28_combout ) # ((cnt_wait[14] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~28_combout ), + .datac(cnt_wait[14]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[14]~3_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[14]~3 .lut_mask = 16'hF444; +defparam \cnt_wait[14]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N20 +cycloneive_lcell_comb \cnt_wait[13]~4 ( +// Equation(s): +// \cnt_wait[13]~4_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[13] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~26_combout ) # ((cnt_wait[13] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~26_combout ), + .datac(cnt_wait[13]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[13]~4_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[13]~4 .lut_mask = 16'hF444; +defparam \cnt_wait[13]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N22 +cycloneive_lcell_comb \cnt_wait[12]~5 ( +// Equation(s): +// \cnt_wait[12]~5_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[12] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~24_combout ) # ((cnt_wait[12] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~24_combout ), + .datac(cnt_wait[12]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[12]~5_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[12]~5 .lut_mask = 16'hF444; +defparam \cnt_wait[12]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N22 +cycloneive_lcell_comb \cnt_wait[9]~6 ( +// Equation(s): +// \cnt_wait[9]~6_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[9] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~18_combout ) # ((cnt_wait[9] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~18_combout ), + .datac(cnt_wait[9]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[9]~6_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[9]~6 .lut_mask = 16'hF444; +defparam \cnt_wait[9]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N8 +cycloneive_lcell_comb \cnt_wait[11]~7 ( +// Equation(s): +// \cnt_wait[11]~7_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[11] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~22_combout ) # ((cnt_wait[11] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~22_combout ), + .datac(cnt_wait[11]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[11]~7_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[11]~7 .lut_mask = 16'hF444; +defparam \cnt_wait[11]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N10 +cycloneive_lcell_comb \cnt_wait[10]~8 ( +// Equation(s): +// \cnt_wait[10]~8_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[10] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~20_combout ) # ((cnt_wait[10] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~20_combout ), + .datac(cnt_wait[10]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[10]~8_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[10]~8 .lut_mask = 16'hF444; +defparam \cnt_wait[10]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N4 +cycloneive_lcell_comb \cnt_wait[8]~9 ( +// Equation(s): +// \cnt_wait[8]~9_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[8] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~16_combout ) # ((cnt_wait[8] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~16_combout ), + .datac(cnt_wait[8]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[8]~9_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[8]~9 .lut_mask = 16'hF444; +defparam \cnt_wait[8]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N2 +cycloneive_lcell_comb \cnt_wait[7]~10 ( +// Equation(s): +// \cnt_wait[7]~10_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[7] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~14_combout ) # ((cnt_wait[7] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~14_combout ), + .datac(cnt_wait[7]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[7]~10_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[7]~10 .lut_mask = 16'hF444; +defparam \cnt_wait[7]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N12 +cycloneive_lcell_comb \cnt_wait[6]~11 ( +// Equation(s): +// \cnt_wait[6]~11_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[6] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~12_combout ) # ((cnt_wait[6] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~12_combout ), + .datac(cnt_wait[6]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[6]~11_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[6]~11 .lut_mask = 16'hF444; +defparam \cnt_wait[6]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N14 +cycloneive_lcell_comb \cnt_wait[5]~12 ( +// Equation(s): +// \cnt_wait[5]~12_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[5] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~10_combout ) # ((cnt_wait[5] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~10_combout ), + .datac(cnt_wait[5]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[5]~12_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[5]~12 .lut_mask = 16'hF444; +defparam \cnt_wait[5]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N16 +cycloneive_lcell_comb \cnt_wait[4]~13 ( +// Equation(s): +// \cnt_wait[4]~13_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[4] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~8_combout ) # ((cnt_wait[4] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~8_combout ), + .datac(cnt_wait[4]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[4]~13 .lut_mask = 16'hF444; +defparam \cnt_wait[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N4 +cycloneive_lcell_comb \cnt_wait[3]~14 ( +// Equation(s): +// \cnt_wait[3]~14_combout = (\Add1~6_combout & (((\cnt_wait[8]~0_combout & cnt_wait[3])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~6_combout & (\cnt_wait[8]~0_combout & (cnt_wait[3]))) + + .dataa(\Add1~6_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[3]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[3]~14 .lut_mask = 16'hC0EA; +defparam \cnt_wait[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N6 +cycloneive_lcell_comb \cnt_wait[2]~15 ( +// Equation(s): +// \cnt_wait[2]~15_combout = (\Add1~4_combout & (((\cnt_wait[8]~0_combout & cnt_wait[2])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~4_combout & (\cnt_wait[8]~0_combout & (cnt_wait[2]))) + + .dataa(\Add1~4_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[2]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[2]~15_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[2]~15 .lut_mask = 16'hC0EA; +defparam \cnt_wait[2]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N0 +cycloneive_lcell_comb \cnt_wait[1]~16 ( +// Equation(s): +// \cnt_wait[1]~16_combout = (\Add1~2_combout & (((\cnt_wait[8]~0_combout & cnt_wait[1])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~2_combout & (\cnt_wait[8]~0_combout & (cnt_wait[1]))) + + .dataa(\Add1~2_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[1]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[1]~16 .lut_mask = 16'hC0EA; +defparam \cnt_wait[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N18 +cycloneive_lcell_comb \cnt_wait[0]~17 ( +// Equation(s): +// \cnt_wait[0]~17_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[0] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~0_combout ) # ((cnt_wait[0] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~0_combout ), + .datac(cnt_wait[0]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[0]~17 .lut_mask = 16'hF444; +defparam \cnt_wait[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h4812; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h0084; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ) # +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout +// & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'hAAEA; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h4812; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h4182; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout +// )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'hB830; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h0004; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N1 +dffeas \fifo_read_inst|rd_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|rd_flag~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|rd_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|rd_flag .is_wysiwyg = "true"; +defparam \fifo_read_inst|rd_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N30 +cycloneive_lcell_comb \fifo_read_inst|Equal4~2 ( +// Equation(s): +// \fifo_read_inst|Equal4~2_combout = (!\fifo_read_inst|baud_cnt [11] & (\fifo_read_inst|baud_cnt [10] & (!\fifo_read_inst|baud_cnt [9] & \fifo_read_inst|baud_cnt [6]))) + + .dataa(\fifo_read_inst|baud_cnt [11]), + .datab(\fifo_read_inst|baud_cnt [10]), + .datac(\fifo_read_inst|baud_cnt [9]), + .datad(\fifo_read_inst|baud_cnt [6]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~2 .lut_mask = 16'h0400; +defparam \fifo_read_inst|Equal4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout & ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0 .lut_mask = 16'h1030; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N23 +dffeas \uart_rx_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N28 +cycloneive_lcell_comb \fifo_read_inst|Equal2~0 ( +// Equation(s): +// \fifo_read_inst|Equal2~0_combout = (\fifo_read_inst|cnt_read [3] & (\fifo_read_inst|cnt_read [1] & (!\fifo_read_inst|cnt_read [2] & !\fifo_read_inst|cnt_read [0]))) + + .dataa(\fifo_read_inst|cnt_read [3]), + .datab(\fifo_read_inst|cnt_read [1]), + .datac(\fifo_read_inst|cnt_read [2]), + .datad(\fifo_read_inst|cnt_read [0]), + .cin(gnd), + .combout(\fifo_read_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal2~0 .lut_mask = 16'h0008; +defparam \fifo_read_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N30 +cycloneive_lcell_comb \fifo_read_inst|Equal2~1 ( +// Equation(s): +// \fifo_read_inst|Equal2~1_combout = (!\fifo_read_inst|cnt_read [6] & (!\fifo_read_inst|cnt_read [7] & (!\fifo_read_inst|cnt_read [4] & !\fifo_read_inst|cnt_read [5]))) + + .dataa(\fifo_read_inst|cnt_read [6]), + .datab(\fifo_read_inst|cnt_read [7]), + .datac(\fifo_read_inst|cnt_read [4]), + .datad(\fifo_read_inst|cnt_read [5]), + .cin(gnd), + .combout(\fifo_read_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal2~1 .lut_mask = 16'h0001; +defparam \fifo_read_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N24 +cycloneive_lcell_comb \fifo_read_inst|Equal2~2 ( +// Equation(s): +// \fifo_read_inst|Equal2~2_combout = (\fifo_read_inst|Equal2~0_combout & (!\fifo_read_inst|cnt_read [9] & (\fifo_read_inst|Equal2~1_combout & !\fifo_read_inst|cnt_read [8]))) + + .dataa(\fifo_read_inst|Equal2~0_combout ), + .datab(\fifo_read_inst|cnt_read [9]), + .datac(\fifo_read_inst|Equal2~1_combout ), + .datad(\fifo_read_inst|cnt_read [8]), + .cin(gnd), + .combout(\fifo_read_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal2~2 .lut_mask = 16'h0020; +defparam \fifo_read_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N0 +cycloneive_lcell_comb \fifo_read_inst|rd_flag~0 ( +// Equation(s): +// \fifo_read_inst|rd_flag~0_combout = (!\fifo_read_inst|Equal2~2_combout & ((\fifo_read_inst|rd_flag~q ) # ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] & +// \fifo_read_inst|Equal1~2_combout )))) + + .dataa(\fifo_read_inst|Equal2~2_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datac(\fifo_read_inst|rd_flag~q ), + .datad(\fifo_read_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\fifo_read_inst|rd_flag~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|rd_flag~0 .lut_mask = 16'h5450; +defparam \fifo_read_inst|rd_flag~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N22 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~1_combout = (\uart_rx_inst|Add1~0_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_flag~q )) # (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(\uart_rx_inst|bit_cnt [3]), + .datab(\uart_rx_inst|Add1~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h4CCC; +defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N7 +dffeas \uart_rx_inst|work_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_rx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y24_N7 +dffeas \uart_rx_inst|start_nedge ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|start_nedge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; +defparam \uart_rx_inst|start_nedge .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N6 +cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( +// Equation(s): +// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) + + .dataa(gnd), + .datab(\uart_rx_inst|start_nedge~q ), + .datac(\uart_rx_inst|work_en~q ), + .datad(\uart_rx_inst|always4~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hCCFC; +defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N6 +cycloneive_lcell_comb \uart_rx_inst|always3~0 ( +// Equation(s): +// \uart_rx_inst|always3~0_combout = (\uart_rx_inst|rx_reg2~q & !\uart_rx_inst|rx_reg3~q ) + + .dataa(gnd), + .datab(\uart_rx_inst|rx_reg2~q ), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg3~q ), + .cin(gnd), + .combout(\uart_rx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always3~0 .lut_mask = 16'h00CC; +defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|bit_flag~q & \uart_tx_inst|work_en~q ))))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h1230; +defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y9_N16 +cycloneive_io_obuf \tx~output ( + .i(!\uart_tx_inst|tx~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tx), + .obar()); +// synopsys translate_off +defparam \tx~output .bus_hold = "false"; +defparam \tx~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y29_N30 +cycloneive_io_obuf \sdram_clk~output ( + .i(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_clk), + .obar()); +// synopsys translate_off +defparam \sdram_clk~output .bus_hold = "false"; +defparam \sdram_clk~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y13_N23 +cycloneive_io_obuf \sdram_cke~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_cke), + .obar()); +// synopsys translate_off +defparam \sdram_cke~output .bus_hold = "false"; +defparam \sdram_cke~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N9 +cycloneive_io_obuf \sdram_cs_n~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_cs_n), + .obar()); +// synopsys translate_off +defparam \sdram_cs_n~output .bus_hold = "false"; +defparam \sdram_cs_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y29_N16 +cycloneive_io_obuf \sdram_cas_n~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_cas_n), + .obar()); +// synopsys translate_off +defparam \sdram_cas_n~output .bus_hold = "false"; +defparam \sdram_cas_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N16 +cycloneive_io_obuf \sdram_ras_n~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_ras_n), + .obar()); +// synopsys translate_off +defparam \sdram_ras_n~output .bus_hold = "false"; +defparam \sdram_ras_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y29_N9 +cycloneive_io_obuf \sdram_we_n~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_we_n), + .obar()); +// synopsys translate_off +defparam \sdram_we_n~output .bus_hold = "false"; +defparam \sdram_we_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N16 +cycloneive_io_obuf \sdram_ba[0]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_ba[0]), + .obar()); +// synopsys translate_off +defparam \sdram_ba[0]~output .bus_hold = "false"; +defparam \sdram_ba[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y29_N2 +cycloneive_io_obuf \sdram_ba[1]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_ba[1]), + .obar()); +// synopsys translate_off +defparam \sdram_ba[1]~output .bus_hold = "false"; +defparam \sdram_ba[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N9 +cycloneive_io_obuf \sdram_addr[0]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[0]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[0]~output .bus_hold = "false"; +defparam \sdram_addr[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y27_N16 +cycloneive_io_obuf \sdram_addr[1]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[1]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[1]~output .bus_hold = "false"; +defparam \sdram_addr[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y27_N9 +cycloneive_io_obuf \sdram_addr[2]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[2]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[2]~output .bus_hold = "false"; +defparam \sdram_addr[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y26_N23 +cycloneive_io_obuf \sdram_addr[3]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[3]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[3]~output .bus_hold = "false"; +defparam \sdram_addr[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y26_N16 +cycloneive_io_obuf \sdram_addr[4]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[4]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[4]~output .bus_hold = "false"; +defparam \sdram_addr[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y24_N16 +cycloneive_io_obuf \sdram_addr[5]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[5]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[5]~output .bus_hold = "false"; +defparam \sdram_addr[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y23_N2 +cycloneive_io_obuf \sdram_addr[6]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[6]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[6]~output .bus_hold = "false"; +defparam \sdram_addr[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y24_N23 +cycloneive_io_obuf \sdram_addr[7]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[7]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[7]~output .bus_hold = "false"; +defparam \sdram_addr[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N16 +cycloneive_io_obuf \sdram_addr[8]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[8]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[8]~output .bus_hold = "false"; +defparam \sdram_addr[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N16 +cycloneive_io_obuf \sdram_addr[9]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[9]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[9]~output .bus_hold = "false"; +defparam \sdram_addr[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N2 +cycloneive_io_obuf \sdram_addr[10]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[10]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[10]~output .bus_hold = "false"; +defparam \sdram_addr[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N23 +cycloneive_io_obuf \sdram_addr[11]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[11]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[11]~output .bus_hold = "false"; +defparam \sdram_addr[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y13_N16 +cycloneive_io_obuf \sdram_addr[12]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[12]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[12]~output .bus_hold = "false"; +defparam \sdram_addr[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N2 +cycloneive_io_obuf \sdram_dqm[0]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dqm[0]), + .obar()); +// synopsys translate_off +defparam \sdram_dqm[0]~output .bus_hold = "false"; +defparam \sdram_dqm[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y20_N2 +cycloneive_io_obuf \sdram_dqm[1]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dqm[1]), + .obar()); +// synopsys translate_off +defparam \sdram_dqm[1]~output .bus_hold = "false"; +defparam \sdram_dqm[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N9 +cycloneive_io_obuf \sdram_dq[0]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[0]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[0]~output .bus_hold = "false"; +defparam \sdram_dq[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N2 +cycloneive_io_obuf \sdram_dq[1]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[1]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[1]~output .bus_hold = "false"; +defparam \sdram_dq[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y29_N2 +cycloneive_io_obuf \sdram_dq[2]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[2]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[2]~output .bus_hold = "false"; +defparam \sdram_dq[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y29_N30 +cycloneive_io_obuf \sdram_dq[3]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[3]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[3]~output .bus_hold = "false"; +defparam \sdram_dq[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y29_N23 +cycloneive_io_obuf \sdram_dq[4]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[4]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[4]~output .bus_hold = "false"; +defparam \sdram_dq[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y29_N9 +cycloneive_io_obuf \sdram_dq[5]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[5]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[5]~output .bus_hold = "false"; +defparam \sdram_dq[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N16 +cycloneive_io_obuf \sdram_dq[6]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[6]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[6]~output .bus_hold = "false"; +defparam \sdram_dq[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N23 +cycloneive_io_obuf \sdram_dq[7]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[7]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[7]~output .bus_hold = "false"; +defparam \sdram_dq[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y20_N9 +cycloneive_io_obuf \sdram_dq[8]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [8]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[8]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[8]~output .bus_hold = "false"; +defparam \sdram_dq[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N30 +cycloneive_io_obuf \sdram_dq[9]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [9]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[9]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[9]~output .bus_hold = "false"; +defparam \sdram_dq[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y25_N2 +cycloneive_io_obuf \sdram_dq[10]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [10]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[10]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[10]~output .bus_hold = "false"; +defparam \sdram_dq[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y26_N9 +cycloneive_io_obuf \sdram_dq[11]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [11]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[11]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[11]~output .bus_hold = "false"; +defparam \sdram_dq[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y23_N9 +cycloneive_io_obuf \sdram_dq[12]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [12]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[12]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[12]~output .bus_hold = "false"; +defparam \sdram_dq[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N9 +cycloneive_io_obuf \sdram_dq[13]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [13]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[13]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[13]~output .bus_hold = "false"; +defparam \sdram_dq[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N23 +cycloneive_io_obuf \sdram_dq[14]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [14]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[14]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[14]~output .bus_hold = "false"; +defparam \sdram_dq[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N2 +cycloneive_io_obuf \sdram_dq[15]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [15]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[15]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[15]~output .bus_hold = "false"; +defparam \sdram_dq[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N2 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) +// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_rx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 4; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 4; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "c2"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "-833"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 4; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 6891; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N24 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X27_Y26_N25 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N26 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked )) # (!\sys_rst_n~input_o ) + + .dataa(\sys_rst_n~input_o ), + .datab(gnd), + .datac(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h5FFF; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G17 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N6 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) +// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_rx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[1]~16 ), + .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_rx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N8 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[2]~18 ), + .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_rx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N9 +dffeas \uart_rx_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N12 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) + + .dataa(\uart_rx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[4]~22 ), + .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_rx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N13 +dffeas \uart_rx_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N30 +cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( +// Equation(s): +// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt [3] & !\uart_rx_inst|baud_cnt [5]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [2]), + .datac(\uart_rx_inst|baud_cnt [3]), + .datad(\uart_rx_inst|baud_cnt [5]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0008; +defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N14 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) +// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[5]~24 ), + .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_rx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N15 +dffeas \uart_rx_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N16 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[6]~26 ), + .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_rx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N17 +dffeas \uart_rx_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N18 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) +// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[7]~28 ), + .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_rx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N19 +dffeas \uart_rx_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N0 +cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( +// Equation(s): +// \uart_rx_inst|Equal1~0_combout = (\uart_rx_inst|baud_cnt [0] & (!\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt [1] & !\uart_rx_inst|baud_cnt [7]))) + + .dataa(\uart_rx_inst|baud_cnt [0]), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(\uart_rx_inst|baud_cnt [1]), + .datad(\uart_rx_inst|baud_cnt [7]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N20 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[8]~30 ), + .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_rx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N21 +dffeas \uart_rx_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N22 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) +// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[9]~32 ), + .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_rx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N24 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[10]~34 ), + .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_rx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N25 +dffeas \uart_rx_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N8 +cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( +// Equation(s): +// \uart_rx_inst|Equal1~2_combout = (!\uart_rx_inst|baud_cnt [9] & \uart_rx_inst|baud_cnt [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|baud_cnt [9]), + .datad(\uart_rx_inst|baud_cnt [6]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0F00; +defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N23 +dffeas \uart_rx_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N2 +cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( +// Equation(s): +// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|baud_cnt [12] & (!\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|Equal1~2_combout & \uart_rx_inst|baud_cnt [10]))) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|Equal1~2_combout ), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h2000; +defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N12 +cycloneive_lcell_comb \uart_rx_inst|always5~0 ( +// Equation(s): +// \uart_rx_inst|always5~0_combout = ((\uart_rx_inst|Equal1~1_combout & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal1~3_combout ))) # (!\uart_rx_inst|work_en~q ) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|Equal1~1_combout ), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal1~3_combout ), + .cin(gnd), + .combout(\uart_rx_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always5~0 .lut_mask = 16'hD555; +defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N3 +dffeas \uart_rx_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N4 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[0]~14 ), + .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_rx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N5 +dffeas \uart_rx_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y25_N7 +dffeas \uart_rx_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N28 +cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( +// Equation(s): +// \uart_rx_inst|Equal2~0_combout = (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt [3] & \uart_rx_inst|baud_cnt [5]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [2]), + .datac(\uart_rx_inst|baud_cnt [3]), + .datad(\uart_rx_inst|baud_cnt [5]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h1000; +defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N26 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt [12] $ (!\uart_rx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_rx_inst|baud_cnt[11]~36 ), + .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N27 +dffeas \uart_rx_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N20 +cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( +// Equation(s): +// \uart_rx_inst|Equal2~1_combout = (!\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|baud_cnt [9] & !\uart_rx_inst|baud_cnt [10]))) + + .dataa(\uart_rx_inst|baud_cnt [6]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [9]), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0040; +defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N4 +cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( +// Equation(s): +// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal1~0_combout & (\uart_rx_inst|Equal2~0_combout & (!\uart_rx_inst|baud_cnt [12] & \uart_rx_inst|Equal2~1_combout ))) + + .dataa(\uart_rx_inst|Equal1~0_combout ), + .datab(\uart_rx_inst|Equal2~0_combout ), + .datac(\uart_rx_inst|baud_cnt [12]), + .datad(\uart_rx_inst|Equal2~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h0800; +defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N5 +dffeas \uart_rx_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Equal2~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N26 +cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( +// Equation(s): +// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) +// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~1 ), + .combout(\uart_rx_inst|Add1~2_combout ), + .cout(\uart_rx_inst|Add1~3 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y25_N29 +dffeas \uart_rx_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y25_N27 +dffeas \uart_rx_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N0 +cycloneive_lcell_comb \uart_rx_inst|always4~0 ( +// Equation(s): +// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [0] & (!\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [0]), + .datab(\uart_rx_inst|bit_cnt [2]), + .datac(\uart_rx_inst|bit_cnt [1]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0101; +defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N16 +cycloneive_lcell_comb \uart_rx_inst|always4~1 ( +// Equation(s): +// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|bit_cnt [3] & (\uart_rx_inst|always4~0_combout & \uart_rx_inst|bit_flag~q )) + + .dataa(\uart_rx_inst|bit_cnt [3]), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~1 .lut_mask = 16'h8080; +defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N17 +dffeas \uart_rx_inst|rx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always4~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_flag .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N1 +dffeas \uart_rx_inst|po_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_flag~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h5A5A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hF0B4; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0800; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h0100; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .lut_mask = 16'hC3F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h3CC3; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h0200; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0004; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hB4F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4 .lut_mask = 16'h0001; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6 .lut_mask = 16'h0100; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8 .lut_mask = 16'h1000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5 .lut_mask = 16'h9696; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y22_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y22_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0040; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hE1F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'h2000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8 .lut_mask = 16'h000F; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'h8008; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'h8008; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'h0F33; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ) # (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q )))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ) # +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hEEE0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X16_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y20_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [0]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [0])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1 .lut_mask = 16'h00BB; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y20_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|LessThan2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ) # ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ) # +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ) # (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~0 .lut_mask = 16'hFFFE; +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|LessThan2~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ) # ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ) # (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~1 .lut_mask = 16'hFFC8; +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .lut_mask = 16'h0010; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 $ (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [9])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [9]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [9]), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18 .lut_mask = 16'h5AA5; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & ((\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ) # ((\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ) # +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0 .lut_mask = 16'hAAA8; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y20_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h5A5A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hF0B4; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hD2F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h0040; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .lut_mask = 16'hD2D2; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1] $ (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h3CC3; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0020; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hD2F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & (\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4 .lut_mask = 16'h0500; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9] $ (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28 .lut_mask = 16'h5A5A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3 .lut_mask = 16'h000F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5 .lut_mask = 16'h2000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0 .lut_mask = 16'hCCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [5] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2 .lut_mask = 16'h0001; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ) # ((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0 .lut_mask = 16'hFF30; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1 .lut_mask = 16'hC0C0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0 .lut_mask = 16'h00F8; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16 .lut_mask = 16'h0088; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0 .lut_mask = 16'hCCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1 .lut_mask = 16'hCC00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2 .lut_mask = 16'hEEFF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [0] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0 .lut_mask = 16'h00FE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3 .lut_mask = 16'hFFEC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y23_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y23_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [1]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]) # (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1 .lut_mask = 16'h5776; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hF0D2; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h78F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0100; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0010; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .lut_mask = 16'hA5F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2] $ (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h3CC3; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0008; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h0200; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'hB4F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'hFCFF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1 .lut_mask = 16'hF05A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout +// )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'hAC0C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout )))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'h59FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h0021; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout & +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout +// )) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'h1333; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y24_N25 +dffeas \fifo_read_inst|read_en_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\fifo_read_inst|read_en~q ), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_en_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_en_dly .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_en_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout = (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q & \fifo_read_inst|read_en_dly~q ) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datab(gnd), + .datac(\fifo_read_inst|read_en_dly~q ), + .datad(gnd), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq .lut_mask = 16'h5050; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N6 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] $ (((VCC) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT = CARRY(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] $ +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0 .lut_mask = 16'h5599; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y24_N7 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N8 +cycloneive_lcell_comb \fifo_read_inst|Add2~0 ( +// Equation(s): +// \fifo_read_inst|Add2~0_combout = (\fifo_read_inst|bit_flag~q & (\fifo_read_inst|bit_cnt [0] $ (VCC))) # (!\fifo_read_inst|bit_flag~q & (\fifo_read_inst|bit_cnt [0] & VCC)) +// \fifo_read_inst|Add2~1 = CARRY((\fifo_read_inst|bit_flag~q & \fifo_read_inst|bit_cnt [0])) + + .dataa(\fifo_read_inst|bit_flag~q ), + .datab(\fifo_read_inst|bit_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|Add2~0_combout ), + .cout(\fifo_read_inst|Add2~1 )); +// synopsys translate_off +defparam \fifo_read_inst|Add2~0 .lut_mask = 16'h6688; +defparam \fifo_read_inst|Add2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N9 +dffeas \fifo_read_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|Add2~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N10 +cycloneive_lcell_comb \fifo_read_inst|Add2~2 ( +// Equation(s): +// \fifo_read_inst|Add2~2_combout = (\fifo_read_inst|bit_cnt [1] & (!\fifo_read_inst|Add2~1 )) # (!\fifo_read_inst|bit_cnt [1] & ((\fifo_read_inst|Add2~1 ) # (GND))) +// \fifo_read_inst|Add2~3 = CARRY((!\fifo_read_inst|Add2~1 ) # (!\fifo_read_inst|bit_cnt [1])) + + .dataa(\fifo_read_inst|bit_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|Add2~1 ), + .combout(\fifo_read_inst|Add2~2_combout ), + .cout(\fifo_read_inst|Add2~3 )); +// synopsys translate_off +defparam \fifo_read_inst|Add2~2 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|Add2~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N14 +cycloneive_lcell_comb \fifo_read_inst|Add2~6 ( +// Equation(s): +// \fifo_read_inst|Add2~6_combout = \fifo_read_inst|bit_cnt [3] $ (\fifo_read_inst|Add2~5 ) + + .dataa(gnd), + .datab(\fifo_read_inst|bit_cnt [3]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|Add2~5 ), + .combout(\fifo_read_inst|Add2~6_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Add2~6 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|Add2~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N4 +cycloneive_lcell_comb \fifo_read_inst|bit_cnt~0 ( +// Equation(s): +// \fifo_read_inst|bit_cnt~0_combout = (\fifo_read_inst|Add2~6_combout & ((!\fifo_read_inst|always5~0_combout ) # (!\fifo_read_inst|bit_cnt [0]))) + + .dataa(gnd), + .datab(\fifo_read_inst|bit_cnt [0]), + .datac(\fifo_read_inst|Add2~6_combout ), + .datad(\fifo_read_inst|always5~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt~0 .lut_mask = 16'h30F0; +defparam \fifo_read_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N5 +dffeas \fifo_read_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N4 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[0]~13 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[0]~13_combout = (\fifo_read_inst|rd_flag~q & (\fifo_read_inst|baud_cnt [0] $ (VCC))) # (!\fifo_read_inst|rd_flag~q & (\fifo_read_inst|baud_cnt [0] & VCC)) +// \fifo_read_inst|baud_cnt[0]~14 = CARRY((\fifo_read_inst|rd_flag~q & \fifo_read_inst|baud_cnt [0])) + + .dataa(\fifo_read_inst|rd_flag~q ), + .datab(\fifo_read_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|baud_cnt[0]~13_combout ), + .cout(\fifo_read_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \fifo_read_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N14 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[5]~23 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[5]~23_combout = (\fifo_read_inst|baud_cnt [5] & (!\fifo_read_inst|baud_cnt[4]~22 )) # (!\fifo_read_inst|baud_cnt [5] & ((\fifo_read_inst|baud_cnt[4]~22 ) # (GND))) +// \fifo_read_inst|baud_cnt[5]~24 = CARRY((!\fifo_read_inst|baud_cnt[4]~22 ) # (!\fifo_read_inst|baud_cnt [5])) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[4]~22 ), + .combout(\fifo_read_inst|baud_cnt[5]~23_combout ), + .cout(\fifo_read_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N16 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[6]~25 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[6]~25_combout = (\fifo_read_inst|baud_cnt [6] & (\fifo_read_inst|baud_cnt[5]~24 $ (GND))) # (!\fifo_read_inst|baud_cnt [6] & (!\fifo_read_inst|baud_cnt[5]~24 & VCC)) +// \fifo_read_inst|baud_cnt[6]~26 = CARRY((\fifo_read_inst|baud_cnt [6] & !\fifo_read_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[5]~24 ), + .combout(\fifo_read_inst|baud_cnt[6]~25_combout ), + .cout(\fifo_read_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N17 +dffeas \fifo_read_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N18 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[7]~27 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[7]~27_combout = (\fifo_read_inst|baud_cnt [7] & (!\fifo_read_inst|baud_cnt[6]~26 )) # (!\fifo_read_inst|baud_cnt [7] & ((\fifo_read_inst|baud_cnt[6]~26 ) # (GND))) +// \fifo_read_inst|baud_cnt[7]~28 = CARRY((!\fifo_read_inst|baud_cnt[6]~26 ) # (!\fifo_read_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[6]~26 ), + .combout(\fifo_read_inst|baud_cnt[7]~27_combout ), + .cout(\fifo_read_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N19 +dffeas \fifo_read_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N20 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[8]~29 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[8]~29_combout = (\fifo_read_inst|baud_cnt [8] & (\fifo_read_inst|baud_cnt[7]~28 $ (GND))) # (!\fifo_read_inst|baud_cnt [8] & (!\fifo_read_inst|baud_cnt[7]~28 & VCC)) +// \fifo_read_inst|baud_cnt[8]~30 = CARRY((\fifo_read_inst|baud_cnt [8] & !\fifo_read_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[7]~28 ), + .combout(\fifo_read_inst|baud_cnt[8]~29_combout ), + .cout(\fifo_read_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N21 +dffeas \fifo_read_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N0 +cycloneive_lcell_comb \fifo_read_inst|Equal4~0 ( +// Equation(s): +// \fifo_read_inst|Equal4~0_combout = (\fifo_read_inst|baud_cnt [1] & (!\fifo_read_inst|baud_cnt [8] & (\fifo_read_inst|baud_cnt [0] & !\fifo_read_inst|baud_cnt [7]))) + + .dataa(\fifo_read_inst|baud_cnt [1]), + .datab(\fifo_read_inst|baud_cnt [8]), + .datac(\fifo_read_inst|baud_cnt [0]), + .datad(\fifo_read_inst|baud_cnt [7]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~0 .lut_mask = 16'h0020; +defparam \fifo_read_inst|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N10 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[3]~19 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[3]~19_combout = (\fifo_read_inst|baud_cnt [3] & (!\fifo_read_inst|baud_cnt[2]~18 )) # (!\fifo_read_inst|baud_cnt [3] & ((\fifo_read_inst|baud_cnt[2]~18 ) # (GND))) +// \fifo_read_inst|baud_cnt[3]~20 = CARRY((!\fifo_read_inst|baud_cnt[2]~18 ) # (!\fifo_read_inst|baud_cnt [3])) + + .dataa(\fifo_read_inst|baud_cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[2]~18 ), + .combout(\fifo_read_inst|baud_cnt[3]~19_combout ), + .cout(\fifo_read_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N11 +dffeas \fifo_read_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N22 +cycloneive_lcell_comb \fifo_read_inst|Equal4~1 ( +// Equation(s): +// \fifo_read_inst|Equal4~1_combout = (\fifo_read_inst|baud_cnt [4] & (!\fifo_read_inst|baud_cnt [5] & (!\fifo_read_inst|baud_cnt [3] & \fifo_read_inst|baud_cnt [2]))) + + .dataa(\fifo_read_inst|baud_cnt [4]), + .datab(\fifo_read_inst|baud_cnt [5]), + .datac(\fifo_read_inst|baud_cnt [3]), + .datad(\fifo_read_inst|baud_cnt [2]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~1 .lut_mask = 16'h0200; +defparam \fifo_read_inst|Equal4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N24 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[10]~33 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[10]~33_combout = (\fifo_read_inst|baud_cnt [10] & (\fifo_read_inst|baud_cnt[9]~32 $ (GND))) # (!\fifo_read_inst|baud_cnt [10] & (!\fifo_read_inst|baud_cnt[9]~32 & VCC)) +// \fifo_read_inst|baud_cnt[10]~34 = CARRY((\fifo_read_inst|baud_cnt [10] & !\fifo_read_inst|baud_cnt[9]~32 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[9]~32 ), + .combout(\fifo_read_inst|baud_cnt[10]~33_combout ), + .cout(\fifo_read_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N25 +dffeas \fifo_read_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N28 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[12]~37 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[12]~37_combout = \fifo_read_inst|baud_cnt[11]~36 $ (!\fifo_read_inst|baud_cnt [12]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\fifo_read_inst|baud_cnt [12]), + .cin(\fifo_read_inst|baud_cnt[11]~36 ), + .combout(\fifo_read_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; +defparam \fifo_read_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N29 +dffeas \fifo_read_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N16 +cycloneive_lcell_comb \fifo_read_inst|Equal4~3 ( +// Equation(s): +// \fifo_read_inst|Equal4~3_combout = (\fifo_read_inst|Equal4~2_combout & (\fifo_read_inst|Equal4~0_combout & (\fifo_read_inst|Equal4~1_combout & \fifo_read_inst|baud_cnt [12]))) + + .dataa(\fifo_read_inst|Equal4~2_combout ), + .datab(\fifo_read_inst|Equal4~0_combout ), + .datac(\fifo_read_inst|Equal4~1_combout ), + .datad(\fifo_read_inst|baud_cnt [12]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~3_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~3 .lut_mask = 16'h8000; +defparam \fifo_read_inst|Equal4~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y25_N5 +dffeas \fifo_read_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N8 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[2]~17 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[2]~17_combout = (\fifo_read_inst|baud_cnt [2] & (\fifo_read_inst|baud_cnt[1]~16 $ (GND))) # (!\fifo_read_inst|baud_cnt [2] & (!\fifo_read_inst|baud_cnt[1]~16 & VCC)) +// \fifo_read_inst|baud_cnt[2]~18 = CARRY((\fifo_read_inst|baud_cnt [2] & !\fifo_read_inst|baud_cnt[1]~16 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[1]~16 ), + .combout(\fifo_read_inst|baud_cnt[2]~17_combout ), + .cout(\fifo_read_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N9 +dffeas \fifo_read_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N15 +dffeas \fifo_read_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N28 +cycloneive_lcell_comb \fifo_read_inst|Equal5~0 ( +// Equation(s): +// \fifo_read_inst|Equal5~0_combout = (!\fifo_read_inst|baud_cnt [4] & (\fifo_read_inst|baud_cnt [5] & (\fifo_read_inst|baud_cnt [3] & !\fifo_read_inst|baud_cnt [2]))) + + .dataa(\fifo_read_inst|baud_cnt [4]), + .datab(\fifo_read_inst|baud_cnt [5]), + .datac(\fifo_read_inst|baud_cnt [3]), + .datad(\fifo_read_inst|baud_cnt [2]), + .cin(gnd), + .combout(\fifo_read_inst|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal5~0 .lut_mask = 16'h0040; +defparam \fifo_read_inst|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N26 +cycloneive_lcell_comb \fifo_read_inst|Equal5~2 ( +// Equation(s): +// \fifo_read_inst|Equal5~2_combout = (\fifo_read_inst|Equal5~1_combout & (\fifo_read_inst|Equal5~0_combout & (\fifo_read_inst|Equal4~0_combout & !\fifo_read_inst|baud_cnt [12]))) + + .dataa(\fifo_read_inst|Equal5~1_combout ), + .datab(\fifo_read_inst|Equal5~0_combout ), + .datac(\fifo_read_inst|Equal4~0_combout ), + .datad(\fifo_read_inst|baud_cnt [12]), + .cin(gnd), + .combout(\fifo_read_inst|Equal5~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal5~2 .lut_mask = 16'h0080; +defparam \fifo_read_inst|Equal5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N27 +dffeas \fifo_read_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|Equal5~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_flag .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N6 +cycloneive_lcell_comb \fifo_read_inst|bit_cnt~1 ( +// Equation(s): +// \fifo_read_inst|bit_cnt~1_combout = (\fifo_read_inst|Add2~2_combout & ((!\fifo_read_inst|bit_cnt [0]) # (!\fifo_read_inst|always5~0_combout ))) + + .dataa(gnd), + .datab(\fifo_read_inst|always5~0_combout ), + .datac(\fifo_read_inst|bit_cnt [0]), + .datad(\fifo_read_inst|Add2~2_combout ), + .cin(gnd), + .combout(\fifo_read_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt~1 .lut_mask = 16'h3F00; +defparam \fifo_read_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N7 +dffeas \fifo_read_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N24 +cycloneive_lcell_comb \fifo_read_inst|always5~0 ( +// Equation(s): +// \fifo_read_inst|always5~0_combout = (!\fifo_read_inst|bit_cnt [2] & (\fifo_read_inst|bit_cnt [3] & (\fifo_read_inst|bit_flag~q & !\fifo_read_inst|bit_cnt [1]))) + + .dataa(\fifo_read_inst|bit_cnt [2]), + .datab(\fifo_read_inst|bit_cnt [3]), + .datac(\fifo_read_inst|bit_flag~q ), + .datad(\fifo_read_inst|bit_cnt [1]), + .cin(gnd), + .combout(\fifo_read_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|always5~0 .lut_mask = 16'h0040; +defparam \fifo_read_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N0 +cycloneive_lcell_comb \fifo_read_inst|always5~1 ( +// Equation(s): +// \fifo_read_inst|always5~1_combout = (\fifo_read_inst|bit_cnt [0] & \fifo_read_inst|always5~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\fifo_read_inst|bit_cnt [0]), + .datad(\fifo_read_inst|always5~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|always5~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|always5~1 .lut_mask = 16'hF000; +defparam \fifo_read_inst|always5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N1 +dffeas \fifo_read_inst|rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|always5~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|rd_en .is_wysiwyg = "true"; +defparam \fifo_read_inst|rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]) # +// (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]) # (!\fifo_read_inst|rd_en~q )) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0])) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .lut_mask = 16'hFBFF; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N6 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ) # (\fifo_read_inst|read_en_dly~q ) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datab(gnd), + .datac(\fifo_read_inst|read_en_dly~q ), + .datad(gnd), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .lut_mask = 16'hFAFA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ) # +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ) # (!\fifo_read_inst|Equal1~1_combout )))) + + .dataa(\fifo_read_inst|Equal1~1_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .lut_mask = 16'hFFD0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N26 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ) # +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q & !\fifo_read_inst|rd_en~q )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ), + .datab(gnd), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4 .lut_mask = 16'hAAFA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N27 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout = (\fifo_read_inst|read_en_dly~q & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q $ (((!\fifo_read_inst|rd_en~q ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ))))) # (!\fifo_read_inst|read_en_dly~q & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & +// ((\fifo_read_inst|rd_en~q )))) + + .dataa(\fifo_read_inst|read_en_dly~q ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .lut_mask = 16'hC60A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N9 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y25_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y22_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N10 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h0040; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N28 +cycloneive_lcell_comb \fifo_read_inst|read_en~0 ( +// Equation(s): +// \fifo_read_inst|read_en~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout & (\Equal2~1_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout & +// \Equal2~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .datab(\Equal2~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .datad(\Equal2~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_en~0 .lut_mask = 16'h0400; +defparam \fifo_read_inst|read_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N8 +cycloneive_lcell_comb \fifo_read_inst|read_en~1 ( +// Equation(s): +// \fifo_read_inst|read_en~1_combout = (\fifo_read_inst|read_en~0_combout ) # ((\fifo_read_inst|read_en~q & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]) # +// (!\fifo_read_inst|Equal1~2_combout )))) + + .dataa(\fifo_read_inst|Equal1~2_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datac(\fifo_read_inst|read_en~q ), + .datad(\fifo_read_inst|read_en~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_en~1 .lut_mask = 16'hFFD0; +defparam \fifo_read_inst|read_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N9 +dffeas \fifo_read_inst|read_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_en~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_en .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout = (\fifo_read_inst|read_en~q & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ) # +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .datad(\fifo_read_inst|read_en~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hFC00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h0800; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0010; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N2 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0001; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9 .lut_mask = 16'h55AA; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 $ (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [9])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [9]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [9]), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18 .lut_mask = 16'h5AA5; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout = (\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout & (!\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2 .lut_mask = 16'h0002; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout = (!\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout & (\Equal2~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout & +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ), + .datab(\Equal2~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q & (!\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0 .lut_mask = 16'h0100; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0 .lut_mask = 16'h5500; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & !\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1 .lut_mask = 16'hFF08; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7 .lut_mask = 16'h0030; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0 .lut_mask = 16'hDCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ) # ((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0 .lut_mask = 16'hFF50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & (\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1 .lut_mask = 16'hF888; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ) # +// (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3 .lut_mask = 16'hFEFE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0 .lut_mask = 16'hC0C0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0 .lut_mask = 16'h00F8; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4 .lut_mask = 16'h0F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2 .lut_mask = 16'h0AA0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15 .lut_mask = 16'h00F0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ) # ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0 .lut_mask = 16'hFF50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]))) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1 .lut_mask = 16'h0330; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0 .lut_mask = 16'h0300; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout = ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1 .lut_mask = 16'hFFD5; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2 .lut_mask = 16'hFF88; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2] $ +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0 .lut_mask = 16'h1230; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0 .lut_mask = 16'h7F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1 .lut_mask = 16'hFCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2 .lut_mask = 16'h0007; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk +// [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ) # +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0 .lut_mask = 16'hB3A0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3 .lut_mask = 16'hF5F5; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17 .lut_mask = 16'h2020; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0 .lut_mask = 16'hFFC0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3 .lut_mask = 16'h000F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]))) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2 .lut_mask = 16'h003C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1 .lut_mask = 16'h0C0C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0 .lut_mask = 16'hEAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0 .lut_mask = 16'hB800; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3 .lut_mask = 16'h0055; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4 .lut_mask = 16'h0004; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0 .lut_mask = 16'h2AAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [9] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [11] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[12] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 $ (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28 .lut_mask = 16'hF00F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[14] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[11] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0 .lut_mask = 16'h0040; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1 .lut_mask = 16'h0020; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6]), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2 .lut_mask = 16'h5000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0 .lut_mask = 16'h2000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2 .lut_mask = 16'hFEFF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] $ +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4 .lut_mask = 16'h1230; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0 .lut_mask = 16'hCC00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0 .lut_mask = 16'hF2F0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16 .lut_mask = 16'h4040; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0 .lut_mask = 16'h55AA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref +// [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref +// [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1 .lut_mask = 16'hF0FF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref +// [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8 .lut_mask = 16'hCC00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout = (((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0 .lut_mask = 16'h777F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5] & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1 .lut_mask = 16'h8C00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout = ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2 .lut_mask = 16'h1F3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3 .lut_mask = 16'hC840; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 $ (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1 .lut_mask = 16'h0040; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2 .lut_mask = 16'hC000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ) # +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0 .lut_mask = 16'hBA30; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0 .lut_mask = 16'h0F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & (\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0 .lut_mask = 16'h5450; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1 .lut_mask = 16'hFFCF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout & +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0 .lut_mask = 16'hF888; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2 .lut_mask = 16'hFFF8; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] $ (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datac(gnd), + .datad(gnd), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5 .lut_mask = 16'h0033; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0 .lut_mask = 16'hAAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout = ((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2 .lut_mask = 16'h5557; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ) # +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h00A8; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h5400; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .lut_mask = 16'h9696; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1] $ (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .lut_mask = 16'h5AA5; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h2000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h0200; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hB4F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h0040; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .lut_mask = 16'hC3F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h2814; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout +// )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'hE2C0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'hA018; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout = (\uart_rx_inst|po_flag~q & ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .datab(gnd), + .datac(\uart_rx_inst|po_flag~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .lut_mask = 16'h50F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \rx~input ( + .i(rx), + .ibar(gnd), + .o(\rx~input_o )); +// synopsys translate_off +defparam \rx~input .bus_hold = "false"; +defparam \rx~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N12 +cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( +// Equation(s): +// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rx~input_o ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y24_N13 +dffeas \uart_rx_inst|rx_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg1~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y24_N3 +dffeas \uart_rx_inst|rx_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_reg3~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg3~feeder_combout = \uart_rx_inst|rx_reg2~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg2~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y24_N1 +dffeas \uart_rx_inst|rx_reg3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg3~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N14 +cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( +// Equation(s): +// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg3~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N10 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~0_combout = (\uart_rx_inst|Add1~6_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q ))) + + .dataa(\uart_rx_inst|Add1~6_combout ), + .datab(\uart_rx_inst|bit_flag~q ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h2AAA; +defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N11 +dffeas \uart_rx_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N18 +cycloneive_lcell_comb \uart_rx_inst|always8~0 ( +// Equation(s): +// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(gnd), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|always8~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always8~0 .lut_mask = 16'hC030; +defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N15 +dffeas \uart_rx_inst|rx_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[7]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y23_N21 +dffeas \uart_rx_inst|rx_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N18 +cycloneive_lcell_comb \uart_rx_inst|rx_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[5]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N19 +dffeas \uart_rx_inst|rx_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[4]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N1 +dffeas \uart_rx_inst|rx_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N6 +cycloneive_lcell_comb \uart_rx_inst|rx_data[3]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[3]~feeder_combout = \uart_rx_inst|rx_data [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [4]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N7 +dffeas \uart_rx_inst|rx_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N28 +cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N29 +dffeas \uart_rx_inst|rx_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[1]~feeder_combout = \uart_rx_inst|rx_data [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [2]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N3 +dffeas \uart_rx_inst|rx_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N24 +cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N25 +dffeas \uart_rx_inst|rx_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N8 +cycloneive_lcell_comb \uart_rx_inst|po_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[0]~feeder_combout = \uart_rx_inst|rx_data [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [0]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N9 +dffeas \uart_rx_inst|po_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a[9] ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9]), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a[9] .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout = !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N10 +cycloneive_lcell_comb \uart_rx_inst|po_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[1]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N11 +dffeas \uart_rx_inst|po_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N12 +cycloneive_lcell_comb \uart_rx_inst|po_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[2]~feeder_combout = \uart_rx_inst|rx_data [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [2]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N13 +dffeas \uart_rx_inst|po_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N30 +cycloneive_lcell_comb \uart_rx_inst|po_data[3]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[3]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N31 +dffeas \uart_rx_inst|po_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N16 +cycloneive_lcell_comb \uart_rx_inst|po_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[4]~feeder_combout = \uart_rx_inst|rx_data [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [4]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N17 +dffeas \uart_rx_inst|po_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N26 +cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N27 +dffeas \uart_rx_inst|po_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N4 +cycloneive_lcell_comb \uart_rx_inst|po_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[6]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N5 +dffeas \uart_rx_inst|po_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y23_N23 +dffeas \uart_rx_inst|po_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y23_N8 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X13_Y23_N0 +cycloneive_ram_block \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .ena0(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(\rst_n~0clkctrl_outclk ), + .portadatain({\~GND~combout ,\uart_rx_inst|po_data [7],\uart_rx_inst|po_data [6],\uart_rx_inst|po_data [5],\uart_rx_inst|po_data [4],\uart_rx_inst|po_data [3],\uart_rx_inst|po_data [2],\uart_rx_inst|po_data [1],\uart_rx_inst|po_data [0]}), + .portaaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "sdram_top:sdram_top_inst|fifo_ctrl:fifo_ctrl_inst|fifo_data:wr_fifo_data|dcfifo:dcfifo_component|dcfifo_3fk1:auto_generated|altsyncram_em31:fifo_ram|ALTSYNCRAM"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X13_Y21_N0 +cycloneive_ram_block \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 ( + .portawe(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .ena0(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(\rst_n~0clkctrl_outclk ), + .portadatain({gnd,gnd,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout }), + .portaaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .clk0_core_clock_enable = "ena0"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .clk1_output_clock_enable = "ena1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .data_interleave_offset_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .data_interleave_width_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .logical_ram_name = "sdram_top:sdram_top_inst|fifo_ctrl:fifo_ctrl_inst|fifo_data:wr_fifo_data|dcfifo:dcfifo_component|dcfifo_3fk1:auto_generated|altsyncram_em31:fifo_ram|ALTSYNCRAM"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .operation_mode = "dual_port"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_address_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_byte_enable_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_data_out_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_data_out_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_first_bit_number = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_address_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_address_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_data_out_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_data_out_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_first_bit_number = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_read_enable_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: CLKCTRL_G5 +cycloneive_clkctrl \sys_clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sys_clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sys_clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \sys_clk~inputclkctrl .clock_type = "global clock"; +defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N4 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) +// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_tx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N26 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) + + .dataa(\uart_tx_inst|baud_cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[10]~34 ), + .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_tx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N27 +dffeas \uart_tx_inst|baud_cnt[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N0 +cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( +// Equation(s): +// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt [5] & (\uart_tx_inst|baud_cnt [0] & !\uart_tx_inst|baud_cnt [7]))) + + .dataa(\uart_tx_inst|baud_cnt [3]), + .datab(\uart_tx_inst|baud_cnt [5]), + .datac(\uart_tx_inst|baud_cnt [0]), + .datad(\uart_tx_inst|baud_cnt [7]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0010; +defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N22 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) + + .dataa(\uart_tx_inst|baud_cnt [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[8]~30 ), + .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_tx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N23 +dffeas \uart_tx_inst|baud_cnt[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N2 +cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( +// Equation(s): +// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt [11] & (\uart_tx_inst|Equal1~0_combout & !\uart_tx_inst|baud_cnt [9]))) + + .dataa(\uart_tx_inst|baud_cnt [8]), + .datab(\uart_tx_inst|baud_cnt [11]), + .datac(\uart_tx_inst|Equal1~0_combout ), + .datad(\uart_tx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0010; +defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N6 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) + + .dataa(\uart_tx_inst|baud_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[0]~14 ), + .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_tx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N7 +dffeas \uart_tx_inst|baud_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N30 +cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( +// Equation(s): +// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [2] & \uart_tx_inst|baud_cnt [1]))) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [2]), + .datad(\uart_tx_inst|baud_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; +defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N19 +dffeas \fifo_read_inst|tx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\fifo_read_inst|rd_en~q ), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|tx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|tx_flag .is_wysiwyg = "true"; +defparam \fifo_read_inst|tx_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \uart_tx_inst|always3~0 ( +// Equation(s): +// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|work_en~q ) # (!\uart_tx_inst|bit_flag~q ) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(gnd), + .datac(\uart_tx_inst|work_en~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_tx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always3~0 .lut_mask = 16'h5F5F; +defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~2 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[1]~2_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [1]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1]~2 .lut_mask = 16'h00D2; +defparam \uart_tx_inst|bit_cnt[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N19 +dffeas \uart_tx_inst|bit_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[1]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~3 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[2]~3_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~0_combout )))) + + .dataa(\uart_tx_inst|Add1~0_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2]~3 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N5 +dffeas \uart_tx_inst|bit_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[2]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \uart_tx_inst|always0~1 ( +// Equation(s): +// \uart_tx_inst|always0~1_combout = (\uart_tx_inst|bit_cnt [0] & (!\uart_tx_inst|bit_cnt [1] & (!\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|always0~0_combout ))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~1 .lut_mask = 16'h0200; +defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N18 +cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( +// Equation(s): +// \uart_tx_inst|work_en~0_combout = (\fifo_read_inst|tx_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) + + .dataa(gnd), + .datab(\uart_tx_inst|work_en~q ), + .datac(\fifo_read_inst|tx_flag~q ), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hF0FC; +defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N25 +dffeas \uart_tx_inst|work_en ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_tx_inst|work_en~0_combout ), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_tx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N6 +cycloneive_lcell_comb \uart_tx_inst|always1~0 ( +// Equation(s): +// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~3_combout & (\uart_tx_inst|Equal1~1_combout & \uart_tx_inst|Equal1~2_combout ))) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|Equal1~3_combout ), + .datab(\uart_tx_inst|Equal1~1_combout ), + .datac(\uart_tx_inst|Equal1~2_combout ), + .datad(\uart_tx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_tx_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always1~0 .lut_mask = 16'h80FF; +defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y18_N5 +dffeas \uart_tx_inst|baud_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N8 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) +// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[1]~16 ), + .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_tx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N9 +dffeas \uart_tx_inst|baud_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N14 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[4]~22 ), + .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_tx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N15 +dffeas \uart_tx_inst|baud_cnt[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N16 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) +// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[5]~24 ), + .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_tx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N17 +dffeas \uart_tx_inst|baud_cnt[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N18 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[6]~26 ), + .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_tx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N19 +dffeas \uart_tx_inst|baud_cnt[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N20 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) +// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[7]~28 ), + .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_tx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N21 +dffeas \uart_tx_inst|baud_cnt[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N24 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) +// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[9]~32 ), + .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_tx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N25 +dffeas \uart_tx_inst|baud_cnt[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N28 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt[11]~36 $ (!\uart_tx_inst|baud_cnt [12]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_tx_inst|baud_cnt [12]), + .cin(\uart_tx_inst|baud_cnt[11]~36 ), + .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; +defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N29 +dffeas \uart_tx_inst|baud_cnt[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N2 +cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( +// Equation(s): +// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt [1]))) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [2]), + .datad(\uart_tx_inst|baud_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N24 +cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( +// Equation(s): +// \uart_tx_inst|Equal2~1_combout = (\uart_tx_inst|Equal1~1_combout & (!\uart_tx_inst|baud_cnt [12] & (\uart_tx_inst|Equal2~0_combout & !\uart_tx_inst|baud_cnt [10]))) + + .dataa(\uart_tx_inst|Equal1~1_combout ), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(\uart_tx_inst|Equal2~0_combout ), + .datad(\uart_tx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h0020; +defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y18_N25 +dffeas \uart_tx_inst|bit_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|Equal2~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \uart_tx_inst|always0~0 ( +// Equation(s): +// \uart_tx_inst|always0~0_combout = (\uart_tx_inst|bit_cnt [3] & \uart_tx_inst|bit_flag~q ) + + .dataa(\uart_tx_inst|bit_cnt [3]), + .datab(gnd), + .datac(\uart_tx_inst|bit_flag~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_tx_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~0 .lut_mask = 16'hA0A0; +defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N30 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & \fifo_read_inst|rd_en~q ) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datab(gnd), + .datac(gnd), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq .lut_mask = 16'hAA00; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N8 +cycloneive_io_ibuf \sdram_dq[0]~input ( + .i(sdram_dq[0]), + .ibar(gnd), + .o(\sdram_dq[0]~input_o )); +// synopsys translate_off +defparam \sdram_dq[0]~input .bus_hold = "false"; +defparam \sdram_dq[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[0]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout = !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N1 +cycloneive_io_ibuf \sdram_dq[1]~input ( + .i(sdram_dq[1]), + .ibar(gnd), + .o(\sdram_dq[1]~input_o )); +// synopsys translate_off +defparam \sdram_dq[1]~input .bus_hold = "false"; +defparam \sdram_dq[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[1]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [1] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y29_N1 +cycloneive_io_ibuf \sdram_dq[2]~input ( + .i(sdram_dq[2]), + .ibar(gnd), + .o(\sdram_dq[2]~input_o )); +// synopsys translate_off +defparam \sdram_dq[2]~input .bus_hold = "false"; +defparam \sdram_dq[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[2]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y29_N29 +cycloneive_io_ibuf \sdram_dq[3]~input ( + .i(sdram_dq[3]), + .ibar(gnd), + .o(\sdram_dq[3]~input_o )); +// synopsys translate_off +defparam \sdram_dq[3]~input .bus_hold = "false"; +defparam \sdram_dq[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[3]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [3] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [3]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y29_N22 +cycloneive_io_ibuf \sdram_dq[4]~input ( + .i(sdram_dq[4]), + .ibar(gnd), + .o(\sdram_dq[4]~input_o )); +// synopsys translate_off +defparam \sdram_dq[4]~input .bus_hold = "false"; +defparam \sdram_dq[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[4]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [4] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [4]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y29_N8 +cycloneive_io_ibuf \sdram_dq[5]~input ( + .i(sdram_dq[5]), + .ibar(gnd), + .o(\sdram_dq[5]~input_o )); +// synopsys translate_off +defparam \sdram_dq[5]~input .bus_hold = "false"; +defparam \sdram_dq[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[5]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [5] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N15 +cycloneive_io_ibuf \sdram_dq[6]~input ( + .i(sdram_dq[6]), + .ibar(gnd), + .o(\sdram_dq[6]~input_o )); +// synopsys translate_off +defparam \sdram_dq[6]~input .bus_hold = "false"; +defparam \sdram_dq[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[6]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [6] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [6]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N22 +cycloneive_io_ibuf \sdram_dq[7]~input ( + .i(sdram_dq[7]), + .ibar(gnd), + .o(\sdram_dq[7]~input_o )); +// synopsys translate_off +defparam \sdram_dq[7]~input .bus_hold = "false"; +defparam \sdram_dq[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[7]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [7] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [7]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X25_Y25_N0 +cycloneive_ram_block \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .ena1(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(\rst_n~0clkctrl_outclk ), + .portadatain({gnd,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout , +\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout , +\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout }), + .portaaddr({\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "sdram_top:sdram_top_inst|fifo_ctrl:fifo_ctrl_inst|fifo_data:rd_fifo_data|dcfifo:dcfifo_component|dcfifo_3fk1:auto_generated|altsyncram_em31:fifo_ram|ALTSYNCRAM"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N6 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0] $ (VCC) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT = CARRY(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0 .lut_mask = 16'h55AA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N7 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N8 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N9 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N10 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N11 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3])) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N14 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N15 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N17 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N18 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N19 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N21 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N23 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N25 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N10 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0] $ (VCC) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT = CARRY(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0 .lut_mask = 16'h55AA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N11 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1])) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N14 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N15 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N17 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N18 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N19 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N21 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N23 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N25 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N26 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N27 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N28 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9]), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9 .lut_mask = 16'h0FF0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N29 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \uart_tx_inst|tx~4 ( +// Equation(s): +// \uart_tx_inst|tx~4_combout = (\uart_tx_inst|bit_cnt [0]) # ((\uart_tx_inst|bit_cnt [2]) # ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [7]) # (\uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [7]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~4 .lut_mask = 16'hFFFE; +defparam \uart_tx_inst|tx~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \uart_tx_inst|tx~3 ( +// Equation(s): +// \uart_tx_inst|tx~3_combout = (!\uart_tx_inst|bit_flag~q & !\uart_tx_inst|tx~q ) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(gnd), + .datac(gnd), + .datad(\uart_tx_inst|tx~q ), + .cin(gnd), + .combout(\uart_tx_inst|tx~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~3 .lut_mask = 16'h0055; +defparam \uart_tx_inst|tx~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \uart_tx_inst|tx~5 ( +// Equation(s): +// \uart_tx_inst|tx~5_combout = (!\uart_tx_inst|tx~2_combout & (!\uart_tx_inst|tx~3_combout & ((!\uart_tx_inst|tx~4_combout ) # (!\uart_tx_inst|always0~0_combout )))) + + .dataa(\uart_tx_inst|tx~2_combout ), + .datab(\uart_tx_inst|always0~0_combout ), + .datac(\uart_tx_inst|tx~4_combout ), + .datad(\uart_tx_inst|tx~3_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~5 .lut_mask = 16'h0015; +defparam \uart_tx_inst|tx~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N1 +dffeas \uart_tx_inst|tx ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|tx~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|tx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|tx .is_wysiwyg = "true"; +defparam \uart_tx_inst|tx .power_up = "low"; +// synopsys translate_on + +// Location: CLKCTRL_G7 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X23_Y22_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y22_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1 .lut_mask = 16'hF0FC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0 .lut_mask = 16'hBAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0 .lut_mask = 16'h4000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2 .lut_mask = 16'hFF20; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0 .lut_mask = 16'hFFAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [1])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [1]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2 .lut_mask = 16'h8C9D; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [1]))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [1])))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [1]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3 .lut_mask = 16'h5F22; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0 .lut_mask = 16'hFAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17 .lut_mask = 16'h00CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) # +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5 .lut_mask = 16'hFFEE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0 .lut_mask = 16'hFFAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [2])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [2] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0 .lut_mask = 16'hA1AB; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [2])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [2]))))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [2]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1 .lut_mask = 16'h5F30; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0 .lut_mask = 16'h5554; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ) # +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1 .lut_mask = 16'hAAA0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [0]) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [0] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1 .lut_mask = 16'h1ABA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2 .lut_mask = 16'hFAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1 .lut_mask = 16'h4055; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6 .lut_mask = 16'h0F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3 .lut_mask = 16'hF0FF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]))) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5 .lut_mask = 16'h3C00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2] $ +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4 .lut_mask = 16'h7800; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15 .lut_mask = 16'h0002; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y21_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0 .lut_mask = 16'h55CF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1 .lut_mask = 16'hF7F2; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0 .lut_mask = 16'h4CCC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2 .lut_mask = 16'h0001; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0] & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & +// (((!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0 .lut_mask = 16'h0777; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0 .lut_mask = 16'h0101; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0 .lut_mask = 16'h2022; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16 .lut_mask = 16'h4400; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0 .lut_mask = 16'h5053; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1 .lut_mask = 16'h008F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10])))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0 .lut_mask = 16'h0FDD; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1 .lut_mask = 16'hDFCE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y20_N8 +cycloneive_io_ibuf \sdram_dq[8]~input ( + .i(sdram_dq[8]), + .ibar(gnd), + .o(\sdram_dq[8]~input_o )); +// synopsys translate_off +defparam \sdram_dq[8]~input .bus_hold = "false"; +defparam \sdram_dq[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y29_N29 +cycloneive_io_ibuf \sdram_dq[9]~input ( + .i(sdram_dq[9]), + .ibar(gnd), + .o(\sdram_dq[9]~input_o )); +// synopsys translate_off +defparam \sdram_dq[9]~input .bus_hold = "false"; +defparam \sdram_dq[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y25_N1 +cycloneive_io_ibuf \sdram_dq[10]~input ( + .i(sdram_dq[10]), + .ibar(gnd), + .o(\sdram_dq[10]~input_o )); +// synopsys translate_off +defparam \sdram_dq[10]~input .bus_hold = "false"; +defparam \sdram_dq[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y26_N8 +cycloneive_io_ibuf \sdram_dq[11]~input ( + .i(sdram_dq[11]), + .ibar(gnd), + .o(\sdram_dq[11]~input_o )); +// synopsys translate_off +defparam \sdram_dq[11]~input .bus_hold = "false"; +defparam \sdram_dq[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N8 +cycloneive_io_ibuf \sdram_dq[12]~input ( + .i(sdram_dq[12]), + .ibar(gnd), + .o(\sdram_dq[12]~input_o )); +// synopsys translate_off +defparam \sdram_dq[12]~input .bus_hold = "false"; +defparam \sdram_dq[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N8 +cycloneive_io_ibuf \sdram_dq[13]~input ( + .i(sdram_dq[13]), + .ibar(gnd), + .o(\sdram_dq[13]~input_o )); +// synopsys translate_off +defparam \sdram_dq[13]~input .bus_hold = "false"; +defparam \sdram_dq[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N22 +cycloneive_io_ibuf \sdram_dq[14]~input ( + .i(sdram_dq[14]), + .ibar(gnd), + .o(\sdram_dq[14]~input_o )); +// synopsys translate_off +defparam \sdram_dq[14]~input .bus_hold = "false"; +defparam \sdram_dq[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N1 +cycloneive_io_ibuf \sdram_dq[15]~input ( + .i(sdram_dq[15]), + .ibar(gnd), + .o(\sdram_dq[15]~input_o )); +// synopsys translate_off +defparam \sdram_dq[15]~input .bus_hold = "false"; +defparam \sdram_dq[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_8_1200mv_0c_slow.vo b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_8_1200mv_0c_slow.vo new file mode 100644 index 0000000..9d22bab --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_8_1200mv_0c_slow.vo @@ -0,0 +1,24917 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:26:31" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module uart_sdram ( + sys_clk, + sys_rst_n, + rx, + tx, + sdram_clk, + sdram_cke, + sdram_cs_n, + sdram_cas_n, + sdram_ras_n, + sdram_we_n, + sdram_ba, + sdram_addr, + sdram_dqm, + sdram_dq); +input sys_clk; +input sys_rst_n; +input rx; +output tx; +output sdram_clk; +output sdram_cke; +output sdram_cs_n; +output sdram_cas_n; +output sdram_ras_n; +output sdram_we_n; +output [1:0] sdram_ba; +output [12:0] sdram_addr; +output [1:0] sdram_dqm; +inout [15:0] sdram_dq; + +// Design Ports Information +// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_clk => Location: PIN_E5, I/O Standard: 2.5 V, Current Strength: Default +// sdram_cke => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_cs_n => Location: PIN_A4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_cas_n => Location: PIN_B5, I/O Standard: 2.5 V, Current Strength: Default +// sdram_ras_n => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_we_n => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default +// sdram_ba[0] => Location: PIN_B4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_ba[1] => Location: PIN_C4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[0] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[1] => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[2] => Location: PIN_B2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[3] => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[4] => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[5] => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[6] => Location: PIN_F1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[7] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[8] => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[9] => Location: PIN_N2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[10] => Location: PIN_A3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[11] => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[12] => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dqm[0] => Location: PIN_C6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dqm[1] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[0] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[1] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[2] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[3] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[4] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[5] => Location: PIN_C7, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[6] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[7] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[8] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[9] => Location: PIN_C3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[10] => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[11] => Location: PIN_E3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[12] => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[13] => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[14] => Location: PIN_J3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[15] => Location: PIN_J4, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("uart_sdram_8_1200mv_0c_v_slow.sdo"); +// synopsys translate_on + +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout ; +wire \uart_tx_inst|baud_cnt[3]~19_combout ; +wire \uart_tx_inst|baud_cnt[4]~21_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout ; +wire \fifo_read_inst|Add2~4_combout ; +wire \Add1~1 ; +wire \Add1~0_combout ; +wire \Add1~3 ; +wire \Add1~2_combout ; +wire \Add1~5 ; +wire \Add1~4_combout ; +wire \Add1~7 ; +wire \Add1~6_combout ; +wire \Add1~9 ; +wire \Add1~8_combout ; +wire \Add1~11 ; +wire \Add1~10_combout ; +wire \Add1~13 ; +wire \Add1~12_combout ; +wire \Add1~15 ; +wire \Add1~14_combout ; +wire \Add1~17 ; +wire \Add1~16_combout ; +wire \Add1~19 ; +wire \Add1~18_combout ; +wire \Add1~21 ; +wire \Add1~20_combout ; +wire \Add1~23 ; +wire \Add1~22_combout ; +wire \Add1~25 ; +wire \Add1~24_combout ; +wire \Add1~27 ; +wire \Add1~26_combout ; +wire \Add1~29 ; +wire \Add1~28_combout ; +wire \Add1~30_combout ; +wire \fifo_read_inst|baud_cnt[1]~15_combout ; +wire \fifo_read_inst|baud_cnt[4]~21_combout ; +wire \fifo_read_inst|baud_cnt[9]~31_combout ; +wire \fifo_read_inst|baud_cnt[11]~35_combout ; +wire \data_num[0]~25 ; +wire \data_num[0]~24_combout ; +wire \data_num[1]~27 ; +wire \data_num[1]~26_combout ; +wire \data_num[2]~29 ; +wire \data_num[2]~28_combout ; +wire \data_num[3]~31 ; +wire \data_num[3]~30_combout ; +wire \data_num[4]~33 ; +wire \data_num[4]~32_combout ; +wire \data_num[5]~35 ; +wire \data_num[5]~34_combout ; +wire \data_num[6]~37 ; +wire \data_num[6]~36_combout ; +wire \data_num[7]~39 ; +wire \data_num[7]~38_combout ; +wire \data_num[8]~41 ; +wire \data_num[8]~40_combout ; +wire \data_num[9]~43 ; +wire \data_num[9]~42_combout ; +wire \data_num[10]~45 ; +wire \data_num[10]~44_combout ; +wire \data_num[11]~47 ; +wire \data_num[11]~46_combout ; +wire \data_num[12]~49 ; +wire \data_num[12]~48_combout ; +wire \data_num[13]~51 ; +wire \data_num[13]~50_combout ; +wire \data_num[14]~53 ; +wire \data_num[14]~52_combout ; +wire \data_num[15]~55 ; +wire \data_num[15]~54_combout ; +wire \data_num[16]~57 ; +wire \data_num[16]~56_combout ; +wire \data_num[17]~59 ; +wire \data_num[17]~58_combout ; +wire \data_num[18]~61 ; +wire \data_num[18]~60_combout ; +wire \data_num[19]~63 ; +wire \data_num[19]~62_combout ; +wire \data_num[20]~65 ; +wire \data_num[20]~64_combout ; +wire \data_num[21]~67 ; +wire \data_num[21]~66_combout ; +wire \data_num[22]~69 ; +wire \data_num[22]~68_combout ; +wire \data_num[23]~70_combout ; +wire \uart_rx_inst|Add1~0_combout ; +wire \uart_rx_inst|Add1~5 ; +wire \uart_rx_inst|Add1~6_combout ; +wire \fifo_read_inst|cnt_read[0]~11 ; +wire \fifo_read_inst|cnt_read[0]~10_combout ; +wire \fifo_read_inst|cnt_read[1]~13 ; +wire \fifo_read_inst|cnt_read[1]~12_combout ; +wire \fifo_read_inst|cnt_read[2]~15 ; +wire \fifo_read_inst|cnt_read[2]~14_combout ; +wire \fifo_read_inst|cnt_read[3]~17 ; +wire \fifo_read_inst|cnt_read[3]~16_combout ; +wire \fifo_read_inst|cnt_read[4]~19 ; +wire \fifo_read_inst|cnt_read[4]~18_combout ; +wire \fifo_read_inst|cnt_read[5]~21 ; +wire \fifo_read_inst|cnt_read[5]~20_combout ; +wire \fifo_read_inst|cnt_read[6]~23 ; +wire \fifo_read_inst|cnt_read[6]~22_combout ; +wire \fifo_read_inst|cnt_read[7]~25 ; +wire \fifo_read_inst|cnt_read[7]~24_combout ; +wire \fifo_read_inst|cnt_read[8]~27 ; +wire \fifo_read_inst|cnt_read[8]~26_combout ; +wire \fifo_read_inst|cnt_read[9]~28_combout ; +wire \uart_rx_inst|baud_cnt[4]~21_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout ; +wire \uart_tx_inst|Mux0~0_combout ; +wire \uart_tx_inst|Mux0~1_combout ; +wire \uart_tx_inst|tx~0_combout ; +wire \uart_tx_inst|tx~1_combout ; +wire \uart_tx_inst|tx~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout ; +wire \uart_tx_inst|Add1~0_combout ; +wire \uart_tx_inst|Add1~1_combout ; +wire \uart_tx_inst|bit_cnt[3]~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout ; +wire \read_valid~q ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout ; +wire \uart_tx_inst|Equal1~3_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ; +wire \fifo_read_inst|Equal1~0_combout ; +wire \fifo_read_inst|Equal1~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout ; +wire \Equal0~0_combout ; +wire \Equal0~1_combout ; +wire \Equal0~2_combout ; +wire \Equal0~3_combout ; +wire \Equal0~4_combout ; +wire \read_valid~0_combout ; +wire \read_valid~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ; +wire \fifo_read_inst|Equal1~2_combout ; +wire \fifo_read_inst|Equal5~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \Equal1~0_combout ; +wire \Equal1~1_combout ; +wire \Equal1~2_combout ; +wire \Equal1~3_combout ; +wire \Equal1~4_combout ; +wire \Equal1~5_combout ; +wire \Equal1~6_combout ; +wire \cnt_wait[8]~0_combout ; +wire \cnt_wait[15]~1_combout ; +wire \cnt_wait[15]~2_combout ; +wire \cnt_wait[14]~3_combout ; +wire \cnt_wait[13]~4_combout ; +wire \cnt_wait[12]~5_combout ; +wire \cnt_wait[9]~6_combout ; +wire \cnt_wait[11]~7_combout ; +wire \cnt_wait[10]~8_combout ; +wire \cnt_wait[8]~9_combout ; +wire \cnt_wait[7]~10_combout ; +wire \cnt_wait[6]~11_combout ; +wire \cnt_wait[5]~12_combout ; +wire \cnt_wait[4]~13_combout ; +wire \cnt_wait[3]~14_combout ; +wire \cnt_wait[2]~15_combout ; +wire \cnt_wait[1]~16_combout ; +wire \cnt_wait[0]~17_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \fifo_read_inst|rd_flag~q ; +wire \fifo_read_inst|Equal4~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ; +wire \fifo_read_inst|Equal2~0_combout ; +wire \fifo_read_inst|Equal2~1_combout ; +wire \fifo_read_inst|Equal2~2_combout ; +wire \fifo_read_inst|rd_flag~0_combout ; +wire \uart_rx_inst|bit_cnt~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout ; +wire \uart_rx_inst|work_en~q ; +wire \uart_rx_inst|start_nedge~q ; +wire \uart_rx_inst|work_en~0_combout ; +wire \uart_rx_inst|always3~0_combout ; +wire \uart_tx_inst|bit_cnt[0]~5_combout ; +wire \sdram_dq[8]~input_o ; +wire \sdram_dq[9]~input_o ; +wire \sdram_dq[10]~input_o ; +wire \sdram_dq[11]~input_o ; +wire \sdram_dq[12]~input_o ; +wire \sdram_dq[13]~input_o ; +wire \sdram_dq[14]~input_o ; +wire \sdram_dq[15]~input_o ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout ; +wire \uart_rx_inst|baud_cnt[0]~13_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \uart_rx_inst|baud_cnt[2]~18 ; +wire \uart_rx_inst|baud_cnt[3]~19_combout ; +wire \uart_rx_inst|baud_cnt[3]~20 ; +wire \uart_rx_inst|baud_cnt[4]~22 ; +wire \uart_rx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|Equal1~1_combout ; +wire \uart_rx_inst|baud_cnt[5]~24 ; +wire \uart_rx_inst|baud_cnt[6]~25_combout ; +wire \uart_rx_inst|baud_cnt[6]~26 ; +wire \uart_rx_inst|baud_cnt[7]~27_combout ; +wire \uart_rx_inst|baud_cnt[7]~28 ; +wire \uart_rx_inst|baud_cnt[8]~29_combout ; +wire \uart_rx_inst|Equal1~0_combout ; +wire \uart_rx_inst|baud_cnt[8]~30 ; +wire \uart_rx_inst|baud_cnt[9]~31_combout ; +wire \uart_rx_inst|baud_cnt[9]~32 ; +wire \uart_rx_inst|baud_cnt[10]~34 ; +wire \uart_rx_inst|baud_cnt[11]~35_combout ; +wire \uart_rx_inst|Equal1~2_combout ; +wire \uart_rx_inst|baud_cnt[10]~33_combout ; +wire \uart_rx_inst|Equal1~3_combout ; +wire \uart_rx_inst|always5~0_combout ; +wire \uart_rx_inst|baud_cnt[0]~14 ; +wire \uart_rx_inst|baud_cnt[1]~15_combout ; +wire \uart_rx_inst|baud_cnt[1]~16 ; +wire \uart_rx_inst|baud_cnt[2]~17_combout ; +wire \uart_rx_inst|Equal2~0_combout ; +wire \uart_rx_inst|baud_cnt[11]~36 ; +wire \uart_rx_inst|baud_cnt[12]~37_combout ; +wire \uart_rx_inst|Equal2~1_combout ; +wire \uart_rx_inst|Equal2~2_combout ; +wire \uart_rx_inst|bit_flag~q ; +wire \uart_rx_inst|Add1~1 ; +wire \uart_rx_inst|Add1~3 ; +wire \uart_rx_inst|Add1~4_combout ; +wire \uart_rx_inst|Add1~2_combout ; +wire \uart_rx_inst|always4~0_combout ; +wire \uart_rx_inst|always4~1_combout ; +wire \uart_rx_inst|rx_flag~q ; +wire \uart_rx_inst|po_flag~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ; +wire \fifo_read_inst|read_en_dly~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout ; +wire \fifo_read_inst|Add2~0_combout ; +wire \fifo_read_inst|Add2~1 ; +wire \fifo_read_inst|Add2~3 ; +wire \fifo_read_inst|Add2~5 ; +wire \fifo_read_inst|Add2~6_combout ; +wire \fifo_read_inst|bit_cnt~0_combout ; +wire \fifo_read_inst|baud_cnt[0]~13_combout ; +wire \fifo_read_inst|baud_cnt[5]~24 ; +wire \fifo_read_inst|baud_cnt[6]~25_combout ; +wire \fifo_read_inst|baud_cnt[6]~26 ; +wire \fifo_read_inst|baud_cnt[7]~27_combout ; +wire \fifo_read_inst|baud_cnt[7]~28 ; +wire \fifo_read_inst|baud_cnt[8]~29_combout ; +wire \fifo_read_inst|Equal4~0_combout ; +wire \fifo_read_inst|baud_cnt[3]~19_combout ; +wire \fifo_read_inst|Equal4~1_combout ; +wire \fifo_read_inst|baud_cnt[8]~30 ; +wire \fifo_read_inst|baud_cnt[9]~32 ; +wire \fifo_read_inst|baud_cnt[10]~33_combout ; +wire \fifo_read_inst|baud_cnt[10]~34 ; +wire \fifo_read_inst|baud_cnt[11]~36 ; +wire \fifo_read_inst|baud_cnt[12]~37_combout ; +wire \fifo_read_inst|Equal4~3_combout ; +wire \fifo_read_inst|baud_cnt[0]~14 ; +wire \fifo_read_inst|baud_cnt[1]~16 ; +wire \fifo_read_inst|baud_cnt[2]~17_combout ; +wire \fifo_read_inst|baud_cnt[2]~18 ; +wire \fifo_read_inst|baud_cnt[3]~20 ; +wire \fifo_read_inst|baud_cnt[4]~22 ; +wire \fifo_read_inst|baud_cnt[5]~23_combout ; +wire \fifo_read_inst|Equal5~0_combout ; +wire \fifo_read_inst|Equal5~2_combout ; +wire \fifo_read_inst|bit_flag~q ; +wire \fifo_read_inst|Add2~2_combout ; +wire \fifo_read_inst|bit_cnt~1_combout ; +wire \fifo_read_inst|always5~0_combout ; +wire \fifo_read_inst|always5~1_combout ; +wire \fifo_read_inst|rd_en~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ; +wire \Equal2~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ; +wire \fifo_read_inst|read_en~0_combout ; +wire \fifo_read_inst|read_en~1_combout ; +wire \fifo_read_inst|read_en~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ; +wire \Equal2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \rx~input_o ; +wire \uart_rx_inst|rx_reg1~0_combout ; +wire \uart_rx_inst|rx_reg1~q ; +wire \uart_rx_inst|rx_reg2~feeder_combout ; +wire \uart_rx_inst|rx_reg2~q ; +wire \uart_rx_inst|rx_reg3~feeder_combout ; +wire \uart_rx_inst|rx_reg3~q ; +wire \uart_rx_inst|rx_data[7]~0_combout ; +wire \uart_rx_inst|bit_cnt~0_combout ; +wire \uart_rx_inst|always8~0_combout ; +wire \uart_rx_inst|rx_data[5]~feeder_combout ; +wire \uart_rx_inst|rx_data[4]~feeder_combout ; +wire \uart_rx_inst|rx_data[3]~feeder_combout ; +wire \uart_rx_inst|rx_data[2]~feeder_combout ; +wire \uart_rx_inst|rx_data[1]~feeder_combout ; +wire \uart_rx_inst|rx_data[0]~feeder_combout ; +wire \uart_rx_inst|po_data[0]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \uart_rx_inst|po_data[1]~feeder_combout ; +wire \uart_rx_inst|po_data[2]~feeder_combout ; +wire \uart_rx_inst|po_data[3]~feeder_combout ; +wire \uart_rx_inst|po_data[4]~feeder_combout ; +wire \uart_rx_inst|po_data[5]~feeder_combout ; +wire \uart_rx_inst|po_data[6]~feeder_combout ; +wire \~GND~combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ; +wire \sys_clk~inputclkctrl_outclk ; +wire \uart_tx_inst|baud_cnt[0]~13_combout ; +wire \uart_tx_inst|baud_cnt[11]~35_combout ; +wire \uart_tx_inst|Equal1~0_combout ; +wire \uart_tx_inst|baud_cnt[9]~31_combout ; +wire \uart_tx_inst|Equal1~1_combout ; +wire \uart_tx_inst|baud_cnt[1]~15_combout ; +wire \uart_tx_inst|Equal1~2_combout ; +wire \fifo_read_inst|tx_flag~q ; +wire \uart_tx_inst|always3~0_combout ; +wire \uart_tx_inst|bit_cnt[1]~2_combout ; +wire \uart_tx_inst|bit_cnt[2]~3_combout ; +wire \uart_tx_inst|always0~1_combout ; +wire \uart_tx_inst|work_en~0_combout ; +wire \uart_tx_inst|work_en~q ; +wire \uart_tx_inst|always1~0_combout ; +wire \uart_tx_inst|baud_cnt[0]~14 ; +wire \uart_tx_inst|baud_cnt[1]~16 ; +wire \uart_tx_inst|baud_cnt[2]~17_combout ; +wire \uart_tx_inst|baud_cnt[2]~18 ; +wire \uart_tx_inst|baud_cnt[3]~20 ; +wire \uart_tx_inst|baud_cnt[4]~22 ; +wire \uart_tx_inst|baud_cnt[5]~23_combout ; +wire \uart_tx_inst|baud_cnt[5]~24 ; +wire \uart_tx_inst|baud_cnt[6]~25_combout ; +wire \uart_tx_inst|baud_cnt[6]~26 ; +wire \uart_tx_inst|baud_cnt[7]~27_combout ; +wire \uart_tx_inst|baud_cnt[7]~28 ; +wire \uart_tx_inst|baud_cnt[8]~29_combout ; +wire \uart_tx_inst|baud_cnt[8]~30 ; +wire \uart_tx_inst|baud_cnt[9]~32 ; +wire \uart_tx_inst|baud_cnt[10]~33_combout ; +wire \uart_tx_inst|baud_cnt[10]~34 ; +wire \uart_tx_inst|baud_cnt[11]~36 ; +wire \uart_tx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal2~0_combout ; +wire \uart_tx_inst|Equal2~1_combout ; +wire \uart_tx_inst|bit_flag~q ; +wire \uart_tx_inst|always0~0_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ; +wire \sdram_dq[0]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \sdram_dq[1]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout ; +wire \sdram_dq[2]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout ; +wire \sdram_dq[3]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout ; +wire \sdram_dq[4]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout ; +wire \sdram_dq[5]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout ; +wire \sdram_dq[6]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout ; +wire \sdram_dq[7]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout ; +wire \uart_tx_inst|tx~4_combout ; +wire \uart_tx_inst|tx~3_combout ; +wire \uart_tx_inst|tx~5_combout ; +wire \uart_tx_inst|tx~q ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a ; +wire [15:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a ; +wire [9:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit ; +wire [23:0] data_num; +wire [15:0] cnt_wait; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \uart_rx_inst|rx_data ; +wire [7:0] \uart_rx_inst|po_data ; +wire [3:0] \uart_rx_inst|bit_cnt ; +wire [12:0] \uart_rx_inst|baud_cnt ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g ; +wire [9:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a ; +wire [15:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd ; +wire [1:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref ; +wire [2:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk ; +wire [14:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us ; +wire [2:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk ; +wire [1:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref ; +wire [9:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd ; +wire [1:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba ; +wire [12:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr ; +wire [9:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd ; +wire [12:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr ; +wire [15:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg ; +wire [9:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk ; +wire [9:0] \fifo_read_inst|cnt_read ; +wire [3:0] \fifo_read_inst|bit_cnt ; +wire [12:0] \fifo_read_inst|baud_cnt ; +wire [9:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit ; +wire [7:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b ; +wire [9:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit ; +wire [3:0] \uart_tx_inst|bit_cnt ; +wire [12:0] \uart_tx_inst|baud_cnt ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; +wire [8:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus ; +wire [8:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; +wire [8:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; +wire [8:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [0] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [0]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [1] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [1]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [2] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [2]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [3] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [3]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [4] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [4]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [5] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [5]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [6] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [6]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [7] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [7]; + +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; + +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [8] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [8]; + +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [9] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [0]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [10] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [1]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [11] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [2]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [12] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [3]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [13] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [4]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [14] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [5]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [15] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [6]; + +// Location: M9K_X25_Y18_N0 +cycloneive_ram_block \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 ( + .portawe(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .ena1(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({gnd,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0]}), + .portaaddr({\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .clk0_core_clock_enable = "ena0"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .clk1_core_clock_enable = "ena1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .clk1_input_clock_enable = "ena1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .data_interleave_offset_in_bits = 1; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .data_interleave_width_in_bits = 1; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .logical_ram_name = "fifo_read:fifo_read_inst|read_fifo:read_fifo_inst|scfifo:scfifo_component|scfifo_un21:auto_generated|a_dpfifo_5u21:dpfifo|dpram_d811:FIFOram|altsyncram_c3k1:altsyncram1|ALTSYNCRAM"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .operation_mode = "dual_port"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_address_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_address_width = 10; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_byte_enable_clock = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_data_out_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_data_out_clock = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_data_width = 9; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_first_address = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_first_bit_number = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_last_address = 1023; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_logical_ram_depth = 1024; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_logical_ram_width = 8; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_address_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_address_clock = "clock1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_address_width = 10; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_data_out_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_data_out_clock = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_data_width = 9; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_first_address = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_first_bit_number = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_last_address = 1023; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_logical_ram_depth = 1024; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_logical_ram_width = 8; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_read_enable_clock = "clock1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: FF_X24_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y21_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y23_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y23_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y18_N11 +dffeas \uart_tx_inst|baud_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y18_N13 +dffeas \uart_tx_inst|baud_cnt[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0] & ((GND) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0]))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0] $ (GND))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0 .lut_mask = 16'h66BB; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N10 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) + + .dataa(\uart_tx_inst|baud_cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[2]~18 ), + .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_tx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N12 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) +// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[3]~20 ), + .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_tx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [13] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N8 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N10 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N14 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N18 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT ) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N7 +dffeas \fifo_read_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N13 +dffeas \fifo_read_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N23 +dffeas \fifo_read_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N27 +dffeas \fifo_read_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N12 +cycloneive_lcell_comb \fifo_read_inst|Add2~4 ( +// Equation(s): +// \fifo_read_inst|Add2~4_combout = (\fifo_read_inst|bit_cnt [2] & (\fifo_read_inst|Add2~3 $ (GND))) # (!\fifo_read_inst|bit_cnt [2] & (!\fifo_read_inst|Add2~3 & VCC)) +// \fifo_read_inst|Add2~5 = CARRY((\fifo_read_inst|bit_cnt [2] & !\fifo_read_inst|Add2~3 )) + + .dataa(\fifo_read_inst|bit_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|Add2~3 ), + .combout(\fifo_read_inst|Add2~4_combout ), + .cout(\fifo_read_inst|Add2~5 )); +// synopsys translate_off +defparam \fifo_read_inst|Add2~4 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|Add2~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y24_N9 +dffeas \data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[0]~24_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[0] .is_wysiwyg = "true"; +defparam \data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N13 +dffeas \data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[2]~28_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[2] .is_wysiwyg = "true"; +defparam \data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N11 +dffeas \data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[1]~26_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[1] .is_wysiwyg = "true"; +defparam \data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N15 +dffeas \data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[3]~30_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[3] .is_wysiwyg = "true"; +defparam \data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N17 +dffeas \data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[4]~32_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[4] .is_wysiwyg = "true"; +defparam \data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N19 +dffeas \data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[5]~34_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[5] .is_wysiwyg = "true"; +defparam \data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N21 +dffeas \data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[6]~36_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[6] .is_wysiwyg = "true"; +defparam \data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N23 +dffeas \data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[7]~38_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[7] .is_wysiwyg = "true"; +defparam \data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N25 +dffeas \data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[8]~40_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[8] .is_wysiwyg = "true"; +defparam \data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N27 +dffeas \data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[9]~42_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[9] .is_wysiwyg = "true"; +defparam \data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N29 +dffeas \data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[10]~44_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[10] .is_wysiwyg = "true"; +defparam \data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N31 +dffeas \data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[11]~46_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[11]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[11] .is_wysiwyg = "true"; +defparam \data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N1 +dffeas \data_num[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[12]~48_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[12]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[12] .is_wysiwyg = "true"; +defparam \data_num[12] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N3 +dffeas \data_num[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[13]~50_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[13]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[13] .is_wysiwyg = "true"; +defparam \data_num[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N5 +dffeas \data_num[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[14]~52_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[14]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[14] .is_wysiwyg = "true"; +defparam \data_num[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N7 +dffeas \data_num[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[15]~54_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[15]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[15] .is_wysiwyg = "true"; +defparam \data_num[15] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N9 +dffeas \data_num[16] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[16]~56_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[16]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[16] .is_wysiwyg = "true"; +defparam \data_num[16] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N11 +dffeas \data_num[17] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[17]~58_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[17]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[17] .is_wysiwyg = "true"; +defparam \data_num[17] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N13 +dffeas \data_num[18] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[18]~60_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[18]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[18] .is_wysiwyg = "true"; +defparam \data_num[18] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N15 +dffeas \data_num[19] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[19]~62_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[19]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[19] .is_wysiwyg = "true"; +defparam \data_num[19] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N17 +dffeas \data_num[20] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[20]~64_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[20]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[20] .is_wysiwyg = "true"; +defparam \data_num[20] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N19 +dffeas \data_num[21] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[21]~66_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[21]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[21] .is_wysiwyg = "true"; +defparam \data_num[21] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N21 +dffeas \data_num[22] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[22]~68_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[22]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[22] .is_wysiwyg = "true"; +defparam \data_num[22] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N23 +dffeas \data_num[23] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[23]~70_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[23]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[23] .is_wysiwyg = "true"; +defparam \data_num[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N0 +cycloneive_lcell_comb \Add1~0 ( +// Equation(s): +// \Add1~0_combout = cnt_wait[0] $ (VCC) +// \Add1~1 = CARRY(cnt_wait[0]) + + .dataa(gnd), + .datab(cnt_wait[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Add1~0_combout ), + .cout(\Add1~1 )); +// synopsys translate_off +defparam \Add1~0 .lut_mask = 16'h33CC; +defparam \Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N2 +cycloneive_lcell_comb \Add1~2 ( +// Equation(s): +// \Add1~2_combout = (cnt_wait[1] & (!\Add1~1 )) # (!cnt_wait[1] & ((\Add1~1 ) # (GND))) +// \Add1~3 = CARRY((!\Add1~1 ) # (!cnt_wait[1])) + + .dataa(cnt_wait[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~1 ), + .combout(\Add1~2_combout ), + .cout(\Add1~3 )); +// synopsys translate_off +defparam \Add1~2 .lut_mask = 16'h5A5F; +defparam \Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N4 +cycloneive_lcell_comb \Add1~4 ( +// Equation(s): +// \Add1~4_combout = (cnt_wait[2] & (\Add1~3 $ (GND))) # (!cnt_wait[2] & (!\Add1~3 & VCC)) +// \Add1~5 = CARRY((cnt_wait[2] & !\Add1~3 )) + + .dataa(gnd), + .datab(cnt_wait[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~3 ), + .combout(\Add1~4_combout ), + .cout(\Add1~5 )); +// synopsys translate_off +defparam \Add1~4 .lut_mask = 16'hC30C; +defparam \Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N6 +cycloneive_lcell_comb \Add1~6 ( +// Equation(s): +// \Add1~6_combout = (cnt_wait[3] & (!\Add1~5 )) # (!cnt_wait[3] & ((\Add1~5 ) # (GND))) +// \Add1~7 = CARRY((!\Add1~5 ) # (!cnt_wait[3])) + + .dataa(gnd), + .datab(cnt_wait[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~5 ), + .combout(\Add1~6_combout ), + .cout(\Add1~7 )); +// synopsys translate_off +defparam \Add1~6 .lut_mask = 16'h3C3F; +defparam \Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N8 +cycloneive_lcell_comb \Add1~8 ( +// Equation(s): +// \Add1~8_combout = (cnt_wait[4] & (\Add1~7 $ (GND))) # (!cnt_wait[4] & (!\Add1~7 & VCC)) +// \Add1~9 = CARRY((cnt_wait[4] & !\Add1~7 )) + + .dataa(cnt_wait[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~7 ), + .combout(\Add1~8_combout ), + .cout(\Add1~9 )); +// synopsys translate_off +defparam \Add1~8 .lut_mask = 16'hA50A; +defparam \Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N10 +cycloneive_lcell_comb \Add1~10 ( +// Equation(s): +// \Add1~10_combout = (cnt_wait[5] & (!\Add1~9 )) # (!cnt_wait[5] & ((\Add1~9 ) # (GND))) +// \Add1~11 = CARRY((!\Add1~9 ) # (!cnt_wait[5])) + + .dataa(cnt_wait[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~9 ), + .combout(\Add1~10_combout ), + .cout(\Add1~11 )); +// synopsys translate_off +defparam \Add1~10 .lut_mask = 16'h5A5F; +defparam \Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N12 +cycloneive_lcell_comb \Add1~12 ( +// Equation(s): +// \Add1~12_combout = (cnt_wait[6] & (\Add1~11 $ (GND))) # (!cnt_wait[6] & (!\Add1~11 & VCC)) +// \Add1~13 = CARRY((cnt_wait[6] & !\Add1~11 )) + + .dataa(cnt_wait[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~11 ), + .combout(\Add1~12_combout ), + .cout(\Add1~13 )); +// synopsys translate_off +defparam \Add1~12 .lut_mask = 16'hA50A; +defparam \Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N14 +cycloneive_lcell_comb \Add1~14 ( +// Equation(s): +// \Add1~14_combout = (cnt_wait[7] & (!\Add1~13 )) # (!cnt_wait[7] & ((\Add1~13 ) # (GND))) +// \Add1~15 = CARRY((!\Add1~13 ) # (!cnt_wait[7])) + + .dataa(cnt_wait[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~13 ), + .combout(\Add1~14_combout ), + .cout(\Add1~15 )); +// synopsys translate_off +defparam \Add1~14 .lut_mask = 16'h5A5F; +defparam \Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N16 +cycloneive_lcell_comb \Add1~16 ( +// Equation(s): +// \Add1~16_combout = (cnt_wait[8] & (\Add1~15 $ (GND))) # (!cnt_wait[8] & (!\Add1~15 & VCC)) +// \Add1~17 = CARRY((cnt_wait[8] & !\Add1~15 )) + + .dataa(cnt_wait[8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~15 ), + .combout(\Add1~16_combout ), + .cout(\Add1~17 )); +// synopsys translate_off +defparam \Add1~16 .lut_mask = 16'hA50A; +defparam \Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N18 +cycloneive_lcell_comb \Add1~18 ( +// Equation(s): +// \Add1~18_combout = (cnt_wait[9] & (!\Add1~17 )) # (!cnt_wait[9] & ((\Add1~17 ) # (GND))) +// \Add1~19 = CARRY((!\Add1~17 ) # (!cnt_wait[9])) + + .dataa(gnd), + .datab(cnt_wait[9]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~17 ), + .combout(\Add1~18_combout ), + .cout(\Add1~19 )); +// synopsys translate_off +defparam \Add1~18 .lut_mask = 16'h3C3F; +defparam \Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N20 +cycloneive_lcell_comb \Add1~20 ( +// Equation(s): +// \Add1~20_combout = (cnt_wait[10] & (\Add1~19 $ (GND))) # (!cnt_wait[10] & (!\Add1~19 & VCC)) +// \Add1~21 = CARRY((cnt_wait[10] & !\Add1~19 )) + + .dataa(cnt_wait[10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~19 ), + .combout(\Add1~20_combout ), + .cout(\Add1~21 )); +// synopsys translate_off +defparam \Add1~20 .lut_mask = 16'hA50A; +defparam \Add1~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N22 +cycloneive_lcell_comb \Add1~22 ( +// Equation(s): +// \Add1~22_combout = (cnt_wait[11] & (!\Add1~21 )) # (!cnt_wait[11] & ((\Add1~21 ) # (GND))) +// \Add1~23 = CARRY((!\Add1~21 ) # (!cnt_wait[11])) + + .dataa(gnd), + .datab(cnt_wait[11]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~21 ), + .combout(\Add1~22_combout ), + .cout(\Add1~23 )); +// synopsys translate_off +defparam \Add1~22 .lut_mask = 16'h3C3F; +defparam \Add1~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N24 +cycloneive_lcell_comb \Add1~24 ( +// Equation(s): +// \Add1~24_combout = (cnt_wait[12] & (\Add1~23 $ (GND))) # (!cnt_wait[12] & (!\Add1~23 & VCC)) +// \Add1~25 = CARRY((cnt_wait[12] & !\Add1~23 )) + + .dataa(gnd), + .datab(cnt_wait[12]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~23 ), + .combout(\Add1~24_combout ), + .cout(\Add1~25 )); +// synopsys translate_off +defparam \Add1~24 .lut_mask = 16'hC30C; +defparam \Add1~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N26 +cycloneive_lcell_comb \Add1~26 ( +// Equation(s): +// \Add1~26_combout = (cnt_wait[13] & (!\Add1~25 )) # (!cnt_wait[13] & ((\Add1~25 ) # (GND))) +// \Add1~27 = CARRY((!\Add1~25 ) # (!cnt_wait[13])) + + .dataa(gnd), + .datab(cnt_wait[13]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~25 ), + .combout(\Add1~26_combout ), + .cout(\Add1~27 )); +// synopsys translate_off +defparam \Add1~26 .lut_mask = 16'h3C3F; +defparam \Add1~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N28 +cycloneive_lcell_comb \Add1~28 ( +// Equation(s): +// \Add1~28_combout = (cnt_wait[14] & (\Add1~27 $ (GND))) # (!cnt_wait[14] & (!\Add1~27 & VCC)) +// \Add1~29 = CARRY((cnt_wait[14] & !\Add1~27 )) + + .dataa(cnt_wait[14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~27 ), + .combout(\Add1~28_combout ), + .cout(\Add1~29 )); +// synopsys translate_off +defparam \Add1~28 .lut_mask = 16'hA50A; +defparam \Add1~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N30 +cycloneive_lcell_comb \Add1~30 ( +// Equation(s): +// \Add1~30_combout = \Add1~29 $ (cnt_wait[15]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(cnt_wait[15]), + .cin(\Add1~29 ), + .combout(\Add1~30_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~30 .lut_mask = 16'h0FF0; +defparam \Add1~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N6 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[1]~15 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[1]~15_combout = (\fifo_read_inst|baud_cnt [1] & (!\fifo_read_inst|baud_cnt[0]~14 )) # (!\fifo_read_inst|baud_cnt [1] & ((\fifo_read_inst|baud_cnt[0]~14 ) # (GND))) +// \fifo_read_inst|baud_cnt[1]~16 = CARRY((!\fifo_read_inst|baud_cnt[0]~14 ) # (!\fifo_read_inst|baud_cnt [1])) + + .dataa(\fifo_read_inst|baud_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[0]~14 ), + .combout(\fifo_read_inst|baud_cnt[1]~15_combout ), + .cout(\fifo_read_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N12 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[4]~21 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[4]~21_combout = (\fifo_read_inst|baud_cnt [4] & (\fifo_read_inst|baud_cnt[3]~20 $ (GND))) # (!\fifo_read_inst|baud_cnt [4] & (!\fifo_read_inst|baud_cnt[3]~20 & VCC)) +// \fifo_read_inst|baud_cnt[4]~22 = CARRY((\fifo_read_inst|baud_cnt [4] & !\fifo_read_inst|baud_cnt[3]~20 )) + + .dataa(\fifo_read_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[3]~20 ), + .combout(\fifo_read_inst|baud_cnt[4]~21_combout ), + .cout(\fifo_read_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N22 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[9]~31 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[9]~31_combout = (\fifo_read_inst|baud_cnt [9] & (!\fifo_read_inst|baud_cnt[8]~30 )) # (!\fifo_read_inst|baud_cnt [9] & ((\fifo_read_inst|baud_cnt[8]~30 ) # (GND))) +// \fifo_read_inst|baud_cnt[9]~32 = CARRY((!\fifo_read_inst|baud_cnt[8]~30 ) # (!\fifo_read_inst|baud_cnt [9])) + + .dataa(\fifo_read_inst|baud_cnt [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[8]~30 ), + .combout(\fifo_read_inst|baud_cnt[9]~31_combout ), + .cout(\fifo_read_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[9]~31 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N26 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[11]~35 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[11]~35_combout = (\fifo_read_inst|baud_cnt [11] & (!\fifo_read_inst|baud_cnt[10]~34 )) # (!\fifo_read_inst|baud_cnt [11] & ((\fifo_read_inst|baud_cnt[10]~34 ) # (GND))) +// \fifo_read_inst|baud_cnt[11]~36 = CARRY((!\fifo_read_inst|baud_cnt[10]~34 ) # (!\fifo_read_inst|baud_cnt [11])) + + .dataa(\fifo_read_inst|baud_cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[10]~34 ), + .combout(\fifo_read_inst|baud_cnt[11]~35_combout ), + .cout(\fifo_read_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N8 +cycloneive_lcell_comb \data_num[0]~24 ( +// Equation(s): +// \data_num[0]~24_combout = (\uart_rx_inst|po_flag~q & (data_num[0] $ (VCC))) # (!\uart_rx_inst|po_flag~q & (data_num[0] & VCC)) +// \data_num[0]~25 = CARRY((\uart_rx_inst|po_flag~q & data_num[0])) + + .dataa(\uart_rx_inst|po_flag~q ), + .datab(data_num[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_num[0]~24_combout ), + .cout(\data_num[0]~25 )); +// synopsys translate_off +defparam \data_num[0]~24 .lut_mask = 16'h6688; +defparam \data_num[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N10 +cycloneive_lcell_comb \data_num[1]~26 ( +// Equation(s): +// \data_num[1]~26_combout = (data_num[1] & (!\data_num[0]~25 )) # (!data_num[1] & ((\data_num[0]~25 ) # (GND))) +// \data_num[1]~27 = CARRY((!\data_num[0]~25 ) # (!data_num[1])) + + .dataa(data_num[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[0]~25 ), + .combout(\data_num[1]~26_combout ), + .cout(\data_num[1]~27 )); +// synopsys translate_off +defparam \data_num[1]~26 .lut_mask = 16'h5A5F; +defparam \data_num[1]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N12 +cycloneive_lcell_comb \data_num[2]~28 ( +// Equation(s): +// \data_num[2]~28_combout = (data_num[2] & (\data_num[1]~27 $ (GND))) # (!data_num[2] & (!\data_num[1]~27 & VCC)) +// \data_num[2]~29 = CARRY((data_num[2] & !\data_num[1]~27 )) + + .dataa(data_num[2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[1]~27 ), + .combout(\data_num[2]~28_combout ), + .cout(\data_num[2]~29 )); +// synopsys translate_off +defparam \data_num[2]~28 .lut_mask = 16'hA50A; +defparam \data_num[2]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N14 +cycloneive_lcell_comb \data_num[3]~30 ( +// Equation(s): +// \data_num[3]~30_combout = (data_num[3] & (!\data_num[2]~29 )) # (!data_num[3] & ((\data_num[2]~29 ) # (GND))) +// \data_num[3]~31 = CARRY((!\data_num[2]~29 ) # (!data_num[3])) + + .dataa(gnd), + .datab(data_num[3]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[2]~29 ), + .combout(\data_num[3]~30_combout ), + .cout(\data_num[3]~31 )); +// synopsys translate_off +defparam \data_num[3]~30 .lut_mask = 16'h3C3F; +defparam \data_num[3]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N16 +cycloneive_lcell_comb \data_num[4]~32 ( +// Equation(s): +// \data_num[4]~32_combout = (data_num[4] & (\data_num[3]~31 $ (GND))) # (!data_num[4] & (!\data_num[3]~31 & VCC)) +// \data_num[4]~33 = CARRY((data_num[4] & !\data_num[3]~31 )) + + .dataa(gnd), + .datab(data_num[4]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[3]~31 ), + .combout(\data_num[4]~32_combout ), + .cout(\data_num[4]~33 )); +// synopsys translate_off +defparam \data_num[4]~32 .lut_mask = 16'hC30C; +defparam \data_num[4]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N18 +cycloneive_lcell_comb \data_num[5]~34 ( +// Equation(s): +// \data_num[5]~34_combout = (data_num[5] & (!\data_num[4]~33 )) # (!data_num[5] & ((\data_num[4]~33 ) # (GND))) +// \data_num[5]~35 = CARRY((!\data_num[4]~33 ) # (!data_num[5])) + + .dataa(gnd), + .datab(data_num[5]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[4]~33 ), + .combout(\data_num[5]~34_combout ), + .cout(\data_num[5]~35 )); +// synopsys translate_off +defparam \data_num[5]~34 .lut_mask = 16'h3C3F; +defparam \data_num[5]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N20 +cycloneive_lcell_comb \data_num[6]~36 ( +// Equation(s): +// \data_num[6]~36_combout = (data_num[6] & (\data_num[5]~35 $ (GND))) # (!data_num[6] & (!\data_num[5]~35 & VCC)) +// \data_num[6]~37 = CARRY((data_num[6] & !\data_num[5]~35 )) + + .dataa(gnd), + .datab(data_num[6]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[5]~35 ), + .combout(\data_num[6]~36_combout ), + .cout(\data_num[6]~37 )); +// synopsys translate_off +defparam \data_num[6]~36 .lut_mask = 16'hC30C; +defparam \data_num[6]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N22 +cycloneive_lcell_comb \data_num[7]~38 ( +// Equation(s): +// \data_num[7]~38_combout = (data_num[7] & (!\data_num[6]~37 )) # (!data_num[7] & ((\data_num[6]~37 ) # (GND))) +// \data_num[7]~39 = CARRY((!\data_num[6]~37 ) # (!data_num[7])) + + .dataa(data_num[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[6]~37 ), + .combout(\data_num[7]~38_combout ), + .cout(\data_num[7]~39 )); +// synopsys translate_off +defparam \data_num[7]~38 .lut_mask = 16'h5A5F; +defparam \data_num[7]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N24 +cycloneive_lcell_comb \data_num[8]~40 ( +// Equation(s): +// \data_num[8]~40_combout = (data_num[8] & (\data_num[7]~39 $ (GND))) # (!data_num[8] & (!\data_num[7]~39 & VCC)) +// \data_num[8]~41 = CARRY((data_num[8] & !\data_num[7]~39 )) + + .dataa(gnd), + .datab(data_num[8]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[7]~39 ), + .combout(\data_num[8]~40_combout ), + .cout(\data_num[8]~41 )); +// synopsys translate_off +defparam \data_num[8]~40 .lut_mask = 16'hC30C; +defparam \data_num[8]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N26 +cycloneive_lcell_comb \data_num[9]~42 ( +// Equation(s): +// \data_num[9]~42_combout = (data_num[9] & (!\data_num[8]~41 )) # (!data_num[9] & ((\data_num[8]~41 ) # (GND))) +// \data_num[9]~43 = CARRY((!\data_num[8]~41 ) # (!data_num[9])) + + .dataa(data_num[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[8]~41 ), + .combout(\data_num[9]~42_combout ), + .cout(\data_num[9]~43 )); +// synopsys translate_off +defparam \data_num[9]~42 .lut_mask = 16'h5A5F; +defparam \data_num[9]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N28 +cycloneive_lcell_comb \data_num[10]~44 ( +// Equation(s): +// \data_num[10]~44_combout = (data_num[10] & (\data_num[9]~43 $ (GND))) # (!data_num[10] & (!\data_num[9]~43 & VCC)) +// \data_num[10]~45 = CARRY((data_num[10] & !\data_num[9]~43 )) + + .dataa(gnd), + .datab(data_num[10]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[9]~43 ), + .combout(\data_num[10]~44_combout ), + .cout(\data_num[10]~45 )); +// synopsys translate_off +defparam \data_num[10]~44 .lut_mask = 16'hC30C; +defparam \data_num[10]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N30 +cycloneive_lcell_comb \data_num[11]~46 ( +// Equation(s): +// \data_num[11]~46_combout = (data_num[11] & (!\data_num[10]~45 )) # (!data_num[11] & ((\data_num[10]~45 ) # (GND))) +// \data_num[11]~47 = CARRY((!\data_num[10]~45 ) # (!data_num[11])) + + .dataa(data_num[11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[10]~45 ), + .combout(\data_num[11]~46_combout ), + .cout(\data_num[11]~47 )); +// synopsys translate_off +defparam \data_num[11]~46 .lut_mask = 16'h5A5F; +defparam \data_num[11]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N0 +cycloneive_lcell_comb \data_num[12]~48 ( +// Equation(s): +// \data_num[12]~48_combout = (data_num[12] & (\data_num[11]~47 $ (GND))) # (!data_num[12] & (!\data_num[11]~47 & VCC)) +// \data_num[12]~49 = CARRY((data_num[12] & !\data_num[11]~47 )) + + .dataa(gnd), + .datab(data_num[12]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[11]~47 ), + .combout(\data_num[12]~48_combout ), + .cout(\data_num[12]~49 )); +// synopsys translate_off +defparam \data_num[12]~48 .lut_mask = 16'hC30C; +defparam \data_num[12]~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N2 +cycloneive_lcell_comb \data_num[13]~50 ( +// Equation(s): +// \data_num[13]~50_combout = (data_num[13] & (!\data_num[12]~49 )) # (!data_num[13] & ((\data_num[12]~49 ) # (GND))) +// \data_num[13]~51 = CARRY((!\data_num[12]~49 ) # (!data_num[13])) + + .dataa(gnd), + .datab(data_num[13]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[12]~49 ), + .combout(\data_num[13]~50_combout ), + .cout(\data_num[13]~51 )); +// synopsys translate_off +defparam \data_num[13]~50 .lut_mask = 16'h3C3F; +defparam \data_num[13]~50 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N4 +cycloneive_lcell_comb \data_num[14]~52 ( +// Equation(s): +// \data_num[14]~52_combout = (data_num[14] & (\data_num[13]~51 $ (GND))) # (!data_num[14] & (!\data_num[13]~51 & VCC)) +// \data_num[14]~53 = CARRY((data_num[14] & !\data_num[13]~51 )) + + .dataa(gnd), + .datab(data_num[14]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[13]~51 ), + .combout(\data_num[14]~52_combout ), + .cout(\data_num[14]~53 )); +// synopsys translate_off +defparam \data_num[14]~52 .lut_mask = 16'hC30C; +defparam \data_num[14]~52 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N6 +cycloneive_lcell_comb \data_num[15]~54 ( +// Equation(s): +// \data_num[15]~54_combout = (data_num[15] & (!\data_num[14]~53 )) # (!data_num[15] & ((\data_num[14]~53 ) # (GND))) +// \data_num[15]~55 = CARRY((!\data_num[14]~53 ) # (!data_num[15])) + + .dataa(data_num[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[14]~53 ), + .combout(\data_num[15]~54_combout ), + .cout(\data_num[15]~55 )); +// synopsys translate_off +defparam \data_num[15]~54 .lut_mask = 16'h5A5F; +defparam \data_num[15]~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N8 +cycloneive_lcell_comb \data_num[16]~56 ( +// Equation(s): +// \data_num[16]~56_combout = (data_num[16] & (\data_num[15]~55 $ (GND))) # (!data_num[16] & (!\data_num[15]~55 & VCC)) +// \data_num[16]~57 = CARRY((data_num[16] & !\data_num[15]~55 )) + + .dataa(gnd), + .datab(data_num[16]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[15]~55 ), + .combout(\data_num[16]~56_combout ), + .cout(\data_num[16]~57 )); +// synopsys translate_off +defparam \data_num[16]~56 .lut_mask = 16'hC30C; +defparam \data_num[16]~56 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N10 +cycloneive_lcell_comb \data_num[17]~58 ( +// Equation(s): +// \data_num[17]~58_combout = (data_num[17] & (!\data_num[16]~57 )) # (!data_num[17] & ((\data_num[16]~57 ) # (GND))) +// \data_num[17]~59 = CARRY((!\data_num[16]~57 ) # (!data_num[17])) + + .dataa(data_num[17]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[16]~57 ), + .combout(\data_num[17]~58_combout ), + .cout(\data_num[17]~59 )); +// synopsys translate_off +defparam \data_num[17]~58 .lut_mask = 16'h5A5F; +defparam \data_num[17]~58 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N12 +cycloneive_lcell_comb \data_num[18]~60 ( +// Equation(s): +// \data_num[18]~60_combout = (data_num[18] & (\data_num[17]~59 $ (GND))) # (!data_num[18] & (!\data_num[17]~59 & VCC)) +// \data_num[18]~61 = CARRY((data_num[18] & !\data_num[17]~59 )) + + .dataa(data_num[18]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[17]~59 ), + .combout(\data_num[18]~60_combout ), + .cout(\data_num[18]~61 )); +// synopsys translate_off +defparam \data_num[18]~60 .lut_mask = 16'hA50A; +defparam \data_num[18]~60 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N14 +cycloneive_lcell_comb \data_num[19]~62 ( +// Equation(s): +// \data_num[19]~62_combout = (data_num[19] & (!\data_num[18]~61 )) # (!data_num[19] & ((\data_num[18]~61 ) # (GND))) +// \data_num[19]~63 = CARRY((!\data_num[18]~61 ) # (!data_num[19])) + + .dataa(gnd), + .datab(data_num[19]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[18]~61 ), + .combout(\data_num[19]~62_combout ), + .cout(\data_num[19]~63 )); +// synopsys translate_off +defparam \data_num[19]~62 .lut_mask = 16'h3C3F; +defparam \data_num[19]~62 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N16 +cycloneive_lcell_comb \data_num[20]~64 ( +// Equation(s): +// \data_num[20]~64_combout = (data_num[20] & (\data_num[19]~63 $ (GND))) # (!data_num[20] & (!\data_num[19]~63 & VCC)) +// \data_num[20]~65 = CARRY((data_num[20] & !\data_num[19]~63 )) + + .dataa(gnd), + .datab(data_num[20]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[19]~63 ), + .combout(\data_num[20]~64_combout ), + .cout(\data_num[20]~65 )); +// synopsys translate_off +defparam \data_num[20]~64 .lut_mask = 16'hC30C; +defparam \data_num[20]~64 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N18 +cycloneive_lcell_comb \data_num[21]~66 ( +// Equation(s): +// \data_num[21]~66_combout = (data_num[21] & (!\data_num[20]~65 )) # (!data_num[21] & ((\data_num[20]~65 ) # (GND))) +// \data_num[21]~67 = CARRY((!\data_num[20]~65 ) # (!data_num[21])) + + .dataa(gnd), + .datab(data_num[21]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[20]~65 ), + .combout(\data_num[21]~66_combout ), + .cout(\data_num[21]~67 )); +// synopsys translate_off +defparam \data_num[21]~66 .lut_mask = 16'h3C3F; +defparam \data_num[21]~66 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N20 +cycloneive_lcell_comb \data_num[22]~68 ( +// Equation(s): +// \data_num[22]~68_combout = (data_num[22] & (\data_num[21]~67 $ (GND))) # (!data_num[22] & (!\data_num[21]~67 & VCC)) +// \data_num[22]~69 = CARRY((data_num[22] & !\data_num[21]~67 )) + + .dataa(gnd), + .datab(data_num[22]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[21]~67 ), + .combout(\data_num[22]~68_combout ), + .cout(\data_num[22]~69 )); +// synopsys translate_off +defparam \data_num[22]~68 .lut_mask = 16'hC30C; +defparam \data_num[22]~68 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N22 +cycloneive_lcell_comb \data_num[23]~70 ( +// Equation(s): +// \data_num[23]~70_combout = data_num[23] $ (\data_num[22]~69 ) + + .dataa(data_num[23]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_num[22]~69 ), + .combout(\data_num[23]~70_combout ), + .cout()); +// synopsys translate_off +defparam \data_num[23]~70 .lut_mask = 16'h5A5A; +defparam \data_num[23]~70 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y26_N3 +dffeas \fifo_read_inst|cnt_read[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[1]~12_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N7 +dffeas \fifo_read_inst|cnt_read[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[3]~16_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N1 +dffeas \fifo_read_inst|cnt_read[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[0]~10_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N5 +dffeas \fifo_read_inst|cnt_read[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[2]~14_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N9 +dffeas \fifo_read_inst|cnt_read[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[4]~18_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N11 +dffeas \fifo_read_inst|cnt_read[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[5]~20_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N13 +dffeas \fifo_read_inst|cnt_read[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[6]~22_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N15 +dffeas \fifo_read_inst|cnt_read[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[7]~24_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N17 +dffeas \fifo_read_inst|cnt_read[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[8]~26_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N19 +dffeas \fifo_read_inst|cnt_read[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[9]~28_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N24 +cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( +// Equation(s): +// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_cnt [0] & (\uart_rx_inst|bit_flag~q $ (VCC))) # (!\uart_rx_inst|bit_cnt [0] & (\uart_rx_inst|bit_flag~q & VCC)) +// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_cnt [0] & \uart_rx_inst|bit_flag~q )) + + .dataa(\uart_rx_inst|bit_cnt [0]), + .datab(\uart_rx_inst|bit_flag~q ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|Add1~0_combout ), + .cout(\uart_rx_inst|Add1~1 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; +defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N28 +cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( +// Equation(s): +// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) +// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~3 ), + .combout(\uart_rx_inst|Add1~4_combout ), + .cout(\uart_rx_inst|Add1~5 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N30 +cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( +// Equation(s): +// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|Add1~5 $ (\uart_rx_inst|bit_cnt [3]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(\uart_rx_inst|Add1~5 ), + .combout(\uart_rx_inst|Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h0FF0; +defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N11 +dffeas \uart_rx_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N0 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[0]~10 ( +// Equation(s): +// \fifo_read_inst|cnt_read[0]~10_combout = (\fifo_read_inst|rd_en~q & (\fifo_read_inst|cnt_read [0] $ (VCC))) # (!\fifo_read_inst|rd_en~q & (\fifo_read_inst|cnt_read [0] & VCC)) +// \fifo_read_inst|cnt_read[0]~11 = CARRY((\fifo_read_inst|rd_en~q & \fifo_read_inst|cnt_read [0])) + + .dataa(\fifo_read_inst|rd_en~q ), + .datab(\fifo_read_inst|cnt_read [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|cnt_read[0]~10_combout ), + .cout(\fifo_read_inst|cnt_read[0]~11 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[0]~10 .lut_mask = 16'h6688; +defparam \fifo_read_inst|cnt_read[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N2 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[1]~12 ( +// Equation(s): +// \fifo_read_inst|cnt_read[1]~12_combout = (\fifo_read_inst|cnt_read [1] & (!\fifo_read_inst|cnt_read[0]~11 )) # (!\fifo_read_inst|cnt_read [1] & ((\fifo_read_inst|cnt_read[0]~11 ) # (GND))) +// \fifo_read_inst|cnt_read[1]~13 = CARRY((!\fifo_read_inst|cnt_read[0]~11 ) # (!\fifo_read_inst|cnt_read [1])) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [1]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[0]~11 ), + .combout(\fifo_read_inst|cnt_read[1]~12_combout ), + .cout(\fifo_read_inst|cnt_read[1]~13 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[1]~12 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|cnt_read[1]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N4 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[2]~14 ( +// Equation(s): +// \fifo_read_inst|cnt_read[2]~14_combout = (\fifo_read_inst|cnt_read [2] & (\fifo_read_inst|cnt_read[1]~13 $ (GND))) # (!\fifo_read_inst|cnt_read [2] & (!\fifo_read_inst|cnt_read[1]~13 & VCC)) +// \fifo_read_inst|cnt_read[2]~15 = CARRY((\fifo_read_inst|cnt_read [2] & !\fifo_read_inst|cnt_read[1]~13 )) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [2]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[1]~13 ), + .combout(\fifo_read_inst|cnt_read[2]~14_combout ), + .cout(\fifo_read_inst|cnt_read[2]~15 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[2]~14 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|cnt_read[2]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N6 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[3]~16 ( +// Equation(s): +// \fifo_read_inst|cnt_read[3]~16_combout = (\fifo_read_inst|cnt_read [3] & (!\fifo_read_inst|cnt_read[2]~15 )) # (!\fifo_read_inst|cnt_read [3] & ((\fifo_read_inst|cnt_read[2]~15 ) # (GND))) +// \fifo_read_inst|cnt_read[3]~17 = CARRY((!\fifo_read_inst|cnt_read[2]~15 ) # (!\fifo_read_inst|cnt_read [3])) + + .dataa(\fifo_read_inst|cnt_read [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[2]~15 ), + .combout(\fifo_read_inst|cnt_read[3]~16_combout ), + .cout(\fifo_read_inst|cnt_read[3]~17 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[3]~16 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|cnt_read[3]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N8 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[4]~18 ( +// Equation(s): +// \fifo_read_inst|cnt_read[4]~18_combout = (\fifo_read_inst|cnt_read [4] & (\fifo_read_inst|cnt_read[3]~17 $ (GND))) # (!\fifo_read_inst|cnt_read [4] & (!\fifo_read_inst|cnt_read[3]~17 & VCC)) +// \fifo_read_inst|cnt_read[4]~19 = CARRY((\fifo_read_inst|cnt_read [4] & !\fifo_read_inst|cnt_read[3]~17 )) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [4]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[3]~17 ), + .combout(\fifo_read_inst|cnt_read[4]~18_combout ), + .cout(\fifo_read_inst|cnt_read[4]~19 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[4]~18 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|cnt_read[4]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N10 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[5]~20 ( +// Equation(s): +// \fifo_read_inst|cnt_read[5]~20_combout = (\fifo_read_inst|cnt_read [5] & (!\fifo_read_inst|cnt_read[4]~19 )) # (!\fifo_read_inst|cnt_read [5] & ((\fifo_read_inst|cnt_read[4]~19 ) # (GND))) +// \fifo_read_inst|cnt_read[5]~21 = CARRY((!\fifo_read_inst|cnt_read[4]~19 ) # (!\fifo_read_inst|cnt_read [5])) + + .dataa(\fifo_read_inst|cnt_read [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[4]~19 ), + .combout(\fifo_read_inst|cnt_read[5]~20_combout ), + .cout(\fifo_read_inst|cnt_read[5]~21 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[5]~20 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|cnt_read[5]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N12 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[6]~22 ( +// Equation(s): +// \fifo_read_inst|cnt_read[6]~22_combout = (\fifo_read_inst|cnt_read [6] & (\fifo_read_inst|cnt_read[5]~21 $ (GND))) # (!\fifo_read_inst|cnt_read [6] & (!\fifo_read_inst|cnt_read[5]~21 & VCC)) +// \fifo_read_inst|cnt_read[6]~23 = CARRY((\fifo_read_inst|cnt_read [6] & !\fifo_read_inst|cnt_read[5]~21 )) + + .dataa(\fifo_read_inst|cnt_read [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[5]~21 ), + .combout(\fifo_read_inst|cnt_read[6]~22_combout ), + .cout(\fifo_read_inst|cnt_read[6]~23 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[6]~22 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|cnt_read[6]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N14 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[7]~24 ( +// Equation(s): +// \fifo_read_inst|cnt_read[7]~24_combout = (\fifo_read_inst|cnt_read [7] & (!\fifo_read_inst|cnt_read[6]~23 )) # (!\fifo_read_inst|cnt_read [7] & ((\fifo_read_inst|cnt_read[6]~23 ) # (GND))) +// \fifo_read_inst|cnt_read[7]~25 = CARRY((!\fifo_read_inst|cnt_read[6]~23 ) # (!\fifo_read_inst|cnt_read [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[6]~23 ), + .combout(\fifo_read_inst|cnt_read[7]~24_combout ), + .cout(\fifo_read_inst|cnt_read[7]~25 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[7]~24 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|cnt_read[7]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N16 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[8]~26 ( +// Equation(s): +// \fifo_read_inst|cnt_read[8]~26_combout = (\fifo_read_inst|cnt_read [8] & (\fifo_read_inst|cnt_read[7]~25 $ (GND))) # (!\fifo_read_inst|cnt_read [8] & (!\fifo_read_inst|cnt_read[7]~25 & VCC)) +// \fifo_read_inst|cnt_read[8]~27 = CARRY((\fifo_read_inst|cnt_read [8] & !\fifo_read_inst|cnt_read[7]~25 )) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [8]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[7]~25 ), + .combout(\fifo_read_inst|cnt_read[8]~26_combout ), + .cout(\fifo_read_inst|cnt_read[8]~27 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[8]~26 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|cnt_read[8]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N18 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[9]~28 ( +// Equation(s): +// \fifo_read_inst|cnt_read[9]~28_combout = \fifo_read_inst|cnt_read [9] $ (\fifo_read_inst|cnt_read[8]~27 ) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [9]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|cnt_read[8]~27 ), + .combout(\fifo_read_inst|cnt_read[9]~28_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[9]~28 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|cnt_read[9]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N10 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) +// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[3]~20 ), + .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_rx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X22_Y22_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y22_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y22_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [0])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [0]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0 .lut_mask = 16'h8C9D; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N13 +dffeas \uart_tx_inst|bit_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[0]~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( +// Equation(s): +// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b +// [4])) # (!\uart_tx_inst|bit_cnt [0] & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [3]))))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [4]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [3]), + .datad(\uart_tx_inst|bit_cnt [0]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hEE30; +defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N8 +cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( +// Equation(s): +// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|Mux0~0_combout & (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [6]) # (!\uart_tx_inst|bit_cnt [1])))) # (!\uart_tx_inst|Mux0~0_combout & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [5] & ((\uart_tx_inst|bit_cnt [1])))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [5]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [6]), + .datac(\uart_tx_inst|Mux0~0_combout ), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hCAF0; +defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \uart_tx_inst|tx~0 ( +// Equation(s): +// \uart_tx_inst|tx~0_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [2]))) # (!\uart_tx_inst|bit_cnt [1] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [0])))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [0]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~0 .lut_mask = 16'hA088; +defparam \uart_tx_inst|tx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \uart_tx_inst|tx~1 ( +// Equation(s): +// \uart_tx_inst|tx~1_combout = (\uart_tx_inst|tx~0_combout ) # ((!\uart_tx_inst|bit_cnt [0] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [1] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|tx~0_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [1]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~1 .lut_mask = 16'hDCCC; +defparam \uart_tx_inst|tx~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \uart_tx_inst|tx~2 ( +// Equation(s): +// \uart_tx_inst|tx~2_combout = (\uart_tx_inst|bit_flag~q & ((\uart_tx_inst|bit_cnt [2] & (\uart_tx_inst|Mux0~1_combout )) # (!\uart_tx_inst|bit_cnt [2] & ((\uart_tx_inst|tx~1_combout ))))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\uart_tx_inst|Mux0~1_combout ), + .datad(\uart_tx_inst|tx~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~2 .lut_mask = 16'hA280; +defparam \uart_tx_inst|tx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N27 +dffeas \uart_tx_inst|bit_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[3]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y21_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0 .lut_mask = 16'hFFAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0 .lut_mask = 16'h3111; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ) # (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1 .lut_mask = 16'hAFEF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0 .lut_mask = 16'h0CAE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( +// Equation(s): +// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(gnd), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h5AF0; +defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( +// Equation(s): +// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [0] & (\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|bit_cnt [1])))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h78F0; +defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~4 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[3]~4_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [3]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) + + .dataa(\uart_tx_inst|Add1~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3]~4 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0 .lut_mask = 16'h0400; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y22_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y22_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y20_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y20_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N29 +dffeas read_valid( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\read_valid~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\read_valid~q ), + .prn(vcc)); +// synopsys translate_off +defparam read_valid.is_wysiwyg = "true"; +defparam read_valid.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0 .lut_mask = 16'h000F; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout = (\read_valid~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & ((\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout )))) + + .dataa(\read_valid~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1 .lut_mask = 16'h8088; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0 .lut_mask = 16'hFAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[13] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N12 +cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( +// Equation(s): +// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [12] & \uart_tx_inst|baud_cnt [10]) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(gnd), + .datad(\uart_tx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hCC00; +defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N25 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N2 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout = (\fifo_read_inst|read_en_dly~q & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9] & !\fifo_read_inst|rd_en~q ))) + + .dataa(\fifo_read_inst|read_en_dly~q ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .lut_mask = 16'h0080; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N23 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N21 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N19 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N17 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N0 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] & +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .lut_mask = 16'h8000; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N15 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N11 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N26 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] & +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .lut_mask = 16'h8000; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] & +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .lut_mask = 16'h8000; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N13 +dffeas \fifo_read_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|Add2~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N28 +cycloneive_lcell_comb \fifo_read_inst|Equal1~0 ( +// Equation(s): +// \fifo_read_inst|Equal1~0_combout = (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] & (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .cin(gnd), + .combout(\fifo_read_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal1~0 .lut_mask = 16'h0001; +defparam \fifo_read_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N2 +cycloneive_lcell_comb \fifo_read_inst|Equal1~1 ( +// Equation(s): +// \fifo_read_inst|Equal1~1_combout = (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] & (\fifo_read_inst|Equal1~0_combout & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] & !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .datab(\fifo_read_inst|Equal1~0_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .cin(gnd), + .combout(\fifo_read_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal1~1 .lut_mask = 16'h0004; +defparam \fifo_read_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .lut_mask = 16'h50F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y23_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5 .lut_mask = 16'h9966; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y20_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2 .lut_mask = 16'h9696; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y26_N25 +dffeas \cnt_wait[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[15]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[15]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[15] .is_wysiwyg = "true"; +defparam \cnt_wait[15] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N27 +dffeas \cnt_wait[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[14]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[14]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[14] .is_wysiwyg = "true"; +defparam \cnt_wait[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N21 +dffeas \cnt_wait[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[13]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[13]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[13] .is_wysiwyg = "true"; +defparam \cnt_wait[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N23 +dffeas \cnt_wait[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[12]~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[12]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[12] .is_wysiwyg = "true"; +defparam \cnt_wait[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N8 +cycloneive_lcell_comb \Equal0~0 ( +// Equation(s): +// \Equal0~0_combout = (!cnt_wait[12] & (!cnt_wait[15] & (!cnt_wait[14] & !cnt_wait[13]))) + + .dataa(cnt_wait[12]), + .datab(cnt_wait[15]), + .datac(cnt_wait[14]), + .datad(cnt_wait[13]), + .cin(gnd), + .combout(\Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~0 .lut_mask = 16'h0001; +defparam \Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y26_N23 +dffeas \cnt_wait[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[9]~6_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[9]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[9] .is_wysiwyg = "true"; +defparam \cnt_wait[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N9 +dffeas \cnt_wait[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[11]~7_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[11]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[11] .is_wysiwyg = "true"; +defparam \cnt_wait[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N11 +dffeas \cnt_wait[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[10]~8_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[10]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[10] .is_wysiwyg = "true"; +defparam \cnt_wait[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N5 +dffeas \cnt_wait[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[8]~9_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[8]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[8] .is_wysiwyg = "true"; +defparam \cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N14 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (!cnt_wait[10] & (!cnt_wait[8] & (cnt_wait[9] & !cnt_wait[11]))) + + .dataa(cnt_wait[10]), + .datab(cnt_wait[8]), + .datac(cnt_wait[9]), + .datad(cnt_wait[11]), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0010; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y26_N3 +dffeas \cnt_wait[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[7]~10_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[7]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[7] .is_wysiwyg = "true"; +defparam \cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N13 +dffeas \cnt_wait[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[6]~11_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[6]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[6] .is_wysiwyg = "true"; +defparam \cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N15 +dffeas \cnt_wait[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[5]~12_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[5]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[5] .is_wysiwyg = "true"; +defparam \cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N17 +dffeas \cnt_wait[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[4]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[4]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[4] .is_wysiwyg = "true"; +defparam \cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N10 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (cnt_wait[6] & (cnt_wait[7] & (cnt_wait[5] & !cnt_wait[4]))) + + .dataa(cnt_wait[6]), + .datab(cnt_wait[7]), + .datac(cnt_wait[5]), + .datad(cnt_wait[4]), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0080; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y26_N5 +dffeas \cnt_wait[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[3]~14_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[3]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[3] .is_wysiwyg = "true"; +defparam \cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N7 +dffeas \cnt_wait[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[2]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[2]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[2] .is_wysiwyg = "true"; +defparam \cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N1 +dffeas \cnt_wait[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[1]~16_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[1]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[1] .is_wysiwyg = "true"; +defparam \cnt_wait[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N19 +dffeas \cnt_wait[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[0]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[0]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[0] .is_wysiwyg = "true"; +defparam \cnt_wait[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N28 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (!cnt_wait[0] & (cnt_wait[1] & (cnt_wait[3] & cnt_wait[2]))) + + .dataa(cnt_wait[0]), + .datab(cnt_wait[1]), + .datac(cnt_wait[3]), + .datad(cnt_wait[2]), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h4000; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N30 +cycloneive_lcell_comb \Equal0~4 ( +// Equation(s): +// \Equal0~4_combout = (\Equal0~2_combout & (\Equal0~3_combout & (\Equal0~0_combout & \Equal0~1_combout ))) + + .dataa(\Equal0~2_combout ), + .datab(\Equal0~3_combout ), + .datac(\Equal0~0_combout ), + .datad(\Equal0~1_combout ), + .cin(gnd), + .combout(\Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~4 .lut_mask = 16'h8000; +defparam \Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N16 +cycloneive_lcell_comb \read_valid~0 ( +// Equation(s): +// \read_valid~0_combout = (\Equal0~4_combout ) # ((\read_valid~q & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ) # (!\Equal2~1_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\Equal0~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .datad(\read_valid~q ), + .cin(gnd), + .combout(\read_valid~0_combout ), + .cout()); +// synopsys translate_off +defparam \read_valid~0 .lut_mask = 16'hFDCC; +defparam \read_valid~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N28 +cycloneive_lcell_comb \read_valid~1 ( +// Equation(s): +// \read_valid~1_combout = (\read_valid~0_combout ) # ((\read_valid~q & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ) # (!\Equal2~0_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .datab(\Equal2~0_combout ), + .datac(\read_valid~q ), + .datad(\read_valid~0_combout ), + .cin(gnd), + .combout(\read_valid~1_combout ), + .cout()); +// synopsys translate_off +defparam \read_valid~1 .lut_mask = 16'hFFB0; +defparam \read_valid~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0 .lut_mask = 16'hECFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk +// [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3] $ (((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0 .lut_mask = 16'h6AAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2 .lut_mask = 16'hC0C0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N10 +cycloneive_lcell_comb \fifo_read_inst|Equal1~2 ( +// Equation(s): +// \fifo_read_inst|Equal1~2_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] & \fifo_read_inst|Equal1~1_combout )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datac(gnd), + .datad(\fifo_read_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\fifo_read_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal1~2 .lut_mask = 16'h2200; +defparam \fifo_read_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N2 +cycloneive_lcell_comb \fifo_read_inst|Equal5~1 ( +// Equation(s): +// \fifo_read_inst|Equal5~1_combout = (\fifo_read_inst|baud_cnt [11] & (!\fifo_read_inst|baud_cnt [10] & (\fifo_read_inst|baud_cnt [9] & !\fifo_read_inst|baud_cnt [6]))) + + .dataa(\fifo_read_inst|baud_cnt [11]), + .datab(\fifo_read_inst|baud_cnt [10]), + .datac(\fifo_read_inst|baud_cnt [9]), + .datad(\fifo_read_inst|baud_cnt [6]), + .cin(gnd), + .combout(\fifo_read_inst|Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal5~1 .lut_mask = 16'h0020; +defparam \fifo_read_inst|Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h4182; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'hF000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'hC000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout +// )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8 .lut_mask = 16'hCA0A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'h4812; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'h8008; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h2814; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'h8200; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout )) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'hF5A0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h2814; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'hE0C2; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h0004; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N0 +cycloneive_lcell_comb \Equal1~0 ( +// Equation(s): +// \Equal1~0_combout = (data_num[2]) # (((data_num[0]) # (!data_num[1])) # (!data_num[3])) + + .dataa(data_num[2]), + .datab(data_num[3]), + .datac(data_num[0]), + .datad(data_num[1]), + .cin(gnd), + .combout(\Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~0 .lut_mask = 16'hFBFF; +defparam \Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N2 +cycloneive_lcell_comb \Equal1~1 ( +// Equation(s): +// \Equal1~1_combout = (data_num[6]) # ((data_num[5]) # ((data_num[7]) # (data_num[4]))) + + .dataa(data_num[6]), + .datab(data_num[5]), + .datac(data_num[7]), + .datad(data_num[4]), + .cin(gnd), + .combout(\Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~1 .lut_mask = 16'hFFFE; +defparam \Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N4 +cycloneive_lcell_comb \Equal1~2 ( +// Equation(s): +// \Equal1~2_combout = (data_num[11]) # ((data_num[10]) # ((data_num[9]) # (data_num[8]))) + + .dataa(data_num[11]), + .datab(data_num[10]), + .datac(data_num[9]), + .datad(data_num[8]), + .cin(gnd), + .combout(\Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~2 .lut_mask = 16'hFFFE; +defparam \Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N24 +cycloneive_lcell_comb \Equal1~3 ( +// Equation(s): +// \Equal1~3_combout = (data_num[15]) # ((data_num[13]) # ((data_num[14]) # (data_num[12]))) + + .dataa(data_num[15]), + .datab(data_num[13]), + .datac(data_num[14]), + .datad(data_num[12]), + .cin(gnd), + .combout(\Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~3 .lut_mask = 16'hFFFE; +defparam \Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N6 +cycloneive_lcell_comb \Equal1~4 ( +// Equation(s): +// \Equal1~4_combout = (\Equal1~3_combout ) # ((\Equal1~1_combout ) # ((\Equal1~2_combout ) # (\Equal1~0_combout ))) + + .dataa(\Equal1~3_combout ), + .datab(\Equal1~1_combout ), + .datac(\Equal1~2_combout ), + .datad(\Equal1~0_combout ), + .cin(gnd), + .combout(\Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~4 .lut_mask = 16'hFFFE; +defparam \Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N26 +cycloneive_lcell_comb \Equal1~5 ( +// Equation(s): +// \Equal1~5_combout = (data_num[18]) # ((data_num[19]) # ((data_num[16]) # (data_num[17]))) + + .dataa(data_num[18]), + .datab(data_num[19]), + .datac(data_num[16]), + .datad(data_num[17]), + .cin(gnd), + .combout(\Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~5 .lut_mask = 16'hFFFE; +defparam \Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N28 +cycloneive_lcell_comb \Equal1~6 ( +// Equation(s): +// \Equal1~6_combout = (data_num[22]) # ((data_num[21]) # ((data_num[23]) # (data_num[20]))) + + .dataa(data_num[22]), + .datab(data_num[21]), + .datac(data_num[23]), + .datad(data_num[20]), + .cin(gnd), + .combout(\Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~6 .lut_mask = 16'hFFFE; +defparam \Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N18 +cycloneive_lcell_comb \cnt_wait[8]~0 ( +// Equation(s): +// \cnt_wait[8]~0_combout = (!\Equal0~4_combout & ((\Equal1~4_combout ) # ((\Equal1~5_combout ) # (\Equal1~6_combout )))) + + .dataa(\Equal1~4_combout ), + .datab(\Equal0~4_combout ), + .datac(\Equal1~5_combout ), + .datad(\Equal1~6_combout ), + .cin(gnd), + .combout(\cnt_wait[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[8]~0 .lut_mask = 16'h3332; +defparam \cnt_wait[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N12 +cycloneive_lcell_comb \cnt_wait[15]~1 ( +// Equation(s): +// \cnt_wait[15]~1_combout = (\Equal1~4_combout ) # ((\Equal0~4_combout ) # ((\Equal1~5_combout ) # (\Equal1~6_combout ))) + + .dataa(\Equal1~4_combout ), + .datab(\Equal0~4_combout ), + .datac(\Equal1~5_combout ), + .datad(\Equal1~6_combout ), + .cin(gnd), + .combout(\cnt_wait[15]~1_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[15]~1 .lut_mask = 16'hFFFE; +defparam \cnt_wait[15]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N24 +cycloneive_lcell_comb \cnt_wait[15]~2 ( +// Equation(s): +// \cnt_wait[15]~2_combout = (\Add1~30_combout & (((\cnt_wait[8]~0_combout & cnt_wait[15])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~30_combout & (\cnt_wait[8]~0_combout & (cnt_wait[15]))) + + .dataa(\Add1~30_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[15]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[15]~2_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[15]~2 .lut_mask = 16'hC0EA; +defparam \cnt_wait[15]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N26 +cycloneive_lcell_comb \cnt_wait[14]~3 ( +// Equation(s): +// \cnt_wait[14]~3_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[14] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~28_combout ) # ((cnt_wait[14] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~28_combout ), + .datac(cnt_wait[14]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[14]~3_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[14]~3 .lut_mask = 16'hF444; +defparam \cnt_wait[14]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N20 +cycloneive_lcell_comb \cnt_wait[13]~4 ( +// Equation(s): +// \cnt_wait[13]~4_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[13] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~26_combout ) # ((cnt_wait[13] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~26_combout ), + .datac(cnt_wait[13]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[13]~4_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[13]~4 .lut_mask = 16'hF444; +defparam \cnt_wait[13]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N22 +cycloneive_lcell_comb \cnt_wait[12]~5 ( +// Equation(s): +// \cnt_wait[12]~5_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[12] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~24_combout ) # ((cnt_wait[12] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~24_combout ), + .datac(cnt_wait[12]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[12]~5_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[12]~5 .lut_mask = 16'hF444; +defparam \cnt_wait[12]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N22 +cycloneive_lcell_comb \cnt_wait[9]~6 ( +// Equation(s): +// \cnt_wait[9]~6_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[9] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~18_combout ) # ((cnt_wait[9] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~18_combout ), + .datac(cnt_wait[9]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[9]~6_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[9]~6 .lut_mask = 16'hF444; +defparam \cnt_wait[9]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N8 +cycloneive_lcell_comb \cnt_wait[11]~7 ( +// Equation(s): +// \cnt_wait[11]~7_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[11] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~22_combout ) # ((cnt_wait[11] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~22_combout ), + .datac(cnt_wait[11]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[11]~7_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[11]~7 .lut_mask = 16'hF444; +defparam \cnt_wait[11]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N10 +cycloneive_lcell_comb \cnt_wait[10]~8 ( +// Equation(s): +// \cnt_wait[10]~8_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[10] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~20_combout ) # ((cnt_wait[10] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~20_combout ), + .datac(cnt_wait[10]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[10]~8_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[10]~8 .lut_mask = 16'hF444; +defparam \cnt_wait[10]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N4 +cycloneive_lcell_comb \cnt_wait[8]~9 ( +// Equation(s): +// \cnt_wait[8]~9_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[8] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~16_combout ) # ((cnt_wait[8] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~16_combout ), + .datac(cnt_wait[8]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[8]~9_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[8]~9 .lut_mask = 16'hF444; +defparam \cnt_wait[8]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N2 +cycloneive_lcell_comb \cnt_wait[7]~10 ( +// Equation(s): +// \cnt_wait[7]~10_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[7] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~14_combout ) # ((cnt_wait[7] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~14_combout ), + .datac(cnt_wait[7]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[7]~10_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[7]~10 .lut_mask = 16'hF444; +defparam \cnt_wait[7]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N12 +cycloneive_lcell_comb \cnt_wait[6]~11 ( +// Equation(s): +// \cnt_wait[6]~11_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[6] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~12_combout ) # ((cnt_wait[6] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~12_combout ), + .datac(cnt_wait[6]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[6]~11_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[6]~11 .lut_mask = 16'hF444; +defparam \cnt_wait[6]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N14 +cycloneive_lcell_comb \cnt_wait[5]~12 ( +// Equation(s): +// \cnt_wait[5]~12_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[5] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~10_combout ) # ((cnt_wait[5] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~10_combout ), + .datac(cnt_wait[5]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[5]~12_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[5]~12 .lut_mask = 16'hF444; +defparam \cnt_wait[5]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N16 +cycloneive_lcell_comb \cnt_wait[4]~13 ( +// Equation(s): +// \cnt_wait[4]~13_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[4] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~8_combout ) # ((cnt_wait[4] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~8_combout ), + .datac(cnt_wait[4]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[4]~13 .lut_mask = 16'hF444; +defparam \cnt_wait[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N4 +cycloneive_lcell_comb \cnt_wait[3]~14 ( +// Equation(s): +// \cnt_wait[3]~14_combout = (\Add1~6_combout & (((\cnt_wait[8]~0_combout & cnt_wait[3])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~6_combout & (\cnt_wait[8]~0_combout & (cnt_wait[3]))) + + .dataa(\Add1~6_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[3]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[3]~14 .lut_mask = 16'hC0EA; +defparam \cnt_wait[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N6 +cycloneive_lcell_comb \cnt_wait[2]~15 ( +// Equation(s): +// \cnt_wait[2]~15_combout = (\Add1~4_combout & (((\cnt_wait[8]~0_combout & cnt_wait[2])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~4_combout & (\cnt_wait[8]~0_combout & (cnt_wait[2]))) + + .dataa(\Add1~4_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[2]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[2]~15_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[2]~15 .lut_mask = 16'hC0EA; +defparam \cnt_wait[2]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N0 +cycloneive_lcell_comb \cnt_wait[1]~16 ( +// Equation(s): +// \cnt_wait[1]~16_combout = (\Add1~2_combout & (((\cnt_wait[8]~0_combout & cnt_wait[1])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~2_combout & (\cnt_wait[8]~0_combout & (cnt_wait[1]))) + + .dataa(\Add1~2_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[1]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[1]~16 .lut_mask = 16'hC0EA; +defparam \cnt_wait[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N18 +cycloneive_lcell_comb \cnt_wait[0]~17 ( +// Equation(s): +// \cnt_wait[0]~17_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[0] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~0_combout ) # ((cnt_wait[0] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~0_combout ), + .datac(cnt_wait[0]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[0]~17 .lut_mask = 16'hF444; +defparam \cnt_wait[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h4812; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h0084; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ) # +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout +// & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'hAAEA; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h4812; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h4182; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout +// )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'hB830; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h0004; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N1 +dffeas \fifo_read_inst|rd_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|rd_flag~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|rd_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|rd_flag .is_wysiwyg = "true"; +defparam \fifo_read_inst|rd_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N30 +cycloneive_lcell_comb \fifo_read_inst|Equal4~2 ( +// Equation(s): +// \fifo_read_inst|Equal4~2_combout = (!\fifo_read_inst|baud_cnt [11] & (\fifo_read_inst|baud_cnt [10] & (!\fifo_read_inst|baud_cnt [9] & \fifo_read_inst|baud_cnt [6]))) + + .dataa(\fifo_read_inst|baud_cnt [11]), + .datab(\fifo_read_inst|baud_cnt [10]), + .datac(\fifo_read_inst|baud_cnt [9]), + .datad(\fifo_read_inst|baud_cnt [6]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~2 .lut_mask = 16'h0400; +defparam \fifo_read_inst|Equal4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout & ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0 .lut_mask = 16'h1030; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N23 +dffeas \uart_rx_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N28 +cycloneive_lcell_comb \fifo_read_inst|Equal2~0 ( +// Equation(s): +// \fifo_read_inst|Equal2~0_combout = (\fifo_read_inst|cnt_read [3] & (\fifo_read_inst|cnt_read [1] & (!\fifo_read_inst|cnt_read [2] & !\fifo_read_inst|cnt_read [0]))) + + .dataa(\fifo_read_inst|cnt_read [3]), + .datab(\fifo_read_inst|cnt_read [1]), + .datac(\fifo_read_inst|cnt_read [2]), + .datad(\fifo_read_inst|cnt_read [0]), + .cin(gnd), + .combout(\fifo_read_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal2~0 .lut_mask = 16'h0008; +defparam \fifo_read_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N30 +cycloneive_lcell_comb \fifo_read_inst|Equal2~1 ( +// Equation(s): +// \fifo_read_inst|Equal2~1_combout = (!\fifo_read_inst|cnt_read [6] & (!\fifo_read_inst|cnt_read [7] & (!\fifo_read_inst|cnt_read [4] & !\fifo_read_inst|cnt_read [5]))) + + .dataa(\fifo_read_inst|cnt_read [6]), + .datab(\fifo_read_inst|cnt_read [7]), + .datac(\fifo_read_inst|cnt_read [4]), + .datad(\fifo_read_inst|cnt_read [5]), + .cin(gnd), + .combout(\fifo_read_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal2~1 .lut_mask = 16'h0001; +defparam \fifo_read_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N24 +cycloneive_lcell_comb \fifo_read_inst|Equal2~2 ( +// Equation(s): +// \fifo_read_inst|Equal2~2_combout = (\fifo_read_inst|Equal2~0_combout & (!\fifo_read_inst|cnt_read [9] & (\fifo_read_inst|Equal2~1_combout & !\fifo_read_inst|cnt_read [8]))) + + .dataa(\fifo_read_inst|Equal2~0_combout ), + .datab(\fifo_read_inst|cnt_read [9]), + .datac(\fifo_read_inst|Equal2~1_combout ), + .datad(\fifo_read_inst|cnt_read [8]), + .cin(gnd), + .combout(\fifo_read_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal2~2 .lut_mask = 16'h0020; +defparam \fifo_read_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N0 +cycloneive_lcell_comb \fifo_read_inst|rd_flag~0 ( +// Equation(s): +// \fifo_read_inst|rd_flag~0_combout = (!\fifo_read_inst|Equal2~2_combout & ((\fifo_read_inst|rd_flag~q ) # ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] & +// \fifo_read_inst|Equal1~2_combout )))) + + .dataa(\fifo_read_inst|Equal2~2_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datac(\fifo_read_inst|rd_flag~q ), + .datad(\fifo_read_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\fifo_read_inst|rd_flag~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|rd_flag~0 .lut_mask = 16'h5450; +defparam \fifo_read_inst|rd_flag~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N22 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~1_combout = (\uart_rx_inst|Add1~0_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_flag~q )) # (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(\uart_rx_inst|bit_cnt [3]), + .datab(\uart_rx_inst|Add1~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h4CCC; +defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N7 +dffeas \uart_rx_inst|work_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_rx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y24_N7 +dffeas \uart_rx_inst|start_nedge ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|start_nedge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; +defparam \uart_rx_inst|start_nedge .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N6 +cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( +// Equation(s): +// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) + + .dataa(gnd), + .datab(\uart_rx_inst|start_nedge~q ), + .datac(\uart_rx_inst|work_en~q ), + .datad(\uart_rx_inst|always4~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hCCFC; +defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N6 +cycloneive_lcell_comb \uart_rx_inst|always3~0 ( +// Equation(s): +// \uart_rx_inst|always3~0_combout = (\uart_rx_inst|rx_reg2~q & !\uart_rx_inst|rx_reg3~q ) + + .dataa(gnd), + .datab(\uart_rx_inst|rx_reg2~q ), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg3~q ), + .cin(gnd), + .combout(\uart_rx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always3~0 .lut_mask = 16'h00CC; +defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|bit_flag~q & \uart_tx_inst|work_en~q ))))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h1230; +defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y9_N16 +cycloneive_io_obuf \tx~output ( + .i(!\uart_tx_inst|tx~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tx), + .obar()); +// synopsys translate_off +defparam \tx~output .bus_hold = "false"; +defparam \tx~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y29_N30 +cycloneive_io_obuf \sdram_clk~output ( + .i(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_clk), + .obar()); +// synopsys translate_off +defparam \sdram_clk~output .bus_hold = "false"; +defparam \sdram_clk~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y13_N23 +cycloneive_io_obuf \sdram_cke~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_cke), + .obar()); +// synopsys translate_off +defparam \sdram_cke~output .bus_hold = "false"; +defparam \sdram_cke~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N9 +cycloneive_io_obuf \sdram_cs_n~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_cs_n), + .obar()); +// synopsys translate_off +defparam \sdram_cs_n~output .bus_hold = "false"; +defparam \sdram_cs_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y29_N16 +cycloneive_io_obuf \sdram_cas_n~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_cas_n), + .obar()); +// synopsys translate_off +defparam \sdram_cas_n~output .bus_hold = "false"; +defparam \sdram_cas_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N16 +cycloneive_io_obuf \sdram_ras_n~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_ras_n), + .obar()); +// synopsys translate_off +defparam \sdram_ras_n~output .bus_hold = "false"; +defparam \sdram_ras_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y29_N9 +cycloneive_io_obuf \sdram_we_n~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_we_n), + .obar()); +// synopsys translate_off +defparam \sdram_we_n~output .bus_hold = "false"; +defparam \sdram_we_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N16 +cycloneive_io_obuf \sdram_ba[0]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_ba[0]), + .obar()); +// synopsys translate_off +defparam \sdram_ba[0]~output .bus_hold = "false"; +defparam \sdram_ba[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y29_N2 +cycloneive_io_obuf \sdram_ba[1]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_ba[1]), + .obar()); +// synopsys translate_off +defparam \sdram_ba[1]~output .bus_hold = "false"; +defparam \sdram_ba[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N9 +cycloneive_io_obuf \sdram_addr[0]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[0]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[0]~output .bus_hold = "false"; +defparam \sdram_addr[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y27_N16 +cycloneive_io_obuf \sdram_addr[1]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[1]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[1]~output .bus_hold = "false"; +defparam \sdram_addr[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y27_N9 +cycloneive_io_obuf \sdram_addr[2]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[2]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[2]~output .bus_hold = "false"; +defparam \sdram_addr[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y26_N23 +cycloneive_io_obuf \sdram_addr[3]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[3]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[3]~output .bus_hold = "false"; +defparam \sdram_addr[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y26_N16 +cycloneive_io_obuf \sdram_addr[4]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[4]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[4]~output .bus_hold = "false"; +defparam \sdram_addr[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y24_N16 +cycloneive_io_obuf \sdram_addr[5]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[5]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[5]~output .bus_hold = "false"; +defparam \sdram_addr[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y23_N2 +cycloneive_io_obuf \sdram_addr[6]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[6]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[6]~output .bus_hold = "false"; +defparam \sdram_addr[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y24_N23 +cycloneive_io_obuf \sdram_addr[7]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[7]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[7]~output .bus_hold = "false"; +defparam \sdram_addr[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N16 +cycloneive_io_obuf \sdram_addr[8]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[8]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[8]~output .bus_hold = "false"; +defparam \sdram_addr[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N16 +cycloneive_io_obuf \sdram_addr[9]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[9]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[9]~output .bus_hold = "false"; +defparam \sdram_addr[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N2 +cycloneive_io_obuf \sdram_addr[10]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[10]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[10]~output .bus_hold = "false"; +defparam \sdram_addr[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N23 +cycloneive_io_obuf \sdram_addr[11]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[11]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[11]~output .bus_hold = "false"; +defparam \sdram_addr[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y13_N16 +cycloneive_io_obuf \sdram_addr[12]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[12]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[12]~output .bus_hold = "false"; +defparam \sdram_addr[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N2 +cycloneive_io_obuf \sdram_dqm[0]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dqm[0]), + .obar()); +// synopsys translate_off +defparam \sdram_dqm[0]~output .bus_hold = "false"; +defparam \sdram_dqm[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y20_N2 +cycloneive_io_obuf \sdram_dqm[1]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dqm[1]), + .obar()); +// synopsys translate_off +defparam \sdram_dqm[1]~output .bus_hold = "false"; +defparam \sdram_dqm[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N9 +cycloneive_io_obuf \sdram_dq[0]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[0]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[0]~output .bus_hold = "false"; +defparam \sdram_dq[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N2 +cycloneive_io_obuf \sdram_dq[1]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[1]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[1]~output .bus_hold = "false"; +defparam \sdram_dq[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y29_N2 +cycloneive_io_obuf \sdram_dq[2]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[2]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[2]~output .bus_hold = "false"; +defparam \sdram_dq[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y29_N30 +cycloneive_io_obuf \sdram_dq[3]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[3]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[3]~output .bus_hold = "false"; +defparam \sdram_dq[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y29_N23 +cycloneive_io_obuf \sdram_dq[4]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[4]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[4]~output .bus_hold = "false"; +defparam \sdram_dq[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y29_N9 +cycloneive_io_obuf \sdram_dq[5]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[5]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[5]~output .bus_hold = "false"; +defparam \sdram_dq[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N16 +cycloneive_io_obuf \sdram_dq[6]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[6]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[6]~output .bus_hold = "false"; +defparam \sdram_dq[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N23 +cycloneive_io_obuf \sdram_dq[7]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[7]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[7]~output .bus_hold = "false"; +defparam \sdram_dq[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y20_N9 +cycloneive_io_obuf \sdram_dq[8]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [8]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[8]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[8]~output .bus_hold = "false"; +defparam \sdram_dq[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N30 +cycloneive_io_obuf \sdram_dq[9]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [9]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[9]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[9]~output .bus_hold = "false"; +defparam \sdram_dq[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y25_N2 +cycloneive_io_obuf \sdram_dq[10]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [10]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[10]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[10]~output .bus_hold = "false"; +defparam \sdram_dq[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y26_N9 +cycloneive_io_obuf \sdram_dq[11]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [11]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[11]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[11]~output .bus_hold = "false"; +defparam \sdram_dq[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y23_N9 +cycloneive_io_obuf \sdram_dq[12]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [12]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[12]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[12]~output .bus_hold = "false"; +defparam \sdram_dq[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N9 +cycloneive_io_obuf \sdram_dq[13]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [13]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[13]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[13]~output .bus_hold = "false"; +defparam \sdram_dq[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N23 +cycloneive_io_obuf \sdram_dq[14]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [14]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[14]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[14]~output .bus_hold = "false"; +defparam \sdram_dq[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N2 +cycloneive_io_obuf \sdram_dq[15]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [15]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[15]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[15]~output .bus_hold = "false"; +defparam \sdram_dq[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N2 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) +// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_rx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 4; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 4; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "c2"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "-833"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 4; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 5989; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N24 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X27_Y26_N25 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N26 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked )) # (!\sys_rst_n~input_o ) + + .dataa(\sys_rst_n~input_o ), + .datab(gnd), + .datac(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h5FFF; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G17 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N6 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) +// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_rx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[1]~16 ), + .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_rx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N8 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[2]~18 ), + .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_rx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N9 +dffeas \uart_rx_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N12 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) + + .dataa(\uart_rx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[4]~22 ), + .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_rx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N13 +dffeas \uart_rx_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N30 +cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( +// Equation(s): +// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt [3] & !\uart_rx_inst|baud_cnt [5]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [2]), + .datac(\uart_rx_inst|baud_cnt [3]), + .datad(\uart_rx_inst|baud_cnt [5]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0008; +defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N14 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) +// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[5]~24 ), + .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_rx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N15 +dffeas \uart_rx_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N16 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[6]~26 ), + .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_rx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N17 +dffeas \uart_rx_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N18 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) +// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[7]~28 ), + .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_rx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N19 +dffeas \uart_rx_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N0 +cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( +// Equation(s): +// \uart_rx_inst|Equal1~0_combout = (\uart_rx_inst|baud_cnt [0] & (!\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt [1] & !\uart_rx_inst|baud_cnt [7]))) + + .dataa(\uart_rx_inst|baud_cnt [0]), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(\uart_rx_inst|baud_cnt [1]), + .datad(\uart_rx_inst|baud_cnt [7]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N20 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[8]~30 ), + .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_rx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N21 +dffeas \uart_rx_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N22 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) +// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[9]~32 ), + .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_rx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N24 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[10]~34 ), + .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_rx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N25 +dffeas \uart_rx_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N8 +cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( +// Equation(s): +// \uart_rx_inst|Equal1~2_combout = (!\uart_rx_inst|baud_cnt [9] & \uart_rx_inst|baud_cnt [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|baud_cnt [9]), + .datad(\uart_rx_inst|baud_cnt [6]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0F00; +defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N23 +dffeas \uart_rx_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N2 +cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( +// Equation(s): +// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|baud_cnt [12] & (!\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|Equal1~2_combout & \uart_rx_inst|baud_cnt [10]))) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|Equal1~2_combout ), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h2000; +defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N12 +cycloneive_lcell_comb \uart_rx_inst|always5~0 ( +// Equation(s): +// \uart_rx_inst|always5~0_combout = ((\uart_rx_inst|Equal1~1_combout & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal1~3_combout ))) # (!\uart_rx_inst|work_en~q ) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|Equal1~1_combout ), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal1~3_combout ), + .cin(gnd), + .combout(\uart_rx_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always5~0 .lut_mask = 16'hD555; +defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N3 +dffeas \uart_rx_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N4 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[0]~14 ), + .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_rx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N5 +dffeas \uart_rx_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y25_N7 +dffeas \uart_rx_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N28 +cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( +// Equation(s): +// \uart_rx_inst|Equal2~0_combout = (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt [3] & \uart_rx_inst|baud_cnt [5]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [2]), + .datac(\uart_rx_inst|baud_cnt [3]), + .datad(\uart_rx_inst|baud_cnt [5]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h1000; +defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N26 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt [12] $ (!\uart_rx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_rx_inst|baud_cnt[11]~36 ), + .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N27 +dffeas \uart_rx_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N20 +cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( +// Equation(s): +// \uart_rx_inst|Equal2~1_combout = (!\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|baud_cnt [9] & !\uart_rx_inst|baud_cnt [10]))) + + .dataa(\uart_rx_inst|baud_cnt [6]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [9]), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0040; +defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N4 +cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( +// Equation(s): +// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal1~0_combout & (\uart_rx_inst|Equal2~0_combout & (!\uart_rx_inst|baud_cnt [12] & \uart_rx_inst|Equal2~1_combout ))) + + .dataa(\uart_rx_inst|Equal1~0_combout ), + .datab(\uart_rx_inst|Equal2~0_combout ), + .datac(\uart_rx_inst|baud_cnt [12]), + .datad(\uart_rx_inst|Equal2~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h0800; +defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N5 +dffeas \uart_rx_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Equal2~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N26 +cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( +// Equation(s): +// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) +// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~1 ), + .combout(\uart_rx_inst|Add1~2_combout ), + .cout(\uart_rx_inst|Add1~3 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y25_N29 +dffeas \uart_rx_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y25_N27 +dffeas \uart_rx_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N0 +cycloneive_lcell_comb \uart_rx_inst|always4~0 ( +// Equation(s): +// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [0] & (!\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [0]), + .datab(\uart_rx_inst|bit_cnt [2]), + .datac(\uart_rx_inst|bit_cnt [1]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0101; +defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N16 +cycloneive_lcell_comb \uart_rx_inst|always4~1 ( +// Equation(s): +// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|bit_cnt [3] & (\uart_rx_inst|always4~0_combout & \uart_rx_inst|bit_flag~q )) + + .dataa(\uart_rx_inst|bit_cnt [3]), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~1 .lut_mask = 16'h8080; +defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N17 +dffeas \uart_rx_inst|rx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always4~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_flag .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N1 +dffeas \uart_rx_inst|po_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_flag~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h5A5A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hF0B4; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0800; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h0100; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .lut_mask = 16'hC3F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h3CC3; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h0200; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0004; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hB4F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4 .lut_mask = 16'h0001; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6 .lut_mask = 16'h0100; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8 .lut_mask = 16'h1000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5 .lut_mask = 16'h9696; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y22_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y22_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0040; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hE1F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'h2000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8 .lut_mask = 16'h000F; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'h8008; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'h8008; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'h0F33; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ) # (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q )))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ) # +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hEEE0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X16_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y20_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [0]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [0])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1 .lut_mask = 16'h00BB; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y20_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|LessThan2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ) # ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ) # +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ) # (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~0 .lut_mask = 16'hFFFE; +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|LessThan2~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ) # ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ) # (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~1 .lut_mask = 16'hFFC8; +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .lut_mask = 16'h0010; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 $ (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [9])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [9]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [9]), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18 .lut_mask = 16'h5AA5; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & ((\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ) # ((\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ) # +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0 .lut_mask = 16'hAAA8; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y20_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h5A5A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hF0B4; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hD2F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h0040; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .lut_mask = 16'hD2D2; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1] $ (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h3CC3; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0020; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hD2F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & (\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4 .lut_mask = 16'h0500; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9] $ (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28 .lut_mask = 16'h5A5A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3 .lut_mask = 16'h000F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5 .lut_mask = 16'h2000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0 .lut_mask = 16'hCCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [5] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2 .lut_mask = 16'h0001; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ) # ((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0 .lut_mask = 16'hFF30; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1 .lut_mask = 16'hC0C0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0 .lut_mask = 16'h00F8; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16 .lut_mask = 16'h0088; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0 .lut_mask = 16'hCCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1 .lut_mask = 16'hCC00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2 .lut_mask = 16'hEEFF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [0] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0 .lut_mask = 16'h00FE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3 .lut_mask = 16'hFFEC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y23_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y23_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [1]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]) # (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1 .lut_mask = 16'h5776; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hF0D2; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h78F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0100; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0010; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .lut_mask = 16'hA5F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2] $ (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h3CC3; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0008; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h0200; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'hB4F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'hFCFF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1 .lut_mask = 16'hF05A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout +// )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'hAC0C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout )))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'h59FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h0021; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout & +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout +// )) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'h1333; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y24_N25 +dffeas \fifo_read_inst|read_en_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\fifo_read_inst|read_en~q ), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_en_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_en_dly .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_en_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout = (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q & \fifo_read_inst|read_en_dly~q ) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datab(gnd), + .datac(\fifo_read_inst|read_en_dly~q ), + .datad(gnd), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq .lut_mask = 16'h5050; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N6 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] $ (((VCC) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT = CARRY(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] $ +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0 .lut_mask = 16'h5599; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y24_N7 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N8 +cycloneive_lcell_comb \fifo_read_inst|Add2~0 ( +// Equation(s): +// \fifo_read_inst|Add2~0_combout = (\fifo_read_inst|bit_flag~q & (\fifo_read_inst|bit_cnt [0] $ (VCC))) # (!\fifo_read_inst|bit_flag~q & (\fifo_read_inst|bit_cnt [0] & VCC)) +// \fifo_read_inst|Add2~1 = CARRY((\fifo_read_inst|bit_flag~q & \fifo_read_inst|bit_cnt [0])) + + .dataa(\fifo_read_inst|bit_flag~q ), + .datab(\fifo_read_inst|bit_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|Add2~0_combout ), + .cout(\fifo_read_inst|Add2~1 )); +// synopsys translate_off +defparam \fifo_read_inst|Add2~0 .lut_mask = 16'h6688; +defparam \fifo_read_inst|Add2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N9 +dffeas \fifo_read_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|Add2~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N10 +cycloneive_lcell_comb \fifo_read_inst|Add2~2 ( +// Equation(s): +// \fifo_read_inst|Add2~2_combout = (\fifo_read_inst|bit_cnt [1] & (!\fifo_read_inst|Add2~1 )) # (!\fifo_read_inst|bit_cnt [1] & ((\fifo_read_inst|Add2~1 ) # (GND))) +// \fifo_read_inst|Add2~3 = CARRY((!\fifo_read_inst|Add2~1 ) # (!\fifo_read_inst|bit_cnt [1])) + + .dataa(\fifo_read_inst|bit_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|Add2~1 ), + .combout(\fifo_read_inst|Add2~2_combout ), + .cout(\fifo_read_inst|Add2~3 )); +// synopsys translate_off +defparam \fifo_read_inst|Add2~2 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|Add2~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N14 +cycloneive_lcell_comb \fifo_read_inst|Add2~6 ( +// Equation(s): +// \fifo_read_inst|Add2~6_combout = \fifo_read_inst|bit_cnt [3] $ (\fifo_read_inst|Add2~5 ) + + .dataa(gnd), + .datab(\fifo_read_inst|bit_cnt [3]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|Add2~5 ), + .combout(\fifo_read_inst|Add2~6_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Add2~6 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|Add2~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N4 +cycloneive_lcell_comb \fifo_read_inst|bit_cnt~0 ( +// Equation(s): +// \fifo_read_inst|bit_cnt~0_combout = (\fifo_read_inst|Add2~6_combout & ((!\fifo_read_inst|always5~0_combout ) # (!\fifo_read_inst|bit_cnt [0]))) + + .dataa(gnd), + .datab(\fifo_read_inst|bit_cnt [0]), + .datac(\fifo_read_inst|Add2~6_combout ), + .datad(\fifo_read_inst|always5~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt~0 .lut_mask = 16'h30F0; +defparam \fifo_read_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N5 +dffeas \fifo_read_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N4 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[0]~13 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[0]~13_combout = (\fifo_read_inst|rd_flag~q & (\fifo_read_inst|baud_cnt [0] $ (VCC))) # (!\fifo_read_inst|rd_flag~q & (\fifo_read_inst|baud_cnt [0] & VCC)) +// \fifo_read_inst|baud_cnt[0]~14 = CARRY((\fifo_read_inst|rd_flag~q & \fifo_read_inst|baud_cnt [0])) + + .dataa(\fifo_read_inst|rd_flag~q ), + .datab(\fifo_read_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|baud_cnt[0]~13_combout ), + .cout(\fifo_read_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \fifo_read_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N14 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[5]~23 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[5]~23_combout = (\fifo_read_inst|baud_cnt [5] & (!\fifo_read_inst|baud_cnt[4]~22 )) # (!\fifo_read_inst|baud_cnt [5] & ((\fifo_read_inst|baud_cnt[4]~22 ) # (GND))) +// \fifo_read_inst|baud_cnt[5]~24 = CARRY((!\fifo_read_inst|baud_cnt[4]~22 ) # (!\fifo_read_inst|baud_cnt [5])) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[4]~22 ), + .combout(\fifo_read_inst|baud_cnt[5]~23_combout ), + .cout(\fifo_read_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N16 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[6]~25 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[6]~25_combout = (\fifo_read_inst|baud_cnt [6] & (\fifo_read_inst|baud_cnt[5]~24 $ (GND))) # (!\fifo_read_inst|baud_cnt [6] & (!\fifo_read_inst|baud_cnt[5]~24 & VCC)) +// \fifo_read_inst|baud_cnt[6]~26 = CARRY((\fifo_read_inst|baud_cnt [6] & !\fifo_read_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[5]~24 ), + .combout(\fifo_read_inst|baud_cnt[6]~25_combout ), + .cout(\fifo_read_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N17 +dffeas \fifo_read_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N18 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[7]~27 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[7]~27_combout = (\fifo_read_inst|baud_cnt [7] & (!\fifo_read_inst|baud_cnt[6]~26 )) # (!\fifo_read_inst|baud_cnt [7] & ((\fifo_read_inst|baud_cnt[6]~26 ) # (GND))) +// \fifo_read_inst|baud_cnt[7]~28 = CARRY((!\fifo_read_inst|baud_cnt[6]~26 ) # (!\fifo_read_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[6]~26 ), + .combout(\fifo_read_inst|baud_cnt[7]~27_combout ), + .cout(\fifo_read_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N19 +dffeas \fifo_read_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N20 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[8]~29 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[8]~29_combout = (\fifo_read_inst|baud_cnt [8] & (\fifo_read_inst|baud_cnt[7]~28 $ (GND))) # (!\fifo_read_inst|baud_cnt [8] & (!\fifo_read_inst|baud_cnt[7]~28 & VCC)) +// \fifo_read_inst|baud_cnt[8]~30 = CARRY((\fifo_read_inst|baud_cnt [8] & !\fifo_read_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[7]~28 ), + .combout(\fifo_read_inst|baud_cnt[8]~29_combout ), + .cout(\fifo_read_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N21 +dffeas \fifo_read_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N0 +cycloneive_lcell_comb \fifo_read_inst|Equal4~0 ( +// Equation(s): +// \fifo_read_inst|Equal4~0_combout = (\fifo_read_inst|baud_cnt [1] & (!\fifo_read_inst|baud_cnt [8] & (\fifo_read_inst|baud_cnt [0] & !\fifo_read_inst|baud_cnt [7]))) + + .dataa(\fifo_read_inst|baud_cnt [1]), + .datab(\fifo_read_inst|baud_cnt [8]), + .datac(\fifo_read_inst|baud_cnt [0]), + .datad(\fifo_read_inst|baud_cnt [7]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~0 .lut_mask = 16'h0020; +defparam \fifo_read_inst|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N10 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[3]~19 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[3]~19_combout = (\fifo_read_inst|baud_cnt [3] & (!\fifo_read_inst|baud_cnt[2]~18 )) # (!\fifo_read_inst|baud_cnt [3] & ((\fifo_read_inst|baud_cnt[2]~18 ) # (GND))) +// \fifo_read_inst|baud_cnt[3]~20 = CARRY((!\fifo_read_inst|baud_cnt[2]~18 ) # (!\fifo_read_inst|baud_cnt [3])) + + .dataa(\fifo_read_inst|baud_cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[2]~18 ), + .combout(\fifo_read_inst|baud_cnt[3]~19_combout ), + .cout(\fifo_read_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N11 +dffeas \fifo_read_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N22 +cycloneive_lcell_comb \fifo_read_inst|Equal4~1 ( +// Equation(s): +// \fifo_read_inst|Equal4~1_combout = (\fifo_read_inst|baud_cnt [4] & (!\fifo_read_inst|baud_cnt [5] & (!\fifo_read_inst|baud_cnt [3] & \fifo_read_inst|baud_cnt [2]))) + + .dataa(\fifo_read_inst|baud_cnt [4]), + .datab(\fifo_read_inst|baud_cnt [5]), + .datac(\fifo_read_inst|baud_cnt [3]), + .datad(\fifo_read_inst|baud_cnt [2]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~1 .lut_mask = 16'h0200; +defparam \fifo_read_inst|Equal4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N24 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[10]~33 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[10]~33_combout = (\fifo_read_inst|baud_cnt [10] & (\fifo_read_inst|baud_cnt[9]~32 $ (GND))) # (!\fifo_read_inst|baud_cnt [10] & (!\fifo_read_inst|baud_cnt[9]~32 & VCC)) +// \fifo_read_inst|baud_cnt[10]~34 = CARRY((\fifo_read_inst|baud_cnt [10] & !\fifo_read_inst|baud_cnt[9]~32 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[9]~32 ), + .combout(\fifo_read_inst|baud_cnt[10]~33_combout ), + .cout(\fifo_read_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N25 +dffeas \fifo_read_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N28 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[12]~37 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[12]~37_combout = \fifo_read_inst|baud_cnt[11]~36 $ (!\fifo_read_inst|baud_cnt [12]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\fifo_read_inst|baud_cnt [12]), + .cin(\fifo_read_inst|baud_cnt[11]~36 ), + .combout(\fifo_read_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; +defparam \fifo_read_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N29 +dffeas \fifo_read_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N16 +cycloneive_lcell_comb \fifo_read_inst|Equal4~3 ( +// Equation(s): +// \fifo_read_inst|Equal4~3_combout = (\fifo_read_inst|Equal4~2_combout & (\fifo_read_inst|Equal4~0_combout & (\fifo_read_inst|Equal4~1_combout & \fifo_read_inst|baud_cnt [12]))) + + .dataa(\fifo_read_inst|Equal4~2_combout ), + .datab(\fifo_read_inst|Equal4~0_combout ), + .datac(\fifo_read_inst|Equal4~1_combout ), + .datad(\fifo_read_inst|baud_cnt [12]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~3_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~3 .lut_mask = 16'h8000; +defparam \fifo_read_inst|Equal4~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y25_N5 +dffeas \fifo_read_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N8 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[2]~17 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[2]~17_combout = (\fifo_read_inst|baud_cnt [2] & (\fifo_read_inst|baud_cnt[1]~16 $ (GND))) # (!\fifo_read_inst|baud_cnt [2] & (!\fifo_read_inst|baud_cnt[1]~16 & VCC)) +// \fifo_read_inst|baud_cnt[2]~18 = CARRY((\fifo_read_inst|baud_cnt [2] & !\fifo_read_inst|baud_cnt[1]~16 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[1]~16 ), + .combout(\fifo_read_inst|baud_cnt[2]~17_combout ), + .cout(\fifo_read_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N9 +dffeas \fifo_read_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N15 +dffeas \fifo_read_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N28 +cycloneive_lcell_comb \fifo_read_inst|Equal5~0 ( +// Equation(s): +// \fifo_read_inst|Equal5~0_combout = (!\fifo_read_inst|baud_cnt [4] & (\fifo_read_inst|baud_cnt [5] & (\fifo_read_inst|baud_cnt [3] & !\fifo_read_inst|baud_cnt [2]))) + + .dataa(\fifo_read_inst|baud_cnt [4]), + .datab(\fifo_read_inst|baud_cnt [5]), + .datac(\fifo_read_inst|baud_cnt [3]), + .datad(\fifo_read_inst|baud_cnt [2]), + .cin(gnd), + .combout(\fifo_read_inst|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal5~0 .lut_mask = 16'h0040; +defparam \fifo_read_inst|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N26 +cycloneive_lcell_comb \fifo_read_inst|Equal5~2 ( +// Equation(s): +// \fifo_read_inst|Equal5~2_combout = (\fifo_read_inst|Equal5~1_combout & (\fifo_read_inst|Equal5~0_combout & (\fifo_read_inst|Equal4~0_combout & !\fifo_read_inst|baud_cnt [12]))) + + .dataa(\fifo_read_inst|Equal5~1_combout ), + .datab(\fifo_read_inst|Equal5~0_combout ), + .datac(\fifo_read_inst|Equal4~0_combout ), + .datad(\fifo_read_inst|baud_cnt [12]), + .cin(gnd), + .combout(\fifo_read_inst|Equal5~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal5~2 .lut_mask = 16'h0080; +defparam \fifo_read_inst|Equal5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N27 +dffeas \fifo_read_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|Equal5~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_flag .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N6 +cycloneive_lcell_comb \fifo_read_inst|bit_cnt~1 ( +// Equation(s): +// \fifo_read_inst|bit_cnt~1_combout = (\fifo_read_inst|Add2~2_combout & ((!\fifo_read_inst|bit_cnt [0]) # (!\fifo_read_inst|always5~0_combout ))) + + .dataa(gnd), + .datab(\fifo_read_inst|always5~0_combout ), + .datac(\fifo_read_inst|bit_cnt [0]), + .datad(\fifo_read_inst|Add2~2_combout ), + .cin(gnd), + .combout(\fifo_read_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt~1 .lut_mask = 16'h3F00; +defparam \fifo_read_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N7 +dffeas \fifo_read_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N24 +cycloneive_lcell_comb \fifo_read_inst|always5~0 ( +// Equation(s): +// \fifo_read_inst|always5~0_combout = (!\fifo_read_inst|bit_cnt [2] & (\fifo_read_inst|bit_cnt [3] & (\fifo_read_inst|bit_flag~q & !\fifo_read_inst|bit_cnt [1]))) + + .dataa(\fifo_read_inst|bit_cnt [2]), + .datab(\fifo_read_inst|bit_cnt [3]), + .datac(\fifo_read_inst|bit_flag~q ), + .datad(\fifo_read_inst|bit_cnt [1]), + .cin(gnd), + .combout(\fifo_read_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|always5~0 .lut_mask = 16'h0040; +defparam \fifo_read_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N0 +cycloneive_lcell_comb \fifo_read_inst|always5~1 ( +// Equation(s): +// \fifo_read_inst|always5~1_combout = (\fifo_read_inst|bit_cnt [0] & \fifo_read_inst|always5~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\fifo_read_inst|bit_cnt [0]), + .datad(\fifo_read_inst|always5~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|always5~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|always5~1 .lut_mask = 16'hF000; +defparam \fifo_read_inst|always5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N1 +dffeas \fifo_read_inst|rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|always5~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|rd_en .is_wysiwyg = "true"; +defparam \fifo_read_inst|rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]) # +// (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]) # (!\fifo_read_inst|rd_en~q )) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0])) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .lut_mask = 16'hFBFF; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N6 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ) # (\fifo_read_inst|read_en_dly~q ) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datab(gnd), + .datac(\fifo_read_inst|read_en_dly~q ), + .datad(gnd), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .lut_mask = 16'hFAFA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ) # +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ) # (!\fifo_read_inst|Equal1~1_combout )))) + + .dataa(\fifo_read_inst|Equal1~1_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .lut_mask = 16'hFFD0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N26 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ) # +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q & !\fifo_read_inst|rd_en~q )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ), + .datab(gnd), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4 .lut_mask = 16'hAAFA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N27 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout = (\fifo_read_inst|read_en_dly~q & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q $ (((!\fifo_read_inst|rd_en~q ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ))))) # (!\fifo_read_inst|read_en_dly~q & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & +// ((\fifo_read_inst|rd_en~q )))) + + .dataa(\fifo_read_inst|read_en_dly~q ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .lut_mask = 16'hC60A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N9 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y25_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y22_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N10 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h0040; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N28 +cycloneive_lcell_comb \fifo_read_inst|read_en~0 ( +// Equation(s): +// \fifo_read_inst|read_en~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout & (\Equal2~1_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout & +// \Equal2~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .datab(\Equal2~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .datad(\Equal2~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_en~0 .lut_mask = 16'h0400; +defparam \fifo_read_inst|read_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N8 +cycloneive_lcell_comb \fifo_read_inst|read_en~1 ( +// Equation(s): +// \fifo_read_inst|read_en~1_combout = (\fifo_read_inst|read_en~0_combout ) # ((\fifo_read_inst|read_en~q & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]) # +// (!\fifo_read_inst|Equal1~2_combout )))) + + .dataa(\fifo_read_inst|Equal1~2_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datac(\fifo_read_inst|read_en~q ), + .datad(\fifo_read_inst|read_en~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_en~1 .lut_mask = 16'hFFD0; +defparam \fifo_read_inst|read_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N9 +dffeas \fifo_read_inst|read_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_en~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_en .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout = (\fifo_read_inst|read_en~q & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ) # +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .datad(\fifo_read_inst|read_en~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hFC00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h0800; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0010; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N2 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0001; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9 .lut_mask = 16'h55AA; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 $ (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [9])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [9]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [9]), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18 .lut_mask = 16'h5AA5; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout = (\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout & (!\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2 .lut_mask = 16'h0002; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout = (!\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout & (\Equal2~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout & +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ), + .datab(\Equal2~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q & (!\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0 .lut_mask = 16'h0100; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0 .lut_mask = 16'h5500; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & !\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1 .lut_mask = 16'hFF08; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7 .lut_mask = 16'h0030; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0 .lut_mask = 16'hDCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ) # ((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0 .lut_mask = 16'hFF50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & (\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1 .lut_mask = 16'hF888; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ) # +// (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3 .lut_mask = 16'hFEFE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0 .lut_mask = 16'hC0C0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0 .lut_mask = 16'h00F8; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4 .lut_mask = 16'h0F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2 .lut_mask = 16'h0AA0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15 .lut_mask = 16'h00F0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ) # ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0 .lut_mask = 16'hFF50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]))) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1 .lut_mask = 16'h0330; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0 .lut_mask = 16'h0300; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout = ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1 .lut_mask = 16'hFFD5; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2 .lut_mask = 16'hFF88; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2] $ +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0 .lut_mask = 16'h1230; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0 .lut_mask = 16'h7F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1 .lut_mask = 16'hFCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2 .lut_mask = 16'h0007; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk +// [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ) # +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0 .lut_mask = 16'hB3A0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3 .lut_mask = 16'hF5F5; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17 .lut_mask = 16'h2020; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0 .lut_mask = 16'hFFC0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3 .lut_mask = 16'h000F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]))) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2 .lut_mask = 16'h003C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1 .lut_mask = 16'h0C0C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0 .lut_mask = 16'hEAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0 .lut_mask = 16'hB800; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3 .lut_mask = 16'h0055; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4 .lut_mask = 16'h0004; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0 .lut_mask = 16'h2AAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [9] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [11] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[12] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 $ (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28 .lut_mask = 16'hF00F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[14] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[11] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0 .lut_mask = 16'h0040; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1 .lut_mask = 16'h0020; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6]), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2 .lut_mask = 16'h5000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0 .lut_mask = 16'h2000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2 .lut_mask = 16'hFEFF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] $ +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4 .lut_mask = 16'h1230; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0 .lut_mask = 16'hCC00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0 .lut_mask = 16'hF2F0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16 .lut_mask = 16'h4040; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0 .lut_mask = 16'h55AA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref +// [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref +// [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1 .lut_mask = 16'hF0FF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref +// [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8 .lut_mask = 16'hCC00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout = (((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0 .lut_mask = 16'h777F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5] & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1 .lut_mask = 16'h8C00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout = ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2 .lut_mask = 16'h1F3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3 .lut_mask = 16'hC840; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 $ (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1 .lut_mask = 16'h0040; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2 .lut_mask = 16'hC000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ) # +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0 .lut_mask = 16'hBA30; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0 .lut_mask = 16'h0F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & (\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0 .lut_mask = 16'h5450; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1 .lut_mask = 16'hFFCF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout & +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0 .lut_mask = 16'hF888; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2 .lut_mask = 16'hFFF8; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] $ (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datac(gnd), + .datad(gnd), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5 .lut_mask = 16'h0033; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0 .lut_mask = 16'hAAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout = ((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2 .lut_mask = 16'h5557; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ) # +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h00A8; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h5400; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .lut_mask = 16'h9696; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1] $ (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .lut_mask = 16'h5AA5; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h2000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h0200; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hB4F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h0040; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .lut_mask = 16'hC3F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h2814; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout +// )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'hE2C0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'hA018; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout = (\uart_rx_inst|po_flag~q & ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .datab(gnd), + .datac(\uart_rx_inst|po_flag~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .lut_mask = 16'h50F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \rx~input ( + .i(rx), + .ibar(gnd), + .o(\rx~input_o )); +// synopsys translate_off +defparam \rx~input .bus_hold = "false"; +defparam \rx~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N12 +cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( +// Equation(s): +// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rx~input_o ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y24_N13 +dffeas \uart_rx_inst|rx_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg1~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y24_N3 +dffeas \uart_rx_inst|rx_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_reg3~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg3~feeder_combout = \uart_rx_inst|rx_reg2~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg2~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y24_N1 +dffeas \uart_rx_inst|rx_reg3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg3~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N14 +cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( +// Equation(s): +// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg3~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N10 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~0_combout = (\uart_rx_inst|Add1~6_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q ))) + + .dataa(\uart_rx_inst|Add1~6_combout ), + .datab(\uart_rx_inst|bit_flag~q ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h2AAA; +defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N11 +dffeas \uart_rx_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N18 +cycloneive_lcell_comb \uart_rx_inst|always8~0 ( +// Equation(s): +// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(gnd), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|always8~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always8~0 .lut_mask = 16'hC030; +defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N15 +dffeas \uart_rx_inst|rx_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[7]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y23_N21 +dffeas \uart_rx_inst|rx_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N18 +cycloneive_lcell_comb \uart_rx_inst|rx_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[5]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N19 +dffeas \uart_rx_inst|rx_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[4]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N1 +dffeas \uart_rx_inst|rx_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N6 +cycloneive_lcell_comb \uart_rx_inst|rx_data[3]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[3]~feeder_combout = \uart_rx_inst|rx_data [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [4]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N7 +dffeas \uart_rx_inst|rx_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N28 +cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N29 +dffeas \uart_rx_inst|rx_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[1]~feeder_combout = \uart_rx_inst|rx_data [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [2]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N3 +dffeas \uart_rx_inst|rx_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N24 +cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N25 +dffeas \uart_rx_inst|rx_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N8 +cycloneive_lcell_comb \uart_rx_inst|po_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[0]~feeder_combout = \uart_rx_inst|rx_data [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [0]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N9 +dffeas \uart_rx_inst|po_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a[9] ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9]), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a[9] .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout = !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N10 +cycloneive_lcell_comb \uart_rx_inst|po_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[1]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N11 +dffeas \uart_rx_inst|po_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N12 +cycloneive_lcell_comb \uart_rx_inst|po_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[2]~feeder_combout = \uart_rx_inst|rx_data [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [2]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N13 +dffeas \uart_rx_inst|po_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N30 +cycloneive_lcell_comb \uart_rx_inst|po_data[3]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[3]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N31 +dffeas \uart_rx_inst|po_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N16 +cycloneive_lcell_comb \uart_rx_inst|po_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[4]~feeder_combout = \uart_rx_inst|rx_data [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [4]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N17 +dffeas \uart_rx_inst|po_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N26 +cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N27 +dffeas \uart_rx_inst|po_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N4 +cycloneive_lcell_comb \uart_rx_inst|po_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[6]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N5 +dffeas \uart_rx_inst|po_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y23_N23 +dffeas \uart_rx_inst|po_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y23_N8 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X13_Y23_N0 +cycloneive_ram_block \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .ena0(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(\rst_n~0clkctrl_outclk ), + .portadatain({\~GND~combout ,\uart_rx_inst|po_data [7],\uart_rx_inst|po_data [6],\uart_rx_inst|po_data [5],\uart_rx_inst|po_data [4],\uart_rx_inst|po_data [3],\uart_rx_inst|po_data [2],\uart_rx_inst|po_data [1],\uart_rx_inst|po_data [0]}), + .portaaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "sdram_top:sdram_top_inst|fifo_ctrl:fifo_ctrl_inst|fifo_data:wr_fifo_data|dcfifo:dcfifo_component|dcfifo_3fk1:auto_generated|altsyncram_em31:fifo_ram|ALTSYNCRAM"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X13_Y21_N0 +cycloneive_ram_block \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 ( + .portawe(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .ena0(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(\rst_n~0clkctrl_outclk ), + .portadatain({gnd,gnd,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout }), + .portaaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .clk0_core_clock_enable = "ena0"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .clk1_output_clock_enable = "ena1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .data_interleave_offset_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .data_interleave_width_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .logical_ram_name = "sdram_top:sdram_top_inst|fifo_ctrl:fifo_ctrl_inst|fifo_data:wr_fifo_data|dcfifo:dcfifo_component|dcfifo_3fk1:auto_generated|altsyncram_em31:fifo_ram|ALTSYNCRAM"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .operation_mode = "dual_port"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_address_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_byte_enable_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_data_out_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_data_out_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_first_bit_number = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_address_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_address_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_data_out_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_data_out_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_first_bit_number = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_read_enable_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: CLKCTRL_G5 +cycloneive_clkctrl \sys_clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sys_clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sys_clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \sys_clk~inputclkctrl .clock_type = "global clock"; +defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N4 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) +// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_tx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N26 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) + + .dataa(\uart_tx_inst|baud_cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[10]~34 ), + .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_tx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N27 +dffeas \uart_tx_inst|baud_cnt[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N0 +cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( +// Equation(s): +// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt [5] & (\uart_tx_inst|baud_cnt [0] & !\uart_tx_inst|baud_cnt [7]))) + + .dataa(\uart_tx_inst|baud_cnt [3]), + .datab(\uart_tx_inst|baud_cnt [5]), + .datac(\uart_tx_inst|baud_cnt [0]), + .datad(\uart_tx_inst|baud_cnt [7]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0010; +defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N22 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) + + .dataa(\uart_tx_inst|baud_cnt [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[8]~30 ), + .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_tx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N23 +dffeas \uart_tx_inst|baud_cnt[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N2 +cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( +// Equation(s): +// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt [11] & (\uart_tx_inst|Equal1~0_combout & !\uart_tx_inst|baud_cnt [9]))) + + .dataa(\uart_tx_inst|baud_cnt [8]), + .datab(\uart_tx_inst|baud_cnt [11]), + .datac(\uart_tx_inst|Equal1~0_combout ), + .datad(\uart_tx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0010; +defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N6 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) + + .dataa(\uart_tx_inst|baud_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[0]~14 ), + .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_tx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N7 +dffeas \uart_tx_inst|baud_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N30 +cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( +// Equation(s): +// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [2] & \uart_tx_inst|baud_cnt [1]))) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [2]), + .datad(\uart_tx_inst|baud_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; +defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N19 +dffeas \fifo_read_inst|tx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\fifo_read_inst|rd_en~q ), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|tx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|tx_flag .is_wysiwyg = "true"; +defparam \fifo_read_inst|tx_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \uart_tx_inst|always3~0 ( +// Equation(s): +// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|work_en~q ) # (!\uart_tx_inst|bit_flag~q ) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(gnd), + .datac(\uart_tx_inst|work_en~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_tx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always3~0 .lut_mask = 16'h5F5F; +defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~2 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[1]~2_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [1]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1]~2 .lut_mask = 16'h00D2; +defparam \uart_tx_inst|bit_cnt[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N19 +dffeas \uart_tx_inst|bit_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[1]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~3 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[2]~3_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~0_combout )))) + + .dataa(\uart_tx_inst|Add1~0_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2]~3 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N5 +dffeas \uart_tx_inst|bit_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[2]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \uart_tx_inst|always0~1 ( +// Equation(s): +// \uart_tx_inst|always0~1_combout = (\uart_tx_inst|bit_cnt [0] & (!\uart_tx_inst|bit_cnt [1] & (!\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|always0~0_combout ))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~1 .lut_mask = 16'h0200; +defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N18 +cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( +// Equation(s): +// \uart_tx_inst|work_en~0_combout = (\fifo_read_inst|tx_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) + + .dataa(gnd), + .datab(\uart_tx_inst|work_en~q ), + .datac(\fifo_read_inst|tx_flag~q ), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hF0FC; +defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N25 +dffeas \uart_tx_inst|work_en ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_tx_inst|work_en~0_combout ), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_tx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N6 +cycloneive_lcell_comb \uart_tx_inst|always1~0 ( +// Equation(s): +// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~3_combout & (\uart_tx_inst|Equal1~1_combout & \uart_tx_inst|Equal1~2_combout ))) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|Equal1~3_combout ), + .datab(\uart_tx_inst|Equal1~1_combout ), + .datac(\uart_tx_inst|Equal1~2_combout ), + .datad(\uart_tx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_tx_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always1~0 .lut_mask = 16'h80FF; +defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y18_N5 +dffeas \uart_tx_inst|baud_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N8 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) +// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[1]~16 ), + .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_tx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N9 +dffeas \uart_tx_inst|baud_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N14 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[4]~22 ), + .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_tx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N15 +dffeas \uart_tx_inst|baud_cnt[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N16 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) +// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[5]~24 ), + .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_tx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N17 +dffeas \uart_tx_inst|baud_cnt[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N18 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[6]~26 ), + .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_tx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N19 +dffeas \uart_tx_inst|baud_cnt[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N20 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) +// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[7]~28 ), + .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_tx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N21 +dffeas \uart_tx_inst|baud_cnt[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N24 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) +// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[9]~32 ), + .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_tx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N25 +dffeas \uart_tx_inst|baud_cnt[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N28 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt[11]~36 $ (!\uart_tx_inst|baud_cnt [12]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_tx_inst|baud_cnt [12]), + .cin(\uart_tx_inst|baud_cnt[11]~36 ), + .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; +defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N29 +dffeas \uart_tx_inst|baud_cnt[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N2 +cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( +// Equation(s): +// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt [1]))) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [2]), + .datad(\uart_tx_inst|baud_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N24 +cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( +// Equation(s): +// \uart_tx_inst|Equal2~1_combout = (\uart_tx_inst|Equal1~1_combout & (!\uart_tx_inst|baud_cnt [12] & (\uart_tx_inst|Equal2~0_combout & !\uart_tx_inst|baud_cnt [10]))) + + .dataa(\uart_tx_inst|Equal1~1_combout ), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(\uart_tx_inst|Equal2~0_combout ), + .datad(\uart_tx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h0020; +defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y18_N25 +dffeas \uart_tx_inst|bit_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|Equal2~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \uart_tx_inst|always0~0 ( +// Equation(s): +// \uart_tx_inst|always0~0_combout = (\uart_tx_inst|bit_cnt [3] & \uart_tx_inst|bit_flag~q ) + + .dataa(\uart_tx_inst|bit_cnt [3]), + .datab(gnd), + .datac(\uart_tx_inst|bit_flag~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_tx_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~0 .lut_mask = 16'hA0A0; +defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N30 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & \fifo_read_inst|rd_en~q ) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datab(gnd), + .datac(gnd), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq .lut_mask = 16'hAA00; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N8 +cycloneive_io_ibuf \sdram_dq[0]~input ( + .i(sdram_dq[0]), + .ibar(gnd), + .o(\sdram_dq[0]~input_o )); +// synopsys translate_off +defparam \sdram_dq[0]~input .bus_hold = "false"; +defparam \sdram_dq[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[0]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout = !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N1 +cycloneive_io_ibuf \sdram_dq[1]~input ( + .i(sdram_dq[1]), + .ibar(gnd), + .o(\sdram_dq[1]~input_o )); +// synopsys translate_off +defparam \sdram_dq[1]~input .bus_hold = "false"; +defparam \sdram_dq[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[1]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [1] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y29_N1 +cycloneive_io_ibuf \sdram_dq[2]~input ( + .i(sdram_dq[2]), + .ibar(gnd), + .o(\sdram_dq[2]~input_o )); +// synopsys translate_off +defparam \sdram_dq[2]~input .bus_hold = "false"; +defparam \sdram_dq[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[2]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y29_N29 +cycloneive_io_ibuf \sdram_dq[3]~input ( + .i(sdram_dq[3]), + .ibar(gnd), + .o(\sdram_dq[3]~input_o )); +// synopsys translate_off +defparam \sdram_dq[3]~input .bus_hold = "false"; +defparam \sdram_dq[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[3]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [3] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [3]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y29_N22 +cycloneive_io_ibuf \sdram_dq[4]~input ( + .i(sdram_dq[4]), + .ibar(gnd), + .o(\sdram_dq[4]~input_o )); +// synopsys translate_off +defparam \sdram_dq[4]~input .bus_hold = "false"; +defparam \sdram_dq[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[4]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [4] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [4]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y29_N8 +cycloneive_io_ibuf \sdram_dq[5]~input ( + .i(sdram_dq[5]), + .ibar(gnd), + .o(\sdram_dq[5]~input_o )); +// synopsys translate_off +defparam \sdram_dq[5]~input .bus_hold = "false"; +defparam \sdram_dq[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[5]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [5] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N15 +cycloneive_io_ibuf \sdram_dq[6]~input ( + .i(sdram_dq[6]), + .ibar(gnd), + .o(\sdram_dq[6]~input_o )); +// synopsys translate_off +defparam \sdram_dq[6]~input .bus_hold = "false"; +defparam \sdram_dq[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[6]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [6] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [6]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N22 +cycloneive_io_ibuf \sdram_dq[7]~input ( + .i(sdram_dq[7]), + .ibar(gnd), + .o(\sdram_dq[7]~input_o )); +// synopsys translate_off +defparam \sdram_dq[7]~input .bus_hold = "false"; +defparam \sdram_dq[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[7]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [7] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [7]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X25_Y25_N0 +cycloneive_ram_block \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .ena1(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(\rst_n~0clkctrl_outclk ), + .portadatain({gnd,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout , +\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout , +\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout }), + .portaaddr({\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "sdram_top:sdram_top_inst|fifo_ctrl:fifo_ctrl_inst|fifo_data:rd_fifo_data|dcfifo:dcfifo_component|dcfifo_3fk1:auto_generated|altsyncram_em31:fifo_ram|ALTSYNCRAM"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N6 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0] $ (VCC) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT = CARRY(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0 .lut_mask = 16'h55AA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N7 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N8 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N9 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N10 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N11 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3])) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N14 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N15 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N17 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N18 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N19 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N21 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N23 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N25 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N10 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0] $ (VCC) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT = CARRY(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0 .lut_mask = 16'h55AA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N11 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1])) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N14 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N15 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N17 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N18 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N19 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N21 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N23 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N25 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N26 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N27 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N28 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9]), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9 .lut_mask = 16'h0FF0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N29 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \uart_tx_inst|tx~4 ( +// Equation(s): +// \uart_tx_inst|tx~4_combout = (\uart_tx_inst|bit_cnt [0]) # ((\uart_tx_inst|bit_cnt [2]) # ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [7]) # (\uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [7]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~4 .lut_mask = 16'hFFFE; +defparam \uart_tx_inst|tx~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \uart_tx_inst|tx~3 ( +// Equation(s): +// \uart_tx_inst|tx~3_combout = (!\uart_tx_inst|bit_flag~q & !\uart_tx_inst|tx~q ) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(gnd), + .datac(gnd), + .datad(\uart_tx_inst|tx~q ), + .cin(gnd), + .combout(\uart_tx_inst|tx~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~3 .lut_mask = 16'h0055; +defparam \uart_tx_inst|tx~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \uart_tx_inst|tx~5 ( +// Equation(s): +// \uart_tx_inst|tx~5_combout = (!\uart_tx_inst|tx~2_combout & (!\uart_tx_inst|tx~3_combout & ((!\uart_tx_inst|tx~4_combout ) # (!\uart_tx_inst|always0~0_combout )))) + + .dataa(\uart_tx_inst|tx~2_combout ), + .datab(\uart_tx_inst|always0~0_combout ), + .datac(\uart_tx_inst|tx~4_combout ), + .datad(\uart_tx_inst|tx~3_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~5 .lut_mask = 16'h0015; +defparam \uart_tx_inst|tx~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N1 +dffeas \uart_tx_inst|tx ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|tx~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|tx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|tx .is_wysiwyg = "true"; +defparam \uart_tx_inst|tx .power_up = "low"; +// synopsys translate_on + +// Location: CLKCTRL_G7 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X23_Y22_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y22_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1 .lut_mask = 16'hF0FC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0 .lut_mask = 16'hBAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0 .lut_mask = 16'h4000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2 .lut_mask = 16'hFF20; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0 .lut_mask = 16'hFFAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [1])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [1]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2 .lut_mask = 16'h8C9D; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [1]))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [1])))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [1]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3 .lut_mask = 16'h5F22; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0 .lut_mask = 16'hFAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17 .lut_mask = 16'h00CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) # +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5 .lut_mask = 16'hFFEE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0 .lut_mask = 16'hFFAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [2])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [2] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0 .lut_mask = 16'hA1AB; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [2])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [2]))))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [2]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1 .lut_mask = 16'h5F30; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0 .lut_mask = 16'h5554; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ) # +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1 .lut_mask = 16'hAAA0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [0]) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [0] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1 .lut_mask = 16'h1ABA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2 .lut_mask = 16'hFAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1 .lut_mask = 16'h4055; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6 .lut_mask = 16'h0F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3 .lut_mask = 16'hF0FF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]))) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5 .lut_mask = 16'h3C00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2] $ +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4 .lut_mask = 16'h7800; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15 .lut_mask = 16'h0002; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y21_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0 .lut_mask = 16'h55CF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1 .lut_mask = 16'hF7F2; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0 .lut_mask = 16'h4CCC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2 .lut_mask = 16'h0001; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0] & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & +// (((!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0 .lut_mask = 16'h0777; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0 .lut_mask = 16'h0101; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0 .lut_mask = 16'h2022; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16 .lut_mask = 16'h4400; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0 .lut_mask = 16'h5053; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1 .lut_mask = 16'h008F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10])))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0 .lut_mask = 16'h0FDD; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1 .lut_mask = 16'hDFCE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y20_N8 +cycloneive_io_ibuf \sdram_dq[8]~input ( + .i(sdram_dq[8]), + .ibar(gnd), + .o(\sdram_dq[8]~input_o )); +// synopsys translate_off +defparam \sdram_dq[8]~input .bus_hold = "false"; +defparam \sdram_dq[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y29_N29 +cycloneive_io_ibuf \sdram_dq[9]~input ( + .i(sdram_dq[9]), + .ibar(gnd), + .o(\sdram_dq[9]~input_o )); +// synopsys translate_off +defparam \sdram_dq[9]~input .bus_hold = "false"; +defparam \sdram_dq[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y25_N1 +cycloneive_io_ibuf \sdram_dq[10]~input ( + .i(sdram_dq[10]), + .ibar(gnd), + .o(\sdram_dq[10]~input_o )); +// synopsys translate_off +defparam \sdram_dq[10]~input .bus_hold = "false"; +defparam \sdram_dq[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y26_N8 +cycloneive_io_ibuf \sdram_dq[11]~input ( + .i(sdram_dq[11]), + .ibar(gnd), + .o(\sdram_dq[11]~input_o )); +// synopsys translate_off +defparam \sdram_dq[11]~input .bus_hold = "false"; +defparam \sdram_dq[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N8 +cycloneive_io_ibuf \sdram_dq[12]~input ( + .i(sdram_dq[12]), + .ibar(gnd), + .o(\sdram_dq[12]~input_o )); +// synopsys translate_off +defparam \sdram_dq[12]~input .bus_hold = "false"; +defparam \sdram_dq[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N8 +cycloneive_io_ibuf \sdram_dq[13]~input ( + .i(sdram_dq[13]), + .ibar(gnd), + .o(\sdram_dq[13]~input_o )); +// synopsys translate_off +defparam \sdram_dq[13]~input .bus_hold = "false"; +defparam \sdram_dq[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N22 +cycloneive_io_ibuf \sdram_dq[14]~input ( + .i(sdram_dq[14]), + .ibar(gnd), + .o(\sdram_dq[14]~input_o )); +// synopsys translate_off +defparam \sdram_dq[14]~input .bus_hold = "false"; +defparam \sdram_dq[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N1 +cycloneive_io_ibuf \sdram_dq[15]~input ( + .i(sdram_dq[15]), + .ibar(gnd), + .o(\sdram_dq[15]~input_o )); +// synopsys translate_off +defparam \sdram_dq[15]~input .bus_hold = "false"; +defparam \sdram_dq[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_8_1200mv_0c_v_slow.sdo b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_8_1200mv_0c_v_slow.sdo new file mode 100644 index 0000000..dd3ba87 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_8_1200mv_0c_v_slow.sdo @@ -0,0 +1,19618 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "uart_sdram") + (DATE "06/02/2023 04:26:31") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1631:1631:1631) (1432:1432:1432)) + (PORT d[1] (1572:1572:1572) (1374:1374:1374)) + (PORT d[2] (1676:1676:1676) (1456:1456:1456)) + (PORT d[3] (1662:1662:1662) (1450:1450:1450)) + (PORT d[4] (1610:1610:1610) (1406:1406:1406)) + (PORT d[5] (1604:1604:1604) (1406:1406:1406)) + (PORT d[6] (1672:1672:1672) (1451:1451:1451)) + (PORT d[7] (1636:1636:1636) (1431:1431:1431)) + (PORT clk (2026:2026:2026) (2067:2067:2067)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1255:1255:1255) (1153:1153:1153)) + (PORT d[1] (1332:1332:1332) (1213:1213:1213)) + (PORT d[2] (946:946:946) (891:891:891)) + (PORT d[3] (1185:1185:1185) (1064:1064:1064)) + (PORT d[4] (984:984:984) (918:918:918)) + (PORT d[5] (933:933:933) (879:879:879)) + (PORT d[6] (1224:1224:1224) (1094:1094:1094)) + (PORT d[7] (1288:1288:1288) (1179:1179:1179)) + (PORT d[8] (944:944:944) (892:892:892)) + (PORT d[9] (940:940:940) (887:887:887)) + (PORT clk (2023:2023:2023) (2063:2063:2063)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1956:1956:1956) (1705:1705:1705)) + (PORT clk (2023:2023:2023) (2063:2063:2063)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2026:2026:2026) (2067:2067:2067)) + (PORT d[0] (2578:2578:2578) (2337:2337:2337)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2027:2027:2027) (2068:2068:2068)) + (IOPATH (posedge clk) pulse (0:0:0) (2490:2490:2490)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2027:2027:2027) (2068:2068:2068)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2027:2027:2027) (2068:2068:2068)) + (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2027:2027:2027) (2068:2068:2068)) + (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (956:956:956) (893:893:893)) + (PORT d[1] (944:944:944) (867:867:867)) + (PORT d[2] (1331:1331:1331) (1200:1200:1200)) + (PORT d[3] (1682:1682:1682) (1474:1474:1474)) + (PORT d[4] (938:938:938) (880:880:880)) + (PORT d[5] (1702:1702:1702) (1596:1596:1596)) + (PORT d[6] (1692:1692:1692) (1502:1502:1502)) + (PORT d[7] (1279:1279:1279) (1173:1173:1173)) + (PORT d[8] (972:972:972) (899:899:899)) + (PORT d[9] (1434:1434:1434) (1235:1235:1235)) + (PORT clk (1979:1979:1979) (1975:1975:1975)) + (PORT ena (2420:2420:2420) (2187:2187:2187)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + (HOLD ena (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1979:1979:1979) (1975:1975:1975)) + (PORT d[0] (2420:2420:2420) (2187:2187:2187)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1980:1980:1980) (1976:1976:1976)) + (IOPATH (posedge clk) pulse (0:0:0) (2957:2957:2957)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1980:1980:1980) (1976:1976:1976)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1980:1980:1980) (1976:1976:1976)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1668:1668:1668) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4535:4535:4535) (4419:4419:4419)) + (PORT sclr (1417:1417:1417) (1340:1340:1340)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1668:1668:1668) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4535:4535:4535) (4419:4419:4419)) + (PORT sclr (1417:1417:1417) (1340:1340:1340)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (733:733:733)) + (PORT datab (525:525:525) (500:500:500)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (852:852:852)) + (PORT datab (979:979:979) (875:875:875)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1561:1561:1561) (1394:1394:1394)) + (PORT datab (528:528:528) (509:509:509)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (522:522:522) (508:508:508)) + (PORT datab (852:852:852) (738:738:738)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (417:417:417)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[5\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (392:392:392)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (419:419:419)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (393:393:393)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (393:393:393)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (406:406:406)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (558:558:558)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (843:843:843) (754:754:754)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~26) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (392:392:392)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita1) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (544:544:544)) + (PORT datab (945:945:945) (829:829:829)) + (IOPATH dataa combout (420:420:420) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita2) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (406:406:406)) + (PORT datab (944:944:944) (828:828:828)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita3) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (412:412:412)) + (PORT datab (944:944:944) (827:827:827)) + (IOPATH dataa combout (420:420:420) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita4) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (537:537:537)) + (PORT datab (943:943:943) (827:827:827)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita5) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (549:549:549)) + (PORT datab (942:942:942) (825:825:825)) + (IOPATH dataa combout (420:420:420) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita6) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (548:548:548)) + (PORT datab (942:942:942) (825:825:825)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita7) + (DELAY + (ABSOLUTE + (PORT dataa (820:820:820) (728:728:728)) + (PORT datab (941:941:941) (824:824:824)) + (IOPATH dataa combout (420:420:420) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita8) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (401:401:401)) + (PORT datab (941:941:941) (823:823:823)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita9) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (397:397:397)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5415:5415:5415) (5448:5448:5448)) + (PORT sclr (1065:1065:1065) (1046:1046:1046)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5415:5415:5415) (5448:5448:5448)) + (PORT sclr (1065:1065:1065) (1046:1046:1046)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5415:5415:5415) (5448:5448:5448)) + (PORT sclr (1065:1065:1065) (1046:1046:1046)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5415:5415:5415) (5448:5448:5448)) + (PORT sclr (1065:1065:1065) (1046:1046:1046)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Add2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (392:392:392)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5204:5204:5204) (5163:5163:5163)) + (PORT sclr (1582:1582:1582) (1567:1567:1567)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5204:5204:5204) (5163:5163:5163)) + (PORT sclr (1582:1582:1582) (1567:1567:1567)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5204:5204:5204) (5163:5163:5163)) + (PORT sclr (1582:1582:1582) (1567:1567:1567)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5204:5204:5204) (5163:5163:5163)) + (PORT sclr (1582:1582:1582) (1567:1567:1567)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5204:5204:5204) (5163:5163:5163)) + (PORT sclr (1582:1582:1582) (1567:1567:1567)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5204:5204:5204) (5163:5163:5163)) + (PORT sclr (1582:1582:1582) (1567:1567:1567)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5204:5204:5204) (5163:5163:5163)) + (PORT sclr (1582:1582:1582) (1567:1567:1567)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5204:5204:5204) (5163:5163:5163)) + (PORT sclr (1582:1582:1582) (1567:1567:1567)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5204:5204:5204) (5163:5163:5163)) + (PORT sclr (1582:1582:1582) (1567:1567:1567)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5204:5204:5204) (5163:5163:5163)) + (PORT sclr (1582:1582:1582) (1567:1567:1567)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5204:5204:5204) (5163:5163:5163)) + (PORT sclr (1582:1582:1582) (1567:1567:1567)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5204:5204:5204) (5163:5163:5163)) + (PORT sclr (1582:1582:1582) (1567:1567:1567)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5169:5169:5169)) + (PORT sclr (1532:1532:1532) (1524:1524:1524)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5169:5169:5169)) + (PORT sclr (1532:1532:1532) (1524:1524:1524)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5169:5169:5169)) + (PORT sclr (1532:1532:1532) (1524:1524:1524)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5169:5169:5169)) + (PORT sclr (1532:1532:1532) (1524:1524:1524)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5169:5169:5169)) + (PORT sclr (1532:1532:1532) (1524:1524:1524)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5169:5169:5169)) + (PORT sclr (1532:1532:1532) (1524:1524:1524)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5169:5169:5169)) + (PORT sclr (1532:1532:1532) (1524:1524:1524)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5169:5169:5169)) + (PORT sclr (1532:1532:1532) (1524:1524:1524)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5169:5169:5169)) + (PORT sclr (1532:1532:1532) (1524:1524:1524)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5169:5169:5169)) + (PORT sclr (1532:1532:1532) (1524:1524:1524)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5169:5169:5169)) + (PORT sclr (1532:1532:1532) (1524:1524:1524)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5169:5169:5169)) + (PORT sclr (1532:1532:1532) (1524:1524:1524)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~0) + (DELAY + (ABSOLUTE + (PORT datab (529:529:529) (511:511:511)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (603:603:603) (552:552:552)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (547:547:547) (522:522:522)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~6) + (DELAY + (ABSOLUTE + (PORT datab (540:540:540) (521:521:521)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (533:533:533)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (551:551:551) (533:533:533)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (558:558:558)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (556:556:556)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (841:841:841)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~18) + (DELAY + (ABSOLUTE + (PORT datab (985:985:985) (873:873:873)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (946:946:946) (855:855:855)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~22) + (DELAY + (ABSOLUTE + (PORT datab (889:889:889) (813:813:813)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~24) + (DELAY + (ABSOLUTE + (PORT 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(IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[15\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (390:390:390)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[16\]\~56) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (381:381:381)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[17\]\~58) + (DELAY + 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(posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4943:4943:4943) (4875:4875:4875)) + (PORT sclr (867:867:867) (924:924:924)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4943:4943:4943) (4875:4875:4875)) + (PORT sclr (867:867:867) (924:924:924)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4943:4943:4943) (4875:4875:4875)) + (PORT sclr (867:867:867) (924:924:924)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4943:4943:4943) (4875:4875:4875)) + (PORT sclr (867:867:867) (924:924:924)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4943:4943:4943) (4875:4875:4875)) + (PORT sclr (867:867:867) (924:924:924)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4943:4943:4943) (4875:4875:4875)) + (PORT sclr (867:867:867) (924:924:924)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4943:4943:4943) (4875:4875:4875)) + (PORT sclr (867:867:867) (924:924:924)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4943:4943:4943) (4875:4875:4875)) + (PORT sclr (867:867:867) (924:924:924)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4943:4943:4943) (4875:4875:4875)) + (PORT sclr (867:867:867) (924:924:924)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (391:391:391)) + (PORT datab (354:354:354) (421:421:421)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (323:323:323) (381:381:381)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datad (306:306:306) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1100:1100:1100) (1090:1090:1090)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (788:788:788)) + (PORT datab (322:322:322) (379:379:379)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (324:324:324) (381:381:381)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (324:324:324) (381:381:381)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (391:391:391)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[5\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (389:389:389)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (393:393:393)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[8\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[9\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (329:329:329) (386:386:386)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (405:405:405)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT asdata (1590:1590:1590) (1467:1467:1467)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1157:1157:1157) (966:966:966)) + (PORT datab (1146:1146:1146) (972:972:972)) + (PORT datad (275:275:275) (329:329:329)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1667:1667:1667) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4540:4540:4540) (4423:4423:4423)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (761:761:761) (628:628:628)) + (PORT datab (386:386:386) (458:458:458)) + (PORT datac (759:759:759) (622:622:622)) + (PORT datad (340:340:340) (425:425:425)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (963:963:963) (812:812:812)) + (PORT datab (897:897:897) (781:781:781)) + (PORT datac (1118:1118:1118) (953:953:953)) + (PORT datad (1233:1233:1233) (1105:1105:1105)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (473:473:473)) + (PORT datab (867:867:867) (688:688:688)) + (PORT datac (1434:1434:1434) (1216:1216:1216)) + (PORT datad (344:344:344) (420:420:420)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~1) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (473:473:473)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (752:752:752) (612:612:612)) + (PORT datad (345:345:345) (422:422:422)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (843:843:843)) + (PORT datab (355:355:355) (421:421:421)) + (PORT datac (1082:1082:1082) (891:891:891)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1667:1667:1667) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4540:4540:4540) (4423:4423:4423)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (380:380:380)) + (PORT datab (624:624:624) (588:588:588)) + (PORT datac (1189:1189:1189) (1066:1066:1066)) + (PORT datad (319:319:319) (392:392:392)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\~0) + (DELAY + (ABSOLUTE + (PORT datac (502:502:502) (492:492:492)) + (PORT datad (521:521:521) (503:503:503)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|WideOr5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1699:1699:1699) (1456:1456:1456)) + (PORT datad (1586:1586:1586) (1388:1388:1388)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (447:447:447)) + (PORT datab (350:350:350) (408:408:408)) + (PORT datac (233:233:233) (251:251:251)) + (PORT datad (956:956:956) (879:879:879)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (404:404:404)) + (PORT datab (391:391:391) (463:463:463)) + (PORT datac (859:859:859) (806:806:806)) + (PORT datad (1105:1105:1105) (964:964:964)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector21\~0) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (445:445:445)) + (PORT datab (276:276:276) (286:286:286)) + (PORT datac (305:305:305) (372:372:372)) + (PORT datad (300:300:300) (356:356:356)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (386:386:386) (475:475:475)) + (PORT datac (311:311:311) (386:386:386)) + (PORT datad (344:344:344) (420:420:420)) + (IOPATH dataa combout (375:375:375) (392:392:392)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (387:387:387) (477:477:477)) + (PORT datab (357:357:357) (424:424:424)) + (PORT datac (284:284:284) (351:351:351)) + (PORT datad (343:343:343) (419:419:419)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (282:282:282)) + (PORT datab (284:284:284) (296:296:296)) + (PORT datad (276:276:276) (294:294:294)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (PORT ena (968:968:968) (936:936:936)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (417:417:417)) + (PORT datab (349:349:349) (407:407:407)) + (PORT datac (307:307:307) (374:374:374)) + (PORT datad (309:309:309) (370:370:370)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1693:1693:1693) (1643:1643:1643)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE read_valid) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4924:4924:4924) (4848:4848:4848)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~0) + (DELAY + (ABSOLUTE + (PORT datac (234:234:234) (252:252:252)) + (PORT datad (235:235:235) (246:246:246)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1552:1552:1552) (1398:1398:1398)) + (PORT datab (971:971:971) (880:880:880)) + (PORT datac (224:224:224) (239:239:239)) + (PORT datad (236:236:236) (248:248:248)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_TMRD) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.IDLE\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1103:1103:1103)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1639:1639:1639)) + (PORT ena (1012:1012:1012) (982:982:982)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT datab (907:907:907) (845:845:845)) + (PORT datad (935:935:935) (845:845:845)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1532:1532:1532) (1370:1370:1370)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~0) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (542:542:542)) + (PORT datab (557:557:557) (544:544:544)) + (PORT datac (883:883:883) (812:812:812)) + (PORT datad (883:883:883) (834:834:834)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1532:1532:1532) (1370:1370:1370)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1532:1532:1532) (1370:1370:1370)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1532:1532:1532) (1370:1370:1370)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1532:1532:1532) (1370:1370:1370)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~1) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (550:550:550)) + (PORT datab (349:349:349) (407:407:407)) + (PORT datac (294:294:294) (364:364:364)) + (PORT datad (307:307:307) (366:366:366)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1532:1532:1532) (1370:1370:1370)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1532:1532:1532) (1370:1370:1370)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1532:1532:1532) (1370:1370:1370)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~2) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (406:406:406)) + (PORT datab (348:348:348) (406:406:406)) + (PORT datac (298:298:298) (362:362:362)) + (PORT datad (308:308:308) (369:369:369)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~3) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (702:702:702)) + (PORT datab (854:854:854) (716:716:716)) + (PORT datac (910:910:910) (832:832:832)) + (PORT datad (228:228:228) (236:236:236)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5193:5193:5193)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (543:543:543)) + (PORT datab (347:347:347) (405:405:405)) + (PORT datac (291:291:291) (360:360:360)) + (PORT datad (304:304:304) (363:363:363)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (404:404:404)) + (PORT datab (270:270:270) (278:278:278)) + (PORT datac (305:305:305) (372:372:372)) + (PORT datad (300:300:300) (355:355:355)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (388:388:388)) + (PORT datac (927:927:927) (857:857:857)) + (PORT datad (1243:1243:1243) (1125:1125:1125)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~2) + (DELAY + (ABSOLUTE + (PORT datac (441:441:441) (389:389:389)) + (PORT datad (294:294:294) (322:322:322)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT asdata (922:922:922) (926:926:926)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (294:294:294) (363:363:363)) + (PORT datad (830:830:830) (720:720:720)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1673:1673:1673)) + (PORT asdata (1611:1611:1611) (1520:1520:1520)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (397:397:397)) + (PORT datac (293:293:293) (362:362:362)) + (PORT datad (828:828:828) (719:719:719)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (1281:1281:1281) (1163:1163:1163)) + (PORT datab (1304:1304:1304) (1167:1167:1167)) + (PORT datac (1246:1246:1246) (1145:1145:1145)) + (PORT datad (242:242:242) (255:255:255)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datab (1269:1269:1269) (1163:1163:1163)) + (PORT datac (228:228:228) (243:243:243)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (870:870:870)) + (PORT datab (950:950:950) (807:807:807)) + (PORT datad (935:935:935) (872:872:872)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datab (952:952:952) (809:809:809)) + (PORT datad (936:936:936) (873:873:873)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (398:398:398)) + (PORT datac (299:299:299) (363:363:363)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (565:565:565)) + (PORT datac (331:331:331) (399:399:399)) + (PORT datad (317:317:317) (380:380:380)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT dataa (1302:1302:1302) (1134:1134:1134)) + (PORT datac (314:314:314) (389:389:389)) + (PORT datad (244:244:244) (258:258:258)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (493:493:493) (495:495:495)) + (PORT datad (821:821:821) (704:704:704)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (859:859:859)) + (PORT datab (923:923:923) (836:836:836)) + (PORT datac (495:495:495) (428:428:428)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT asdata (1652:1652:1652) (1518:1518:1518)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (PORT ena (1955:1955:1955) (1752:1752:1752)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datac (225:225:225) (240:240:240)) + (PORT datad (827:827:827) (767:767:767)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datac (315:315:315) (390:390:390)) + (PORT datad (245:245:245) (258:258:258)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (385:385:385)) + (PORT datac (295:295:295) (365:365:365)) + (PORT datad (510:510:510) (497:497:497)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT datac (295:295:295) (364:364:364)) + (PORT datad (509:509:509) (497:497:497)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1683:1683:1683)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4763:4763:4763) (4712:4712:4712)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1683:1683:1683)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4763:4763:4763) (4712:4712:4712)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1683:1683:1683)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4763:4763:4763) (4712:4712:4712)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1683:1683:1683)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4763:4763:4763) (4712:4712:4712)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (PORT datab (340:340:340) (395:395:395)) + (PORT datac (298:298:298) (361:361:361)) + (PORT datad (299:299:299) (354:354:354)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4924:4924:4924) (4848:4848:4848)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4924:4924:4924) (4848:4848:4848)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4924:4924:4924) (4848:4848:4848)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4924:4924:4924) (4848:4848:4848)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (PORT datab (338:338:338) (394:394:394)) + (PORT datac (297:297:297) (360:360:360)) + (PORT datad (491:491:491) (481:481:481)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1683:1683:1683)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4763:4763:4763) (4712:4712:4712)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1683:1683:1683)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4763:4763:4763) (4712:4712:4712)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1683:1683:1683)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4763:4763:4763) (4712:4712:4712)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1683:1683:1683)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4763:4763:4763) (4712:4712:4712)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (401:401:401)) + (PORT datab (338:338:338) (393:393:393)) + (PORT datac (296:296:296) (360:360:360)) + (PORT datad (298:298:298) (354:354:354)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1683:1683:1683)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4763:4763:4763) (4712:4712:4712)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1683:1683:1683)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4763:4763:4763) (4712:4712:4712)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1683:1683:1683)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4763:4763:4763) (4712:4712:4712)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1683:1683:1683)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4763:4763:4763) (4712:4712:4712)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (525:525:525)) + (PORT datab (342:342:342) (398:398:398)) + (PORT datac (299:299:299) (363:363:363)) + (PORT datad (300:300:300) (356:356:356)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (266:266:266) (273:273:273)) + (PORT datac (228:228:228) (243:243:243)) + (PORT datad (823:823:823) (684:684:684)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE read_valid\~0) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (729:729:729)) + (PORT datab (820:820:820) (710:710:710)) + (PORT datac (909:909:909) (787:787:787)) + (PORT datad (300:300:300) (355:355:355)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE read_valid\~1) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (773:773:773)) + (PORT datab (906:906:906) (772:772:772)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (563:563:563) (541:541:541)) + (PORT datab (343:343:343) (398:398:398)) + (PORT datad (490:490:490) (439:439:439)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (571:571:571)) + (PORT datab (382:382:382) (453:453:453)) + (PORT datac (341:341:341) (418:418:418)) + (PORT datad (290:290:290) (352:352:352)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (394:394:394)) + (PORT datab (358:358:358) (420:420:420)) + (PORT datac (293:293:293) (362:362:362)) + (PORT datad (284:284:284) (342:342:342)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~2) + (DELAY + (ABSOLUTE + (PORT datab (270:270:270) (277:277:277)) + (PORT datac (324:324:324) (388:388:388)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (825:825:825)) + (PORT datab (951:951:951) (864:864:864)) + (PORT datad (812:812:812) (691:691:691)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (409:409:409)) + (PORT datab (337:337:337) (398:398:398)) + (PORT datac (294:294:294) (364:364:364)) + (PORT datad (293:293:293) (355:355:355)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT asdata (1898:1898:1898) (1732:1732:1732)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (PORT ena (1981:1981:1981) (1791:1791:1791)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (416:416:416)) + (PORT datab (1213:1213:1213) (1107:1107:1107)) + (PORT datad (1199:1199:1199) (1091:1091:1091)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT asdata (2051:2051:2051) (1882:1882:1882)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (PORT ena (1613:1613:1613) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (552:552:552)) + (PORT datab (552:552:552) (531:531:531)) + (PORT datad (308:308:308) (367:367:367)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (416:416:416)) + (PORT datab (573:573:573) (556:556:556)) + (PORT datad (545:545:545) (517:517:517)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT datac (438:438:438) (386:386:386)) + (PORT datad (229:229:229) (237:237:237)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1229:1229:1229) (1110:1110:1110)) + (PORT datab (940:940:940) (860:860:860)) + (PORT datad (301:301:301) (357:357:357)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (525:525:525)) + (PORT datab (339:339:339) (395:395:395)) + (PORT datad (307:307:307) (366:366:366)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (412:412:412)) + (PORT datab (341:341:341) (396:396:396)) + (PORT datad (299:299:299) (355:355:355)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (225:225:225) (240:240:240)) + (PORT datad (803:803:803) (678:678:678)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1180:1180:1180) (1012:1012:1012)) + (PORT datab (1229:1229:1229) (1045:1045:1045)) + (PORT datac (1215:1215:1215) (1040:1040:1040)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (400:400:400)) + (PORT datab (346:346:346) (404:404:404)) + (PORT datad (552:552:552) (530:530:530)) + (IOPATH dataa combout (394:394:394) (419:419:419)) + (IOPATH datab combout (400:400:400) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (589:589:589)) + (PORT datab (348:348:348) (406:406:406)) + (PORT datad (315:315:315) (378:378:378)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT asdata (2404:2404:2404) (2152:2152:2152)) + (PORT clrn (1693:1693:1693) (1645:1645:1645)) + (PORT ena (1622:1622:1622) (1494:1494:1494)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (679:679:679)) + (PORT datab (482:482:482) (417:417:417)) + (PORT datad (328:328:328) (387:387:387)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (435:435:435)) + (PORT datab (608:608:608) (563:563:563)) + (PORT datad (545:545:545) (518:518:518)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (545:545:545)) + (PORT datab (364:364:364) (419:419:419)) + (PORT datad (541:541:541) (517:517:517)) + (IOPATH dataa combout (394:394:394) (419:419:419)) + (IOPATH datab combout (400:400:400) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (452:452:452)) + (PORT datab (534:534:534) (522:522:522)) + (PORT datad (228:228:228) (236:236:236)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (345:345:345)) + (PORT datac (769:769:769) (666:666:666)) + (PORT datad (842:842:842) (708:708:708)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1307:1307:1307) (1170:1170:1170)) + (PORT datab (1719:1719:1719) (1507:1507:1507)) + (PORT datad (483:483:483) (469:469:469)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (538:538:538) (518:518:518)) + (PORT datab (913:913:913) (860:860:860)) + (PORT datad (1236:1236:1236) (1111:1111:1111)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT asdata (1243:1243:1243) (1180:1180:1180)) + (PORT clrn (1693:1693:1693) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (815:815:815)) + (PORT datab (348:348:348) (406:406:406)) + (PORT datad (299:299:299) (355:355:355)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (281:281:281)) + (PORT datab (938:938:938) (814:814:814)) + (PORT datad (496:496:496) (489:489:489)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT asdata (1287:1287:1287) (1192:1192:1192)) + (PORT clrn (1693:1693:1693) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (520:520:520)) + (PORT datab (1003:1003:1003) (899:899:899)) + (PORT datad (1237:1237:1237) (1102:1102:1102)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (416:416:416)) + (PORT datab (307:307:307) (321:321:321)) + (PORT datac (314:314:314) (384:384:384)) + (PORT datad (315:315:315) (378:378:378)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (392:392:392)) + (PORT datab (326:326:326) (383:383:383)) + (PORT datac (282:282:282) (348:348:348)) + (PORT datad (285:285:285) (344:344:344)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (538:538:538)) + (PORT datab (326:326:326) (383:383:383)) + (PORT datac (285:285:285) (352:352:352)) + (PORT datad (285:285:285) (343:343:343)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (394:394:394)) + (PORT datab (327:327:327) (384:384:384)) + (PORT datac (285:285:285) (352:352:352)) + (PORT datad (285:285:285) (344:344:344)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (392:392:392)) + (PORT datab (326:326:326) (383:383:383)) + (PORT datac (283:283:283) (349:349:349)) + (PORT datad (286:286:286) (344:344:344)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (703:703:703)) + (PORT datab (266:266:266) (273:273:273)) + (PORT datac (224:224:224) (239:239:239)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (393:393:393)) + (PORT datab (326:326:326) (383:383:383)) + (PORT datac (284:284:284) (350:350:350)) + (PORT datad (286:286:286) (345:345:345)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (536:536:536)) + (PORT datab (325:325:325) (382:382:382)) + (PORT datac (283:283:283) (350:350:350)) + (PORT datad (284:284:284) (343:343:343)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[8\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (747:747:747)) + (PORT datab (819:819:819) (709:709:709)) + (PORT datac (839:839:839) (723:723:723)) + (PORT datad (828:828:828) (712:712:712)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[15\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (748:748:748)) + (PORT datab (821:821:821) (711:711:711)) + (PORT datac (840:840:840) (725:725:725)) + (PORT datad (830:830:830) (714:714:714)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[15\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (455:455:455)) + (PORT datab (976:976:976) (874:874:874)) + (PORT datad (925:925:925) (825:825:825)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[14\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (875:875:875)) + (PORT datab (480:480:480) (418:418:418)) + (PORT datad (914:914:914) (833:833:833)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[13\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (967:967:967) (873:873:873)) + (PORT datab (736:736:736) (602:602:602)) + (PORT datad (916:916:916) (835:835:835)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[12\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (967:967:967) (874:874:874)) + (PORT datab (536:536:536) (442:442:442)) + (PORT datad (915:915:915) (835:835:835)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[9\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (345:345:345)) + (PORT datab (861:861:861) (718:718:718)) + (PORT datad (270:270:270) (288:288:288)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[11\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (345:345:345)) + (PORT datab (814:814:814) (705:705:705)) + (PORT datad (272:272:272) (290:290:290)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[10\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (345:345:345)) + (PORT datab (804:804:804) (699:699:699)) + (PORT datad (272:272:272) (289:289:289)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[8\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (344:344:344)) + (PORT datab (888:888:888) (739:739:739)) + (PORT datad (272:272:272) (290:290:290)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[7\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (962:962:962) (867:867:867)) + (PORT datab (539:539:539) (448:448:448)) + (PORT datad (921:921:921) (842:842:842)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (964:964:964) (870:870:870)) + (PORT datab (540:540:540) (449:449:449)) + (PORT datad (918:918:918) (839:839:839)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[5\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (965:965:965) (870:870:870)) + (PORT datab (484:484:484) (424:424:424)) + (PORT datad (918:918:918) (838:838:838)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (872:872:872)) + (PORT datab (542:542:542) (452:452:452)) + (PORT datad (917:917:917) (837:837:837)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (430:430:430)) + (PORT datab (982:982:982) (881:881:881)) + (PORT datad (919:919:919) (819:819:819)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (459:459:459)) + (PORT datab (982:982:982) (881:881:881)) + (PORT datad (919:919:919) (819:819:819)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (431:431:431)) + (PORT datab (983:983:983) (882:882:882)) + (PORT datad (918:918:918) (817:817:817)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (872:872:872)) + (PORT datab (543:543:543) (453:453:453)) + (PORT datad (916:916:916) (836:836:836)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1290:1290:1290) (1102:1102:1102)) + (PORT datab (992:992:992) (890:890:890)) + (PORT datad (550:550:550) (526:526:526)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (624:624:624) (580:580:580)) + (PORT datab (554:554:554) (543:543:543)) + (PORT datad (918:918:918) (834:834:834)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (883:883:883) (808:808:808)) + (PORT datab (569:569:569) (545:545:545)) + (PORT datac (867:867:867) (798:798:798)) + (PORT datad (847:847:847) (787:787:787)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (286:286:286)) + (PORT datab (267:267:267) (273:273:273)) + (PORT datac (1599:1599:1599) (1365:1365:1365)) + (PORT datad (229:229:229) (236:236:236)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (819:819:819)) + (PORT datab (952:952:952) (862:862:862)) + (PORT datad (299:299:299) (354:354:354)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb\|data_wire\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (1848:1848:1848) (1565:1565:1565)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (757:757:757)) + (PORT datab (1128:1128:1128) (927:927:927)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (560:560:560)) + (PORT datab (530:530:530) (511:511:511)) + (PORT datad (1566:1566:1566) (1379:1379:1379)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (434:434:434)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (439:439:439) (373:373:373)) + (PORT datad (282:282:282) (304:304:304)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1291:1291:1291) (1112:1112:1112)) + (PORT datab (351:351:351) (417:417:417)) + (PORT datad (878:878:878) (799:799:799)) + (IOPATH dataa combout (394:394:394) (419:419:419)) + (IOPATH datab combout (400:400:400) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (404:404:404)) + (PORT datab (934:934:934) (844:844:844)) + (PORT datac (1333:1333:1333) (1192:1192:1192)) + (PORT datad (304:304:304) (373:373:373)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (430:430:430)) + (PORT datab (353:353:353) (420:420:420)) + (PORT datac (854:854:854) (786:786:786)) + (PORT datad (856:856:856) (784:784:784)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (928:928:928) (774:774:774)) + (PORT datab (328:328:328) (348:348:348)) + (PORT datad (480:480:480) (408:408:408)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (806:806:806)) + (PORT datab (539:539:539) (521:521:521)) + (PORT datad (527:527:527) (499:499:499)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (966:966:966) (865:865:865)) + (PORT datab (342:342:342) (397:397:397)) + (PORT datad (838:838:838) (750:750:750)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (429:429:429)) + (PORT datab (957:957:957) (847:847:847)) + (PORT datad (837:837:837) (781:781:781)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (424:424:424)) + (PORT datab (357:357:357) (418:418:418)) + (PORT datac (1184:1184:1184) (1059:1059:1059)) + (PORT datad (336:336:336) (398:398:398)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|rd_flag) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5255:5255:5255) (5235:5235:5235)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (404:404:404)) + (PORT datab (334:334:334) (394:394:394)) + (PORT datac (291:291:291) (361:361:361)) + (PORT datad (292:292:292) (354:354:354)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|cntr_cout\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1289:1289:1289) (1175:1175:1175)) + (PORT datab (895:895:895) (831:831:831)) + (PORT datac (464:464:464) (403:403:403)) + (PORT datad (288:288:288) (348:348:348)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (PORT ena (1667:1667:1667) (1526:1526:1526)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (394:394:394)) + (PORT datab (328:328:328) (385:385:385)) + (PORT datac (285:285:285) (351:351:351)) + (PORT datad (288:288:288) (346:346:346)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (394:394:394)) + (PORT datab (327:327:327) (384:384:384)) + (PORT datac (285:285:285) (351:351:351)) + (PORT datad (287:287:287) (347:347:347)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (419:419:419)) + (PORT datab (326:326:326) (383:383:383)) + (PORT datac (225:225:225) (240:240:240)) + (PORT datad (285:285:285) (344:344:344)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|rd_flag\~0) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (787:787:787)) + (PORT datab (964:964:964) (881:881:881)) + (PORT datad (236:236:236) (248:248:248)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (418:418:418)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (313:313:313) (388:388:388)) + (PORT datad (254:254:254) (273:273:273)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1071:1071:1071)) + (PORT datab (360:360:360) (421:421:421)) + (PORT datac (314:314:314) (386:386:386)) + (PORT datad (308:308:308) (367:367:367)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|start_nedge) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (1257:1257:1257) (1073:1073:1073)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (PORT datad (299:299:299) (355:355:355)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (846:846:846)) + (PORT datab (312:312:312) (328:328:328)) + (PORT datad (840:840:840) (759:759:759)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1456:1456:1456) (1274:1274:1274)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1147:1147:1147) (1013:1013:1013)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (301:301:301) (357:357:357)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (843:843:843) (773:773:773)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (527:527:527) (498:498:498)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tx\~output) + (DELAY + (ABSOLUTE + (PORT i (2198:2198:2198) (2389:2389:2389)) + (IOPATH i o (2961:2961:2961) (3013:3013:3013)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_clk\~output) + (DELAY + (ABSOLUTE + (PORT i (1468:1468:1468) (1389:1389:1389)) + (IOPATH i o (2892:2892:2892) (2812:2812:2812)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_cas_n\~output) + (DELAY + (ABSOLUTE + (PORT i (2130:2130:2130) (1818:1818:1818)) + (IOPATH i o (2912:2912:2912) (2832:2832:2832)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_ras_n\~output) + (DELAY + (ABSOLUTE + (PORT i (2298:2298:2298) (1877:1877:1877)) + (IOPATH i o (4163:4163:4163) (4170:4170:4170)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_we_n\~output) + (DELAY + (ABSOLUTE + (PORT i (2301:2301:2301) (2012:2012:2012)) + (IOPATH i o (2932:2932:2932) (2852:2852:2852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_ba\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3246:3246:3246) (2813:2813:2813)) + (IOPATH i o (2912:2912:2912) (2832:2832:2832)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_ba\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3529:3529:3529) (3038:3038:3038)) + (IOPATH i o (2912:2912:2912) (2832:2832:2832)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2613:2613:2613) (2134:2134:2134)) + (IOPATH i o (2922:2922:2922) (2842:2842:2842)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2607:2607:2607) (2136:2136:2136)) + (IOPATH i o (3043:3043:3043) (2991:2991:2991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2607:2607:2607) (2136:2136:2136)) + (IOPATH i o (3043:3043:3043) (2991:2991:2991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3239:3239:3239) (2808:2808:2808)) + (IOPATH i o (3043:3043:3043) (2991:2991:2991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2994:2994:2994) (2460:2460:2460)) + (IOPATH i o (3043:3043:3043) (2991:2991:2991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3011:3011:3011) (2481:2481:2481)) + (IOPATH i o (3023:3023:3023) (2971:2971:2971)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (4333:4333:4333) (3744:3744:3744)) + (IOPATH i o (3023:3023:3023) (2971:2971:2971)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3936:3936:3936) (3401:3401:3401)) + (IOPATH i o (3013:3013:3013) (2961:2961:2961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (4339:4339:4339) (3751:3751:3751)) + (IOPATH i o (3023:3023:3023) (2971:2971:2971)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2581:2581:2581) (2243:2243:2243)) + (IOPATH i o (3013:3013:3013) (2961:2961:2961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2598:2598:2598) (2252:2252:2252)) + (IOPATH i o (2932:2932:2932) (2852:2852:2852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2581:2581:2581) (2243:2243:2243)) + (IOPATH i o (3023:3023:3023) (2971:2971:2971)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3140:3140:3140) (2670:2670:2670)) + (IOPATH i o (3013:3013:3013) (2961:2961:2961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1486:1486:1486) (1268:1268:1268)) + (PORT oe (1586:1586:1586) (1428:1428:1428)) + (IOPATH i o (2912:2912:2912) (2832:2832:2832)) + (IOPATH oe o (2938:2938:2938) (2788:2788:2788)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1432:1432:1432) (1218:1218:1218)) + (PORT oe (1586:1586:1586) (1428:1428:1428)) + (IOPATH i o (2912:2912:2912) (2832:2832:2832)) + (IOPATH oe o (2938:2938:2938) (2788:2788:2788)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1514:1514:1514) (1298:1298:1298)) + (PORT oe (1964:1964:1964) (1728:1728:1728)) + (IOPATH i o (2872:2872:2872) (2792:2792:2792)) + (IOPATH oe o (2938:2938:2938) (2788:2788:2788)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1072:1072:1072) (892:892:892)) + (PORT oe (1201:1201:1201) (1085:1085:1085)) + (IOPATH i o (2902:2902:2902) (2822:2822:2822)) + (IOPATH oe o (2938:2938:2938) (2788:2788:2788)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1089:1089:1089) (918:918:918)) + (PORT oe (1201:1201:1201) (1085:1085:1085)) + (IOPATH i o (2912:2912:2912) (2832:2832:2832)) + (IOPATH oe o (2938:2938:2938) (2788:2788:2788)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1463:1463:1463) (1242:1242:1242)) + (PORT oe (1964:1964:1964) (1728:1728:1728)) + (IOPATH i o (2892:2892:2892) (2812:2812:2812)) + (IOPATH oe o (2938:2938:2938) (2788:2788:2788)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1480:1480:1480) (1263:1263:1263)) + (PORT oe (1586:1586:1586) (1428:1428:1428)) + (IOPATH i o (2922:2922:2922) (2842:2842:2842)) + (IOPATH oe o (2938:2938:2938) (2788:2788:2788)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1160:1160:1160) (988:988:988)) + (PORT oe (1586:1586:1586) (1428:1428:1428)) + (IOPATH i o (2912:2912:2912) (2832:2832:2832)) + (IOPATH oe o (2938:2938:2938) (2788:2788:2788)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1578:1578:1578) (1371:1371:1371)) + (PORT oe (2587:2587:2587) (2226:2226:2226)) + (IOPATH i o (3023:3023:3023) (2971:2971:2971)) + (IOPATH oe o (3016:3016:3016) (2899:2899:2899)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1698:1698:1698) (1403:1403:1403)) + (PORT oe (2195:2195:2195) (1907:1907:1907)) + (IOPATH i o (2922:2922:2922) (2842:2842:2842)) + (IOPATH oe o (2938:2938:2938) (2788:2788:2788)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2010:2010:2010) (1617:1617:1617)) + (PORT oe (1881:1881:1881) (1642:1642:1642)) + (IOPATH i o (3033:3033:3033) (2981:2981:2981)) + (IOPATH oe o (3016:3016:3016) (2899:2899:2899)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2133:2133:2133) (1821:1821:1821)) + (PORT oe (2213:2213:2213) (1922:1922:1922)) + (IOPATH i o (3013:3013:3013) (2961:2961:2961)) + (IOPATH oe o (3016:3016:3016) (2899:2899:2899)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1789:1789:1789) (1494:1494:1494)) + (PORT oe (2245:2245:2245) (1968:1968:1968)) + (IOPATH i o (3003:3003:3003) (2951:2951:2951)) + (IOPATH oe o (3016:3016:3016) (2899:2899:2899)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1455:1455:1455) (1209:1209:1209)) + (PORT oe (2252:2252:2252) (1977:1977:1977)) + (IOPATH i o (3013:3013:3013) (2961:2961:2961)) + (IOPATH oe o (3016:3016:3016) (2899:2899:2899)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1711:1711:1711) (1368:1368:1368)) + (PORT oe (2252:2252:2252) (1976:1976:1976)) + (IOPATH i o (4207:4207:4207) (4224:4224:4224)) + (IOPATH oe o (4220:4220:4220) (4166:4166:4166)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1616:1616:1616) (1301:1301:1301)) + (PORT oe (2252:2252:2252) (1977:1977:1977)) + (IOPATH i o (2938:2938:2938) (2862:2862:2862)) + (IOPATH oe o (2950:2950:2950) (2804:2804:2804)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (546:546:546)) + (PORT datab (338:338:338) (393:393:393)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (788:788:788) (813:813:813)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (4678:4678:4678) (4678:4678:4678)) + (PORT inclk[0] (2063:2063:2063) (2063:2063:2063)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (1917:1917:1917) (2106:2106:2106)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4924:4924:4924) (4848:4848:4848)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (4268:4268:4268) (4274:4274:4274)) + (PORT datac (1272:1272:1272) (1435:1435:1435)) + (PORT datad (275:275:275) (329:329:329)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2384:2384:2384) (2150:2150:2150)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (401:401:401)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (333:333:333) (393:393:393)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1100:1100:1100) (1090:1090:1090)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (400:400:400)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1100:1100:1100) (1090:1090:1090)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (409:409:409)) + (PORT datab (570:570:570) (546:546:546)) + (PORT datac (294:294:294) (364:364:364)) + (PORT datad (295:295:295) (359:359:359)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1100:1100:1100) (1090:1090:1090)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (383:383:383)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1100:1100:1100) (1090:1090:1090)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1100:1100:1100) (1090:1090:1090)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (616:616:616) (565:565:565)) + (PORT datab (328:328:328) (385:385:385)) + (PORT datac (283:283:283) (349:349:349)) + (PORT datad (286:286:286) (345:345:345)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1100:1100:1100) (1090:1090:1090)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1100:1100:1100) (1090:1090:1090)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datac (827:827:827) (734:734:734)) + (PORT datad (513:513:513) (499:499:499)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1100:1100:1100) (1090:1090:1090)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (575:575:575)) + (PORT datab (612:612:612) (564:564:564)) + (PORT datac (225:225:225) (240:240:240)) + (PORT datad (514:514:514) (495:495:495)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (PORT datab (472:472:472) (406:406:406)) + (PORT datac (484:484:484) (402:402:402)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1100:1100:1100) (1090:1090:1090)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1100:1100:1100) (1090:1090:1090)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1100:1100:1100) (1090:1090:1090)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (410:410:410)) + (PORT datab (571:571:571) (546:546:546)) + (PORT datac (294:294:294) (364:364:364)) + (PORT datad (295:295:295) (359:359:359)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (404:404:404)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (PORT sclr (1100:1100:1100) (1090:1090:1090)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (544:544:544)) + (PORT datab (609:609:609) (561:561:561)) + (PORT datac (826:826:826) (733:733:733)) + (PORT datad (512:512:512) (493:493:493)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (444:444:444)) + (PORT datab (532:532:532) (435:435:435)) + (PORT datac (565:565:565) (534:534:534)) + (PORT datad (229:229:229) (236:236:236)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (388:388:388)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (394:394:394)) + (PORT datab (329:329:329) (386:386:386)) + (PORT datac (287:287:287) (354:354:354)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (416:416:416)) + (PORT datab (293:293:293) (309:309:309)) + (PORT datac (311:311:311) (386:386:386)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_flag) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_flag) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT asdata (1635:1635:1635) (1522:1522:1522)) + (PORT clrn (1676:1676:1676) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (419:419:419)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a0) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (PORT ena (2349:2349:2349) (2100:2100:2100)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (417:417:417)) + (PORT datab (1975:1975:1975) (1689:1689:1689)) + (PORT datad (543:543:543) (539:539:539)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (584:584:584)) + (PORT datab (358:358:358) (419:419:419)) + (PORT datac (302:302:302) (376:376:376)) + (PORT datad (1621:1621:1621) (1400:1400:1400)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (233:233:233)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (310:310:310) (324:324:324)) + (PORT datad (536:536:536) (526:526:526)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~10) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (576:576:576)) + (PORT datab (361:361:361) (422:422:422)) + (PORT datac (332:332:332) (407:407:407)) + (PORT datad (539:539:539) (528:528:528)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (PORT ena (2349:2349:2349) (2100:2100:2100)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (444:444:444)) + (PORT datab (376:376:376) (442:442:442)) + (PORT datad (535:535:535) (525:525:525)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (432:432:432)) + (PORT datab (311:311:311) (325:325:325)) + (PORT datac (330:330:330) (405:405:405)) + (PORT datad (306:306:306) (365:365:365)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (798:798:798) (678:678:678)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (468:468:468)) + (PORT datad (795:795:795) (685:685:685)) + (IOPATH dataa combout (375:375:375) (392:392:392)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT dataa (914:914:914) (845:845:845)) + (PORT datab (354:354:354) (420:420:420)) + (PORT datac (344:344:344) (426:426:426)) + (PORT datad (333:333:333) (405:405:405)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1628:1628:1628)) + (PORT ena (1068:1068:1068) (1053:1053:1053)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (448:448:448)) + (PORT datab (352:352:352) (418:418:418)) + (PORT datac (344:344:344) (426:426:426)) + (PORT datad (795:795:795) (685:685:685)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8\~0) + (DELAY + (ABSOLUTE + (PORT datad (427:427:427) (358:358:358)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1629:1629:1629)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (448:448:448)) + (PORT datab (353:353:353) (419:419:419)) + (PORT datac (342:342:342) (423:423:423)) + (PORT datad (794:794:794) (684:684:684)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10\~0) + (DELAY + (ABSOLUTE + (PORT datab (356:356:356) (423:423:423)) + (PORT datad (449:449:449) (378:378:378)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1629:1629:1629)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (422:422:422)) + (PORT datad (312:312:312) (382:382:382)) + (IOPATH dataa combout (375:375:375) (392:392:392)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1629:1629:1629)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT datab (353:353:353) (420:420:420)) + (PORT datac (294:294:294) (365:365:365)) + (PORT datad (762:762:762) (698:698:698)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1629:1629:1629)) + (PORT ena (1236:1236:1236) (1138:1138:1138)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT datab (322:322:322) (377:377:377)) + (PORT datac (871:871:871) (796:796:796)) + (PORT datad (1094:1094:1094) (959:959:959)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|parity9) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (PORT ena (2349:2349:2349) (2100:2100:2100)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (581:581:581)) + (PORT datab (356:356:356) (417:417:417)) + (PORT datac (301:301:301) (374:374:374)) + (PORT datad (1619:1619:1619) (1399:1399:1399)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (430:430:430)) + (PORT datab (309:309:309) (324:324:324)) + (PORT datac (330:330:330) (404:404:404)) + (PORT datad (306:306:306) (365:365:365)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (470:470:470)) + (PORT datab (836:836:836) (724:724:724)) + (PORT datad (332:332:332) (404:404:404)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT asdata (720:720:720) (789:789:789)) + (PORT clrn (1676:1676:1676) (1629:1629:1629)) + (PORT ena (1236:1236:1236) (1138:1138:1138)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (402:402:402)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (389:389:389)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (391:391:391)) + (PORT datab (325:325:325) (382:382:382)) + (PORT datac (283:283:283) (348:348:348)) + (PORT datad (285:285:285) (345:345:345)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (422:422:422)) + (PORT datab (347:347:347) (410:410:410)) + (PORT datac (303:303:303) (374:374:374)) + (PORT datad (302:302:302) (367:367:367)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (768:768:768)) + (PORT datab (569:569:569) (558:558:558)) + (PORT datac (499:499:499) (458:458:458)) + (PORT datad (488:488:488) (420:420:420)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (313:313:313) (383:383:383)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1629:1629:1629)) + (PORT ena (1236:1236:1236) (1138:1138:1138)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT asdata (932:932:932) (924:924:924)) + (PORT clrn (1676:1676:1676) (1629:1629:1629)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1120:1120:1120) (974:974:974)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (762:762:762) (697:697:697)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1629:1629:1629)) + (PORT ena (1236:1236:1236) (1138:1138:1138)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (308:308:308) (368:368:368)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1629:1629:1629)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1246:1246:1246) (1080:1080:1080)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (300:300:300) (356:356:356)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1629:1629:1629)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1110:1110:1110) (982:982:982)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (597:597:597) (548:548:548)) + (PORT datab (325:325:325) (383:383:383)) + (PORT datac (291:291:291) (361:361:361)) + (PORT datad (506:506:506) (493:493:493)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (334:334:334) (406:406:406)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1628:1628:1628)) + (PORT ena (1068:1068:1068) (1053:1053:1053)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT asdata (2251:2251:2251) (2035:2035:2035)) + (PORT clrn (1676:1676:1676) (1629:1629:1629)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT asdata (1183:1183:1183) (1095:1095:1095)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (395:395:395)) + (PORT datab (286:286:286) (299:299:299)) + (PORT datac (294:294:294) (364:364:364)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT asdata (1294:1294:1294) (1229:1229:1229)) + (PORT clrn (1676:1676:1676) (1628:1628:1628)) + (PORT ena (1068:1068:1068) (1053:1053:1053)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1206:1206:1206) (1079:1079:1079)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (309:309:309) (368:368:368)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (391:391:391)) + (PORT datab (286:286:286) (299:299:299)) + (PORT datac (294:294:294) (364:364:364)) + (PORT datad (276:276:276) (330:330:330)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (288:288:288) (301:301:301)) + (PORT datad (1239:1239:1239) (1117:1117:1117)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT asdata (742:742:742) (812:812:812)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (PORT ena (2349:2349:2349) (2100:2100:2100)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1637:1637:1637) (1453:1453:1453)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT asdata (759:759:759) (831:831:831)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (PORT ena (2349:2349:2349) (2100:2100:2100)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT asdata (1629:1629:1629) (1500:1500:1500)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (452:452:452)) + (PORT datab (340:340:340) (396:396:396)) + (PORT datad (1236:1236:1236) (1114:1114:1114)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (451:451:451)) + (PORT datab (286:286:286) (299:299:299)) + (PORT datac (299:299:299) (363:363:363)) + (PORT datad (1237:1237:1237) (1115:1115:1115)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (807:807:807) (683:683:683)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT asdata (766:766:766) (845:845:845)) + (PORT clrn (1676:1676:1676) (1628:1628:1628)) + (PORT ena (1068:1068:1068) (1053:1053:1053)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT asdata (1859:1859:1859) (1659:1659:1659)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (867:867:867)) + (PORT datab (362:362:362) (417:417:417)) + (PORT datad (305:305:305) (364:364:364)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT datad (339:339:339) (402:402:402)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (PORT ena (1667:1667:1667) (1526:1526:1526)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (597:597:597)) + (PORT datab (360:360:360) (421:421:421)) + (PORT datad (933:933:933) (820:820:820)) + (IOPATH dataa combout (377:377:377) (377:377:377)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (1123:1123:1123) (1004:1004:1004)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1628:1628:1628)) + (PORT ena (1068:1068:1068) (1053:1053:1053)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT asdata (2389:2389:2389) (2141:2141:2141)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (536:536:536) (527:527:527)) + (PORT datab (1269:1269:1269) (1140:1140:1140)) + (PORT datad (1244:1244:1244) (1117:1117:1117)) + (IOPATH dataa combout (394:394:394) (419:419:419)) + (IOPATH datab combout (400:400:400) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1197:1197:1197) (1035:1035:1035)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (1147:1147:1147) (966:966:966)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT asdata (1593:1593:1593) (1461:1461:1461)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (PORT ena (1033:1033:1033) (1005:1005:1005)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT asdata (1964:1964:1964) (1725:1725:1725)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (PORT ena (1955:1955:1955) (1752:1752:1752)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (869:869:869) (760:760:760)) + (PORT datab (813:813:813) (729:729:729)) + (PORT datad (1232:1232:1232) (1082:1082:1082)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1924:1924:1924) (1710:1710:1710)) + (PORT datab (609:609:609) (562:562:562)) + (PORT datad (498:498:498) (478:478:478)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (282:282:282)) + (PORT datab (1214:1214:1214) (1046:1046:1046)) + (PORT datac (1161:1161:1161) (967:967:967)) + (PORT datad (1803:1803:1803) (1497:1497:1497)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (225:225:225) (240:240:240)) + (PORT datad (480:480:480) (409:409:409)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT asdata (1649:1649:1649) (1515:1515:1515)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (PORT ena (1033:1033:1033) (1005:1005:1005)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (425:425:425)) + (PORT datab (944:944:944) (855:855:855)) + (PORT datad (1510:1510:1510) (1289:1289:1289)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT asdata (1322:1322:1322) (1252:1252:1252)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (PORT ena (1033:1033:1033) (1005:1005:1005)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT asdata (737:737:737) (809:809:809)) + (PORT clrn (1676:1676:1676) (1628:1628:1628)) + (PORT ena (1068:1068:1068) (1053:1053:1053)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1663:1663:1663)) + (PORT asdata (1190:1190:1190) (1108:1108:1108)) + (PORT clrn (1676:1676:1676) (1629:1629:1629)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (422:422:422)) + (PORT datab (270:270:270) (277:277:277)) + (PORT datad (858:858:858) (786:786:786)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (812:812:812)) + (PORT datab (340:340:340) (395:395:395)) + (PORT datad (1127:1127:1127) (1018:1018:1018)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datad (839:839:839) (784:784:784)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT datab (1152:1152:1152) (945:945:945)) + (PORT datac (767:767:767) (644:644:644)) + (PORT datad (1155:1155:1155) (990:990:990)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1538:1538:1538) (1254:1254:1254)) + (PORT datab (1569:1569:1569) (1375:1375:1375)) + (PORT datac (769:769:769) (694:694:694)) + (PORT datad (1207:1207:1207) (1048:1048:1048)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT asdata (2336:2336:2336) (2089:2089:2089)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (PORT ena (1955:1955:1955) (1752:1752:1752)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6\~0) + (DELAY + (ABSOLUTE + (PORT datab (294:294:294) (309:309:309)) + (PORT datad (1274:1274:1274) (1136:1136:1136)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT asdata (1546:1546:1546) (1418:1418:1418)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (PORT ena (1033:1033:1033) (1005:1005:1005)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (430:430:430)) + (PORT datab (554:554:554) (544:544:544)) + (PORT datac (299:299:299) (363:363:363)) + (PORT datad (525:525:525) (508:508:508)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (1295:1295:1295) (1126:1126:1126)) + (PORT datab (348:348:348) (414:414:414)) + (PORT datac (299:299:299) (363:363:363)) + (PORT datad (239:239:239) (253:253:253)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (317:317:317) (387:387:387)) + (PORT datad (1129:1129:1129) (924:924:924)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (1924:1924:1924) (1710:1710:1710)) + (PORT datac (315:315:315) (385:385:385)) + (PORT datad (1129:1129:1129) (923:923:923)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (552:552:552) (524:524:524)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT asdata (1542:1542:1542) (1417:1417:1417)) + (PORT clrn (1676:1676:1676) (1628:1628:1628)) + (PORT ena (1068:1068:1068) (1053:1053:1053)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (863:863:863) (786:786:786)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (500:500:500) (483:483:483)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (857:857:857)) + (PORT datab (922:922:922) (836:836:836)) + (PORT datac (494:494:494) (427:427:427)) + (PORT datad (856:856:856) (781:781:781)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (1246:1246:1246) (1103:1103:1103)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (PORT ena (1955:1955:1955) (1752:1752:1752)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT asdata (1678:1678:1678) (1538:1538:1538)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (PORT ena (1955:1955:1955) (1752:1752:1752)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (1921:1921:1921) (1707:1707:1707)) + (PORT datab (571:571:571) (546:546:546)) + (PORT datac (316:316:316) (386:386:386)) + (PORT datad (1129:1129:1129) (923:923:923)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datac (839:839:839) (769:769:769)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (377:377:377)) + (PORT datab (942:942:942) (836:836:836)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1539:1539:1539) (1338:1338:1338)) + (PORT datab (913:913:913) (819:819:819)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (822:822:822)) + (PORT datab (906:906:906) (832:832:832)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (818:818:818)) + (PORT datab (826:826:826) (717:717:717)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (764:764:764)) + (PORT datab (842:842:842) (736:736:736)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (399:399:399)) + (PORT datac (244:244:244) (266:266:266)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (792:792:792) (696:696:696)) + (PORT datab (838:838:838) (732:732:732)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (530:530:530) (510:510:510)) + (PORT datab (792:792:792) (695:695:695)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (227:227:227) (243:243:243)) + (PORT datad (229:229:229) (236:236:236)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (226:226:226) (242:242:242)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1333:1333:1333) (1176:1176:1176)) + (PORT datab (956:956:956) (857:857:857)) + (PORT datac (250:250:250) (274:274:274)) + (PORT datad (882:882:882) (799:799:799)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9\~0) + (DELAY + (ABSOLUTE + (PORT datab (277:277:277) (287:287:287)) + (PORT datad (308:308:308) (367:367:367)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT asdata (1295:1295:1295) (1231:1231:1231)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (PORT ena (1033:1033:1033) (1005:1005:1005)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT datac (318:318:318) (389:389:389)) + (PORT datad (315:315:315) (389:389:389)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (434:434:434)) + (PORT datac (316:316:316) (388:388:388)) + (PORT datad (529:529:529) (512:512:512)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (541:541:541)) + (PORT datad (783:783:783) (684:684:684)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_wr_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2221:2221:2221) (1901:1901:1901)) + (PORT datab (289:289:289) (296:296:296)) + (PORT datac (249:249:249) (266:266:266)) + (PORT datad (251:251:251) (259:259:259)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_wr_req) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (744:744:744)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (PORT ena (1068:1068:1068) (1054:1054:1054)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (749:749:749)) + (PORT datab (323:323:323) (343:343:343)) + (PORT datad (531:531:531) (518:518:518)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1657:1657:1657) (1481:1481:1481)) + (PORT datab (1667:1667:1667) (1491:1491:1491)) + (PORT datac (914:914:914) (826:826:826)) + (PORT datad (2008:2008:2008) (1776:1776:1776)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (PORT ena (1613:1613:1613) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (301:301:301) (323:323:323)) + (PORT datab (363:363:363) (426:426:426)) + (PORT datad (300:300:300) (356:356:356)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~10) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (818:818:818)) + (PORT datab (1656:1656:1656) (1457:1457:1457)) + (PORT datac (866:866:866) (782:782:782)) + (PORT datad (799:799:799) (738:738:738)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (PORT ena (1613:1613:1613) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (417:417:417)) + (PORT datab (307:307:307) (321:321:321)) + (PORT datac (315:315:315) (385:385:385)) + (PORT datad (316:316:316) (378:378:378)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8\~0) + (DELAY + (ABSOLUTE + (PORT datad (807:807:807) (680:680:680)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (717:717:717)) + (PORT datad (321:321:321) (384:384:384)) + (IOPATH dataa combout (375:375:375) (392:392:392)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (716:716:716)) + (PORT datab (362:362:362) (424:424:424)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT datab (356:356:356) (418:418:418)) + (PORT datac (309:309:309) (375:375:375)) + (PORT datad (310:310:310) (369:369:369)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1665:1665:1665) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1697:1697:1697) (1649:1649:1649)) + (PORT ena (1659:1659:1659) (1498:1498:1498)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT datab (321:321:321) (376:376:376)) + (PORT datac (277:277:277) (340:340:340)) + (PORT datad (1259:1259:1259) (1103:1103:1103)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|parity6) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (PORT ena (1613:1613:1613) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (419:419:419)) + (PORT datab (330:330:330) (351:351:351)) + (PORT datac (784:784:784) (703:703:703)) + (PORT datad (524:524:524) (510:510:510)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (542:542:542)) + (PORT datab (573:573:573) (552:552:552)) + (PORT datac (255:255:255) (282:282:282)) + (PORT datad (321:321:321) (386:386:386)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5\~0) + (DELAY + (ABSOLUTE + (PORT datab (269:269:269) (276:276:276)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (501:501:501) (448:448:448)) + (PORT datab (356:356:356) (416:416:416)) + (PORT datad (524:524:524) (513:513:513)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (763:763:763)) + (PORT datab (892:892:892) (840:840:840)) + (PORT datad (317:317:317) (380:380:380)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1693:1693:1693) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (560:560:560)) + (PORT datab (938:938:938) (878:878:878)) + (PORT datac (1913:1913:1913) (1688:1688:1688)) + (PORT datad (829:829:829) (739:739:739)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (403:403:403)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|rd_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (576:576:576)) + (PORT datab (1187:1187:1187) (1052:1052:1052)) + (PORT datad (252:252:252) (271:271:271)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|rd_en) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (408:408:408)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (421:421:421)) + (PORT datac (303:303:303) (374:374:374)) + (PORT datad (302:302:302) (368:368:368)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (356:356:356) (417:417:417)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[5\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[8\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (406:406:406)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[9\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (416:416:416)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT datac (869:869:869) (809:809:809)) + (PORT datad (923:923:923) (848:848:848)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (925:925:925) (805:805:805)) + (PORT datab (1015:1015:1015) (917:917:917)) + (PORT datac (837:837:837) (726:726:726)) + (PORT datad (868:868:868) (762:762:762)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datab (619:619:619) (575:575:575)) + (PORT datad (470:470:470) (410:410:410)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_CL) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1266:1266:1266) (1048:1048:1048)) + (PORT datab (350:350:350) (408:408:408)) + (PORT datad (469:469:469) (409:409:409)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_DATA) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (392:392:392)) + (PORT datab (325:325:325) (382:382:382)) + (PORT datac (283:283:283) (349:349:349)) + (PORT datad (284:284:284) (342:342:342)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|tread_end\~3) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (781:781:781)) + (PORT datab (931:931:931) (805:805:805)) + (PORT datac (330:330:330) (407:407:407)) + (PORT datad (855:855:855) (752:752:752)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_PRE) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT datab (511:511:511) (449:449:449)) + (PORT datad (521:521:521) (502:502:502)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_TRP) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|trp_end\~1) + (DELAY + (ABSOLUTE + (PORT datab (549:549:549) (463:463:463)) + (PORT datac (563:563:563) (535:535:535)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_END) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2473:2473:2473) (2188:2188:2188)) + (PORT datab (329:329:329) (386:386:386)) + (PORT datad (533:533:533) (533:533:533)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2472:2472:2472) (2187:2187:2187)) + (PORT datab (330:330:330) (387:387:387)) + (PORT datad (286:286:286) (344:344:344)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_ACTIVE) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT datab (546:546:546) (527:527:527)) + (PORT datad (469:469:469) (410:410:410)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_TRCD) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|trcd_end\~1) + (DELAY + (ABSOLUTE + (PORT datab (611:611:611) (568:568:568)) + (PORT datad (487:487:487) (420:420:420)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_READ) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (575:575:575)) + (PORT datab (339:339:339) (394:394:394)) + (PORT datad (282:282:282) (340:340:340)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|tread_end\~2) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (417:417:417)) + (PORT datab (355:355:355) (416:416:416)) + (PORT datac (297:297:297) (368:368:368)) + (PORT datad (298:298:298) (363:363:363)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|tread_end\~4) + (DELAY + (ABSOLUTE + (PORT dataa (500:500:500) (442:442:442)) + (PORT datab (294:294:294) (302:302:302)) + (PORT datac (306:306:306) (374:374:374)) + (PORT datad (307:307:307) (366:366:366)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (PORT datab (341:341:341) (397:397:397)) + (PORT datac (513:513:513) (497:497:497)) + (PORT datad (956:956:956) (879:879:879)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (800:800:800)) + (PORT datab (887:887:887) (758:758:758)) + (PORT datac (443:443:443) (380:380:380)) + (PORT datad (869:869:869) (763:763:763)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~3) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (841:841:841)) + (PORT datab (1195:1195:1195) (983:983:983)) + (PORT datac (251:251:251) (268:268:268)) + (PORT datad (793:793:793) (671:671:671)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (420:420:420)) + (PORT datab (357:357:357) (418:418:418)) + (PORT datac (303:303:303) (374:374:374)) + (PORT datad (302:302:302) (368:368:368)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|valid_wrreq\~1) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (282:282:282)) + (PORT datab (843:843:843) (721:721:721)) + (PORT datac (470:470:470) (412:412:412)) + (PORT datad (835:835:835) (728:728:728)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1693:1693:1693) (1643:1643:1643)) + (PORT ena (1599:1599:1599) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (347:347:347)) + (PORT datab (374:374:374) (442:442:442)) + (PORT datad (925:925:925) (837:837:837)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (299:299:299)) + (PORT datab (377:377:377) (445:445:445)) + (PORT datad (341:341:341) (404:404:404)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (383:383:383) (443:443:443)) + (PORT datad (244:244:244) (259:259:259)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (589:589:589) (577:577:577)) + (PORT datab (350:350:350) (408:408:408)) + (PORT datac (327:327:327) (403:403:403)) + (PORT datad (239:239:239) (253:253:253)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (560:560:560)) + (PORT datab (937:937:937) (877:877:877)) + (PORT datac (788:788:788) (671:671:671)) + (PORT datad (828:828:828) (738:738:738)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (602:602:602)) + (PORT datad (235:235:235) (246:246:246)) + (IOPATH dataa combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1693:1693:1693) (1643:1643:1643)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (646:646:646) (601:601:601)) + (PORT datad (236:236:236) (247:247:247)) + (IOPATH dataa combout (375:375:375) (392:392:392)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1693:1693:1693) (1643:1643:1643)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (605:605:605)) + (PORT datac (308:308:308) (375:375:375)) + (PORT datad (518:518:518) (505:505:505)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1693:1693:1693) (1643:1643:1643)) + (PORT ena (1599:1599:1599) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (443:443:443)) + (PORT datab (382:382:382) (443:443:443)) + (PORT datac (339:339:339) (409:409:409)) + (PORT datad (333:333:333) (404:404:404)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (PORT ena (1068:1068:1068) (1054:1054:1054)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (320:320:320) (375:375:375)) + (PORT datac (277:277:277) (340:340:340)) + (PORT datad (815:815:815) (752:752:752)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|parity9) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1693:1693:1693) (1643:1643:1643)) + (PORT ena (1599:1599:1599) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT datad (925:925:925) (837:837:837)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a0) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (PORT ena (1068:1068:1068) (1054:1054:1054)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (343:343:343)) + (PORT datab (375:375:375) (442:442:442)) + (PORT datac (538:538:538) (532:532:532)) + (PORT datad (922:922:922) (834:834:834)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (441:441:441)) + (PORT datab (286:286:286) (298:298:298)) + (PORT datad (553:553:553) (537:537:537)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (284:284:284) (301:301:301)) + (PORT datab (383:383:383) (444:444:444)) + (PORT datac (337:337:337) (406:406:406)) + (PORT datad (336:336:336) (406:406:406)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (442:442:442)) + (PORT datab (349:349:349) (407:407:407)) + (PORT datad (229:229:229) (237:237:237)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (767:767:767)) + (PORT datad (850:850:850) (799:799:799)) + (IOPATH dataa combout (375:375:375) (392:392:392)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1693:1693:1693) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1678:1678:1678)) + (PORT asdata (959:959:959) (944:944:944)) + (PORT clrn (1693:1693:1693) (1643:1643:1643)) + (PORT ena (1599:1599:1599) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT asdata (1281:1281:1281) (1198:1198:1198)) + (PORT clrn (1693:1693:1693) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT asdata (1977:1977:1977) (1802:1802:1802)) + (PORT clrn (1693:1693:1693) (1645:1645:1645)) + (PORT ena (1622:1622:1622) (1494:1494:1494)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1502:1502:1502) (1321:1321:1321)) + (PORT datab (349:349:349) (407:407:407)) + (PORT datad (298:298:298) (353:353:353)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1678:1678:1678)) + (PORT asdata (731:731:731) (796:796:796)) + (PORT clrn (1693:1693:1693) (1643:1643:1643)) + (PORT ena (1599:1599:1599) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT asdata (1299:1299:1299) (1213:1213:1213)) + (PORT clrn (1693:1693:1693) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8\~0) + (DELAY + (ABSOLUTE + (PORT datab (357:357:357) (417:417:417)) + (PORT datac (850:850:850) (791:791:791)) + (PORT datad (330:330:330) (388:388:388)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8\~1) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (769:769:769)) + (PORT datad (229:229:229) (236:236:236)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1693:1693:1693) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1678:1678:1678)) + (PORT asdata (1012:1012:1012) (982:982:982)) + (PORT clrn (1693:1693:1693) (1643:1643:1643)) + (PORT ena (1599:1599:1599) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT asdata (1268:1268:1268) (1188:1188:1188)) + (PORT clrn (1693:1693:1693) (1645:1645:1645)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1365:1365:1365) (1202:1202:1202)) + (PORT datab (1328:1328:1328) (1176:1176:1176)) + (PORT datad (794:794:794) (692:692:692)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (282:282:282)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (891:891:891) (786:786:786)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1195:1195:1195) (974:974:974)) + (PORT datab (327:327:327) (347:347:347)) + (PORT datac (315:315:315) (385:385:385)) + (PORT datad (792:792:792) (666:666:666)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT asdata (1367:1367:1367) (1269:1269:1269)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (PORT ena (1217:1217:1217) (1119:1119:1119)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1670:1670:1670)) + (PORT asdata (2068:2068:2068) (1878:1878:1878)) + (PORT clrn (1684:1684:1684) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (515:515:515) (496:496:496)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (PORT ena (1217:1217:1217) (1119:1119:1119)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1670:1670:1670)) + (PORT asdata (1673:1673:1673) (1571:1571:1571)) + (PORT clrn (1684:1684:1684) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1614:1614:1614) (1452:1452:1452)) + (PORT datab (837:837:837) (727:727:727)) + (PORT datad (1264:1264:1264) (1150:1150:1150)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (899:899:899) (841:841:841)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1693:1693:1693) (1643:1643:1643)) + (PORT ena (1599:1599:1599) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1670:1670:1670)) + (PORT asdata (1643:1643:1643) (1512:1512:1512)) + (PORT clrn (1684:1684:1684) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1678:1678:1678)) + (PORT asdata (2336:2336:2336) (2108:2108:2108)) + (PORT clrn (1693:1693:1693) (1643:1643:1643)) + (PORT ena (1599:1599:1599) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1670:1670:1670)) + (PORT asdata (1370:1370:1370) (1292:1292:1292)) + (PORT clrn (1684:1684:1684) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1581:1581:1581) (1433:1433:1433)) + (PORT datab (1882:1882:1882) (1640:1640:1640)) + (PORT datad (279:279:279) (334:334:334)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (282:282:282)) + (PORT datab (1649:1649:1649) (1419:1419:1419)) + (PORT datac (448:448:448) (385:385:385)) + (PORT datad (228:228:228) (236:236:236)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (2006:2006:2006) (1774:1774:1774)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (PORT ena (1613:1613:1613) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (548:548:548) (519:519:519)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (PORT ena (1217:1217:1217) (1119:1119:1119)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1670:1670:1670)) + (PORT asdata (1652:1652:1652) (1553:1553:1553)) + (PORT clrn (1684:1684:1684) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdempty_eq_comp_lsb\|data_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1292:1292:1292) (1163:1163:1163)) + (PORT datad (818:818:818) (729:729:729)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT asdata (1324:1324:1324) (1243:1243:1243)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (PORT ena (1217:1217:1217) (1119:1119:1119)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1670:1670:1670)) + (PORT asdata (2055:2055:2055) (1876:1876:1876)) + (PORT clrn (1684:1684:1684) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1306:1306:1306) (1169:1169:1169)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datad (1588:1588:1588) (1377:1377:1377)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT asdata (2039:2039:2039) (1867:1867:1867)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (PORT ena (1613:1613:1613) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1277:1277:1277) (1171:1171:1171)) + (PORT datab (1646:1646:1646) (1485:1485:1485)) + (PORT datad (279:279:279) (335:335:335)) + (IOPATH dataa combout (420:420:420) (450:450:450)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (679:679:679)) + (PORT datab (270:270:270) (278:278:278)) + (PORT datac (228:228:228) (243:243:243)) + (PORT datad (230:230:230) (237:237:237)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_en_dly) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1676:1676:1676)) + (PORT asdata (725:725:725) (787:787:787)) + (PORT clrn (5255:5255:5255) (5235:5235:5235)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|valid_wreq) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (400:400:400)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (PORT datab (945:945:945) (829:829:829)) + (IOPATH dataa combout (408:408:408) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1532:1532:1532) (1370:1370:1370)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Add2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (391:391:391)) + (PORT datab (344:344:344) (405:405:405)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5193:5193:5193)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Add2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (388:388:388)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Add2\~6) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT datab (346:346:346) (408:408:408)) + (PORT datac (226:226:226) (242:242:242)) + (PORT datad (247:247:247) (262:262:262)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5193:5193:5193)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (765:765:765)) + (PORT datab (325:325:325) (382:382:382)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (333:333:333) (393:393:393)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5415:5415:5415) (5448:5448:5448)) + (PORT sclr (1065:1065:1065) (1046:1046:1046)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5415:5415:5415) (5448:5448:5448)) + (PORT sclr (1065:1065:1065) (1046:1046:1046)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (326:326:326) (383:383:383)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5415:5415:5415) (5448:5448:5448)) + (PORT sclr (1065:1065:1065) (1046:1046:1046)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (392:392:392)) + (PORT datab (328:328:328) (385:385:385)) + (PORT datac (283:283:283) (348:348:348)) + (PORT datad (286:286:286) (345:345:345)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5415:5415:5415) (5448:5448:5448)) + (PORT sclr (1065:1065:1065) (1046:1046:1046)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (800:800:800)) + (PORT datab (621:621:621) (578:578:578)) + (PORT datac (525:525:525) (519:519:519)) + (PORT datad (864:864:864) (787:787:787)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (334:334:334) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5415:5415:5415) (5448:5448:5448)) + (PORT sclr (1065:1065:1065) (1046:1046:1046)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (495:495:495) (482:482:482)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5415:5415:5415) (5448:5448:5448)) + (PORT sclr (1065:1065:1065) (1046:1046:1046)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~3) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (458:458:458)) + (PORT datab (550:550:550) (464:464:464)) + (PORT datac (226:226:226) (241:241:241)) + (PORT datad (509:509:509) (501:501:501)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5415:5415:5415) (5448:5448:5448)) + (PORT sclr (1065:1065:1065) (1046:1046:1046)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5415:5415:5415) (5448:5448:5448)) + (PORT sclr (1065:1065:1065) (1046:1046:1046)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5415:5415:5415) (5448:5448:5448)) + (PORT sclr (1065:1065:1065) (1046:1046:1046)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (801:801:801)) + (PORT datab (621:621:621) (579:579:579)) + (PORT datac (526:526:526) (520:520:520)) + (PORT datad (865:865:865) (788:788:788)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (491:491:491) (437:437:437)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (502:502:502) (434:434:434)) + (PORT datad (508:508:508) (500:500:500)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5193:5193:5193)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT datab (287:287:287) (300:300:300)) + (PORT datac (303:303:303) (375:375:375)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5193:5193:5193)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (394:394:394)) + (PORT datab (329:329:329) (386:386:386)) + (PORT datac (283:283:283) (349:349:349)) + (PORT datad (287:287:287) (347:347:347)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|always5\~1) + (DELAY + (ABSOLUTE + (PORT datac (303:303:303) (374:374:374)) + (PORT datad (248:248:248) (263:263:263)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|rd_en) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1677:1677:1677)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5210:5210:5210) (5193:5193:5193)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty\~1) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (827:827:827)) + (PORT datab (953:953:953) (866:866:866)) + (PORT datac (913:913:913) (848:848:848)) + (PORT datad (881:881:881) (831:831:831)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty\~0) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (406:406:406)) + (PORT datac (514:514:514) (503:503:503)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty\~2) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (742:742:742)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~4) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (656:656:656)) + (PORT datad (880:880:880) (830:830:830)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (538:538:538)) + (PORT datab (559:559:559) (547:547:547)) + (PORT datac (292:292:292) (364:364:364)) + (PORT datad (879:879:879) (830:830:830)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1662:1662:1662) (1680:1680:1680)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (1532:1532:1532) (1370:1370:1370)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1678:1678:1678)) + (PORT asdata (727:727:727) (789:789:789)) + (PORT clrn (1693:1693:1693) (1643:1643:1643)) + (PORT ena (1599:1599:1599) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1678:1678:1678)) + (PORT asdata (955:955:955) (936:936:936)) + (PORT clrn (1693:1693:1693) (1643:1643:1643)) + (PORT ena (1599:1599:1599) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (561:561:561)) + (PORT datab (356:356:356) (417:417:417)) + (PORT datac (299:299:299) (362:362:362)) + (PORT datad (538:538:538) (524:524:524)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (915:915:915) (866:866:866)) + (PORT datab (995:995:995) (912:912:912)) + (PORT datac (941:941:941) (864:864:864)) + (PORT datad (890:890:890) (767:767:767)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (1246:1246:1246) (1145:1145:1145)) + (PORT datad (242:242:242) (256:256:256)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (1282:1282:1282) (1163:1163:1163)) + (PORT datac (1246:1246:1246) (1146:1146:1146)) + (PORT datad (242:242:242) (256:256:256)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT asdata (1339:1339:1339) (1248:1248:1248)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (PORT ena (1613:1613:1613) (1466:1466:1466)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1233:1233:1233) (1118:1118:1118)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1216:1216:1216) (1117:1117:1117)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1561:1561:1561) (1361:1361:1361)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (PORT ena (1981:1981:1981) (1791:1791:1791)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT asdata (732:732:732) (799:799:799)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT asdata (1734:1734:1734) (1585:1585:1585)) + (PORT clrn (1693:1693:1693) (1645:1645:1645)) + (PORT ena (1622:1622:1622) (1494:1494:1494)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT asdata (1330:1330:1330) (1254:1254:1254)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT asdata (1960:1960:1960) (1748:1748:1748)) + (PORT clrn (1693:1693:1693) (1645:1645:1645)) + (PORT ena (1622:1622:1622) (1494:1494:1494)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (864:864:864) (804:804:804)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (872:872:872) (800:800:800)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (518:518:518)) + (PORT datab (324:324:324) (381:381:381)) + (PORT datac (292:292:292) (361:361:361)) + (PORT datad (513:513:513) (501:501:501)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (381:381:381)) + (PORT datab (327:327:327) (384:384:384)) + (PORT datac (290:290:290) (358:358:358)) + (PORT datad (243:243:243) (257:257:257)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (395:395:395)) + (PORT datab (320:320:320) (374:374:374)) + (PORT datac (292:292:292) (361:361:361)) + (PORT datad (828:828:828) (719:719:719)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1673:1673:1673)) + (PORT asdata (1714:1714:1714) (1583:1583:1583)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datac (279:279:279) (342:342:342)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1655:1655:1655) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (787:787:787)) + (PORT datab (834:834:834) (734:734:734)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (535:535:535)) + (PORT datab (872:872:872) (793:793:793)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (510:510:510)) + (PORT datab (913:913:913) (816:816:816)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (282:282:282)) + (PORT datab (276:276:276) (286:286:286)) + (PORT datac (234:234:234) (252:252:252)) + (PORT datad (235:235:235) (246:246:246)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datab (329:329:329) (387:387:387)) + (PORT datac (294:294:294) (363:363:363)) + (PORT datad (517:517:517) (505:505:505)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1693:1693:1693) (1643:1643:1643)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT datab (329:329:329) (387:387:387)) + (PORT datac (291:291:291) (359:359:359)) + (PORT datad (244:244:244) (258:258:258)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1228:1228:1228) (1076:1076:1076)) + (PORT datab (893:893:893) (819:819:819)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (806:806:806)) + (PORT datab (960:960:960) (850:850:850)) + (IOPATH dataa combout (414:414:414) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1158:1158:1158) (1023:1023:1023)) + (PORT datab (901:901:901) (829:829:829)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (919:919:919) (848:848:848)) + (PORT datab (942:942:942) (838:838:838)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (423:423:423) (453:453:453)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (768:768:768)) + (PORT datab (837:837:837) (717:717:717)) + (PORT datac (904:904:904) (781:781:781)) + (PORT datad (835:835:835) (719:719:719)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (292:292:292)) + (PORT datab (964:964:964) (881:881:881)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_en) + (DELAY + (ABSOLUTE + (PORT clk (1659:1659:1659) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (5255:5255:5255) (5235:5235:5235)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT datab (318:318:318) (372:372:372)) + (PORT datac (1276:1276:1276) (1143:1143:1143)) + (PORT datad (1255:1255:1255) (1125:1125:1125)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (419:419:419)) + (PORT datab (328:328:328) (348:348:348)) + (PORT datac (787:787:787) (706:706:706)) + (PORT datad (527:527:527) (514:514:514)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (229:229:229) (236:236:236)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (321:321:321)) + (PORT datad (322:322:322) (388:388:388)) + (IOPATH dataa combout (375:375:375) (392:392:392)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (543:543:543)) + (PORT datab (572:572:572) (552:552:552)) + (PORT datac (251:251:251) (277:277:277)) + (PORT datad (323:323:323) (388:388:388)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6\~0) + (DELAY + (ABSOLUTE + (PORT datab (307:307:307) (321:321:321)) + (PORT datad (524:524:524) (514:514:514)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (947:947:947) (862:862:862)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1693:1693:1693) (1645:1645:1645)) + (PORT ena (1622:1622:1622) (1494:1494:1494)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT asdata (1331:1331:1331) (1257:1257:1257)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datac (296:296:296) (365:365:365)) + (PORT datad (240:240:240) (253:253:253)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1675:1675:1675)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1689:1689:1689) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (227:227:227) (242:242:242)) + (PORT datad (228:228:228) (236:236:236)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (564:564:564)) + (PORT datad (312:312:312) (375:375:375)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1661:1661:1661) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1693:1693:1693) (1643:1643:1643)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (830:830:830)) + (PORT datad (861:861:861) (793:793:793)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (280:280:280)) + (PORT datab (1908:1908:1908) (1567:1567:1567)) + (PORT datac (1818:1818:1818) (1517:1517:1517)) + (PORT datad (252:252:252) (261:261:261)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1818:1818:1818) (1528:1528:1528)) + (PORT datab (289:289:289) (297:297:297)) + (PORT datac (250:250:250) (266:266:266)) + (PORT datad (225:225:225) (233:233:233)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1578:1578:1578) (1419:1419:1419)) + (PORT datab (888:888:888) (829:829:829)) + (PORT datac (1141:1141:1141) (1016:1016:1016)) + (PORT datad (307:307:307) (366:366:366)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (572:572:572)) + (PORT datad (310:310:310) (369:369:369)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (314:314:314)) + (PORT datab (1189:1189:1189) (1054:1054:1054)) + (PORT datac (1498:1498:1498) (1310:1310:1310)) + (PORT datad (230:230:230) (238:238:238)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.READ) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~7) + (DELAY + (ABSOLUTE + (PORT datab (624:624:624) (587:587:587)) + (PORT datac (501:501:501) (460:460:460)) + (PORT datad (529:529:529) (520:520:520)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (497:497:497)) + (PORT datab (362:362:362) (424:424:424)) + (PORT datad (250:250:250) (258:258:258)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_DATA) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|twrite_end\~0) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (423:423:423)) + (PORT datab (349:349:349) (412:412:412)) + (PORT datac (304:304:304) (376:376:376)) + (PORT datad (303:303:303) (369:369:369)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|twrite_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (546:546:546) (499:499:499)) + (PORT datab (318:318:318) (334:334:334)) + (PORT datac (349:349:349) (431:431:431)) + (PORT datad (795:795:795) (644:644:644)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_PRE) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (300:300:300) (316:316:316)) + (PORT datad (526:526:526) (516:516:516)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_TRP) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|trp_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (501:501:501)) + (PORT datab (336:336:336) (396:396:396)) + (PORT datac (276:276:276) (301:301:301)) + (PORT datad (490:490:490) (422:422:422)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_END) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1262:1262:1262) (1132:1132:1132)) + (PORT datab (1549:1549:1549) (1343:1343:1343)) + (PORT datad (251:251:251) (269:269:269)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.WRITE) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (577:577:577)) + (PORT datab (346:346:346) (404:404:404)) + (PORT datac (1214:1214:1214) (1090:1090:1090)) + (PORT datad (302:302:302) (358:358:358)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (809:809:809) (704:704:704)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (226:226:226) (241:241:241)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.ARBIT) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT datab (1110:1110:1110) (1069:1069:1069)) + (PORT datac (308:308:308) (376:376:376)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1234:1234:1234) (1106:1106:1106)) + (PORT datab (363:363:363) (432:432:432)) + (PORT datad (565:565:565) (548:548:548)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\~4) + (DELAY + (ABSOLUTE + (PORT datad (574:574:574) (547:547:547)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\~2) + (DELAY + (ABSOLUTE + (PORT dataa (643:643:643) (598:598:598)) + (PORT datad (293:293:293) (355:355:355)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (PORT ena (1018:1018:1018) (991:991:991)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\~15) + (DELAY + (ABSOLUTE + (PORT datac (284:284:284) (350:350:350)) + (PORT datad (290:290:290) (351:351:351)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (309:309:309)) + (PORT datad (549:549:549) (522:522:522)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_TRP) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\~1) + (DELAY + (ABSOLUTE + (PORT datab (278:278:278) (287:287:287)) + (PORT datad (311:311:311) (380:380:380)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT datab (350:350:350) (416:416:416)) + (PORT datac (290:290:290) (358:358:358)) + (PORT datad (518:518:518) (514:514:514)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (640:640:640) (596:596:596)) + (PORT datab (325:325:325) (382:382:382)) + (PORT datac (245:245:245) (269:269:269)) + (PORT datad (300:300:300) (355:355:355)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (300:300:300) (323:323:323)) + (PORT datab (341:341:341) (404:404:404)) + (PORT datad (236:236:236) (247:247:247)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\~0) + (DELAY + (ABSOLUTE + (PORT dataa (565:565:565) (562:562:562)) + (PORT datab (274:274:274) (284:284:284)) + (PORT datad (310:310:310) (379:379:379)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (560:560:560) (557:557:557)) + (PORT datab (351:351:351) (417:417:417)) + (PORT datac (292:292:292) (360:360:360)) + (PORT datad (301:301:301) (367:367:367)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (306:306:306) (373:373:373)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_TRF) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\~2) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (322:322:322)) + (PORT datab (344:344:344) (407:407:407)) + (PORT datad (235:235:235) (246:246:246)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|trc_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (554:554:554)) + (PORT datab (351:351:351) (417:417:417)) + (PORT datac (293:293:293) (361:361:361)) + (PORT datad (301:301:301) (366:366:366)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (287:287:287) (306:306:306)) + (PORT datab (272:272:272) (280:280:280)) + (PORT datac (287:287:287) (353:353:353)) + (PORT datad (258:258:258) (280:280:280)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AUTO_REF) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (641:641:641) (597:597:597)) + (PORT datac (308:308:308) (375:375:375)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (PORT ena (1018:1018:1018) (991:991:991)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\~17) + (DELAY + (ABSOLUTE + (PORT dataa (300:300:300) (323:323:323)) + (PORT datab (337:337:337) (397:397:397)) + (PORT datac (286:286:286) (352:352:352)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_END) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|aref_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (1110:1110:1110) (1069:1069:1069)) + (PORT datac (308:308:308) (376:376:376)) + (PORT datad (562:562:562) (545:545:545)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.AREF) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (PORT ena (973:973:973) (947:947:947)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\~3) + (DELAY + (ABSOLUTE + (PORT datad (242:242:242) (256:256:256)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\~2) + (DELAY + (ABSOLUTE + (PORT datab (389:389:389) (460:460:460)) + (PORT datad (247:247:247) (261:261:261)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT datab (354:354:354) (414:414:414)) + (PORT datac (339:339:339) (417:417:417)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1217:1217:1217) (1074:1074:1074)) + (PORT datab (385:385:385) (457:457:457)) + (PORT datad (245:245:245) (260:260:260)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_TRP) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (395:395:395)) + (PORT datab (385:385:385) (457:457:457)) + (PORT datac (285:285:285) (351:351:351)) + (PORT datad (243:243:243) (258:258:258)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (854:854:854) (793:793:793)) + (PORT datad (306:306:306) (365:365:365)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (808:808:808)) + (PORT datab (900:900:900) (801:801:801)) + (PORT datac (800:800:800) (725:725:725)) + (PORT datad (855:855:855) (786:786:786)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\~0) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (701:701:701)) + (PORT datab (269:269:269) (275:275:275)) + (PORT datac (227:227:227) (242:242:242)) + (PORT datad (235:235:235) (246:246:246)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (393:393:393)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (394:394:394)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~20) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~22) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (391:391:391)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~24) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~28) + (DELAY + (ABSOLUTE + (PORT datad (497:497:497) (479:479:479)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1684:1684:1684)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1696:1696:1696) (1649:1649:1649)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (390:390:390)) + (PORT datab (534:534:534) (515:515:515)) + (PORT datac (283:283:283) (350:350:350)) + (PORT datad (284:284:284) (342:342:342)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (847:847:847) (770:770:770)) + (PORT datab (884:884:884) (796:796:796)) + (PORT datac (842:842:842) (754:754:754)) + (PORT datad (864:864:864) (767:767:767)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (832:832:832) (763:763:763)) + (PORT datac (740:740:740) (629:629:629)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (805:805:805)) + (PORT datab (896:896:896) (797:797:797)) + (PORT datac (795:795:795) (720:720:720)) + (PORT datad (856:856:856) (787:787:787)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (857:857:857) (797:797:797)) + (PORT datab (277:277:277) (287:287:287)) + (PORT datac (485:485:485) (408:408:408)) + (PORT datad (307:307:307) (366:366:366)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_IDLE\~0) + (DELAY + (ABSOLUTE + (PORT datad (236:236:236) (246:246:246)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (282:282:282)) + (PORT datab (364:364:364) (419:419:419)) + (PORT datac (228:228:228) (243:243:243)) + (PORT datad (1246:1246:1246) (1093:1093:1093)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\~4) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (547:547:547)) + (PORT datab (284:284:284) (296:296:296)) + (PORT datad (316:316:316) (378:378:378)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT datab (386:386:386) (457:457:457)) + (PORT datad (312:312:312) (374:374:374)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_END\~0) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (395:395:395)) + (PORT datab (386:386:386) (456:456:456)) + (PORT datad (486:486:486) (434:434:434)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_END) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (407:407:407)) + (PORT datab (362:362:362) (432:432:432)) + (PORT datac (1187:1187:1187) (1065:1065:1065)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_PCHA) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (614:614:614) (568:568:568)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (621:621:621) (572:572:572)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (533:533:533)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (549:549:549) (524:524:524)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~4) + (DELAY + (ABSOLUTE + (PORT datac (488:488:488) (414:414:414)) + (PORT datad (293:293:293) (321:321:321)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (1528:1528:1528) (1349:1349:1349)) + (PORT datad (300:300:300) (329:329:329)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (PORT ena (968:968:968) (936:936:936)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (407:407:407)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (498:498:498)) + (PORT datab (1315:1315:1315) (1208:1208:1208)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (406:406:406)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[6\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (497:497:497)) + (PORT datab (1315:1315:1315) (1209:1209:1209)) + (PORT datad (228:228:228) (236:236:236)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (412:412:412)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[7\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (596:596:596) (503:503:503)) + (PORT datab (1312:1312:1312) (1206:1206:1206)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~0) + (DELAY + (ABSOLUTE + (PORT datac (489:489:489) (416:416:416)) + (PORT datad (297:297:297) (325:325:325)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (PORT ena (968:968:968) (936:936:936)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~7) + (DELAY + (ABSOLUTE + (PORT datac (490:490:490) (418:418:418)) + (PORT datad (300:300:300) (328:328:328)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (PORT ena (968:968:968) (936:936:936)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~8) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (361:361:361)) + (PORT datad (443:443:443) (383:383:383)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (PORT ena (968:968:968) (936:936:936)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (413:413:413)) + (PORT datab (348:348:348) (406:406:406)) + (PORT datac (296:296:296) (360:360:360)) + (PORT datad (299:299:299) (355:355:355)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (414:414:414)) + (PORT datab (612:612:612) (570:570:570)) + (PORT datac (228:228:228) (243:243:243)) + (PORT datad (549:549:549) (522:522:522)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|LessThan0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (548:548:548)) + (PORT datab (346:346:346) (404:404:404)) + (PORT datac (561:561:561) (533:533:533)) + (PORT datad (225:225:225) (232:232:232)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (544:544:544) (525:525:525)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[8\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1573:1573:1573) (1389:1389:1389)) + (PORT datab (334:334:334) (358:358:358)) + (PORT datad (477:477:477) (403:403:403)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (311:311:311) (371:371:371)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[9\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (590:590:590) (497:497:497)) + (PORT datab (1316:1316:1316) (1209:1209:1209)) + (PORT datad (230:230:230) (237:237:237)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1679:1679:1679)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1692:1692:1692) (1644:1644:1644)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (568:568:568)) + (PORT datab (351:351:351) (409:409:409)) + (PORT datac (305:305:305) (373:373:373)) + (PORT datad (548:548:548) (519:519:519)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (267:267:267) (274:274:274)) + (PORT datac (309:309:309) (376:376:376)) + (PORT datad (311:311:311) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1152:1152:1152) (971:971:971)) + (PORT datab (344:344:344) (399:399:399)) + (PORT datad (1094:1094:1094) (907:907:907)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_req) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datac (845:845:845) (795:795:795)) + (PORT datad (307:307:307) (366:366:366)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|wr_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1133:1133:1133)) + (PORT datab (1549:1549:1549) (1343:1343:1343)) + (PORT datad (251:251:251) (269:269:269)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|wr_en) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1259:1259:1259) (1128:1128:1128)) + (PORT datab (333:333:333) (391:391:391)) + (PORT datad (2432:2432:2432) (2146:2146:2146)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector4\~1) + (DELAY + (ABSOLUTE + (PORT datab (616:616:616) (575:575:575)) + (PORT datac (866:866:866) (814:814:814)) + (PORT datad (509:509:509) (494:494:494)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (320:320:320)) + (PORT datab (337:337:337) (397:397:397)) + (PORT datac (227:227:227) (242:242:242)) + (PORT datad (506:506:506) (493:493:493)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (954:954:954) (845:845:845)) + (PORT datab (497:497:497) (438:438:438)) + (PORT datac (225:225:225) (240:240:240)) + (PORT datad (430:430:430) (361:361:361)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (336:336:336) (398:398:398)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (402:402:402)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[8\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[9\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (398:398:398)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (PORT sclr (844:844:844) (900:900:900)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~5) + (DELAY + (ABSOLUTE + (PORT datab (621:621:621) (585:585:585)) + (PORT datad (527:527:527) (519:519:519)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (786:786:786)) + (PORT datad (803:803:803) (700:700:700)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_TRCD) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|trcd_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (501:501:501)) + (PORT datab (319:319:319) (335:335:335)) + (PORT datac (549:549:549) (527:527:527)) + (PORT datad (490:490:490) (422:422:422)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_WRITE) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_ack\~2) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (420:420:420)) + (PORT datab (345:345:345) (408:408:408)) + (PORT datac (301:301:301) (373:373:373)) + (PORT datad (301:301:301) (366:366:366)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_ack\~3) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (501:501:501)) + (PORT datab (315:315:315) (331:331:331)) + (PORT datac (342:342:342) (423:423:423)) + (PORT datad (476:476:476) (402:402:402)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1309:1309:1309) (1165:1165:1165)) + (PORT datab (340:340:340) (395:395:395)) + (PORT datac (297:297:297) (360:360:360)) + (PORT datad (1229:1229:1229) (1103:1103:1103)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1108:1108:1108)) + (PORT datab (1539:1539:1539) (1331:1331:1331)) + (PORT datac (1131:1131:1131) (919:919:919)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (457:457:457)) + (PORT datab (282:282:282) (294:294:294)) + (PORT datad (1235:1235:1235) (1113:1113:1113)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1335:1335:1335) (1177:1177:1177)) + (PORT datab (957:957:957) (858:858:858)) + (PORT datac (1185:1185:1185) (1060:1060:1060)) + (PORT datad (883:883:883) (800:800:800)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (PORT ena (1667:1667:1667) (1526:1526:1526)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~11) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (846:846:846)) + (PORT datab (1217:1217:1217) (1080:1080:1080)) + (PORT datac (1223:1223:1223) (1091:1091:1091)) + (IOPATH dataa combout (435:435:435) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (PORT ena (1033:1033:1033) (1005:1005:1005)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~10) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (385:385:385)) + (PORT datac (276:276:276) (339:339:339)) + (PORT datad (877:877:877) (799:799:799)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|parity6) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (PORT ena (1667:1667:1667) (1526:1526:1526)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (798:798:798)) + (PORT datab (378:378:378) (438:438:438)) + (PORT datac (317:317:317) (388:388:388)) + (PORT datad (937:937:937) (824:824:824)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (227:227:227) (235:235:235)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (282:282:282)) + (PORT datab (348:348:348) (406:406:406)) + (PORT datac (1152:1152:1152) (1032:1032:1032)) + (PORT datad (936:936:936) (823:823:823)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1336:1336:1336) (1179:1179:1179)) + (PORT datab (293:293:293) (308:308:308)) + (PORT datad (882:882:882) (799:799:799)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1339:1339:1339) (1183:1183:1183)) + (PORT datab (954:954:954) (854:854:854)) + (PORT datac (251:251:251) (275:275:275)) + (PORT datad (878:878:878) (795:795:795)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8\~0) + (DELAY + (ABSOLUTE + (PORT datad (226:226:226) (233:233:233)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10\~0) + (DELAY + (ABSOLUTE + (PORT datab (351:351:351) (409:409:409)) + (PORT datad (233:233:233) (243:243:243)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1667:1667:1667)) + (PORT asdata (1593:1593:1593) (1471:1471:1471)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (PORT ena (1033:1033:1033) (1005:1005:1005)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (885:885:885)) + (PORT datab (884:884:884) (818:818:818)) + (PORT datad (528:528:528) (511:511:511)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1118:1118:1118) (923:923:923)) + (PORT datab (321:321:321) (340:340:340)) + (PORT datac (307:307:307) (381:381:381)) + (PORT datad (810:810:810) (691:691:691)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (270:270:270) (282:282:282)) + (PORT datab (331:331:331) (350:350:350)) + (PORT datac (446:446:446) (384:384:384)) + (PORT datad (934:934:934) (849:849:849)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1663:1663:1663)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1628:1628:1628)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (318:318:318) (377:377:377)) + (PORT datad (278:278:278) (333:333:333)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2044:2044:2044) (2012:2012:2012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2044:2044:2044) (2012:2012:2012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rx\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (778:778:778) (803:803:803)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg1\~0) + (DELAY + (ABSOLUTE + (PORT datad (3671:3671:3671) (3716:3716:3716)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (278:278:278) (333:333:333)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (285:285:285) (343:343:343)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg3) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1670:1670:1670)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1635:1635:1635)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (877:877:877) (798:798:798)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (353:353:353) (419:419:419)) + (PORT datad (250:250:250) (268:268:268)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1672:1672:1672)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1637:1637:1637)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always8\~0) + (DELAY + (ABSOLUTE + (PORT datab (293:293:293) (308:308:308)) + (PORT datac (310:310:310) (385:385:385)) + (PORT datad (303:303:303) (372:372:372)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1933:1933:1933) (1711:1711:1711)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT asdata (710:710:710) (775:775:775)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1933:1933:1933) (1711:1711:1711)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (285:285:285) (344:344:344)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1933:1933:1933) (1711:1711:1711)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (287:287:287) (345:345:345)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1933:1933:1933) (1711:1711:1711)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (284:284:284) (342:342:342)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1933:1933:1933) (1711:1711:1711)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (288:288:288) (347:347:347)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1933:1933:1933) (1711:1711:1711)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (288:288:288) (347:347:347)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1933:1933:1933) (1711:1711:1711)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (287:287:287) (345:345:345)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1933:1933:1933) (1711:1711:1711)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (279:279:279) (334:334:334)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1918:1918:1918) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|ram_address_a\[9\]) + (DELAY + (ABSOLUTE + (PORT datad (307:307:307) (366:366:366)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (1242:1242:1242) (1115:1115:1115)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datab (1216:1216:1216) (1078:1078:1078)) + (PORT datac (866:866:866) (805:805:805)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (284:284:284) (342:342:342)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1918:1918:1918) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (286:286:286) (345:345:345)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1918:1918:1918) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (289:289:289) (348:348:348)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1918:1918:1918) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (286:286:286) (345:345:345)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1918:1918:1918) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (285:285:285) (343:343:343)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1918:1918:1918) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (286:286:286) (345:345:345)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1918:1918:1918) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT asdata (710:710:710) (775:775:775)) + (PORT clrn (1681:1681:1681) (1633:1633:1633)) + (PORT ena (1918:1918:1918) (1761:1761:1761)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (944:944:944) (885:885:885)) + (PORT d[1] (1009:1009:1009) (935:935:935)) + (PORT d[2] (957:957:957) (881:881:881)) + (PORT d[3] (940:940:940) (877:877:877)) + (PORT d[4] (968:968:968) (901:901:901)) + (PORT d[5] (969:969:969) (904:904:904)) + (PORT d[6] (957:957:957) (881:881:881)) + (PORT d[7] (935:935:935) (879:879:879)) + (PORT d[8] (587:587:587) (540:540:540)) + (PORT clk (2012:2012:2012) (2055:2055:2055)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1304:1304:1304) (1188:1188:1188)) + (PORT d[1] (1508:1508:1508) (1410:1410:1410)) + (PORT d[2] (1342:1342:1342) (1240:1240:1240)) + (PORT d[3] (1698:1698:1698) (1541:1541:1541)) + (PORT d[4] (1287:1287:1287) (1184:1184:1184)) + (PORT d[5] (1361:1361:1361) (1239:1239:1239)) + (PORT d[6] (1658:1658:1658) (1504:1504:1504)) + (PORT d[7] (1282:1282:1282) (1162:1162:1162)) + (PORT d[8] (1328:1328:1328) (1229:1229:1229)) + (PORT d[9] (1186:1186:1186) (1012:1012:1012)) + (PORT clk (2009:2009:2009) (2051:2051:2051)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2346:2346:2346) (2035:2035:2035)) + (PORT clk (2009:2009:2009) (2051:2051:2051)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2012:2012:2012) (2055:2055:2055)) + (PORT d[0] (2968:2968:2968) (2667:2667:2667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2013:2013:2013) (2056:2056:2056)) + (IOPATH (posedge clk) pulse (0:0:0) (2490:2490:2490)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2013:2013:2013) (2056:2056:2056)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2013:2013:2013) (2056:2056:2056)) + (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2013:2013:2013) (2056:2056:2056)) + (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1226:1226:1226) (1084:1084:1084)) + (PORT d[1] (1475:1475:1475) (1381:1381:1381)) + (PORT d[2] (1682:1682:1682) (1520:1520:1520)) + (PORT d[3] (1323:1323:1323) (1222:1222:1222)) + (PORT d[4] (1647:1647:1647) (1485:1485:1485)) + (PORT d[5] (1038:1038:1038) (976:976:976)) + (PORT d[6] (1269:1269:1269) (1160:1160:1160)) + (PORT d[7] (1272:1272:1272) (1153:1153:1153)) + (PORT d[8] (1310:1310:1310) (1218:1218:1218)) + (PORT d[9] (1190:1190:1190) (1006:1006:1006)) + (PORT clk (1965:1965:1965) (1963:1963:1963)) + (PORT aclr (2001:2001:2001) (2007:2007:2007)) + (PORT stall (1449:1449:1449) (1645:1645:1645)) + (IOPATH (posedge aclr) q (356:356:356) (356:356:356)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + (HOLD stall (posedge clk) (230:230:230)) + (HOLD aclr (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1965:1965:1965) (1963:1963:1963)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1966:1966:1966) (1964:1964:1964)) + (IOPATH (posedge clk) pulse (0:0:0) (2891:2891:2891)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1966:1966:1966) (1964:1964:1964)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1966:1966:1966) (1964:1964:1964)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1956:1956:1956) (1956:1956:1956)) + (PORT ena (2005:2005:2005) (1830:1830:1830)) + (PORT aclr (1954:1954:1954) (2017:2017:2017)) + (IOPATH (posedge clk) q (353:353:353) (353:353:353)) + (IOPATH (posedge aclr) q (393:393:393) (393:393:393)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (56:56:56)) + (SETUP ena (posedge clk) (56:56:56)) + (SETUP aclr (posedge clk) (56:56:56)) + (HOLD d (posedge clk) (190:190:190)) + (HOLD ena (posedge clk) (190:190:190)) + (HOLD aclr (posedge clk) (190:190:190)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_ack) + (DELAY + (ABSOLUTE + (PORT datac (1133:1133:1133) (920:920:920)) + (PORT datad (1498:1498:1498) (1292:1292:1292)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_sdram_en) + (DELAY + (ABSOLUTE + (PORT clk (1643:1643:1643) (1662:1662:1662)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1675:1675:1675) (1627:1627:1627)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1074:1074:1074) (1001:1001:1001)) + (PORT d[1] (1074:1074:1074) (1001:1001:1001)) + (PORT d[2] (1074:1074:1074) (1001:1001:1001)) + (PORT d[3] (1074:1074:1074) (1001:1001:1001)) + (PORT d[4] (1062:1062:1062) (986:986:986)) + (PORT d[5] (1062:1062:1062) (986:986:986)) + (PORT d[6] (1062:1062:1062) (986:986:986)) + (PORT clk (2006:2006:2006) (2049:2049:2049)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1820:1820:1820) (1668:1668:1668)) + (PORT d[1] (988:988:988) (928:928:928)) + (PORT d[2] (2253:2253:2253) (2067:2067:2067)) + (PORT d[3] (1324:1324:1324) (1212:1212:1212)) + (PORT d[4] (975:975:975) (925:925:925)) + (PORT d[5] (1126:1126:1126) (998:998:998)) + (PORT d[6] (1641:1641:1641) (1485:1485:1485)) + (PORT d[7] (1980:1980:1980) (1714:1714:1714)) + (PORT d[8] (1661:1661:1661) (1516:1516:1516)) + (PORT d[9] (845:845:845) (706:706:706)) + (PORT clk (2003:2003:2003) (2045:2045:2045)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2661:2661:2661) (2314:2314:2314)) + (PORT clk (2003:2003:2003) (2045:2045:2045)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2006:2006:2006) (2049:2049:2049)) + (PORT d[0] (3283:3283:3283) (2946:2946:2946)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2007:2007:2007) (2050:2050:2050)) + (IOPATH (posedge clk) pulse (0:0:0) (2490:2490:2490)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2007:2007:2007) (2050:2050:2050)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2007:2007:2007) (2050:2050:2050)) + (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2007:2007:2007) (2050:2050:2050)) + (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (949:949:949) (838:838:838)) + (PORT d[1] (1476:1476:1476) (1378:1378:1378)) + (PORT d[2] (1676:1676:1676) (1514:1514:1514)) + (PORT d[3] (1057:1057:1057) (990:990:990)) + (PORT d[4] (962:962:962) (917:917:917)) + (PORT d[5] (977:977:977) (923:923:923)) + (PORT d[6] (971:971:971) (906:906:906)) + (PORT d[7] (1302:1302:1302) (1191:1191:1191)) + (PORT d[8] (1660:1660:1660) (1510:1510:1510)) + (PORT d[9] (1887:1887:1887) (1603:1603:1603)) + (PORT clk (1959:1959:1959) (1957:1957:1957)) + (PORT aclr (1995:1995:1995) (2001:2001:2001)) + (PORT stall (1723:1723:1723) (1961:1961:1961)) + (IOPATH (posedge aclr) q (356:356:356) (356:356:356)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + (HOLD stall (posedge clk) (230:230:230)) + (HOLD aclr (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1959:1959:1959) (1957:1957:1957)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1960:1960:1960) (1958:1958:1958)) + (IOPATH (posedge clk) pulse (0:0:0) (2891:2891:2891)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1960:1960:1960) (1958:1958:1958)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1960:1960:1960) (1958:1958:1958)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1950:1950:1950) (1950:1950:1950)) + (PORT ena (1975:1975:1975) (1792:1792:1792)) + (PORT aclr (1948:1948:1948) (2011:2011:2011)) + (IOPATH (posedge clk) q (353:353:353) (353:353:353)) + (IOPATH (posedge aclr) q (393:393:393) (393:393:393)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (56:56:56)) + (SETUP ena (posedge clk) (56:56:56)) + (SETUP aclr (posedge clk) (56:56:56)) + (HOLD d (posedge clk) (190:190:190)) + (HOLD ena (posedge clk) (190:190:190)) + (HOLD aclr (posedge clk) (190:190:190)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sys_clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (175:175:175) (172:172:172)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (867:867:867) (793:793:793)) + (PORT datab (325:325:325) (382:382:382)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1668:1668:1668) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4535:4535:4535) (4419:4419:4419)) + (PORT sclr (1417:1417:1417) (1340:1340:1340)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (329:329:329) (392:392:392)) + (PORT datab (326:326:326) (383:383:383)) + (PORT datac (282:282:282) (348:348:348)) + (PORT datad (286:286:286) (344:344:344)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1668:1668:1668) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4535:4535:4535) (4419:4419:4419)) + (PORT sclr (1417:1417:1417) (1340:1340:1340)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (847:847:847)) + (PORT datab (938:938:938) (838:838:838)) + (PORT datac (818:818:818) (689:689:689)) + (PORT datad (927:927:927) (834:834:834)) + (IOPATH dataa combout (392:392:392) (419:419:419)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (398:398:398)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1668:1668:1668) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4535:4535:4535) (4419:4419:4419)) + (PORT sclr (1417:1417:1417) (1340:1340:1340)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (407:407:407)) + (PORT datab (334:334:334) (394:394:394)) + (PORT datac (293:293:293) (362:362:362)) + (PORT datad (295:295:295) (358:358:358)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|tx_flag) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1677:1677:1677)) + (PORT asdata (976:976:976) (950:950:950)) + (PORT clrn (5210:5210:5210) (5193:5193:5193)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (843:843:843)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datac combout (415:415:415) (429:429:429)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (388:388:388) (477:477:477)) + (PORT datab (285:285:285) (298:298:298)) + (PORT datad (274:274:274) (292:292:292)) + (IOPATH dataa combout (435:435:435) (419:419:419)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1667:1667:1667) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4540:4540:4540) (4423:4423:4423)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (757:757:757) (626:626:626)) + (PORT datab (287:287:287) (300:300:300)) + (PORT datad (270:270:270) (288:288:288)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1667:1667:1667) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4540:4540:4540) (4423:4423:4423)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (470:470:470)) + (PORT datab (386:386:386) (459:459:459)) + (PORT datac (304:304:304) (378:378:378)) + (PORT datad (238:238:238) (250:250:250)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (1323:1323:1323) (1182:1182:1182)) + (PORT datad (1230:1230:1230) (1057:1057:1057)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1667:1667:1667) (1686:1686:1686)) + (PORT asdata (5177:5177:5177) (4374:4374:4374)) + (PORT clrn (4540:4540:4540) (4423:4423:4423)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (289:289:289) (297:297:297)) + (PORT datac (1371:1371:1371) (1143:1143:1143)) + (PORT datad (1137:1137:1137) (995:995:995)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1668:1668:1668) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4535:4535:4535) (4419:4419:4419)) + (PORT sclr (1417:1417:1417) (1340:1340:1340)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (334:334:334) (393:393:393)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1668:1668:1668) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4535:4535:4535) (4419:4419:4419)) + (PORT sclr (1417:1417:1417) (1340:1340:1340)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (327:327:327) (384:384:384)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1668:1668:1668) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4535:4535:4535) (4419:4419:4419)) + (PORT sclr (1417:1417:1417) (1340:1340:1340)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (335:335:335) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1668:1668:1668) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4535:4535:4535) (4419:4419:4419)) + (PORT sclr (1417:1417:1417) (1340:1340:1340)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (325:325:325) (382:382:382)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1668:1668:1668) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4535:4535:4535) (4419:4419:4419)) + (PORT sclr (1417:1417:1417) (1340:1340:1340)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1668:1668:1668) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4535:4535:4535) (4419:4419:4419)) + (PORT sclr (1417:1417:1417) (1340:1340:1340)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1668:1668:1668) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4535:4535:4535) (4419:4419:4419)) + (PORT sclr (1417:1417:1417) (1340:1340:1340)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (299:299:299) (355:355:355)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1668:1668:1668) (1687:1687:1687)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4535:4535:4535) (4419:4419:4419)) + (PORT sclr (1417:1417:1417) (1340:1340:1340)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD sclr (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (405:405:405)) + (PORT datab (336:336:336) (396:396:396)) + (PORT datac (290:290:290) (359:359:359)) + (PORT datad (291:291:291) (354:354:354)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (477:477:477)) + (PORT datab (906:906:906) (843:843:843)) + (PORT datac (780:780:780) (660:660:660)) + (PORT datad (935:935:935) (845:845:845)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1671:1671:1671) (1691:1691:1691)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4486:4486:4486) (4392:4392:4392)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (387:387:387)) + (PORT datac (857:857:857) (800:800:800)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|valid_rreq) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (405:405:405)) + (PORT datad (878:878:878) (828:828:828)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (757:757:757) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT asdata (4150:4150:4150) (4272:4272:4272)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_ack\~2) + (DELAY + (ABSOLUTE + (PORT dataa (969:969:969) (894:894:894)) + (PORT datab (874:874:874) (765:765:765)) + (PORT datac (805:805:805) (692:692:692)) + (PORT datad (250:250:250) (258:258:258)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT datad (860:860:860) (729:729:729)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (2009:2009:2009) (1777:1777:1777)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (403:403:403)) + (PORT datac (304:304:304) (370:370:370)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (757:757:757) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT asdata (4075:4075:4075) (4201:4201:4201)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT datad (856:856:856) (725:725:725)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (717:717:717) (741:741:741)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT asdata (4089:4089:4089) (4173:4173:4173)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datad (854:854:854) (723:723:723)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (747:747:747) (771:771:771)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT asdata (3873:3873:3873) (3900:3900:3900)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT datad (861:861:861) (731:731:731)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (757:757:757) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT asdata (3922:3922:3922) (3924:3924:3924)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[4\]\~1) + (DELAY + (ABSOLUTE + (PORT datad (854:854:854) (723:723:723)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (737:737:737) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT asdata (4158:4158:4158) (4248:4248:4248)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (857:857:857) (726:726:726)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (767:767:767) (791:791:791)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT asdata (4305:4305:4305) (4347:4347:4347)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[6\]\~3) + (DELAY + (ABSOLUTE + (PORT datad (861:861:861) (730:730:730)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (757:757:757) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1664:1664:1664) (1682:1682:1682)) + (PORT asdata (4045:4045:4045) (4160:4160:4160)) + (PORT clrn (1696:1696:1696) (1647:1647:1647)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT datad (855:855:855) (724:724:724)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (929:929:929) (801:801:801)) + (PORT d[1] (853:853:853) (744:744:744)) + (PORT d[2] (852:852:852) (744:744:744)) + (PORT d[3] (926:926:926) (797:797:797)) + (PORT d[4] (856:856:856) (756:756:756)) + (PORT d[5] (853:853:853) (743:743:743)) + (PORT d[6] (874:874:874) (756:756:756)) + (PORT d[7] (890:890:890) (778:778:778)) + (PORT clk (2028:2028:2028) (2069:2069:2069)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (989:989:989) (909:909:909)) + (PORT d[1] (944:944:944) (888:888:888)) + (PORT d[2] (916:916:916) (866:866:866)) + (PORT d[3] (1695:1695:1695) (1545:1545:1545)) + (PORT d[4] (916:916:916) (865:865:865)) + (PORT d[5] (1730:1730:1730) (1544:1544:1544)) + (PORT d[6] (1647:1647:1647) (1445:1445:1445)) + (PORT d[7] (965:965:965) (904:904:904)) + (PORT d[8] (1012:1012:1012) (943:943:943)) + (PORT d[9] (904:904:904) (790:790:790)) + (PORT clk (2025:2025:2025) (2065:2065:2065)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1224:1224:1224) (1061:1061:1061)) + (PORT clk (2025:2025:2025) (2065:2065:2065)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2028:2028:2028) (2069:2069:2069)) + (PORT d[0] (1846:1846:1846) (1693:1693:1693)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2029:2029:2029) (2070:2070:2070)) + (IOPATH (posedge clk) pulse (0:0:0) (2490:2490:2490)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2029:2029:2029) (2070:2070:2070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2029:2029:2029) (2070:2070:2070)) + (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2029:2029:2029) (2070:2070:2070)) + (IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (513:513:513) (456:456:456)) + (PORT d[1] (926:926:926) (871:871:871)) + (PORT d[2] (1734:1734:1734) (1566:1566:1566)) + (PORT d[3] (1930:1930:1930) (1722:1722:1722)) + (PORT d[4] (1906:1906:1906) (1685:1685:1685)) + (PORT d[5] (1939:1939:1939) (1714:1714:1714)) + (PORT d[6] (982:982:982) (912:912:912)) + (PORT d[7] (1027:1027:1027) (954:954:954)) + (PORT d[8] (1649:1649:1649) (1462:1462:1462)) + (PORT d[9] (894:894:894) (782:782:782)) + (PORT clk (1981:1981:1981) (1977:1977:1977)) + (PORT aclr (2017:2017:2017) (2021:2021:2021)) + (PORT stall (1163:1163:1163) (1322:1322:1322)) + (IOPATH (posedge aclr) q (356:356:356) (356:356:356)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (230:230:230)) + (HOLD stall (posedge clk) (230:230:230)) + (HOLD aclr (posedge clk) (230:230:230)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1981:1981:1981) (1977:1977:1977)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1982:1982:1982) (1978:1978:1978)) + (IOPATH (posedge clk) pulse (0:0:0) (2891:2891:2891)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1982:1982:1982) (1978:1978:1978)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1982:1982:1982) (1978:1978:1978)) + (IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1972:1972:1972) (1970:1970:1970)) + (PORT ena (1676:1676:1676) (1537:1537:1537)) + (PORT aclr (1970:1970:1970) (2031:2031:2031)) + (IOPATH (posedge clk) q (353:353:353) (353:353:353)) + (IOPATH (posedge aclr) q (393:393:393) (393:393:393)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (56:56:56)) + (SETUP ena (posedge clk) (56:56:56)) + (SETUP aclr (posedge clk) (56:56:56)) + (HOLD d (posedge clk) (190:190:190)) + (HOLD ena (posedge clk) (190:190:190)) + (HOLD aclr (posedge clk) (190:190:190)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2617:2617:2617) (2315:2315:2315)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita1) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2617:2617:2617) (2315:2315:2315)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita2) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2617:2617:2617) (2315:2315:2315)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita3) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2617:2617:2617) (2315:2315:2315)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita4) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2617:2617:2617) (2315:2315:2315)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita5) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2617:2617:2617) (2315:2315:2315)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita6) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2617:2617:2617) (2315:2315:2315)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita7) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2617:2617:2617) (2315:2315:2315)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita8) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2617:2617:2617) (2315:2315:2315)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita9) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (397:397:397)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2617:2617:2617) (2315:2315:2315)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2202:2202:2202) (1946:1946:1946)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita1) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2202:2202:2202) (1946:1946:1946)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita2) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2202:2202:2202) (1946:1946:1946)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita3) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (396:396:396)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2202:2202:2202) (1946:1946:1946)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita4) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2202:2202:2202) (1946:1946:1946)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita5) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2202:2202:2202) (1946:1946:1946)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita6) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (403:403:403)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2202:2202:2202) (1946:1946:1946)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita7) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (395:395:395)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2202:2202:2202) (1946:1946:1946)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita8) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2202:2202:2202) (1946:1946:1946)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita9) + (DELAY + (ABSOLUTE + (PORT datad (494:494:494) (481:481:481)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1660:1660:1660) (1678:1678:1678)) + (PORT d (90:90:90) (101:101:101)) + (PORT ena (2202:2202:2202) (1946:1946:1946)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~4) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (473:473:473)) + (PORT datab (352:352:352) (418:418:418)) + (PORT datac (713:713:713) (583:583:583)) + (PORT datad (345:345:345) (421:421:421)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~3) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (845:845:845)) + (PORT datad (299:299:299) (354:354:354)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~5) + (DELAY + (ABSOLUTE + (PORT dataa (801:801:801) (654:654:654)) + (PORT datab (280:280:280) (291:291:291)) + (PORT datac (1102:1102:1102) (891:891:891)) + (PORT datad (437:437:437) (372:372:372)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|tx) + (DELAY + (ABSOLUTE + (PORT clk (1667:1667:1667) (1686:1686:1686)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4540:4540:4540) (4423:4423:4423)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[2\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2044:2044:2044) (2012:2012:2012)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT asdata (1338:1338:1338) (1267:1267:1267)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT asdata (1250:1250:1250) (1174:1174:1174)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (427:427:427)) + (PORT datac (1177:1177:1177) (1146:1146:1146)) + (PORT datad (1124:1124:1124) (1091:1091:1091)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT asdata (2029:2029:2029) (1853:1853:1853)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (430:430:430)) + (PORT datab (386:386:386) (456:456:456)) + (PORT datad (488:488:488) (437:437:437)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_TRF) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1212:1212:1212) (997:997:997)) + (PORT datab (290:290:290) (298:298:298)) + (PORT datac (340:340:340) (418:418:418)) + (PORT datad (295:295:295) (357:357:357)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (286:286:286) (303:303:303)) + (PORT datab (387:387:387) (459:459:459)) + (PORT datac (286:286:286) (353:353:353)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_AR) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1700:1700:1700) (1457:1457:1457)) + (PORT datad (1269:1269:1269) (1154:1154:1154)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1162:1162:1162) (971:971:971)) + (PORT datab (1144:1144:1144) (970:970:970)) + (PORT datad (276:276:276) (331:331:331)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1163:1163:1163) (972:972:972)) + (PORT datab (315:315:315) (368:368:368)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~4) + (DELAY + (ABSOLUTE + (PORT datac (898:898:898) (851:851:851)) + (PORT datad (226:226:226) (233:233:233)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1646:1646:1646) (1467:1467:1467)) + (PORT datac (1165:1165:1165) (1044:1044:1044)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\~17) + (DELAY + (ABSOLUTE + (PORT datab (276:276:276) (285:285:285)) + (PORT datad (569:569:569) (556:556:556)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_PRE) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1639:1639:1639)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|WideOr5) + (DELAY + (ABSOLUTE + (PORT dataa (1695:1695:1695) (1452:1452:1452)) + (PORT datab (1310:1310:1310) (1193:1193:1193)) + (PORT datad (1587:1587:1587) (1389:1389:1389)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\~0) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (784:784:784)) + (PORT datad (1204:1204:1204) (1065:1065:1065)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1159:1159:1159) (968:968:968)) + (PORT datab (316:316:316) (370:370:370)) + (PORT datac (1103:1103:1103) (938:938:938)) + (PORT datad (275:275:275) (330:330:330)) + (IOPATH dataa combout (420:420:420) (425:425:425)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (510:510:510)) + (PORT datab (317:317:317) (371:371:371)) + (PORT datac (1100:1100:1100) (935:935:935)) + (PORT datad (227:227:227) (234:234:234)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector5\~2) + (DELAY + (ABSOLUTE + (PORT datac (898:898:898) (850:850:850)) + (PORT datad (225:225:225) (232:232:232)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (443:443:443)) + (PORT datab (362:362:362) (425:425:425)) + (PORT datac (345:345:345) (427:427:427)) + (PORT datad (531:531:531) (521:521:521)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT datac (1170:1170:1170) (1138:1138:1138)) + (PORT datad (1130:1130:1130) (1099:1099:1099)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (296:296:296)) + (PORT datac (308:308:308) (375:375:375)) + (PORT datad (534:534:534) (527:527:527)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (269:269:269) (280:280:280)) + (PORT datab (526:526:526) (506:506:506)) + (PORT datac (1098:1098:1098) (923:923:923)) + (PORT datad (479:479:479) (458:458:458)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (393:393:393) (431:431:431)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (268:268:268) (280:280:280)) + (PORT datac (898:898:898) (851:851:851)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (923:923:923) (802:802:802)) + (PORT datab (887:887:887) (758:758:758)) + (PORT datac (940:940:940) (857:857:857)) + (PORT datad (902:902:902) (835:835:835)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (1015:1015:1015) (918:918:918)) + (PORT datac (234:234:234) (252:252:252)) + (PORT datad (533:533:533) (525:525:525)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_addr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~6) + (DELAY + (ABSOLUTE + (PORT datad (573:573:573) (561:561:561)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT datac (1187:1187:1187) (1047:1047:1047)) + (PORT datad (569:569:569) (557:557:557)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1639:1639:1639)) + (PORT ena (1012:1012:1012) (982:982:982)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~5) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (421:421:421)) + (PORT datad (572:572:572) (559:559:559)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1639:1639:1639)) + (PORT ena (1012:1012:1012) (982:982:982)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~4) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (546:546:546)) + (PORT datab (339:339:339) (399:399:399)) + (PORT datad (567:567:567) (554:554:554)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1652:1652:1652) (1674:1674:1674)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1684:1684:1684) (1639:1639:1639)) + (PORT ena (1012:1012:1012) (982:982:982)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + (HOLD ena (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\~15) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (394:394:394)) + (PORT datab (358:358:358) (420:420:420)) + (PORT datac (293:293:293) (362:362:362)) + (PORT datad (282:282:282) (339:339:339)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (529:529:529) (479:479:479)) + (PORT datab (334:334:334) (394:394:394)) + (PORT datac (342:342:342) (421:421:421)) + (PORT datad (1148:1148:1148) (950:950:950)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_MRS) + (DELAY + (ABSOLUTE + (PORT clk (1650:1650:1650) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1682:1682:1682) (1634:1634:1634)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_ba\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT asdata (1627:1627:1627) (1467:1467:1467)) + (PORT clrn (1687:1687:1687) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1039:1039:1039)) + (PORT datab (358:358:358) (427:427:427)) + (PORT datad (1123:1123:1123) (1090:1090:1090)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1233:1233:1233) (1184:1184:1184)) + (PORT datab (1290:1290:1290) (1160:1160:1160)) + (PORT datac (1064:1064:1064) (1032:1032:1032)) + (PORT datad (469:469:469) (419:419:419)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (493:493:493)) + (PORT datab (393:393:393) (465:465:465)) + (PORT datac (500:500:500) (459:459:459)) + (PORT datad (466:466:466) (396:396:396)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (283:283:283)) + (PORT datab (336:336:336) (396:396:396)) + (PORT datac (547:547:547) (525:525:525)) + (PORT datad (250:250:250) (258:258:258)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_ba\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1229:1229:1229) (1180:1180:1180)) + (PORT datab (1291:1291:1291) (1161:1161:1161)) + (PORT datac (1092:1092:1092) (964:964:964)) + (PORT datad (1130:1130:1130) (1098:1098:1098)) + (IOPATH dataa combout (428:428:428) (449:449:449)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|WideOr7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (448:448:448)) + (PORT datab (620:620:620) (577:577:577)) + (PORT datac (496:496:496) (487:487:487)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (299:299:299)) + (PORT datab (281:281:281) (292:292:292)) + (PORT datad (533:533:533) (525:525:525)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_addr\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1657:1657:1657) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (407:407:407)) + (PORT datab (328:328:328) (386:386:386)) + (PORT datad (2431:2431:2431) (2145:2145:2145)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_ACTIVE) + (DELAY + (ABSOLUTE + (PORT clk (1658:1658:1658) (1676:1676:1676)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1690:1690:1690) (1641:1641:1641)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (758:758:758)) + (PORT datab (1221:1221:1221) (1075:1075:1075)) + (PORT datac (345:345:345) (427:427:427)) + (PORT datad (319:319:319) (383:383:383)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (493:493:493)) + (PORT datab (499:499:499) (439:439:439)) + (PORT datac (350:350:350) (432:432:432)) + (PORT datad (228:228:228) (236:236:236)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_addr\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1654:1654:1654) (1673:1673:1673)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1686:1686:1686) (1638:1638:1638)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (376:376:376)) + (PORT datab (358:358:358) (428:428:428)) + (PORT datac (805:805:805) (727:727:727)) + (PORT datad (1126:1126:1126) (1093:1093:1093)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1231:1231:1231) (1181:1181:1181)) + (PORT datab (1104:1104:1104) (1062:1062:1062)) + (PORT datac (769:769:769) (683:683:683)) + (PORT datad (227:227:227) (235:235:235)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) +) diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_8_1200mv_85c_slow.vo b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_8_1200mv_85c_slow.vo new file mode 100644 index 0000000..aa229f8 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_8_1200mv_85c_slow.vo @@ -0,0 +1,24917 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:26:30" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module uart_sdram ( + sys_clk, + sys_rst_n, + rx, + tx, + sdram_clk, + sdram_cke, + sdram_cs_n, + sdram_cas_n, + sdram_ras_n, + sdram_we_n, + sdram_ba, + sdram_addr, + sdram_dqm, + sdram_dq); +input sys_clk; +input sys_rst_n; +input rx; +output tx; +output sdram_clk; +output sdram_cke; +output sdram_cs_n; +output sdram_cas_n; +output sdram_ras_n; +output sdram_we_n; +output [1:0] sdram_ba; +output [12:0] sdram_addr; +output [1:0] sdram_dqm; +inout [15:0] sdram_dq; + +// Design Ports Information +// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_clk => Location: PIN_E5, I/O Standard: 2.5 V, Current Strength: Default +// sdram_cke => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_cs_n => Location: PIN_A4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_cas_n => Location: PIN_B5, I/O Standard: 2.5 V, Current Strength: Default +// sdram_ras_n => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_we_n => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default +// sdram_ba[0] => Location: PIN_B4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_ba[1] => Location: PIN_C4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[0] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[1] => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[2] => Location: PIN_B2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[3] => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[4] => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[5] => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[6] => Location: PIN_F1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[7] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[8] => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[9] => Location: PIN_N2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[10] => Location: PIN_A3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[11] => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[12] => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dqm[0] => Location: PIN_C6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dqm[1] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[0] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[1] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[2] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[3] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[4] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[5] => Location: PIN_C7, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[6] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[7] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[8] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[9] => Location: PIN_C3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[10] => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[11] => Location: PIN_E3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[12] => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[13] => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[14] => Location: PIN_J3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[15] => Location: PIN_J4, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("uart_sdram_8_1200mv_85c_v_slow.sdo"); +// synopsys translate_on + +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout ; +wire \uart_tx_inst|baud_cnt[3]~19_combout ; +wire \uart_tx_inst|baud_cnt[4]~21_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout ; +wire \fifo_read_inst|Add2~4_combout ; +wire \Add1~1 ; +wire \Add1~0_combout ; +wire \Add1~3 ; +wire \Add1~2_combout ; +wire \Add1~5 ; +wire \Add1~4_combout ; +wire \Add1~7 ; +wire \Add1~6_combout ; +wire \Add1~9 ; +wire \Add1~8_combout ; +wire \Add1~11 ; +wire \Add1~10_combout ; +wire \Add1~13 ; +wire \Add1~12_combout ; +wire \Add1~15 ; +wire \Add1~14_combout ; +wire \Add1~17 ; +wire \Add1~16_combout ; +wire \Add1~19 ; +wire \Add1~18_combout ; +wire \Add1~21 ; +wire \Add1~20_combout ; +wire \Add1~23 ; +wire \Add1~22_combout ; +wire \Add1~25 ; +wire \Add1~24_combout ; +wire \Add1~27 ; +wire \Add1~26_combout ; +wire \Add1~29 ; +wire \Add1~28_combout ; +wire \Add1~30_combout ; +wire \fifo_read_inst|baud_cnt[1]~15_combout ; +wire \fifo_read_inst|baud_cnt[4]~21_combout ; +wire \fifo_read_inst|baud_cnt[9]~31_combout ; +wire \fifo_read_inst|baud_cnt[11]~35_combout ; +wire \data_num[0]~25 ; +wire \data_num[0]~24_combout ; +wire \data_num[1]~27 ; +wire \data_num[1]~26_combout ; +wire \data_num[2]~29 ; +wire \data_num[2]~28_combout ; +wire \data_num[3]~31 ; +wire \data_num[3]~30_combout ; +wire \data_num[4]~33 ; +wire \data_num[4]~32_combout ; +wire \data_num[5]~35 ; +wire \data_num[5]~34_combout ; +wire \data_num[6]~37 ; +wire \data_num[6]~36_combout ; +wire \data_num[7]~39 ; +wire \data_num[7]~38_combout ; +wire \data_num[8]~41 ; +wire \data_num[8]~40_combout ; +wire \data_num[9]~43 ; +wire \data_num[9]~42_combout ; +wire \data_num[10]~45 ; +wire \data_num[10]~44_combout ; +wire \data_num[11]~47 ; +wire \data_num[11]~46_combout ; +wire \data_num[12]~49 ; +wire \data_num[12]~48_combout ; +wire \data_num[13]~51 ; +wire \data_num[13]~50_combout ; +wire \data_num[14]~53 ; +wire \data_num[14]~52_combout ; +wire \data_num[15]~55 ; +wire \data_num[15]~54_combout ; +wire \data_num[16]~57 ; +wire \data_num[16]~56_combout ; +wire \data_num[17]~59 ; +wire \data_num[17]~58_combout ; +wire \data_num[18]~61 ; +wire \data_num[18]~60_combout ; +wire \data_num[19]~63 ; +wire \data_num[19]~62_combout ; +wire \data_num[20]~65 ; +wire \data_num[20]~64_combout ; +wire \data_num[21]~67 ; +wire \data_num[21]~66_combout ; +wire \data_num[22]~69 ; +wire \data_num[22]~68_combout ; +wire \data_num[23]~70_combout ; +wire \uart_rx_inst|Add1~0_combout ; +wire \uart_rx_inst|Add1~5 ; +wire \uart_rx_inst|Add1~6_combout ; +wire \fifo_read_inst|cnt_read[0]~11 ; +wire \fifo_read_inst|cnt_read[0]~10_combout ; +wire \fifo_read_inst|cnt_read[1]~13 ; +wire \fifo_read_inst|cnt_read[1]~12_combout ; +wire \fifo_read_inst|cnt_read[2]~15 ; +wire \fifo_read_inst|cnt_read[2]~14_combout ; +wire \fifo_read_inst|cnt_read[3]~17 ; +wire \fifo_read_inst|cnt_read[3]~16_combout ; +wire \fifo_read_inst|cnt_read[4]~19 ; +wire \fifo_read_inst|cnt_read[4]~18_combout ; +wire \fifo_read_inst|cnt_read[5]~21 ; +wire \fifo_read_inst|cnt_read[5]~20_combout ; +wire \fifo_read_inst|cnt_read[6]~23 ; +wire \fifo_read_inst|cnt_read[6]~22_combout ; +wire \fifo_read_inst|cnt_read[7]~25 ; +wire \fifo_read_inst|cnt_read[7]~24_combout ; +wire \fifo_read_inst|cnt_read[8]~27 ; +wire \fifo_read_inst|cnt_read[8]~26_combout ; +wire \fifo_read_inst|cnt_read[9]~28_combout ; +wire \uart_rx_inst|baud_cnt[4]~21_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout ; +wire \uart_tx_inst|Mux0~0_combout ; +wire \uart_tx_inst|Mux0~1_combout ; +wire \uart_tx_inst|tx~0_combout ; +wire \uart_tx_inst|tx~1_combout ; +wire \uart_tx_inst|tx~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout ; +wire \uart_tx_inst|Add1~0_combout ; +wire \uart_tx_inst|Add1~1_combout ; +wire \uart_tx_inst|bit_cnt[3]~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout ; +wire \read_valid~q ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout ; +wire \uart_tx_inst|Equal1~3_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ; +wire \fifo_read_inst|Equal1~0_combout ; +wire \fifo_read_inst|Equal1~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout ; +wire \Equal0~0_combout ; +wire \Equal0~1_combout ; +wire \Equal0~2_combout ; +wire \Equal0~3_combout ; +wire \Equal0~4_combout ; +wire \read_valid~0_combout ; +wire \read_valid~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ; +wire \fifo_read_inst|Equal1~2_combout ; +wire \fifo_read_inst|Equal5~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \Equal1~0_combout ; +wire \Equal1~1_combout ; +wire \Equal1~2_combout ; +wire \Equal1~3_combout ; +wire \Equal1~4_combout ; +wire \Equal1~5_combout ; +wire \Equal1~6_combout ; +wire \cnt_wait[8]~0_combout ; +wire \cnt_wait[15]~1_combout ; +wire \cnt_wait[15]~2_combout ; +wire \cnt_wait[14]~3_combout ; +wire \cnt_wait[13]~4_combout ; +wire \cnt_wait[12]~5_combout ; +wire \cnt_wait[9]~6_combout ; +wire \cnt_wait[11]~7_combout ; +wire \cnt_wait[10]~8_combout ; +wire \cnt_wait[8]~9_combout ; +wire \cnt_wait[7]~10_combout ; +wire \cnt_wait[6]~11_combout ; +wire \cnt_wait[5]~12_combout ; +wire \cnt_wait[4]~13_combout ; +wire \cnt_wait[3]~14_combout ; +wire \cnt_wait[2]~15_combout ; +wire \cnt_wait[1]~16_combout ; +wire \cnt_wait[0]~17_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \fifo_read_inst|rd_flag~q ; +wire \fifo_read_inst|Equal4~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ; +wire \fifo_read_inst|Equal2~0_combout ; +wire \fifo_read_inst|Equal2~1_combout ; +wire \fifo_read_inst|Equal2~2_combout ; +wire \fifo_read_inst|rd_flag~0_combout ; +wire \uart_rx_inst|bit_cnt~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout ; +wire \uart_rx_inst|work_en~q ; +wire \uart_rx_inst|start_nedge~q ; +wire \uart_rx_inst|work_en~0_combout ; +wire \uart_rx_inst|always3~0_combout ; +wire \uart_tx_inst|bit_cnt[0]~5_combout ; +wire \sdram_dq[8]~input_o ; +wire \sdram_dq[9]~input_o ; +wire \sdram_dq[10]~input_o ; +wire \sdram_dq[11]~input_o ; +wire \sdram_dq[12]~input_o ; +wire \sdram_dq[13]~input_o ; +wire \sdram_dq[14]~input_o ; +wire \sdram_dq[15]~input_o ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout ; +wire \uart_rx_inst|baud_cnt[0]~13_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \uart_rx_inst|baud_cnt[2]~18 ; +wire \uart_rx_inst|baud_cnt[3]~19_combout ; +wire \uart_rx_inst|baud_cnt[3]~20 ; +wire \uart_rx_inst|baud_cnt[4]~22 ; +wire \uart_rx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|Equal1~1_combout ; +wire \uart_rx_inst|baud_cnt[5]~24 ; +wire \uart_rx_inst|baud_cnt[6]~25_combout ; +wire \uart_rx_inst|baud_cnt[6]~26 ; +wire \uart_rx_inst|baud_cnt[7]~27_combout ; +wire \uart_rx_inst|baud_cnt[7]~28 ; +wire \uart_rx_inst|baud_cnt[8]~29_combout ; +wire \uart_rx_inst|Equal1~0_combout ; +wire \uart_rx_inst|baud_cnt[8]~30 ; +wire \uart_rx_inst|baud_cnt[9]~31_combout ; +wire \uart_rx_inst|baud_cnt[9]~32 ; +wire \uart_rx_inst|baud_cnt[10]~34 ; +wire \uart_rx_inst|baud_cnt[11]~35_combout ; +wire \uart_rx_inst|Equal1~2_combout ; +wire \uart_rx_inst|baud_cnt[10]~33_combout ; +wire \uart_rx_inst|Equal1~3_combout ; +wire \uart_rx_inst|always5~0_combout ; +wire \uart_rx_inst|baud_cnt[0]~14 ; +wire \uart_rx_inst|baud_cnt[1]~15_combout ; +wire \uart_rx_inst|baud_cnt[1]~16 ; +wire \uart_rx_inst|baud_cnt[2]~17_combout ; +wire \uart_rx_inst|Equal2~0_combout ; +wire \uart_rx_inst|baud_cnt[11]~36 ; +wire \uart_rx_inst|baud_cnt[12]~37_combout ; +wire \uart_rx_inst|Equal2~1_combout ; +wire \uart_rx_inst|Equal2~2_combout ; +wire \uart_rx_inst|bit_flag~q ; +wire \uart_rx_inst|Add1~1 ; +wire \uart_rx_inst|Add1~3 ; +wire \uart_rx_inst|Add1~4_combout ; +wire \uart_rx_inst|Add1~2_combout ; +wire \uart_rx_inst|always4~0_combout ; +wire \uart_rx_inst|always4~1_combout ; +wire \uart_rx_inst|rx_flag~q ; +wire \uart_rx_inst|po_flag~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ; +wire \fifo_read_inst|read_en_dly~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout ; +wire \fifo_read_inst|Add2~0_combout ; +wire \fifo_read_inst|Add2~1 ; +wire \fifo_read_inst|Add2~3 ; +wire \fifo_read_inst|Add2~5 ; +wire \fifo_read_inst|Add2~6_combout ; +wire \fifo_read_inst|bit_cnt~0_combout ; +wire \fifo_read_inst|baud_cnt[0]~13_combout ; +wire \fifo_read_inst|baud_cnt[5]~24 ; +wire \fifo_read_inst|baud_cnt[6]~25_combout ; +wire \fifo_read_inst|baud_cnt[6]~26 ; +wire \fifo_read_inst|baud_cnt[7]~27_combout ; +wire \fifo_read_inst|baud_cnt[7]~28 ; +wire \fifo_read_inst|baud_cnt[8]~29_combout ; +wire \fifo_read_inst|Equal4~0_combout ; +wire \fifo_read_inst|baud_cnt[3]~19_combout ; +wire \fifo_read_inst|Equal4~1_combout ; +wire \fifo_read_inst|baud_cnt[8]~30 ; +wire \fifo_read_inst|baud_cnt[9]~32 ; +wire \fifo_read_inst|baud_cnt[10]~33_combout ; +wire \fifo_read_inst|baud_cnt[10]~34 ; +wire \fifo_read_inst|baud_cnt[11]~36 ; +wire \fifo_read_inst|baud_cnt[12]~37_combout ; +wire \fifo_read_inst|Equal4~3_combout ; +wire \fifo_read_inst|baud_cnt[0]~14 ; +wire \fifo_read_inst|baud_cnt[1]~16 ; +wire \fifo_read_inst|baud_cnt[2]~17_combout ; +wire \fifo_read_inst|baud_cnt[2]~18 ; +wire \fifo_read_inst|baud_cnt[3]~20 ; +wire \fifo_read_inst|baud_cnt[4]~22 ; +wire \fifo_read_inst|baud_cnt[5]~23_combout ; +wire \fifo_read_inst|Equal5~0_combout ; +wire \fifo_read_inst|Equal5~2_combout ; +wire \fifo_read_inst|bit_flag~q ; +wire \fifo_read_inst|Add2~2_combout ; +wire \fifo_read_inst|bit_cnt~1_combout ; +wire \fifo_read_inst|always5~0_combout ; +wire \fifo_read_inst|always5~1_combout ; +wire \fifo_read_inst|rd_en~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ; +wire \Equal2~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ; +wire \fifo_read_inst|read_en~0_combout ; +wire \fifo_read_inst|read_en~1_combout ; +wire \fifo_read_inst|read_en~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ; +wire \Equal2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \rx~input_o ; +wire \uart_rx_inst|rx_reg1~0_combout ; +wire \uart_rx_inst|rx_reg1~q ; +wire \uart_rx_inst|rx_reg2~feeder_combout ; +wire \uart_rx_inst|rx_reg2~q ; +wire \uart_rx_inst|rx_reg3~feeder_combout ; +wire \uart_rx_inst|rx_reg3~q ; +wire \uart_rx_inst|rx_data[7]~0_combout ; +wire \uart_rx_inst|bit_cnt~0_combout ; +wire \uart_rx_inst|always8~0_combout ; +wire \uart_rx_inst|rx_data[5]~feeder_combout ; +wire \uart_rx_inst|rx_data[4]~feeder_combout ; +wire \uart_rx_inst|rx_data[3]~feeder_combout ; +wire \uart_rx_inst|rx_data[2]~feeder_combout ; +wire \uart_rx_inst|rx_data[1]~feeder_combout ; +wire \uart_rx_inst|rx_data[0]~feeder_combout ; +wire \uart_rx_inst|po_data[0]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \uart_rx_inst|po_data[1]~feeder_combout ; +wire \uart_rx_inst|po_data[2]~feeder_combout ; +wire \uart_rx_inst|po_data[3]~feeder_combout ; +wire \uart_rx_inst|po_data[4]~feeder_combout ; +wire \uart_rx_inst|po_data[5]~feeder_combout ; +wire \uart_rx_inst|po_data[6]~feeder_combout ; +wire \~GND~combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ; +wire \sys_clk~inputclkctrl_outclk ; +wire \uart_tx_inst|baud_cnt[0]~13_combout ; +wire \uart_tx_inst|baud_cnt[11]~35_combout ; +wire \uart_tx_inst|Equal1~0_combout ; +wire \uart_tx_inst|baud_cnt[9]~31_combout ; +wire \uart_tx_inst|Equal1~1_combout ; +wire \uart_tx_inst|baud_cnt[1]~15_combout ; +wire \uart_tx_inst|Equal1~2_combout ; +wire \fifo_read_inst|tx_flag~q ; +wire \uart_tx_inst|always3~0_combout ; +wire \uart_tx_inst|bit_cnt[1]~2_combout ; +wire \uart_tx_inst|bit_cnt[2]~3_combout ; +wire \uart_tx_inst|always0~1_combout ; +wire \uart_tx_inst|work_en~0_combout ; +wire \uart_tx_inst|work_en~q ; +wire \uart_tx_inst|always1~0_combout ; +wire \uart_tx_inst|baud_cnt[0]~14 ; +wire \uart_tx_inst|baud_cnt[1]~16 ; +wire \uart_tx_inst|baud_cnt[2]~17_combout ; +wire \uart_tx_inst|baud_cnt[2]~18 ; +wire \uart_tx_inst|baud_cnt[3]~20 ; +wire \uart_tx_inst|baud_cnt[4]~22 ; +wire \uart_tx_inst|baud_cnt[5]~23_combout ; +wire \uart_tx_inst|baud_cnt[5]~24 ; +wire \uart_tx_inst|baud_cnt[6]~25_combout ; +wire \uart_tx_inst|baud_cnt[6]~26 ; +wire \uart_tx_inst|baud_cnt[7]~27_combout ; +wire \uart_tx_inst|baud_cnt[7]~28 ; +wire \uart_tx_inst|baud_cnt[8]~29_combout ; +wire \uart_tx_inst|baud_cnt[8]~30 ; +wire \uart_tx_inst|baud_cnt[9]~32 ; +wire \uart_tx_inst|baud_cnt[10]~33_combout ; +wire \uart_tx_inst|baud_cnt[10]~34 ; +wire \uart_tx_inst|baud_cnt[11]~36 ; +wire \uart_tx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal2~0_combout ; +wire \uart_tx_inst|Equal2~1_combout ; +wire \uart_tx_inst|bit_flag~q ; +wire \uart_tx_inst|always0~0_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ; +wire \sdram_dq[0]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \sdram_dq[1]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout ; +wire \sdram_dq[2]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout ; +wire \sdram_dq[3]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout ; +wire \sdram_dq[4]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout ; +wire \sdram_dq[5]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout ; +wire \sdram_dq[6]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout ; +wire \sdram_dq[7]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout ; +wire \uart_tx_inst|tx~4_combout ; +wire \uart_tx_inst|tx~3_combout ; +wire \uart_tx_inst|tx~5_combout ; +wire \uart_tx_inst|tx~q ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a ; +wire [15:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a ; +wire [9:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit ; +wire [23:0] data_num; +wire [15:0] cnt_wait; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \uart_rx_inst|rx_data ; +wire [7:0] \uart_rx_inst|po_data ; +wire [3:0] \uart_rx_inst|bit_cnt ; +wire [12:0] \uart_rx_inst|baud_cnt ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g ; +wire [9:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a ; +wire [15:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd ; +wire [1:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref ; +wire [2:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk ; +wire [14:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us ; +wire [2:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk ; +wire [1:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref ; +wire [9:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd ; +wire [1:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba ; +wire [12:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr ; +wire [9:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd ; +wire [12:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr ; +wire [15:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg ; +wire [9:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk ; +wire [9:0] \fifo_read_inst|cnt_read ; +wire [3:0] \fifo_read_inst|bit_cnt ; +wire [12:0] \fifo_read_inst|baud_cnt ; +wire [9:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit ; +wire [7:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b ; +wire [9:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit ; +wire [3:0] \uart_tx_inst|bit_cnt ; +wire [12:0] \uart_tx_inst|baud_cnt ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; +wire [8:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus ; +wire [8:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; +wire [8:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; +wire [8:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [0] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [0]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [1] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [1]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [2] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [2]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [3] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [3]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [4] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [4]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [5] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [5]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [6] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [6]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [7] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [7]; + +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; + +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [8] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [8]; + +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [9] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [0]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [10] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [1]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [11] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [2]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [12] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [3]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [13] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [4]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [14] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [5]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [15] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [6]; + +// Location: M9K_X25_Y18_N0 +cycloneive_ram_block \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 ( + .portawe(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .ena1(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({gnd,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0]}), + .portaaddr({\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .clk0_core_clock_enable = "ena0"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .clk1_core_clock_enable = "ena1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .clk1_input_clock_enable = "ena1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .data_interleave_offset_in_bits = 1; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .data_interleave_width_in_bits = 1; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .logical_ram_name = "fifo_read:fifo_read_inst|read_fifo:read_fifo_inst|scfifo:scfifo_component|scfifo_un21:auto_generated|a_dpfifo_5u21:dpfifo|dpram_d811:FIFOram|altsyncram_c3k1:altsyncram1|ALTSYNCRAM"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .operation_mode = "dual_port"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_address_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_address_width = 10; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_byte_enable_clock = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_data_out_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_data_out_clock = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_data_width = 9; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_first_address = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_first_bit_number = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_last_address = 1023; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_logical_ram_depth = 1024; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_logical_ram_width = 8; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_address_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_address_clock = "clock1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_address_width = 10; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_data_out_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_data_out_clock = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_data_width = 9; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_first_address = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_first_bit_number = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_last_address = 1023; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_logical_ram_depth = 1024; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_logical_ram_width = 8; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_read_enable_clock = "clock1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: FF_X24_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y21_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y23_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y23_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y18_N11 +dffeas \uart_tx_inst|baud_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y18_N13 +dffeas \uart_tx_inst|baud_cnt[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0] & ((GND) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0]))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0] $ (GND))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0 .lut_mask = 16'h66BB; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N10 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) + + .dataa(\uart_tx_inst|baud_cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[2]~18 ), + .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_tx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N12 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) +// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[3]~20 ), + .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_tx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [13] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N8 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N10 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N14 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N18 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT ) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N7 +dffeas \fifo_read_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N13 +dffeas \fifo_read_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N23 +dffeas \fifo_read_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N27 +dffeas \fifo_read_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N12 +cycloneive_lcell_comb \fifo_read_inst|Add2~4 ( +// Equation(s): +// \fifo_read_inst|Add2~4_combout = (\fifo_read_inst|bit_cnt [2] & (\fifo_read_inst|Add2~3 $ (GND))) # (!\fifo_read_inst|bit_cnt [2] & (!\fifo_read_inst|Add2~3 & VCC)) +// \fifo_read_inst|Add2~5 = CARRY((\fifo_read_inst|bit_cnt [2] & !\fifo_read_inst|Add2~3 )) + + .dataa(\fifo_read_inst|bit_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|Add2~3 ), + .combout(\fifo_read_inst|Add2~4_combout ), + .cout(\fifo_read_inst|Add2~5 )); +// synopsys translate_off +defparam \fifo_read_inst|Add2~4 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|Add2~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y24_N9 +dffeas \data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[0]~24_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[0] .is_wysiwyg = "true"; +defparam \data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N13 +dffeas \data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[2]~28_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[2] .is_wysiwyg = "true"; +defparam \data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N11 +dffeas \data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[1]~26_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[1] .is_wysiwyg = "true"; +defparam \data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N15 +dffeas \data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[3]~30_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[3] .is_wysiwyg = "true"; +defparam \data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N17 +dffeas \data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[4]~32_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[4] .is_wysiwyg = "true"; +defparam \data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N19 +dffeas \data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[5]~34_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[5] .is_wysiwyg = "true"; +defparam \data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N21 +dffeas \data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[6]~36_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[6] .is_wysiwyg = "true"; +defparam \data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N23 +dffeas \data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[7]~38_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[7] .is_wysiwyg = "true"; +defparam \data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N25 +dffeas \data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[8]~40_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[8] .is_wysiwyg = "true"; +defparam \data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N27 +dffeas \data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[9]~42_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[9] .is_wysiwyg = "true"; +defparam \data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N29 +dffeas \data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[10]~44_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[10] .is_wysiwyg = "true"; +defparam \data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N31 +dffeas \data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[11]~46_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[11]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[11] .is_wysiwyg = "true"; +defparam \data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N1 +dffeas \data_num[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[12]~48_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[12]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[12] .is_wysiwyg = "true"; +defparam \data_num[12] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N3 +dffeas \data_num[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[13]~50_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[13]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[13] .is_wysiwyg = "true"; +defparam \data_num[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N5 +dffeas \data_num[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[14]~52_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[14]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[14] .is_wysiwyg = "true"; +defparam \data_num[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N7 +dffeas \data_num[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[15]~54_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[15]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[15] .is_wysiwyg = "true"; +defparam \data_num[15] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N9 +dffeas \data_num[16] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[16]~56_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[16]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[16] .is_wysiwyg = "true"; +defparam \data_num[16] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N11 +dffeas \data_num[17] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[17]~58_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[17]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[17] .is_wysiwyg = "true"; +defparam \data_num[17] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N13 +dffeas \data_num[18] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[18]~60_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[18]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[18] .is_wysiwyg = "true"; +defparam \data_num[18] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N15 +dffeas \data_num[19] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[19]~62_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[19]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[19] .is_wysiwyg = "true"; +defparam \data_num[19] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N17 +dffeas \data_num[20] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[20]~64_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[20]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[20] .is_wysiwyg = "true"; +defparam \data_num[20] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N19 +dffeas \data_num[21] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[21]~66_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[21]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[21] .is_wysiwyg = "true"; +defparam \data_num[21] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N21 +dffeas \data_num[22] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[22]~68_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[22]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[22] .is_wysiwyg = "true"; +defparam \data_num[22] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N23 +dffeas \data_num[23] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[23]~70_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[23]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[23] .is_wysiwyg = "true"; +defparam \data_num[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N0 +cycloneive_lcell_comb \Add1~0 ( +// Equation(s): +// \Add1~0_combout = cnt_wait[0] $ (VCC) +// \Add1~1 = CARRY(cnt_wait[0]) + + .dataa(gnd), + .datab(cnt_wait[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Add1~0_combout ), + .cout(\Add1~1 )); +// synopsys translate_off +defparam \Add1~0 .lut_mask = 16'h33CC; +defparam \Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N2 +cycloneive_lcell_comb \Add1~2 ( +// Equation(s): +// \Add1~2_combout = (cnt_wait[1] & (!\Add1~1 )) # (!cnt_wait[1] & ((\Add1~1 ) # (GND))) +// \Add1~3 = CARRY((!\Add1~1 ) # (!cnt_wait[1])) + + .dataa(cnt_wait[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~1 ), + .combout(\Add1~2_combout ), + .cout(\Add1~3 )); +// synopsys translate_off +defparam \Add1~2 .lut_mask = 16'h5A5F; +defparam \Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N4 +cycloneive_lcell_comb \Add1~4 ( +// Equation(s): +// \Add1~4_combout = (cnt_wait[2] & (\Add1~3 $ (GND))) # (!cnt_wait[2] & (!\Add1~3 & VCC)) +// \Add1~5 = CARRY((cnt_wait[2] & !\Add1~3 )) + + .dataa(gnd), + .datab(cnt_wait[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~3 ), + .combout(\Add1~4_combout ), + .cout(\Add1~5 )); +// synopsys translate_off +defparam \Add1~4 .lut_mask = 16'hC30C; +defparam \Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N6 +cycloneive_lcell_comb \Add1~6 ( +// Equation(s): +// \Add1~6_combout = (cnt_wait[3] & (!\Add1~5 )) # (!cnt_wait[3] & ((\Add1~5 ) # (GND))) +// \Add1~7 = CARRY((!\Add1~5 ) # (!cnt_wait[3])) + + .dataa(gnd), + .datab(cnt_wait[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~5 ), + .combout(\Add1~6_combout ), + .cout(\Add1~7 )); +// synopsys translate_off +defparam \Add1~6 .lut_mask = 16'h3C3F; +defparam \Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N8 +cycloneive_lcell_comb \Add1~8 ( +// Equation(s): +// \Add1~8_combout = (cnt_wait[4] & (\Add1~7 $ (GND))) # (!cnt_wait[4] & (!\Add1~7 & VCC)) +// \Add1~9 = CARRY((cnt_wait[4] & !\Add1~7 )) + + .dataa(cnt_wait[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~7 ), + .combout(\Add1~8_combout ), + .cout(\Add1~9 )); +// synopsys translate_off +defparam \Add1~8 .lut_mask = 16'hA50A; +defparam \Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N10 +cycloneive_lcell_comb \Add1~10 ( +// Equation(s): +// \Add1~10_combout = (cnt_wait[5] & (!\Add1~9 )) # (!cnt_wait[5] & ((\Add1~9 ) # (GND))) +// \Add1~11 = CARRY((!\Add1~9 ) # (!cnt_wait[5])) + + .dataa(cnt_wait[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~9 ), + .combout(\Add1~10_combout ), + .cout(\Add1~11 )); +// synopsys translate_off +defparam \Add1~10 .lut_mask = 16'h5A5F; +defparam \Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N12 +cycloneive_lcell_comb \Add1~12 ( +// Equation(s): +// \Add1~12_combout = (cnt_wait[6] & (\Add1~11 $ (GND))) # (!cnt_wait[6] & (!\Add1~11 & VCC)) +// \Add1~13 = CARRY((cnt_wait[6] & !\Add1~11 )) + + .dataa(cnt_wait[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~11 ), + .combout(\Add1~12_combout ), + .cout(\Add1~13 )); +// synopsys translate_off +defparam \Add1~12 .lut_mask = 16'hA50A; +defparam \Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N14 +cycloneive_lcell_comb \Add1~14 ( +// Equation(s): +// \Add1~14_combout = (cnt_wait[7] & (!\Add1~13 )) # (!cnt_wait[7] & ((\Add1~13 ) # (GND))) +// \Add1~15 = CARRY((!\Add1~13 ) # (!cnt_wait[7])) + + .dataa(cnt_wait[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~13 ), + .combout(\Add1~14_combout ), + .cout(\Add1~15 )); +// synopsys translate_off +defparam \Add1~14 .lut_mask = 16'h5A5F; +defparam \Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N16 +cycloneive_lcell_comb \Add1~16 ( +// Equation(s): +// \Add1~16_combout = (cnt_wait[8] & (\Add1~15 $ (GND))) # (!cnt_wait[8] & (!\Add1~15 & VCC)) +// \Add1~17 = CARRY((cnt_wait[8] & !\Add1~15 )) + + .dataa(cnt_wait[8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~15 ), + .combout(\Add1~16_combout ), + .cout(\Add1~17 )); +// synopsys translate_off +defparam \Add1~16 .lut_mask = 16'hA50A; +defparam \Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N18 +cycloneive_lcell_comb \Add1~18 ( +// Equation(s): +// \Add1~18_combout = (cnt_wait[9] & (!\Add1~17 )) # (!cnt_wait[9] & ((\Add1~17 ) # (GND))) +// \Add1~19 = CARRY((!\Add1~17 ) # (!cnt_wait[9])) + + .dataa(gnd), + .datab(cnt_wait[9]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~17 ), + .combout(\Add1~18_combout ), + .cout(\Add1~19 )); +// synopsys translate_off +defparam \Add1~18 .lut_mask = 16'h3C3F; +defparam \Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N20 +cycloneive_lcell_comb \Add1~20 ( +// Equation(s): +// \Add1~20_combout = (cnt_wait[10] & (\Add1~19 $ (GND))) # (!cnt_wait[10] & (!\Add1~19 & VCC)) +// \Add1~21 = CARRY((cnt_wait[10] & !\Add1~19 )) + + .dataa(cnt_wait[10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~19 ), + .combout(\Add1~20_combout ), + .cout(\Add1~21 )); +// synopsys translate_off +defparam \Add1~20 .lut_mask = 16'hA50A; +defparam \Add1~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N22 +cycloneive_lcell_comb \Add1~22 ( +// Equation(s): +// \Add1~22_combout = (cnt_wait[11] & (!\Add1~21 )) # (!cnt_wait[11] & ((\Add1~21 ) # (GND))) +// \Add1~23 = CARRY((!\Add1~21 ) # (!cnt_wait[11])) + + .dataa(gnd), + .datab(cnt_wait[11]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~21 ), + .combout(\Add1~22_combout ), + .cout(\Add1~23 )); +// synopsys translate_off +defparam \Add1~22 .lut_mask = 16'h3C3F; +defparam \Add1~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N24 +cycloneive_lcell_comb \Add1~24 ( +// Equation(s): +// \Add1~24_combout = (cnt_wait[12] & (\Add1~23 $ (GND))) # (!cnt_wait[12] & (!\Add1~23 & VCC)) +// \Add1~25 = CARRY((cnt_wait[12] & !\Add1~23 )) + + .dataa(gnd), + .datab(cnt_wait[12]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~23 ), + .combout(\Add1~24_combout ), + .cout(\Add1~25 )); +// synopsys translate_off +defparam \Add1~24 .lut_mask = 16'hC30C; +defparam \Add1~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N26 +cycloneive_lcell_comb \Add1~26 ( +// Equation(s): +// \Add1~26_combout = (cnt_wait[13] & (!\Add1~25 )) # (!cnt_wait[13] & ((\Add1~25 ) # (GND))) +// \Add1~27 = CARRY((!\Add1~25 ) # (!cnt_wait[13])) + + .dataa(gnd), + .datab(cnt_wait[13]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~25 ), + .combout(\Add1~26_combout ), + .cout(\Add1~27 )); +// synopsys translate_off +defparam \Add1~26 .lut_mask = 16'h3C3F; +defparam \Add1~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N28 +cycloneive_lcell_comb \Add1~28 ( +// Equation(s): +// \Add1~28_combout = (cnt_wait[14] & (\Add1~27 $ (GND))) # (!cnt_wait[14] & (!\Add1~27 & VCC)) +// \Add1~29 = CARRY((cnt_wait[14] & !\Add1~27 )) + + .dataa(cnt_wait[14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~27 ), + .combout(\Add1~28_combout ), + .cout(\Add1~29 )); +// synopsys translate_off +defparam \Add1~28 .lut_mask = 16'hA50A; +defparam \Add1~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N30 +cycloneive_lcell_comb \Add1~30 ( +// Equation(s): +// \Add1~30_combout = \Add1~29 $ (cnt_wait[15]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(cnt_wait[15]), + .cin(\Add1~29 ), + .combout(\Add1~30_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~30 .lut_mask = 16'h0FF0; +defparam \Add1~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N6 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[1]~15 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[1]~15_combout = (\fifo_read_inst|baud_cnt [1] & (!\fifo_read_inst|baud_cnt[0]~14 )) # (!\fifo_read_inst|baud_cnt [1] & ((\fifo_read_inst|baud_cnt[0]~14 ) # (GND))) +// \fifo_read_inst|baud_cnt[1]~16 = CARRY((!\fifo_read_inst|baud_cnt[0]~14 ) # (!\fifo_read_inst|baud_cnt [1])) + + .dataa(\fifo_read_inst|baud_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[0]~14 ), + .combout(\fifo_read_inst|baud_cnt[1]~15_combout ), + .cout(\fifo_read_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N12 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[4]~21 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[4]~21_combout = (\fifo_read_inst|baud_cnt [4] & (\fifo_read_inst|baud_cnt[3]~20 $ (GND))) # (!\fifo_read_inst|baud_cnt [4] & (!\fifo_read_inst|baud_cnt[3]~20 & VCC)) +// \fifo_read_inst|baud_cnt[4]~22 = CARRY((\fifo_read_inst|baud_cnt [4] & !\fifo_read_inst|baud_cnt[3]~20 )) + + .dataa(\fifo_read_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[3]~20 ), + .combout(\fifo_read_inst|baud_cnt[4]~21_combout ), + .cout(\fifo_read_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N22 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[9]~31 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[9]~31_combout = (\fifo_read_inst|baud_cnt [9] & (!\fifo_read_inst|baud_cnt[8]~30 )) # (!\fifo_read_inst|baud_cnt [9] & ((\fifo_read_inst|baud_cnt[8]~30 ) # (GND))) +// \fifo_read_inst|baud_cnt[9]~32 = CARRY((!\fifo_read_inst|baud_cnt[8]~30 ) # (!\fifo_read_inst|baud_cnt [9])) + + .dataa(\fifo_read_inst|baud_cnt [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[8]~30 ), + .combout(\fifo_read_inst|baud_cnt[9]~31_combout ), + .cout(\fifo_read_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[9]~31 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N26 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[11]~35 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[11]~35_combout = (\fifo_read_inst|baud_cnt [11] & (!\fifo_read_inst|baud_cnt[10]~34 )) # (!\fifo_read_inst|baud_cnt [11] & ((\fifo_read_inst|baud_cnt[10]~34 ) # (GND))) +// \fifo_read_inst|baud_cnt[11]~36 = CARRY((!\fifo_read_inst|baud_cnt[10]~34 ) # (!\fifo_read_inst|baud_cnt [11])) + + .dataa(\fifo_read_inst|baud_cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[10]~34 ), + .combout(\fifo_read_inst|baud_cnt[11]~35_combout ), + .cout(\fifo_read_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N8 +cycloneive_lcell_comb \data_num[0]~24 ( +// Equation(s): +// \data_num[0]~24_combout = (\uart_rx_inst|po_flag~q & (data_num[0] $ (VCC))) # (!\uart_rx_inst|po_flag~q & (data_num[0] & VCC)) +// \data_num[0]~25 = CARRY((\uart_rx_inst|po_flag~q & data_num[0])) + + .dataa(\uart_rx_inst|po_flag~q ), + .datab(data_num[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_num[0]~24_combout ), + .cout(\data_num[0]~25 )); +// synopsys translate_off +defparam \data_num[0]~24 .lut_mask = 16'h6688; +defparam \data_num[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N10 +cycloneive_lcell_comb \data_num[1]~26 ( +// Equation(s): +// \data_num[1]~26_combout = (data_num[1] & (!\data_num[0]~25 )) # (!data_num[1] & ((\data_num[0]~25 ) # (GND))) +// \data_num[1]~27 = CARRY((!\data_num[0]~25 ) # (!data_num[1])) + + .dataa(data_num[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[0]~25 ), + .combout(\data_num[1]~26_combout ), + .cout(\data_num[1]~27 )); +// synopsys translate_off +defparam \data_num[1]~26 .lut_mask = 16'h5A5F; +defparam \data_num[1]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N12 +cycloneive_lcell_comb \data_num[2]~28 ( +// Equation(s): +// \data_num[2]~28_combout = (data_num[2] & (\data_num[1]~27 $ (GND))) # (!data_num[2] & (!\data_num[1]~27 & VCC)) +// \data_num[2]~29 = CARRY((data_num[2] & !\data_num[1]~27 )) + + .dataa(data_num[2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[1]~27 ), + .combout(\data_num[2]~28_combout ), + .cout(\data_num[2]~29 )); +// synopsys translate_off +defparam \data_num[2]~28 .lut_mask = 16'hA50A; +defparam \data_num[2]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N14 +cycloneive_lcell_comb \data_num[3]~30 ( +// Equation(s): +// \data_num[3]~30_combout = (data_num[3] & (!\data_num[2]~29 )) # (!data_num[3] & ((\data_num[2]~29 ) # (GND))) +// \data_num[3]~31 = CARRY((!\data_num[2]~29 ) # (!data_num[3])) + + .dataa(gnd), + .datab(data_num[3]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[2]~29 ), + .combout(\data_num[3]~30_combout ), + .cout(\data_num[3]~31 )); +// synopsys translate_off +defparam \data_num[3]~30 .lut_mask = 16'h3C3F; +defparam \data_num[3]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N16 +cycloneive_lcell_comb \data_num[4]~32 ( +// Equation(s): +// \data_num[4]~32_combout = (data_num[4] & (\data_num[3]~31 $ (GND))) # (!data_num[4] & (!\data_num[3]~31 & VCC)) +// \data_num[4]~33 = CARRY((data_num[4] & !\data_num[3]~31 )) + + .dataa(gnd), + .datab(data_num[4]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[3]~31 ), + .combout(\data_num[4]~32_combout ), + .cout(\data_num[4]~33 )); +// synopsys translate_off +defparam \data_num[4]~32 .lut_mask = 16'hC30C; +defparam \data_num[4]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N18 +cycloneive_lcell_comb \data_num[5]~34 ( +// Equation(s): +// \data_num[5]~34_combout = (data_num[5] & (!\data_num[4]~33 )) # (!data_num[5] & ((\data_num[4]~33 ) # (GND))) +// \data_num[5]~35 = CARRY((!\data_num[4]~33 ) # (!data_num[5])) + + .dataa(gnd), + .datab(data_num[5]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[4]~33 ), + .combout(\data_num[5]~34_combout ), + .cout(\data_num[5]~35 )); +// synopsys translate_off +defparam \data_num[5]~34 .lut_mask = 16'h3C3F; +defparam \data_num[5]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N20 +cycloneive_lcell_comb \data_num[6]~36 ( +// Equation(s): +// \data_num[6]~36_combout = (data_num[6] & (\data_num[5]~35 $ (GND))) # (!data_num[6] & (!\data_num[5]~35 & VCC)) +// \data_num[6]~37 = CARRY((data_num[6] & !\data_num[5]~35 )) + + .dataa(gnd), + .datab(data_num[6]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[5]~35 ), + .combout(\data_num[6]~36_combout ), + .cout(\data_num[6]~37 )); +// synopsys translate_off +defparam \data_num[6]~36 .lut_mask = 16'hC30C; +defparam \data_num[6]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N22 +cycloneive_lcell_comb \data_num[7]~38 ( +// Equation(s): +// \data_num[7]~38_combout = (data_num[7] & (!\data_num[6]~37 )) # (!data_num[7] & ((\data_num[6]~37 ) # (GND))) +// \data_num[7]~39 = CARRY((!\data_num[6]~37 ) # (!data_num[7])) + + .dataa(data_num[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[6]~37 ), + .combout(\data_num[7]~38_combout ), + .cout(\data_num[7]~39 )); +// synopsys translate_off +defparam \data_num[7]~38 .lut_mask = 16'h5A5F; +defparam \data_num[7]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N24 +cycloneive_lcell_comb \data_num[8]~40 ( +// Equation(s): +// \data_num[8]~40_combout = (data_num[8] & (\data_num[7]~39 $ (GND))) # (!data_num[8] & (!\data_num[7]~39 & VCC)) +// \data_num[8]~41 = CARRY((data_num[8] & !\data_num[7]~39 )) + + .dataa(gnd), + .datab(data_num[8]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[7]~39 ), + .combout(\data_num[8]~40_combout ), + .cout(\data_num[8]~41 )); +// synopsys translate_off +defparam \data_num[8]~40 .lut_mask = 16'hC30C; +defparam \data_num[8]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N26 +cycloneive_lcell_comb \data_num[9]~42 ( +// Equation(s): +// \data_num[9]~42_combout = (data_num[9] & (!\data_num[8]~41 )) # (!data_num[9] & ((\data_num[8]~41 ) # (GND))) +// \data_num[9]~43 = CARRY((!\data_num[8]~41 ) # (!data_num[9])) + + .dataa(data_num[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[8]~41 ), + .combout(\data_num[9]~42_combout ), + .cout(\data_num[9]~43 )); +// synopsys translate_off +defparam \data_num[9]~42 .lut_mask = 16'h5A5F; +defparam \data_num[9]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N28 +cycloneive_lcell_comb \data_num[10]~44 ( +// Equation(s): +// \data_num[10]~44_combout = (data_num[10] & (\data_num[9]~43 $ (GND))) # (!data_num[10] & (!\data_num[9]~43 & VCC)) +// \data_num[10]~45 = CARRY((data_num[10] & !\data_num[9]~43 )) + + .dataa(gnd), + .datab(data_num[10]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[9]~43 ), + .combout(\data_num[10]~44_combout ), + .cout(\data_num[10]~45 )); +// synopsys translate_off +defparam \data_num[10]~44 .lut_mask = 16'hC30C; +defparam \data_num[10]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N30 +cycloneive_lcell_comb \data_num[11]~46 ( +// Equation(s): +// \data_num[11]~46_combout = (data_num[11] & (!\data_num[10]~45 )) # (!data_num[11] & ((\data_num[10]~45 ) # (GND))) +// \data_num[11]~47 = CARRY((!\data_num[10]~45 ) # (!data_num[11])) + + .dataa(data_num[11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[10]~45 ), + .combout(\data_num[11]~46_combout ), + .cout(\data_num[11]~47 )); +// synopsys translate_off +defparam \data_num[11]~46 .lut_mask = 16'h5A5F; +defparam \data_num[11]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N0 +cycloneive_lcell_comb \data_num[12]~48 ( +// Equation(s): +// \data_num[12]~48_combout = (data_num[12] & (\data_num[11]~47 $ (GND))) # (!data_num[12] & (!\data_num[11]~47 & VCC)) +// \data_num[12]~49 = CARRY((data_num[12] & !\data_num[11]~47 )) + + .dataa(gnd), + .datab(data_num[12]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[11]~47 ), + .combout(\data_num[12]~48_combout ), + .cout(\data_num[12]~49 )); +// synopsys translate_off +defparam \data_num[12]~48 .lut_mask = 16'hC30C; +defparam \data_num[12]~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N2 +cycloneive_lcell_comb \data_num[13]~50 ( +// Equation(s): +// \data_num[13]~50_combout = (data_num[13] & (!\data_num[12]~49 )) # (!data_num[13] & ((\data_num[12]~49 ) # (GND))) +// \data_num[13]~51 = CARRY((!\data_num[12]~49 ) # (!data_num[13])) + + .dataa(gnd), + .datab(data_num[13]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[12]~49 ), + .combout(\data_num[13]~50_combout ), + .cout(\data_num[13]~51 )); +// synopsys translate_off +defparam \data_num[13]~50 .lut_mask = 16'h3C3F; +defparam \data_num[13]~50 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N4 +cycloneive_lcell_comb \data_num[14]~52 ( +// Equation(s): +// \data_num[14]~52_combout = (data_num[14] & (\data_num[13]~51 $ (GND))) # (!data_num[14] & (!\data_num[13]~51 & VCC)) +// \data_num[14]~53 = CARRY((data_num[14] & !\data_num[13]~51 )) + + .dataa(gnd), + .datab(data_num[14]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[13]~51 ), + .combout(\data_num[14]~52_combout ), + .cout(\data_num[14]~53 )); +// synopsys translate_off +defparam \data_num[14]~52 .lut_mask = 16'hC30C; +defparam \data_num[14]~52 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N6 +cycloneive_lcell_comb \data_num[15]~54 ( +// Equation(s): +// \data_num[15]~54_combout = (data_num[15] & (!\data_num[14]~53 )) # (!data_num[15] & ((\data_num[14]~53 ) # (GND))) +// \data_num[15]~55 = CARRY((!\data_num[14]~53 ) # (!data_num[15])) + + .dataa(data_num[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[14]~53 ), + .combout(\data_num[15]~54_combout ), + .cout(\data_num[15]~55 )); +// synopsys translate_off +defparam \data_num[15]~54 .lut_mask = 16'h5A5F; +defparam \data_num[15]~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N8 +cycloneive_lcell_comb \data_num[16]~56 ( +// Equation(s): +// \data_num[16]~56_combout = (data_num[16] & (\data_num[15]~55 $ (GND))) # (!data_num[16] & (!\data_num[15]~55 & VCC)) +// \data_num[16]~57 = CARRY((data_num[16] & !\data_num[15]~55 )) + + .dataa(gnd), + .datab(data_num[16]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[15]~55 ), + .combout(\data_num[16]~56_combout ), + .cout(\data_num[16]~57 )); +// synopsys translate_off +defparam \data_num[16]~56 .lut_mask = 16'hC30C; +defparam \data_num[16]~56 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N10 +cycloneive_lcell_comb \data_num[17]~58 ( +// Equation(s): +// \data_num[17]~58_combout = (data_num[17] & (!\data_num[16]~57 )) # (!data_num[17] & ((\data_num[16]~57 ) # (GND))) +// \data_num[17]~59 = CARRY((!\data_num[16]~57 ) # (!data_num[17])) + + .dataa(data_num[17]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[16]~57 ), + .combout(\data_num[17]~58_combout ), + .cout(\data_num[17]~59 )); +// synopsys translate_off +defparam \data_num[17]~58 .lut_mask = 16'h5A5F; +defparam \data_num[17]~58 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N12 +cycloneive_lcell_comb \data_num[18]~60 ( +// Equation(s): +// \data_num[18]~60_combout = (data_num[18] & (\data_num[17]~59 $ (GND))) # (!data_num[18] & (!\data_num[17]~59 & VCC)) +// \data_num[18]~61 = CARRY((data_num[18] & !\data_num[17]~59 )) + + .dataa(data_num[18]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[17]~59 ), + .combout(\data_num[18]~60_combout ), + .cout(\data_num[18]~61 )); +// synopsys translate_off +defparam \data_num[18]~60 .lut_mask = 16'hA50A; +defparam \data_num[18]~60 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N14 +cycloneive_lcell_comb \data_num[19]~62 ( +// Equation(s): +// \data_num[19]~62_combout = (data_num[19] & (!\data_num[18]~61 )) # (!data_num[19] & ((\data_num[18]~61 ) # (GND))) +// \data_num[19]~63 = CARRY((!\data_num[18]~61 ) # (!data_num[19])) + + .dataa(gnd), + .datab(data_num[19]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[18]~61 ), + .combout(\data_num[19]~62_combout ), + .cout(\data_num[19]~63 )); +// synopsys translate_off +defparam \data_num[19]~62 .lut_mask = 16'h3C3F; +defparam \data_num[19]~62 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N16 +cycloneive_lcell_comb \data_num[20]~64 ( +// Equation(s): +// \data_num[20]~64_combout = (data_num[20] & (\data_num[19]~63 $ (GND))) # (!data_num[20] & (!\data_num[19]~63 & VCC)) +// \data_num[20]~65 = CARRY((data_num[20] & !\data_num[19]~63 )) + + .dataa(gnd), + .datab(data_num[20]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[19]~63 ), + .combout(\data_num[20]~64_combout ), + .cout(\data_num[20]~65 )); +// synopsys translate_off +defparam \data_num[20]~64 .lut_mask = 16'hC30C; +defparam \data_num[20]~64 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N18 +cycloneive_lcell_comb \data_num[21]~66 ( +// Equation(s): +// \data_num[21]~66_combout = (data_num[21] & (!\data_num[20]~65 )) # (!data_num[21] & ((\data_num[20]~65 ) # (GND))) +// \data_num[21]~67 = CARRY((!\data_num[20]~65 ) # (!data_num[21])) + + .dataa(gnd), + .datab(data_num[21]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[20]~65 ), + .combout(\data_num[21]~66_combout ), + .cout(\data_num[21]~67 )); +// synopsys translate_off +defparam \data_num[21]~66 .lut_mask = 16'h3C3F; +defparam \data_num[21]~66 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N20 +cycloneive_lcell_comb \data_num[22]~68 ( +// Equation(s): +// \data_num[22]~68_combout = (data_num[22] & (\data_num[21]~67 $ (GND))) # (!data_num[22] & (!\data_num[21]~67 & VCC)) +// \data_num[22]~69 = CARRY((data_num[22] & !\data_num[21]~67 )) + + .dataa(gnd), + .datab(data_num[22]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[21]~67 ), + .combout(\data_num[22]~68_combout ), + .cout(\data_num[22]~69 )); +// synopsys translate_off +defparam \data_num[22]~68 .lut_mask = 16'hC30C; +defparam \data_num[22]~68 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N22 +cycloneive_lcell_comb \data_num[23]~70 ( +// Equation(s): +// \data_num[23]~70_combout = data_num[23] $ (\data_num[22]~69 ) + + .dataa(data_num[23]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_num[22]~69 ), + .combout(\data_num[23]~70_combout ), + .cout()); +// synopsys translate_off +defparam \data_num[23]~70 .lut_mask = 16'h5A5A; +defparam \data_num[23]~70 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y26_N3 +dffeas \fifo_read_inst|cnt_read[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[1]~12_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N7 +dffeas \fifo_read_inst|cnt_read[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[3]~16_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N1 +dffeas \fifo_read_inst|cnt_read[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[0]~10_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N5 +dffeas \fifo_read_inst|cnt_read[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[2]~14_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N9 +dffeas \fifo_read_inst|cnt_read[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[4]~18_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N11 +dffeas \fifo_read_inst|cnt_read[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[5]~20_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N13 +dffeas \fifo_read_inst|cnt_read[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[6]~22_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N15 +dffeas \fifo_read_inst|cnt_read[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[7]~24_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N17 +dffeas \fifo_read_inst|cnt_read[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[8]~26_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N19 +dffeas \fifo_read_inst|cnt_read[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[9]~28_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N24 +cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( +// Equation(s): +// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_cnt [0] & (\uart_rx_inst|bit_flag~q $ (VCC))) # (!\uart_rx_inst|bit_cnt [0] & (\uart_rx_inst|bit_flag~q & VCC)) +// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_cnt [0] & \uart_rx_inst|bit_flag~q )) + + .dataa(\uart_rx_inst|bit_cnt [0]), + .datab(\uart_rx_inst|bit_flag~q ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|Add1~0_combout ), + .cout(\uart_rx_inst|Add1~1 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; +defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N28 +cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( +// Equation(s): +// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) +// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~3 ), + .combout(\uart_rx_inst|Add1~4_combout ), + .cout(\uart_rx_inst|Add1~5 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N30 +cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( +// Equation(s): +// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|Add1~5 $ (\uart_rx_inst|bit_cnt [3]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(\uart_rx_inst|Add1~5 ), + .combout(\uart_rx_inst|Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h0FF0; +defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N11 +dffeas \uart_rx_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N0 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[0]~10 ( +// Equation(s): +// \fifo_read_inst|cnt_read[0]~10_combout = (\fifo_read_inst|rd_en~q & (\fifo_read_inst|cnt_read [0] $ (VCC))) # (!\fifo_read_inst|rd_en~q & (\fifo_read_inst|cnt_read [0] & VCC)) +// \fifo_read_inst|cnt_read[0]~11 = CARRY((\fifo_read_inst|rd_en~q & \fifo_read_inst|cnt_read [0])) + + .dataa(\fifo_read_inst|rd_en~q ), + .datab(\fifo_read_inst|cnt_read [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|cnt_read[0]~10_combout ), + .cout(\fifo_read_inst|cnt_read[0]~11 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[0]~10 .lut_mask = 16'h6688; +defparam \fifo_read_inst|cnt_read[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N2 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[1]~12 ( +// Equation(s): +// \fifo_read_inst|cnt_read[1]~12_combout = (\fifo_read_inst|cnt_read [1] & (!\fifo_read_inst|cnt_read[0]~11 )) # (!\fifo_read_inst|cnt_read [1] & ((\fifo_read_inst|cnt_read[0]~11 ) # (GND))) +// \fifo_read_inst|cnt_read[1]~13 = CARRY((!\fifo_read_inst|cnt_read[0]~11 ) # (!\fifo_read_inst|cnt_read [1])) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [1]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[0]~11 ), + .combout(\fifo_read_inst|cnt_read[1]~12_combout ), + .cout(\fifo_read_inst|cnt_read[1]~13 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[1]~12 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|cnt_read[1]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N4 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[2]~14 ( +// Equation(s): +// \fifo_read_inst|cnt_read[2]~14_combout = (\fifo_read_inst|cnt_read [2] & (\fifo_read_inst|cnt_read[1]~13 $ (GND))) # (!\fifo_read_inst|cnt_read [2] & (!\fifo_read_inst|cnt_read[1]~13 & VCC)) +// \fifo_read_inst|cnt_read[2]~15 = CARRY((\fifo_read_inst|cnt_read [2] & !\fifo_read_inst|cnt_read[1]~13 )) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [2]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[1]~13 ), + .combout(\fifo_read_inst|cnt_read[2]~14_combout ), + .cout(\fifo_read_inst|cnt_read[2]~15 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[2]~14 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|cnt_read[2]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N6 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[3]~16 ( +// Equation(s): +// \fifo_read_inst|cnt_read[3]~16_combout = (\fifo_read_inst|cnt_read [3] & (!\fifo_read_inst|cnt_read[2]~15 )) # (!\fifo_read_inst|cnt_read [3] & ((\fifo_read_inst|cnt_read[2]~15 ) # (GND))) +// \fifo_read_inst|cnt_read[3]~17 = CARRY((!\fifo_read_inst|cnt_read[2]~15 ) # (!\fifo_read_inst|cnt_read [3])) + + .dataa(\fifo_read_inst|cnt_read [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[2]~15 ), + .combout(\fifo_read_inst|cnt_read[3]~16_combout ), + .cout(\fifo_read_inst|cnt_read[3]~17 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[3]~16 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|cnt_read[3]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N8 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[4]~18 ( +// Equation(s): +// \fifo_read_inst|cnt_read[4]~18_combout = (\fifo_read_inst|cnt_read [4] & (\fifo_read_inst|cnt_read[3]~17 $ (GND))) # (!\fifo_read_inst|cnt_read [4] & (!\fifo_read_inst|cnt_read[3]~17 & VCC)) +// \fifo_read_inst|cnt_read[4]~19 = CARRY((\fifo_read_inst|cnt_read [4] & !\fifo_read_inst|cnt_read[3]~17 )) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [4]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[3]~17 ), + .combout(\fifo_read_inst|cnt_read[4]~18_combout ), + .cout(\fifo_read_inst|cnt_read[4]~19 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[4]~18 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|cnt_read[4]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N10 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[5]~20 ( +// Equation(s): +// \fifo_read_inst|cnt_read[5]~20_combout = (\fifo_read_inst|cnt_read [5] & (!\fifo_read_inst|cnt_read[4]~19 )) # (!\fifo_read_inst|cnt_read [5] & ((\fifo_read_inst|cnt_read[4]~19 ) # (GND))) +// \fifo_read_inst|cnt_read[5]~21 = CARRY((!\fifo_read_inst|cnt_read[4]~19 ) # (!\fifo_read_inst|cnt_read [5])) + + .dataa(\fifo_read_inst|cnt_read [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[4]~19 ), + .combout(\fifo_read_inst|cnt_read[5]~20_combout ), + .cout(\fifo_read_inst|cnt_read[5]~21 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[5]~20 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|cnt_read[5]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N12 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[6]~22 ( +// Equation(s): +// \fifo_read_inst|cnt_read[6]~22_combout = (\fifo_read_inst|cnt_read [6] & (\fifo_read_inst|cnt_read[5]~21 $ (GND))) # (!\fifo_read_inst|cnt_read [6] & (!\fifo_read_inst|cnt_read[5]~21 & VCC)) +// \fifo_read_inst|cnt_read[6]~23 = CARRY((\fifo_read_inst|cnt_read [6] & !\fifo_read_inst|cnt_read[5]~21 )) + + .dataa(\fifo_read_inst|cnt_read [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[5]~21 ), + .combout(\fifo_read_inst|cnt_read[6]~22_combout ), + .cout(\fifo_read_inst|cnt_read[6]~23 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[6]~22 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|cnt_read[6]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N14 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[7]~24 ( +// Equation(s): +// \fifo_read_inst|cnt_read[7]~24_combout = (\fifo_read_inst|cnt_read [7] & (!\fifo_read_inst|cnt_read[6]~23 )) # (!\fifo_read_inst|cnt_read [7] & ((\fifo_read_inst|cnt_read[6]~23 ) # (GND))) +// \fifo_read_inst|cnt_read[7]~25 = CARRY((!\fifo_read_inst|cnt_read[6]~23 ) # (!\fifo_read_inst|cnt_read [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[6]~23 ), + .combout(\fifo_read_inst|cnt_read[7]~24_combout ), + .cout(\fifo_read_inst|cnt_read[7]~25 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[7]~24 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|cnt_read[7]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N16 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[8]~26 ( +// Equation(s): +// \fifo_read_inst|cnt_read[8]~26_combout = (\fifo_read_inst|cnt_read [8] & (\fifo_read_inst|cnt_read[7]~25 $ (GND))) # (!\fifo_read_inst|cnt_read [8] & (!\fifo_read_inst|cnt_read[7]~25 & VCC)) +// \fifo_read_inst|cnt_read[8]~27 = CARRY((\fifo_read_inst|cnt_read [8] & !\fifo_read_inst|cnt_read[7]~25 )) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [8]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[7]~25 ), + .combout(\fifo_read_inst|cnt_read[8]~26_combout ), + .cout(\fifo_read_inst|cnt_read[8]~27 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[8]~26 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|cnt_read[8]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N18 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[9]~28 ( +// Equation(s): +// \fifo_read_inst|cnt_read[9]~28_combout = \fifo_read_inst|cnt_read [9] $ (\fifo_read_inst|cnt_read[8]~27 ) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [9]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|cnt_read[8]~27 ), + .combout(\fifo_read_inst|cnt_read[9]~28_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[9]~28 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|cnt_read[9]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N10 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) +// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[3]~20 ), + .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_rx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X22_Y22_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y22_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y22_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [0])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [0]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0 .lut_mask = 16'h8C9D; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N13 +dffeas \uart_tx_inst|bit_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[0]~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( +// Equation(s): +// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b +// [4])) # (!\uart_tx_inst|bit_cnt [0] & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [3]))))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [4]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [3]), + .datad(\uart_tx_inst|bit_cnt [0]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hEE30; +defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N8 +cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( +// Equation(s): +// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|Mux0~0_combout & (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [6]) # (!\uart_tx_inst|bit_cnt [1])))) # (!\uart_tx_inst|Mux0~0_combout & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [5] & ((\uart_tx_inst|bit_cnt [1])))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [5]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [6]), + .datac(\uart_tx_inst|Mux0~0_combout ), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hCAF0; +defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \uart_tx_inst|tx~0 ( +// Equation(s): +// \uart_tx_inst|tx~0_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [2]))) # (!\uart_tx_inst|bit_cnt [1] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [0])))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [0]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~0 .lut_mask = 16'hA088; +defparam \uart_tx_inst|tx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \uart_tx_inst|tx~1 ( +// Equation(s): +// \uart_tx_inst|tx~1_combout = (\uart_tx_inst|tx~0_combout ) # ((!\uart_tx_inst|bit_cnt [0] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [1] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|tx~0_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [1]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~1 .lut_mask = 16'hDCCC; +defparam \uart_tx_inst|tx~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \uart_tx_inst|tx~2 ( +// Equation(s): +// \uart_tx_inst|tx~2_combout = (\uart_tx_inst|bit_flag~q & ((\uart_tx_inst|bit_cnt [2] & (\uart_tx_inst|Mux0~1_combout )) # (!\uart_tx_inst|bit_cnt [2] & ((\uart_tx_inst|tx~1_combout ))))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\uart_tx_inst|Mux0~1_combout ), + .datad(\uart_tx_inst|tx~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~2 .lut_mask = 16'hA280; +defparam \uart_tx_inst|tx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N27 +dffeas \uart_tx_inst|bit_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[3]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y21_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0 .lut_mask = 16'hFFAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0 .lut_mask = 16'h3111; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ) # (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1 .lut_mask = 16'hAFEF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0 .lut_mask = 16'h0CAE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( +// Equation(s): +// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(gnd), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h5AF0; +defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( +// Equation(s): +// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [0] & (\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|bit_cnt [1])))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h78F0; +defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~4 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[3]~4_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [3]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) + + .dataa(\uart_tx_inst|Add1~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3]~4 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0 .lut_mask = 16'h0400; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y22_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y22_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y20_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y20_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N29 +dffeas read_valid( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\read_valid~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\read_valid~q ), + .prn(vcc)); +// synopsys translate_off +defparam read_valid.is_wysiwyg = "true"; +defparam read_valid.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0 .lut_mask = 16'h000F; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout = (\read_valid~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & ((\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout )))) + + .dataa(\read_valid~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1 .lut_mask = 16'h8088; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0 .lut_mask = 16'hFAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[13] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N12 +cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( +// Equation(s): +// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [12] & \uart_tx_inst|baud_cnt [10]) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(gnd), + .datad(\uart_tx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hCC00; +defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N25 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N2 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout = (\fifo_read_inst|read_en_dly~q & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9] & !\fifo_read_inst|rd_en~q ))) + + .dataa(\fifo_read_inst|read_en_dly~q ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .lut_mask = 16'h0080; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N23 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N21 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N19 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N17 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N0 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] & +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .lut_mask = 16'h8000; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N15 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N11 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N26 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] & +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .lut_mask = 16'h8000; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] & +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .lut_mask = 16'h8000; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N13 +dffeas \fifo_read_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|Add2~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N28 +cycloneive_lcell_comb \fifo_read_inst|Equal1~0 ( +// Equation(s): +// \fifo_read_inst|Equal1~0_combout = (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] & (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .cin(gnd), + .combout(\fifo_read_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal1~0 .lut_mask = 16'h0001; +defparam \fifo_read_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N2 +cycloneive_lcell_comb \fifo_read_inst|Equal1~1 ( +// Equation(s): +// \fifo_read_inst|Equal1~1_combout = (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] & (\fifo_read_inst|Equal1~0_combout & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] & !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .datab(\fifo_read_inst|Equal1~0_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .cin(gnd), + .combout(\fifo_read_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal1~1 .lut_mask = 16'h0004; +defparam \fifo_read_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .lut_mask = 16'h50F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y23_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5 .lut_mask = 16'h9966; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y20_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2 .lut_mask = 16'h9696; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y26_N25 +dffeas \cnt_wait[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[15]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[15]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[15] .is_wysiwyg = "true"; +defparam \cnt_wait[15] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N27 +dffeas \cnt_wait[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[14]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[14]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[14] .is_wysiwyg = "true"; +defparam \cnt_wait[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N21 +dffeas \cnt_wait[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[13]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[13]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[13] .is_wysiwyg = "true"; +defparam \cnt_wait[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N23 +dffeas \cnt_wait[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[12]~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[12]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[12] .is_wysiwyg = "true"; +defparam \cnt_wait[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N8 +cycloneive_lcell_comb \Equal0~0 ( +// Equation(s): +// \Equal0~0_combout = (!cnt_wait[12] & (!cnt_wait[15] & (!cnt_wait[14] & !cnt_wait[13]))) + + .dataa(cnt_wait[12]), + .datab(cnt_wait[15]), + .datac(cnt_wait[14]), + .datad(cnt_wait[13]), + .cin(gnd), + .combout(\Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~0 .lut_mask = 16'h0001; +defparam \Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y26_N23 +dffeas \cnt_wait[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[9]~6_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[9]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[9] .is_wysiwyg = "true"; +defparam \cnt_wait[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N9 +dffeas \cnt_wait[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[11]~7_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[11]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[11] .is_wysiwyg = "true"; +defparam \cnt_wait[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N11 +dffeas \cnt_wait[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[10]~8_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[10]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[10] .is_wysiwyg = "true"; +defparam \cnt_wait[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N5 +dffeas \cnt_wait[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[8]~9_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[8]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[8] .is_wysiwyg = "true"; +defparam \cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N14 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (!cnt_wait[10] & (!cnt_wait[8] & (cnt_wait[9] & !cnt_wait[11]))) + + .dataa(cnt_wait[10]), + .datab(cnt_wait[8]), + .datac(cnt_wait[9]), + .datad(cnt_wait[11]), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0010; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y26_N3 +dffeas \cnt_wait[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[7]~10_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[7]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[7] .is_wysiwyg = "true"; +defparam \cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N13 +dffeas \cnt_wait[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[6]~11_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[6]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[6] .is_wysiwyg = "true"; +defparam \cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N15 +dffeas \cnt_wait[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[5]~12_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[5]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[5] .is_wysiwyg = "true"; +defparam \cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N17 +dffeas \cnt_wait[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[4]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[4]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[4] .is_wysiwyg = "true"; +defparam \cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N10 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (cnt_wait[6] & (cnt_wait[7] & (cnt_wait[5] & !cnt_wait[4]))) + + .dataa(cnt_wait[6]), + .datab(cnt_wait[7]), + .datac(cnt_wait[5]), + .datad(cnt_wait[4]), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0080; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y26_N5 +dffeas \cnt_wait[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[3]~14_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[3]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[3] .is_wysiwyg = "true"; +defparam \cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N7 +dffeas \cnt_wait[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[2]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[2]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[2] .is_wysiwyg = "true"; +defparam \cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N1 +dffeas \cnt_wait[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[1]~16_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[1]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[1] .is_wysiwyg = "true"; +defparam \cnt_wait[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N19 +dffeas \cnt_wait[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[0]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[0]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[0] .is_wysiwyg = "true"; +defparam \cnt_wait[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N28 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (!cnt_wait[0] & (cnt_wait[1] & (cnt_wait[3] & cnt_wait[2]))) + + .dataa(cnt_wait[0]), + .datab(cnt_wait[1]), + .datac(cnt_wait[3]), + .datad(cnt_wait[2]), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h4000; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N30 +cycloneive_lcell_comb \Equal0~4 ( +// Equation(s): +// \Equal0~4_combout = (\Equal0~2_combout & (\Equal0~3_combout & (\Equal0~0_combout & \Equal0~1_combout ))) + + .dataa(\Equal0~2_combout ), + .datab(\Equal0~3_combout ), + .datac(\Equal0~0_combout ), + .datad(\Equal0~1_combout ), + .cin(gnd), + .combout(\Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~4 .lut_mask = 16'h8000; +defparam \Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N16 +cycloneive_lcell_comb \read_valid~0 ( +// Equation(s): +// \read_valid~0_combout = (\Equal0~4_combout ) # ((\read_valid~q & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ) # (!\Equal2~1_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\Equal0~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .datad(\read_valid~q ), + .cin(gnd), + .combout(\read_valid~0_combout ), + .cout()); +// synopsys translate_off +defparam \read_valid~0 .lut_mask = 16'hFDCC; +defparam \read_valid~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N28 +cycloneive_lcell_comb \read_valid~1 ( +// Equation(s): +// \read_valid~1_combout = (\read_valid~0_combout ) # ((\read_valid~q & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ) # (!\Equal2~0_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .datab(\Equal2~0_combout ), + .datac(\read_valid~q ), + .datad(\read_valid~0_combout ), + .cin(gnd), + .combout(\read_valid~1_combout ), + .cout()); +// synopsys translate_off +defparam \read_valid~1 .lut_mask = 16'hFFB0; +defparam \read_valid~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0 .lut_mask = 16'hECFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk +// [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3] $ (((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0 .lut_mask = 16'h6AAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2 .lut_mask = 16'hC0C0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N10 +cycloneive_lcell_comb \fifo_read_inst|Equal1~2 ( +// Equation(s): +// \fifo_read_inst|Equal1~2_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] & \fifo_read_inst|Equal1~1_combout )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datac(gnd), + .datad(\fifo_read_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\fifo_read_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal1~2 .lut_mask = 16'h2200; +defparam \fifo_read_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N2 +cycloneive_lcell_comb \fifo_read_inst|Equal5~1 ( +// Equation(s): +// \fifo_read_inst|Equal5~1_combout = (\fifo_read_inst|baud_cnt [11] & (!\fifo_read_inst|baud_cnt [10] & (\fifo_read_inst|baud_cnt [9] & !\fifo_read_inst|baud_cnt [6]))) + + .dataa(\fifo_read_inst|baud_cnt [11]), + .datab(\fifo_read_inst|baud_cnt [10]), + .datac(\fifo_read_inst|baud_cnt [9]), + .datad(\fifo_read_inst|baud_cnt [6]), + .cin(gnd), + .combout(\fifo_read_inst|Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal5~1 .lut_mask = 16'h0020; +defparam \fifo_read_inst|Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h4182; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'hF000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'hC000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout +// )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8 .lut_mask = 16'hCA0A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'h4812; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'h8008; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h2814; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'h8200; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout )) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'hF5A0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h2814; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'hE0C2; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h0004; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N0 +cycloneive_lcell_comb \Equal1~0 ( +// Equation(s): +// \Equal1~0_combout = (data_num[2]) # (((data_num[0]) # (!data_num[1])) # (!data_num[3])) + + .dataa(data_num[2]), + .datab(data_num[3]), + .datac(data_num[0]), + .datad(data_num[1]), + .cin(gnd), + .combout(\Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~0 .lut_mask = 16'hFBFF; +defparam \Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N2 +cycloneive_lcell_comb \Equal1~1 ( +// Equation(s): +// \Equal1~1_combout = (data_num[6]) # ((data_num[5]) # ((data_num[7]) # (data_num[4]))) + + .dataa(data_num[6]), + .datab(data_num[5]), + .datac(data_num[7]), + .datad(data_num[4]), + .cin(gnd), + .combout(\Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~1 .lut_mask = 16'hFFFE; +defparam \Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N4 +cycloneive_lcell_comb \Equal1~2 ( +// Equation(s): +// \Equal1~2_combout = (data_num[11]) # ((data_num[10]) # ((data_num[9]) # (data_num[8]))) + + .dataa(data_num[11]), + .datab(data_num[10]), + .datac(data_num[9]), + .datad(data_num[8]), + .cin(gnd), + .combout(\Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~2 .lut_mask = 16'hFFFE; +defparam \Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N24 +cycloneive_lcell_comb \Equal1~3 ( +// Equation(s): +// \Equal1~3_combout = (data_num[15]) # ((data_num[13]) # ((data_num[14]) # (data_num[12]))) + + .dataa(data_num[15]), + .datab(data_num[13]), + .datac(data_num[14]), + .datad(data_num[12]), + .cin(gnd), + .combout(\Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~3 .lut_mask = 16'hFFFE; +defparam \Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N6 +cycloneive_lcell_comb \Equal1~4 ( +// Equation(s): +// \Equal1~4_combout = (\Equal1~3_combout ) # ((\Equal1~1_combout ) # ((\Equal1~2_combout ) # (\Equal1~0_combout ))) + + .dataa(\Equal1~3_combout ), + .datab(\Equal1~1_combout ), + .datac(\Equal1~2_combout ), + .datad(\Equal1~0_combout ), + .cin(gnd), + .combout(\Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~4 .lut_mask = 16'hFFFE; +defparam \Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N26 +cycloneive_lcell_comb \Equal1~5 ( +// Equation(s): +// \Equal1~5_combout = (data_num[18]) # ((data_num[19]) # ((data_num[16]) # (data_num[17]))) + + .dataa(data_num[18]), + .datab(data_num[19]), + .datac(data_num[16]), + .datad(data_num[17]), + .cin(gnd), + .combout(\Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~5 .lut_mask = 16'hFFFE; +defparam \Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N28 +cycloneive_lcell_comb \Equal1~6 ( +// Equation(s): +// \Equal1~6_combout = (data_num[22]) # ((data_num[21]) # ((data_num[23]) # (data_num[20]))) + + .dataa(data_num[22]), + .datab(data_num[21]), + .datac(data_num[23]), + .datad(data_num[20]), + .cin(gnd), + .combout(\Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~6 .lut_mask = 16'hFFFE; +defparam \Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N18 +cycloneive_lcell_comb \cnt_wait[8]~0 ( +// Equation(s): +// \cnt_wait[8]~0_combout = (!\Equal0~4_combout & ((\Equal1~4_combout ) # ((\Equal1~5_combout ) # (\Equal1~6_combout )))) + + .dataa(\Equal1~4_combout ), + .datab(\Equal0~4_combout ), + .datac(\Equal1~5_combout ), + .datad(\Equal1~6_combout ), + .cin(gnd), + .combout(\cnt_wait[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[8]~0 .lut_mask = 16'h3332; +defparam \cnt_wait[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N12 +cycloneive_lcell_comb \cnt_wait[15]~1 ( +// Equation(s): +// \cnt_wait[15]~1_combout = (\Equal1~4_combout ) # ((\Equal0~4_combout ) # ((\Equal1~5_combout ) # (\Equal1~6_combout ))) + + .dataa(\Equal1~4_combout ), + .datab(\Equal0~4_combout ), + .datac(\Equal1~5_combout ), + .datad(\Equal1~6_combout ), + .cin(gnd), + .combout(\cnt_wait[15]~1_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[15]~1 .lut_mask = 16'hFFFE; +defparam \cnt_wait[15]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N24 +cycloneive_lcell_comb \cnt_wait[15]~2 ( +// Equation(s): +// \cnt_wait[15]~2_combout = (\Add1~30_combout & (((\cnt_wait[8]~0_combout & cnt_wait[15])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~30_combout & (\cnt_wait[8]~0_combout & (cnt_wait[15]))) + + .dataa(\Add1~30_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[15]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[15]~2_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[15]~2 .lut_mask = 16'hC0EA; +defparam \cnt_wait[15]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N26 +cycloneive_lcell_comb \cnt_wait[14]~3 ( +// Equation(s): +// \cnt_wait[14]~3_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[14] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~28_combout ) # ((cnt_wait[14] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~28_combout ), + .datac(cnt_wait[14]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[14]~3_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[14]~3 .lut_mask = 16'hF444; +defparam \cnt_wait[14]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N20 +cycloneive_lcell_comb \cnt_wait[13]~4 ( +// Equation(s): +// \cnt_wait[13]~4_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[13] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~26_combout ) # ((cnt_wait[13] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~26_combout ), + .datac(cnt_wait[13]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[13]~4_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[13]~4 .lut_mask = 16'hF444; +defparam \cnt_wait[13]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N22 +cycloneive_lcell_comb \cnt_wait[12]~5 ( +// Equation(s): +// \cnt_wait[12]~5_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[12] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~24_combout ) # ((cnt_wait[12] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~24_combout ), + .datac(cnt_wait[12]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[12]~5_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[12]~5 .lut_mask = 16'hF444; +defparam \cnt_wait[12]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N22 +cycloneive_lcell_comb \cnt_wait[9]~6 ( +// Equation(s): +// \cnt_wait[9]~6_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[9] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~18_combout ) # ((cnt_wait[9] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~18_combout ), + .datac(cnt_wait[9]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[9]~6_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[9]~6 .lut_mask = 16'hF444; +defparam \cnt_wait[9]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N8 +cycloneive_lcell_comb \cnt_wait[11]~7 ( +// Equation(s): +// \cnt_wait[11]~7_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[11] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~22_combout ) # ((cnt_wait[11] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~22_combout ), + .datac(cnt_wait[11]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[11]~7_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[11]~7 .lut_mask = 16'hF444; +defparam \cnt_wait[11]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N10 +cycloneive_lcell_comb \cnt_wait[10]~8 ( +// Equation(s): +// \cnt_wait[10]~8_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[10] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~20_combout ) # ((cnt_wait[10] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~20_combout ), + .datac(cnt_wait[10]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[10]~8_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[10]~8 .lut_mask = 16'hF444; +defparam \cnt_wait[10]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N4 +cycloneive_lcell_comb \cnt_wait[8]~9 ( +// Equation(s): +// \cnt_wait[8]~9_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[8] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~16_combout ) # ((cnt_wait[8] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~16_combout ), + .datac(cnt_wait[8]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[8]~9_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[8]~9 .lut_mask = 16'hF444; +defparam \cnt_wait[8]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N2 +cycloneive_lcell_comb \cnt_wait[7]~10 ( +// Equation(s): +// \cnt_wait[7]~10_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[7] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~14_combout ) # ((cnt_wait[7] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~14_combout ), + .datac(cnt_wait[7]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[7]~10_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[7]~10 .lut_mask = 16'hF444; +defparam \cnt_wait[7]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N12 +cycloneive_lcell_comb \cnt_wait[6]~11 ( +// Equation(s): +// \cnt_wait[6]~11_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[6] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~12_combout ) # ((cnt_wait[6] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~12_combout ), + .datac(cnt_wait[6]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[6]~11_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[6]~11 .lut_mask = 16'hF444; +defparam \cnt_wait[6]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N14 +cycloneive_lcell_comb \cnt_wait[5]~12 ( +// Equation(s): +// \cnt_wait[5]~12_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[5] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~10_combout ) # ((cnt_wait[5] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~10_combout ), + .datac(cnt_wait[5]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[5]~12_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[5]~12 .lut_mask = 16'hF444; +defparam \cnt_wait[5]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N16 +cycloneive_lcell_comb \cnt_wait[4]~13 ( +// Equation(s): +// \cnt_wait[4]~13_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[4] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~8_combout ) # ((cnt_wait[4] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~8_combout ), + .datac(cnt_wait[4]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[4]~13 .lut_mask = 16'hF444; +defparam \cnt_wait[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N4 +cycloneive_lcell_comb \cnt_wait[3]~14 ( +// Equation(s): +// \cnt_wait[3]~14_combout = (\Add1~6_combout & (((\cnt_wait[8]~0_combout & cnt_wait[3])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~6_combout & (\cnt_wait[8]~0_combout & (cnt_wait[3]))) + + .dataa(\Add1~6_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[3]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[3]~14 .lut_mask = 16'hC0EA; +defparam \cnt_wait[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N6 +cycloneive_lcell_comb \cnt_wait[2]~15 ( +// Equation(s): +// \cnt_wait[2]~15_combout = (\Add1~4_combout & (((\cnt_wait[8]~0_combout & cnt_wait[2])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~4_combout & (\cnt_wait[8]~0_combout & (cnt_wait[2]))) + + .dataa(\Add1~4_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[2]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[2]~15_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[2]~15 .lut_mask = 16'hC0EA; +defparam \cnt_wait[2]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N0 +cycloneive_lcell_comb \cnt_wait[1]~16 ( +// Equation(s): +// \cnt_wait[1]~16_combout = (\Add1~2_combout & (((\cnt_wait[8]~0_combout & cnt_wait[1])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~2_combout & (\cnt_wait[8]~0_combout & (cnt_wait[1]))) + + .dataa(\Add1~2_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[1]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[1]~16 .lut_mask = 16'hC0EA; +defparam \cnt_wait[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N18 +cycloneive_lcell_comb \cnt_wait[0]~17 ( +// Equation(s): +// \cnt_wait[0]~17_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[0] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~0_combout ) # ((cnt_wait[0] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~0_combout ), + .datac(cnt_wait[0]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[0]~17 .lut_mask = 16'hF444; +defparam \cnt_wait[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h4812; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h0084; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ) # +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout +// & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'hAAEA; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h4812; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h4182; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout +// )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'hB830; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h0004; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N1 +dffeas \fifo_read_inst|rd_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|rd_flag~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|rd_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|rd_flag .is_wysiwyg = "true"; +defparam \fifo_read_inst|rd_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N30 +cycloneive_lcell_comb \fifo_read_inst|Equal4~2 ( +// Equation(s): +// \fifo_read_inst|Equal4~2_combout = (!\fifo_read_inst|baud_cnt [11] & (\fifo_read_inst|baud_cnt [10] & (!\fifo_read_inst|baud_cnt [9] & \fifo_read_inst|baud_cnt [6]))) + + .dataa(\fifo_read_inst|baud_cnt [11]), + .datab(\fifo_read_inst|baud_cnt [10]), + .datac(\fifo_read_inst|baud_cnt [9]), + .datad(\fifo_read_inst|baud_cnt [6]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~2 .lut_mask = 16'h0400; +defparam \fifo_read_inst|Equal4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout & ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0 .lut_mask = 16'h1030; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N23 +dffeas \uart_rx_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N28 +cycloneive_lcell_comb \fifo_read_inst|Equal2~0 ( +// Equation(s): +// \fifo_read_inst|Equal2~0_combout = (\fifo_read_inst|cnt_read [3] & (\fifo_read_inst|cnt_read [1] & (!\fifo_read_inst|cnt_read [2] & !\fifo_read_inst|cnt_read [0]))) + + .dataa(\fifo_read_inst|cnt_read [3]), + .datab(\fifo_read_inst|cnt_read [1]), + .datac(\fifo_read_inst|cnt_read [2]), + .datad(\fifo_read_inst|cnt_read [0]), + .cin(gnd), + .combout(\fifo_read_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal2~0 .lut_mask = 16'h0008; +defparam \fifo_read_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N30 +cycloneive_lcell_comb \fifo_read_inst|Equal2~1 ( +// Equation(s): +// \fifo_read_inst|Equal2~1_combout = (!\fifo_read_inst|cnt_read [6] & (!\fifo_read_inst|cnt_read [7] & (!\fifo_read_inst|cnt_read [4] & !\fifo_read_inst|cnt_read [5]))) + + .dataa(\fifo_read_inst|cnt_read [6]), + .datab(\fifo_read_inst|cnt_read [7]), + .datac(\fifo_read_inst|cnt_read [4]), + .datad(\fifo_read_inst|cnt_read [5]), + .cin(gnd), + .combout(\fifo_read_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal2~1 .lut_mask = 16'h0001; +defparam \fifo_read_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N24 +cycloneive_lcell_comb \fifo_read_inst|Equal2~2 ( +// Equation(s): +// \fifo_read_inst|Equal2~2_combout = (\fifo_read_inst|Equal2~0_combout & (!\fifo_read_inst|cnt_read [9] & (\fifo_read_inst|Equal2~1_combout & !\fifo_read_inst|cnt_read [8]))) + + .dataa(\fifo_read_inst|Equal2~0_combout ), + .datab(\fifo_read_inst|cnt_read [9]), + .datac(\fifo_read_inst|Equal2~1_combout ), + .datad(\fifo_read_inst|cnt_read [8]), + .cin(gnd), + .combout(\fifo_read_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal2~2 .lut_mask = 16'h0020; +defparam \fifo_read_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N0 +cycloneive_lcell_comb \fifo_read_inst|rd_flag~0 ( +// Equation(s): +// \fifo_read_inst|rd_flag~0_combout = (!\fifo_read_inst|Equal2~2_combout & ((\fifo_read_inst|rd_flag~q ) # ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] & +// \fifo_read_inst|Equal1~2_combout )))) + + .dataa(\fifo_read_inst|Equal2~2_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datac(\fifo_read_inst|rd_flag~q ), + .datad(\fifo_read_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\fifo_read_inst|rd_flag~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|rd_flag~0 .lut_mask = 16'h5450; +defparam \fifo_read_inst|rd_flag~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N22 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~1_combout = (\uart_rx_inst|Add1~0_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_flag~q )) # (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(\uart_rx_inst|bit_cnt [3]), + .datab(\uart_rx_inst|Add1~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h4CCC; +defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N7 +dffeas \uart_rx_inst|work_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_rx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y24_N7 +dffeas \uart_rx_inst|start_nedge ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|start_nedge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; +defparam \uart_rx_inst|start_nedge .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N6 +cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( +// Equation(s): +// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) + + .dataa(gnd), + .datab(\uart_rx_inst|start_nedge~q ), + .datac(\uart_rx_inst|work_en~q ), + .datad(\uart_rx_inst|always4~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hCCFC; +defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N6 +cycloneive_lcell_comb \uart_rx_inst|always3~0 ( +// Equation(s): +// \uart_rx_inst|always3~0_combout = (\uart_rx_inst|rx_reg2~q & !\uart_rx_inst|rx_reg3~q ) + + .dataa(gnd), + .datab(\uart_rx_inst|rx_reg2~q ), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg3~q ), + .cin(gnd), + .combout(\uart_rx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always3~0 .lut_mask = 16'h00CC; +defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|bit_flag~q & \uart_tx_inst|work_en~q ))))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h1230; +defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y9_N16 +cycloneive_io_obuf \tx~output ( + .i(!\uart_tx_inst|tx~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tx), + .obar()); +// synopsys translate_off +defparam \tx~output .bus_hold = "false"; +defparam \tx~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y29_N30 +cycloneive_io_obuf \sdram_clk~output ( + .i(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_clk), + .obar()); +// synopsys translate_off +defparam \sdram_clk~output .bus_hold = "false"; +defparam \sdram_clk~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y13_N23 +cycloneive_io_obuf \sdram_cke~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_cke), + .obar()); +// synopsys translate_off +defparam \sdram_cke~output .bus_hold = "false"; +defparam \sdram_cke~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N9 +cycloneive_io_obuf \sdram_cs_n~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_cs_n), + .obar()); +// synopsys translate_off +defparam \sdram_cs_n~output .bus_hold = "false"; +defparam \sdram_cs_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y29_N16 +cycloneive_io_obuf \sdram_cas_n~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_cas_n), + .obar()); +// synopsys translate_off +defparam \sdram_cas_n~output .bus_hold = "false"; +defparam \sdram_cas_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N16 +cycloneive_io_obuf \sdram_ras_n~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_ras_n), + .obar()); +// synopsys translate_off +defparam \sdram_ras_n~output .bus_hold = "false"; +defparam \sdram_ras_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y29_N9 +cycloneive_io_obuf \sdram_we_n~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_we_n), + .obar()); +// synopsys translate_off +defparam \sdram_we_n~output .bus_hold = "false"; +defparam \sdram_we_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N16 +cycloneive_io_obuf \sdram_ba[0]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_ba[0]), + .obar()); +// synopsys translate_off +defparam \sdram_ba[0]~output .bus_hold = "false"; +defparam \sdram_ba[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y29_N2 +cycloneive_io_obuf \sdram_ba[1]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_ba[1]), + .obar()); +// synopsys translate_off +defparam \sdram_ba[1]~output .bus_hold = "false"; +defparam \sdram_ba[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N9 +cycloneive_io_obuf \sdram_addr[0]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[0]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[0]~output .bus_hold = "false"; +defparam \sdram_addr[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y27_N16 +cycloneive_io_obuf \sdram_addr[1]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[1]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[1]~output .bus_hold = "false"; +defparam \sdram_addr[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y27_N9 +cycloneive_io_obuf \sdram_addr[2]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[2]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[2]~output .bus_hold = "false"; +defparam \sdram_addr[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y26_N23 +cycloneive_io_obuf \sdram_addr[3]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[3]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[3]~output .bus_hold = "false"; +defparam \sdram_addr[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y26_N16 +cycloneive_io_obuf \sdram_addr[4]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[4]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[4]~output .bus_hold = "false"; +defparam \sdram_addr[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y24_N16 +cycloneive_io_obuf \sdram_addr[5]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[5]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[5]~output .bus_hold = "false"; +defparam \sdram_addr[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y23_N2 +cycloneive_io_obuf \sdram_addr[6]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[6]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[6]~output .bus_hold = "false"; +defparam \sdram_addr[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y24_N23 +cycloneive_io_obuf \sdram_addr[7]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[7]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[7]~output .bus_hold = "false"; +defparam \sdram_addr[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N16 +cycloneive_io_obuf \sdram_addr[8]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[8]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[8]~output .bus_hold = "false"; +defparam \sdram_addr[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N16 +cycloneive_io_obuf \sdram_addr[9]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[9]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[9]~output .bus_hold = "false"; +defparam \sdram_addr[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N2 +cycloneive_io_obuf \sdram_addr[10]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[10]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[10]~output .bus_hold = "false"; +defparam \sdram_addr[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N23 +cycloneive_io_obuf \sdram_addr[11]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[11]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[11]~output .bus_hold = "false"; +defparam \sdram_addr[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y13_N16 +cycloneive_io_obuf \sdram_addr[12]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[12]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[12]~output .bus_hold = "false"; +defparam \sdram_addr[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N2 +cycloneive_io_obuf \sdram_dqm[0]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dqm[0]), + .obar()); +// synopsys translate_off +defparam \sdram_dqm[0]~output .bus_hold = "false"; +defparam \sdram_dqm[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y20_N2 +cycloneive_io_obuf \sdram_dqm[1]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dqm[1]), + .obar()); +// synopsys translate_off +defparam \sdram_dqm[1]~output .bus_hold = "false"; +defparam \sdram_dqm[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N9 +cycloneive_io_obuf \sdram_dq[0]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[0]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[0]~output .bus_hold = "false"; +defparam \sdram_dq[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N2 +cycloneive_io_obuf \sdram_dq[1]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[1]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[1]~output .bus_hold = "false"; +defparam \sdram_dq[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y29_N2 +cycloneive_io_obuf \sdram_dq[2]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[2]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[2]~output .bus_hold = "false"; +defparam \sdram_dq[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y29_N30 +cycloneive_io_obuf \sdram_dq[3]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[3]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[3]~output .bus_hold = "false"; +defparam \sdram_dq[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y29_N23 +cycloneive_io_obuf \sdram_dq[4]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[4]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[4]~output .bus_hold = "false"; +defparam \sdram_dq[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y29_N9 +cycloneive_io_obuf \sdram_dq[5]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[5]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[5]~output .bus_hold = "false"; +defparam \sdram_dq[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N16 +cycloneive_io_obuf \sdram_dq[6]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[6]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[6]~output .bus_hold = "false"; +defparam \sdram_dq[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N23 +cycloneive_io_obuf \sdram_dq[7]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[7]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[7]~output .bus_hold = "false"; +defparam \sdram_dq[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y20_N9 +cycloneive_io_obuf \sdram_dq[8]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [8]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[8]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[8]~output .bus_hold = "false"; +defparam \sdram_dq[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N30 +cycloneive_io_obuf \sdram_dq[9]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [9]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[9]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[9]~output .bus_hold = "false"; +defparam \sdram_dq[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y25_N2 +cycloneive_io_obuf \sdram_dq[10]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [10]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[10]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[10]~output .bus_hold = "false"; +defparam \sdram_dq[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y26_N9 +cycloneive_io_obuf \sdram_dq[11]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [11]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[11]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[11]~output .bus_hold = "false"; +defparam \sdram_dq[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y23_N9 +cycloneive_io_obuf \sdram_dq[12]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [12]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[12]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[12]~output .bus_hold = "false"; +defparam \sdram_dq[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N9 +cycloneive_io_obuf \sdram_dq[13]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [13]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[13]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[13]~output .bus_hold = "false"; +defparam \sdram_dq[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N23 +cycloneive_io_obuf \sdram_dq[14]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [14]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[14]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[14]~output .bus_hold = "false"; +defparam \sdram_dq[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N2 +cycloneive_io_obuf \sdram_dq[15]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [15]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[15]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[15]~output .bus_hold = "false"; +defparam \sdram_dq[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N2 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) +// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_rx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 4; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 4; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "c2"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "-833"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 4; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 6891; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N24 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X27_Y26_N25 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N26 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked )) # (!\sys_rst_n~input_o ) + + .dataa(\sys_rst_n~input_o ), + .datab(gnd), + .datac(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h5FFF; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G17 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N6 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) +// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_rx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[1]~16 ), + .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_rx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N8 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[2]~18 ), + .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_rx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N9 +dffeas \uart_rx_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N12 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) + + .dataa(\uart_rx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[4]~22 ), + .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_rx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N13 +dffeas \uart_rx_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N30 +cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( +// Equation(s): +// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt [3] & !\uart_rx_inst|baud_cnt [5]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [2]), + .datac(\uart_rx_inst|baud_cnt [3]), + .datad(\uart_rx_inst|baud_cnt [5]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0008; +defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N14 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) +// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[5]~24 ), + .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_rx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N15 +dffeas \uart_rx_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N16 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[6]~26 ), + .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_rx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N17 +dffeas \uart_rx_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N18 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) +// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[7]~28 ), + .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_rx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N19 +dffeas \uart_rx_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N0 +cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( +// Equation(s): +// \uart_rx_inst|Equal1~0_combout = (\uart_rx_inst|baud_cnt [0] & (!\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt [1] & !\uart_rx_inst|baud_cnt [7]))) + + .dataa(\uart_rx_inst|baud_cnt [0]), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(\uart_rx_inst|baud_cnt [1]), + .datad(\uart_rx_inst|baud_cnt [7]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N20 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[8]~30 ), + .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_rx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N21 +dffeas \uart_rx_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N22 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) +// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[9]~32 ), + .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_rx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N24 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[10]~34 ), + .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_rx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N25 +dffeas \uart_rx_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N8 +cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( +// Equation(s): +// \uart_rx_inst|Equal1~2_combout = (!\uart_rx_inst|baud_cnt [9] & \uart_rx_inst|baud_cnt [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|baud_cnt [9]), + .datad(\uart_rx_inst|baud_cnt [6]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0F00; +defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N23 +dffeas \uart_rx_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N2 +cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( +// Equation(s): +// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|baud_cnt [12] & (!\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|Equal1~2_combout & \uart_rx_inst|baud_cnt [10]))) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|Equal1~2_combout ), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h2000; +defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N12 +cycloneive_lcell_comb \uart_rx_inst|always5~0 ( +// Equation(s): +// \uart_rx_inst|always5~0_combout = ((\uart_rx_inst|Equal1~1_combout & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal1~3_combout ))) # (!\uart_rx_inst|work_en~q ) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|Equal1~1_combout ), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal1~3_combout ), + .cin(gnd), + .combout(\uart_rx_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always5~0 .lut_mask = 16'hD555; +defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N3 +dffeas \uart_rx_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N4 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[0]~14 ), + .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_rx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N5 +dffeas \uart_rx_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y25_N7 +dffeas \uart_rx_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N28 +cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( +// Equation(s): +// \uart_rx_inst|Equal2~0_combout = (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt [3] & \uart_rx_inst|baud_cnt [5]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [2]), + .datac(\uart_rx_inst|baud_cnt [3]), + .datad(\uart_rx_inst|baud_cnt [5]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h1000; +defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N26 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt [12] $ (!\uart_rx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_rx_inst|baud_cnt[11]~36 ), + .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N27 +dffeas \uart_rx_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N20 +cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( +// Equation(s): +// \uart_rx_inst|Equal2~1_combout = (!\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|baud_cnt [9] & !\uart_rx_inst|baud_cnt [10]))) + + .dataa(\uart_rx_inst|baud_cnt [6]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [9]), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0040; +defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N4 +cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( +// Equation(s): +// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal1~0_combout & (\uart_rx_inst|Equal2~0_combout & (!\uart_rx_inst|baud_cnt [12] & \uart_rx_inst|Equal2~1_combout ))) + + .dataa(\uart_rx_inst|Equal1~0_combout ), + .datab(\uart_rx_inst|Equal2~0_combout ), + .datac(\uart_rx_inst|baud_cnt [12]), + .datad(\uart_rx_inst|Equal2~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h0800; +defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N5 +dffeas \uart_rx_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Equal2~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N26 +cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( +// Equation(s): +// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) +// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~1 ), + .combout(\uart_rx_inst|Add1~2_combout ), + .cout(\uart_rx_inst|Add1~3 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y25_N29 +dffeas \uart_rx_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y25_N27 +dffeas \uart_rx_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N0 +cycloneive_lcell_comb \uart_rx_inst|always4~0 ( +// Equation(s): +// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [0] & (!\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [0]), + .datab(\uart_rx_inst|bit_cnt [2]), + .datac(\uart_rx_inst|bit_cnt [1]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0101; +defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N16 +cycloneive_lcell_comb \uart_rx_inst|always4~1 ( +// Equation(s): +// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|bit_cnt [3] & (\uart_rx_inst|always4~0_combout & \uart_rx_inst|bit_flag~q )) + + .dataa(\uart_rx_inst|bit_cnt [3]), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~1 .lut_mask = 16'h8080; +defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N17 +dffeas \uart_rx_inst|rx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always4~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_flag .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N1 +dffeas \uart_rx_inst|po_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_flag~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h5A5A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hF0B4; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0800; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h0100; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .lut_mask = 16'hC3F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h3CC3; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h0200; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0004; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hB4F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4 .lut_mask = 16'h0001; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6 .lut_mask = 16'h0100; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8 .lut_mask = 16'h1000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5 .lut_mask = 16'h9696; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y22_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y22_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0040; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hE1F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'h2000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8 .lut_mask = 16'h000F; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'h8008; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'h8008; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'h0F33; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ) # (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q )))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ) # +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hEEE0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X16_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y20_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [0]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [0])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1 .lut_mask = 16'h00BB; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y20_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|LessThan2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ) # ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ) # +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ) # (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~0 .lut_mask = 16'hFFFE; +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|LessThan2~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ) # ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ) # (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~1 .lut_mask = 16'hFFC8; +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .lut_mask = 16'h0010; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 $ (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [9])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [9]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [9]), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18 .lut_mask = 16'h5AA5; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & ((\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ) # ((\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ) # +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0 .lut_mask = 16'hAAA8; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y20_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h5A5A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hF0B4; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hD2F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h0040; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .lut_mask = 16'hD2D2; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1] $ (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h3CC3; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0020; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hD2F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & (\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4 .lut_mask = 16'h0500; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9] $ (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28 .lut_mask = 16'h5A5A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3 .lut_mask = 16'h000F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5 .lut_mask = 16'h2000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0 .lut_mask = 16'hCCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [5] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2 .lut_mask = 16'h0001; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ) # ((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0 .lut_mask = 16'hFF30; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1 .lut_mask = 16'hC0C0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0 .lut_mask = 16'h00F8; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16 .lut_mask = 16'h0088; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0 .lut_mask = 16'hCCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1 .lut_mask = 16'hCC00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2 .lut_mask = 16'hEEFF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [0] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0 .lut_mask = 16'h00FE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3 .lut_mask = 16'hFFEC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y23_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y23_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [1]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]) # (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1 .lut_mask = 16'h5776; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hF0D2; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h78F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0100; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0010; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .lut_mask = 16'hA5F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2] $ (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h3CC3; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0008; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h0200; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'hB4F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'hFCFF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1 .lut_mask = 16'hF05A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout +// )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'hAC0C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout )))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'h59FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h0021; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout & +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout +// )) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'h1333; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y24_N25 +dffeas \fifo_read_inst|read_en_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\fifo_read_inst|read_en~q ), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_en_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_en_dly .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_en_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout = (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q & \fifo_read_inst|read_en_dly~q ) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datab(gnd), + .datac(\fifo_read_inst|read_en_dly~q ), + .datad(gnd), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq .lut_mask = 16'h5050; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N6 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] $ (((VCC) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT = CARRY(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] $ +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0 .lut_mask = 16'h5599; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y24_N7 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N8 +cycloneive_lcell_comb \fifo_read_inst|Add2~0 ( +// Equation(s): +// \fifo_read_inst|Add2~0_combout = (\fifo_read_inst|bit_flag~q & (\fifo_read_inst|bit_cnt [0] $ (VCC))) # (!\fifo_read_inst|bit_flag~q & (\fifo_read_inst|bit_cnt [0] & VCC)) +// \fifo_read_inst|Add2~1 = CARRY((\fifo_read_inst|bit_flag~q & \fifo_read_inst|bit_cnt [0])) + + .dataa(\fifo_read_inst|bit_flag~q ), + .datab(\fifo_read_inst|bit_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|Add2~0_combout ), + .cout(\fifo_read_inst|Add2~1 )); +// synopsys translate_off +defparam \fifo_read_inst|Add2~0 .lut_mask = 16'h6688; +defparam \fifo_read_inst|Add2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N9 +dffeas \fifo_read_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|Add2~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N10 +cycloneive_lcell_comb \fifo_read_inst|Add2~2 ( +// Equation(s): +// \fifo_read_inst|Add2~2_combout = (\fifo_read_inst|bit_cnt [1] & (!\fifo_read_inst|Add2~1 )) # (!\fifo_read_inst|bit_cnt [1] & ((\fifo_read_inst|Add2~1 ) # (GND))) +// \fifo_read_inst|Add2~3 = CARRY((!\fifo_read_inst|Add2~1 ) # (!\fifo_read_inst|bit_cnt [1])) + + .dataa(\fifo_read_inst|bit_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|Add2~1 ), + .combout(\fifo_read_inst|Add2~2_combout ), + .cout(\fifo_read_inst|Add2~3 )); +// synopsys translate_off +defparam \fifo_read_inst|Add2~2 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|Add2~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N14 +cycloneive_lcell_comb \fifo_read_inst|Add2~6 ( +// Equation(s): +// \fifo_read_inst|Add2~6_combout = \fifo_read_inst|bit_cnt [3] $ (\fifo_read_inst|Add2~5 ) + + .dataa(gnd), + .datab(\fifo_read_inst|bit_cnt [3]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|Add2~5 ), + .combout(\fifo_read_inst|Add2~6_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Add2~6 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|Add2~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N4 +cycloneive_lcell_comb \fifo_read_inst|bit_cnt~0 ( +// Equation(s): +// \fifo_read_inst|bit_cnt~0_combout = (\fifo_read_inst|Add2~6_combout & ((!\fifo_read_inst|always5~0_combout ) # (!\fifo_read_inst|bit_cnt [0]))) + + .dataa(gnd), + .datab(\fifo_read_inst|bit_cnt [0]), + .datac(\fifo_read_inst|Add2~6_combout ), + .datad(\fifo_read_inst|always5~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt~0 .lut_mask = 16'h30F0; +defparam \fifo_read_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N5 +dffeas \fifo_read_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N4 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[0]~13 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[0]~13_combout = (\fifo_read_inst|rd_flag~q & (\fifo_read_inst|baud_cnt [0] $ (VCC))) # (!\fifo_read_inst|rd_flag~q & (\fifo_read_inst|baud_cnt [0] & VCC)) +// \fifo_read_inst|baud_cnt[0]~14 = CARRY((\fifo_read_inst|rd_flag~q & \fifo_read_inst|baud_cnt [0])) + + .dataa(\fifo_read_inst|rd_flag~q ), + .datab(\fifo_read_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|baud_cnt[0]~13_combout ), + .cout(\fifo_read_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \fifo_read_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N14 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[5]~23 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[5]~23_combout = (\fifo_read_inst|baud_cnt [5] & (!\fifo_read_inst|baud_cnt[4]~22 )) # (!\fifo_read_inst|baud_cnt [5] & ((\fifo_read_inst|baud_cnt[4]~22 ) # (GND))) +// \fifo_read_inst|baud_cnt[5]~24 = CARRY((!\fifo_read_inst|baud_cnt[4]~22 ) # (!\fifo_read_inst|baud_cnt [5])) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[4]~22 ), + .combout(\fifo_read_inst|baud_cnt[5]~23_combout ), + .cout(\fifo_read_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N16 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[6]~25 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[6]~25_combout = (\fifo_read_inst|baud_cnt [6] & (\fifo_read_inst|baud_cnt[5]~24 $ (GND))) # (!\fifo_read_inst|baud_cnt [6] & (!\fifo_read_inst|baud_cnt[5]~24 & VCC)) +// \fifo_read_inst|baud_cnt[6]~26 = CARRY((\fifo_read_inst|baud_cnt [6] & !\fifo_read_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[5]~24 ), + .combout(\fifo_read_inst|baud_cnt[6]~25_combout ), + .cout(\fifo_read_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N17 +dffeas \fifo_read_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N18 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[7]~27 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[7]~27_combout = (\fifo_read_inst|baud_cnt [7] & (!\fifo_read_inst|baud_cnt[6]~26 )) # (!\fifo_read_inst|baud_cnt [7] & ((\fifo_read_inst|baud_cnt[6]~26 ) # (GND))) +// \fifo_read_inst|baud_cnt[7]~28 = CARRY((!\fifo_read_inst|baud_cnt[6]~26 ) # (!\fifo_read_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[6]~26 ), + .combout(\fifo_read_inst|baud_cnt[7]~27_combout ), + .cout(\fifo_read_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N19 +dffeas \fifo_read_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N20 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[8]~29 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[8]~29_combout = (\fifo_read_inst|baud_cnt [8] & (\fifo_read_inst|baud_cnt[7]~28 $ (GND))) # (!\fifo_read_inst|baud_cnt [8] & (!\fifo_read_inst|baud_cnt[7]~28 & VCC)) +// \fifo_read_inst|baud_cnt[8]~30 = CARRY((\fifo_read_inst|baud_cnt [8] & !\fifo_read_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[7]~28 ), + .combout(\fifo_read_inst|baud_cnt[8]~29_combout ), + .cout(\fifo_read_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N21 +dffeas \fifo_read_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N0 +cycloneive_lcell_comb \fifo_read_inst|Equal4~0 ( +// Equation(s): +// \fifo_read_inst|Equal4~0_combout = (\fifo_read_inst|baud_cnt [1] & (!\fifo_read_inst|baud_cnt [8] & (\fifo_read_inst|baud_cnt [0] & !\fifo_read_inst|baud_cnt [7]))) + + .dataa(\fifo_read_inst|baud_cnt [1]), + .datab(\fifo_read_inst|baud_cnt [8]), + .datac(\fifo_read_inst|baud_cnt [0]), + .datad(\fifo_read_inst|baud_cnt [7]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~0 .lut_mask = 16'h0020; +defparam \fifo_read_inst|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N10 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[3]~19 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[3]~19_combout = (\fifo_read_inst|baud_cnt [3] & (!\fifo_read_inst|baud_cnt[2]~18 )) # (!\fifo_read_inst|baud_cnt [3] & ((\fifo_read_inst|baud_cnt[2]~18 ) # (GND))) +// \fifo_read_inst|baud_cnt[3]~20 = CARRY((!\fifo_read_inst|baud_cnt[2]~18 ) # (!\fifo_read_inst|baud_cnt [3])) + + .dataa(\fifo_read_inst|baud_cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[2]~18 ), + .combout(\fifo_read_inst|baud_cnt[3]~19_combout ), + .cout(\fifo_read_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N11 +dffeas \fifo_read_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N22 +cycloneive_lcell_comb \fifo_read_inst|Equal4~1 ( +// Equation(s): +// \fifo_read_inst|Equal4~1_combout = (\fifo_read_inst|baud_cnt [4] & (!\fifo_read_inst|baud_cnt [5] & (!\fifo_read_inst|baud_cnt [3] & \fifo_read_inst|baud_cnt [2]))) + + .dataa(\fifo_read_inst|baud_cnt [4]), + .datab(\fifo_read_inst|baud_cnt [5]), + .datac(\fifo_read_inst|baud_cnt [3]), + .datad(\fifo_read_inst|baud_cnt [2]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~1 .lut_mask = 16'h0200; +defparam \fifo_read_inst|Equal4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N24 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[10]~33 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[10]~33_combout = (\fifo_read_inst|baud_cnt [10] & (\fifo_read_inst|baud_cnt[9]~32 $ (GND))) # (!\fifo_read_inst|baud_cnt [10] & (!\fifo_read_inst|baud_cnt[9]~32 & VCC)) +// \fifo_read_inst|baud_cnt[10]~34 = CARRY((\fifo_read_inst|baud_cnt [10] & !\fifo_read_inst|baud_cnt[9]~32 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[9]~32 ), + .combout(\fifo_read_inst|baud_cnt[10]~33_combout ), + .cout(\fifo_read_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N25 +dffeas \fifo_read_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N28 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[12]~37 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[12]~37_combout = \fifo_read_inst|baud_cnt[11]~36 $ (!\fifo_read_inst|baud_cnt [12]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\fifo_read_inst|baud_cnt [12]), + .cin(\fifo_read_inst|baud_cnt[11]~36 ), + .combout(\fifo_read_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; +defparam \fifo_read_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N29 +dffeas \fifo_read_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N16 +cycloneive_lcell_comb \fifo_read_inst|Equal4~3 ( +// Equation(s): +// \fifo_read_inst|Equal4~3_combout = (\fifo_read_inst|Equal4~2_combout & (\fifo_read_inst|Equal4~0_combout & (\fifo_read_inst|Equal4~1_combout & \fifo_read_inst|baud_cnt [12]))) + + .dataa(\fifo_read_inst|Equal4~2_combout ), + .datab(\fifo_read_inst|Equal4~0_combout ), + .datac(\fifo_read_inst|Equal4~1_combout ), + .datad(\fifo_read_inst|baud_cnt [12]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~3_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~3 .lut_mask = 16'h8000; +defparam \fifo_read_inst|Equal4~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y25_N5 +dffeas \fifo_read_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N8 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[2]~17 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[2]~17_combout = (\fifo_read_inst|baud_cnt [2] & (\fifo_read_inst|baud_cnt[1]~16 $ (GND))) # (!\fifo_read_inst|baud_cnt [2] & (!\fifo_read_inst|baud_cnt[1]~16 & VCC)) +// \fifo_read_inst|baud_cnt[2]~18 = CARRY((\fifo_read_inst|baud_cnt [2] & !\fifo_read_inst|baud_cnt[1]~16 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[1]~16 ), + .combout(\fifo_read_inst|baud_cnt[2]~17_combout ), + .cout(\fifo_read_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N9 +dffeas \fifo_read_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N15 +dffeas \fifo_read_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N28 +cycloneive_lcell_comb \fifo_read_inst|Equal5~0 ( +// Equation(s): +// \fifo_read_inst|Equal5~0_combout = (!\fifo_read_inst|baud_cnt [4] & (\fifo_read_inst|baud_cnt [5] & (\fifo_read_inst|baud_cnt [3] & !\fifo_read_inst|baud_cnt [2]))) + + .dataa(\fifo_read_inst|baud_cnt [4]), + .datab(\fifo_read_inst|baud_cnt [5]), + .datac(\fifo_read_inst|baud_cnt [3]), + .datad(\fifo_read_inst|baud_cnt [2]), + .cin(gnd), + .combout(\fifo_read_inst|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal5~0 .lut_mask = 16'h0040; +defparam \fifo_read_inst|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N26 +cycloneive_lcell_comb \fifo_read_inst|Equal5~2 ( +// Equation(s): +// \fifo_read_inst|Equal5~2_combout = (\fifo_read_inst|Equal5~1_combout & (\fifo_read_inst|Equal5~0_combout & (\fifo_read_inst|Equal4~0_combout & !\fifo_read_inst|baud_cnt [12]))) + + .dataa(\fifo_read_inst|Equal5~1_combout ), + .datab(\fifo_read_inst|Equal5~0_combout ), + .datac(\fifo_read_inst|Equal4~0_combout ), + .datad(\fifo_read_inst|baud_cnt [12]), + .cin(gnd), + .combout(\fifo_read_inst|Equal5~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal5~2 .lut_mask = 16'h0080; +defparam \fifo_read_inst|Equal5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N27 +dffeas \fifo_read_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|Equal5~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_flag .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N6 +cycloneive_lcell_comb \fifo_read_inst|bit_cnt~1 ( +// Equation(s): +// \fifo_read_inst|bit_cnt~1_combout = (\fifo_read_inst|Add2~2_combout & ((!\fifo_read_inst|bit_cnt [0]) # (!\fifo_read_inst|always5~0_combout ))) + + .dataa(gnd), + .datab(\fifo_read_inst|always5~0_combout ), + .datac(\fifo_read_inst|bit_cnt [0]), + .datad(\fifo_read_inst|Add2~2_combout ), + .cin(gnd), + .combout(\fifo_read_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt~1 .lut_mask = 16'h3F00; +defparam \fifo_read_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N7 +dffeas \fifo_read_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N24 +cycloneive_lcell_comb \fifo_read_inst|always5~0 ( +// Equation(s): +// \fifo_read_inst|always5~0_combout = (!\fifo_read_inst|bit_cnt [2] & (\fifo_read_inst|bit_cnt [3] & (\fifo_read_inst|bit_flag~q & !\fifo_read_inst|bit_cnt [1]))) + + .dataa(\fifo_read_inst|bit_cnt [2]), + .datab(\fifo_read_inst|bit_cnt [3]), + .datac(\fifo_read_inst|bit_flag~q ), + .datad(\fifo_read_inst|bit_cnt [1]), + .cin(gnd), + .combout(\fifo_read_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|always5~0 .lut_mask = 16'h0040; +defparam \fifo_read_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N0 +cycloneive_lcell_comb \fifo_read_inst|always5~1 ( +// Equation(s): +// \fifo_read_inst|always5~1_combout = (\fifo_read_inst|bit_cnt [0] & \fifo_read_inst|always5~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\fifo_read_inst|bit_cnt [0]), + .datad(\fifo_read_inst|always5~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|always5~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|always5~1 .lut_mask = 16'hF000; +defparam \fifo_read_inst|always5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N1 +dffeas \fifo_read_inst|rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|always5~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|rd_en .is_wysiwyg = "true"; +defparam \fifo_read_inst|rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]) # +// (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]) # (!\fifo_read_inst|rd_en~q )) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0])) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .lut_mask = 16'hFBFF; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N6 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ) # (\fifo_read_inst|read_en_dly~q ) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datab(gnd), + .datac(\fifo_read_inst|read_en_dly~q ), + .datad(gnd), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .lut_mask = 16'hFAFA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ) # +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ) # (!\fifo_read_inst|Equal1~1_combout )))) + + .dataa(\fifo_read_inst|Equal1~1_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .lut_mask = 16'hFFD0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N26 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ) # +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q & !\fifo_read_inst|rd_en~q )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ), + .datab(gnd), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4 .lut_mask = 16'hAAFA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N27 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout = (\fifo_read_inst|read_en_dly~q & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q $ (((!\fifo_read_inst|rd_en~q ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ))))) # (!\fifo_read_inst|read_en_dly~q & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & +// ((\fifo_read_inst|rd_en~q )))) + + .dataa(\fifo_read_inst|read_en_dly~q ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .lut_mask = 16'hC60A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N9 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y25_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y22_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N10 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h0040; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N28 +cycloneive_lcell_comb \fifo_read_inst|read_en~0 ( +// Equation(s): +// \fifo_read_inst|read_en~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout & (\Equal2~1_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout & +// \Equal2~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .datab(\Equal2~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .datad(\Equal2~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_en~0 .lut_mask = 16'h0400; +defparam \fifo_read_inst|read_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N8 +cycloneive_lcell_comb \fifo_read_inst|read_en~1 ( +// Equation(s): +// \fifo_read_inst|read_en~1_combout = (\fifo_read_inst|read_en~0_combout ) # ((\fifo_read_inst|read_en~q & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]) # +// (!\fifo_read_inst|Equal1~2_combout )))) + + .dataa(\fifo_read_inst|Equal1~2_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datac(\fifo_read_inst|read_en~q ), + .datad(\fifo_read_inst|read_en~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_en~1 .lut_mask = 16'hFFD0; +defparam \fifo_read_inst|read_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N9 +dffeas \fifo_read_inst|read_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_en~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_en .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout = (\fifo_read_inst|read_en~q & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ) # +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .datad(\fifo_read_inst|read_en~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hFC00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h0800; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0010; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N2 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0001; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9 .lut_mask = 16'h55AA; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 $ (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [9])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [9]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [9]), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18 .lut_mask = 16'h5AA5; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout = (\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout & (!\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2 .lut_mask = 16'h0002; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout = (!\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout & (\Equal2~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout & +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ), + .datab(\Equal2~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q & (!\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0 .lut_mask = 16'h0100; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0 .lut_mask = 16'h5500; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & !\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1 .lut_mask = 16'hFF08; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7 .lut_mask = 16'h0030; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0 .lut_mask = 16'hDCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ) # ((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0 .lut_mask = 16'hFF50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & (\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1 .lut_mask = 16'hF888; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ) # +// (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3 .lut_mask = 16'hFEFE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0 .lut_mask = 16'hC0C0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0 .lut_mask = 16'h00F8; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4 .lut_mask = 16'h0F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2 .lut_mask = 16'h0AA0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15 .lut_mask = 16'h00F0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ) # ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0 .lut_mask = 16'hFF50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]))) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1 .lut_mask = 16'h0330; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0 .lut_mask = 16'h0300; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout = ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1 .lut_mask = 16'hFFD5; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2 .lut_mask = 16'hFF88; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2] $ +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0 .lut_mask = 16'h1230; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0 .lut_mask = 16'h7F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1 .lut_mask = 16'hFCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2 .lut_mask = 16'h0007; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk +// [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ) # +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0 .lut_mask = 16'hB3A0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3 .lut_mask = 16'hF5F5; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17 .lut_mask = 16'h2020; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0 .lut_mask = 16'hFFC0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3 .lut_mask = 16'h000F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]))) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2 .lut_mask = 16'h003C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1 .lut_mask = 16'h0C0C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0 .lut_mask = 16'hEAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0 .lut_mask = 16'hB800; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3 .lut_mask = 16'h0055; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4 .lut_mask = 16'h0004; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0 .lut_mask = 16'h2AAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [9] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [11] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[12] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 $ (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28 .lut_mask = 16'hF00F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[14] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[11] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0 .lut_mask = 16'h0040; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1 .lut_mask = 16'h0020; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6]), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2 .lut_mask = 16'h5000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0 .lut_mask = 16'h2000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2 .lut_mask = 16'hFEFF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] $ +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4 .lut_mask = 16'h1230; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0 .lut_mask = 16'hCC00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0 .lut_mask = 16'hF2F0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16 .lut_mask = 16'h4040; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0 .lut_mask = 16'h55AA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref +// [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref +// [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1 .lut_mask = 16'hF0FF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref +// [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8 .lut_mask = 16'hCC00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout = (((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0 .lut_mask = 16'h777F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5] & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1 .lut_mask = 16'h8C00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout = ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2 .lut_mask = 16'h1F3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3 .lut_mask = 16'hC840; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 $ (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1 .lut_mask = 16'h0040; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2 .lut_mask = 16'hC000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ) # +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0 .lut_mask = 16'hBA30; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0 .lut_mask = 16'h0F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & (\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0 .lut_mask = 16'h5450; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1 .lut_mask = 16'hFFCF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout & +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0 .lut_mask = 16'hF888; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2 .lut_mask = 16'hFFF8; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] $ (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datac(gnd), + .datad(gnd), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5 .lut_mask = 16'h0033; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0 .lut_mask = 16'hAAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout = ((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2 .lut_mask = 16'h5557; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ) # +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h00A8; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h5400; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .lut_mask = 16'h9696; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1] $ (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .lut_mask = 16'h5AA5; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h2000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h0200; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hB4F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h0040; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .lut_mask = 16'hC3F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h2814; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout +// )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'hE2C0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'hA018; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout = (\uart_rx_inst|po_flag~q & ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .datab(gnd), + .datac(\uart_rx_inst|po_flag~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .lut_mask = 16'h50F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \rx~input ( + .i(rx), + .ibar(gnd), + .o(\rx~input_o )); +// synopsys translate_off +defparam \rx~input .bus_hold = "false"; +defparam \rx~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N12 +cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( +// Equation(s): +// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rx~input_o ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y24_N13 +dffeas \uart_rx_inst|rx_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg1~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y24_N3 +dffeas \uart_rx_inst|rx_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_reg3~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg3~feeder_combout = \uart_rx_inst|rx_reg2~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg2~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y24_N1 +dffeas \uart_rx_inst|rx_reg3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg3~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N14 +cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( +// Equation(s): +// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg3~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N10 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~0_combout = (\uart_rx_inst|Add1~6_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q ))) + + .dataa(\uart_rx_inst|Add1~6_combout ), + .datab(\uart_rx_inst|bit_flag~q ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h2AAA; +defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N11 +dffeas \uart_rx_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N18 +cycloneive_lcell_comb \uart_rx_inst|always8~0 ( +// Equation(s): +// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(gnd), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|always8~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always8~0 .lut_mask = 16'hC030; +defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N15 +dffeas \uart_rx_inst|rx_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[7]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y23_N21 +dffeas \uart_rx_inst|rx_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N18 +cycloneive_lcell_comb \uart_rx_inst|rx_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[5]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N19 +dffeas \uart_rx_inst|rx_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[4]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N1 +dffeas \uart_rx_inst|rx_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N6 +cycloneive_lcell_comb \uart_rx_inst|rx_data[3]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[3]~feeder_combout = \uart_rx_inst|rx_data [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [4]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N7 +dffeas \uart_rx_inst|rx_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N28 +cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N29 +dffeas \uart_rx_inst|rx_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[1]~feeder_combout = \uart_rx_inst|rx_data [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [2]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N3 +dffeas \uart_rx_inst|rx_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N24 +cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N25 +dffeas \uart_rx_inst|rx_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N8 +cycloneive_lcell_comb \uart_rx_inst|po_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[0]~feeder_combout = \uart_rx_inst|rx_data [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [0]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N9 +dffeas \uart_rx_inst|po_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a[9] ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9]), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a[9] .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout = !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N10 +cycloneive_lcell_comb \uart_rx_inst|po_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[1]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N11 +dffeas \uart_rx_inst|po_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N12 +cycloneive_lcell_comb \uart_rx_inst|po_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[2]~feeder_combout = \uart_rx_inst|rx_data [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [2]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N13 +dffeas \uart_rx_inst|po_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N30 +cycloneive_lcell_comb \uart_rx_inst|po_data[3]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[3]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N31 +dffeas \uart_rx_inst|po_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N16 +cycloneive_lcell_comb \uart_rx_inst|po_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[4]~feeder_combout = \uart_rx_inst|rx_data [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [4]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N17 +dffeas \uart_rx_inst|po_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N26 +cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N27 +dffeas \uart_rx_inst|po_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N4 +cycloneive_lcell_comb \uart_rx_inst|po_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[6]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N5 +dffeas \uart_rx_inst|po_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y23_N23 +dffeas \uart_rx_inst|po_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y23_N8 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X13_Y23_N0 +cycloneive_ram_block \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .ena0(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(\rst_n~0clkctrl_outclk ), + .portadatain({\~GND~combout ,\uart_rx_inst|po_data [7],\uart_rx_inst|po_data [6],\uart_rx_inst|po_data [5],\uart_rx_inst|po_data [4],\uart_rx_inst|po_data [3],\uart_rx_inst|po_data [2],\uart_rx_inst|po_data [1],\uart_rx_inst|po_data [0]}), + .portaaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "sdram_top:sdram_top_inst|fifo_ctrl:fifo_ctrl_inst|fifo_data:wr_fifo_data|dcfifo:dcfifo_component|dcfifo_3fk1:auto_generated|altsyncram_em31:fifo_ram|ALTSYNCRAM"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X13_Y21_N0 +cycloneive_ram_block \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 ( + .portawe(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .ena0(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(\rst_n~0clkctrl_outclk ), + .portadatain({gnd,gnd,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout }), + .portaaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .clk0_core_clock_enable = "ena0"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .clk1_output_clock_enable = "ena1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .data_interleave_offset_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .data_interleave_width_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .logical_ram_name = "sdram_top:sdram_top_inst|fifo_ctrl:fifo_ctrl_inst|fifo_data:wr_fifo_data|dcfifo:dcfifo_component|dcfifo_3fk1:auto_generated|altsyncram_em31:fifo_ram|ALTSYNCRAM"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .operation_mode = "dual_port"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_address_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_byte_enable_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_data_out_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_data_out_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_first_bit_number = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_address_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_address_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_data_out_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_data_out_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_first_bit_number = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_read_enable_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: CLKCTRL_G5 +cycloneive_clkctrl \sys_clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sys_clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sys_clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \sys_clk~inputclkctrl .clock_type = "global clock"; +defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N4 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) +// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_tx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N26 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) + + .dataa(\uart_tx_inst|baud_cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[10]~34 ), + .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_tx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N27 +dffeas \uart_tx_inst|baud_cnt[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N0 +cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( +// Equation(s): +// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt [5] & (\uart_tx_inst|baud_cnt [0] & !\uart_tx_inst|baud_cnt [7]))) + + .dataa(\uart_tx_inst|baud_cnt [3]), + .datab(\uart_tx_inst|baud_cnt [5]), + .datac(\uart_tx_inst|baud_cnt [0]), + .datad(\uart_tx_inst|baud_cnt [7]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0010; +defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N22 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) + + .dataa(\uart_tx_inst|baud_cnt [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[8]~30 ), + .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_tx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N23 +dffeas \uart_tx_inst|baud_cnt[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N2 +cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( +// Equation(s): +// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt [11] & (\uart_tx_inst|Equal1~0_combout & !\uart_tx_inst|baud_cnt [9]))) + + .dataa(\uart_tx_inst|baud_cnt [8]), + .datab(\uart_tx_inst|baud_cnt [11]), + .datac(\uart_tx_inst|Equal1~0_combout ), + .datad(\uart_tx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0010; +defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N6 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) + + .dataa(\uart_tx_inst|baud_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[0]~14 ), + .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_tx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N7 +dffeas \uart_tx_inst|baud_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N30 +cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( +// Equation(s): +// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [2] & \uart_tx_inst|baud_cnt [1]))) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [2]), + .datad(\uart_tx_inst|baud_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; +defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N19 +dffeas \fifo_read_inst|tx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\fifo_read_inst|rd_en~q ), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|tx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|tx_flag .is_wysiwyg = "true"; +defparam \fifo_read_inst|tx_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \uart_tx_inst|always3~0 ( +// Equation(s): +// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|work_en~q ) # (!\uart_tx_inst|bit_flag~q ) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(gnd), + .datac(\uart_tx_inst|work_en~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_tx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always3~0 .lut_mask = 16'h5F5F; +defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~2 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[1]~2_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [1]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1]~2 .lut_mask = 16'h00D2; +defparam \uart_tx_inst|bit_cnt[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N19 +dffeas \uart_tx_inst|bit_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[1]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~3 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[2]~3_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~0_combout )))) + + .dataa(\uart_tx_inst|Add1~0_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2]~3 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N5 +dffeas \uart_tx_inst|bit_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[2]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \uart_tx_inst|always0~1 ( +// Equation(s): +// \uart_tx_inst|always0~1_combout = (\uart_tx_inst|bit_cnt [0] & (!\uart_tx_inst|bit_cnt [1] & (!\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|always0~0_combout ))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~1 .lut_mask = 16'h0200; +defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N18 +cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( +// Equation(s): +// \uart_tx_inst|work_en~0_combout = (\fifo_read_inst|tx_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) + + .dataa(gnd), + .datab(\uart_tx_inst|work_en~q ), + .datac(\fifo_read_inst|tx_flag~q ), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hF0FC; +defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N25 +dffeas \uart_tx_inst|work_en ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_tx_inst|work_en~0_combout ), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_tx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N6 +cycloneive_lcell_comb \uart_tx_inst|always1~0 ( +// Equation(s): +// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~3_combout & (\uart_tx_inst|Equal1~1_combout & \uart_tx_inst|Equal1~2_combout ))) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|Equal1~3_combout ), + .datab(\uart_tx_inst|Equal1~1_combout ), + .datac(\uart_tx_inst|Equal1~2_combout ), + .datad(\uart_tx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_tx_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always1~0 .lut_mask = 16'h80FF; +defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y18_N5 +dffeas \uart_tx_inst|baud_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N8 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) +// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[1]~16 ), + .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_tx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N9 +dffeas \uart_tx_inst|baud_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N14 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[4]~22 ), + .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_tx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N15 +dffeas \uart_tx_inst|baud_cnt[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N16 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) +// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[5]~24 ), + .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_tx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N17 +dffeas \uart_tx_inst|baud_cnt[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N18 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[6]~26 ), + .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_tx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N19 +dffeas \uart_tx_inst|baud_cnt[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N20 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) +// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[7]~28 ), + .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_tx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N21 +dffeas \uart_tx_inst|baud_cnt[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N24 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) +// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[9]~32 ), + .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_tx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N25 +dffeas \uart_tx_inst|baud_cnt[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N28 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt[11]~36 $ (!\uart_tx_inst|baud_cnt [12]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_tx_inst|baud_cnt [12]), + .cin(\uart_tx_inst|baud_cnt[11]~36 ), + .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; +defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N29 +dffeas \uart_tx_inst|baud_cnt[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N2 +cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( +// Equation(s): +// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt [1]))) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [2]), + .datad(\uart_tx_inst|baud_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N24 +cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( +// Equation(s): +// \uart_tx_inst|Equal2~1_combout = (\uart_tx_inst|Equal1~1_combout & (!\uart_tx_inst|baud_cnt [12] & (\uart_tx_inst|Equal2~0_combout & !\uart_tx_inst|baud_cnt [10]))) + + .dataa(\uart_tx_inst|Equal1~1_combout ), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(\uart_tx_inst|Equal2~0_combout ), + .datad(\uart_tx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h0020; +defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y18_N25 +dffeas \uart_tx_inst|bit_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|Equal2~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \uart_tx_inst|always0~0 ( +// Equation(s): +// \uart_tx_inst|always0~0_combout = (\uart_tx_inst|bit_cnt [3] & \uart_tx_inst|bit_flag~q ) + + .dataa(\uart_tx_inst|bit_cnt [3]), + .datab(gnd), + .datac(\uart_tx_inst|bit_flag~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_tx_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~0 .lut_mask = 16'hA0A0; +defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N30 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & \fifo_read_inst|rd_en~q ) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datab(gnd), + .datac(gnd), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq .lut_mask = 16'hAA00; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N8 +cycloneive_io_ibuf \sdram_dq[0]~input ( + .i(sdram_dq[0]), + .ibar(gnd), + .o(\sdram_dq[0]~input_o )); +// synopsys translate_off +defparam \sdram_dq[0]~input .bus_hold = "false"; +defparam \sdram_dq[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[0]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout = !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N1 +cycloneive_io_ibuf \sdram_dq[1]~input ( + .i(sdram_dq[1]), + .ibar(gnd), + .o(\sdram_dq[1]~input_o )); +// synopsys translate_off +defparam \sdram_dq[1]~input .bus_hold = "false"; +defparam \sdram_dq[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[1]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [1] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y29_N1 +cycloneive_io_ibuf \sdram_dq[2]~input ( + .i(sdram_dq[2]), + .ibar(gnd), + .o(\sdram_dq[2]~input_o )); +// synopsys translate_off +defparam \sdram_dq[2]~input .bus_hold = "false"; +defparam \sdram_dq[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[2]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y29_N29 +cycloneive_io_ibuf \sdram_dq[3]~input ( + .i(sdram_dq[3]), + .ibar(gnd), + .o(\sdram_dq[3]~input_o )); +// synopsys translate_off +defparam \sdram_dq[3]~input .bus_hold = "false"; +defparam \sdram_dq[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[3]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [3] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [3]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y29_N22 +cycloneive_io_ibuf \sdram_dq[4]~input ( + .i(sdram_dq[4]), + .ibar(gnd), + .o(\sdram_dq[4]~input_o )); +// synopsys translate_off +defparam \sdram_dq[4]~input .bus_hold = "false"; +defparam \sdram_dq[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[4]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [4] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [4]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y29_N8 +cycloneive_io_ibuf \sdram_dq[5]~input ( + .i(sdram_dq[5]), + .ibar(gnd), + .o(\sdram_dq[5]~input_o )); +// synopsys translate_off +defparam \sdram_dq[5]~input .bus_hold = "false"; +defparam \sdram_dq[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[5]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [5] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N15 +cycloneive_io_ibuf \sdram_dq[6]~input ( + .i(sdram_dq[6]), + .ibar(gnd), + .o(\sdram_dq[6]~input_o )); +// synopsys translate_off +defparam \sdram_dq[6]~input .bus_hold = "false"; +defparam \sdram_dq[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[6]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [6] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [6]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N22 +cycloneive_io_ibuf \sdram_dq[7]~input ( + .i(sdram_dq[7]), + .ibar(gnd), + .o(\sdram_dq[7]~input_o )); +// synopsys translate_off +defparam \sdram_dq[7]~input .bus_hold = "false"; +defparam \sdram_dq[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[7]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [7] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [7]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X25_Y25_N0 +cycloneive_ram_block \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .ena1(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(\rst_n~0clkctrl_outclk ), + .portadatain({gnd,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout , +\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout , +\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout }), + .portaaddr({\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "sdram_top:sdram_top_inst|fifo_ctrl:fifo_ctrl_inst|fifo_data:rd_fifo_data|dcfifo:dcfifo_component|dcfifo_3fk1:auto_generated|altsyncram_em31:fifo_ram|ALTSYNCRAM"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N6 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0] $ (VCC) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT = CARRY(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0 .lut_mask = 16'h55AA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N7 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N8 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N9 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N10 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N11 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3])) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N14 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N15 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N17 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N18 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N19 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N21 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N23 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N25 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N10 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0] $ (VCC) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT = CARRY(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0 .lut_mask = 16'h55AA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N11 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1])) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N14 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N15 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N17 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N18 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N19 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N21 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N23 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N25 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N26 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N27 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N28 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9]), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9 .lut_mask = 16'h0FF0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N29 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \uart_tx_inst|tx~4 ( +// Equation(s): +// \uart_tx_inst|tx~4_combout = (\uart_tx_inst|bit_cnt [0]) # ((\uart_tx_inst|bit_cnt [2]) # ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [7]) # (\uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [7]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~4 .lut_mask = 16'hFFFE; +defparam \uart_tx_inst|tx~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \uart_tx_inst|tx~3 ( +// Equation(s): +// \uart_tx_inst|tx~3_combout = (!\uart_tx_inst|bit_flag~q & !\uart_tx_inst|tx~q ) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(gnd), + .datac(gnd), + .datad(\uart_tx_inst|tx~q ), + .cin(gnd), + .combout(\uart_tx_inst|tx~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~3 .lut_mask = 16'h0055; +defparam \uart_tx_inst|tx~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \uart_tx_inst|tx~5 ( +// Equation(s): +// \uart_tx_inst|tx~5_combout = (!\uart_tx_inst|tx~2_combout & (!\uart_tx_inst|tx~3_combout & ((!\uart_tx_inst|tx~4_combout ) # (!\uart_tx_inst|always0~0_combout )))) + + .dataa(\uart_tx_inst|tx~2_combout ), + .datab(\uart_tx_inst|always0~0_combout ), + .datac(\uart_tx_inst|tx~4_combout ), + .datad(\uart_tx_inst|tx~3_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~5 .lut_mask = 16'h0015; +defparam \uart_tx_inst|tx~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N1 +dffeas \uart_tx_inst|tx ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|tx~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|tx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|tx .is_wysiwyg = "true"; +defparam \uart_tx_inst|tx .power_up = "low"; +// synopsys translate_on + +// Location: CLKCTRL_G7 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X23_Y22_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y22_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1 .lut_mask = 16'hF0FC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0 .lut_mask = 16'hBAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0 .lut_mask = 16'h4000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2 .lut_mask = 16'hFF20; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0 .lut_mask = 16'hFFAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [1])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [1]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2 .lut_mask = 16'h8C9D; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [1]))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [1])))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [1]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3 .lut_mask = 16'h5F22; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0 .lut_mask = 16'hFAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17 .lut_mask = 16'h00CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) # +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5 .lut_mask = 16'hFFEE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0 .lut_mask = 16'hFFAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [2])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [2] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0 .lut_mask = 16'hA1AB; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [2])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [2]))))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [2]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1 .lut_mask = 16'h5F30; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0 .lut_mask = 16'h5554; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ) # +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1 .lut_mask = 16'hAAA0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [0]) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [0] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1 .lut_mask = 16'h1ABA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2 .lut_mask = 16'hFAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1 .lut_mask = 16'h4055; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6 .lut_mask = 16'h0F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3 .lut_mask = 16'hF0FF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]))) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5 .lut_mask = 16'h3C00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2] $ +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4 .lut_mask = 16'h7800; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15 .lut_mask = 16'h0002; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y21_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0 .lut_mask = 16'h55CF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1 .lut_mask = 16'hF7F2; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0 .lut_mask = 16'h4CCC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2 .lut_mask = 16'h0001; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0] & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & +// (((!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0 .lut_mask = 16'h0777; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0 .lut_mask = 16'h0101; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0 .lut_mask = 16'h2022; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16 .lut_mask = 16'h4400; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0 .lut_mask = 16'h5053; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1 .lut_mask = 16'h008F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10])))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0 .lut_mask = 16'h0FDD; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1 .lut_mask = 16'hDFCE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y20_N8 +cycloneive_io_ibuf \sdram_dq[8]~input ( + .i(sdram_dq[8]), + .ibar(gnd), + .o(\sdram_dq[8]~input_o )); +// synopsys translate_off +defparam \sdram_dq[8]~input .bus_hold = "false"; +defparam \sdram_dq[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y29_N29 +cycloneive_io_ibuf \sdram_dq[9]~input ( + .i(sdram_dq[9]), + .ibar(gnd), + .o(\sdram_dq[9]~input_o )); +// synopsys translate_off +defparam \sdram_dq[9]~input .bus_hold = "false"; +defparam \sdram_dq[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y25_N1 +cycloneive_io_ibuf \sdram_dq[10]~input ( + .i(sdram_dq[10]), + .ibar(gnd), + .o(\sdram_dq[10]~input_o )); +// synopsys translate_off +defparam \sdram_dq[10]~input .bus_hold = "false"; +defparam \sdram_dq[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y26_N8 +cycloneive_io_ibuf \sdram_dq[11]~input ( + .i(sdram_dq[11]), + .ibar(gnd), + .o(\sdram_dq[11]~input_o )); +// synopsys translate_off +defparam \sdram_dq[11]~input .bus_hold = "false"; +defparam \sdram_dq[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N8 +cycloneive_io_ibuf \sdram_dq[12]~input ( + .i(sdram_dq[12]), + .ibar(gnd), + .o(\sdram_dq[12]~input_o )); +// synopsys translate_off +defparam \sdram_dq[12]~input .bus_hold = "false"; +defparam \sdram_dq[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N8 +cycloneive_io_ibuf \sdram_dq[13]~input ( + .i(sdram_dq[13]), + .ibar(gnd), + .o(\sdram_dq[13]~input_o )); +// synopsys translate_off +defparam \sdram_dq[13]~input .bus_hold = "false"; +defparam \sdram_dq[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N22 +cycloneive_io_ibuf \sdram_dq[14]~input ( + .i(sdram_dq[14]), + .ibar(gnd), + .o(\sdram_dq[14]~input_o )); +// synopsys translate_off +defparam \sdram_dq[14]~input .bus_hold = "false"; +defparam \sdram_dq[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N1 +cycloneive_io_ibuf \sdram_dq[15]~input ( + .i(sdram_dq[15]), + .ibar(gnd), + .o(\sdram_dq[15]~input_o )); +// synopsys translate_off +defparam \sdram_dq[15]~input .bus_hold = "false"; +defparam \sdram_dq[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_8_1200mv_85c_v_slow.sdo b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_8_1200mv_85c_v_slow.sdo new file mode 100644 index 0000000..5006d42 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_8_1200mv_85c_v_slow.sdo @@ -0,0 +1,19618 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "uart_sdram") + (DATE "06/02/2023 04:26:31") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1692:1692:1692) (1583:1583:1583)) + (PORT d[1] (1627:1627:1627) (1518:1518:1518)) + (PORT d[2] (1737:1737:1737) (1611:1611:1611)) + (PORT d[3] (1724:1724:1724) (1602:1602:1602)) + (PORT d[4] (1667:1667:1667) (1555:1555:1555)) + (PORT d[5] (1663:1663:1663) (1554:1554:1554)) + (PORT d[6] (1729:1729:1729) (1606:1606:1606)) + (PORT d[7] (1695:1695:1695) (1579:1579:1579)) + (PORT clk (2276:2276:2276) (2303:2303:2303)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1303:1303:1303) (1270:1270:1270)) + (PORT d[1] (1383:1383:1383) (1337:1337:1337)) + (PORT d[2] (986:986:986) (980:980:980)) + (PORT d[3] (1229:1229:1229) (1175:1175:1175)) + (PORT d[4] (1022:1022:1022) (1011:1011:1011)) + (PORT d[5] (970:970:970) (967:967:967)) + (PORT d[6] (1276:1276:1276) (1208:1208:1208)) + (PORT d[7] (1337:1337:1337) (1302:1302:1302)) + (PORT d[8] (983:983:983) (981:981:981)) + (PORT d[9] (979:979:979) (977:977:977)) + (PORT clk (2272:2272:2272) (2298:2298:2298)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2060:2060:2060) (1886:1886:1886)) + (PORT clk (2272:2272:2272) (2298:2298:2298)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2276:2276:2276) (2303:2303:2303)) + (PORT d[0] (2767:2767:2767) (2600:2600:2600)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2277:2277:2277) (2304:2304:2304)) + (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2277:2277:2277) (2304:2304:2304)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2277:2277:2277) (2304:2304:2304)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2277:2277:2277) (2304:2304:2304)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (989:989:989) (979:979:979)) + (PORT d[1] (974:974:974) (952:952:952)) + (PORT d[2] (1375:1375:1375) (1321:1321:1321)) + (PORT d[3] (1735:1735:1735) (1635:1635:1635)) + (PORT d[4] (974:974:974) (965:965:965)) + (PORT d[5] (1768:1768:1768) (1761:1761:1761)) + (PORT d[6] (1757:1757:1757) (1674:1674:1674)) + (PORT d[7] (1328:1328:1328) (1287:1287:1287)) + (PORT d[8] (1003:1003:1003) (986:986:986)) + (PORT d[9] (1472:1472:1472) (1376:1376:1376)) + (PORT clk (2226:2226:2226) (2212:2212:2212)) + (PORT ena (2597:2597:2597) (2442:2442:2442)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + (HOLD ena (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (2226:2226:2226) (2212:2212:2212)) + (PORT d[0] (2597:2597:2597) (2442:2442:2442)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2227:2227:2227) (2213:2213:2213)) + (IOPATH (posedge clk) pulse (0:0:0) (3251:3251:3251)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2227:2227:2227) (2213:2213:2213)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2227:2227:2227) (2213:2213:2213)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (820:820:820)) + (PORT datab (539:539:539) (560:560:560)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (956:956:956)) + (PORT datab (1005:1005:1005) (982:982:982)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1617:1617:1617) (1564:1564:1564)) + (PORT datab (538:538:538) (569:569:569)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (571:571:571)) + (PORT datab (866:866:866) (831:831:831)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (462:462:462)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[5\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (464:464:464)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (449:449:449)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (629:629:629)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (863:863:863) (845:845:845)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~26) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita1) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (611:611:611)) + (PORT datab (956:956:956) (934:934:934)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita2) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (449:449:449)) + (PORT datab (955:955:955) (933:933:933)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita3) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (458:458:458)) + (PORT datab (955:955:955) (933:933:933)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita4) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (600:600:600)) + (PORT datab (955:955:955) (932:932:932)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita5) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (614:614:614)) + (PORT datab (953:953:953) (931:931:931)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita6) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (613:613:613)) + (PORT datab (953:953:953) (930:930:930)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita7) + (DELAY + (ABSOLUTE + (PORT dataa (842:842:842) (823:823:823)) + (PORT datab (952:952:952) (929:929:929)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita8) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (446:446:446)) + (PORT datab (952:952:952) (929:929:929)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita9) + (DELAY + (ABSOLUTE + (PORT datab (362:362:362) (439:439:439)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn 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(261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + 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(HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5942:5942:5942) (5724:5724:5724)) + (PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5942:5942:5942) (5724:5724:5724)) + (PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5942:5942:5942) (5724:5724:5724)) + (PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[15\]) + (DELAY + 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(1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5942:5942:5942) (5724:5724:5724)) + (PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5942:5942:5942) (5724:5724:5724)) + (PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5942:5942:5942) (5724:5724:5724)) + (PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5942:5942:5942) (5724:5724:5724)) + (PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn 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(PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~0) + (DELAY + (ABSOLUTE + (PORT datab (542:542:542) (573:573:573)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (623:623:623)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (566:566:566) (584:584:584)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~6) + (DELAY + (ABSOLUTE + (PORT datab (554:554:554) (584:584:584)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (598:598:598)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (598:598:598)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (629:629:629)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (627:627:627)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (942:942:942)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~18) + (DELAY + (ABSOLUTE + (PORT datab (1008:1008:1008) (980:980:980)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (958:958:958)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~22) + (DELAY + (ABSOLUTE + (PORT datab (912:912:912) (910:910:910)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~24) + (DELAY + (ABSOLUTE + (PORT datab (559:559:559) (585:585:585)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~26) + (DELAY + (ABSOLUTE + (PORT datab (614:614:614) (618:618:618)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (623:623:623) (628:628:628)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~30) + (DELAY + (ABSOLUTE + (PORT datad (555:555:555) (569:569:569)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (445:445:445)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (448:448:448)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1892:1892:1892) (1762:1762:1762)) + (PORT datab (341:341:341) (422:422:422)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (430:430:430)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (433:433:433)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[3\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (424:424:424)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[4\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (421:421:421)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[5\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[6\]\~36) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[7\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (430:430:430)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[8\]\~40) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (419:419:419)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[9\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (429:429:429)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[10\]\~44) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (421:421:421)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[11\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (431:431:431)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[12\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (418:418:418)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[13\]\~50) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (421:421:421)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[14\]\~52) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (420:420:420)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[15\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (432:432:432)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[16\]\~56) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (421:421:421)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[17\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (431:431:431)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[18\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[19\]\~62) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[20\]\~64) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[21\]\~66) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[22\]\~68) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[23\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (436:436:436)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (433:433:433)) + (PORT datab (369:369:369) (468:468:468)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (421:421:421)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datad (324:324:324) (411:411:411)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (883:883:883)) + (PORT datab (340:340:340) (419:419:419)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (421:421:421)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (420:420:420)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (433:433:433)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[5\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (435:435:435)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[8\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (423:423:423)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[9\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (344:344:344) (427:427:427)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (448:448:448)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT asdata (1686:1686:1686) (1628:1628:1628)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1083:1083:1083)) + (PORT datab (1182:1182:1182) (1098:1098:1098)) + (PORT datad (292:292:292) (362:362:362)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5192:5192:5192) (4949:4949:4949)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (788:788:788) (716:716:716)) + (PORT datab (412:412:412) (512:512:512)) + (PORT datac (784:784:784) (707:707:707)) + (PORT datad (350:350:350) (465:465:465)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (923:923:923)) + (PORT datab (928:928:928) (877:877:877)) + (PORT datac (1148:1148:1148) (1069:1069:1069)) + (PORT datad (1275:1275:1275) (1239:1239:1239)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (523:523:523)) + (PORT datab (888:888:888) (788:788:788)) + (PORT datac (1486:1486:1486) (1370:1370:1370)) + (PORT datad (369:369:369) (468:468:468)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~1) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (523:523:523)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (773:773:773) (696:696:696)) + (PORT datad (370:370:370) (470:470:470)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (941:941:941)) + (PORT datab (369:369:369) (470:470:470)) + (PORT datac (1111:1111:1111) (997:997:997)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5192:5192:5192) (4949:4949:4949)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (421:421:421)) + (PORT datab (643:643:643) (658:658:658)) + (PORT datac (1220:1220:1220) (1194:1194:1194)) + (PORT datad (335:335:335) (438:438:438)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\~0) + (DELAY + (ABSOLUTE + (PORT datac (513:513:513) (554:554:554)) + (PORT datad (540:540:540) (561:561:561)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|WideOr5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1734:1734:1734) (1630:1630:1630)) + (PORT datad (1627:1627:1627) (1547:1547:1547)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (494:494:494)) + (PORT datab (370:370:370) (453:453:453)) + (PORT datac (244:244:244) (275:275:275)) + (PORT datad (988:988:988) (986:986:986)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (448:448:448)) + (PORT datab (411:411:411) (519:519:519)) + (PORT datac (901:901:901) (900:900:900)) + (PORT datad (1137:1137:1137) (1084:1084:1084)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector21\~0) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (493:493:493)) + (PORT datab (284:284:284) (316:316:316)) + (PORT datac (328:328:328) (411:411:411)) + (PORT datad (322:322:322) (393:393:393)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (525:525:525)) + (PORT datac (327:327:327) (430:430:430)) + (PORT datad (369:369:369) (468:468:468)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (526:526:526)) + (PORT datab (372:372:372) (473:473:473)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (369:369:369) (468:468:468)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (292:292:292) (329:329:329)) + (PORT datad (293:293:293) (324:324:324)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT ena (1037:1037:1037) (1012:1012:1012)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (463:463:463)) + (PORT datab (369:369:369) (452:452:452)) + (PORT datac (329:329:329) (413:413:413)) + (PORT datad (330:330:330) (408:408:408)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE read_valid) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5631:5631:5631) (5380:5380:5380)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~0) + (DELAY + (ABSOLUTE + (PORT datac (245:245:245) (276:276:276)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1614:1614:1614) (1562:1562:1562)) + (PORT datab (1002:1002:1002) (983:983:983)) + (PORT datac (236:236:236) (261:261:261)) + (PORT datad (247:247:247) (272:272:272)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_TMRD) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.IDLE\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1262:1262:1262) (1239:1239:1239)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1859:1859:1859)) + (PORT ena (1080:1080:1080) (1064:1064:1064)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT datab (937:937:937) (945:945:945)) + (PORT datad (962:962:962) (949:949:949)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~0) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (608:608:608)) + (PORT datab (575:575:575) (608:608:608)) + (PORT datac (914:914:914) (907:907:907)) + (PORT datad (923:923:923) (933:933:933)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~1) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (615:615:615)) + (PORT datab (369:369:369) (452:452:452)) + (PORT datac (311:311:311) (400:400:400)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~2) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (450:450:450)) + (PORT datab (368:368:368) (450:450:450)) + (PORT datac (320:320:320) (399:399:399)) + (PORT datad (329:329:329) (406:406:406)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~3) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (785:785:785)) + (PORT datab (873:873:873) (799:799:799)) + (PORT datac (940:940:940) (927:927:927)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5949:5949:5949) (5747:5747:5747)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (610:610:610)) + (PORT datab (367:367:367) (450:450:450)) + (PORT datac (308:308:308) (397:397:397)) + (PORT datad (328:328:328) (401:401:401)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (447:447:447)) + (PORT datab (280:280:280) (305:305:305)) + (PORT datac (327:327:327) (411:411:411)) + (PORT datad (321:321:321) (392:392:392)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (430:430:430)) + (PORT datac (959:959:959) (952:952:952)) + (PORT datad (1282:1282:1282) (1257:1257:1257)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~2) + (DELAY + (ABSOLUTE + (PORT datac (449:449:449) (435:435:435)) + (PORT datad (313:313:313) (359:359:359)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT asdata (983:983:983) (1016:1016:1016)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (312:312:312) (400:400:400)) + (PORT datad (856:856:856) (810:810:810)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT asdata (1704:1704:1704) (1676:1676:1676)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (439:439:439)) + (PORT datac (311:311:311) (399:399:399)) + (PORT datad (855:855:855) (809:809:809)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (1328:1328:1328) (1293:1293:1293)) + (PORT datab (1350:1350:1350) (1302:1302:1302)) + (PORT datac (1301:1301:1301) (1278:1278:1278)) + (PORT datad (255:255:255) (280:280:280)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datab (1320:1320:1320) (1297:1297:1297)) + (PORT datac (239:239:239) (265:265:265)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (970:970:970)) + (PORT datab (968:968:968) (907:907:907)) + (PORT datad (969:969:969) (971:971:971)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datab (970:970:970) (910:910:910)) + (PORT datad (970:970:970) (972:972:972)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT datab (354:354:354) (440:440:440)) + (PORT datac (322:322:322) (400:400:400)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (632:632:632)) + (PORT datac (354:354:354) (440:440:440)) + (PORT datad (340:340:340) (421:421:421)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT dataa (1333:1333:1333) (1273:1273:1273)) + (PORT datac (330:330:330) (434:434:434)) + (PORT datad (257:257:257) (283:283:283)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (512:512:512) (551:551:551)) + (PORT datad (843:843:843) (794:794:794)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (959:959:959)) + (PORT datab (943:943:943) (935:935:935)) + (PORT datac (501:501:501) (485:485:485)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT asdata (1737:1737:1737) (1682:1682:1682)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (2053:2053:2053) (1939:1939:1939)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (859:859:859) (858:858:858)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datac (331:331:331) (435:435:435)) + (PORT datad (258:258:258) (283:283:283)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (313:313:313) (402:402:402)) + (PORT datad (526:526:526) (557:557:557)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT datac (313:313:313) (402:402:402)) + (PORT datad (525:525:525) (557:557:557)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (PORT datab (360:360:360) (437:437:437)) + (PORT datac (320:320:320) (398:398:398)) + (PORT datad (320:320:320) (391:391:391)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5631:5631:5631) (5380:5380:5380)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5631:5631:5631) (5380:5380:5380)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5631:5631:5631) (5380:5380:5380)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5631:5631:5631) (5380:5380:5380)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (PORT datab (359:359:359) (435:435:435)) + (PORT datac (319:319:319) (396:396:396)) + (PORT datad (509:509:509) (537:537:537)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (PORT datab (358:358:358) (435:435:435)) + (PORT datac (318:318:318) (396:396:396)) + (PORT datad (320:320:320) (390:390:390)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (589:589:589)) + (PORT datab (362:362:362) (439:439:439)) + (PORT datac (321:321:321) (399:399:399)) + (PORT datad (322:322:322) (392:392:392)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (314:314:314)) + (PORT datab (276:276:276) (300:300:300)) + (PORT datac (239:239:239) (265:265:265)) + (PORT datad (831:831:831) (765:765:765)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE read_valid\~0) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (819:819:819)) + (PORT datab (838:838:838) (798:798:798)) + (PORT datac (937:937:937) (883:883:883)) + (PORT datad (322:322:322) (392:392:392)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE read_valid\~1) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (863:863:863)) + (PORT datab (929:929:929) (864:864:864)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (605:605:605)) + (PORT datab (363:363:363) (440:440:440)) + (PORT datad (507:507:507) (489:489:489)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (642:642:642)) + (PORT datab (400:400:400) (511:511:511)) + (PORT datac (361:361:361) (468:468:468)) + (PORT datad (309:309:309) (389:389:389)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (378:378:378) (468:468:468)) + (PORT datac (310:310:310) (401:401:401)) + (PORT datad (303:303:303) (376:376:376)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~2) + (DELAY + (ABSOLUTE + (PORT datab (279:279:279) (304:304:304)) + (PORT datac (348:348:348) (427:427:427)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (923:923:923)) + (PORT datab (981:981:981) (963:963:963)) + (PORT datad (833:833:833) (777:777:777)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (452:452:452)) + (PORT datab (353:353:353) (442:442:442)) + (PORT datac (312:312:312) (401:401:401)) + (PORT datad (312:312:312) (392:392:392)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT asdata (1997:1997:1997) (1917:1917:1917)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (PORT ena (2086:2086:2086) (1974:1974:1974)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (462:462:462)) + (PORT datab (1255:1255:1255) (1234:1234:1234)) + (PORT datad (1253:1253:1253) (1214:1214:1214)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (2163:2163:2163) (2083:2083:2083)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1708:1708:1708) (1615:1615:1615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (619:619:619)) + (PORT datab (570:570:570) (596:596:596)) + (PORT datad (331:331:331) (405:405:405)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (461:461:461)) + (PORT datab (593:593:593) (620:620:620)) + (PORT datad (564:564:564) (581:581:581)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT datac (447:447:447) (431:431:431)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1244:1244:1244)) + (PORT datab (969:969:969) (963:963:963)) + (PORT datad (323:323:323) (393:393:393)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (590:590:590)) + (PORT datab (360:360:360) (436:436:436)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (458:458:458)) + (PORT datab (361:361:361) (438:438:438)) + (PORT datad (321:321:321) (392:392:392)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (814:814:814) (765:765:765)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1130:1130:1130)) + (PORT datab (1264:1264:1264) (1171:1171:1171)) + (PORT datac (1253:1253:1253) (1164:1164:1164)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (445:445:445)) + (PORT datab (366:366:366) (449:449:449)) + (PORT datad (572:572:572) (592:592:592)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (660:660:660)) + (PORT datab (368:368:368) (451:451:451)) + (PORT datad (338:338:338) (419:419:419)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (2530:2530:2530) (2385:2385:2385)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT ena (1720:1720:1720) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (772:772:772)) + (PORT datab (484:484:484) (468:468:468)) + (PORT datad (353:353:353) (427:427:427)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (483:483:483)) + (PORT datab (626:626:626) (638:638:638)) + (PORT datad (564:564:564) (583:583:583)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (613:613:613)) + (PORT datab (386:386:386) (463:463:463)) + (PORT datad (560:560:560) (582:582:582)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (515:515:515)) + (PORT datab (548:548:548) (586:586:586)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (382:382:382)) + (PORT datac (780:780:780) (746:746:746)) + (PORT datad (855:855:855) (796:796:796)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1358:1358:1358) (1307:1307:1307)) + (PORT datab (1780:1780:1780) (1689:1689:1689)) + (PORT datad (499:499:499) (523:523:523)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (580:580:580)) + (PORT datab (947:947:947) (961:961:961)) + (PORT datad (1275:1275:1275) (1245:1245:1245)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (1312:1312:1312) (1309:1309:1309)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (923:923:923)) + (PORT datab (368:368:368) (451:451:451)) + (PORT datad (321:321:321) (391:391:391)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (976:976:976) (910:910:910)) + (PORT datad (515:515:515) (546:546:546)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (1349:1349:1349) (1318:1318:1318)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (584:584:584)) + (PORT datab (1039:1039:1039) (1008:1008:1008)) + (PORT datad (1278:1278:1278) (1236:1236:1236)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (462:462:462)) + (PORT datab (320:320:320) (357:357:357)) + (PORT datac (337:337:337) (425:425:425)) + (PORT datad (338:338:338) (418:418:418)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (602:602:602)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (302:302:302) (386:386:386)) + (PORT datad (302:302:302) (379:379:379)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (343:343:343) (425:425:425)) + (PORT datac (302:302:302) (386:386:386)) + (PORT datad (302:302:302) (379:379:379)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (433:433:433)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (789:789:789)) + (PORT datab (276:276:276) (300:300:300)) + (PORT datac (236:236:236) (261:261:261)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (435:435:435)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (303:303:303) (379:379:379)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (600:600:600)) + (PORT datab (341:341:341) (424:424:424)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[8\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (842:842:842)) + (PORT datab (837:837:837) (797:797:797)) + (PORT datac (859:859:859) (812:812:812)) + (PORT datad (849:849:849) (802:802:802)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[15\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (842:842:842)) + (PORT datab (839:839:839) (799:799:799)) + (PORT datac (861:861:861) (813:813:813)) + (PORT datad (851:851:851) (803:803:803)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[15\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (552:552:552) (512:512:512)) + (PORT datab (1006:1006:1006) (986:986:986)) + (PORT datad (935:935:935) (923:923:923)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[14\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (982:982:982)) + (PORT datab (486:486:486) (466:466:466)) + (PORT datad (943:943:943) (934:934:934)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[13\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (980:980:980)) + (PORT datab (740:740:740) (682:682:682)) + (PORT datad (945:945:945) (936:936:936)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[12\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (981:981:981)) + (PORT datab (540:540:540) (498:498:498)) + (PORT datad (944:944:944) (936:936:936)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[9\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (381:381:381)) + (PORT datab (878:878:878) (805:805:805)) + (PORT datad (290:290:290) (317:317:317)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[11\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (381:381:381)) + (PORT datab (837:837:837) (790:790:790)) + (PORT datad (291:291:291) (319:319:319)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[10\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (381:381:381)) + (PORT datab (828:828:828) (784:784:784)) + (PORT datad (291:291:291) (319:319:319)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[8\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (381:381:381)) + (PORT datab (909:909:909) (833:833:833)) + (PORT datad (292:292:292) (319:319:319)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[7\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (975:975:975)) + (PORT datab (543:543:543) (505:505:505)) + (PORT datad (950:950:950) (943:943:943)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (977:977:977)) + (PORT datab (544:544:544) (507:507:507)) + (PORT datad (947:947:947) (940:940:940)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[5\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (977:977:977) (978:978:978)) + (PORT datab (489:489:489) (474:474:474)) + (PORT datad (947:947:947) (939:939:939)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (979:979:979)) + (PORT datab (547:547:547) (510:510:510)) + (PORT datad (946:946:946) (938:938:938)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (484:484:484)) + (PORT datab (1011:1011:1011) (993:993:993)) + (PORT datad (930:930:930) (916:916:916)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (518:518:518)) + (PORT datab (1011:1011:1011) (993:993:993)) + (PORT datad (930:930:930) (917:917:917)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (485:485:485)) + (PORT datab (1012:1012:1012) (995:995:995)) + (PORT datad (929:929:929) (915:915:915)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (980:980:980)) + (PORT datab (548:548:548) (511:511:511)) + (PORT datad (945:945:945) (937:937:937)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1326:1326:1326) (1238:1238:1238)) + (PORT datab (1022:1022:1022) (1001:1001:1001)) + (PORT datad (569:569:569) (588:588:588)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (653:653:653)) + (PORT datab (577:577:577) (606:606:606)) + (PORT datad (951:951:951) (933:933:933)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (914:914:914)) + (PORT datab (588:588:588) (611:611:611)) + (PORT datac (901:901:901) (890:890:890)) + (PORT datad (878:878:878) (878:878:878)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (316:316:316)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (1650:1650:1650) (1527:1527:1527)) + (PORT datad (240:240:240) (258:258:258)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (917:917:917)) + (PORT datab (987:987:987) (968:968:968)) + (PORT datad (320:320:320) (390:390:390)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb\|data_wire\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (1912:1912:1912) (1751:1751:1751)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (852:852:852)) + (PORT datab (1154:1154:1154) (1044:1044:1044)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (632:632:632)) + (PORT datab (542:542:542) (574:574:574)) + (PORT datad (1623:1623:1623) (1547:1547:1547)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (494:494:494)) + (PORT datab (279:279:279) (304:304:304)) + (PORT datac (446:446:446) (417:417:417)) + (PORT datad (298:298:298) (339:339:339)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1320:1320:1320) (1253:1253:1253)) + (PORT datab (366:366:366) (466:466:466)) + (PORT datad (909:909:909) (894:894:894)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (449:449:449)) + (PORT datab (965:965:965) (948:948:948)) + (PORT datac (1383:1383:1383) (1333:1333:1333)) + (PORT datad (325:325:325) (414:414:414)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (475:475:475)) + (PORT datab (368:368:368) (468:468:468)) + (PORT datac (888:888:888) (879:879:879)) + (PORT datad (881:881:881) (879:879:879)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (872:872:872)) + (PORT datab (343:343:343) (386:386:386)) + (PORT datad (486:486:486) (459:459:459)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (912:912:912)) + (PORT datab (553:553:553) (585:585:585)) + (PORT datad (542:542:542) (562:562:562)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (971:971:971)) + (PORT datab (362:362:362) (439:439:439)) + (PORT datad (864:864:864) (838:838:838)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (474:474:474)) + (PORT datab (981:981:981) (954:954:954)) + (PORT datad (874:874:874) (875:875:875)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (472:472:472)) + (PORT datab (376:376:376) (466:466:466)) + (PORT datac (1231:1231:1231) (1184:1184:1184)) + (PORT datad (361:361:361) (441:441:441)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|rd_flag) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5995:5995:5995) (5789:5789:5789)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (447:447:447)) + (PORT datab (349:349:349) (438:438:438)) + (PORT datac (308:308:308) (398:398:398)) + (PORT datad (311:311:311) (391:391:391)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|cntr_cout\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1329:1329:1329) (1316:1316:1316)) + (PORT datab (922:922:922) (929:929:929)) + (PORT datac (477:477:477) (450:450:450)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (PORT ena (1757:1757:1757) (1679:1679:1679)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (435:435:435)) + (PORT datab (344:344:344) (426:426:426)) + (PORT datac (303:303:303) (387:387:387)) + (PORT datad (305:305:305) (382:382:382)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (303:303:303) (387:387:387)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (471:471:471)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (302:302:302) (379:379:379)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|rd_flag\~0) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (882:882:882)) + (PORT datab (999:999:999) (985:985:985)) + (PORT datad (246:246:246) (271:271:271)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (464:464:464)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (330:330:330) (432:432:432)) + (PORT datad (266:266:266) (302:302:302)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1237:1237:1237) (1198:1198:1198)) + (PORT datab (379:379:379) (469:469:469)) + (PORT datac (336:336:336) (426:426:426)) + (PORT datad (329:329:329) (407:407:407)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|start_nedge) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (1291:1291:1291) (1207:1207:1207)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (424:424:424)) + (PORT datad (321:321:321) (392:392:392)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (945:945:945)) + (PORT datab (330:330:330) (363:363:363)) + (PORT datad (865:865:865) (859:859:859)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1504:1504:1504) (1434:1434:1434)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1180:1180:1180) (1142:1142:1142)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (323:323:323) (394:394:394)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (873:873:873) (870:870:870)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (542:542:542) (562:562:562)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tx\~output) + (DELAY + (ABSOLUTE + (PORT i (2462:2462:2462) (2477:2477:2477)) + (IOPATH i o (3336:3336:3336) (3399:3399:3399)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_clk\~output) + (DELAY + (ABSOLUTE + (PORT i (1622:1622:1622) (1573:1573:1573)) + (IOPATH i o (3251:3251:3251) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_cas_n\~output) + (DELAY + (ABSOLUTE + (PORT i (2191:2191:2191) (2040:2040:2040)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_ras_n\~output) + (DELAY + (ABSOLUTE + (PORT i (2334:2334:2334) (2117:2117:2117)) + (IOPATH i o (4708:4708:4708) (4746:4746:4746)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_we_n\~output) + (DELAY + (ABSOLUTE + (PORT i (2385:2385:2385) (2240:2240:2240)) + (IOPATH i o (3291:3291:3291) (3194:3194:3194)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_ba\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3348:3348:3348) (3145:3145:3145)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_ba\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3636:3636:3636) (3398:3398:3398)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2660:2660:2660) (2398:2398:2398)) + (IOPATH i o (3281:3281:3281) (3184:3184:3184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2653:2653:2653) (2401:2401:2401)) + (IOPATH i o (3429:3429:3429) (3366:3366:3366)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2653:2653:2653) (2401:2401:2401)) + (IOPATH i o (3429:3429:3429) (3366:3366:3366)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3335:3335:3335) (3152:3152:3152)) + (IOPATH i o (3429:3429:3429) (3366:3366:3366)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3060:3060:3060) (2762:2762:2762)) + (IOPATH i o (3429:3429:3429) (3366:3366:3366)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3079:3079:3079) (2783:2783:2783)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (4466:4466:4466) (4181:4181:4181)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (4050:4050:4050) (3800:3800:3800)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (4473:4473:4473) (4187:4187:4187)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2666:2666:2666) (2508:2508:2508)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2685:2685:2685) (2509:2509:2509)) + (IOPATH i o (3291:3291:3291) (3194:3194:3194)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2666:2666:2666) (2508:2508:2508)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3225:3225:3225) (2988:2988:2988)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1550:1550:1550) (1417:1417:1417)) + (PORT oe (1648:1648:1648) (1586:1586:1586)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1491:1491:1491) (1367:1367:1367)) + (PORT oe (1648:1648:1648) (1586:1586:1586)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1577:1577:1577) (1450:1450:1450)) + (PORT oe (2036:2036:2036) (1919:1919:1919)) + (IOPATH i o (3231:3231:3231) (3134:3134:3134)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1113:1113:1113) (1003:1003:1003)) + (PORT oe (1252:1252:1252) (1208:1208:1208)) + (IOPATH i o (3261:3261:3261) (3164:3164:3164)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1135:1135:1135) (1030:1030:1030)) + (PORT oe (1252:1252:1252) (1208:1208:1208)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1522:1522:1522) (1395:1395:1395)) + (PORT oe (2036:2036:2036) (1919:1919:1919)) + (IOPATH i o (3251:3251:3251) (3154:3154:3154)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1541:1541:1541) (1413:1413:1413)) + (PORT oe (1648:1648:1648) (1586:1586:1586)) + (IOPATH i o (3281:3281:3281) (3184:3184:3184)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1200:1200:1200) (1108:1108:1108)) + (PORT oe (1648:1648:1648) (1586:1586:1586)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1637:1637:1637) (1534:1534:1534)) + (PORT oe (2662:2662:2662) (2485:2485:2485)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + (IOPATH oe o (3433:3433:3433) (3294:3294:3294)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1745:1745:1745) (1590:1590:1590)) + (PORT oe (2255:2255:2255) (2128:2128:2128)) + (IOPATH i o (3281:3281:3281) (3184:3184:3184)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2059:2059:2059) (1828:1828:1828)) + (PORT oe (1931:1931:1931) (1833:1833:1833)) + (IOPATH i o (3419:3419:3419) (3356:3356:3356)) + (IOPATH oe o (3433:3433:3433) (3294:3294:3294)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2200:2200:2200) (2043:2043:2043)) + (PORT oe (2276:2276:2276) (2145:2145:2145)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + (IOPATH oe o (3433:3433:3433) (3294:3294:3294)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1838:1838:1838) (1674:1674:1674)) + (PORT oe (2316:2316:2316) (2194:2194:2194)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + (IOPATH oe o (3433:3433:3433) (3294:3294:3294)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1495:1495:1495) (1364:1364:1364)) + (PORT oe (2323:2323:2323) (2202:2202:2202)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + (IOPATH oe o (3433:3433:3433) (3294:3294:3294)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1746:1746:1746) (1547:1547:1547)) + (PORT oe (2323:2323:2323) (2202:2202:2202)) + (IOPATH i o (4760:4760:4760) (4817:4817:4817)) + (IOPATH oe o (4805:4805:4805) (4785:4785:4785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1655:1655:1655) (1474:1474:1474)) + (PORT oe (2323:2323:2323) (2202:2202:2202)) + (IOPATH i o (3291:3291:3291) (3218:3218:3218)) + (IOPATH oe o (3335:3335:3335) (3194:3194:3194)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (609:609:609)) + (PORT datab (358:358:358) (434:434:434)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (806:806:806) (852:852:852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (5286:5286:5286) (5286:5286:5286)) + (PORT inclk[0] (2340:2340:2340) (2340:2340:2340)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (2135:2135:2135) (2190:2190:2190)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5631:5631:5631) (5380:5380:5380)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (4719:4719:4719) (4925:4925:4925)) + (PORT datac (1430:1430:1430) (1466:1466:1466)) + (PORT datad (293:293:293) (362:362:362)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2483:2483:2483) (2391:2391:2391)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (349:349:349) (435:435:435)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (443:443:443)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (452:452:452)) + (PORT datab (588:588:588) (611:611:611)) + (PORT datac (312:312:312) (402:402:402)) + (PORT datad (314:314:314) (394:394:394)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (636:636:636)) + (PORT datab (343:343:343) (427:427:427)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datac (848:848:848) (818:818:818)) + (PORT datad (530:530:530) (558:558:558)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (647:647:647)) + (PORT datab (627:627:627) (636:636:636)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (534:534:534) (554:554:554)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (447:447:447)) + (PORT datab (475:475:475) (459:459:459)) + (PORT datac (483:483:483) (457:457:457)) + (PORT datad (237:237:237) (256:256:256)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (453:453:453)) + (PORT datab (589:589:589) (612:612:612)) + (PORT datac (312:312:312) (402:402:402)) + (PORT datad (314:314:314) (394:394:394)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (449:449:449)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (613:613:613)) + (PORT datab (625:625:625) (633:633:633)) + (PORT datac (848:848:848) (817:817:817)) + (PORT datad (533:533:533) (552:552:552)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (504:504:504)) + (PORT datab (534:534:534) (496:496:496)) + (PORT datac (577:577:577) (599:599:599)) + (PORT datad (240:240:240) (258:258:258)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (430:430:430)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (345:345:345) (427:427:427)) + (PORT datac (304:304:304) (388:388:388)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (461:461:461)) + (PORT datab (305:305:305) (343:343:343)) + (PORT datac (327:327:327) (429:429:429)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_flag) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_flag) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (1718:1718:1718) (1681:1681:1681)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (465:465:465)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a0) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT ena (2467:2467:2467) (2319:2319:2319)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (463:463:463)) + (PORT datab (2041:2041:2041) (1890:1890:1890)) + (PORT datad (561:561:561) (599:599:599)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (653:653:653)) + (PORT datab (378:378:378) (467:467:467)) + (PORT datac (318:318:318) (414:414:414)) + (PORT datad (1679:1679:1679) (1566:1566:1566)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (236:236:236) (255:255:255)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (322:322:322) (360:360:360)) + (PORT datad (558:558:558) (589:589:589)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~10) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (645:645:645)) + (PORT datab (380:380:380) (470:470:470)) + (PORT datac (354:354:354) (453:453:453)) + (PORT datad (560:560:560) (592:592:592)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT ena (2467:2467:2467) (2319:2319:2319)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (498:498:498)) + (PORT datab (397:397:397) (493:493:493)) + (PORT datad (557:557:557) (588:588:588)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (480:480:480)) + (PORT datab (323:323:323) (361:361:361)) + (PORT datac (352:352:352) (451:451:451)) + (PORT datad (330:330:330) (403:403:403)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (822:822:822) (761:761:761)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (521:521:521)) + (PORT datad (819:819:819) (773:773:773)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (950:950:950)) + (PORT datab (369:369:369) (467:467:467)) + (PORT datac (364:364:364) (472:472:472)) + (PORT datad (357:357:357) (447:447:447)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1141:1141:1141) (1149:1149:1149)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (497:497:497)) + (PORT datab (367:367:367) (465:465:465)) + (PORT datac (364:364:364) (472:472:472)) + (PORT datad (819:819:819) (773:773:773)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8\~0) + (DELAY + (ABSOLUTE + (PORT datad (432:432:432) (405:405:405)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (497:497:497)) + (PORT datab (368:368:368) (466:466:466)) + (PORT datac (362:362:362) (469:469:469)) + (PORT datad (818:818:818) (772:772:772)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10\~0) + (DELAY + (ABSOLUTE + (PORT datab (375:375:375) (469:469:469)) + (PORT datad (457:457:457) (426:426:426)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (478:478:478)) + (PORT datad (333:333:333) (424:424:424)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT datab (372:372:372) (465:465:465)) + (PORT datac (311:311:311) (402:402:402)) + (PORT datad (790:790:790) (780:780:780)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1306:1306:1306) (1246:1246:1246)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (416:416:416)) + (PORT datac (898:898:898) (891:891:891)) + (PORT datad (1121:1121:1121) (1075:1075:1075)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|parity9) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT ena (2467:2467:2467) (2319:2319:2319)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (649:649:649)) + (PORT datab (376:376:376) (465:465:465)) + (PORT datac (317:317:317) (412:412:412)) + (PORT datad (1677:1677:1677) (1565:1565:1565)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (478:478:478)) + (PORT datab (322:322:322) (360:360:360)) + (PORT datac (351:351:351) (450:450:450)) + (PORT datad (329:329:329) (403:403:403)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (523:523:523)) + (PORT datab (860:860:860) (816:816:816)) + (PORT datad (356:356:356) (446:446:446)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (778:778:778) (859:859:859)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1306:1306:1306) (1246:1246:1246)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (354:354:354) (449:449:449)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (432:432:432)) + (PORT datab (341:341:341) (423:423:423)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (467:467:467)) + (PORT datab (361:361:361) (458:458:458)) + (PORT datac (320:320:320) (414:414:414)) + (PORT datad (322:322:322) (405:405:405)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (867:867:867)) + (PORT datab (589:589:589) (622:622:622)) + (PORT datac (501:501:501) (510:510:510)) + (PORT datad (498:498:498) (472:472:472)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (333:333:333) (425:425:425)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1306:1306:1306) (1246:1246:1246)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (991:991:991) (1016:1016:1016)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1148:1148:1148) (1098:1098:1098)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (789:789:789) (779:779:779)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1306:1306:1306) (1246:1246:1246)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (332:332:332) (406:406:406)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1283:1283:1283) (1215:1215:1215)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1145:1145:1145) (1104:1104:1104)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (617:617:617)) + (PORT datab (341:341:341) (423:423:423)) + (PORT datac (309:309:309) (398:398:398)) + (PORT datad (521:521:521) (553:553:553)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (358:358:358) (448:448:448)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1141:1141:1141) (1149:1149:1149)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (2366:2366:2366) (2261:2261:2261)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT asdata (1242:1242:1242) (1212:1212:1212)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (437:437:437)) + (PORT datab (295:295:295) (332:332:332)) + (PORT datac (312:312:312) (402:402:402)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (1372:1372:1372) (1359:1359:1359)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1141:1141:1141) (1149:1149:1149)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1256:1256:1256) (1213:1213:1213)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (332:332:332) (406:406:406)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (433:433:433)) + (PORT datab (295:295:295) (331:331:331)) + (PORT datac (312:312:312) (402:402:402)) + (PORT datad (294:294:294) (363:363:363)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (296:296:296) (334:334:334)) + (PORT datad (1292:1292:1292) (1256:1256:1256)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (803:803:803) (886:886:886)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT ena (2467:2467:2467) (2319:2319:2319)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1705:1705:1705) (1625:1625:1625)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (821:821:821) (912:912:912)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT ena (2467:2467:2467) (2319:2319:2319)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT asdata (1711:1711:1711) (1670:1670:1670)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (502:502:502)) + (PORT datab (361:361:361) (437:437:437)) + (PORT datad (1289:1289:1289) (1253:1253:1253)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (500:500:500)) + (PORT datab (294:294:294) (332:332:332)) + (PORT datac (321:321:321) (399:399:399)) + (PORT datad (1291:1291:1291) (1254:1254:1254)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (824:824:824) (767:767:767)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (827:827:827) (926:926:926)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1141:1141:1141) (1149:1149:1149)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT asdata (1943:1943:1943) (1841:1841:1841)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (974:974:974)) + (PORT datab (384:384:384) (461:461:461)) + (PORT datad (328:328:328) (402:402:402)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT datad (364:364:364) (445:445:445)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (PORT ena (1757:1757:1757) (1679:1679:1679)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (668:668:668)) + (PORT datab (379:379:379) (470:470:470)) + (PORT datad (964:964:964) (921:921:921)) + (IOPATH dataa combout (405:405:405) (407:407:407)) + (IOPATH datab combout (410:410:410) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (1169:1169:1169) (1119:1119:1119)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1141:1141:1141) (1149:1149:1149)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT asdata (2501:2501:2501) (2388:2388:2388)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (552:552:552) (590:590:590)) + (PORT datab (1313:1313:1313) (1280:1280:1280)) + (PORT datad (1287:1287:1287) (1255:1255:1255)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1166:1166:1166)) + (PORT datab (278:278:278) (304:304:304)) + (PORT datac (1178:1178:1178) (1083:1083:1083)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (1685:1685:1685) (1617:1617:1617)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (PORT ena (1106:1106:1106) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT asdata (2051:2051:2051) (1920:1920:1920)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (2053:2053:2053) (1939:1939:1939)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (852:852:852)) + (PORT datab (841:841:841) (817:817:817)) + (PORT datad (1261:1261:1261) (1212:1212:1212)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1991:1991:1991) (1909:1909:1909)) + (PORT datab (628:628:628) (636:636:636)) + (PORT datad (516:516:516) (536:536:536)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (1254:1254:1254) (1177:1177:1177)) + (PORT datac (1192:1192:1192) (1090:1090:1090)) + (PORT datad (1865:1865:1865) (1684:1684:1684)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (487:487:487) (460:460:460)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (1738:1738:1738) (1676:1676:1676)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (PORT ena (1106:1106:1106) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (473:473:473)) + (PORT datab (976:976:976) (960:960:960)) + (PORT datad (1553:1553:1553) (1445:1445:1445)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (1391:1391:1391) (1386:1386:1386)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (PORT ena (1106:1106:1106) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (794:794:794) (888:888:888)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1141:1141:1141) (1149:1149:1149)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (1260:1260:1260) (1227:1227:1227)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (475:475:475)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datad (886:886:886) (882:882:882)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (912:912:912)) + (PORT datab (360:360:360) (437:437:437)) + (PORT datad (1175:1175:1175) (1138:1138:1138)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (313:313:313)) + (PORT datab (277:277:277) (303:303:303)) + (PORT datad (870:870:870) (877:877:877)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT datab (1169:1169:1169) (1068:1068:1068)) + (PORT datac (779:779:779) (726:726:726)) + (PORT datad (1194:1194:1194) (1114:1114:1114)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1561:1561:1561) (1410:1410:1410)) + (PORT datab (1614:1614:1614) (1540:1540:1540)) + (PORT datac (798:798:798) (776:776:776)) + (PORT datad (1245:1245:1245) (1176:1176:1176)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT asdata (2446:2446:2446) (2316:2316:2316)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (2053:2053:2053) (1939:1939:1939)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6\~0) + (DELAY + (ABSOLUTE + (PORT datab (303:303:303) (344:344:344)) + (PORT datad (1309:1309:1309) (1266:1266:1266)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (1631:1631:1631) (1569:1569:1569)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (PORT ena (1106:1106:1106) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (474:474:474)) + (PORT datab (577:577:577) (606:606:606)) + (PORT datac (321:321:321) (399:399:399)) + (PORT datad (545:545:545) (567:567:567)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (1327:1327:1327) (1265:1265:1265)) + (PORT datab (364:364:364) (463:463:463)) + (PORT datac (321:321:321) (399:399:399)) + (PORT datad (253:253:253) (277:277:277)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (340:340:340) (429:429:429)) + (PORT datad (1151:1151:1151) (1048:1048:1048)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (1991:1991:1991) (1909:1909:1909)) + (PORT datac (337:337:337) (426:426:426)) + (PORT datad (1150:1150:1150) (1047:1047:1047)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (571:571:571) (590:590:590)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (1625:1625:1625) (1569:1569:1569)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1141:1141:1141) (1149:1149:1149)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (888:888:888) (884:884:884)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (515:515:515) (544:544:544)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (958:958:958)) + (PORT datab (942:942:942) (934:934:934)) + (PORT datac (500:500:500) (484:484:484)) + (PORT datad (887:887:887) (876:876:876)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (1292:1292:1292) (1239:1239:1239)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (2053:2053:2053) (1939:1939:1939)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT asdata (1767:1767:1767) (1710:1710:1710)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (2053:2053:2053) (1939:1939:1939)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (1989:1989:1989) (1906:1906:1906)) + (PORT datab (590:590:590) (613:613:613)) + (PORT datac (338:338:338) (427:427:427)) + (PORT datad (1151:1151:1151) (1048:1048:1048)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datac (864:864:864) (867:867:867)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (417:417:417)) + (PORT datab (966:966:966) (938:938:938)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1589:1589:1589) (1501:1501:1501)) + (PORT datab (934:934:934) (920:920:920)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (925:925:925)) + (PORT datab (931:931:931) (932:932:932)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (921:921:921)) + (PORT datab (839:839:839) (807:807:807)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (860:860:860)) + (PORT datab (866:866:866) (829:829:829)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datab (355:355:355) (441:441:441)) + (PORT datac (254:254:254) (294:294:294)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (785:785:785)) + (PORT datab (854:854:854) (821:821:821)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (574:574:574)) + (PORT datab (805:805:805) (783:783:783)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (314:314:314)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (238:238:238) (265:265:265)) + (PORT datad (240:240:240) (258:258:258)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (237:237:237) (256:256:256)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1372:1372:1372) (1315:1315:1315)) + (PORT datab (982:982:982) (970:970:970)) + (PORT datac (260:260:260) (304:304:304)) + (PORT datad (920:920:920) (901:901:901)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9\~0) + (DELAY + (ABSOLUTE + (PORT datab (287:287:287) (316:316:316)) + (PORT datad (330:330:330) (407:407:407)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (1366:1366:1366) (1359:1359:1359)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (PORT ena (1106:1106:1106) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT datac (339:339:339) (430:430:430)) + (PORT datad (330:330:330) (426:426:426)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (479:479:479)) + (PORT datac (338:338:338) (428:428:428)) + (PORT datad (550:550:550) (572:572:572)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (611:611:611)) + (PORT datad (793:793:793) (773:773:773)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_wr_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2267:2267:2267) (2132:2132:2132)) + (PORT datab (302:302:302) (326:326:326)) + (PORT datac (265:265:265) (290:290:290)) + (PORT datad (266:266:266) (283:283:283)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_wr_req) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (840:840:840)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (PORT ena (1139:1139:1139) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (845:845:845)) + (PORT datab (337:337:337) (384:384:384)) + (PORT datad (552:552:552) (579:579:579)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1730:1730:1730) (1656:1656:1656)) + (PORT datab (1737:1737:1737) (1662:1662:1662)) + (PORT datac (949:949:949) (928:928:928)) + (PORT datad (2095:2095:2095) (1988:1988:1988)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1708:1708:1708) (1615:1615:1615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (309:309:309) (358:358:358)) + (PORT datab (387:387:387) (473:473:473)) + (PORT datad (322:322:322) (393:393:393)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~10) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (916:916:916)) + (PORT datab (1720:1720:1720) (1630:1630:1630)) + (PORT datac (905:905:905) (880:880:880)) + (PORT datad (833:833:833) (827:827:827)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1708:1708:1708) (1615:1615:1615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (463:463:463)) + (PORT datab (320:320:320) (357:357:357)) + (PORT datac (337:337:337) (426:426:426)) + (PORT datad (338:338:338) (419:419:419)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8\~0) + (DELAY + (ABSOLUTE + (PORT datad (827:827:827) (766:766:766)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (807:807:807)) + (PORT datad (342:342:342) (427:427:427)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (806:806:806)) + (PORT datab (384:384:384) (471:471:471)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT datab (378:378:378) (465:465:465)) + (PORT datac (331:331:331) (414:414:414)) + (PORT datad (331:331:331) (408:408:408)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (PORT ena (1742:1742:1742) (1651:1651:1651)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (414:414:414)) + (PORT datac (295:295:295) (373:373:373)) + (PORT datad (1299:1299:1299) (1243:1243:1243)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|parity6) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1708:1708:1708) (1615:1615:1615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (464:464:464)) + (PORT datab (343:343:343) (392:392:392)) + (PORT datac (800:800:800) (791:791:791)) + (PORT datad (544:544:544) (571:571:571)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (607:607:607)) + (PORT datab (593:593:593) (620:620:620)) + (PORT datac (264:264:264) (309:309:309)) + (PORT datad (345:345:345) (429:429:429)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5\~0) + (DELAY + (ABSOLUTE + (PORT datab (278:278:278) (303:303:303)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (501:501:501)) + (PORT datab (378:378:378) (462:462:462)) + (PORT datad (545:545:545) (574:574:574)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (858:858:858)) + (PORT datab (925:925:925) (934:934:934)) + (PORT datad (340:340:340) (421:421:421)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (630:630:630)) + (PORT datab (970:970:970) (978:978:978)) + (PORT datac (2000:2000:2000) (1888:1888:1888)) + (PORT datad (855:855:855) (827:827:827)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (357:357:357) (447:447:447)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|rd_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (645:645:645)) + (PORT datab (1212:1212:1212) (1182:1182:1182)) + (PORT datad (265:265:265) (297:297:297)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|rd_en) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (453:453:453)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (465:465:465)) + (PORT datac (320:320:320) (414:414:414)) + (PORT datad (322:322:322) (405:405:405)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (376:376:376) (465:465:465)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[5\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[8\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (370:370:370) (450:450:450)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[9\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (462:462:462)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT datac (903:903:903) (903:903:903)) + (PORT datad (956:956:956) (947:947:947)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (903:903:903)) + (PORT datab (1046:1046:1046) (1032:1032:1032)) + (PORT datac (858:858:858) (814:814:814)) + (PORT datad (895:895:895) (852:852:852)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datab (638:638:638) (651:651:651)) + (PORT datad (479:479:479) (462:462:462)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_CL) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1296:1296:1296) (1179:1179:1179)) + (PORT datab (370:370:370) (453:453:453)) + (PORT datad (478:478:478) (462:462:462)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_DATA) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (PORT datab (340:340:340) (423:423:423)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (301:301:301) (378:378:378)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|tread_end\~3) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (877:877:877)) + (PORT datab (957:957:957) (903:903:903)) + (PORT datac (349:349:349) (449:449:449)) + (PORT datad (870:870:870) (842:842:842)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_PRE) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT datab (519:519:519) (506:506:506)) + (PORT datad (539:539:539) (561:561:561)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_TRP) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|trp_end\~1) + (DELAY + (ABSOLUTE + (PORT datab (556:556:556) (521:521:521)) + (PORT datac (581:581:581) (597:597:597)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_END) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2564:2564:2564) (2442:2442:2442)) + (PORT datab (344:344:344) (427:427:427)) + (PORT datad (546:546:546) (593:593:593)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2563:2563:2563) (2441:2441:2441)) + (PORT datab (345:345:345) (429:429:429)) + (PORT datad (305:305:305) (378:378:378)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_ACTIVE) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT datab (556:556:556) (593:593:593)) + (PORT datad (478:478:478) (462:462:462)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_TRCD) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|trcd_end\~1) + (DELAY + (ABSOLUTE + (PORT datab (628:628:628) (635:635:635)) + (PORT datad (494:494:494) (470:470:470)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_READ) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (643:643:643)) + (PORT datab (360:360:360) (436:436:436)) + (PORT datad (302:302:302) (375:375:375)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|tread_end\~2) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (462:462:462)) + (PORT datab (374:374:374) (463:463:463)) + (PORT datac (315:315:315) (408:408:408)) + (PORT datad (317:317:317) (400:400:400)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|tread_end\~4) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (497:497:497)) + (PORT datab (307:307:307) (332:332:332)) + (PORT datac (327:327:327) (412:412:412)) + (PORT datad (328:328:328) (405:405:405)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (PORT datab (362:362:362) (439:439:439)) + (PORT datac (531:531:531) (553:553:553)) + (PORT datad (988:988:988) (986:986:986)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (899:899:899)) + (PORT datab (908:908:908) (851:851:851)) + (PORT datac (450:450:450) (427:427:427)) + (PORT datad (897:897:897) (854:854:854)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~3) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (943:943:943)) + (PORT datab (1220:1220:1220) (1113:1113:1113)) + (PORT datac (266:266:266) (293:293:293)) + (PORT datad (816:816:816) (753:753:753)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (464:464:464)) + (PORT datab (376:376:376) (466:466:466)) + (PORT datac (320:320:320) (414:414:414)) + (PORT datad (322:322:322) (405:405:405)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|valid_wrreq\~1) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (862:862:862) (806:806:806)) + (PORT datac (483:483:483) (460:460:460)) + (PORT datad (858:858:858) (814:814:814)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (383:383:383)) + (PORT datab (396:396:396) (494:494:494)) + (PORT datad (951:951:951) (932:932:932)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (330:330:330)) + (PORT datab (398:398:398) (497:497:497)) + (PORT datad (364:364:364) (449:449:449)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (405:405:405) (492:492:492)) + (PORT datad (256:256:256) (285:285:285)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (645:645:645)) + (PORT datab (370:370:370) (454:454:454)) + (PORT datac (346:346:346) (444:444:444)) + (PORT datad (251:251:251) (279:279:279)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (629:629:629)) + (PORT datab (970:970:970) (978:978:978)) + (PORT datac (813:813:813) (750:750:750)) + (PORT datad (854:854:854) (826:826:826)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (678:678:678)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (677:677:677)) + (PORT datad (248:248:248) (270:270:270)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (680:680:680)) + (PORT datac (331:331:331) (414:414:414)) + (PORT datad (537:537:537) (564:564:564)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (493:493:493)) + (PORT datab (405:405:405) (492:492:492)) + (PORT datac (363:363:363) (453:453:453)) + (PORT datad (356:356:356) (451:451:451)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1135:1135:1135) (1146:1146:1146)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (413:413:413)) + (PORT datac (296:296:296) (374:374:374)) + (PORT datad (844:844:844) (839:839:839)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|parity9) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT datad (951:951:951) (932:932:932)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a0) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1135:1135:1135) (1146:1146:1146)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (379:379:379)) + (PORT datab (396:396:396) (494:494:494)) + (PORT datac (562:562:562) (591:591:591)) + (PORT datad (949:949:949) (929:929:929)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (490:490:490)) + (PORT datab (297:297:297) (329:329:329)) + (PORT datad (571:571:571) (598:598:598)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (292:292:292) (332:332:332)) + (PORT datab (405:405:405) (493:493:493)) + (PORT datac (360:360:360) (451:451:451)) + (PORT datad (358:358:358) (453:453:453)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (491:491:491)) + (PORT datab (369:369:369) (452:452:452)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (861:861:861)) + (PORT datad (883:883:883) (890:890:890)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT asdata (1021:1021:1021) (1040:1040:1040)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (1352:1352:1352) (1327:1327:1327)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (2086:2086:2086) (1993:1993:1993)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT ena (1720:1720:1720) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1562:1562:1562) (1479:1479:1479)) + (PORT datab (368:368:368) (452:452:452)) + (PORT datad (319:319:319) (389:389:389)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT asdata (794:794:794) (869:869:869)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (1369:1369:1369) (1347:1347:1347)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8\~0) + (DELAY + (ABSOLUTE + (PORT datab (380:380:380) (463:463:463)) + (PORT datac (882:882:882) (879:879:879)) + (PORT datad (355:355:355) (429:429:429)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8\~1) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (863:863:863)) + (PORT datad (240:240:240) (258:258:258)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT asdata (1062:1062:1062) (1085:1085:1085)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (1336:1336:1336) (1314:1314:1314)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1412:1412:1412) (1348:1348:1348)) + (PORT datab (1382:1382:1382) (1317:1317:1317)) + (PORT datad (812:812:812) (777:777:777)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (311:311:311)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (930:930:930) (878:878:878)) + (PORT datad (237:237:237) (256:256:256)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1213:1213:1213) (1102:1102:1102)) + (PORT datab (341:341:341) (388:388:388)) + (PORT datac (338:338:338) (426:426:426)) + (PORT datad (805:805:805) (745:745:745)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (1441:1441:1441) (1405:1405:1405)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1293:1293:1293) (1224:1224:1224)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT asdata (2168:2168:2168) (2075:2075:2075)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (534:534:534) (557:557:557)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1293:1293:1293) (1224:1224:1224)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT asdata (1769:1769:1769) (1738:1738:1738)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1679:1679:1679) (1618:1618:1618)) + (PORT datab (854:854:854) (816:816:816)) + (PORT datad (1321:1321:1321) (1278:1278:1278)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (932:932:932) (937:937:937)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT asdata (1726:1726:1726) (1674:1674:1674)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT asdata (2464:2464:2464) (2342:2342:2342)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT asdata (1438:1438:1438) (1429:1429:1429)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1642:1642:1642) (1599:1599:1599)) + (PORT datab (1950:1950:1950) (1833:1833:1833)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (1713:1713:1713) (1587:1587:1587)) + (PORT datac (456:456:456) (430:430:430)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (2093:2093:2093) (1986:1986:1986)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1708:1708:1708) (1615:1615:1615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (567:567:567) (584:584:584)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1293:1293:1293) (1224:1224:1224)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT asdata (1746:1746:1746) (1717:1717:1717)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdempty_eq_comp_lsb\|data_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1342:1342:1342) (1286:1286:1286)) + (PORT datad (837:837:837) (827:827:827)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (1401:1401:1401) (1374:1374:1374)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1293:1293:1293) (1224:1224:1224)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT asdata (2161:2161:2161) (2076:2076:2076)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1352:1352:1352) (1302:1302:1302)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datad (1653:1653:1653) (1538:1538:1538)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (2154:2154:2154) (2068:2068:2068)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1708:1708:1708) (1615:1615:1615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1322:1322:1322) (1305:1305:1305)) + (PORT datab (1713:1713:1713) (1656:1656:1656)) + (PORT datad (297:297:297) (367:367:367)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (770:770:770)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (239:239:239) (265:265:265)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_en_dly) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1868:1868:1868)) + (PORT asdata (788:788:788) (858:858:858)) + (PORT clrn (5995:5995:5995) (5789:5789:5789)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|valid_wreq) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (444:444:444)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (PORT datab (956:956:956) (934:934:934)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Add2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (433:433:433)) + (PORT datab (359:359:359) (450:450:450)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5949:5949:5949) (5747:5747:5747)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Add2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (430:430:430)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Add2\~6) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (426:426:426)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT datab (362:362:362) (454:454:454)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (258:258:258) (288:288:288)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5949:5949:5949) (5747:5747:5747)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (855:855:855)) + (PORT datab (341:341:341) (422:422:422)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (352:352:352) (434:434:434)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (424:424:424)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (PORT datab (344:344:344) (426:426:426)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (903:903:903)) + (PORT datab (638:638:638) (646:646:646)) + (PORT datac (545:545:545) (577:577:577)) + (PORT datad (894:894:894) (882:882:882)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (350:350:350) (438:438:438)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (509:509:509) (540:540:540)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~3) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (515:515:515)) + (PORT datab (556:556:556) (523:523:523)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (527:527:527) (559:559:559)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (903:903:903)) + (PORT datab (638:638:638) (647:647:647)) + (PORT datac (546:546:546) (578:578:578)) + (PORT datad (895:895:895) (883:883:883)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (490:490:490)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (507:507:507) (488:488:488)) + (PORT datad (526:526:526) (559:559:559)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5949:5949:5949) (5747:5747:5747)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT datab (299:299:299) (331:331:331)) + (PORT datac (320:320:320) (416:416:416)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5949:5949:5949) (5747:5747:5747)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (345:345:345) (428:428:428)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|always5\~1) + (DELAY + (ABSOLUTE + (PORT datac (320:320:320) (416:416:416)) + (PORT datad (259:259:259) (289:289:289)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|rd_en) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5949:5949:5949) (5747:5747:5747)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty\~1) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (924:924:924)) + (PORT datab (982:982:982) (965:965:965)) + (PORT datac (948:948:948) (946:946:946)) + (PORT datad (918:918:918) (930:930:930)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty\~0) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (450:450:450)) + (PORT datac (526:526:526) (561:561:561)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty\~2) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (837:837:837)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~4) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (738:738:738)) + (PORT datad (919:919:919) (929:929:929)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (604:604:604)) + (PORT datab (577:577:577) (611:611:611)) + (PORT datac (309:309:309) (399:399:399)) + (PORT datad (919:919:919) (929:929:929)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT asdata (790:790:790) (861:861:861)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT asdata (1021:1021:1021) (1029:1029:1029)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (628:628:628)) + (PORT datab (379:379:379) (462:462:462)) + (PORT datac (321:321:321) (399:399:399)) + (PORT datad (563:563:563) (582:582:582)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (966:966:966)) + (PORT datab (1028:1028:1028) (1018:1018:1018)) + (PORT datac (967:967:967) (967:967:967)) + (PORT datad (909:909:909) (860:860:860)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (1300:1300:1300) (1278:1278:1278)) + (PORT datad (255:255:255) (281:281:281)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (1329:1329:1329) (1294:1294:1294)) + (PORT datac (1301:1301:1301) (1278:1278:1278)) + (PORT datad (255:255:255) (281:281:281)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (1414:1414:1414) (1385:1385:1385)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1708:1708:1708) (1615:1615:1615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1285:1285:1285) (1241:1241:1241)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1270:1270:1270) (1242:1242:1242)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1618:1618:1618) (1524:1524:1524)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (PORT ena (2086:2086:2086) (1974:1974:1974)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT asdata (795:795:795) (871:871:871)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (1818:1818:1818) (1758:1758:1758)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT ena (1720:1720:1720) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT asdata (1403:1403:1403) (1389:1389:1389)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (2057:2057:2057) (1942:1942:1942)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT ena (1720:1720:1720) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (899:899:899) (900:900:900)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (909:909:909) (896:896:896)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (580:580:580)) + (PORT datab (340:340:340) (422:422:422)) + (PORT datac (309:309:309) (399:399:399)) + (PORT datad (535:535:535) (558:558:558)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (421:421:421)) + (PORT datab (343:343:343) (425:425:425)) + (PORT datac (308:308:308) (395:395:395)) + (PORT datad (256:256:256) (281:281:281)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (437:437:437)) + (PORT datab (336:336:336) (412:412:412)) + (PORT datac (310:310:310) (398:398:398)) + (PORT datad (855:855:855) (809:809:809)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT asdata (1805:1805:1805) (1740:1740:1740)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datac (297:297:297) (375:375:375)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (882:882:882)) + (PORT datab (850:850:850) (822:822:822)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (605:605:605)) + (PORT datab (901:901:901) (887:887:887)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (572:572:572)) + (PORT datab (937:937:937) (917:917:917)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (286:286:286) (314:314:314)) + (PORT datac (245:245:245) (276:276:276)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (428:428:428)) + (PORT datac (312:312:312) (402:402:402)) + (PORT datad (539:539:539) (562:562:562)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (428:428:428)) + (PORT datac (309:309:309) (397:397:397)) + (PORT datad (258:258:258) (283:283:283)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1217:1217:1217)) + (PORT datab (922:922:922) (918:918:918)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (903:903:903)) + (PORT datab (984:984:984) (957:957:957)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1143:1143:1143)) + (PORT datab (929:929:929) (925:925:925)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (949:949:949)) + (PORT datab (965:965:965) (942:942:942)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (858:858:858)) + (PORT datab (855:855:855) (804:804:804)) + (PORT datac (932:932:932) (877:877:877)) + (PORT datad (861:861:861) (804:804:804)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (324:324:324)) + (PORT datab (1000:1000:1000) (985:985:985)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_en) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5995:5995:5995) (5789:5789:5789)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT datab (334:334:334) (410:410:410)) + (PORT datac (1312:1312:1312) (1277:1277:1277)) + (PORT datad (1296:1296:1296) (1256:1256:1256)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (465:465:465)) + (PORT datab (341:341:341) (389:389:389)) + (PORT datac (803:803:803) (794:794:794)) + (PORT datad (548:548:548) (575:575:575)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (240:240:240) (258:258:258)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (356:356:356)) + (PORT datad (347:347:347) (430:430:430)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (609:609:609)) + (PORT datab (593:593:593) (620:620:620)) + (PORT datac (260:260:260) (304:304:304)) + (PORT datad (347:347:347) (430:430:430)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6\~0) + (DELAY + (ABSOLUTE + (PORT datab (320:320:320) (357:357:357)) + (PORT datad (545:545:545) (574:574:574)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (984:984:984) (964:964:964)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT ena (1720:1720:1720) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT asdata (1406:1406:1406) (1385:1385:1385)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datac (314:314:314) (403:403:403)) + (PORT datad (254:254:254) (278:278:278)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (278:278:278) (304:304:304)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (631:631:631)) + (PORT datad (335:335:335) (416:416:416)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (933:933:933)) + (PORT datad (889:889:889) (886:886:886)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (310:310:310)) + (PORT datab (1958:1958:1958) (1762:1762:1762)) + (PORT datac (1882:1882:1882) (1695:1695:1695)) + (PORT datad (267:267:267) (285:285:285)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1884:1884:1884) (1709:1709:1709)) + (PORT datab (303:303:303) (327:327:327)) + (PORT datac (265:265:265) (291:291:291)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1855:1855:1855)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1643:1643:1643) (1583:1583:1583)) + (PORT datab (921:921:921) (928:928:928)) + (PORT datac (1168:1168:1168) (1141:1141:1141)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (640:640:640)) + (PORT datad (331:331:331) (408:408:408)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (308:308:308) (349:349:349)) + (PORT datab (1213:1213:1213) (1184:1184:1184)) + (PORT datac (1552:1552:1552) (1461:1461:1461)) + (PORT datad (241:241:241) (260:260:260)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.READ) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~7) + (DELAY + (ABSOLUTE + (PORT datab (643:643:643) (658:658:658)) + (PORT datac (503:503:503) (515:515:515)) + (PORT datad (550:550:550) (579:579:579)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (557:557:557)) + (PORT datab (383:383:383) (471:471:471)) + (PORT datad (265:265:265) (282:282:282)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_DATA) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|twrite_end\~0) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (468:468:468)) + (PORT datab (363:363:363) (459:459:459)) + (PORT datac (321:321:321) (416:416:416)) + (PORT datad (324:324:324) (407:407:407)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|twrite_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (562:562:562)) + (PORT datab (330:330:330) (372:372:372)) + (PORT datac (369:369:369) (483:483:483)) + (PORT datad (806:806:806) (727:727:727)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_PRE) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (313:313:313) (350:350:350)) + (PORT datad (553:553:553) (578:578:578)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_TRP) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|trp_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (563:563:563)) + (PORT datab (351:351:351) (440:440:440)) + (PORT datac (289:289:289) (335:335:335)) + (PORT datad (500:500:500) (474:474:474)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_END) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1273:1273:1273)) + (PORT datab (1603:1603:1603) (1500:1500:1500)) + (PORT datad (264:264:264) (295:295:295)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.WRITE) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (645:645:645)) + (PORT datab (368:368:368) (447:447:447)) + (PORT datac (1253:1253:1253) (1222:1222:1222)) + (PORT datad (324:324:324) (395:395:395)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (793:793:793)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (237:237:237) (263:263:263)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.ARBIT) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT datab (1162:1162:1162) (1191:1191:1191)) + (PORT datac (331:331:331) (415:415:415)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1265:1265:1265) (1242:1242:1242)) + (PORT datab (378:378:378) (485:485:485)) + (PORT datad (585:585:585) (612:612:612)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\~4) + (DELAY + (ABSOLUTE + (PORT datad (580:580:580) (615:615:615)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\~2) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (674:674:674)) + (PORT datad (312:312:312) (393:393:393)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (PORT ena (1083:1083:1083) (1077:1077:1077)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\~15) + (DELAY + (ABSOLUTE + (PORT datac (302:302:302) (384:384:384)) + (PORT datad (309:309:309) (388:388:388)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (342:342:342)) + (PORT datad (569:569:569) (588:588:588)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_TRP) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\~1) + (DELAY + (ABSOLUTE + (PORT datab (287:287:287) (318:318:318)) + (PORT datad (330:330:330) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (463:463:463)) + (PORT datac (308:308:308) (395:395:395)) + (PORT datad (531:531:531) (572:572:572)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (671:671:671)) + (PORT datab (341:341:341) (422:422:422)) + (PORT datac (254:254:254) (293:293:293)) + (PORT datad (321:321:321) (392:392:392)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (308:308:308) (357:357:357)) + (PORT datab (359:359:359) (448:448:448)) + (PORT datad (248:248:248) (270:270:270)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\~0) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (628:628:628)) + (PORT datab (283:283:283) (314:314:314)) + (PORT datad (329:329:329) (422:422:422)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (623:623:623)) + (PORT datab (369:369:369) (464:464:464)) + (PORT datac (310:310:310) (398:398:398)) + (PORT datad (320:320:320) (407:407:407)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT datab (279:279:279) (304:304:304)) + (PORT datac (329:329:329) (412:412:412)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_TRF) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\~2) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (356:356:356)) + (PORT datab (362:362:362) (451:451:451)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|trc_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (621:621:621)) + (PORT datab (368:368:368) (464:464:464)) + (PORT datac (310:310:310) (398:398:398)) + (PORT datad (320:320:320) (407:407:407)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (339:339:339)) + (PORT datab (281:281:281) (307:307:307)) + (PORT datac (305:305:305) (389:389:389)) + (PORT datad (266:266:266) (306:306:306)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AUTO_REF) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (672:672:672)) + (PORT datac (331:331:331) (414:414:414)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (PORT ena (1083:1083:1083) (1077:1077:1077)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\~17) + (DELAY + (ABSOLUTE + (PORT dataa (308:308:308) (357:357:357)) + (PORT datab (356:356:356) (439:439:439)) + (PORT datac (304:304:304) (387:387:387)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_END) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|aref_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (1162:1162:1162) (1191:1191:1191)) + (PORT datac (330:330:330) (414:414:414)) + (PORT datad (582:582:582) (608:608:608)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.AREF) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\~3) + (DELAY + (ABSOLUTE + (PORT datad (254:254:254) (282:282:282)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\~2) + (DELAY + (ABSOLUTE + (PORT datab (406:406:406) (518:518:518)) + (PORT datad (258:258:258) (288:288:288)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT datab (377:377:377) (459:459:459)) + (PORT datac (360:360:360) (466:466:466)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1242:1242:1242) (1201:1201:1201)) + (PORT datab (403:403:403) (515:515:515)) + (PORT datad (256:256:256) (284:284:284)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_TRP) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (437:437:437)) + (PORT datab (403:403:403) (514:514:514)) + (PORT datac (303:303:303) (386:386:386)) + (PORT datad (254:254:254) (282:282:282)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (886:886:886)) + (PORT datad (329:329:329) (403:403:403)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (905:905:905)) + (PORT datab (923:923:923) (892:892:892)) + (PORT datac (831:831:831) (810:810:810)) + (PORT datad (893:893:893) (884:884:884)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\~0) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (789:789:789)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (245:245:245) (271:271:271)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~20) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~22) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (433:433:433)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~24) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~28) + (DELAY + (ABSOLUTE + (PORT datad (507:507:507) (538:538:538)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (432:432:432)) + (PORT datab (544:544:544) (578:578:578)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (301:301:301) (378:378:378)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (862:862:862)) + (PORT datab (908:908:908) (890:890:890)) + (PORT datac (867:867:867) (838:838:838)) + (PORT datad (894:894:894) (857:857:857)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (853:853:853)) + (PORT datac (764:764:764) (706:706:706)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (903:903:903)) + (PORT datab (920:920:920) (889:889:889)) + (PORT datac (826:826:826) (806:806:806)) + (PORT datad (894:894:894) (885:885:885)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (890:890:890)) + (PORT datab (287:287:287) (316:316:316)) + (PORT datac (486:486:486) (463:463:463)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_IDLE\~0) + (DELAY + (ABSOLUTE + (PORT datad (246:246:246) (271:271:271)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (311:311:311)) + (PORT datab (386:386:386) (464:464:464)) + (PORT datac (239:239:239) (266:266:266)) + (PORT datad (1280:1280:1280) (1223:1223:1223)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\~4) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (612:612:612)) + (PORT datab (295:295:295) (327:327:327)) + (PORT datad (339:339:339) (419:419:419)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT datab (403:403:403) (515:515:515)) + (PORT datad (335:335:335) (415:415:415)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_END\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (437:437:437)) + (PORT datab (405:405:405) (510:510:510)) + (PORT datad (504:504:504) (485:485:485)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_END) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (451:451:451)) + (PORT datab (378:378:378) (485:485:485)) + (PORT datac (1219:1219:1219) (1192:1192:1192)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_PCHA) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (641:641:641)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (644:644:644)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (599:599:599)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (567:567:567) (587:587:587)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~4) + (DELAY + (ABSOLUTE + (PORT datac (492:492:492) (466:466:466)) + (PORT datad (311:311:311) (357:357:357)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (1574:1574:1574) (1507:1507:1507)) + (PORT datad (318:318:318) (365:365:365)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT ena (1037:1037:1037) (1012:1012:1012)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (369:369:369) (450:450:450)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (562:562:562)) + (PORT datab (1360:1360:1360) (1352:1352:1352)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1861:1861:1861)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (370:370:370) (450:450:450)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[6\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (562:562:562)) + (PORT datab (1360:1360:1360) (1353:1353:1353)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1861:1861:1861)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (459:459:459)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[7\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (567:567:567)) + (PORT datab (1358:1358:1358) (1349:1349:1349)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1861:1861:1861)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~0) + (DELAY + (ABSOLUTE + (PORT datac (494:494:494) (468:468:468)) + (PORT datad (315:315:315) (362:362:362)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT ena (1037:1037:1037) (1012:1012:1012)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~7) + (DELAY + (ABSOLUTE + (PORT datac (495:495:495) (469:469:469)) + (PORT datad (318:318:318) (365:365:365)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT ena (1037:1037:1037) (1012:1012:1012)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~8) + (DELAY + (ABSOLUTE + (PORT datab (356:356:356) (403:403:403)) + (PORT datad (451:451:451) (429:429:429)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT ena (1037:1037:1037) (1012:1012:1012)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (459:459:459)) + (PORT datab (368:368:368) (451:451:451)) + (PORT datac (318:318:318) (396:396:396)) + (PORT datad (321:321:321) (391:391:391)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (460:460:460)) + (PORT datab (628:628:628) (638:638:638)) + (PORT datac (239:239:239) (265:265:265)) + (PORT datad (569:569:569) (582:582:582)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|LessThan0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (611:611:611)) + (PORT datab (367:367:367) (448:448:448)) + (PORT datac (579:579:579) (595:595:595)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (558:558:558) (589:589:589)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[8\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1618:1618:1618) (1555:1555:1555)) + (PORT datab (353:353:353) (400:400:400)) + (PORT datad (483:483:483) (451:451:451)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (332:332:332) (410:410:410)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[9\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (562:562:562)) + (PORT datab (1361:1361:1361) (1353:1353:1353)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1861:1861:1861)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (641:641:641)) + (PORT datab (372:372:372) (453:453:453)) + (PORT datac (326:326:326) (411:411:411)) + (PORT datad (560:560:560) (584:584:584)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (330:330:330) (416:416:416)) + (PORT datad (332:332:332) (410:410:410)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1090:1090:1090)) + (PORT datab (364:364:364) (441:441:441)) + (PORT datad (1115:1115:1115) (1021:1021:1021)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_req) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datac (879:879:879) (890:890:890)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|wr_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1301:1301:1301) (1273:1273:1273)) + (PORT datab (1604:1604:1604) (1500:1500:1500)) + (PORT datad (264:264:264) (296:296:296)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|wr_en) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1269:1269:1269)) + (PORT datab (349:349:349) (433:433:433)) + (PORT datad (2523:2523:2523) (2391:2391:2391)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector4\~1) + (DELAY + (ABSOLUTE + (PORT datab (636:636:636) (650:650:650)) + (PORT datac (907:907:907) (907:907:907)) + (PORT datad (530:530:530) (554:554:554)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (354:354:354)) + (PORT datab (352:352:352) (441:441:441)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (527:527:527) (548:548:548)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (952:952:952)) + (PORT datab (507:507:507) (492:492:492)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (435:435:435) (409:409:409)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (356:356:356) (442:442:442)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (356:356:356) (446:446:446)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[8\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[9\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (363:363:363) (440:440:440)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~5) + (DELAY + (ABSOLUTE + (PORT datab (641:641:641) (656:656:656)) + (PORT datad (548:548:548) (578:578:578)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (883:883:883)) + (PORT datad (831:831:831) (784:784:784)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_TRCD) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|trcd_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (563:563:563)) + (PORT datab (331:331:331) (373:373:373)) + (PORT datac (560:560:560) (591:591:591)) + (PORT datad (500:500:500) (474:474:474)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_WRITE) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_ack\~2) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (465:465:465)) + (PORT datab (359:359:359) (455:455:455)) + (PORT datac (319:319:319) (413:413:413)) + (PORT datad (321:321:321) (404:404:404)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_ack\~3) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (563:563:563)) + (PORT datab (328:328:328) (369:369:369)) + (PORT datac (363:363:363) (475:475:475)) + (PORT datad (483:483:483) (451:451:451)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1356:1356:1356) (1312:1312:1312)) + (PORT datab (360:360:360) (437:437:437)) + (PORT datac (319:319:319) (397:397:397)) + (PORT datad (1274:1274:1274) (1238:1238:1238)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1276:1276:1276) (1244:1244:1244)) + (PORT datab (1567:1567:1567) (1494:1494:1494)) + (PORT datac (1139:1139:1139) (1039:1039:1039)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (506:506:506)) + (PORT datab (290:290:290) (327:327:327)) + (PORT datad (1289:1289:1289) (1252:1252:1252)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1374:1374:1374) (1316:1316:1316)) + (PORT datab (982:982:982) (971:971:971)) + (PORT datac (1232:1232:1232) (1185:1185:1185)) + (PORT datad (921:921:921) (901:901:901)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (PORT ena (1757:1757:1757) (1679:1679:1679)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~11) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (948:948:948)) + (PORT datab (1259:1259:1259) (1212:1212:1212)) + (PORT datac (1271:1271:1271) (1218:1218:1218)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (PORT ena (1106:1106:1106) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~10) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (426:426:426)) + (PORT datac (295:295:295) (373:373:373)) + (PORT datad (903:903:903) (893:893:893)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|parity6) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (PORT ena (1757:1757:1757) (1679:1679:1679)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (901:901:901)) + (PORT datab (402:402:402) (486:486:486)) + (PORT datac (338:338:338) (428:428:428)) + (PORT datad (967:967:967) (924:924:924)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (238:238:238) (257:257:257)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (369:369:369) (449:449:449)) + (PORT datac (1193:1193:1193) (1150:1150:1150)) + (PORT datad (966:966:966) (923:923:923)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1375:1375:1375) (1318:1318:1318)) + (PORT datab (302:302:302) (342:342:342)) + (PORT datad (921:921:921) (901:901:901)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1378:1378:1378) (1322:1322:1322)) + (PORT datab (979:979:979) (967:967:967)) + (PORT datac (261:261:261) (305:305:305)) + (PORT datad (916:916:916) (896:896:896)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8\~0) + (DELAY + (ABSOLUTE + (PORT datad (237:237:237) (255:255:255)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10\~0) + (DELAY + (ABSOLUTE + (PORT datab (372:372:372) (453:453:453)) + (PORT datad (243:243:243) (268:268:268)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (1675:1675:1675) (1632:1632:1632)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (PORT ena (1106:1106:1106) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (991:991:991)) + (PORT datab (913:913:913) (914:914:914)) + (PORT datad (548:548:548) (570:570:570)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1041:1041:1041)) + (PORT datab (337:337:337) (379:379:379)) + (PORT datac (324:324:324) (425:425:425)) + (PORT datad (832:832:832) (775:775:775)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (345:345:345) (389:389:389)) + (PORT datac (454:454:454) (431:431:431)) + (PORT datad (964:964:964) (952:952:952)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (417:417:417)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rx\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (796:796:796) (842:842:842)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg1\~0) + (DELAY + (ABSOLUTE + (PORT datad (4105:4105:4105) (4296:4296:4296)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg3) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (906:906:906) (895:895:895)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (368:368:368) (467:467:467)) + (PORT datad (262:262:262) (297:297:297)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always8\~0) + (DELAY + (ABSOLUTE + (PORT datab (304:304:304) (342:342:342)) + (PORT datac (327:327:327) (428:428:428)) + (PORT datad (321:321:321) (409:409:409)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT asdata (770:770:770) (844:844:844)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (378:378:378)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (306:306:306) (380:380:380)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (376:376:376)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (308:308:308) (382:382:382)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (307:307:307) (381:381:381)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (306:306:306) (380:380:380)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|ram_address_a\[9\]) + (DELAY + (ABSOLUTE + (PORT datad (330:330:330) (404:404:404)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (1285:1285:1285) (1253:1253:1253)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datab (1258:1258:1258) (1210:1210:1210)) + (PORT datac (897:897:897) (898:898:898)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (377:377:377)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (305:305:305) (380:380:380)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (308:308:308) (383:383:383)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (306:306:306) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (378:378:378)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (306:306:306) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT asdata (770:770:770) (844:844:844)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (972:972:972) (971:971:971)) + (PORT d[1] (1038:1038:1038) (1027:1027:1027)) + (PORT d[2] (985:985:985) (968:968:968)) + (PORT d[3] (970:970:970) (964:964:964)) + (PORT d[4] (997:997:997) (990:990:990)) + (PORT d[5] (1000:1000:1000) (994:994:994)) + (PORT d[6] (985:985:985) (968:968:968)) + (PORT d[7] (963:963:963) (964:964:964)) + (PORT d[8] (607:607:607) (590:590:590)) + (PORT clk (2261:2261:2261) (2289:2289:2289)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1350:1350:1350) (1313:1313:1313)) + (PORT d[1] (1573:1573:1573) (1549:1549:1549)) + (PORT d[2] (1399:1399:1399) (1369:1369:1369)) + (PORT d[3] (1767:1767:1767) (1706:1706:1706)) + (PORT d[4] (1342:1342:1342) (1310:1310:1310)) + (PORT d[5] (1406:1406:1406) (1368:1368:1368)) + (PORT d[6] (1726:1726:1726) (1667:1667:1667)) + (PORT d[7] (1330:1330:1330) (1286:1286:1286)) + (PORT d[8] (1374:1374:1374) (1352:1352:1352)) + (PORT d[9] (1214:1214:1214) (1122:1122:1122)) + (PORT clk (2257:2257:2257) (2284:2284:2284)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2463:2463:2463) (2259:2259:2259)) + (PORT clk (2257:2257:2257) (2284:2284:2284)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2261:2261:2261) (2289:2289:2289)) + (PORT d[0] (3170:3170:3170) (2973:2973:2973)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2262:2262:2262) (2290:2290:2290)) + (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2262:2262:2262) (2290:2290:2290)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2262:2262:2262) (2290:2290:2290)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2262:2262:2262) (2290:2290:2290)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1267:1267:1267) (1201:1201:1201)) + (PORT d[1] (1547:1547:1547) (1522:1522:1522)) + (PORT d[2] (1753:1753:1753) (1686:1686:1686)) + (PORT d[3] (1380:1380:1380) (1348:1348:1348)) + (PORT d[4] (1715:1715:1715) (1647:1647:1647)) + (PORT d[5] (1078:1078:1078) (1070:1070:1070)) + (PORT d[6] (1320:1320:1320) (1285:1285:1285)) + (PORT d[7] (1320:1320:1320) (1279:1279:1279)) + (PORT d[8] (1365:1365:1365) (1347:1347:1347)) + (PORT d[9] (1215:1215:1215) (1118:1118:1118)) + (PORT clk (2211:2211:2211) (2198:2198:2198)) + (PORT aclr (2253:2253:2253) (2246:2246:2246)) + (PORT stall (1610:1610:1610) (1736:1736:1736)) + (IOPATH (posedge aclr) q (396:396:396) (396:396:396)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + (HOLD stall (posedge clk) (254:254:254)) + (HOLD aclr (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (2211:2211:2211) (2198:2198:2198)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2212:2212:2212) (2199:2199:2199)) + (IOPATH (posedge clk) pulse (0:0:0) (3182:3182:3182)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2212:2212:2212) (2199:2199:2199)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2212:2212:2212) (2199:2199:2199)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (2203:2203:2203) (2194:2194:2194)) + (PORT ena (2164:2164:2164) (2043:2043:2043)) + (PORT aclr (2204:2204:2204) (2258:2258:2258)) + (IOPATH (posedge clk) q (392:392:392) (392:392:392)) + (IOPATH (posedge aclr) q (440:440:440) (440:440:440)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (64:64:64)) + (SETUP ena (posedge clk) (64:64:64)) + (SETUP aclr (posedge clk) (64:64:64)) + (HOLD d (posedge clk) (211:211:211)) + (HOLD ena (posedge clk) (211:211:211)) + (HOLD aclr (posedge clk) (211:211:211)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_ack) + (DELAY + (ABSOLUTE + (PORT datac (1140:1140:1140) (1040:1040:1040)) + (PORT datad (1527:1527:1527) (1450:1450:1450)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_sdram_en) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1129:1129:1129) (1098:1098:1098)) + (PORT d[1] (1129:1129:1129) (1098:1098:1098)) + (PORT d[2] (1129:1129:1129) (1098:1098:1098)) + (PORT d[3] (1129:1129:1129) (1098:1098:1098)) + (PORT d[4] (1114:1114:1114) (1082:1082:1082)) + (PORT d[5] (1114:1114:1114) (1082:1082:1082)) + (PORT d[6] (1114:1114:1114) (1082:1082:1082)) + (PORT clk (2255:2255:2255) (2284:2284:2284)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1902:1902:1902) (1840:1840:1840)) + (PORT d[1] (1020:1020:1020) (1022:1022:1022)) + (PORT d[2] (2363:2363:2363) (2282:2282:2282)) + (PORT d[3] (1372:1372:1372) (1343:1343:1343)) + (PORT d[4] (1012:1012:1012) (1017:1017:1017)) + (PORT d[5] (1163:1163:1163) (1110:1110:1110)) + (PORT d[6] (1709:1709:1709) (1649:1649:1649)) + (PORT d[7] (2052:2052:2052) (1907:1907:1907)) + (PORT d[8] (1724:1724:1724) (1675:1675:1675)) + (PORT d[9] (857:857:857) (781:781:781)) + (PORT clk (2251:2251:2251) (2279:2279:2279)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2799:2799:2799) (2566:2566:2566)) + (PORT clk (2251:2251:2251) (2279:2279:2279)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2255:2255:2255) (2284:2284:2284)) + (PORT d[0] (3506:3506:3506) (3280:3280:3280)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2256:2256:2256) (2285:2285:2285)) + (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2256:2256:2256) (2285:2285:2285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2256:2256:2256) (2285:2285:2285)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2256:2256:2256) (2285:2285:2285)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (972:972:972) (925:925:925)) + (PORT d[1] (1550:1550:1550) (1515:1515:1515)) + (PORT d[2] (1747:1747:1747) (1679:1679:1679)) + (PORT d[3] (1090:1090:1090) (1090:1090:1090)) + (PORT d[4] (1003:1003:1003) (1011:1011:1011)) + (PORT d[5] (1020:1020:1020) (1014:1014:1014)) + (PORT d[6] (1007:1007:1007) (999:999:999)) + (PORT d[7] (1350:1350:1350) (1322:1322:1322)) + (PORT d[8] (1734:1734:1734) (1675:1675:1675)) + (PORT d[9] (1946:1946:1946) (1784:1784:1784)) + (PORT clk (2205:2205:2205) (2193:2193:2193)) + (PORT aclr (2247:2247:2247) (2241:2241:2241)) + (PORT stall (1917:1917:1917) (2070:2070:2070)) + (IOPATH (posedge aclr) q (396:396:396) (396:396:396)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + (HOLD stall (posedge clk) (254:254:254)) + (HOLD aclr (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (2205:2205:2205) (2193:2193:2193)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2206:2206:2206) (2194:2194:2194)) + (IOPATH (posedge clk) pulse (0:0:0) (3182:3182:3182)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2206:2206:2206) (2194:2194:2194)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2206:2206:2206) (2194:2194:2194)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (2197:2197:2197) (2189:2189:2189)) + (PORT ena (2131:2131:2131) (2004:2004:2004)) + (PORT aclr (2198:2198:2198) (2253:2253:2253)) + (IOPATH (posedge clk) q (392:392:392) (392:392:392)) + (IOPATH (posedge aclr) q (440:440:440) (440:440:440)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (64:64:64)) + (SETUP ena (posedge clk) (64:64:64)) + (SETUP aclr (posedge clk) (64:64:64)) + (HOLD d (posedge clk) (211:211:211)) + (HOLD ena (posedge clk) (211:211:211)) + (HOLD aclr (posedge clk) (211:211:211)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sys_clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (200:200:200) (189:189:189)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (894:894:894)) + (PORT datab (341:341:341) (422:422:422)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (300:300:300) (383:383:383)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (947:947:947)) + (PORT datab (960:960:960) (941:941:941)) + (PORT datac (826:826:826) (767:767:767)) + (PORT datad (953:953:953) (936:936:936)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (441:441:441)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (450:450:450)) + (PORT datab (350:350:350) (439:439:439)) + (PORT datac (311:311:311) (400:400:400)) + (PORT datad (313:313:313) (393:393:393)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|tx_flag) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT asdata (1030:1030:1030) (1048:1048:1048)) + (PORT clrn (5949:5949:5949) (5747:5747:5747)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (942:942:942)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (527:527:527)) + (PORT datab (293:293:293) (331:331:331)) + (PORT datad (292:292:292) (322:322:322)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5192:5192:5192) (4949:4949:4949)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (707:707:707)) + (PORT datab (295:295:295) (333:333:333)) + (PORT datad (288:288:288) (318:318:318)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5192:5192:5192) (4949:4949:4949)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (520:520:520)) + (PORT datab (412:412:412) (513:513:513)) + (PORT datac (321:321:321) (422:422:422)) + (PORT datad (248:248:248) (275:275:275)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (1371:1371:1371) (1321:1321:1321)) + (PORT datad (1269:1269:1269) (1180:1180:1180)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1881:1881:1881)) + (PORT asdata (5350:5350:5350) (4891:4891:4891)) + (PORT clrn (5192:5192:5192) (4949:4949:4949)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (303:303:303) (327:327:327)) + (PORT datac (1403:1403:1403) (1288:1288:1288)) + (PORT datad (1160:1160:1160) (1121:1121:1121)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (350:350:350) (435:435:435)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (350:350:350) (440:440:440)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (321:321:321) (391:391:391)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (448:448:448)) + (PORT datab (351:351:351) (440:440:440)) + (PORT datac (308:308:308) (397:397:397)) + (PORT datad (310:310:310) (389:389:389)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (540:540:540)) + (PORT datab (936:936:936) (944:944:944)) + (PORT datac (794:794:794) (741:741:741)) + (PORT datad (962:962:962) (949:949:949)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1885:1885:1885)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5141:5141:5141) (4901:4901:4901)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (430:430:430)) + (PORT datac (886:886:886) (891:891:891)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|valid_rreq) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (449:449:449)) + (PORT datad (915:915:915) (927:927:927)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (774:774:774) (821:821:821)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4629:4629:4629) (4901:4901:4901)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_ack\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (997:997:997)) + (PORT datab (897:897:897) (855:855:855)) + (PORT datac (824:824:824) (772:772:772)) + (PORT datad (265:265:265) (282:282:282)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT datad (882:882:882) (824:824:824)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (2096:2096:2096) (1989:1989:1989)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (447:447:447)) + (PORT datac (326:326:326) (409:409:409)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (774:774:774) (821:821:821)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4552:4552:4552) (4818:4818:4818)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT datad (878:878:878) (820:820:820)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4558:4558:4558) (4795:4795:4795)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datad (877:877:877) (819:819:819)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (764:764:764) (811:811:811)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4349:4349:4349) (4485:4485:4485)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT datad (883:883:883) (826:826:826)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (774:774:774) (821:821:821)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4391:4391:4391) (4517:4517:4517)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[4\]\~1) + (DELAY + (ABSOLUTE + (PORT datad (876:876:876) (818:818:818)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4641:4641:4641) (4868:4868:4868)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (879:879:879) (822:822:822)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (784:784:784) (831:831:831)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4805:4805:4805) (4978:4978:4978)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[6\]\~3) + (DELAY + (ABSOLUTE + (PORT datad (883:883:883) (826:826:826)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (774:774:774) (821:821:821)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4521:4521:4521) (4777:4777:4777)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT datad (877:877:877) (820:820:820)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (956:956:956) (879:879:879)) + (PORT d[1] (882:882:882) (817:817:817)) + (PORT d[2] (880:880:880) (816:816:816)) + (PORT d[3] (953:953:953) (875:875:875)) + (PORT d[4] (888:888:888) (833:833:833)) + (PORT d[5] (881:881:881) (816:816:816)) + (PORT d[6] (901:901:901) (830:830:830)) + (PORT d[7] (919:919:919) (853:853:853)) + (PORT clk (2277:2277:2277) (2305:2305:2305)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1036:1036:1036) (999:999:999)) + (PORT d[1] (984:984:984) (978:978:978)) + (PORT d[2] (955:955:955) (950:950:950)) + (PORT d[3] (1769:1769:1769) (1707:1707:1707)) + (PORT d[4] (944:944:944) (948:948:948)) + (PORT d[5] (1792:1792:1792) (1709:1709:1709)) + (PORT d[6] (1702:1702:1702) (1604:1604:1604)) + (PORT d[7] (999:999:999) (996:996:996)) + (PORT d[8] (1048:1048:1048) (1035:1035:1035)) + (PORT d[9] (921:921:921) (865:865:865)) + (PORT clk (2273:2273:2273) (2300:2300:2300)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1312:1312:1312) (1167:1167:1167)) + (PORT clk (2273:2273:2273) (2300:2300:2300)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2277:2277:2277) (2305:2305:2305)) + (PORT d[0] (2019:2019:2019) (1881:1881:1881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2306:2306:2306)) + (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2306:2306:2306)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2306:2306:2306)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2306:2306:2306)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (530:530:530) (500:500:500)) + (PORT d[1] (973:973:973) (958:958:958)) + (PORT d[2] (1808:1808:1808) (1728:1728:1728)) + (PORT d[3] (2013:2013:2013) (1906:1906:1906)) + (PORT d[4] (1980:1980:1980) (1869:1869:1869)) + (PORT d[5] (2026:2026:2026) (1902:1902:1902)) + (PORT d[6] (1028:1028:1028) (1005:1005:1005)) + (PORT d[7] (1068:1068:1068) (1048:1048:1048)) + (PORT d[8] (1714:1714:1714) (1625:1625:1625)) + (PORT d[9] (922:922:922) (860:860:860)) + (PORT clk (2227:2227:2227) (2214:2214:2214)) + (PORT aclr (2269:2269:2269) (2262:2262:2262)) + (PORT stall (1288:1288:1288) (1407:1407:1407)) + (IOPATH (posedge aclr) q (396:396:396) (396:396:396)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + (HOLD stall (posedge clk) (254:254:254)) + (HOLD aclr (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (2227:2227:2227) (2214:2214:2214)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2228:2228:2228) (2215:2215:2215)) + (IOPATH (posedge clk) pulse (0:0:0) (3182:3182:3182)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2228:2228:2228) (2215:2215:2215)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2228:2228:2228) (2215:2215:2215)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (2219:2219:2219) (2210:2210:2210)) + (PORT ena (1830:1830:1830) (1713:1713:1713)) + (PORT aclr (2220:2220:2220) (2274:2274:2274)) + (IOPATH (posedge clk) q (392:392:392) (392:392:392)) + (IOPATH (posedge aclr) q (440:440:440) (440:440:440)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (64:64:64)) + (SETUP ena (posedge clk) (64:64:64)) + (SETUP aclr (posedge clk) (64:64:64)) + (HOLD d (posedge clk) (211:211:211)) + (HOLD ena (posedge clk) (211:211:211)) + (HOLD aclr (posedge clk) (211:211:211)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita1) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita2) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita3) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita4) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita5) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita6) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita7) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita8) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita9) + (DELAY + (ABSOLUTE + (PORT datab (362:362:362) (439:439:439)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita1) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita2) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita3) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita4) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita5) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita6) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita7) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita8) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita9) + (DELAY + (ABSOLUTE + (PORT datad (507:507:507) (538:538:538)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~4) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (523:523:523)) + (PORT datab (367:367:367) (467:467:467)) + (PORT datac (740:740:740) (662:662:662)) + (PORT datad (370:370:370) (470:470:470)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~3) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (943:943:943)) + (PORT datad (321:321:321) (391:391:391)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~5) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (734:734:734)) + (PORT datab (291:291:291) (320:320:320)) + (PORT datac (1119:1119:1119) (1006:1006:1006)) + (PORT datad (441:441:441) (420:420:420)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|tx) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5192:5192:5192) (4949:4949:4949)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[2\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT asdata (1416:1416:1416) (1405:1405:1405)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT asdata (1329:1329:1329) (1301:1301:1301)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT datab (373:373:373) (479:479:479)) + (PORT datac (1230:1230:1230) (1271:1271:1271)) + (PORT datad (1186:1186:1186) (1214:1214:1214)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT asdata (2130:2130:2130) (2054:2054:2054)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (476:476:476)) + (PORT datab (406:406:406) (510:510:510)) + (PORT datad (506:506:506) (487:487:487)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_TRF) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1236:1236:1236) (1124:1124:1124)) + (PORT datab (304:304:304) (328:328:328)) + (PORT datac (361:361:361) (467:467:467)) + (PORT datad (314:314:314) (394:394:394)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (336:336:336)) + (PORT datab (405:405:405) (516:516:516)) + (PORT datac (304:304:304) (388:388:388)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_AR) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1735:1735:1735) (1631:1631:1631)) + (PORT datad (1315:1315:1315) (1286:1286:1286)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1088:1088:1088)) + (PORT datab (1181:1181:1181) (1095:1095:1095)) + (PORT datad (294:294:294) (363:363:363)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1090:1090:1090)) + (PORT datab (331:331:331) (406:406:406)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~4) + (DELAY + (ABSOLUTE + (PORT datac (941:941:941) (948:948:948)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1706:1706:1706) (1642:1642:1642)) + (PORT datac (1220:1220:1220) (1172:1172:1172)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\~17) + (DELAY + (ABSOLUTE + (PORT datab (286:286:286) (314:314:314)) + (PORT datad (592:592:592) (621:621:621)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_PRE) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|WideOr5) + (DELAY + (ABSOLUTE + (PORT dataa (1731:1731:1731) (1627:1627:1627)) + (PORT datab (1355:1355:1355) (1330:1330:1330)) + (PORT datad (1628:1628:1628) (1549:1549:1549)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\~0) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (882:882:882)) + (PORT datad (1254:1254:1254) (1195:1195:1195)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1085:1085:1085)) + (PORT datab (332:332:332) (408:408:408)) + (PORT datac (1140:1140:1140) (1060:1060:1060)) + (PORT datad (293:293:293) (363:363:363)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (573:573:573)) + (PORT datab (333:333:333) (409:409:409)) + (PORT datac (1138:1138:1138) (1057:1057:1057)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector5\~2) + (DELAY + (ABSOLUTE + (PORT datac (941:941:941) (948:948:948)) + (PORT datad (236:236:236) (253:253:253)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (520:520:520) (497:497:497)) + (PORT datab (383:383:383) (472:472:472)) + (PORT datac (366:366:366) (479:479:479)) + (PORT datad (559:559:559) (584:584:584)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT datac (1223:1223:1223) (1263:1263:1263)) + (PORT datad (1193:1193:1193) (1222:1222:1222)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (328:328:328)) + (PORT datac (330:330:330) (414:414:414)) + (PORT datad (563:563:563) (588:588:588)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (537:537:537) (566:566:566)) + (PORT datac (1112:1112:1112) (1034:1034:1034)) + (PORT datad (493:493:493) (514:514:514)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (309:309:309)) + (PORT datac (941:941:941) (948:948:948)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (900:900:900)) + (PORT datab (908:908:908) (851:851:851)) + (PORT datac (969:969:969) (962:962:962)) + (PORT datad (936:936:936) (935:935:935)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (314:314:314)) + (PORT datab (1047:1047:1047) (1032:1032:1032)) + (PORT datac (245:245:245) (276:276:276)) + (PORT datad (561:561:561) (587:587:587)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_addr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~6) + (DELAY + (ABSOLUTE + (PORT datad (597:597:597) (626:626:626)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT datac (1238:1238:1238) (1166:1166:1166)) + (PORT datad (593:593:593) (622:622:622)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1859:1859:1859)) + (PORT ena (1080:1080:1080) (1064:1064:1064)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~5) + (DELAY + (ABSOLUTE + (PORT datab (379:379:379) (469:469:469)) + (PORT datad (596:596:596) (624:624:624)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1859:1859:1859)) + (PORT ena (1080:1080:1080) (1064:1064:1064)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~4) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (610:610:610)) + (PORT datab (355:355:355) (442:442:442)) + (PORT datad (591:591:591) (619:619:619)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1859:1859:1859)) + (PORT ena (1080:1080:1080) (1064:1064:1064)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\~15) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (378:378:378) (468:468:468)) + (PORT datac (310:310:310) (400:400:400)) + (PORT datad (301:301:301) (374:374:374)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (538:538:538)) + (PORT datab (353:353:353) (436:436:436)) + (PORT datac (363:363:363) (470:470:470)) + (PORT datad (1169:1169:1169) (1069:1069:1069)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_MRS) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_ba\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT asdata (1691:1691:1691) (1629:1629:1629)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1226:1226:1226) (1171:1171:1171)) + (PORT datab (373:373:373) (479:479:479)) + (PORT datad (1186:1186:1186) (1214:1214:1214)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1291:1291:1291) (1315:1315:1315)) + (PORT datab (1336:1336:1336) (1298:1298:1298)) + (PORT datac (1117:1117:1117) (1149:1149:1149)) + (PORT datad (481:481:481) (471:471:471)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (552:552:552)) + (PORT datab (412:412:412) (520:520:520)) + (PORT datac (503:503:503) (514:514:514)) + (PORT datad (478:478:478) (443:443:443)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (351:351:351) (441:441:441)) + (PORT datac (559:559:559) (589:589:589)) + (PORT datad (265:265:265) (282:282:282)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_ba\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1287:1287:1287) (1310:1310:1310)) + (PORT datab (1337:1337:1337) (1299:1299:1299)) + (PORT datac (1130:1130:1130) (1085:1085:1085)) + (PORT datad (1193:1193:1193) (1221:1221:1221)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|WideOr7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (495:495:495)) + (PORT datab (638:638:638) (652:652:652)) + (PORT datac (508:508:508) (548:548:548)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (330:330:330)) + (PORT datab (290:290:290) (322:322:322)) + (PORT datad (561:561:561) (586:586:586)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_addr\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (452:452:452)) + (PORT datab (344:344:344) (427:427:427)) + (PORT datad (2522:2522:2522) (2390:2390:2390)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_ACTIVE) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (856:856:856)) + (PORT datab (1264:1264:1264) (1204:1204:1204)) + (PORT datac (366:366:366) (479:479:479)) + (PORT datad (340:340:340) (426:426:426)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (552:552:552)) + (PORT datab (511:511:511) (489:489:489)) + (PORT datac (370:370:370) (484:484:484)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_addr\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (416:416:416)) + (PORT datab (373:373:373) (480:480:480)) + (PORT datac (830:830:830) (817:817:817)) + (PORT datad (1188:1188:1188) (1216:1216:1216)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1289:1289:1289) (1312:1312:1312)) + (PORT datab (1157:1157:1157) (1184:1184:1184)) + (PORT datac (790:790:790) (769:769:769)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) +) diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_min_1200mv_0c_fast.vo b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_min_1200mv_0c_fast.vo new file mode 100644 index 0000000..303316b --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_min_1200mv_0c_fast.vo @@ -0,0 +1,24917 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:26:31" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module uart_sdram ( + sys_clk, + sys_rst_n, + rx, + tx, + sdram_clk, + sdram_cke, + sdram_cs_n, + sdram_cas_n, + sdram_ras_n, + sdram_we_n, + sdram_ba, + sdram_addr, + sdram_dqm, + sdram_dq); +input sys_clk; +input sys_rst_n; +input rx; +output tx; +output sdram_clk; +output sdram_cke; +output sdram_cs_n; +output sdram_cas_n; +output sdram_ras_n; +output sdram_we_n; +output [1:0] sdram_ba; +output [12:0] sdram_addr; +output [1:0] sdram_dqm; +inout [15:0] sdram_dq; + +// Design Ports Information +// tx => Location: PIN_U1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_clk => Location: PIN_E5, I/O Standard: 2.5 V, Current Strength: Default +// sdram_cke => Location: PIN_M1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_cs_n => Location: PIN_A4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_cas_n => Location: PIN_B5, I/O Standard: 2.5 V, Current Strength: Default +// sdram_ras_n => Location: PIN_D6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_we_n => Location: PIN_A5, I/O Standard: 2.5 V, Current Strength: Default +// sdram_ba[0] => Location: PIN_B4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_ba[1] => Location: PIN_C4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[0] => Location: PIN_B3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[1] => Location: PIN_B1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[2] => Location: PIN_B2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[3] => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[4] => Location: PIN_C2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[5] => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[6] => Location: PIN_F1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[7] => Location: PIN_F2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[8] => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[9] => Location: PIN_N2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[10] => Location: PIN_A3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[11] => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_addr[12] => Location: PIN_M2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dqm[0] => Location: PIN_C6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dqm[1] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[0] => Location: PIN_B7, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[1] => Location: PIN_A7, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[2] => Location: PIN_C8, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[3] => Location: PIN_B8, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[4] => Location: PIN_A8, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[5] => Location: PIN_C7, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[6] => Location: PIN_A6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[7] => Location: PIN_B6, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[8] => Location: PIN_J1, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[9] => Location: PIN_C3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[10] => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[11] => Location: PIN_E3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[12] => Location: PIN_G4, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[13] => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[14] => Location: PIN_J3, I/O Standard: 2.5 V, Current Strength: Default +// sdram_dq[15] => Location: PIN_J4, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// rx => Location: PIN_V1, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("uart_sdram_min_1200mv_0c_v_fast.sdo"); +// synopsys translate_on + +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout ; +wire \uart_tx_inst|baud_cnt[3]~19_combout ; +wire \uart_tx_inst|baud_cnt[4]~21_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout ; +wire \fifo_read_inst|Add2~4_combout ; +wire \Add1~1 ; +wire \Add1~0_combout ; +wire \Add1~3 ; +wire \Add1~2_combout ; +wire \Add1~5 ; +wire \Add1~4_combout ; +wire \Add1~7 ; +wire \Add1~6_combout ; +wire \Add1~9 ; +wire \Add1~8_combout ; +wire \Add1~11 ; +wire \Add1~10_combout ; +wire \Add1~13 ; +wire \Add1~12_combout ; +wire \Add1~15 ; +wire \Add1~14_combout ; +wire \Add1~17 ; +wire \Add1~16_combout ; +wire \Add1~19 ; +wire \Add1~18_combout ; +wire \Add1~21 ; +wire \Add1~20_combout ; +wire \Add1~23 ; +wire \Add1~22_combout ; +wire \Add1~25 ; +wire \Add1~24_combout ; +wire \Add1~27 ; +wire \Add1~26_combout ; +wire \Add1~29 ; +wire \Add1~28_combout ; +wire \Add1~30_combout ; +wire \fifo_read_inst|baud_cnt[1]~15_combout ; +wire \fifo_read_inst|baud_cnt[4]~21_combout ; +wire \fifo_read_inst|baud_cnt[9]~31_combout ; +wire \fifo_read_inst|baud_cnt[11]~35_combout ; +wire \data_num[0]~25 ; +wire \data_num[0]~24_combout ; +wire \data_num[1]~27 ; +wire \data_num[1]~26_combout ; +wire \data_num[2]~29 ; +wire \data_num[2]~28_combout ; +wire \data_num[3]~31 ; +wire \data_num[3]~30_combout ; +wire \data_num[4]~33 ; +wire \data_num[4]~32_combout ; +wire \data_num[5]~35 ; +wire \data_num[5]~34_combout ; +wire \data_num[6]~37 ; +wire \data_num[6]~36_combout ; +wire \data_num[7]~39 ; +wire \data_num[7]~38_combout ; +wire \data_num[8]~41 ; +wire \data_num[8]~40_combout ; +wire \data_num[9]~43 ; +wire \data_num[9]~42_combout ; +wire \data_num[10]~45 ; +wire \data_num[10]~44_combout ; +wire \data_num[11]~47 ; +wire \data_num[11]~46_combout ; +wire \data_num[12]~49 ; +wire \data_num[12]~48_combout ; +wire \data_num[13]~51 ; +wire \data_num[13]~50_combout ; +wire \data_num[14]~53 ; +wire \data_num[14]~52_combout ; +wire \data_num[15]~55 ; +wire \data_num[15]~54_combout ; +wire \data_num[16]~57 ; +wire \data_num[16]~56_combout ; +wire \data_num[17]~59 ; +wire \data_num[17]~58_combout ; +wire \data_num[18]~61 ; +wire \data_num[18]~60_combout ; +wire \data_num[19]~63 ; +wire \data_num[19]~62_combout ; +wire \data_num[20]~65 ; +wire \data_num[20]~64_combout ; +wire \data_num[21]~67 ; +wire \data_num[21]~66_combout ; +wire \data_num[22]~69 ; +wire \data_num[22]~68_combout ; +wire \data_num[23]~70_combout ; +wire \uart_rx_inst|Add1~0_combout ; +wire \uart_rx_inst|Add1~5 ; +wire \uart_rx_inst|Add1~6_combout ; +wire \fifo_read_inst|cnt_read[0]~11 ; +wire \fifo_read_inst|cnt_read[0]~10_combout ; +wire \fifo_read_inst|cnt_read[1]~13 ; +wire \fifo_read_inst|cnt_read[1]~12_combout ; +wire \fifo_read_inst|cnt_read[2]~15 ; +wire \fifo_read_inst|cnt_read[2]~14_combout ; +wire \fifo_read_inst|cnt_read[3]~17 ; +wire \fifo_read_inst|cnt_read[3]~16_combout ; +wire \fifo_read_inst|cnt_read[4]~19 ; +wire \fifo_read_inst|cnt_read[4]~18_combout ; +wire \fifo_read_inst|cnt_read[5]~21 ; +wire \fifo_read_inst|cnt_read[5]~20_combout ; +wire \fifo_read_inst|cnt_read[6]~23 ; +wire \fifo_read_inst|cnt_read[6]~22_combout ; +wire \fifo_read_inst|cnt_read[7]~25 ; +wire \fifo_read_inst|cnt_read[7]~24_combout ; +wire \fifo_read_inst|cnt_read[8]~27 ; +wire \fifo_read_inst|cnt_read[8]~26_combout ; +wire \fifo_read_inst|cnt_read[9]~28_combout ; +wire \uart_rx_inst|baud_cnt[4]~21_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout ; +wire \uart_tx_inst|Mux0~0_combout ; +wire \uart_tx_inst|Mux0~1_combout ; +wire \uart_tx_inst|tx~0_combout ; +wire \uart_tx_inst|tx~1_combout ; +wire \uart_tx_inst|tx~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout ; +wire \uart_tx_inst|Add1~0_combout ; +wire \uart_tx_inst|Add1~1_combout ; +wire \uart_tx_inst|bit_cnt[3]~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout ; +wire \read_valid~q ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout ; +wire \uart_tx_inst|Equal1~3_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ; +wire \fifo_read_inst|Equal1~0_combout ; +wire \fifo_read_inst|Equal1~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout ; +wire \Equal0~0_combout ; +wire \Equal0~1_combout ; +wire \Equal0~2_combout ; +wire \Equal0~3_combout ; +wire \Equal0~4_combout ; +wire \read_valid~0_combout ; +wire \read_valid~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ; +wire \fifo_read_inst|Equal1~2_combout ; +wire \fifo_read_inst|Equal5~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \Equal1~0_combout ; +wire \Equal1~1_combout ; +wire \Equal1~2_combout ; +wire \Equal1~3_combout ; +wire \Equal1~4_combout ; +wire \Equal1~5_combout ; +wire \Equal1~6_combout ; +wire \cnt_wait[8]~0_combout ; +wire \cnt_wait[15]~1_combout ; +wire \cnt_wait[15]~2_combout ; +wire \cnt_wait[14]~3_combout ; +wire \cnt_wait[13]~4_combout ; +wire \cnt_wait[12]~5_combout ; +wire \cnt_wait[9]~6_combout ; +wire \cnt_wait[11]~7_combout ; +wire \cnt_wait[10]~8_combout ; +wire \cnt_wait[8]~9_combout ; +wire \cnt_wait[7]~10_combout ; +wire \cnt_wait[6]~11_combout ; +wire \cnt_wait[5]~12_combout ; +wire \cnt_wait[4]~13_combout ; +wire \cnt_wait[3]~14_combout ; +wire \cnt_wait[2]~15_combout ; +wire \cnt_wait[1]~16_combout ; +wire \cnt_wait[0]~17_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \fifo_read_inst|rd_flag~q ; +wire \fifo_read_inst|Equal4~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ; +wire \fifo_read_inst|Equal2~0_combout ; +wire \fifo_read_inst|Equal2~1_combout ; +wire \fifo_read_inst|Equal2~2_combout ; +wire \fifo_read_inst|rd_flag~0_combout ; +wire \uart_rx_inst|bit_cnt~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout ; +wire \uart_rx_inst|work_en~q ; +wire \uart_rx_inst|start_nedge~q ; +wire \uart_rx_inst|work_en~0_combout ; +wire \uart_rx_inst|always3~0_combout ; +wire \uart_tx_inst|bit_cnt[0]~5_combout ; +wire \sdram_dq[8]~input_o ; +wire \sdram_dq[9]~input_o ; +wire \sdram_dq[10]~input_o ; +wire \sdram_dq[11]~input_o ; +wire \sdram_dq[12]~input_o ; +wire \sdram_dq[13]~input_o ; +wire \sdram_dq[14]~input_o ; +wire \sdram_dq[15]~input_o ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout ; +wire \uart_rx_inst|baud_cnt[0]~13_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \uart_rx_inst|baud_cnt[2]~18 ; +wire \uart_rx_inst|baud_cnt[3]~19_combout ; +wire \uart_rx_inst|baud_cnt[3]~20 ; +wire \uart_rx_inst|baud_cnt[4]~22 ; +wire \uart_rx_inst|baud_cnt[5]~23_combout ; +wire \uart_rx_inst|Equal1~1_combout ; +wire \uart_rx_inst|baud_cnt[5]~24 ; +wire \uart_rx_inst|baud_cnt[6]~25_combout ; +wire \uart_rx_inst|baud_cnt[6]~26 ; +wire \uart_rx_inst|baud_cnt[7]~27_combout ; +wire \uart_rx_inst|baud_cnt[7]~28 ; +wire \uart_rx_inst|baud_cnt[8]~29_combout ; +wire \uart_rx_inst|Equal1~0_combout ; +wire \uart_rx_inst|baud_cnt[8]~30 ; +wire \uart_rx_inst|baud_cnt[9]~31_combout ; +wire \uart_rx_inst|baud_cnt[9]~32 ; +wire \uart_rx_inst|baud_cnt[10]~34 ; +wire \uart_rx_inst|baud_cnt[11]~35_combout ; +wire \uart_rx_inst|Equal1~2_combout ; +wire \uart_rx_inst|baud_cnt[10]~33_combout ; +wire \uart_rx_inst|Equal1~3_combout ; +wire \uart_rx_inst|always5~0_combout ; +wire \uart_rx_inst|baud_cnt[0]~14 ; +wire \uart_rx_inst|baud_cnt[1]~15_combout ; +wire \uart_rx_inst|baud_cnt[1]~16 ; +wire \uart_rx_inst|baud_cnt[2]~17_combout ; +wire \uart_rx_inst|Equal2~0_combout ; +wire \uart_rx_inst|baud_cnt[11]~36 ; +wire \uart_rx_inst|baud_cnt[12]~37_combout ; +wire \uart_rx_inst|Equal2~1_combout ; +wire \uart_rx_inst|Equal2~2_combout ; +wire \uart_rx_inst|bit_flag~q ; +wire \uart_rx_inst|Add1~1 ; +wire \uart_rx_inst|Add1~3 ; +wire \uart_rx_inst|Add1~4_combout ; +wire \uart_rx_inst|Add1~2_combout ; +wire \uart_rx_inst|always4~0_combout ; +wire \uart_rx_inst|always4~1_combout ; +wire \uart_rx_inst|rx_flag~q ; +wire \uart_rx_inst|po_flag~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ; +wire \fifo_read_inst|read_en_dly~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout ; +wire \fifo_read_inst|Add2~0_combout ; +wire \fifo_read_inst|Add2~1 ; +wire \fifo_read_inst|Add2~3 ; +wire \fifo_read_inst|Add2~5 ; +wire \fifo_read_inst|Add2~6_combout ; +wire \fifo_read_inst|bit_cnt~0_combout ; +wire \fifo_read_inst|baud_cnt[0]~13_combout ; +wire \fifo_read_inst|baud_cnt[5]~24 ; +wire \fifo_read_inst|baud_cnt[6]~25_combout ; +wire \fifo_read_inst|baud_cnt[6]~26 ; +wire \fifo_read_inst|baud_cnt[7]~27_combout ; +wire \fifo_read_inst|baud_cnt[7]~28 ; +wire \fifo_read_inst|baud_cnt[8]~29_combout ; +wire \fifo_read_inst|Equal4~0_combout ; +wire \fifo_read_inst|baud_cnt[3]~19_combout ; +wire \fifo_read_inst|Equal4~1_combout ; +wire \fifo_read_inst|baud_cnt[8]~30 ; +wire \fifo_read_inst|baud_cnt[9]~32 ; +wire \fifo_read_inst|baud_cnt[10]~33_combout ; +wire \fifo_read_inst|baud_cnt[10]~34 ; +wire \fifo_read_inst|baud_cnt[11]~36 ; +wire \fifo_read_inst|baud_cnt[12]~37_combout ; +wire \fifo_read_inst|Equal4~3_combout ; +wire \fifo_read_inst|baud_cnt[0]~14 ; +wire \fifo_read_inst|baud_cnt[1]~16 ; +wire \fifo_read_inst|baud_cnt[2]~17_combout ; +wire \fifo_read_inst|baud_cnt[2]~18 ; +wire \fifo_read_inst|baud_cnt[3]~20 ; +wire \fifo_read_inst|baud_cnt[4]~22 ; +wire \fifo_read_inst|baud_cnt[5]~23_combout ; +wire \fifo_read_inst|Equal5~0_combout ; +wire \fifo_read_inst|Equal5~2_combout ; +wire \fifo_read_inst|bit_flag~q ; +wire \fifo_read_inst|Add2~2_combout ; +wire \fifo_read_inst|bit_cnt~1_combout ; +wire \fifo_read_inst|always5~0_combout ; +wire \fifo_read_inst|always5~1_combout ; +wire \fifo_read_inst|rd_en~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ; +wire \Equal2~1_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ; +wire \fifo_read_inst|read_en~0_combout ; +wire \fifo_read_inst|read_en~1_combout ; +wire \fifo_read_inst|read_en~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ; +wire \Equal2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ; +wire \rx~input_o ; +wire \uart_rx_inst|rx_reg1~0_combout ; +wire \uart_rx_inst|rx_reg1~q ; +wire \uart_rx_inst|rx_reg2~feeder_combout ; +wire \uart_rx_inst|rx_reg2~q ; +wire \uart_rx_inst|rx_reg3~feeder_combout ; +wire \uart_rx_inst|rx_reg3~q ; +wire \uart_rx_inst|rx_data[7]~0_combout ; +wire \uart_rx_inst|bit_cnt~0_combout ; +wire \uart_rx_inst|always8~0_combout ; +wire \uart_rx_inst|rx_data[5]~feeder_combout ; +wire \uart_rx_inst|rx_data[4]~feeder_combout ; +wire \uart_rx_inst|rx_data[3]~feeder_combout ; +wire \uart_rx_inst|rx_data[2]~feeder_combout ; +wire \uart_rx_inst|rx_data[1]~feeder_combout ; +wire \uart_rx_inst|rx_data[0]~feeder_combout ; +wire \uart_rx_inst|po_data[0]~feeder_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \uart_rx_inst|po_data[1]~feeder_combout ; +wire \uart_rx_inst|po_data[2]~feeder_combout ; +wire \uart_rx_inst|po_data[3]~feeder_combout ; +wire \uart_rx_inst|po_data[4]~feeder_combout ; +wire \uart_rx_inst|po_data[5]~feeder_combout ; +wire \uart_rx_inst|po_data[6]~feeder_combout ; +wire \~GND~combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ; +wire \sys_clk~inputclkctrl_outclk ; +wire \uart_tx_inst|baud_cnt[0]~13_combout ; +wire \uart_tx_inst|baud_cnt[11]~35_combout ; +wire \uart_tx_inst|Equal1~0_combout ; +wire \uart_tx_inst|baud_cnt[9]~31_combout ; +wire \uart_tx_inst|Equal1~1_combout ; +wire \uart_tx_inst|baud_cnt[1]~15_combout ; +wire \uart_tx_inst|Equal1~2_combout ; +wire \fifo_read_inst|tx_flag~q ; +wire \uart_tx_inst|always3~0_combout ; +wire \uart_tx_inst|bit_cnt[1]~2_combout ; +wire \uart_tx_inst|bit_cnt[2]~3_combout ; +wire \uart_tx_inst|always0~1_combout ; +wire \uart_tx_inst|work_en~0_combout ; +wire \uart_tx_inst|work_en~q ; +wire \uart_tx_inst|always1~0_combout ; +wire \uart_tx_inst|baud_cnt[0]~14 ; +wire \uart_tx_inst|baud_cnt[1]~16 ; +wire \uart_tx_inst|baud_cnt[2]~17_combout ; +wire \uart_tx_inst|baud_cnt[2]~18 ; +wire \uart_tx_inst|baud_cnt[3]~20 ; +wire \uart_tx_inst|baud_cnt[4]~22 ; +wire \uart_tx_inst|baud_cnt[5]~23_combout ; +wire \uart_tx_inst|baud_cnt[5]~24 ; +wire \uart_tx_inst|baud_cnt[6]~25_combout ; +wire \uart_tx_inst|baud_cnt[6]~26 ; +wire \uart_tx_inst|baud_cnt[7]~27_combout ; +wire \uart_tx_inst|baud_cnt[7]~28 ; +wire \uart_tx_inst|baud_cnt[8]~29_combout ; +wire \uart_tx_inst|baud_cnt[8]~30 ; +wire \uart_tx_inst|baud_cnt[9]~32 ; +wire \uart_tx_inst|baud_cnt[10]~33_combout ; +wire \uart_tx_inst|baud_cnt[10]~34 ; +wire \uart_tx_inst|baud_cnt[11]~36 ; +wire \uart_tx_inst|baud_cnt[12]~37_combout ; +wire \uart_tx_inst|Equal2~0_combout ; +wire \uart_tx_inst|Equal2~1_combout ; +wire \uart_tx_inst|bit_flag~q ; +wire \uart_tx_inst|always0~0_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ; +wire \sdram_dq[0]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ; +wire \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ; +wire \sdram_dq[1]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout ; +wire \sdram_dq[2]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout ; +wire \sdram_dq[3]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout ; +wire \sdram_dq[4]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout ; +wire \sdram_dq[5]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout ; +wire \sdram_dq[6]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout ; +wire \sdram_dq[7]~input_o ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT ; +wire \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout ; +wire \uart_tx_inst|tx~4_combout ; +wire \uart_tx_inst|tx~3_combout ; +wire \uart_tx_inst|tx~5_combout ; +wire \uart_tx_inst|tx~q ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout ; +wire \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a ; +wire [15:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a ; +wire [9:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit ; +wire [23:0] data_num; +wire [15:0] cnt_wait; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [7:0] \uart_rx_inst|rx_data ; +wire [7:0] \uart_rx_inst|po_data ; +wire [3:0] \uart_rx_inst|bit_cnt ; +wire [12:0] \uart_rx_inst|baud_cnt ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g ; +wire [9:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a ; +wire [2:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a ; +wire [15:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a ; +wire [10:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd ; +wire [1:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref ; +wire [2:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk ; +wire [14:0] \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us ; +wire [2:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk ; +wire [1:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref ; +wire [9:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd ; +wire [1:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba ; +wire [12:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr ; +wire [9:0] \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk ; +wire [3:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd ; +wire [12:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr ; +wire [15:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg ; +wire [9:0] \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk ; +wire [9:0] \fifo_read_inst|cnt_read ; +wire [3:0] \fifo_read_inst|bit_cnt ; +wire [12:0] \fifo_read_inst|baud_cnt ; +wire [9:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit ; +wire [7:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b ; +wire [9:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit ; +wire [3:0] \uart_tx_inst|bit_cnt ; +wire [12:0] \uart_tx_inst|baud_cnt ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; +wire [8:0] \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus ; +wire [8:0] \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; +wire [8:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus ; +wire [8:0] \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [0] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [0]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [1] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [1]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [2] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [2]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [3] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [3]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [4] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [4]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [5] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [5]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [6] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [6]; +assign \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [7] = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus [7]; + +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7] = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; + +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [0]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [1]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [2]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [3]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [4]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [5]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [6]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [7]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [8] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus [8]; + +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [9] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [0]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [10] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [1]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [11] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [2]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [12] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [3]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [13] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [4]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [14] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [5]; +assign \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [15] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus [6]; + +// Location: M9K_X25_Y18_N0 +cycloneive_ram_block \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 ( + .portawe(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(gnd), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .ena1(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(gnd), + .portadatain({gnd,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0]}), + .portaaddr({\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2], +\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1],\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]}), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .clk0_core_clock_enable = "ena0"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .clk1_core_clock_enable = "ena1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .clk1_input_clock_enable = "ena1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .data_interleave_offset_in_bits = 1; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .data_interleave_width_in_bits = 1; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .logical_ram_name = "fifo_read:fifo_read_inst|read_fifo:read_fifo_inst|scfifo:scfifo_component|scfifo_un21:auto_generated|a_dpfifo_5u21:dpfifo|dpram_d811:FIFOram|altsyncram_c3k1:altsyncram1|ALTSYNCRAM"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .operation_mode = "dual_port"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_address_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_address_width = 10; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_byte_enable_clock = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_data_out_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_data_out_clock = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_data_width = 9; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_first_address = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_first_bit_number = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_last_address = 1023; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_logical_ram_depth = 1024; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_logical_ram_width = 8; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_address_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_address_clock = "clock1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_address_width = 10; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_data_out_clear = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_data_out_clock = "none"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_data_width = 9; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_first_address = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_first_bit_number = 0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_last_address = 1023; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_logical_ram_depth = 1024; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_logical_ram_width = 8; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .port_b_read_enable_clock = "clock1"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: FF_X24_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y21_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y23_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y23_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y18_N11 +dffeas \uart_tx_inst|baud_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y18_N13 +dffeas \uart_tx_inst|baud_cnt[4] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0] & ((GND) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0]))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0] $ (GND))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0 .lut_mask = 16'h66BB; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N10 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[3]~19_combout = (\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt[2]~18 )) # (!\uart_tx_inst|baud_cnt [3] & ((\uart_tx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_tx_inst|baud_cnt[3]~20 = CARRY((!\uart_tx_inst|baud_cnt[2]~18 ) # (!\uart_tx_inst|baud_cnt [3])) + + .dataa(\uart_tx_inst|baud_cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[2]~18 ), + .combout(\uart_tx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_tx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N12 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[4]~21_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt[3]~20 & VCC)) +// \uart_tx_inst|baud_cnt[4]~22 = CARRY((\uart_tx_inst|baud_cnt [4] & !\uart_tx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[3]~20 ), + .combout(\uart_tx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_tx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_tx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [13] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N8 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N10 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N14 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N18 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7] $ (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ) # (VCC))))) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]) # ((GND)))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7 .lut_mask = 16'h5A6F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] & ((VCC)))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] $ (((VCC) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] $ (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8 .lut_mask = 16'hA509; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT ) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N7 +dffeas \fifo_read_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N13 +dffeas \fifo_read_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N23 +dffeas \fifo_read_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N27 +dffeas \fifo_read_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N12 +cycloneive_lcell_comb \fifo_read_inst|Add2~4 ( +// Equation(s): +// \fifo_read_inst|Add2~4_combout = (\fifo_read_inst|bit_cnt [2] & (\fifo_read_inst|Add2~3 $ (GND))) # (!\fifo_read_inst|bit_cnt [2] & (!\fifo_read_inst|Add2~3 & VCC)) +// \fifo_read_inst|Add2~5 = CARRY((\fifo_read_inst|bit_cnt [2] & !\fifo_read_inst|Add2~3 )) + + .dataa(\fifo_read_inst|bit_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|Add2~3 ), + .combout(\fifo_read_inst|Add2~4_combout ), + .cout(\fifo_read_inst|Add2~5 )); +// synopsys translate_off +defparam \fifo_read_inst|Add2~4 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|Add2~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y24_N9 +dffeas \data_num[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[0]~24_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[0]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[0] .is_wysiwyg = "true"; +defparam \data_num[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N13 +dffeas \data_num[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[2]~28_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[2]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[2] .is_wysiwyg = "true"; +defparam \data_num[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N11 +dffeas \data_num[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[1]~26_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[1]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[1] .is_wysiwyg = "true"; +defparam \data_num[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N15 +dffeas \data_num[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[3]~30_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[3]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[3] .is_wysiwyg = "true"; +defparam \data_num[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N17 +dffeas \data_num[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[4]~32_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[4]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[4] .is_wysiwyg = "true"; +defparam \data_num[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N19 +dffeas \data_num[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[5]~34_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[5]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[5] .is_wysiwyg = "true"; +defparam \data_num[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N21 +dffeas \data_num[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[6]~36_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[6]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[6] .is_wysiwyg = "true"; +defparam \data_num[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N23 +dffeas \data_num[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[7]~38_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[7]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[7] .is_wysiwyg = "true"; +defparam \data_num[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N25 +dffeas \data_num[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[8]~40_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[8]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[8] .is_wysiwyg = "true"; +defparam \data_num[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N27 +dffeas \data_num[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[9]~42_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[9]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[9] .is_wysiwyg = "true"; +defparam \data_num[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N29 +dffeas \data_num[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[10]~44_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[10]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[10] .is_wysiwyg = "true"; +defparam \data_num[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y24_N31 +dffeas \data_num[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[11]~46_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[11]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[11] .is_wysiwyg = "true"; +defparam \data_num[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N1 +dffeas \data_num[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[12]~48_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[12]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[12] .is_wysiwyg = "true"; +defparam \data_num[12] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N3 +dffeas \data_num[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[13]~50_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[13]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[13] .is_wysiwyg = "true"; +defparam \data_num[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N5 +dffeas \data_num[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[14]~52_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[14]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[14] .is_wysiwyg = "true"; +defparam \data_num[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N7 +dffeas \data_num[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[15]~54_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[15]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[15] .is_wysiwyg = "true"; +defparam \data_num[15] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N9 +dffeas \data_num[16] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[16]~56_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[16]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[16] .is_wysiwyg = "true"; +defparam \data_num[16] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N11 +dffeas \data_num[17] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[17]~58_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[17]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[17] .is_wysiwyg = "true"; +defparam \data_num[17] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N13 +dffeas \data_num[18] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[18]~60_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[18]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[18] .is_wysiwyg = "true"; +defparam \data_num[18] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N15 +dffeas \data_num[19] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[19]~62_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[19]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[19] .is_wysiwyg = "true"; +defparam \data_num[19] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N17 +dffeas \data_num[20] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[20]~64_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[20]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[20] .is_wysiwyg = "true"; +defparam \data_num[20] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N19 +dffeas \data_num[21] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[21]~66_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[21]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[21] .is_wysiwyg = "true"; +defparam \data_num[21] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N21 +dffeas \data_num[22] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[22]~68_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[22]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[22] .is_wysiwyg = "true"; +defparam \data_num[22] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y23_N23 +dffeas \data_num[23] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\data_num[23]~70_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\read_valid~q ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(data_num[23]), + .prn(vcc)); +// synopsys translate_off +defparam \data_num[23] .is_wysiwyg = "true"; +defparam \data_num[23] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N0 +cycloneive_lcell_comb \Add1~0 ( +// Equation(s): +// \Add1~0_combout = cnt_wait[0] $ (VCC) +// \Add1~1 = CARRY(cnt_wait[0]) + + .dataa(gnd), + .datab(cnt_wait[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\Add1~0_combout ), + .cout(\Add1~1 )); +// synopsys translate_off +defparam \Add1~0 .lut_mask = 16'h33CC; +defparam \Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N2 +cycloneive_lcell_comb \Add1~2 ( +// Equation(s): +// \Add1~2_combout = (cnt_wait[1] & (!\Add1~1 )) # (!cnt_wait[1] & ((\Add1~1 ) # (GND))) +// \Add1~3 = CARRY((!\Add1~1 ) # (!cnt_wait[1])) + + .dataa(cnt_wait[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~1 ), + .combout(\Add1~2_combout ), + .cout(\Add1~3 )); +// synopsys translate_off +defparam \Add1~2 .lut_mask = 16'h5A5F; +defparam \Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N4 +cycloneive_lcell_comb \Add1~4 ( +// Equation(s): +// \Add1~4_combout = (cnt_wait[2] & (\Add1~3 $ (GND))) # (!cnt_wait[2] & (!\Add1~3 & VCC)) +// \Add1~5 = CARRY((cnt_wait[2] & !\Add1~3 )) + + .dataa(gnd), + .datab(cnt_wait[2]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~3 ), + .combout(\Add1~4_combout ), + .cout(\Add1~5 )); +// synopsys translate_off +defparam \Add1~4 .lut_mask = 16'hC30C; +defparam \Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N6 +cycloneive_lcell_comb \Add1~6 ( +// Equation(s): +// \Add1~6_combout = (cnt_wait[3] & (!\Add1~5 )) # (!cnt_wait[3] & ((\Add1~5 ) # (GND))) +// \Add1~7 = CARRY((!\Add1~5 ) # (!cnt_wait[3])) + + .dataa(gnd), + .datab(cnt_wait[3]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~5 ), + .combout(\Add1~6_combout ), + .cout(\Add1~7 )); +// synopsys translate_off +defparam \Add1~6 .lut_mask = 16'h3C3F; +defparam \Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N8 +cycloneive_lcell_comb \Add1~8 ( +// Equation(s): +// \Add1~8_combout = (cnt_wait[4] & (\Add1~7 $ (GND))) # (!cnt_wait[4] & (!\Add1~7 & VCC)) +// \Add1~9 = CARRY((cnt_wait[4] & !\Add1~7 )) + + .dataa(cnt_wait[4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~7 ), + .combout(\Add1~8_combout ), + .cout(\Add1~9 )); +// synopsys translate_off +defparam \Add1~8 .lut_mask = 16'hA50A; +defparam \Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N10 +cycloneive_lcell_comb \Add1~10 ( +// Equation(s): +// \Add1~10_combout = (cnt_wait[5] & (!\Add1~9 )) # (!cnt_wait[5] & ((\Add1~9 ) # (GND))) +// \Add1~11 = CARRY((!\Add1~9 ) # (!cnt_wait[5])) + + .dataa(cnt_wait[5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~9 ), + .combout(\Add1~10_combout ), + .cout(\Add1~11 )); +// synopsys translate_off +defparam \Add1~10 .lut_mask = 16'h5A5F; +defparam \Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N12 +cycloneive_lcell_comb \Add1~12 ( +// Equation(s): +// \Add1~12_combout = (cnt_wait[6] & (\Add1~11 $ (GND))) # (!cnt_wait[6] & (!\Add1~11 & VCC)) +// \Add1~13 = CARRY((cnt_wait[6] & !\Add1~11 )) + + .dataa(cnt_wait[6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~11 ), + .combout(\Add1~12_combout ), + .cout(\Add1~13 )); +// synopsys translate_off +defparam \Add1~12 .lut_mask = 16'hA50A; +defparam \Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N14 +cycloneive_lcell_comb \Add1~14 ( +// Equation(s): +// \Add1~14_combout = (cnt_wait[7] & (!\Add1~13 )) # (!cnt_wait[7] & ((\Add1~13 ) # (GND))) +// \Add1~15 = CARRY((!\Add1~13 ) # (!cnt_wait[7])) + + .dataa(cnt_wait[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~13 ), + .combout(\Add1~14_combout ), + .cout(\Add1~15 )); +// synopsys translate_off +defparam \Add1~14 .lut_mask = 16'h5A5F; +defparam \Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N16 +cycloneive_lcell_comb \Add1~16 ( +// Equation(s): +// \Add1~16_combout = (cnt_wait[8] & (\Add1~15 $ (GND))) # (!cnt_wait[8] & (!\Add1~15 & VCC)) +// \Add1~17 = CARRY((cnt_wait[8] & !\Add1~15 )) + + .dataa(cnt_wait[8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~15 ), + .combout(\Add1~16_combout ), + .cout(\Add1~17 )); +// synopsys translate_off +defparam \Add1~16 .lut_mask = 16'hA50A; +defparam \Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N18 +cycloneive_lcell_comb \Add1~18 ( +// Equation(s): +// \Add1~18_combout = (cnt_wait[9] & (!\Add1~17 )) # (!cnt_wait[9] & ((\Add1~17 ) # (GND))) +// \Add1~19 = CARRY((!\Add1~17 ) # (!cnt_wait[9])) + + .dataa(gnd), + .datab(cnt_wait[9]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~17 ), + .combout(\Add1~18_combout ), + .cout(\Add1~19 )); +// synopsys translate_off +defparam \Add1~18 .lut_mask = 16'h3C3F; +defparam \Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N20 +cycloneive_lcell_comb \Add1~20 ( +// Equation(s): +// \Add1~20_combout = (cnt_wait[10] & (\Add1~19 $ (GND))) # (!cnt_wait[10] & (!\Add1~19 & VCC)) +// \Add1~21 = CARRY((cnt_wait[10] & !\Add1~19 )) + + .dataa(cnt_wait[10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~19 ), + .combout(\Add1~20_combout ), + .cout(\Add1~21 )); +// synopsys translate_off +defparam \Add1~20 .lut_mask = 16'hA50A; +defparam \Add1~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N22 +cycloneive_lcell_comb \Add1~22 ( +// Equation(s): +// \Add1~22_combout = (cnt_wait[11] & (!\Add1~21 )) # (!cnt_wait[11] & ((\Add1~21 ) # (GND))) +// \Add1~23 = CARRY((!\Add1~21 ) # (!cnt_wait[11])) + + .dataa(gnd), + .datab(cnt_wait[11]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~21 ), + .combout(\Add1~22_combout ), + .cout(\Add1~23 )); +// synopsys translate_off +defparam \Add1~22 .lut_mask = 16'h3C3F; +defparam \Add1~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N24 +cycloneive_lcell_comb \Add1~24 ( +// Equation(s): +// \Add1~24_combout = (cnt_wait[12] & (\Add1~23 $ (GND))) # (!cnt_wait[12] & (!\Add1~23 & VCC)) +// \Add1~25 = CARRY((cnt_wait[12] & !\Add1~23 )) + + .dataa(gnd), + .datab(cnt_wait[12]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~23 ), + .combout(\Add1~24_combout ), + .cout(\Add1~25 )); +// synopsys translate_off +defparam \Add1~24 .lut_mask = 16'hC30C; +defparam \Add1~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N26 +cycloneive_lcell_comb \Add1~26 ( +// Equation(s): +// \Add1~26_combout = (cnt_wait[13] & (!\Add1~25 )) # (!cnt_wait[13] & ((\Add1~25 ) # (GND))) +// \Add1~27 = CARRY((!\Add1~25 ) # (!cnt_wait[13])) + + .dataa(gnd), + .datab(cnt_wait[13]), + .datac(gnd), + .datad(vcc), + .cin(\Add1~25 ), + .combout(\Add1~26_combout ), + .cout(\Add1~27 )); +// synopsys translate_off +defparam \Add1~26 .lut_mask = 16'h3C3F; +defparam \Add1~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N28 +cycloneive_lcell_comb \Add1~28 ( +// Equation(s): +// \Add1~28_combout = (cnt_wait[14] & (\Add1~27 $ (GND))) # (!cnt_wait[14] & (!\Add1~27 & VCC)) +// \Add1~29 = CARRY((cnt_wait[14] & !\Add1~27 )) + + .dataa(cnt_wait[14]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\Add1~27 ), + .combout(\Add1~28_combout ), + .cout(\Add1~29 )); +// synopsys translate_off +defparam \Add1~28 .lut_mask = 16'hA50A; +defparam \Add1~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y26_N30 +cycloneive_lcell_comb \Add1~30 ( +// Equation(s): +// \Add1~30_combout = \Add1~29 $ (cnt_wait[15]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(cnt_wait[15]), + .cin(\Add1~29 ), + .combout(\Add1~30_combout ), + .cout()); +// synopsys translate_off +defparam \Add1~30 .lut_mask = 16'h0FF0; +defparam \Add1~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N6 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[1]~15 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[1]~15_combout = (\fifo_read_inst|baud_cnt [1] & (!\fifo_read_inst|baud_cnt[0]~14 )) # (!\fifo_read_inst|baud_cnt [1] & ((\fifo_read_inst|baud_cnt[0]~14 ) # (GND))) +// \fifo_read_inst|baud_cnt[1]~16 = CARRY((!\fifo_read_inst|baud_cnt[0]~14 ) # (!\fifo_read_inst|baud_cnt [1])) + + .dataa(\fifo_read_inst|baud_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[0]~14 ), + .combout(\fifo_read_inst|baud_cnt[1]~15_combout ), + .cout(\fifo_read_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N12 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[4]~21 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[4]~21_combout = (\fifo_read_inst|baud_cnt [4] & (\fifo_read_inst|baud_cnt[3]~20 $ (GND))) # (!\fifo_read_inst|baud_cnt [4] & (!\fifo_read_inst|baud_cnt[3]~20 & VCC)) +// \fifo_read_inst|baud_cnt[4]~22 = CARRY((\fifo_read_inst|baud_cnt [4] & !\fifo_read_inst|baud_cnt[3]~20 )) + + .dataa(\fifo_read_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[3]~20 ), + .combout(\fifo_read_inst|baud_cnt[4]~21_combout ), + .cout(\fifo_read_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N22 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[9]~31 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[9]~31_combout = (\fifo_read_inst|baud_cnt [9] & (!\fifo_read_inst|baud_cnt[8]~30 )) # (!\fifo_read_inst|baud_cnt [9] & ((\fifo_read_inst|baud_cnt[8]~30 ) # (GND))) +// \fifo_read_inst|baud_cnt[9]~32 = CARRY((!\fifo_read_inst|baud_cnt[8]~30 ) # (!\fifo_read_inst|baud_cnt [9])) + + .dataa(\fifo_read_inst|baud_cnt [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[8]~30 ), + .combout(\fifo_read_inst|baud_cnt[9]~31_combout ), + .cout(\fifo_read_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[9]~31 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N26 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[11]~35 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[11]~35_combout = (\fifo_read_inst|baud_cnt [11] & (!\fifo_read_inst|baud_cnt[10]~34 )) # (!\fifo_read_inst|baud_cnt [11] & ((\fifo_read_inst|baud_cnt[10]~34 ) # (GND))) +// \fifo_read_inst|baud_cnt[11]~36 = CARRY((!\fifo_read_inst|baud_cnt[10]~34 ) # (!\fifo_read_inst|baud_cnt [11])) + + .dataa(\fifo_read_inst|baud_cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[10]~34 ), + .combout(\fifo_read_inst|baud_cnt[11]~35_combout ), + .cout(\fifo_read_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N8 +cycloneive_lcell_comb \data_num[0]~24 ( +// Equation(s): +// \data_num[0]~24_combout = (\uart_rx_inst|po_flag~q & (data_num[0] $ (VCC))) # (!\uart_rx_inst|po_flag~q & (data_num[0] & VCC)) +// \data_num[0]~25 = CARRY((\uart_rx_inst|po_flag~q & data_num[0])) + + .dataa(\uart_rx_inst|po_flag~q ), + .datab(data_num[0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\data_num[0]~24_combout ), + .cout(\data_num[0]~25 )); +// synopsys translate_off +defparam \data_num[0]~24 .lut_mask = 16'h6688; +defparam \data_num[0]~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N10 +cycloneive_lcell_comb \data_num[1]~26 ( +// Equation(s): +// \data_num[1]~26_combout = (data_num[1] & (!\data_num[0]~25 )) # (!data_num[1] & ((\data_num[0]~25 ) # (GND))) +// \data_num[1]~27 = CARRY((!\data_num[0]~25 ) # (!data_num[1])) + + .dataa(data_num[1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[0]~25 ), + .combout(\data_num[1]~26_combout ), + .cout(\data_num[1]~27 )); +// synopsys translate_off +defparam \data_num[1]~26 .lut_mask = 16'h5A5F; +defparam \data_num[1]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N12 +cycloneive_lcell_comb \data_num[2]~28 ( +// Equation(s): +// \data_num[2]~28_combout = (data_num[2] & (\data_num[1]~27 $ (GND))) # (!data_num[2] & (!\data_num[1]~27 & VCC)) +// \data_num[2]~29 = CARRY((data_num[2] & !\data_num[1]~27 )) + + .dataa(data_num[2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[1]~27 ), + .combout(\data_num[2]~28_combout ), + .cout(\data_num[2]~29 )); +// synopsys translate_off +defparam \data_num[2]~28 .lut_mask = 16'hA50A; +defparam \data_num[2]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N14 +cycloneive_lcell_comb \data_num[3]~30 ( +// Equation(s): +// \data_num[3]~30_combout = (data_num[3] & (!\data_num[2]~29 )) # (!data_num[3] & ((\data_num[2]~29 ) # (GND))) +// \data_num[3]~31 = CARRY((!\data_num[2]~29 ) # (!data_num[3])) + + .dataa(gnd), + .datab(data_num[3]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[2]~29 ), + .combout(\data_num[3]~30_combout ), + .cout(\data_num[3]~31 )); +// synopsys translate_off +defparam \data_num[3]~30 .lut_mask = 16'h3C3F; +defparam \data_num[3]~30 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N16 +cycloneive_lcell_comb \data_num[4]~32 ( +// Equation(s): +// \data_num[4]~32_combout = (data_num[4] & (\data_num[3]~31 $ (GND))) # (!data_num[4] & (!\data_num[3]~31 & VCC)) +// \data_num[4]~33 = CARRY((data_num[4] & !\data_num[3]~31 )) + + .dataa(gnd), + .datab(data_num[4]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[3]~31 ), + .combout(\data_num[4]~32_combout ), + .cout(\data_num[4]~33 )); +// synopsys translate_off +defparam \data_num[4]~32 .lut_mask = 16'hC30C; +defparam \data_num[4]~32 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N18 +cycloneive_lcell_comb \data_num[5]~34 ( +// Equation(s): +// \data_num[5]~34_combout = (data_num[5] & (!\data_num[4]~33 )) # (!data_num[5] & ((\data_num[4]~33 ) # (GND))) +// \data_num[5]~35 = CARRY((!\data_num[4]~33 ) # (!data_num[5])) + + .dataa(gnd), + .datab(data_num[5]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[4]~33 ), + .combout(\data_num[5]~34_combout ), + .cout(\data_num[5]~35 )); +// synopsys translate_off +defparam \data_num[5]~34 .lut_mask = 16'h3C3F; +defparam \data_num[5]~34 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N20 +cycloneive_lcell_comb \data_num[6]~36 ( +// Equation(s): +// \data_num[6]~36_combout = (data_num[6] & (\data_num[5]~35 $ (GND))) # (!data_num[6] & (!\data_num[5]~35 & VCC)) +// \data_num[6]~37 = CARRY((data_num[6] & !\data_num[5]~35 )) + + .dataa(gnd), + .datab(data_num[6]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[5]~35 ), + .combout(\data_num[6]~36_combout ), + .cout(\data_num[6]~37 )); +// synopsys translate_off +defparam \data_num[6]~36 .lut_mask = 16'hC30C; +defparam \data_num[6]~36 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N22 +cycloneive_lcell_comb \data_num[7]~38 ( +// Equation(s): +// \data_num[7]~38_combout = (data_num[7] & (!\data_num[6]~37 )) # (!data_num[7] & ((\data_num[6]~37 ) # (GND))) +// \data_num[7]~39 = CARRY((!\data_num[6]~37 ) # (!data_num[7])) + + .dataa(data_num[7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[6]~37 ), + .combout(\data_num[7]~38_combout ), + .cout(\data_num[7]~39 )); +// synopsys translate_off +defparam \data_num[7]~38 .lut_mask = 16'h5A5F; +defparam \data_num[7]~38 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N24 +cycloneive_lcell_comb \data_num[8]~40 ( +// Equation(s): +// \data_num[8]~40_combout = (data_num[8] & (\data_num[7]~39 $ (GND))) # (!data_num[8] & (!\data_num[7]~39 & VCC)) +// \data_num[8]~41 = CARRY((data_num[8] & !\data_num[7]~39 )) + + .dataa(gnd), + .datab(data_num[8]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[7]~39 ), + .combout(\data_num[8]~40_combout ), + .cout(\data_num[8]~41 )); +// synopsys translate_off +defparam \data_num[8]~40 .lut_mask = 16'hC30C; +defparam \data_num[8]~40 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N26 +cycloneive_lcell_comb \data_num[9]~42 ( +// Equation(s): +// \data_num[9]~42_combout = (data_num[9] & (!\data_num[8]~41 )) # (!data_num[9] & ((\data_num[8]~41 ) # (GND))) +// \data_num[9]~43 = CARRY((!\data_num[8]~41 ) # (!data_num[9])) + + .dataa(data_num[9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[8]~41 ), + .combout(\data_num[9]~42_combout ), + .cout(\data_num[9]~43 )); +// synopsys translate_off +defparam \data_num[9]~42 .lut_mask = 16'h5A5F; +defparam \data_num[9]~42 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N28 +cycloneive_lcell_comb \data_num[10]~44 ( +// Equation(s): +// \data_num[10]~44_combout = (data_num[10] & (\data_num[9]~43 $ (GND))) # (!data_num[10] & (!\data_num[9]~43 & VCC)) +// \data_num[10]~45 = CARRY((data_num[10] & !\data_num[9]~43 )) + + .dataa(gnd), + .datab(data_num[10]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[9]~43 ), + .combout(\data_num[10]~44_combout ), + .cout(\data_num[10]~45 )); +// synopsys translate_off +defparam \data_num[10]~44 .lut_mask = 16'hC30C; +defparam \data_num[10]~44 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N30 +cycloneive_lcell_comb \data_num[11]~46 ( +// Equation(s): +// \data_num[11]~46_combout = (data_num[11] & (!\data_num[10]~45 )) # (!data_num[11] & ((\data_num[10]~45 ) # (GND))) +// \data_num[11]~47 = CARRY((!\data_num[10]~45 ) # (!data_num[11])) + + .dataa(data_num[11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[10]~45 ), + .combout(\data_num[11]~46_combout ), + .cout(\data_num[11]~47 )); +// synopsys translate_off +defparam \data_num[11]~46 .lut_mask = 16'h5A5F; +defparam \data_num[11]~46 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N0 +cycloneive_lcell_comb \data_num[12]~48 ( +// Equation(s): +// \data_num[12]~48_combout = (data_num[12] & (\data_num[11]~47 $ (GND))) # (!data_num[12] & (!\data_num[11]~47 & VCC)) +// \data_num[12]~49 = CARRY((data_num[12] & !\data_num[11]~47 )) + + .dataa(gnd), + .datab(data_num[12]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[11]~47 ), + .combout(\data_num[12]~48_combout ), + .cout(\data_num[12]~49 )); +// synopsys translate_off +defparam \data_num[12]~48 .lut_mask = 16'hC30C; +defparam \data_num[12]~48 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N2 +cycloneive_lcell_comb \data_num[13]~50 ( +// Equation(s): +// \data_num[13]~50_combout = (data_num[13] & (!\data_num[12]~49 )) # (!data_num[13] & ((\data_num[12]~49 ) # (GND))) +// \data_num[13]~51 = CARRY((!\data_num[12]~49 ) # (!data_num[13])) + + .dataa(gnd), + .datab(data_num[13]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[12]~49 ), + .combout(\data_num[13]~50_combout ), + .cout(\data_num[13]~51 )); +// synopsys translate_off +defparam \data_num[13]~50 .lut_mask = 16'h3C3F; +defparam \data_num[13]~50 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N4 +cycloneive_lcell_comb \data_num[14]~52 ( +// Equation(s): +// \data_num[14]~52_combout = (data_num[14] & (\data_num[13]~51 $ (GND))) # (!data_num[14] & (!\data_num[13]~51 & VCC)) +// \data_num[14]~53 = CARRY((data_num[14] & !\data_num[13]~51 )) + + .dataa(gnd), + .datab(data_num[14]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[13]~51 ), + .combout(\data_num[14]~52_combout ), + .cout(\data_num[14]~53 )); +// synopsys translate_off +defparam \data_num[14]~52 .lut_mask = 16'hC30C; +defparam \data_num[14]~52 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N6 +cycloneive_lcell_comb \data_num[15]~54 ( +// Equation(s): +// \data_num[15]~54_combout = (data_num[15] & (!\data_num[14]~53 )) # (!data_num[15] & ((\data_num[14]~53 ) # (GND))) +// \data_num[15]~55 = CARRY((!\data_num[14]~53 ) # (!data_num[15])) + + .dataa(data_num[15]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[14]~53 ), + .combout(\data_num[15]~54_combout ), + .cout(\data_num[15]~55 )); +// synopsys translate_off +defparam \data_num[15]~54 .lut_mask = 16'h5A5F; +defparam \data_num[15]~54 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N8 +cycloneive_lcell_comb \data_num[16]~56 ( +// Equation(s): +// \data_num[16]~56_combout = (data_num[16] & (\data_num[15]~55 $ (GND))) # (!data_num[16] & (!\data_num[15]~55 & VCC)) +// \data_num[16]~57 = CARRY((data_num[16] & !\data_num[15]~55 )) + + .dataa(gnd), + .datab(data_num[16]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[15]~55 ), + .combout(\data_num[16]~56_combout ), + .cout(\data_num[16]~57 )); +// synopsys translate_off +defparam \data_num[16]~56 .lut_mask = 16'hC30C; +defparam \data_num[16]~56 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N10 +cycloneive_lcell_comb \data_num[17]~58 ( +// Equation(s): +// \data_num[17]~58_combout = (data_num[17] & (!\data_num[16]~57 )) # (!data_num[17] & ((\data_num[16]~57 ) # (GND))) +// \data_num[17]~59 = CARRY((!\data_num[16]~57 ) # (!data_num[17])) + + .dataa(data_num[17]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[16]~57 ), + .combout(\data_num[17]~58_combout ), + .cout(\data_num[17]~59 )); +// synopsys translate_off +defparam \data_num[17]~58 .lut_mask = 16'h5A5F; +defparam \data_num[17]~58 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N12 +cycloneive_lcell_comb \data_num[18]~60 ( +// Equation(s): +// \data_num[18]~60_combout = (data_num[18] & (\data_num[17]~59 $ (GND))) # (!data_num[18] & (!\data_num[17]~59 & VCC)) +// \data_num[18]~61 = CARRY((data_num[18] & !\data_num[17]~59 )) + + .dataa(data_num[18]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\data_num[17]~59 ), + .combout(\data_num[18]~60_combout ), + .cout(\data_num[18]~61 )); +// synopsys translate_off +defparam \data_num[18]~60 .lut_mask = 16'hA50A; +defparam \data_num[18]~60 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N14 +cycloneive_lcell_comb \data_num[19]~62 ( +// Equation(s): +// \data_num[19]~62_combout = (data_num[19] & (!\data_num[18]~61 )) # (!data_num[19] & ((\data_num[18]~61 ) # (GND))) +// \data_num[19]~63 = CARRY((!\data_num[18]~61 ) # (!data_num[19])) + + .dataa(gnd), + .datab(data_num[19]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[18]~61 ), + .combout(\data_num[19]~62_combout ), + .cout(\data_num[19]~63 )); +// synopsys translate_off +defparam \data_num[19]~62 .lut_mask = 16'h3C3F; +defparam \data_num[19]~62 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N16 +cycloneive_lcell_comb \data_num[20]~64 ( +// Equation(s): +// \data_num[20]~64_combout = (data_num[20] & (\data_num[19]~63 $ (GND))) # (!data_num[20] & (!\data_num[19]~63 & VCC)) +// \data_num[20]~65 = CARRY((data_num[20] & !\data_num[19]~63 )) + + .dataa(gnd), + .datab(data_num[20]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[19]~63 ), + .combout(\data_num[20]~64_combout ), + .cout(\data_num[20]~65 )); +// synopsys translate_off +defparam \data_num[20]~64 .lut_mask = 16'hC30C; +defparam \data_num[20]~64 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N18 +cycloneive_lcell_comb \data_num[21]~66 ( +// Equation(s): +// \data_num[21]~66_combout = (data_num[21] & (!\data_num[20]~65 )) # (!data_num[21] & ((\data_num[20]~65 ) # (GND))) +// \data_num[21]~67 = CARRY((!\data_num[20]~65 ) # (!data_num[21])) + + .dataa(gnd), + .datab(data_num[21]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[20]~65 ), + .combout(\data_num[21]~66_combout ), + .cout(\data_num[21]~67 )); +// synopsys translate_off +defparam \data_num[21]~66 .lut_mask = 16'h3C3F; +defparam \data_num[21]~66 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N20 +cycloneive_lcell_comb \data_num[22]~68 ( +// Equation(s): +// \data_num[22]~68_combout = (data_num[22] & (\data_num[21]~67 $ (GND))) # (!data_num[22] & (!\data_num[21]~67 & VCC)) +// \data_num[22]~69 = CARRY((data_num[22] & !\data_num[21]~67 )) + + .dataa(gnd), + .datab(data_num[22]), + .datac(gnd), + .datad(vcc), + .cin(\data_num[21]~67 ), + .combout(\data_num[22]~68_combout ), + .cout(\data_num[22]~69 )); +// synopsys translate_off +defparam \data_num[22]~68 .lut_mask = 16'hC30C; +defparam \data_num[22]~68 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N22 +cycloneive_lcell_comb \data_num[23]~70 ( +// Equation(s): +// \data_num[23]~70_combout = data_num[23] $ (\data_num[22]~69 ) + + .dataa(data_num[23]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\data_num[22]~69 ), + .combout(\data_num[23]~70_combout ), + .cout()); +// synopsys translate_off +defparam \data_num[23]~70 .lut_mask = 16'h5A5A; +defparam \data_num[23]~70 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X28_Y26_N3 +dffeas \fifo_read_inst|cnt_read[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[1]~12_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N7 +dffeas \fifo_read_inst|cnt_read[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[3]~16_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N1 +dffeas \fifo_read_inst|cnt_read[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[0]~10_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N5 +dffeas \fifo_read_inst|cnt_read[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[2]~14_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N9 +dffeas \fifo_read_inst|cnt_read[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[4]~18_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N11 +dffeas \fifo_read_inst|cnt_read[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[5]~20_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N13 +dffeas \fifo_read_inst|cnt_read[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[6]~22_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N15 +dffeas \fifo_read_inst|cnt_read[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[7]~24_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N17 +dffeas \fifo_read_inst|cnt_read[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[8]~26_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X28_Y26_N19 +dffeas \fifo_read_inst|cnt_read[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|cnt_read[9]~28_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal2~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|cnt_read [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|cnt_read[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N24 +cycloneive_lcell_comb \uart_rx_inst|Add1~0 ( +// Equation(s): +// \uart_rx_inst|Add1~0_combout = (\uart_rx_inst|bit_cnt [0] & (\uart_rx_inst|bit_flag~q $ (VCC))) # (!\uart_rx_inst|bit_cnt [0] & (\uart_rx_inst|bit_flag~q & VCC)) +// \uart_rx_inst|Add1~1 = CARRY((\uart_rx_inst|bit_cnt [0] & \uart_rx_inst|bit_flag~q )) + + .dataa(\uart_rx_inst|bit_cnt [0]), + .datab(\uart_rx_inst|bit_flag~q ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|Add1~0_combout ), + .cout(\uart_rx_inst|Add1~1 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~0 .lut_mask = 16'h6688; +defparam \uart_rx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N28 +cycloneive_lcell_comb \uart_rx_inst|Add1~4 ( +// Equation(s): +// \uart_rx_inst|Add1~4_combout = (\uart_rx_inst|bit_cnt [2] & (\uart_rx_inst|Add1~3 $ (GND))) # (!\uart_rx_inst|bit_cnt [2] & (!\uart_rx_inst|Add1~3 & VCC)) +// \uart_rx_inst|Add1~5 = CARRY((\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|Add1~3 )) + + .dataa(gnd), + .datab(\uart_rx_inst|bit_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~3 ), + .combout(\uart_rx_inst|Add1~4_combout ), + .cout(\uart_rx_inst|Add1~5 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~4 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N30 +cycloneive_lcell_comb \uart_rx_inst|Add1~6 ( +// Equation(s): +// \uart_rx_inst|Add1~6_combout = \uart_rx_inst|Add1~5 $ (\uart_rx_inst|bit_cnt [3]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(\uart_rx_inst|Add1~5 ), + .combout(\uart_rx_inst|Add1~6_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Add1~6 .lut_mask = 16'h0FF0; +defparam \uart_rx_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N11 +dffeas \uart_rx_inst|baud_cnt[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[4]~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N0 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[0]~10 ( +// Equation(s): +// \fifo_read_inst|cnt_read[0]~10_combout = (\fifo_read_inst|rd_en~q & (\fifo_read_inst|cnt_read [0] $ (VCC))) # (!\fifo_read_inst|rd_en~q & (\fifo_read_inst|cnt_read [0] & VCC)) +// \fifo_read_inst|cnt_read[0]~11 = CARRY((\fifo_read_inst|rd_en~q & \fifo_read_inst|cnt_read [0])) + + .dataa(\fifo_read_inst|rd_en~q ), + .datab(\fifo_read_inst|cnt_read [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|cnt_read[0]~10_combout ), + .cout(\fifo_read_inst|cnt_read[0]~11 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[0]~10 .lut_mask = 16'h6688; +defparam \fifo_read_inst|cnt_read[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N2 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[1]~12 ( +// Equation(s): +// \fifo_read_inst|cnt_read[1]~12_combout = (\fifo_read_inst|cnt_read [1] & (!\fifo_read_inst|cnt_read[0]~11 )) # (!\fifo_read_inst|cnt_read [1] & ((\fifo_read_inst|cnt_read[0]~11 ) # (GND))) +// \fifo_read_inst|cnt_read[1]~13 = CARRY((!\fifo_read_inst|cnt_read[0]~11 ) # (!\fifo_read_inst|cnt_read [1])) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [1]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[0]~11 ), + .combout(\fifo_read_inst|cnt_read[1]~12_combout ), + .cout(\fifo_read_inst|cnt_read[1]~13 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[1]~12 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|cnt_read[1]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N4 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[2]~14 ( +// Equation(s): +// \fifo_read_inst|cnt_read[2]~14_combout = (\fifo_read_inst|cnt_read [2] & (\fifo_read_inst|cnt_read[1]~13 $ (GND))) # (!\fifo_read_inst|cnt_read [2] & (!\fifo_read_inst|cnt_read[1]~13 & VCC)) +// \fifo_read_inst|cnt_read[2]~15 = CARRY((\fifo_read_inst|cnt_read [2] & !\fifo_read_inst|cnt_read[1]~13 )) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [2]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[1]~13 ), + .combout(\fifo_read_inst|cnt_read[2]~14_combout ), + .cout(\fifo_read_inst|cnt_read[2]~15 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[2]~14 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|cnt_read[2]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N6 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[3]~16 ( +// Equation(s): +// \fifo_read_inst|cnt_read[3]~16_combout = (\fifo_read_inst|cnt_read [3] & (!\fifo_read_inst|cnt_read[2]~15 )) # (!\fifo_read_inst|cnt_read [3] & ((\fifo_read_inst|cnt_read[2]~15 ) # (GND))) +// \fifo_read_inst|cnt_read[3]~17 = CARRY((!\fifo_read_inst|cnt_read[2]~15 ) # (!\fifo_read_inst|cnt_read [3])) + + .dataa(\fifo_read_inst|cnt_read [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[2]~15 ), + .combout(\fifo_read_inst|cnt_read[3]~16_combout ), + .cout(\fifo_read_inst|cnt_read[3]~17 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[3]~16 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|cnt_read[3]~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N8 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[4]~18 ( +// Equation(s): +// \fifo_read_inst|cnt_read[4]~18_combout = (\fifo_read_inst|cnt_read [4] & (\fifo_read_inst|cnt_read[3]~17 $ (GND))) # (!\fifo_read_inst|cnt_read [4] & (!\fifo_read_inst|cnt_read[3]~17 & VCC)) +// \fifo_read_inst|cnt_read[4]~19 = CARRY((\fifo_read_inst|cnt_read [4] & !\fifo_read_inst|cnt_read[3]~17 )) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [4]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[3]~17 ), + .combout(\fifo_read_inst|cnt_read[4]~18_combout ), + .cout(\fifo_read_inst|cnt_read[4]~19 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[4]~18 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|cnt_read[4]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N10 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[5]~20 ( +// Equation(s): +// \fifo_read_inst|cnt_read[5]~20_combout = (\fifo_read_inst|cnt_read [5] & (!\fifo_read_inst|cnt_read[4]~19 )) # (!\fifo_read_inst|cnt_read [5] & ((\fifo_read_inst|cnt_read[4]~19 ) # (GND))) +// \fifo_read_inst|cnt_read[5]~21 = CARRY((!\fifo_read_inst|cnt_read[4]~19 ) # (!\fifo_read_inst|cnt_read [5])) + + .dataa(\fifo_read_inst|cnt_read [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[4]~19 ), + .combout(\fifo_read_inst|cnt_read[5]~20_combout ), + .cout(\fifo_read_inst|cnt_read[5]~21 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[5]~20 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|cnt_read[5]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N12 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[6]~22 ( +// Equation(s): +// \fifo_read_inst|cnt_read[6]~22_combout = (\fifo_read_inst|cnt_read [6] & (\fifo_read_inst|cnt_read[5]~21 $ (GND))) # (!\fifo_read_inst|cnt_read [6] & (!\fifo_read_inst|cnt_read[5]~21 & VCC)) +// \fifo_read_inst|cnt_read[6]~23 = CARRY((\fifo_read_inst|cnt_read [6] & !\fifo_read_inst|cnt_read[5]~21 )) + + .dataa(\fifo_read_inst|cnt_read [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[5]~21 ), + .combout(\fifo_read_inst|cnt_read[6]~22_combout ), + .cout(\fifo_read_inst|cnt_read[6]~23 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[6]~22 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|cnt_read[6]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N14 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[7]~24 ( +// Equation(s): +// \fifo_read_inst|cnt_read[7]~24_combout = (\fifo_read_inst|cnt_read [7] & (!\fifo_read_inst|cnt_read[6]~23 )) # (!\fifo_read_inst|cnt_read [7] & ((\fifo_read_inst|cnt_read[6]~23 ) # (GND))) +// \fifo_read_inst|cnt_read[7]~25 = CARRY((!\fifo_read_inst|cnt_read[6]~23 ) # (!\fifo_read_inst|cnt_read [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[6]~23 ), + .combout(\fifo_read_inst|cnt_read[7]~24_combout ), + .cout(\fifo_read_inst|cnt_read[7]~25 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[7]~24 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|cnt_read[7]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N16 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[8]~26 ( +// Equation(s): +// \fifo_read_inst|cnt_read[8]~26_combout = (\fifo_read_inst|cnt_read [8] & (\fifo_read_inst|cnt_read[7]~25 $ (GND))) # (!\fifo_read_inst|cnt_read [8] & (!\fifo_read_inst|cnt_read[7]~25 & VCC)) +// \fifo_read_inst|cnt_read[8]~27 = CARRY((\fifo_read_inst|cnt_read [8] & !\fifo_read_inst|cnt_read[7]~25 )) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [8]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|cnt_read[7]~25 ), + .combout(\fifo_read_inst|cnt_read[8]~26_combout ), + .cout(\fifo_read_inst|cnt_read[8]~27 )); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[8]~26 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|cnt_read[8]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N18 +cycloneive_lcell_comb \fifo_read_inst|cnt_read[9]~28 ( +// Equation(s): +// \fifo_read_inst|cnt_read[9]~28_combout = \fifo_read_inst|cnt_read [9] $ (\fifo_read_inst|cnt_read[8]~27 ) + + .dataa(gnd), + .datab(\fifo_read_inst|cnt_read [9]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|cnt_read[8]~27 ), + .combout(\fifo_read_inst|cnt_read[9]~28_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|cnt_read[9]~28 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|cnt_read[9]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N10 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[4]~21 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[4]~21_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt[3]~20 $ (GND))) # (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt[3]~20 & VCC)) +// \uart_rx_inst|baud_cnt[4]~22 = CARRY((\uart_rx_inst|baud_cnt [4] & !\uart_rx_inst|baud_cnt[3]~20 )) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[3]~20 ), + .combout(\uart_rx_inst|baud_cnt[4]~21_combout ), + .cout(\uart_rx_inst|baud_cnt[4]~22 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[4]~21 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[4]~21 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X22_Y22_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y22_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y22_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [0])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [0]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0 .lut_mask = 16'h8C9D; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N13 +dffeas \uart_tx_inst|bit_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[0]~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N6 +cycloneive_lcell_comb \uart_tx_inst|Mux0~0 ( +// Equation(s): +// \uart_tx_inst|Mux0~0_combout = (\uart_tx_inst|bit_cnt [1] & (((\uart_tx_inst|bit_cnt [0])))) # (!\uart_tx_inst|bit_cnt [1] & ((\uart_tx_inst|bit_cnt [0] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b +// [4])) # (!\uart_tx_inst|bit_cnt [0] & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [3]))))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [4]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [3]), + .datad(\uart_tx_inst|bit_cnt [0]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~0 .lut_mask = 16'hEE30; +defparam \uart_tx_inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y15_N8 +cycloneive_lcell_comb \uart_tx_inst|Mux0~1 ( +// Equation(s): +// \uart_tx_inst|Mux0~1_combout = (\uart_tx_inst|Mux0~0_combout & (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [6]) # (!\uart_tx_inst|bit_cnt [1])))) # (!\uart_tx_inst|Mux0~0_combout & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [5] & ((\uart_tx_inst|bit_cnt [1])))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [5]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [6]), + .datac(\uart_tx_inst|Mux0~0_combout ), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Mux0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Mux0~1 .lut_mask = 16'hCAF0; +defparam \uart_tx_inst|Mux0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N16 +cycloneive_lcell_comb \uart_tx_inst|tx~0 ( +// Equation(s): +// \uart_tx_inst|tx~0_combout = (\uart_tx_inst|bit_cnt [0] & ((\uart_tx_inst|bit_cnt [1] & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [2]))) # (!\uart_tx_inst|bit_cnt [1] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [0])))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [0]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~0 .lut_mask = 16'hA088; +defparam \uart_tx_inst|tx~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N10 +cycloneive_lcell_comb \uart_tx_inst|tx~1 ( +// Equation(s): +// \uart_tx_inst|tx~1_combout = (\uart_tx_inst|tx~0_combout ) # ((!\uart_tx_inst|bit_cnt [0] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [1] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|tx~0_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [1]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~1 .lut_mask = 16'hDCCC; +defparam \uart_tx_inst|tx~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N22 +cycloneive_lcell_comb \uart_tx_inst|tx~2 ( +// Equation(s): +// \uart_tx_inst|tx~2_combout = (\uart_tx_inst|bit_flag~q & ((\uart_tx_inst|bit_cnt [2] & (\uart_tx_inst|Mux0~1_combout )) # (!\uart_tx_inst|bit_cnt [2] & ((\uart_tx_inst|tx~1_combout ))))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\uart_tx_inst|Mux0~1_combout ), + .datad(\uart_tx_inst|tx~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~2 .lut_mask = 16'hA280; +defparam \uart_tx_inst|tx~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N27 +dffeas \uart_tx_inst|bit_cnt[3] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[3]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y21_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0 .lut_mask = 16'hFFAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0 .lut_mask = 16'h3111; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ) # (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1 .lut_mask = 16'hAFEF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0 .lut_mask = 16'h0CAE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N20 +cycloneive_lcell_comb \uart_tx_inst|Add1~0 ( +// Equation(s): +// \uart_tx_inst|Add1~0_combout = \uart_tx_inst|bit_cnt [2] $ (((\uart_tx_inst|bit_cnt [0] & \uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(gnd), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~0 .lut_mask = 16'h5AF0; +defparam \uart_tx_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N30 +cycloneive_lcell_comb \uart_tx_inst|Add1~1 ( +// Equation(s): +// \uart_tx_inst|Add1~1_combout = \uart_tx_inst|bit_cnt [3] $ (((\uart_tx_inst|bit_cnt [0] & (\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|bit_cnt [1])))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Add1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Add1~1 .lut_mask = 16'h78F0; +defparam \uart_tx_inst|Add1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N26 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[3]~4 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[3]~4_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [3]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~1_combout )))) + + .dataa(\uart_tx_inst|Add1~1_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [3]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[3]~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[3]~4 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[3]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0 .lut_mask = 16'h0400; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y22_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y22_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y20_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y20_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N29 +dffeas read_valid( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\read_valid~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\read_valid~q ), + .prn(vcc)); +// synopsys translate_off +defparam read_valid.is_wysiwyg = "true"; +defparam read_valid.power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0 .lut_mask = 16'h000F; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout = (\read_valid~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & ((\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout )))) + + .dataa(\read_valid~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1 .lut_mask = 16'h8088; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0 .lut_mask = 16'hFAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[13] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N12 +cycloneive_lcell_comb \uart_tx_inst|Equal1~3 ( +// Equation(s): +// \uart_tx_inst|Equal1~3_combout = (\uart_tx_inst|baud_cnt [12] & \uart_tx_inst|baud_cnt [10]) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(gnd), + .datad(\uart_tx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~3 .lut_mask = 16'hCC00; +defparam \uart_tx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N25 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N2 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout = (\fifo_read_inst|read_en_dly~q & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9] & !\fifo_read_inst|rd_en~q ))) + + .dataa(\fifo_read_inst|read_en_dly~q ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .lut_mask = 16'h0080; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N23 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N21 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N19 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N17 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N0 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] & +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .lut_mask = 16'h8000; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N15 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y24_N11 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N26 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] & +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .lut_mask = 16'h8000; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] & +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .lut_mask = 16'h8000; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N13 +dffeas \fifo_read_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|Add2~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N28 +cycloneive_lcell_comb \fifo_read_inst|Equal1~0 ( +// Equation(s): +// \fifo_read_inst|Equal1~0_combout = (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6] & (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [9]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [6]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [8]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [7]), + .cin(gnd), + .combout(\fifo_read_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal1~0 .lut_mask = 16'h0001; +defparam \fifo_read_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N2 +cycloneive_lcell_comb \fifo_read_inst|Equal1~1 ( +// Equation(s): +// \fifo_read_inst|Equal1~1_combout = (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2] & (\fifo_read_inst|Equal1~0_combout & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4] & !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]))) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [2]), + .datab(\fifo_read_inst|Equal1~0_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [4]), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [5]), + .cin(gnd), + .combout(\fifo_read_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal1~1 .lut_mask = 16'h0004; +defparam \fifo_read_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .lut_mask = 16'h50F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X27_Y23_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1~combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5 .lut_mask = 16'h9966; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X14_Y20_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2 .lut_mask = 16'h9696; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y26_N25 +dffeas \cnt_wait[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[15]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[15]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[15] .is_wysiwyg = "true"; +defparam \cnt_wait[15] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N27 +dffeas \cnt_wait[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[14]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[14]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[14] .is_wysiwyg = "true"; +defparam \cnt_wait[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N21 +dffeas \cnt_wait[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[13]~4_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[13]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[13] .is_wysiwyg = "true"; +defparam \cnt_wait[13] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N23 +dffeas \cnt_wait[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[12]~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[12]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[12] .is_wysiwyg = "true"; +defparam \cnt_wait[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N8 +cycloneive_lcell_comb \Equal0~0 ( +// Equation(s): +// \Equal0~0_combout = (!cnt_wait[12] & (!cnt_wait[15] & (!cnt_wait[14] & !cnt_wait[13]))) + + .dataa(cnt_wait[12]), + .datab(cnt_wait[15]), + .datac(cnt_wait[14]), + .datad(cnt_wait[13]), + .cin(gnd), + .combout(\Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~0 .lut_mask = 16'h0001; +defparam \Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y26_N23 +dffeas \cnt_wait[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[9]~6_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[9]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[9] .is_wysiwyg = "true"; +defparam \cnt_wait[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N9 +dffeas \cnt_wait[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[11]~7_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[11]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[11] .is_wysiwyg = "true"; +defparam \cnt_wait[11] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N11 +dffeas \cnt_wait[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[10]~8_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[10]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[10] .is_wysiwyg = "true"; +defparam \cnt_wait[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y26_N5 +dffeas \cnt_wait[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[8]~9_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[8]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[8] .is_wysiwyg = "true"; +defparam \cnt_wait[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N14 +cycloneive_lcell_comb \Equal0~1 ( +// Equation(s): +// \Equal0~1_combout = (!cnt_wait[10] & (!cnt_wait[8] & (cnt_wait[9] & !cnt_wait[11]))) + + .dataa(cnt_wait[10]), + .datab(cnt_wait[8]), + .datac(cnt_wait[9]), + .datad(cnt_wait[11]), + .cin(gnd), + .combout(\Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~1 .lut_mask = 16'h0010; +defparam \Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y26_N3 +dffeas \cnt_wait[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[7]~10_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[7]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[7] .is_wysiwyg = "true"; +defparam \cnt_wait[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N13 +dffeas \cnt_wait[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[6]~11_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[6]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[6] .is_wysiwyg = "true"; +defparam \cnt_wait[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N15 +dffeas \cnt_wait[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[5]~12_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[5]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[5] .is_wysiwyg = "true"; +defparam \cnt_wait[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N17 +dffeas \cnt_wait[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[4]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[4]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[4] .is_wysiwyg = "true"; +defparam \cnt_wait[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N10 +cycloneive_lcell_comb \Equal0~2 ( +// Equation(s): +// \Equal0~2_combout = (cnt_wait[6] & (cnt_wait[7] & (cnt_wait[5] & !cnt_wait[4]))) + + .dataa(cnt_wait[6]), + .datab(cnt_wait[7]), + .datac(cnt_wait[5]), + .datad(cnt_wait[4]), + .cin(gnd), + .combout(\Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~2 .lut_mask = 16'h0080; +defparam \Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y26_N5 +dffeas \cnt_wait[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[3]~14_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[3]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[3] .is_wysiwyg = "true"; +defparam \cnt_wait[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N7 +dffeas \cnt_wait[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[2]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[2]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[2] .is_wysiwyg = "true"; +defparam \cnt_wait[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N1 +dffeas \cnt_wait[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[1]~16_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[1]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[1] .is_wysiwyg = "true"; +defparam \cnt_wait[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y26_N19 +dffeas \cnt_wait[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\cnt_wait[0]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(cnt_wait[0]), + .prn(vcc)); +// synopsys translate_off +defparam \cnt_wait[0] .is_wysiwyg = "true"; +defparam \cnt_wait[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N28 +cycloneive_lcell_comb \Equal0~3 ( +// Equation(s): +// \Equal0~3_combout = (!cnt_wait[0] & (cnt_wait[1] & (cnt_wait[3] & cnt_wait[2]))) + + .dataa(cnt_wait[0]), + .datab(cnt_wait[1]), + .datac(cnt_wait[3]), + .datad(cnt_wait[2]), + .cin(gnd), + .combout(\Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~3 .lut_mask = 16'h4000; +defparam \Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N30 +cycloneive_lcell_comb \Equal0~4 ( +// Equation(s): +// \Equal0~4_combout = (\Equal0~2_combout & (\Equal0~3_combout & (\Equal0~0_combout & \Equal0~1_combout ))) + + .dataa(\Equal0~2_combout ), + .datab(\Equal0~3_combout ), + .datac(\Equal0~0_combout ), + .datad(\Equal0~1_combout ), + .cin(gnd), + .combout(\Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal0~4 .lut_mask = 16'h8000; +defparam \Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N16 +cycloneive_lcell_comb \read_valid~0 ( +// Equation(s): +// \read_valid~0_combout = (\Equal0~4_combout ) # ((\read_valid~q & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ) # (!\Equal2~1_combout )))) + + .dataa(\Equal2~1_combout ), + .datab(\Equal0~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .datad(\read_valid~q ), + .cin(gnd), + .combout(\read_valid~0_combout ), + .cout()); +// synopsys translate_off +defparam \read_valid~0 .lut_mask = 16'hFDCC; +defparam \read_valid~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N28 +cycloneive_lcell_comb \read_valid~1 ( +// Equation(s): +// \read_valid~1_combout = (\read_valid~0_combout ) # ((\read_valid~q & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ) # (!\Equal2~0_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .datab(\Equal2~0_combout ), + .datac(\read_valid~q ), + .datad(\read_valid~0_combout ), + .cin(gnd), + .combout(\read_valid~1_combout ), + .cout()); +// synopsys translate_off +defparam \read_valid~1 .lut_mask = 16'hFFB0; +defparam \read_valid~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0 .lut_mask = 16'hECFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk +// [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3] $ (((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0 .lut_mask = 16'h6AAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2 .lut_mask = 16'hC0C0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N10 +cycloneive_lcell_comb \fifo_read_inst|Equal1~2 ( +// Equation(s): +// \fifo_read_inst|Equal1~2_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] & \fifo_read_inst|Equal1~1_combout )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datac(gnd), + .datad(\fifo_read_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\fifo_read_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal1~2 .lut_mask = 16'h2200; +defparam \fifo_read_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N2 +cycloneive_lcell_comb \fifo_read_inst|Equal5~1 ( +// Equation(s): +// \fifo_read_inst|Equal5~1_combout = (\fifo_read_inst|baud_cnt [11] & (!\fifo_read_inst|baud_cnt [10] & (\fifo_read_inst|baud_cnt [9] & !\fifo_read_inst|baud_cnt [6]))) + + .dataa(\fifo_read_inst|baud_cnt [11]), + .datab(\fifo_read_inst|baud_cnt [10]), + .datac(\fifo_read_inst|baud_cnt [9]), + .datad(\fifo_read_inst|baud_cnt [6]), + .cin(gnd), + .combout(\fifo_read_inst|Equal5~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal5~1 .lut_mask = 16'h0020; +defparam \fifo_read_inst|Equal5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h4182; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'hF000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'hC000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout +// )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8 .lut_mask = 16'hCA0A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'h4812; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'h8008; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h2814; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'h8200; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout )) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'hF5A0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h2814; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'hE0C2; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h0004; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N0 +cycloneive_lcell_comb \Equal1~0 ( +// Equation(s): +// \Equal1~0_combout = (data_num[2]) # (((data_num[0]) # (!data_num[1])) # (!data_num[3])) + + .dataa(data_num[2]), + .datab(data_num[3]), + .datac(data_num[0]), + .datad(data_num[1]), + .cin(gnd), + .combout(\Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~0 .lut_mask = 16'hFBFF; +defparam \Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N2 +cycloneive_lcell_comb \Equal1~1 ( +// Equation(s): +// \Equal1~1_combout = (data_num[6]) # ((data_num[5]) # ((data_num[7]) # (data_num[4]))) + + .dataa(data_num[6]), + .datab(data_num[5]), + .datac(data_num[7]), + .datad(data_num[4]), + .cin(gnd), + .combout(\Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~1 .lut_mask = 16'hFFFE; +defparam \Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N4 +cycloneive_lcell_comb \Equal1~2 ( +// Equation(s): +// \Equal1~2_combout = (data_num[11]) # ((data_num[10]) # ((data_num[9]) # (data_num[8]))) + + .dataa(data_num[11]), + .datab(data_num[10]), + .datac(data_num[9]), + .datad(data_num[8]), + .cin(gnd), + .combout(\Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~2 .lut_mask = 16'hFFFE; +defparam \Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N24 +cycloneive_lcell_comb \Equal1~3 ( +// Equation(s): +// \Equal1~3_combout = (data_num[15]) # ((data_num[13]) # ((data_num[14]) # (data_num[12]))) + + .dataa(data_num[15]), + .datab(data_num[13]), + .datac(data_num[14]), + .datad(data_num[12]), + .cin(gnd), + .combout(\Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~3 .lut_mask = 16'hFFFE; +defparam \Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y24_N6 +cycloneive_lcell_comb \Equal1~4 ( +// Equation(s): +// \Equal1~4_combout = (\Equal1~3_combout ) # ((\Equal1~1_combout ) # ((\Equal1~2_combout ) # (\Equal1~0_combout ))) + + .dataa(\Equal1~3_combout ), + .datab(\Equal1~1_combout ), + .datac(\Equal1~2_combout ), + .datad(\Equal1~0_combout ), + .cin(gnd), + .combout(\Equal1~4_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~4 .lut_mask = 16'hFFFE; +defparam \Equal1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N26 +cycloneive_lcell_comb \Equal1~5 ( +// Equation(s): +// \Equal1~5_combout = (data_num[18]) # ((data_num[19]) # ((data_num[16]) # (data_num[17]))) + + .dataa(data_num[18]), + .datab(data_num[19]), + .datac(data_num[16]), + .datad(data_num[17]), + .cin(gnd), + .combout(\Equal1~5_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~5 .lut_mask = 16'hFFFE; +defparam \Equal1~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y23_N28 +cycloneive_lcell_comb \Equal1~6 ( +// Equation(s): +// \Equal1~6_combout = (data_num[22]) # ((data_num[21]) # ((data_num[23]) # (data_num[20]))) + + .dataa(data_num[22]), + .datab(data_num[21]), + .datac(data_num[23]), + .datad(data_num[20]), + .cin(gnd), + .combout(\Equal1~6_combout ), + .cout()); +// synopsys translate_off +defparam \Equal1~6 .lut_mask = 16'hFFFE; +defparam \Equal1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N18 +cycloneive_lcell_comb \cnt_wait[8]~0 ( +// Equation(s): +// \cnt_wait[8]~0_combout = (!\Equal0~4_combout & ((\Equal1~4_combout ) # ((\Equal1~5_combout ) # (\Equal1~6_combout )))) + + .dataa(\Equal1~4_combout ), + .datab(\Equal0~4_combout ), + .datac(\Equal1~5_combout ), + .datad(\Equal1~6_combout ), + .cin(gnd), + .combout(\cnt_wait[8]~0_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[8]~0 .lut_mask = 16'h3332; +defparam \cnt_wait[8]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N12 +cycloneive_lcell_comb \cnt_wait[15]~1 ( +// Equation(s): +// \cnt_wait[15]~1_combout = (\Equal1~4_combout ) # ((\Equal0~4_combout ) # ((\Equal1~5_combout ) # (\Equal1~6_combout ))) + + .dataa(\Equal1~4_combout ), + .datab(\Equal0~4_combout ), + .datac(\Equal1~5_combout ), + .datad(\Equal1~6_combout ), + .cin(gnd), + .combout(\cnt_wait[15]~1_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[15]~1 .lut_mask = 16'hFFFE; +defparam \cnt_wait[15]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N24 +cycloneive_lcell_comb \cnt_wait[15]~2 ( +// Equation(s): +// \cnt_wait[15]~2_combout = (\Add1~30_combout & (((\cnt_wait[8]~0_combout & cnt_wait[15])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~30_combout & (\cnt_wait[8]~0_combout & (cnt_wait[15]))) + + .dataa(\Add1~30_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[15]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[15]~2_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[15]~2 .lut_mask = 16'hC0EA; +defparam \cnt_wait[15]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N26 +cycloneive_lcell_comb \cnt_wait[14]~3 ( +// Equation(s): +// \cnt_wait[14]~3_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[14] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~28_combout ) # ((cnt_wait[14] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~28_combout ), + .datac(cnt_wait[14]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[14]~3_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[14]~3 .lut_mask = 16'hF444; +defparam \cnt_wait[14]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N20 +cycloneive_lcell_comb \cnt_wait[13]~4 ( +// Equation(s): +// \cnt_wait[13]~4_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[13] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~26_combout ) # ((cnt_wait[13] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~26_combout ), + .datac(cnt_wait[13]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[13]~4_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[13]~4 .lut_mask = 16'hF444; +defparam \cnt_wait[13]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N22 +cycloneive_lcell_comb \cnt_wait[12]~5 ( +// Equation(s): +// \cnt_wait[12]~5_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[12] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~24_combout ) # ((cnt_wait[12] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~24_combout ), + .datac(cnt_wait[12]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[12]~5_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[12]~5 .lut_mask = 16'hF444; +defparam \cnt_wait[12]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N22 +cycloneive_lcell_comb \cnt_wait[9]~6 ( +// Equation(s): +// \cnt_wait[9]~6_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[9] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~18_combout ) # ((cnt_wait[9] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~18_combout ), + .datac(cnt_wait[9]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[9]~6_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[9]~6 .lut_mask = 16'hF444; +defparam \cnt_wait[9]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N8 +cycloneive_lcell_comb \cnt_wait[11]~7 ( +// Equation(s): +// \cnt_wait[11]~7_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[11] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~22_combout ) # ((cnt_wait[11] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~22_combout ), + .datac(cnt_wait[11]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[11]~7_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[11]~7 .lut_mask = 16'hF444; +defparam \cnt_wait[11]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N10 +cycloneive_lcell_comb \cnt_wait[10]~8 ( +// Equation(s): +// \cnt_wait[10]~8_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[10] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~20_combout ) # ((cnt_wait[10] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~20_combout ), + .datac(cnt_wait[10]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[10]~8_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[10]~8 .lut_mask = 16'hF444; +defparam \cnt_wait[10]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N4 +cycloneive_lcell_comb \cnt_wait[8]~9 ( +// Equation(s): +// \cnt_wait[8]~9_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[8] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~16_combout ) # ((cnt_wait[8] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~16_combout ), + .datac(cnt_wait[8]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[8]~9_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[8]~9 .lut_mask = 16'hF444; +defparam \cnt_wait[8]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N2 +cycloneive_lcell_comb \cnt_wait[7]~10 ( +// Equation(s): +// \cnt_wait[7]~10_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[7] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~14_combout ) # ((cnt_wait[7] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~14_combout ), + .datac(cnt_wait[7]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[7]~10_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[7]~10 .lut_mask = 16'hF444; +defparam \cnt_wait[7]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N12 +cycloneive_lcell_comb \cnt_wait[6]~11 ( +// Equation(s): +// \cnt_wait[6]~11_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[6] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~12_combout ) # ((cnt_wait[6] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~12_combout ), + .datac(cnt_wait[6]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[6]~11_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[6]~11 .lut_mask = 16'hF444; +defparam \cnt_wait[6]~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N14 +cycloneive_lcell_comb \cnt_wait[5]~12 ( +// Equation(s): +// \cnt_wait[5]~12_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[5] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~10_combout ) # ((cnt_wait[5] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~10_combout ), + .datac(cnt_wait[5]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[5]~12_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[5]~12 .lut_mask = 16'hF444; +defparam \cnt_wait[5]~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N16 +cycloneive_lcell_comb \cnt_wait[4]~13 ( +// Equation(s): +// \cnt_wait[4]~13_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[4] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~8_combout ) # ((cnt_wait[4] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~8_combout ), + .datac(cnt_wait[4]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[4]~13_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[4]~13 .lut_mask = 16'hF444; +defparam \cnt_wait[4]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N4 +cycloneive_lcell_comb \cnt_wait[3]~14 ( +// Equation(s): +// \cnt_wait[3]~14_combout = (\Add1~6_combout & (((\cnt_wait[8]~0_combout & cnt_wait[3])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~6_combout & (\cnt_wait[8]~0_combout & (cnt_wait[3]))) + + .dataa(\Add1~6_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[3]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[3]~14_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[3]~14 .lut_mask = 16'hC0EA; +defparam \cnt_wait[3]~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N6 +cycloneive_lcell_comb \cnt_wait[2]~15 ( +// Equation(s): +// \cnt_wait[2]~15_combout = (\Add1~4_combout & (((\cnt_wait[8]~0_combout & cnt_wait[2])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~4_combout & (\cnt_wait[8]~0_combout & (cnt_wait[2]))) + + .dataa(\Add1~4_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[2]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[2]~15_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[2]~15 .lut_mask = 16'hC0EA; +defparam \cnt_wait[2]~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N0 +cycloneive_lcell_comb \cnt_wait[1]~16 ( +// Equation(s): +// \cnt_wait[1]~16_combout = (\Add1~2_combout & (((\cnt_wait[8]~0_combout & cnt_wait[1])) # (!\cnt_wait[15]~1_combout ))) # (!\Add1~2_combout & (\cnt_wait[8]~0_combout & (cnt_wait[1]))) + + .dataa(\Add1~2_combout ), + .datab(\cnt_wait[8]~0_combout ), + .datac(cnt_wait[1]), + .datad(\cnt_wait[15]~1_combout ), + .cin(gnd), + .combout(\cnt_wait[1]~16_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[1]~16 .lut_mask = 16'hC0EA; +defparam \cnt_wait[1]~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y26_N18 +cycloneive_lcell_comb \cnt_wait[0]~17 ( +// Equation(s): +// \cnt_wait[0]~17_combout = (\cnt_wait[15]~1_combout & (((cnt_wait[0] & \cnt_wait[8]~0_combout )))) # (!\cnt_wait[15]~1_combout & ((\Add1~0_combout ) # ((cnt_wait[0] & \cnt_wait[8]~0_combout )))) + + .dataa(\cnt_wait[15]~1_combout ), + .datab(\Add1~0_combout ), + .datac(cnt_wait[0]), + .datad(\cnt_wait[8]~0_combout ), + .cin(gnd), + .combout(\cnt_wait[0]~17_combout ), + .cout()); +// synopsys translate_off +defparam \cnt_wait[0]~17 .lut_mask = 16'hF444; +defparam \cnt_wait[0]~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h4812; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h0084; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ) # +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout +// & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'hAAEA; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h4812; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h4182; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout +// )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'hB830; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h0004; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N1 +dffeas \fifo_read_inst|rd_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|rd_flag~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|rd_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|rd_flag .is_wysiwyg = "true"; +defparam \fifo_read_inst|rd_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N30 +cycloneive_lcell_comb \fifo_read_inst|Equal4~2 ( +// Equation(s): +// \fifo_read_inst|Equal4~2_combout = (!\fifo_read_inst|baud_cnt [11] & (\fifo_read_inst|baud_cnt [10] & (!\fifo_read_inst|baud_cnt [9] & \fifo_read_inst|baud_cnt [6]))) + + .dataa(\fifo_read_inst|baud_cnt [11]), + .datab(\fifo_read_inst|baud_cnt [10]), + .datac(\fifo_read_inst|baud_cnt [9]), + .datad(\fifo_read_inst|baud_cnt [6]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~2 .lut_mask = 16'h0400; +defparam \fifo_read_inst|Equal4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout & ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0 .lut_mask = 16'h1030; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N23 +dffeas \uart_rx_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y22_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N28 +cycloneive_lcell_comb \fifo_read_inst|Equal2~0 ( +// Equation(s): +// \fifo_read_inst|Equal2~0_combout = (\fifo_read_inst|cnt_read [3] & (\fifo_read_inst|cnt_read [1] & (!\fifo_read_inst|cnt_read [2] & !\fifo_read_inst|cnt_read [0]))) + + .dataa(\fifo_read_inst|cnt_read [3]), + .datab(\fifo_read_inst|cnt_read [1]), + .datac(\fifo_read_inst|cnt_read [2]), + .datad(\fifo_read_inst|cnt_read [0]), + .cin(gnd), + .combout(\fifo_read_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal2~0 .lut_mask = 16'h0008; +defparam \fifo_read_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N30 +cycloneive_lcell_comb \fifo_read_inst|Equal2~1 ( +// Equation(s): +// \fifo_read_inst|Equal2~1_combout = (!\fifo_read_inst|cnt_read [6] & (!\fifo_read_inst|cnt_read [7] & (!\fifo_read_inst|cnt_read [4] & !\fifo_read_inst|cnt_read [5]))) + + .dataa(\fifo_read_inst|cnt_read [6]), + .datab(\fifo_read_inst|cnt_read [7]), + .datac(\fifo_read_inst|cnt_read [4]), + .datad(\fifo_read_inst|cnt_read [5]), + .cin(gnd), + .combout(\fifo_read_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal2~1 .lut_mask = 16'h0001; +defparam \fifo_read_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y26_N24 +cycloneive_lcell_comb \fifo_read_inst|Equal2~2 ( +// Equation(s): +// \fifo_read_inst|Equal2~2_combout = (\fifo_read_inst|Equal2~0_combout & (!\fifo_read_inst|cnt_read [9] & (\fifo_read_inst|Equal2~1_combout & !\fifo_read_inst|cnt_read [8]))) + + .dataa(\fifo_read_inst|Equal2~0_combout ), + .datab(\fifo_read_inst|cnt_read [9]), + .datac(\fifo_read_inst|Equal2~1_combout ), + .datad(\fifo_read_inst|cnt_read [8]), + .cin(gnd), + .combout(\fifo_read_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal2~2 .lut_mask = 16'h0020; +defparam \fifo_read_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N0 +cycloneive_lcell_comb \fifo_read_inst|rd_flag~0 ( +// Equation(s): +// \fifo_read_inst|rd_flag~0_combout = (!\fifo_read_inst|Equal2~2_combout & ((\fifo_read_inst|rd_flag~q ) # ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1] & +// \fifo_read_inst|Equal1~2_combout )))) + + .dataa(\fifo_read_inst|Equal2~2_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datac(\fifo_read_inst|rd_flag~q ), + .datad(\fifo_read_inst|Equal1~2_combout ), + .cin(gnd), + .combout(\fifo_read_inst|rd_flag~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|rd_flag~0 .lut_mask = 16'h5450; +defparam \fifo_read_inst|rd_flag~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N22 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~1 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~1_combout = (\uart_rx_inst|Add1~0_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_flag~q )) # (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(\uart_rx_inst|bit_cnt [3]), + .datab(\uart_rx_inst|Add1~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~1 .lut_mask = 16'h4CCC; +defparam \uart_rx_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N7 +dffeas \uart_rx_inst|work_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|work_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_rx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y24_N7 +dffeas \uart_rx_inst|start_nedge ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|start_nedge~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|start_nedge .is_wysiwyg = "true"; +defparam \uart_rx_inst|start_nedge .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N6 +cycloneive_lcell_comb \uart_rx_inst|work_en~0 ( +// Equation(s): +// \uart_rx_inst|work_en~0_combout = (\uart_rx_inst|start_nedge~q ) # ((\uart_rx_inst|work_en~q & !\uart_rx_inst|always4~1_combout )) + + .dataa(gnd), + .datab(\uart_rx_inst|start_nedge~q ), + .datac(\uart_rx_inst|work_en~q ), + .datad(\uart_rx_inst|always4~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|work_en~0 .lut_mask = 16'hCCFC; +defparam \uart_rx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N6 +cycloneive_lcell_comb \uart_rx_inst|always3~0 ( +// Equation(s): +// \uart_rx_inst|always3~0_combout = (\uart_rx_inst|rx_reg2~q & !\uart_rx_inst|rx_reg3~q ) + + .dataa(gnd), + .datab(\uart_rx_inst|rx_reg2~q ), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg3~q ), + .cin(gnd), + .combout(\uart_rx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always3~0 .lut_mask = 16'h00CC; +defparam \uart_rx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N12 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[0]~5 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[0]~5_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [0] $ (((\uart_tx_inst|bit_flag~q & \uart_tx_inst|work_en~q ))))) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(\uart_tx_inst|always0~1_combout ), + .datac(\uart_tx_inst|bit_cnt [0]), + .datad(\uart_tx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[0]~5 .lut_mask = 16'h1230; +defparam \uart_tx_inst|bit_cnt[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y9_N16 +cycloneive_io_obuf \tx~output ( + .i(!\uart_tx_inst|tx~q ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(tx), + .obar()); +// synopsys translate_off +defparam \tx~output .bus_hold = "false"; +defparam \tx~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y29_N30 +cycloneive_io_obuf \sdram_clk~output ( + .i(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_clk), + .obar()); +// synopsys translate_off +defparam \sdram_clk~output .bus_hold = "false"; +defparam \sdram_clk~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y13_N23 +cycloneive_io_obuf \sdram_cke~output ( + .i(vcc), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_cke), + .obar()); +// synopsys translate_off +defparam \sdram_cke~output .bus_hold = "false"; +defparam \sdram_cke~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N9 +cycloneive_io_obuf \sdram_cs_n~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_cs_n), + .obar()); +// synopsys translate_off +defparam \sdram_cs_n~output .bus_hold = "false"; +defparam \sdram_cs_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y29_N16 +cycloneive_io_obuf \sdram_cas_n~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_cas_n), + .obar()); +// synopsys translate_off +defparam \sdram_cas_n~output .bus_hold = "false"; +defparam \sdram_cas_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N16 +cycloneive_io_obuf \sdram_ras_n~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_ras_n), + .obar()); +// synopsys translate_off +defparam \sdram_ras_n~output .bus_hold = "false"; +defparam \sdram_ras_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X7_Y29_N9 +cycloneive_io_obuf \sdram_we_n~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_we_n), + .obar()); +// synopsys translate_off +defparam \sdram_we_n~output .bus_hold = "false"; +defparam \sdram_we_n~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N16 +cycloneive_io_obuf \sdram_ba[0]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_ba[0]), + .obar()); +// synopsys translate_off +defparam \sdram_ba[0]~output .bus_hold = "false"; +defparam \sdram_ba[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X1_Y29_N2 +cycloneive_io_obuf \sdram_ba[1]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_ba[1]), + .obar()); +// synopsys translate_off +defparam \sdram_ba[1]~output .bus_hold = "false"; +defparam \sdram_ba[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N9 +cycloneive_io_obuf \sdram_addr[0]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[0]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[0]~output .bus_hold = "false"; +defparam \sdram_addr[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y27_N16 +cycloneive_io_obuf \sdram_addr[1]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[1]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[1]~output .bus_hold = "false"; +defparam \sdram_addr[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y27_N9 +cycloneive_io_obuf \sdram_addr[2]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[2]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[2]~output .bus_hold = "false"; +defparam \sdram_addr[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y26_N23 +cycloneive_io_obuf \sdram_addr[3]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[3]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[3]~output .bus_hold = "false"; +defparam \sdram_addr[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y26_N16 +cycloneive_io_obuf \sdram_addr[4]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[4]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[4]~output .bus_hold = "false"; +defparam \sdram_addr[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y24_N16 +cycloneive_io_obuf \sdram_addr[5]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[5]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[5]~output .bus_hold = "false"; +defparam \sdram_addr[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y23_N2 +cycloneive_io_obuf \sdram_addr[6]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[6]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[6]~output .bus_hold = "false"; +defparam \sdram_addr[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y24_N23 +cycloneive_io_obuf \sdram_addr[7]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[7]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[7]~output .bus_hold = "false"; +defparam \sdram_addr[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N16 +cycloneive_io_obuf \sdram_addr[8]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[8]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[8]~output .bus_hold = "false"; +defparam \sdram_addr[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N16 +cycloneive_io_obuf \sdram_addr[9]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[9]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[9]~output .bus_hold = "false"; +defparam \sdram_addr[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N2 +cycloneive_io_obuf \sdram_addr[10]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[10]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[10]~output .bus_hold = "false"; +defparam \sdram_addr[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y12_N23 +cycloneive_io_obuf \sdram_addr[11]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[11]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[11]~output .bus_hold = "false"; +defparam \sdram_addr[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y13_N16 +cycloneive_io_obuf \sdram_addr[12]~output ( + .i(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_addr[12]), + .obar()); +// synopsys translate_off +defparam \sdram_addr[12]~output .bus_hold = "false"; +defparam \sdram_addr[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X5_Y29_N2 +cycloneive_io_obuf \sdram_dqm[0]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dqm[0]), + .obar()); +// synopsys translate_off +defparam \sdram_dqm[0]~output .bus_hold = "false"; +defparam \sdram_dqm[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y20_N2 +cycloneive_io_obuf \sdram_dqm[1]~output ( + .i(gnd), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dqm[1]), + .obar()); +// synopsys translate_off +defparam \sdram_dqm[1]~output .bus_hold = "false"; +defparam \sdram_dqm[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N9 +cycloneive_io_obuf \sdram_dq[0]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [0]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[0]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[0]~output .bus_hold = "false"; +defparam \sdram_dq[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N2 +cycloneive_io_obuf \sdram_dq[1]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [1]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[1]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[1]~output .bus_hold = "false"; +defparam \sdram_dq[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y29_N2 +cycloneive_io_obuf \sdram_dq[2]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [2]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[2]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[2]~output .bus_hold = "false"; +defparam \sdram_dq[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y29_N30 +cycloneive_io_obuf \sdram_dq[3]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [3]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[3]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[3]~output .bus_hold = "false"; +defparam \sdram_dq[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X14_Y29_N23 +cycloneive_io_obuf \sdram_dq[4]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [4]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[4]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[4]~output .bus_hold = "false"; +defparam \sdram_dq[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X9_Y29_N9 +cycloneive_io_obuf \sdram_dq[5]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [5]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[5]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[5]~output .bus_hold = "false"; +defparam \sdram_dq[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N16 +cycloneive_io_obuf \sdram_dq[6]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [6]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[6]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[6]~output .bus_hold = "false"; +defparam \sdram_dq[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X11_Y29_N23 +cycloneive_io_obuf \sdram_dq[7]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [7]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[7]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[7]~output .bus_hold = "false"; +defparam \sdram_dq[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y20_N9 +cycloneive_io_obuf \sdram_dq[8]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [8]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[8]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[8]~output .bus_hold = "false"; +defparam \sdram_dq[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X3_Y29_N30 +cycloneive_io_obuf \sdram_dq[9]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [9]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[9]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[9]~output .bus_hold = "false"; +defparam \sdram_dq[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y25_N2 +cycloneive_io_obuf \sdram_dq[10]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [10]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[10]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[10]~output .bus_hold = "false"; +defparam \sdram_dq[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y26_N9 +cycloneive_io_obuf \sdram_dq[11]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [11]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[11]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[11]~output .bus_hold = "false"; +defparam \sdram_dq[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y23_N9 +cycloneive_io_obuf \sdram_dq[12]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [12]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[12]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[12]~output .bus_hold = "false"; +defparam \sdram_dq[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N9 +cycloneive_io_obuf \sdram_dq[13]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [13]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[13]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[13]~output .bus_hold = "false"; +defparam \sdram_dq[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N23 +cycloneive_io_obuf \sdram_dq[14]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [14]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[14]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[14]~output .bus_hold = "false"; +defparam \sdram_dq[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y21_N2 +cycloneive_io_obuf \sdram_dq[15]~output ( + .i(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|q_b [15]), + .oe(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(sdram_dq[15]), + .obar()); +// synopsys translate_off +defparam \sdram_dq[15]~output .bus_hold = "false"; +defparam \sdram_dq[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N2 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[0]~13_combout = (\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] $ (VCC))) # (!\uart_rx_inst|work_en~q & (\uart_rx_inst|baud_cnt [0] & VCC)) +// \uart_rx_inst|baud_cnt[0]~14 = CARRY((\uart_rx_inst|work_en~q & \uart_rx_inst|baud_cnt [0])) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_rx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_rx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_rx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 6; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 4; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 4; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 3; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "c1"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "c2"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "-833"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 4; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 3334; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N24 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X27_Y26_N25 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y26_N26 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked )) # (!\sys_rst_n~input_o ) + + .dataa(\sys_rst_n~input_o ), + .datab(gnd), + .datac(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datad(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h5FFF; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G17 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N6 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[2]~17_combout = (\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt[1]~16 & VCC)) +// \uart_rx_inst|baud_cnt[2]~18 = CARRY((\uart_rx_inst|baud_cnt [2] & !\uart_rx_inst|baud_cnt[1]~16 )) + + .dataa(\uart_rx_inst|baud_cnt [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[1]~16 ), + .combout(\uart_rx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_rx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2]~17 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N8 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[3]~19 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[3]~19_combout = (\uart_rx_inst|baud_cnt [3] & (!\uart_rx_inst|baud_cnt[2]~18 )) # (!\uart_rx_inst|baud_cnt [3] & ((\uart_rx_inst|baud_cnt[2]~18 ) # (GND))) +// \uart_rx_inst|baud_cnt[3]~20 = CARRY((!\uart_rx_inst|baud_cnt[2]~18 ) # (!\uart_rx_inst|baud_cnt [3])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [3]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[2]~18 ), + .combout(\uart_rx_inst|baud_cnt[3]~19_combout ), + .cout(\uart_rx_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3]~19 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N9 +dffeas \uart_rx_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N12 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[5]~23_combout = (\uart_rx_inst|baud_cnt [5] & (!\uart_rx_inst|baud_cnt[4]~22 )) # (!\uart_rx_inst|baud_cnt [5] & ((\uart_rx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_rx_inst|baud_cnt[5]~24 = CARRY((!\uart_rx_inst|baud_cnt[4]~22 ) # (!\uart_rx_inst|baud_cnt [5])) + + .dataa(\uart_rx_inst|baud_cnt [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[4]~22 ), + .combout(\uart_rx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_rx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5]~23 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N13 +dffeas \uart_rx_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N30 +cycloneive_lcell_comb \uart_rx_inst|Equal1~1 ( +// Equation(s): +// \uart_rx_inst|Equal1~1_combout = (\uart_rx_inst|baud_cnt [4] & (\uart_rx_inst|baud_cnt [2] & (!\uart_rx_inst|baud_cnt [3] & !\uart_rx_inst|baud_cnt [5]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [2]), + .datac(\uart_rx_inst|baud_cnt [3]), + .datad(\uart_rx_inst|baud_cnt [5]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~1 .lut_mask = 16'h0008; +defparam \uart_rx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N14 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[6]~25_combout = (\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_rx_inst|baud_cnt [6] & (!\uart_rx_inst|baud_cnt[5]~24 & VCC)) +// \uart_rx_inst|baud_cnt[6]~26 = CARRY((\uart_rx_inst|baud_cnt [6] & !\uart_rx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[5]~24 ), + .combout(\uart_rx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_rx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N15 +dffeas \uart_rx_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N16 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[7]~27_combout = (\uart_rx_inst|baud_cnt [7] & (!\uart_rx_inst|baud_cnt[6]~26 )) # (!\uart_rx_inst|baud_cnt [7] & ((\uart_rx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_rx_inst|baud_cnt[7]~28 = CARRY((!\uart_rx_inst|baud_cnt[6]~26 ) # (!\uart_rx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[6]~26 ), + .combout(\uart_rx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_rx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N17 +dffeas \uart_rx_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N18 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[8]~29_combout = (\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_rx_inst|baud_cnt [8] & (!\uart_rx_inst|baud_cnt[7]~28 & VCC)) +// \uart_rx_inst|baud_cnt[8]~30 = CARRY((\uart_rx_inst|baud_cnt [8] & !\uart_rx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[7]~28 ), + .combout(\uart_rx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_rx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_rx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N19 +dffeas \uart_rx_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N0 +cycloneive_lcell_comb \uart_rx_inst|Equal1~0 ( +// Equation(s): +// \uart_rx_inst|Equal1~0_combout = (\uart_rx_inst|baud_cnt [0] & (!\uart_rx_inst|baud_cnt [8] & (\uart_rx_inst|baud_cnt [1] & !\uart_rx_inst|baud_cnt [7]))) + + .dataa(\uart_rx_inst|baud_cnt [0]), + .datab(\uart_rx_inst|baud_cnt [8]), + .datac(\uart_rx_inst|baud_cnt [1]), + .datad(\uart_rx_inst|baud_cnt [7]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~0 .lut_mask = 16'h0020; +defparam \uart_rx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N20 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[9]~31_combout = (\uart_rx_inst|baud_cnt [9] & (!\uart_rx_inst|baud_cnt[8]~30 )) # (!\uart_rx_inst|baud_cnt [9] & ((\uart_rx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_rx_inst|baud_cnt[9]~32 = CARRY((!\uart_rx_inst|baud_cnt[8]~30 ) # (!\uart_rx_inst|baud_cnt [9])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [9]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[8]~30 ), + .combout(\uart_rx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_rx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9]~31 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N21 +dffeas \uart_rx_inst|baud_cnt[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N22 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[10]~33_combout = (\uart_rx_inst|baud_cnt [10] & (\uart_rx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_rx_inst|baud_cnt [10] & (!\uart_rx_inst|baud_cnt[9]~32 & VCC)) +// \uart_rx_inst|baud_cnt[10]~34 = CARRY((\uart_rx_inst|baud_cnt [10] & !\uart_rx_inst|baud_cnt[9]~32 )) + + .dataa(\uart_rx_inst|baud_cnt [10]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[9]~32 ), + .combout(\uart_rx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_rx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10]~33 .lut_mask = 16'hA50A; +defparam \uart_rx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N24 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[11]~35_combout = (\uart_rx_inst|baud_cnt [11] & (!\uart_rx_inst|baud_cnt[10]~34 )) # (!\uart_rx_inst|baud_cnt [11] & ((\uart_rx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_rx_inst|baud_cnt[11]~36 = CARRY((!\uart_rx_inst|baud_cnt[10]~34 ) # (!\uart_rx_inst|baud_cnt [11])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[10]~34 ), + .combout(\uart_rx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_rx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11]~35 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N25 +dffeas \uart_rx_inst|baud_cnt[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N8 +cycloneive_lcell_comb \uart_rx_inst|Equal1~2 ( +// Equation(s): +// \uart_rx_inst|Equal1~2_combout = (!\uart_rx_inst|baud_cnt [9] & \uart_rx_inst|baud_cnt [6]) + + .dataa(gnd), + .datab(gnd), + .datac(\uart_rx_inst|baud_cnt [9]), + .datad(\uart_rx_inst|baud_cnt [6]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~2 .lut_mask = 16'h0F00; +defparam \uart_rx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N23 +dffeas \uart_rx_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N2 +cycloneive_lcell_comb \uart_rx_inst|Equal1~3 ( +// Equation(s): +// \uart_rx_inst|Equal1~3_combout = (\uart_rx_inst|baud_cnt [12] & (!\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|Equal1~2_combout & \uart_rx_inst|baud_cnt [10]))) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|Equal1~2_combout ), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal1~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal1~3 .lut_mask = 16'h2000; +defparam \uart_rx_inst|Equal1~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N12 +cycloneive_lcell_comb \uart_rx_inst|always5~0 ( +// Equation(s): +// \uart_rx_inst|always5~0_combout = ((\uart_rx_inst|Equal1~1_combout & (\uart_rx_inst|Equal1~0_combout & \uart_rx_inst|Equal1~3_combout ))) # (!\uart_rx_inst|work_en~q ) + + .dataa(\uart_rx_inst|work_en~q ), + .datab(\uart_rx_inst|Equal1~1_combout ), + .datac(\uart_rx_inst|Equal1~0_combout ), + .datad(\uart_rx_inst|Equal1~3_combout ), + .cin(gnd), + .combout(\uart_rx_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always5~0 .lut_mask = 16'hD555; +defparam \uart_rx_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y25_N3 +dffeas \uart_rx_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N4 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[1]~15_combout = (\uart_rx_inst|baud_cnt [1] & (!\uart_rx_inst|baud_cnt[0]~14 )) # (!\uart_rx_inst|baud_cnt [1] & ((\uart_rx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_rx_inst|baud_cnt[1]~16 = CARRY((!\uart_rx_inst|baud_cnt[0]~14 ) # (!\uart_rx_inst|baud_cnt [1])) + + .dataa(gnd), + .datab(\uart_rx_inst|baud_cnt [1]), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|baud_cnt[0]~14 ), + .combout(\uart_rx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_rx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1]~15 .lut_mask = 16'h3C3F; +defparam \uart_rx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N5 +dffeas \uart_rx_inst|baud_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y25_N7 +dffeas \uart_rx_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N28 +cycloneive_lcell_comb \uart_rx_inst|Equal2~0 ( +// Equation(s): +// \uart_rx_inst|Equal2~0_combout = (!\uart_rx_inst|baud_cnt [4] & (!\uart_rx_inst|baud_cnt [2] & (\uart_rx_inst|baud_cnt [3] & \uart_rx_inst|baud_cnt [5]))) + + .dataa(\uart_rx_inst|baud_cnt [4]), + .datab(\uart_rx_inst|baud_cnt [2]), + .datac(\uart_rx_inst|baud_cnt [3]), + .datad(\uart_rx_inst|baud_cnt [5]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~0 .lut_mask = 16'h1000; +defparam \uart_rx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y25_N26 +cycloneive_lcell_comb \uart_rx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_rx_inst|baud_cnt[12]~37_combout = \uart_rx_inst|baud_cnt [12] $ (!\uart_rx_inst|baud_cnt[11]~36 ) + + .dataa(\uart_rx_inst|baud_cnt [12]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\uart_rx_inst|baud_cnt[11]~36 ), + .combout(\uart_rx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12]~37 .lut_mask = 16'hA5A5; +defparam \uart_rx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X15_Y25_N27 +dffeas \uart_rx_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\uart_rx_inst|always5~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_rx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N20 +cycloneive_lcell_comb \uart_rx_inst|Equal2~1 ( +// Equation(s): +// \uart_rx_inst|Equal2~1_combout = (!\uart_rx_inst|baud_cnt [6] & (\uart_rx_inst|baud_cnt [11] & (\uart_rx_inst|baud_cnt [9] & !\uart_rx_inst|baud_cnt [10]))) + + .dataa(\uart_rx_inst|baud_cnt [6]), + .datab(\uart_rx_inst|baud_cnt [11]), + .datac(\uart_rx_inst|baud_cnt [9]), + .datad(\uart_rx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~1 .lut_mask = 16'h0040; +defparam \uart_rx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N4 +cycloneive_lcell_comb \uart_rx_inst|Equal2~2 ( +// Equation(s): +// \uart_rx_inst|Equal2~2_combout = (\uart_rx_inst|Equal1~0_combout & (\uart_rx_inst|Equal2~0_combout & (!\uart_rx_inst|baud_cnt [12] & \uart_rx_inst|Equal2~1_combout ))) + + .dataa(\uart_rx_inst|Equal1~0_combout ), + .datab(\uart_rx_inst|Equal2~0_combout ), + .datac(\uart_rx_inst|baud_cnt [12]), + .datad(\uart_rx_inst|Equal2~1_combout ), + .cin(gnd), + .combout(\uart_rx_inst|Equal2~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|Equal2~2 .lut_mask = 16'h0800; +defparam \uart_rx_inst|Equal2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N5 +dffeas \uart_rx_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Equal2~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N26 +cycloneive_lcell_comb \uart_rx_inst|Add1~2 ( +// Equation(s): +// \uart_rx_inst|Add1~2_combout = (\uart_rx_inst|bit_cnt [1] & (!\uart_rx_inst|Add1~1 )) # (!\uart_rx_inst|bit_cnt [1] & ((\uart_rx_inst|Add1~1 ) # (GND))) +// \uart_rx_inst|Add1~3 = CARRY((!\uart_rx_inst|Add1~1 ) # (!\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_rx_inst|Add1~1 ), + .combout(\uart_rx_inst|Add1~2_combout ), + .cout(\uart_rx_inst|Add1~3 )); +// synopsys translate_off +defparam \uart_rx_inst|Add1~2 .lut_mask = 16'h5A5F; +defparam \uart_rx_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X16_Y25_N29 +dffeas \uart_rx_inst|bit_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y25_N27 +dffeas \uart_rx_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|Add1~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N0 +cycloneive_lcell_comb \uart_rx_inst|always4~0 ( +// Equation(s): +// \uart_rx_inst|always4~0_combout = (!\uart_rx_inst|bit_cnt [0] & (!\uart_rx_inst|bit_cnt [2] & !\uart_rx_inst|bit_cnt [1])) + + .dataa(\uart_rx_inst|bit_cnt [0]), + .datab(\uart_rx_inst|bit_cnt [2]), + .datac(\uart_rx_inst|bit_cnt [1]), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always4~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~0 .lut_mask = 16'h0101; +defparam \uart_rx_inst|always4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N16 +cycloneive_lcell_comb \uart_rx_inst|always4~1 ( +// Equation(s): +// \uart_rx_inst|always4~1_combout = (\uart_rx_inst|bit_cnt [3] & (\uart_rx_inst|always4~0_combout & \uart_rx_inst|bit_flag~q )) + + .dataa(\uart_rx_inst|bit_cnt [3]), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_rx_inst|always4~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always4~1 .lut_mask = 16'h8080; +defparam \uart_rx_inst|always4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N17 +dffeas \uart_rx_inst|rx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|always4~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_flag .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N1 +dffeas \uart_rx_inst|po_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_flag~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_flag .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h5A5A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hF0B4; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0800; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'h0100; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .lut_mask = 16'hC3F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h3CC3; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y22_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h0200; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0004; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hB4F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~21 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22 .lut_mask = 16'hA50A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [5]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [6]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4 .lut_mask = 16'h0001; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6 .lut_mask = 16'h0100; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8 .lut_mask = 16'h1000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y21_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [9]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5 .lut_mask = 16'h9696; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y22_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y22_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0040; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y20_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hE1F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .lut_mask = 16'h0990; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'h2000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8 .lut_mask = 16'h000F; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X16_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y21_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'h8008; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7] $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'h8008; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'h0F33; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ) # (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q )))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ) # +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hEEE0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X16_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4~combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y20_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X15_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y21_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [0]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [0])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [0]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1_cout )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1 .lut_mask = 16'h00BB; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~3 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [3]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~5 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~7 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & +// ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5] & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~9 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7~combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y20_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout = ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~11 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X17_Y20_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )))) +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 = CARRY((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7] & !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7] & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7]) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~13 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~15 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|LessThan2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ) # ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ) # +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ) # (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~0 .lut_mask = 16'hFFFE; +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|LessThan2~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ) # ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout & +// ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ) # (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~1 .lut_mask = 16'hFFC8; +defparam \sdram_top_inst|fifo_ctrl_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .lut_mask = 16'h0010; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 $ (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [9])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a [9]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a [9]), + .cin(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~17 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18 .lut_mask = 16'h5AA5; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X15_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & ((\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ) # ((\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ) # +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0 .lut_mask = 16'hAAA8; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X15_Y20_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .lut_mask = 16'h5A5A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .lut_mask = 16'hF0B4; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hD2F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .lut_mask = 16'h0040; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .lut_mask = 16'hD2D2; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y26_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1] $ (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h3CC3; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h0020; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .lut_mask = 16'hD2F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10 .lut_mask = 16'h33CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & (\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4 .lut_mask = 16'h0500; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~19 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~21 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~23 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~25 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9] $ (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~27 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28 .lut_mask = 16'h5A5A; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X23_Y23_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3 .lut_mask = 16'h000F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5 .lut_mask = 16'h2000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0 .lut_mask = 16'hCCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [5] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [4]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [7]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [6]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2 .lut_mask = 16'h0001; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ) # ((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0 .lut_mask = 16'hFF30; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1 .lut_mask = 16'hC0C0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0 .lut_mask = 16'h00F8; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16 .lut_mask = 16'h0088; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0 .lut_mask = 16'hCCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1 .lut_mask = 16'hCC00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2 .lut_mask = 16'hEEFF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [0] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0 .lut_mask = 16'h00FE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3 .lut_mask = 16'hFFEC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y23_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y23_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y23_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk +// [1]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]) # (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1 .lut_mask = 16'h5776; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .lut_mask = 16'hF0D2; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .lut_mask = 16'h78F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .lut_mask = 16'h0100; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .lut_mask = 16'h0010; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .lut_mask = 16'hA5F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .lut_mask = 16'h9669; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2] $ (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .lut_mask = 16'h3CC3; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .lut_mask = 16'h0008; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .lut_mask = 16'h0200; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .lut_mask = 16'hB4F0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [9]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .lut_mask = 16'hFCFF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1 .lut_mask = 16'hF05A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'h8241; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout +// )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .lut_mask = 16'hAC0C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout )))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'h59FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y25_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .lut_mask = 16'h9009; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [5]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [4]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout = !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [0]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .lut_mask = 16'h0021; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y25_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] $ +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [2]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .lut_mask = 16'h8421; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout & +// (((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout +// )) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .lut_mask = 16'h1333; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y24_N25 +dffeas \fifo_read_inst|read_en_dly ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\fifo_read_inst|read_en~q ), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_en_dly~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_en_dly .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_en_dly .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout = (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q & \fifo_read_inst|read_en_dly~q ) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datab(gnd), + .datac(\fifo_read_inst|read_en_dly~q ), + .datad(gnd), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq .lut_mask = 16'h5050; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y24_N6 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] $ (((VCC) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT = CARRY(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0] $ +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0 .lut_mask = 16'h5599; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y24_N7 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N8 +cycloneive_lcell_comb \fifo_read_inst|Add2~0 ( +// Equation(s): +// \fifo_read_inst|Add2~0_combout = (\fifo_read_inst|bit_flag~q & (\fifo_read_inst|bit_cnt [0] $ (VCC))) # (!\fifo_read_inst|bit_flag~q & (\fifo_read_inst|bit_cnt [0] & VCC)) +// \fifo_read_inst|Add2~1 = CARRY((\fifo_read_inst|bit_flag~q & \fifo_read_inst|bit_cnt [0])) + + .dataa(\fifo_read_inst|bit_flag~q ), + .datab(\fifo_read_inst|bit_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|Add2~0_combout ), + .cout(\fifo_read_inst|Add2~1 )); +// synopsys translate_off +defparam \fifo_read_inst|Add2~0 .lut_mask = 16'h6688; +defparam \fifo_read_inst|Add2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N9 +dffeas \fifo_read_inst|bit_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|Add2~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N10 +cycloneive_lcell_comb \fifo_read_inst|Add2~2 ( +// Equation(s): +// \fifo_read_inst|Add2~2_combout = (\fifo_read_inst|bit_cnt [1] & (!\fifo_read_inst|Add2~1 )) # (!\fifo_read_inst|bit_cnt [1] & ((\fifo_read_inst|Add2~1 ) # (GND))) +// \fifo_read_inst|Add2~3 = CARRY((!\fifo_read_inst|Add2~1 ) # (!\fifo_read_inst|bit_cnt [1])) + + .dataa(\fifo_read_inst|bit_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|Add2~1 ), + .combout(\fifo_read_inst|Add2~2_combout ), + .cout(\fifo_read_inst|Add2~3 )); +// synopsys translate_off +defparam \fifo_read_inst|Add2~2 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|Add2~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N14 +cycloneive_lcell_comb \fifo_read_inst|Add2~6 ( +// Equation(s): +// \fifo_read_inst|Add2~6_combout = \fifo_read_inst|bit_cnt [3] $ (\fifo_read_inst|Add2~5 ) + + .dataa(gnd), + .datab(\fifo_read_inst|bit_cnt [3]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|Add2~5 ), + .combout(\fifo_read_inst|Add2~6_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Add2~6 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|Add2~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N4 +cycloneive_lcell_comb \fifo_read_inst|bit_cnt~0 ( +// Equation(s): +// \fifo_read_inst|bit_cnt~0_combout = (\fifo_read_inst|Add2~6_combout & ((!\fifo_read_inst|always5~0_combout ) # (!\fifo_read_inst|bit_cnt [0]))) + + .dataa(gnd), + .datab(\fifo_read_inst|bit_cnt [0]), + .datac(\fifo_read_inst|Add2~6_combout ), + .datad(\fifo_read_inst|always5~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt~0 .lut_mask = 16'h30F0; +defparam \fifo_read_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N5 +dffeas \fifo_read_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N4 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[0]~13 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[0]~13_combout = (\fifo_read_inst|rd_flag~q & (\fifo_read_inst|baud_cnt [0] $ (VCC))) # (!\fifo_read_inst|rd_flag~q & (\fifo_read_inst|baud_cnt [0] & VCC)) +// \fifo_read_inst|baud_cnt[0]~14 = CARRY((\fifo_read_inst|rd_flag~q & \fifo_read_inst|baud_cnt [0])) + + .dataa(\fifo_read_inst|rd_flag~q ), + .datab(\fifo_read_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|baud_cnt[0]~13_combout ), + .cout(\fifo_read_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \fifo_read_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N14 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[5]~23 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[5]~23_combout = (\fifo_read_inst|baud_cnt [5] & (!\fifo_read_inst|baud_cnt[4]~22 )) # (!\fifo_read_inst|baud_cnt [5] & ((\fifo_read_inst|baud_cnt[4]~22 ) # (GND))) +// \fifo_read_inst|baud_cnt[5]~24 = CARRY((!\fifo_read_inst|baud_cnt[4]~22 ) # (!\fifo_read_inst|baud_cnt [5])) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[4]~22 ), + .combout(\fifo_read_inst|baud_cnt[5]~23_combout ), + .cout(\fifo_read_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N16 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[6]~25 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[6]~25_combout = (\fifo_read_inst|baud_cnt [6] & (\fifo_read_inst|baud_cnt[5]~24 $ (GND))) # (!\fifo_read_inst|baud_cnt [6] & (!\fifo_read_inst|baud_cnt[5]~24 & VCC)) +// \fifo_read_inst|baud_cnt[6]~26 = CARRY((\fifo_read_inst|baud_cnt [6] & !\fifo_read_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[5]~24 ), + .combout(\fifo_read_inst|baud_cnt[6]~25_combout ), + .cout(\fifo_read_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N17 +dffeas \fifo_read_inst|baud_cnt[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N18 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[7]~27 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[7]~27_combout = (\fifo_read_inst|baud_cnt [7] & (!\fifo_read_inst|baud_cnt[6]~26 )) # (!\fifo_read_inst|baud_cnt [7] & ((\fifo_read_inst|baud_cnt[6]~26 ) # (GND))) +// \fifo_read_inst|baud_cnt[7]~28 = CARRY((!\fifo_read_inst|baud_cnt[6]~26 ) # (!\fifo_read_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[6]~26 ), + .combout(\fifo_read_inst|baud_cnt[7]~27_combout ), + .cout(\fifo_read_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N19 +dffeas \fifo_read_inst|baud_cnt[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N20 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[8]~29 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[8]~29_combout = (\fifo_read_inst|baud_cnt [8] & (\fifo_read_inst|baud_cnt[7]~28 $ (GND))) # (!\fifo_read_inst|baud_cnt [8] & (!\fifo_read_inst|baud_cnt[7]~28 & VCC)) +// \fifo_read_inst|baud_cnt[8]~30 = CARRY((\fifo_read_inst|baud_cnt [8] & !\fifo_read_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[7]~28 ), + .combout(\fifo_read_inst|baud_cnt[8]~29_combout ), + .cout(\fifo_read_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N21 +dffeas \fifo_read_inst|baud_cnt[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N0 +cycloneive_lcell_comb \fifo_read_inst|Equal4~0 ( +// Equation(s): +// \fifo_read_inst|Equal4~0_combout = (\fifo_read_inst|baud_cnt [1] & (!\fifo_read_inst|baud_cnt [8] & (\fifo_read_inst|baud_cnt [0] & !\fifo_read_inst|baud_cnt [7]))) + + .dataa(\fifo_read_inst|baud_cnt [1]), + .datab(\fifo_read_inst|baud_cnt [8]), + .datac(\fifo_read_inst|baud_cnt [0]), + .datad(\fifo_read_inst|baud_cnt [7]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~0 .lut_mask = 16'h0020; +defparam \fifo_read_inst|Equal4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N10 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[3]~19 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[3]~19_combout = (\fifo_read_inst|baud_cnt [3] & (!\fifo_read_inst|baud_cnt[2]~18 )) # (!\fifo_read_inst|baud_cnt [3] & ((\fifo_read_inst|baud_cnt[2]~18 ) # (GND))) +// \fifo_read_inst|baud_cnt[3]~20 = CARRY((!\fifo_read_inst|baud_cnt[2]~18 ) # (!\fifo_read_inst|baud_cnt [3])) + + .dataa(\fifo_read_inst|baud_cnt [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[2]~18 ), + .combout(\fifo_read_inst|baud_cnt[3]~19_combout ), + .cout(\fifo_read_inst|baud_cnt[3]~20 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[3]~19 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|baud_cnt[3]~19 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N11 +dffeas \fifo_read_inst|baud_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[3]~19_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N22 +cycloneive_lcell_comb \fifo_read_inst|Equal4~1 ( +// Equation(s): +// \fifo_read_inst|Equal4~1_combout = (\fifo_read_inst|baud_cnt [4] & (!\fifo_read_inst|baud_cnt [5] & (!\fifo_read_inst|baud_cnt [3] & \fifo_read_inst|baud_cnt [2]))) + + .dataa(\fifo_read_inst|baud_cnt [4]), + .datab(\fifo_read_inst|baud_cnt [5]), + .datac(\fifo_read_inst|baud_cnt [3]), + .datad(\fifo_read_inst|baud_cnt [2]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~1 .lut_mask = 16'h0200; +defparam \fifo_read_inst|Equal4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N24 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[10]~33 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[10]~33_combout = (\fifo_read_inst|baud_cnt [10] & (\fifo_read_inst|baud_cnt[9]~32 $ (GND))) # (!\fifo_read_inst|baud_cnt [10] & (!\fifo_read_inst|baud_cnt[9]~32 & VCC)) +// \fifo_read_inst|baud_cnt[10]~34 = CARRY((\fifo_read_inst|baud_cnt [10] & !\fifo_read_inst|baud_cnt[9]~32 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[9]~32 ), + .combout(\fifo_read_inst|baud_cnt[10]~33_combout ), + .cout(\fifo_read_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N25 +dffeas \fifo_read_inst|baud_cnt[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N28 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[12]~37 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[12]~37_combout = \fifo_read_inst|baud_cnt[11]~36 $ (!\fifo_read_inst|baud_cnt [12]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\fifo_read_inst|baud_cnt [12]), + .cin(\fifo_read_inst|baud_cnt[11]~36 ), + .combout(\fifo_read_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; +defparam \fifo_read_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N29 +dffeas \fifo_read_inst|baud_cnt[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N16 +cycloneive_lcell_comb \fifo_read_inst|Equal4~3 ( +// Equation(s): +// \fifo_read_inst|Equal4~3_combout = (\fifo_read_inst|Equal4~2_combout & (\fifo_read_inst|Equal4~0_combout & (\fifo_read_inst|Equal4~1_combout & \fifo_read_inst|baud_cnt [12]))) + + .dataa(\fifo_read_inst|Equal4~2_combout ), + .datab(\fifo_read_inst|Equal4~0_combout ), + .datac(\fifo_read_inst|Equal4~1_combout ), + .datad(\fifo_read_inst|baud_cnt [12]), + .cin(gnd), + .combout(\fifo_read_inst|Equal4~3_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal4~3 .lut_mask = 16'h8000; +defparam \fifo_read_inst|Equal4~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X29_Y25_N5 +dffeas \fifo_read_inst|baud_cnt[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y25_N8 +cycloneive_lcell_comb \fifo_read_inst|baud_cnt[2]~17 ( +// Equation(s): +// \fifo_read_inst|baud_cnt[2]~17_combout = (\fifo_read_inst|baud_cnt [2] & (\fifo_read_inst|baud_cnt[1]~16 $ (GND))) # (!\fifo_read_inst|baud_cnt [2] & (!\fifo_read_inst|baud_cnt[1]~16 & VCC)) +// \fifo_read_inst|baud_cnt[2]~18 = CARRY((\fifo_read_inst|baud_cnt [2] & !\fifo_read_inst|baud_cnt[1]~16 )) + + .dataa(gnd), + .datab(\fifo_read_inst|baud_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|baud_cnt[1]~16 ), + .combout(\fifo_read_inst|baud_cnt[2]~17_combout ), + .cout(\fifo_read_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y25_N9 +dffeas \fifo_read_inst|baud_cnt[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y25_N15 +dffeas \fifo_read_inst|baud_cnt[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\fifo_read_inst|Equal4~3_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N28 +cycloneive_lcell_comb \fifo_read_inst|Equal5~0 ( +// Equation(s): +// \fifo_read_inst|Equal5~0_combout = (!\fifo_read_inst|baud_cnt [4] & (\fifo_read_inst|baud_cnt [5] & (\fifo_read_inst|baud_cnt [3] & !\fifo_read_inst|baud_cnt [2]))) + + .dataa(\fifo_read_inst|baud_cnt [4]), + .datab(\fifo_read_inst|baud_cnt [5]), + .datac(\fifo_read_inst|baud_cnt [3]), + .datad(\fifo_read_inst|baud_cnt [2]), + .cin(gnd), + .combout(\fifo_read_inst|Equal5~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal5~0 .lut_mask = 16'h0040; +defparam \fifo_read_inst|Equal5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N26 +cycloneive_lcell_comb \fifo_read_inst|Equal5~2 ( +// Equation(s): +// \fifo_read_inst|Equal5~2_combout = (\fifo_read_inst|Equal5~1_combout & (\fifo_read_inst|Equal5~0_combout & (\fifo_read_inst|Equal4~0_combout & !\fifo_read_inst|baud_cnt [12]))) + + .dataa(\fifo_read_inst|Equal5~1_combout ), + .datab(\fifo_read_inst|Equal5~0_combout ), + .datac(\fifo_read_inst|Equal4~0_combout ), + .datad(\fifo_read_inst|baud_cnt [12]), + .cin(gnd), + .combout(\fifo_read_inst|Equal5~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|Equal5~2 .lut_mask = 16'h0080; +defparam \fifo_read_inst|Equal5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N27 +dffeas \fifo_read_inst|bit_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|Equal5~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_flag .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N6 +cycloneive_lcell_comb \fifo_read_inst|bit_cnt~1 ( +// Equation(s): +// \fifo_read_inst|bit_cnt~1_combout = (\fifo_read_inst|Add2~2_combout & ((!\fifo_read_inst|bit_cnt [0]) # (!\fifo_read_inst|always5~0_combout ))) + + .dataa(gnd), + .datab(\fifo_read_inst|always5~0_combout ), + .datac(\fifo_read_inst|bit_cnt [0]), + .datad(\fifo_read_inst|Add2~2_combout ), + .cin(gnd), + .combout(\fifo_read_inst|bit_cnt~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt~1 .lut_mask = 16'h3F00; +defparam \fifo_read_inst|bit_cnt~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N7 +dffeas \fifo_read_inst|bit_cnt[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|bit_cnt~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N24 +cycloneive_lcell_comb \fifo_read_inst|always5~0 ( +// Equation(s): +// \fifo_read_inst|always5~0_combout = (!\fifo_read_inst|bit_cnt [2] & (\fifo_read_inst|bit_cnt [3] & (\fifo_read_inst|bit_flag~q & !\fifo_read_inst|bit_cnt [1]))) + + .dataa(\fifo_read_inst|bit_cnt [2]), + .datab(\fifo_read_inst|bit_cnt [3]), + .datac(\fifo_read_inst|bit_flag~q ), + .datad(\fifo_read_inst|bit_cnt [1]), + .cin(gnd), + .combout(\fifo_read_inst|always5~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|always5~0 .lut_mask = 16'h0040; +defparam \fifo_read_inst|always5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N0 +cycloneive_lcell_comb \fifo_read_inst|always5~1 ( +// Equation(s): +// \fifo_read_inst|always5~1_combout = (\fifo_read_inst|bit_cnt [0] & \fifo_read_inst|always5~0_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\fifo_read_inst|bit_cnt [0]), + .datad(\fifo_read_inst|always5~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|always5~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|always5~1 .lut_mask = 16'hF000; +defparam \fifo_read_inst|always5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N1 +dffeas \fifo_read_inst|rd_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|always5~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|rd_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|rd_en .is_wysiwyg = "true"; +defparam \fifo_read_inst|rd_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]) # +// (((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]) # (!\fifo_read_inst|rd_en~q )) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0])) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [3]), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [0]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .lut_mask = 16'hFBFF; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N6 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ) # (\fifo_read_inst|read_en_dly~q ) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datab(gnd), + .datac(\fifo_read_inst|read_en_dly~q ), + .datad(gnd), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .lut_mask = 16'hFAFA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ) # +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ) # (!\fifo_read_inst|Equal1~1_combout )))) + + .dataa(\fifo_read_inst|Equal1~1_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1_combout ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .lut_mask = 16'hFFD0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N26 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ) # +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q & !\fifo_read_inst|rd_en~q )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3_combout ), + .datab(gnd), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4 .lut_mask = 16'hAAFA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N27 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4_combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout = (\fifo_read_inst|read_en_dly~q & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q $ (((!\fifo_read_inst|rd_en~q ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ))))) # (!\fifo_read_inst|read_en_dly~q & (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & +// ((\fifo_read_inst|rd_en~q )))) + + .dataa(\fifo_read_inst|read_en_dly~q ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~q ), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .lut_mask = 16'hC60A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y24_N9 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2 .lut_mask = 16'hA55A; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y21_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[2] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X24_Y25_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [1]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [3]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [5]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N3 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] .x_on_violation = "off"; +// synopsys translate_on + +// Location: FF_X26_Y25_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [7]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [1]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [3]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N13 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y22_N23 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [0]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [0]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y22_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [1]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~1 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [2]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~3 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ) # (GND))))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 & VCC)) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [3]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [3]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~5 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6 .lut_mask = 16'h692B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N10 +cycloneive_lcell_comb \Equal2~1 ( +// Equation(s): +// \Equal2~1_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4_combout ), + .cin(gnd), + .combout(\Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~1 .lut_mask = 16'h0040; +defparam \Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9])) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [8]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[8] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout )) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [5]), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5 .lut_mask = 16'hC33C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[5] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X26_Y21_N17 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [4]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~7 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8 .lut_mask = 16'h964D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N22 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 & VCC)))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & +// ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 ) # (GND))) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )))) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5] & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5] & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5]) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [5]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~9 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10 .lut_mask = 16'h694D; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [6]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~11 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~13 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout = ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8] $ (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 )))) # (GND) +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 = CARRY((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8] & +// ((!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ) # (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8]))) # +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8] & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8] & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~15 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .cout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16 .lut_mask = 16'h962B; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N28 +cycloneive_lcell_comb \fifo_read_inst|read_en~0 ( +// Equation(s): +// \fifo_read_inst|read_en~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout & (\Equal2~1_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout & +// \Equal2~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .datab(\Equal2~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .datad(\Equal2~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_en~0 .lut_mask = 16'h0400; +defparam \fifo_read_inst|read_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N8 +cycloneive_lcell_comb \fifo_read_inst|read_en~1 ( +// Equation(s): +// \fifo_read_inst|read_en~1_combout = (\fifo_read_inst|read_en~0_combout ) # ((\fifo_read_inst|read_en~q & ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]) # +// (!\fifo_read_inst|Equal1~2_combout )))) + + .dataa(\fifo_read_inst|Equal1~2_combout ), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit [1]), + .datac(\fifo_read_inst|read_en~q ), + .datad(\fifo_read_inst|read_en~0_combout ), + .cin(gnd), + .combout(\fifo_read_inst|read_en~1_combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_en~1 .lut_mask = 16'hFFD0; +defparam \fifo_read_inst|read_en~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y24_N9 +dffeas \fifo_read_inst|read_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_en~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_en .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout = (\fifo_read_inst|read_en~q & ((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ) # +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .datad(\fifo_read_inst|read_en~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .lut_mask = 16'hFC00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout = (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h0800; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .lut_mask = 16'h5AF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N11 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & +// !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .lut_mask = 16'h0010; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout & \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .lut_mask = 16'h3CF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y25_N25 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y25_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder .lut_mask = 16'hFF00; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X26_Y25_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X27_Y23_N31 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g [6]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .power_up = "low"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] .x_on_violation = "off"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y23_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a [6]), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7~combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y23_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N2 +cycloneive_lcell_comb \Equal2~0 ( +// Equation(s): +// \Equal2~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8_combout ), + .cin(gnd), + .combout(\Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \Equal2~0 .lut_mask = 16'h0001; +defparam \Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9 .lut_mask = 16'h55AA; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y25_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [9] $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 $ (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [9])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a [9]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a [9]), + .cin(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~17 ), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18 .lut_mask = 16'h5AA5; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout = (\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout & (!\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout & !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|LessThan2~1_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2 .lut_mask = 16'h0002; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout = (!\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout & (\Equal2~0_combout & (!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout & +// \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|LessThan2~0_combout ), + .datab(\Equal2~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3 .lut_mask = 16'h0400; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout = (!\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q & (!\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0 .lut_mask = 16'h0100; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0 .lut_mask = 16'h5500; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q & !\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1 .lut_mask = 16'hFF08; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7 .lut_mask = 16'h0030; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0 .lut_mask = 16'hDCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ) # ((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0 .lut_mask = 16'hFF50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & (\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q & +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1 .lut_mask = 16'hF888; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ) # +// (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1_combout ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3 .lut_mask = 16'hFEFE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0 .lut_mask = 16'hC0C0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0 .lut_mask = 16'h00F8; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4 .lut_mask = 16'h0F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2 .lut_mask = 16'h0AA0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15 .lut_mask = 16'h00F0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ) # ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0 .lut_mask = 16'hFF50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]))) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1 .lut_mask = 16'h0330; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0 .lut_mask = 16'h0300; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout = ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1 .lut_mask = 16'hFFD5; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2 .lut_mask = 16'hFF88; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2] $ +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0 .lut_mask = 16'h1230; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0 .lut_mask = 16'h7F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1 .lut_mask = 16'hFCFC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2 .lut_mask = 16'h0007; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk +// [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ) # +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0 .lut_mask = 16'hB3A0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3 .lut_mask = 16'hF5F5; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref [1]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17 .lut_mask = 16'h2020; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0 .lut_mask = 16'hFFC0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3 .lut_mask = 16'h000F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]))) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2 .lut_mask = 16'h003C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1 .lut_mask = 16'h0C0C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0 .lut_mask = 16'hEAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0 .lut_mask = 16'hB800; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3 .lut_mask = 16'h0055; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4 .lut_mask = 16'h0004; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0 .lut_mask = 16'h2AAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~1 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~3 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~5 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~7 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~9 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [9] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~19 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us +// [11] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~21 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~23 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~25 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[12] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[12] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 $ (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~27 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28 .lut_mask = 16'hF00F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X29_Y20_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[14] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[14] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[14] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X29_Y20_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[11] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[11] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X29_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [13]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [14]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [11]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [12]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0 .lut_mask = 16'h0040; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [9]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [8]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [7]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1 .lut_mask = 16'h0020; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [6]), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2 .lut_mask = 16'h5000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [5]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [4]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0 .lut_mask = 16'h2000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2 .lut_mask = 16'hFEFF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] $ +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4 .lut_mask = 16'h1230; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0 .lut_mask = 16'hCC00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0 .lut_mask = 16'hF2F0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16 .lut_mask = 16'h4040; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0] $ (VCC) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 = CARRY(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0 .lut_mask = 16'h55AA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref +// [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~1 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~3 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref +// [3] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~5 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~7 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1 .lut_mask = 16'hF0FF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref +// [5] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~9 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7])) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8 .lut_mask = 16'hCC00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout = (((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [2]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [3]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0 .lut_mask = 16'h777F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5] & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [4]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1 .lut_mask = 16'h8C00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout = ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2 .lut_mask = 16'h1F3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~15 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y19_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3 .lut_mask = 16'hC840; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y19_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 $ (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5 .lut_mask = 16'hA820; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y19_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1] & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7] & !\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [9]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [7]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1 .lut_mask = 16'h0040; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y19_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref [6]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2 .lut_mask = 16'hC000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ) # +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0 .lut_mask = 16'hBA30; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y21_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0 .lut_mask = 16'h0F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & (\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ) # +// ((\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q & \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0 .lut_mask = 16'hDC50; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0 .lut_mask = 16'h5450; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1 .lut_mask = 16'hFFCF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout & +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0 .lut_mask = 16'hF888; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2 .lut_mask = 16'hFFF8; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~11 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N3 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~13 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~15 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~17 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~19 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7] & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ) # (GND))) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 = CARRY((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7])) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~23 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24 .lut_mask = 16'h3C3F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 $ (GND))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 & VCC)) +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 = CARRY((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .datac(gnd), + .datad(vcc), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~25 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout ), + .cout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 )); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26 .lut_mask = 16'hC30C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout = \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] $ (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datac(gnd), + .datad(gnd), + .cin(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~27 ), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X24_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9] & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [9]), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [8]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5 .lut_mask = 16'h0033; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0 .lut_mask = 16'hAAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y21_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout = ((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2] & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2 .lut_mask = 16'h5557; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ) # +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .lut_mask = 16'h00A8; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .lut_mask = 16'h5400; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .lut_mask = 16'hF078; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12 .lut_mask = 16'h6996; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N5 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q )) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .lut_mask = 16'h9696; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X17_Y20_N15 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1] $ (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2])) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [0]), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [1]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a [2]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .lut_mask = 16'h5AA5; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N1 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .lut_mask = 16'h2000; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N21 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q & (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .lut_mask = 16'h0200; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .lut_mask = 16'hB4F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N9 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N24 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout = (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout & +// !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .lut_mask = 16'h0040; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N19 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q & \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ))) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .lut_mask = 16'hC3F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y22_N7 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 .power_up = "low"; +// synopsys translate_on + +// Location: FF_X17_Y20_N27 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8] & +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8] & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8]), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [8]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .lut_mask = 16'h2814; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q )))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout & ((\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout +// )))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .lut_mask = 16'hE2C0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout = (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7])))) # (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout & +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout & (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout $ +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7])))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5_combout ), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2_combout ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g [7]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .lut_mask = 16'hA018; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y21_N29 +dffeas \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .is_wysiwyg = "true"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout = (\uart_rx_inst|po_flag~q & ((!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ) # +// (!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ))) + + .dataa(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg~q ), + .datab(gnd), + .datac(\uart_rx_inst|po_flag~q ), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .lut_mask = 16'h50F0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G9 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N1 +cycloneive_io_ibuf \rx~input ( + .i(rx), + .ibar(gnd), + .o(\rx~input_o )); +// synopsys translate_off +defparam \rx~input .bus_hold = "false"; +defparam \rx~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N12 +cycloneive_lcell_comb \uart_rx_inst|rx_reg1~0 ( +// Equation(s): +// \uart_rx_inst|rx_reg1~0_combout = !\rx~input_o + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\rx~input_o ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_reg1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y24_N13 +dffeas \uart_rx_inst|rx_reg1 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg1~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg1~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg1 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg1 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_reg2~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg2~feeder_combout = \uart_rx_inst|rx_reg1~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg1~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg2~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg2~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y24_N3 +dffeas \uart_rx_inst|rx_reg2 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg2~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg2~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg2 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg2 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y24_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_reg3~feeder ( +// Equation(s): +// \uart_rx_inst|rx_reg3~feeder_combout = \uart_rx_inst|rx_reg2~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg2~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_reg3~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_reg3~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y24_N1 +dffeas \uart_rx_inst|rx_reg3 ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_reg3~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_reg3~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_reg3 .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_reg3 .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N14 +cycloneive_lcell_comb \uart_rx_inst|rx_data[7]~0 ( +// Equation(s): +// \uart_rx_inst|rx_data[7]~0_combout = !\uart_rx_inst|rx_reg3~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_reg3~q ), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[7]~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7]~0 .lut_mask = 16'h00FF; +defparam \uart_rx_inst|rx_data[7]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N10 +cycloneive_lcell_comb \uart_rx_inst|bit_cnt~0 ( +// Equation(s): +// \uart_rx_inst|bit_cnt~0_combout = (\uart_rx_inst|Add1~6_combout & (((!\uart_rx_inst|always4~0_combout ) # (!\uart_rx_inst|bit_cnt [3])) # (!\uart_rx_inst|bit_flag~q ))) + + .dataa(\uart_rx_inst|Add1~6_combout ), + .datab(\uart_rx_inst|bit_flag~q ), + .datac(\uart_rx_inst|bit_cnt [3]), + .datad(\uart_rx_inst|always4~0_combout ), + .cin(gnd), + .combout(\uart_rx_inst|bit_cnt~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt~0 .lut_mask = 16'h2AAA; +defparam \uart_rx_inst|bit_cnt~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X16_Y25_N11 +dffeas \uart_rx_inst|bit_cnt[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|bit_cnt~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|bit_cnt [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|bit_cnt[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|bit_cnt[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X16_Y25_N18 +cycloneive_lcell_comb \uart_rx_inst|always8~0 ( +// Equation(s): +// \uart_rx_inst|always8~0_combout = (\uart_rx_inst|bit_flag~q & (\uart_rx_inst|always4~0_combout $ (!\uart_rx_inst|bit_cnt [3]))) + + .dataa(gnd), + .datab(\uart_rx_inst|always4~0_combout ), + .datac(\uart_rx_inst|bit_flag~q ), + .datad(\uart_rx_inst|bit_cnt [3]), + .cin(gnd), + .combout(\uart_rx_inst|always8~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|always8~0 .lut_mask = 16'hC030; +defparam \uart_rx_inst|always8~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N15 +dffeas \uart_rx_inst|rx_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[7]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y23_N21 +dffeas \uart_rx_inst|rx_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N18 +cycloneive_lcell_comb \uart_rx_inst|rx_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[5]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N19 +dffeas \uart_rx_inst|rx_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N0 +cycloneive_lcell_comb \uart_rx_inst|rx_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[4]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N1 +dffeas \uart_rx_inst|rx_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N6 +cycloneive_lcell_comb \uart_rx_inst|rx_data[3]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[3]~feeder_combout = \uart_rx_inst|rx_data [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [4]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N7 +dffeas \uart_rx_inst|rx_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N28 +cycloneive_lcell_comb \uart_rx_inst|rx_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[2]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N29 +dffeas \uart_rx_inst|rx_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N2 +cycloneive_lcell_comb \uart_rx_inst|rx_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[1]~feeder_combout = \uart_rx_inst|rx_data [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [2]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N3 +dffeas \uart_rx_inst|rx_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N24 +cycloneive_lcell_comb \uart_rx_inst|rx_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|rx_data[0]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|rx_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|rx_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N25 +dffeas \uart_rx_inst|rx_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|rx_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|always8~0_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|rx_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|rx_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|rx_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N8 +cycloneive_lcell_comb \uart_rx_inst|po_data[0]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[0]~feeder_combout = \uart_rx_inst|rx_data [0] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [0]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[0]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[0]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N9 +dffeas \uart_rx_inst|po_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[0]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[0] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a[9] ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9] = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10] $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [10]), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [9]), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9]), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a[9] .lut_mask = 16'h0FF0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a[9] .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout = !\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X17_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout = \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N10 +cycloneive_lcell_comb \uart_rx_inst|po_data[1]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[1]~feeder_combout = \uart_rx_inst|rx_data [1] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [1]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[1]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[1]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N11 +dffeas \uart_rx_inst|po_data[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[1]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[1] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N12 +cycloneive_lcell_comb \uart_rx_inst|po_data[2]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[2]~feeder_combout = \uart_rx_inst|rx_data [2] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [2]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[2]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[2]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N13 +dffeas \uart_rx_inst|po_data[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[2]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[2] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N30 +cycloneive_lcell_comb \uart_rx_inst|po_data[3]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[3]~feeder_combout = \uart_rx_inst|rx_data [3] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [3]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N31 +dffeas \uart_rx_inst|po_data[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[3]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [3]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[3] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N16 +cycloneive_lcell_comb \uart_rx_inst|po_data[4]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[4]~feeder_combout = \uart_rx_inst|rx_data [4] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [4]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[4]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[4]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N17 +dffeas \uart_rx_inst|po_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[4]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[4] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N26 +cycloneive_lcell_comb \uart_rx_inst|po_data[5]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[5]~feeder_combout = \uart_rx_inst|rx_data [5] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [5]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[5]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[5]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N27 +dffeas \uart_rx_inst|po_data[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[5]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[5] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y23_N4 +cycloneive_lcell_comb \uart_rx_inst|po_data[6]~feeder ( +// Equation(s): +// \uart_rx_inst|po_data[6]~feeder_combout = \uart_rx_inst|rx_data [6] + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_rx_inst|rx_data [6]), + .cin(gnd), + .combout(\uart_rx_inst|po_data[6]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6]~feeder .lut_mask = 16'hFF00; +defparam \uart_rx_inst|po_data[6]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y23_N5 +dffeas \uart_rx_inst|po_data[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\uart_rx_inst|po_data[6]~feeder_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[6] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[6] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X14_Y23_N23 +dffeas \uart_rx_inst|po_data[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\uart_rx_inst|rx_data [7]), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(\uart_rx_inst|rx_flag~q ), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_rx_inst|po_data [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_rx_inst|po_data[7] .is_wysiwyg = "true"; +defparam \uart_rx_inst|po_data[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X12_Y23_N8 +cycloneive_lcell_comb \~GND ( +// Equation(s): +// \~GND~combout = GND + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\~GND~combout ), + .cout()); +// synopsys translate_off +defparam \~GND .lut_mask = 16'h0000; +defparam \~GND .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X13_Y23_N0 +cycloneive_ram_block \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .ena0(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(\rst_n~0clkctrl_outclk ), + .portadatain({\~GND~combout ,\uart_rx_inst|po_data [7],\uart_rx_inst|po_data [6],\uart_rx_inst|po_data [5],\uart_rx_inst|po_data [4],\uart_rx_inst|po_data [3],\uart_rx_inst|po_data [2],\uart_rx_inst|po_data [1],\uart_rx_inst|po_data [0]}), + .portaaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "sdram_top:sdram_top_inst|fifo_ctrl:fifo_ctrl_inst|fifo_data:wr_fifo_data|dcfifo:dcfifo_component|dcfifo_3fk1:auto_generated|altsyncram_em31:fifo_ram|ALTSYNCRAM"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: LCCOMB_X14_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X14_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en .power_up = "low"; +// synopsys translate_on + +// Location: M9K_X13_Y21_N0 +cycloneive_ram_block \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 ( + .portawe(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .ena0(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0_combout ), + .ena1(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(\rst_n~0clkctrl_outclk ), + .portadatain({gnd,gnd,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout }), + .portaaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a [9],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [8], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [7],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [6],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [5], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [4],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [3],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [2], +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [1],\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q , +\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ,\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .clk0_core_clock_enable = "ena0"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .clk1_output_clock_enable = "ena1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .data_interleave_offset_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .data_interleave_width_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .logical_ram_name = "sdram_top:sdram_top_inst|fifo_ctrl:fifo_ctrl_inst|fifo_data:wr_fifo_data|dcfifo:dcfifo_component|dcfifo_3fk1:auto_generated|altsyncram_em31:fifo_ram|ALTSYNCRAM"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .mixed_port_feed_through_mode = "dont_care"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .operation_mode = "dual_port"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_address_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_byte_enable_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_data_out_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_data_out_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_first_bit_number = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_address_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_address_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_data_out_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_data_out_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_first_bit_number = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .port_b_read_enable_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: CLKCTRL_G5 +cycloneive_clkctrl \sys_clk~inputclkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\sys_clk~input_o }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\sys_clk~inputclkctrl_outclk )); +// synopsys translate_off +defparam \sys_clk~inputclkctrl .clock_type = "global clock"; +defparam \sys_clk~inputclkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N4 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[0]~13 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[0]~13_combout = (\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] $ (VCC))) # (!\uart_tx_inst|work_en~q & (\uart_tx_inst|baud_cnt [0] & VCC)) +// \uart_tx_inst|baud_cnt[0]~14 = CARRY((\uart_tx_inst|work_en~q & \uart_tx_inst|baud_cnt [0])) + + .dataa(\uart_tx_inst|work_en~q ), + .datab(\uart_tx_inst|baud_cnt [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\uart_tx_inst|baud_cnt[0]~13_combout ), + .cout(\uart_tx_inst|baud_cnt[0]~14 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0]~13 .lut_mask = 16'h6688; +defparam \uart_tx_inst|baud_cnt[0]~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N26 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[11]~35 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[11]~35_combout = (\uart_tx_inst|baud_cnt [11] & (!\uart_tx_inst|baud_cnt[10]~34 )) # (!\uart_tx_inst|baud_cnt [11] & ((\uart_tx_inst|baud_cnt[10]~34 ) # (GND))) +// \uart_tx_inst|baud_cnt[11]~36 = CARRY((!\uart_tx_inst|baud_cnt[10]~34 ) # (!\uart_tx_inst|baud_cnt [11])) + + .dataa(\uart_tx_inst|baud_cnt [11]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[10]~34 ), + .combout(\uart_tx_inst|baud_cnt[11]~35_combout ), + .cout(\uart_tx_inst|baud_cnt[11]~36 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11]~35 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[11]~35 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N27 +dffeas \uart_tx_inst|baud_cnt[11] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[11]~35_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [11]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[11] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[11] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N0 +cycloneive_lcell_comb \uart_tx_inst|Equal1~0 ( +// Equation(s): +// \uart_tx_inst|Equal1~0_combout = (!\uart_tx_inst|baud_cnt [3] & (!\uart_tx_inst|baud_cnt [5] & (\uart_tx_inst|baud_cnt [0] & !\uart_tx_inst|baud_cnt [7]))) + + .dataa(\uart_tx_inst|baud_cnt [3]), + .datab(\uart_tx_inst|baud_cnt [5]), + .datac(\uart_tx_inst|baud_cnt [0]), + .datad(\uart_tx_inst|baud_cnt [7]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~0 .lut_mask = 16'h0010; +defparam \uart_tx_inst|Equal1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N22 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[9]~31 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[9]~31_combout = (\uart_tx_inst|baud_cnt [9] & (!\uart_tx_inst|baud_cnt[8]~30 )) # (!\uart_tx_inst|baud_cnt [9] & ((\uart_tx_inst|baud_cnt[8]~30 ) # (GND))) +// \uart_tx_inst|baud_cnt[9]~32 = CARRY((!\uart_tx_inst|baud_cnt[8]~30 ) # (!\uart_tx_inst|baud_cnt [9])) + + .dataa(\uart_tx_inst|baud_cnt [9]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[8]~30 ), + .combout(\uart_tx_inst|baud_cnt[9]~31_combout ), + .cout(\uart_tx_inst|baud_cnt[9]~32 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9]~31 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[9]~31 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N23 +dffeas \uart_tx_inst|baud_cnt[9] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[9]~31_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [9]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[9] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N2 +cycloneive_lcell_comb \uart_tx_inst|Equal1~1 ( +// Equation(s): +// \uart_tx_inst|Equal1~1_combout = (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt [11] & (\uart_tx_inst|Equal1~0_combout & !\uart_tx_inst|baud_cnt [9]))) + + .dataa(\uart_tx_inst|baud_cnt [8]), + .datab(\uart_tx_inst|baud_cnt [11]), + .datac(\uart_tx_inst|Equal1~0_combout ), + .datad(\uart_tx_inst|baud_cnt [9]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~1 .lut_mask = 16'h0010; +defparam \uart_tx_inst|Equal1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N6 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[1]~15 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[1]~15_combout = (\uart_tx_inst|baud_cnt [1] & (!\uart_tx_inst|baud_cnt[0]~14 )) # (!\uart_tx_inst|baud_cnt [1] & ((\uart_tx_inst|baud_cnt[0]~14 ) # (GND))) +// \uart_tx_inst|baud_cnt[1]~16 = CARRY((!\uart_tx_inst|baud_cnt[0]~14 ) # (!\uart_tx_inst|baud_cnt [1])) + + .dataa(\uart_tx_inst|baud_cnt [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[0]~14 ), + .combout(\uart_tx_inst|baud_cnt[1]~15_combout ), + .cout(\uart_tx_inst|baud_cnt[1]~16 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1]~15 .lut_mask = 16'h5A5F; +defparam \uart_tx_inst|baud_cnt[1]~15 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N7 +dffeas \uart_tx_inst|baud_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[1]~15_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N30 +cycloneive_lcell_comb \uart_tx_inst|Equal1~2 ( +// Equation(s): +// \uart_tx_inst|Equal1~2_combout = (\uart_tx_inst|baud_cnt [4] & (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt [2] & \uart_tx_inst|baud_cnt [1]))) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [2]), + .datad(\uart_tx_inst|baud_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Equal1~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal1~2 .lut_mask = 16'h8000; +defparam \uart_tx_inst|Equal1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y25_N19 +dffeas \fifo_read_inst|tx_flag ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(gnd), + .asdata(\fifo_read_inst|rd_en~q ), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|tx_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|tx_flag .is_wysiwyg = "true"; +defparam \fifo_read_inst|tx_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N24 +cycloneive_lcell_comb \uart_tx_inst|always3~0 ( +// Equation(s): +// \uart_tx_inst|always3~0_combout = (!\uart_tx_inst|work_en~q ) # (!\uart_tx_inst|bit_flag~q ) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(gnd), + .datac(\uart_tx_inst|work_en~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_tx_inst|always3~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always3~0 .lut_mask = 16'h5F5F; +defparam \uart_tx_inst|always3~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N18 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[1]~2 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[1]~2_combout = (!\uart_tx_inst|always0~1_combout & (\uart_tx_inst|bit_cnt [1] $ (((\uart_tx_inst|bit_cnt [0] & !\uart_tx_inst|always3~0_combout ))))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [1]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[1]~2_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1]~2 .lut_mask = 16'h00D2; +defparam \uart_tx_inst|bit_cnt[1]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N19 +dffeas \uart_tx_inst|bit_cnt[1] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[1]~2_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [1]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[1] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N4 +cycloneive_lcell_comb \uart_tx_inst|bit_cnt[2]~3 ( +// Equation(s): +// \uart_tx_inst|bit_cnt[2]~3_combout = (!\uart_tx_inst|always0~1_combout & ((\uart_tx_inst|always3~0_combout & ((\uart_tx_inst|bit_cnt [2]))) # (!\uart_tx_inst|always3~0_combout & (\uart_tx_inst|Add1~0_combout )))) + + .dataa(\uart_tx_inst|Add1~0_combout ), + .datab(\uart_tx_inst|always3~0_combout ), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|bit_cnt[2]~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2]~3 .lut_mask = 16'h00E2; +defparam \uart_tx_inst|bit_cnt[2]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N5 +dffeas \uart_tx_inst|bit_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|bit_cnt[2]~3_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N2 +cycloneive_lcell_comb \uart_tx_inst|always0~1 ( +// Equation(s): +// \uart_tx_inst|always0~1_combout = (\uart_tx_inst|bit_cnt [0] & (!\uart_tx_inst|bit_cnt [1] & (!\uart_tx_inst|bit_cnt [2] & \uart_tx_inst|always0~0_combout ))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [1]), + .datac(\uart_tx_inst|bit_cnt [2]), + .datad(\uart_tx_inst|always0~0_combout ), + .cin(gnd), + .combout(\uart_tx_inst|always0~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~1 .lut_mask = 16'h0200; +defparam \uart_tx_inst|always0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y25_N18 +cycloneive_lcell_comb \uart_tx_inst|work_en~0 ( +// Equation(s): +// \uart_tx_inst|work_en~0_combout = (\fifo_read_inst|tx_flag~q ) # ((\uart_tx_inst|work_en~q & !\uart_tx_inst|always0~1_combout )) + + .dataa(gnd), + .datab(\uart_tx_inst|work_en~q ), + .datac(\fifo_read_inst|tx_flag~q ), + .datad(\uart_tx_inst|always0~1_combout ), + .cin(gnd), + .combout(\uart_tx_inst|work_en~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|work_en~0 .lut_mask = 16'hF0FC; +defparam \uart_tx_inst|work_en~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N25 +dffeas \uart_tx_inst|work_en ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(gnd), + .asdata(\uart_tx_inst|work_en~0_combout ), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|work_en~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|work_en .is_wysiwyg = "true"; +defparam \uart_tx_inst|work_en .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N6 +cycloneive_lcell_comb \uart_tx_inst|always1~0 ( +// Equation(s): +// \uart_tx_inst|always1~0_combout = ((\uart_tx_inst|Equal1~3_combout & (\uart_tx_inst|Equal1~1_combout & \uart_tx_inst|Equal1~2_combout ))) # (!\uart_tx_inst|work_en~q ) + + .dataa(\uart_tx_inst|Equal1~3_combout ), + .datab(\uart_tx_inst|Equal1~1_combout ), + .datac(\uart_tx_inst|Equal1~2_combout ), + .datad(\uart_tx_inst|work_en~q ), + .cin(gnd), + .combout(\uart_tx_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always1~0 .lut_mask = 16'h80FF; +defparam \uart_tx_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X27_Y18_N5 +dffeas \uart_tx_inst|baud_cnt[0] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[0]~13_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [0]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[0] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N8 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[2]~17 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[2]~17_combout = (\uart_tx_inst|baud_cnt [2] & (\uart_tx_inst|baud_cnt[1]~16 $ (GND))) # (!\uart_tx_inst|baud_cnt [2] & (!\uart_tx_inst|baud_cnt[1]~16 & VCC)) +// \uart_tx_inst|baud_cnt[2]~18 = CARRY((\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt[1]~16 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [2]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[1]~16 ), + .combout(\uart_tx_inst|baud_cnt[2]~17_combout ), + .cout(\uart_tx_inst|baud_cnt[2]~18 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2]~17 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[2]~17 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N9 +dffeas \uart_tx_inst|baud_cnt[2] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[2]~17_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [2]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[2] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N14 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[5]~23 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[5]~23_combout = (\uart_tx_inst|baud_cnt [5] & (!\uart_tx_inst|baud_cnt[4]~22 )) # (!\uart_tx_inst|baud_cnt [5] & ((\uart_tx_inst|baud_cnt[4]~22 ) # (GND))) +// \uart_tx_inst|baud_cnt[5]~24 = CARRY((!\uart_tx_inst|baud_cnt[4]~22 ) # (!\uart_tx_inst|baud_cnt [5])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [5]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[4]~22 ), + .combout(\uart_tx_inst|baud_cnt[5]~23_combout ), + .cout(\uart_tx_inst|baud_cnt[5]~24 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5]~23 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[5]~23 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N15 +dffeas \uart_tx_inst|baud_cnt[5] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[5]~23_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [5]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[5] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N16 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[6]~25 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[6]~25_combout = (\uart_tx_inst|baud_cnt [6] & (\uart_tx_inst|baud_cnt[5]~24 $ (GND))) # (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt[5]~24 & VCC)) +// \uart_tx_inst|baud_cnt[6]~26 = CARRY((\uart_tx_inst|baud_cnt [6] & !\uart_tx_inst|baud_cnt[5]~24 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[5]~24 ), + .combout(\uart_tx_inst|baud_cnt[6]~25_combout ), + .cout(\uart_tx_inst|baud_cnt[6]~26 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6]~25 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[6]~25 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N17 +dffeas \uart_tx_inst|baud_cnt[6] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[6]~25_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [6]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[6] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N18 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[7]~27 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[7]~27_combout = (\uart_tx_inst|baud_cnt [7] & (!\uart_tx_inst|baud_cnt[6]~26 )) # (!\uart_tx_inst|baud_cnt [7] & ((\uart_tx_inst|baud_cnt[6]~26 ) # (GND))) +// \uart_tx_inst|baud_cnt[7]~28 = CARRY((!\uart_tx_inst|baud_cnt[6]~26 ) # (!\uart_tx_inst|baud_cnt [7])) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [7]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[6]~26 ), + .combout(\uart_tx_inst|baud_cnt[7]~27_combout ), + .cout(\uart_tx_inst|baud_cnt[7]~28 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7]~27 .lut_mask = 16'h3C3F; +defparam \uart_tx_inst|baud_cnt[7]~27 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N19 +dffeas \uart_tx_inst|baud_cnt[7] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[7]~27_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [7]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[7] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N20 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[8]~29 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[8]~29_combout = (\uart_tx_inst|baud_cnt [8] & (\uart_tx_inst|baud_cnt[7]~28 $ (GND))) # (!\uart_tx_inst|baud_cnt [8] & (!\uart_tx_inst|baud_cnt[7]~28 & VCC)) +// \uart_tx_inst|baud_cnt[8]~30 = CARRY((\uart_tx_inst|baud_cnt [8] & !\uart_tx_inst|baud_cnt[7]~28 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [8]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[7]~28 ), + .combout(\uart_tx_inst|baud_cnt[8]~29_combout ), + .cout(\uart_tx_inst|baud_cnt[8]~30 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8]~29 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[8]~29 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N21 +dffeas \uart_tx_inst|baud_cnt[8] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[8]~29_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [8]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[8] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N24 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[10]~33 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[10]~33_combout = (\uart_tx_inst|baud_cnt [10] & (\uart_tx_inst|baud_cnt[9]~32 $ (GND))) # (!\uart_tx_inst|baud_cnt [10] & (!\uart_tx_inst|baud_cnt[9]~32 & VCC)) +// \uart_tx_inst|baud_cnt[10]~34 = CARRY((\uart_tx_inst|baud_cnt [10] & !\uart_tx_inst|baud_cnt[9]~32 )) + + .dataa(gnd), + .datab(\uart_tx_inst|baud_cnt [10]), + .datac(gnd), + .datad(vcc), + .cin(\uart_tx_inst|baud_cnt[9]~32 ), + .combout(\uart_tx_inst|baud_cnt[10]~33_combout ), + .cout(\uart_tx_inst|baud_cnt[10]~34 )); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10]~33 .lut_mask = 16'hC30C; +defparam \uart_tx_inst|baud_cnt[10]~33 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N25 +dffeas \uart_tx_inst|baud_cnt[10] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[10]~33_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [10]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[10] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N28 +cycloneive_lcell_comb \uart_tx_inst|baud_cnt[12]~37 ( +// Equation(s): +// \uart_tx_inst|baud_cnt[12]~37_combout = \uart_tx_inst|baud_cnt[11]~36 $ (!\uart_tx_inst|baud_cnt [12]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\uart_tx_inst|baud_cnt [12]), + .cin(\uart_tx_inst|baud_cnt[11]~36 ), + .combout(\uart_tx_inst|baud_cnt[12]~37_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12]~37 .lut_mask = 16'hF00F; +defparam \uart_tx_inst|baud_cnt[12]~37 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X27_Y18_N29 +dffeas \uart_tx_inst|baud_cnt[12] ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|baud_cnt[12]~37_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(\uart_tx_inst|always1~0_combout ), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|baud_cnt [12]), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|baud_cnt[12] .is_wysiwyg = "true"; +defparam \uart_tx_inst|baud_cnt[12] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y18_N2 +cycloneive_lcell_comb \uart_tx_inst|Equal2~0 ( +// Equation(s): +// \uart_tx_inst|Equal2~0_combout = (!\uart_tx_inst|baud_cnt [4] & (!\uart_tx_inst|baud_cnt [6] & (!\uart_tx_inst|baud_cnt [2] & !\uart_tx_inst|baud_cnt [1]))) + + .dataa(\uart_tx_inst|baud_cnt [4]), + .datab(\uart_tx_inst|baud_cnt [6]), + .datac(\uart_tx_inst|baud_cnt [2]), + .datad(\uart_tx_inst|baud_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~0 .lut_mask = 16'h0001; +defparam \uart_tx_inst|Equal2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y18_N24 +cycloneive_lcell_comb \uart_tx_inst|Equal2~1 ( +// Equation(s): +// \uart_tx_inst|Equal2~1_combout = (\uart_tx_inst|Equal1~1_combout & (!\uart_tx_inst|baud_cnt [12] & (\uart_tx_inst|Equal2~0_combout & !\uart_tx_inst|baud_cnt [10]))) + + .dataa(\uart_tx_inst|Equal1~1_combout ), + .datab(\uart_tx_inst|baud_cnt [12]), + .datac(\uart_tx_inst|Equal2~0_combout ), + .datad(\uart_tx_inst|baud_cnt [10]), + .cin(gnd), + .combout(\uart_tx_inst|Equal2~1_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|Equal2~1 .lut_mask = 16'h0020; +defparam \uart_tx_inst|Equal2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X24_Y18_N25 +dffeas \uart_tx_inst|bit_flag ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|Equal2~1_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|bit_flag~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|bit_flag .is_wysiwyg = "true"; +defparam \uart_tx_inst|bit_flag .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N28 +cycloneive_lcell_comb \uart_tx_inst|always0~0 ( +// Equation(s): +// \uart_tx_inst|always0~0_combout = (\uart_tx_inst|bit_cnt [3] & \uart_tx_inst|bit_flag~q ) + + .dataa(\uart_tx_inst|bit_cnt [3]), + .datab(gnd), + .datac(\uart_tx_inst|bit_flag~q ), + .datad(gnd), + .cin(gnd), + .combout(\uart_tx_inst|always0~0_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|always0~0 .lut_mask = 16'hA0A0; +defparam \uart_tx_inst|always0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X27_Y24_N30 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q & \fifo_read_inst|rd_en~q ) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~q ), + .datab(gnd), + .datac(gnd), + .datad(\fifo_read_inst|rd_en~q ), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq .lut_mask = 16'hAA00; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N8 +cycloneive_io_ibuf \sdram_dq[0]~input ( + .i(sdram_dq[0]), + .ibar(gnd), + .o(\sdram_dq[0]~input_o )); +// synopsys translate_off +defparam \sdram_dq[0]~input .bus_hold = "false"; +defparam \sdram_dq[0]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[0]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X24_Y25_N10 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout = !\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~q ), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .lut_mask = 16'h00FF; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y26_N30 +cycloneive_lcell_comb \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 ( +// Equation(s): +// \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout = \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q $ +// (\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~q ), + .datac(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .lut_mask = 16'h3C3C; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N1 +cycloneive_io_ibuf \sdram_dq[1]~input ( + .i(sdram_dq[1]), + .ibar(gnd), + .o(\sdram_dq[1]~input_o )); +// synopsys translate_off +defparam \sdram_dq[1]~input .bus_hold = "false"; +defparam \sdram_dq[1]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[1]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [1] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y29_N1 +cycloneive_io_ibuf \sdram_dq[2]~input ( + .i(sdram_dq[2]), + .ibar(gnd), + .o(\sdram_dq[2]~input_o )); +// synopsys translate_off +defparam \sdram_dq[2]~input .bus_hold = "false"; +defparam \sdram_dq[2]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[2]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y29_N29 +cycloneive_io_ibuf \sdram_dq[3]~input ( + .i(sdram_dq[3]), + .ibar(gnd), + .o(\sdram_dq[3]~input_o )); +// synopsys translate_off +defparam \sdram_dq[3]~input .bus_hold = "false"; +defparam \sdram_dq[3]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N5 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[3]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [3]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[3] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [3] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [3]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X14_Y29_N22 +cycloneive_io_ibuf \sdram_dq[4]~input ( + .i(sdram_dq[4]), + .ibar(gnd), + .o(\sdram_dq[4]~input_o )); +// synopsys translate_off +defparam \sdram_dq[4]~input .bus_hold = "false"; +defparam \sdram_dq[4]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N27 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[4]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [4]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[4] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [4] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [4]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X9_Y29_N8 +cycloneive_io_ibuf \sdram_dq[5]~input ( + .i(sdram_dq[5]), + .ibar(gnd), + .o(\sdram_dq[5]~input_o )); +// synopsys translate_off +defparam \sdram_dq[5]~input .bus_hold = "false"; +defparam \sdram_dq[5]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N17 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[5]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [5]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[5] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [5] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [5]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N15 +cycloneive_io_ibuf \sdram_dq[6]~input ( + .i(sdram_dq[6]), + .ibar(gnd), + .o(\sdram_dq[6]~input_o )); +// synopsys translate_off +defparam \sdram_dq[6]~input .bus_hold = "false"; +defparam \sdram_dq[6]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[6]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [6]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[6] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [6] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [6]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X11_Y29_N22 +cycloneive_io_ibuf \sdram_dq[7]~input ( + .i(sdram_dq[7]), + .ibar(gnd), + .o(\sdram_dq[7]~input_o )); +// synopsys translate_off +defparam \sdram_dq[7]~input .bus_hold = "false"; +defparam \sdram_dq[7]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X21_Y25_N23 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_dq[7]~input_o ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [7]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[7] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y25_N22 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [7] & \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg [7]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7 .lut_mask = 16'hF000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: M9K_X25_Y25_N0 +cycloneive_ram_block \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 ( + .portawe(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .portare(vcc), + .portaaddrstall(gnd), + .portbwe(gnd), + .portbre(vcc), + .portbaddrstall(!\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .clk0(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .clk1(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .ena0(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1_combout ), + .ena1(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0_combout ), + .ena2(vcc), + .ena3(vcc), + .clr0(gnd), + .clr1(\rst_n~0clkctrl_outclk ), + .portadatain({gnd,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0_combout , +\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4_combout , +\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6_combout ,\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5_combout }), + .portaaddr({\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9~combout ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [8], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [7],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [6],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [5], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [4],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [3],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [2], +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [1],\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g [0]}), + .portabyteenamasks(1'b1), + .portbdatain(9'b000000000), + .portbaddr({\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0_combout ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~q , +\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~q ,\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell_combout }), + .portbbyteenamasks(1'b1), + .devclrn(devclrn), + .devpor(devpor), + .portadataout(), + .portbdataout(\sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0_PORTBDATAOUT_bus )); +// synopsys translate_off +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk0_core_clock_enable = "ena0"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .clk1_output_clock_enable = "ena1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_offset_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .data_interleave_width_in_bits = 1; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .logical_ram_name = "sdram_top:sdram_top_inst|fifo_ctrl:fifo_ctrl_inst|fifo_data:rd_fifo_data|dcfifo:dcfifo_component|dcfifo_3fk1:auto_generated|altsyncram_em31:fifo_ram|ALTSYNCRAM"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .mixed_port_feed_through_mode = "dont_care"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .operation_mode = "dual_port"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_byte_enable_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clear = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_out_clock = "none"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_a_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_address_width = 10; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clear = "clear1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_out_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_data_width = 9; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_address = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_first_bit_number = 0; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_last_address = 1023; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_depth = 1024; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_logical_ram_width = 16; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_during_write_mode = "new_data_with_nbe_read"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .port_b_read_enable_clock = "clock1"; +defparam \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 .ram_block_type = "M9K"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N6 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0] $ (VCC) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT = CARRY(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0 .lut_mask = 16'h55AA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N7 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N8 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N9 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N10 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N11 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3])) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N14 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N15 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N17 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N18 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N19 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N21 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N23 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y19_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9] $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9]), + .datac(gnd), + .datad(gnd), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9 .lut_mask = 16'h3C3C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y19_N25 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N10 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0] $ (VCC) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT = CARRY(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0 .lut_mask = 16'h55AA; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N11 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [0]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N12 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1])) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1 .lut_mask = 16'h5A5F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N13 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [1]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N14 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N15 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [2]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N16 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N17 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [3]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N18 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT )) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4 .lut_mask = 16'hC30C; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N19 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [4]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N20 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N21 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [5]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N22 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N23 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [6]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N24 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT )) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7] & +// ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ) # (GND))) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT = CARRY((!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ) # +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7])) + + .dataa(gnd), + .datab(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7]), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7 .lut_mask = 16'h3C3F; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N25 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [7]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N26 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout = (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8] & +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT $ (GND))) # (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8] & +// (!\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT & VCC)) +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT = CARRY((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8] & +// !\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT )) + + .dataa(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout ), + .cout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT )); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8 .lut_mask = 16'hA50A; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N27 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [8]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X26_Y18_N28 +cycloneive_lcell_comb \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9 ( +// Equation(s): +// \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout = \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT $ +// (\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9]), + .cin(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8~COUT ), + .combout(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout ), + .cout()); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9 .lut_mask = 16'h0FF0; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X26_Y18_N29 +dffeas \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9~combout ), + .asdata(vcc), + .clrn(vcc), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq~combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit [9]), + .prn(vcc)); +// synopsys translate_off +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .is_wysiwyg = "true"; +defparam \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N14 +cycloneive_lcell_comb \uart_tx_inst|tx~4 ( +// Equation(s): +// \uart_tx_inst|tx~4_combout = (\uart_tx_inst|bit_cnt [0]) # ((\uart_tx_inst|bit_cnt [2]) # ((\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [7]) # (\uart_tx_inst|bit_cnt [1]))) + + .dataa(\uart_tx_inst|bit_cnt [0]), + .datab(\uart_tx_inst|bit_cnt [2]), + .datac(\fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|q_b [7]), + .datad(\uart_tx_inst|bit_cnt [1]), + .cin(gnd), + .combout(\uart_tx_inst|tx~4_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~4 .lut_mask = 16'hFFFE; +defparam \uart_tx_inst|tx~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N8 +cycloneive_lcell_comb \uart_tx_inst|tx~3 ( +// Equation(s): +// \uart_tx_inst|tx~3_combout = (!\uart_tx_inst|bit_flag~q & !\uart_tx_inst|tx~q ) + + .dataa(\uart_tx_inst|bit_flag~q ), + .datab(gnd), + .datac(gnd), + .datad(\uart_tx_inst|tx~q ), + .cin(gnd), + .combout(\uart_tx_inst|tx~3_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~3 .lut_mask = 16'h0055; +defparam \uart_tx_inst|tx~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y18_N0 +cycloneive_lcell_comb \uart_tx_inst|tx~5 ( +// Equation(s): +// \uart_tx_inst|tx~5_combout = (!\uart_tx_inst|tx~2_combout & (!\uart_tx_inst|tx~3_combout & ((!\uart_tx_inst|tx~4_combout ) # (!\uart_tx_inst|always0~0_combout )))) + + .dataa(\uart_tx_inst|tx~2_combout ), + .datab(\uart_tx_inst|always0~0_combout ), + .datac(\uart_tx_inst|tx~4_combout ), + .datad(\uart_tx_inst|tx~3_combout ), + .cin(gnd), + .combout(\uart_tx_inst|tx~5_combout ), + .cout()); +// synopsys translate_off +defparam \uart_tx_inst|tx~5 .lut_mask = 16'h0015; +defparam \uart_tx_inst|tx~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y18_N1 +dffeas \uart_tx_inst|tx ( + .clk(\sys_clk~inputclkctrl_outclk ), + .d(\uart_tx_inst|tx~5_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\uart_tx_inst|tx~q ), + .prn(vcc)); +// synopsys translate_off +defparam \uart_tx_inst|tx .is_wysiwyg = "true"; +defparam \uart_tx_inst|tx .power_up = "low"; +// synopsys translate_on + +// Location: CLKCTRL_G7 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X23_Y22_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: FF_X23_Y22_N7 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q )) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1 .lut_mask = 16'hF0FC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0 .lut_mask = 16'hBAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0 .lut_mask = 16'h4000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2 .lut_mask = 16'hFF20; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0 .lut_mask = 16'hFFAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout )) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [1])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [1]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [1]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2 .lut_mask = 16'h8C9D; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [1]))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [1])))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [1]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3 .lut_mask = 16'h5F22; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF~q ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0 .lut_mask = 16'hFAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N24 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1_combout ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17 .lut_mask = 16'h00CC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N25 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) # +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5 .lut_mask = 16'hFFEE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N12 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .datab(gnd), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0 .lut_mask = 16'hFFAA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y22_N13 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [2])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [2] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0 .lut_mask = 16'hA1AB; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [2])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout & ((!\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [2]))))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [2]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1 .lut_mask = 16'h5F30; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N4 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ) # +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0 .lut_mask = 16'h5554; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N1 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0 .lut_mask = 16'hFFF0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout & ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ) # +// (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1 .lut_mask = 16'hAAA0; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [0]) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout )))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [0] & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd [0]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1 .lut_mask = 16'h1ABA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y22_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ) # (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1_combout ), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2 .lut_mask = 16'hFAFA; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8] & !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [8]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [9]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6 .lut_mask = 16'h0008; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2] & +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk [2]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1 .lut_mask = 16'h4055; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N8 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6 .lut_mask = 16'h0F00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ) + + .dataa(gnd), + .datab(gnd), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3 .lut_mask = 16'hF0FF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N9 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[0] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N14 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] $ +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]))) + + .dataa(gnd), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5 .lut_mask = 16'h3C00; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N15 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N28 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2] $ +// (((\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]))))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4 .lut_mask = 16'h7800; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X31_Y20_N29 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3_combout ), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[2] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X31_Y20_N26 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3] & (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0] & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1] & !\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [3]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref [2]), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15 .lut_mask = 16'h0002; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X28_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout & (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q & +// (\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2] & \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk [2]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16 .lut_mask = 16'h8000; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X28_Y21_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS .power_up = "low"; +// synopsys translate_on + +// Location: FF_X21_Y21_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(gnd), + .asdata(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS~q ), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0 .lut_mask = 16'h55CF; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1 .lut_mask = 16'hF7F2; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N16 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4_combout ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0 .lut_mask = 16'h4CCC; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N18 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2 .lut_mask = 16'h0001; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N19 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba[1] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N2 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0] & +// ((!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])))) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & +// (((!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1])))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [0]), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba [1]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0 .lut_mask = 16'h0777; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N0 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q & +// !\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE~q ), + .datad(gnd), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0 .lut_mask = 16'h0101; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X22_Y22_N30 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout & (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout & +// ((\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0 .lut_mask = 16'h2022; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X22_Y22_N31 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y22_N10 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q & (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q & +// \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q )) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~q ), + .datac(gnd), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16 .lut_mask = 16'h4400; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X21_Y22_N11 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10])) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q & !\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0 .lut_mask = 16'h5053; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X23_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout = (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout & (((\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout & +// \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0_combout ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7_combout ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA~q ), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1 .lut_mask = 16'h008F; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X23_Y21_N21 +dffeas \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl_outclk ), + .d(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10]), + .prn(vcc)); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr[10] .is_wysiwyg = "true"; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N20 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (((!\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10])))) # +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q & (((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q )) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba [1]), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE~q ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0 .lut_mask = 16'h0FDD; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X21_Y21_N6 +cycloneive_lcell_comb \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1 ( +// Equation(s): +// \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout = (\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ) # ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & +// (!\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10])) # (!\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q & ((\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout )))) + + .dataa(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ~q ), + .datab(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT~q ), + .datac(\sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr [10]), + .datad(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0_combout ), + .cin(gnd), + .combout(\sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1_combout ), + .cout()); +// synopsys translate_off +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1 .lut_mask = 16'hDFCE; +defparam \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y20_N8 +cycloneive_io_ibuf \sdram_dq[8]~input ( + .i(sdram_dq[8]), + .ibar(gnd), + .o(\sdram_dq[8]~input_o )); +// synopsys translate_off +defparam \sdram_dq[8]~input .bus_hold = "false"; +defparam \sdram_dq[8]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X3_Y29_N29 +cycloneive_io_ibuf \sdram_dq[9]~input ( + .i(sdram_dq[9]), + .ibar(gnd), + .o(\sdram_dq[9]~input_o )); +// synopsys translate_off +defparam \sdram_dq[9]~input .bus_hold = "false"; +defparam \sdram_dq[9]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y25_N1 +cycloneive_io_ibuf \sdram_dq[10]~input ( + .i(sdram_dq[10]), + .ibar(gnd), + .o(\sdram_dq[10]~input_o )); +// synopsys translate_off +defparam \sdram_dq[10]~input .bus_hold = "false"; +defparam \sdram_dq[10]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y26_N8 +cycloneive_io_ibuf \sdram_dq[11]~input ( + .i(sdram_dq[11]), + .ibar(gnd), + .o(\sdram_dq[11]~input_o )); +// synopsys translate_off +defparam \sdram_dq[11]~input .bus_hold = "false"; +defparam \sdram_dq[11]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y23_N8 +cycloneive_io_ibuf \sdram_dq[12]~input ( + .i(sdram_dq[12]), + .ibar(gnd), + .o(\sdram_dq[12]~input_o )); +// synopsys translate_off +defparam \sdram_dq[12]~input .bus_hold = "false"; +defparam \sdram_dq[12]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N8 +cycloneive_io_ibuf \sdram_dq[13]~input ( + .i(sdram_dq[13]), + .ibar(gnd), + .o(\sdram_dq[13]~input_o )); +// synopsys translate_off +defparam \sdram_dq[13]~input .bus_hold = "false"; +defparam \sdram_dq[13]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N22 +cycloneive_io_ibuf \sdram_dq[14]~input ( + .i(sdram_dq[14]), + .ibar(gnd), + .o(\sdram_dq[14]~input_o )); +// synopsys translate_off +defparam \sdram_dq[14]~input .bus_hold = "false"; +defparam \sdram_dq[14]~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y21_N1 +cycloneive_io_ibuf \sdram_dq[15]~input ( + .i(sdram_dq[15]), + .ibar(gnd), + .o(\sdram_dq[15]~input_o )); +// synopsys translate_off +defparam \sdram_dq[15]~input .bus_hold = "false"; +defparam \sdram_dq[15]~input .simulate_z_as = "z"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_min_1200mv_0c_v_fast.sdo b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_min_1200mv_0c_v_fast.sdo new file mode 100644 index 0000000..cc7d6fb --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_min_1200mv_0c_v_fast.sdo @@ -0,0 +1,19618 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Fast Corner delays for the design using part EP4CE15F23C8, +// with speed grade M, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "uart_sdram") + (DATE "06/02/2023 04:26:31") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (718:718:718) (815:815:815)) + (PORT d[1] (691:691:691) (783:783:783)) + (PORT d[2] (728:728:728) (837:837:837)) + (PORT d[3] (725:725:725) (826:826:826)) + (PORT d[4] (705:705:705) (799:799:799)) + (PORT d[5] (709:709:709) (803:803:803)) + (PORT d[6] (725:725:725) (828:828:828)) + (PORT d[7] (718:718:718) (819:819:819)) + (PORT clk (1066:1066:1066) (1085:1085:1085)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (532:532:532) (624:624:624)) + (PORT d[1] (559:559:559) (655:655:655)) + (PORT d[2] (395:395:395) (470:470:470)) + (PORT d[3] (483:483:483) (562:562:562)) + (PORT d[4] (405:405:405) (485:485:485)) + (PORT d[5] (388:388:388) (463:463:463)) + (PORT d[6] (496:496:496) (578:578:578)) + (PORT d[7] (543:543:543) (639:639:639)) + (PORT d[8] (395:395:395) (470:470:470)) + (PORT d[9] (392:392:392) (468:468:468)) + (PORT clk (1064:1064:1064) (1083:1083:1083)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (864:864:864) (932:932:932)) + (PORT clk (1064:1064:1064) (1083:1083:1083)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1066:1066:1066) (1085:1085:1085)) + (PORT d[0] (1148:1148:1148) (1225:1225:1225)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1086:1086:1086)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1086:1086:1086)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1086:1086:1086)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1067:1067:1067) (1086:1086:1086)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (399:399:399) (473:473:473)) + (PORT d[1] (396:396:396) (461:461:461)) + (PORT d[2] (561:561:561) (656:656:656)) + (PORT d[3] (695:695:695) (809:809:809)) + (PORT d[4] (397:397:397) (469:469:469)) + (PORT d[5] (749:749:749) (898:898:898)) + (PORT d[6] (691:691:691) (809:809:809)) + (PORT d[7] (549:549:549) (638:638:638)) + (PORT d[8] (403:403:403) (479:479:479)) + (PORT d[9] (577:577:577) (667:667:667)) + (PORT clk (1023:1023:1023) (1044:1044:1044)) + (PORT ena (1058:1058:1058) (1126:1126:1126)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + (HOLD ena (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1023:1023:1023) (1044:1044:1044)) + (PORT d[0] (1058:1058:1058) (1126:1126:1126)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1045:1045:1045)) + (IOPATH (posedge clk) pulse (0:0:0) (1145:1145:1145)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1045:1045:1045)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1045:1045:1045)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2551:2551:2551) (2299:2299:2299)) + (PORT sclr (545:545:545) (627:627:627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2551:2551:2551) (2299:2299:2299)) + (PORT sclr (545:545:545) (627:627:627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (313:313:313) (377:377:377)) + (PORT datab (198:198:198) (251:251:251)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (449:449:449)) + (PORT datab (385:385:385) (469:469:469)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (636:636:636) (753:753:753)) + (PORT datab (200:200:200) (257:257:257)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (199:199:199) (257:257:257)) + (PORT datab (318:318:318) (387:387:387)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (204:204:204)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[5\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (204:204:204)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (189:189:189)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (195:195:195)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (281:281:281)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (331:331:331) (396:396:396)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~26) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (189:189:189)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita1) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (275:275:275)) + (PORT datab (390:390:390) (462:462:462)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita2) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (196:196:196)) + (PORT datab (389:389:389) (461:461:461)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita3) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (198:198:198)) + (PORT datab (389:389:389) (461:461:461)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita4) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (268:268:268)) + (PORT datab (388:388:388) (460:460:460)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita5) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (276:276:276)) + (PORT datab (387:387:387) (458:458:458)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita6) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (276:276:276)) + (PORT datab (386:386:386) (458:458:458)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita7) + (DELAY + (ABSOLUTE + (PORT dataa (312:312:312) (376:376:376)) + (PORT datab (386:386:386) (457:457:457)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita8) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (194:194:194)) + (PORT datab (385:385:385) (456:456:456)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita9) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3047:3047:3047) (2733:2733:2733)) + (PORT sclr (391:391:391) (452:452:452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3047:3047:3047) (2733:2733:2733)) + (PORT sclr (391:391:391) (452:452:452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3047:3047:3047) (2733:2733:2733)) + (PORT sclr (391:391:391) (452:452:452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3047:3047:3047) (2733:2733:2733)) + (PORT sclr (391:391:391) (452:452:452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Add2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2934:2934:2934) (2626:2626:2626)) + (PORT sclr (620:620:620) (738:738:738)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2934:2934:2934) (2626:2626:2626)) + (PORT sclr (620:620:620) (738:738:738)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2934:2934:2934) (2626:2626:2626)) + (PORT sclr (620:620:620) (738:738:738)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2934:2934:2934) (2626:2626:2626)) + (PORT sclr (620:620:620) (738:738:738)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2934:2934:2934) (2626:2626:2626)) + (PORT sclr (620:620:620) (738:738:738)) + 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(84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2934:2934:2934) (2626:2626:2626)) + (PORT sclr (620:620:620) (738:738:738)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2934:2934:2934) (2626:2626:2626)) + (PORT sclr (620:620:620) (738:738:738)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE 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(IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2940:2940:2940) (2632:2632:2632)) + (PORT sclr (610:610:610) (719:719:719)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2940:2940:2940) (2632:2632:2632)) + (PORT sclr (610:610:610) (719:719:719)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[20\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2940:2940:2940) (2632:2632:2632)) + (PORT sclr (610:610:610) (719:719:719)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[21\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2940:2940:2940) (2632:2632:2632)) + (PORT sclr (610:610:610) (719:719:719)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[22\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2940:2940:2940) (2632:2632:2632)) + (PORT sclr (610:610:610) (719:719:719)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[23\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2940:2940:2940) (2632:2632:2632)) + (PORT sclr (610:610:610) (719:719:719)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE 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cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~6) + (DELAY + (ABSOLUTE + (PORT datab (208:208:208) (262:262:262)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (268:268:268)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (267:267:267)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (281:281:281)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (280:280:280)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE 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datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~22) + (DELAY + (ABSOLUTE + (PORT datab (364:364:364) (439:439:439)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~24) + (DELAY + (ABSOLUTE + (PORT datab (209:209:209) (263:263:263)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~26) + (DELAY + (ABSOLUTE + (PORT datab (224:224:224) (277:277:277)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~28) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (280:280:280)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~30) + (DELAY + (ABSOLUTE + (PORT datad (206:206:206) (252:252:252)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (195:195:195)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (197:197:197)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (873:873:873)) + (PORT datab (135:135:135) (184:184:184)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (186:186:186)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (187:187:187)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[3\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[4\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (183:183:183)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[5\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[6\]\~36) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (189:189:189)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[7\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (186:186:186)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[8\]\~40) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (182:182:182)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[9\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[10\]\~44) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (183:183:183)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[11\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[12\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (132:132:132) (182:182:182)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[13\]\~50) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (183:183:183)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[14\]\~52) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[15\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (188:188:188)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[16\]\~56) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[17\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (186:186:186)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[18\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[19\]\~62) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[20\]\~64) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[21\]\~66) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[22\]\~68) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[23\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (188:188:188)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2783:2783:2783) (2483:2483:2483)) + (PORT sclr (331:331:331) (381:381:381)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2783:2783:2783) (2483:2483:2483)) + (PORT sclr (331:331:331) (381:381:381)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2783:2783:2783) (2483:2483:2483)) + (PORT sclr (331:331:331) (381:381:381)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2783:2783:2783) (2483:2483:2483)) + (PORT sclr (331:331:331) (381:381:381)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2783:2783:2783) (2483:2483:2483)) + (PORT sclr (331:331:331) (381:381:381)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2783:2783:2783) (2483:2483:2483)) + (PORT sclr (331:331:331) (381:381:381)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2783:2783:2783) (2483:2483:2483)) + (PORT sclr (331:331:331) (381:381:381)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2783:2783:2783) (2483:2483:2483)) + (PORT sclr (331:331:331) (381:381:381)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2783:2783:2783) (2483:2483:2483)) + (PORT sclr (331:331:331) (381:381:381)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2783:2783:2783) (2483:2483:2483)) + (PORT sclr (331:331:331) (381:381:381)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (187:187:187)) + (PORT datab (154:154:154) (210:210:210)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datad (135:135:135) (179:179:179)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (PORT sclr (404:404:404) (473:473:473)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (336:336:336) (407:407:407)) + (PORT datab (132:132:132) (182:182:182)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (183:183:183)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[5\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[8\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[9\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (196:196:196)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT asdata (652:652:652) (728:728:728)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (450:450:450) (527:527:527)) + (PORT datab (456:456:456) (526:526:526)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2554:2554:2554) (2301:2301:2301)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (303:303:303) (345:345:345)) + (PORT datab (170:170:170) (227:227:227)) + (PORT datac (300:300:300) (342:342:342)) + (PORT datad (151:151:151) (203:203:203)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (462:462:462)) + (PORT datab (377:377:377) (443:443:443)) + (PORT datac (458:458:458) (523:523:523)) + (PORT datad (509:509:509) (598:598:598)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (167:167:167) (233:233:233)) + (PORT datab (331:331:331) (381:381:381)) + (PORT datac (597:597:597) (683:683:683)) + (PORT datad (154:154:154) (202:202:202)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~1) + (DELAY + (ABSOLUTE + (PORT dataa (167:167:167) (229:229:229)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (296:296:296) (338:338:338)) + (PORT datad (155:155:155) (204:204:204)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (452:452:452)) + (PORT datab (154:154:154) (210:210:210)) + (PORT datac (428:428:428) (483:483:483)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2554:2554:2554) (2301:2301:2301)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (133:133:133) (184:184:184)) + (PORT datab (240:240:240) (299:299:299)) + (PORT datac (494:494:494) (577:577:577)) + (PORT datad (140:140:140) (186:186:186)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\~0) + (DELAY + (ABSOLUTE + (PORT datac (196:196:196) (248:248:248)) + (PORT datad (204:204:204) (249:249:249)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|WideOr5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (672:672:672) (798:798:798)) + (PORT datad (651:651:651) (768:768:768)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (163:163:163) (222:222:222)) + (PORT datab (148:148:148) (199:199:199)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (385:385:385) (466:466:466)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (144:144:144) (196:196:196)) + (PORT datab (173:173:173) (233:233:233)) + (PORT datac (365:365:365) (430:430:430)) + (PORT datad (425:425:425) (498:498:498)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector21\~0) + (DELAY + (ABSOLUTE + (PORT dataa (162:162:162) (221:221:221)) + (PORT datab (108:108:108) (140:140:140)) + (PORT datac (133:133:133) (176:176:176)) + (PORT datad (131:131:131) (169:169:169)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (168:168:168) (234:234:234)) + (PORT datac (137:137:137) (186:186:186)) + (PORT datad (154:154:154) (201:201:201)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (171:171:171) (235:235:235)) + (PORT datab (155:155:155) (212:212:212)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (154:154:154) (202:202:202)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (136:136:136)) + (PORT datab (112:112:112) (145:145:145)) + (PORT datad (119:119:119) (143:143:143)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (PORT ena (407:407:407) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (204:204:204)) + (PORT datab (147:147:147) (197:197:197)) + (PORT datac (135:135:135) (179:179:179)) + (PORT datad (136:136:136) (176:176:176)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (864:864:864) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE read_valid) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2773:2773:2773) (2476:2476:2476)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~0) + (DELAY + (ABSOLUTE + (PORT datac (95:95:95) (118:118:118)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (762:762:762)) + (PORT datab (388:388:388) (463:463:463)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_TMRD) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (853:853:853) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.IDLE\~0) + (DELAY + (ABSOLUTE + (PORT dataa (507:507:507) (599:599:599)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (863:863:863)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (869:869:869)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (869:869:869)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (869:869:869)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT datab (376:376:376) (453:453:453)) + (PORT datad (377:377:377) (453:453:453)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (633:633:633) (678:678:678)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~0) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (278:278:278)) + (PORT datab (216:216:216) (274:274:274)) + (PORT datac (364:364:364) (433:433:433)) + (PORT datad (367:367:367) (445:445:445)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (633:633:633) (678:678:678)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (633:633:633) (678:678:678)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (633:633:633) (678:678:678)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (633:633:633) (678:678:678)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~1) + (DELAY + (ABSOLUTE + (PORT dataa (219:219:219) (276:276:276)) + (PORT datab (148:148:148) (199:199:199)) + (PORT datac (128:128:128) (174:174:174)) + (PORT datad (135:135:135) (174:174:174)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (633:633:633) (678:678:678)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (633:633:633) (678:678:678)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (633:633:633) (678:678:678)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~2) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (198:198:198)) + (PORT datab (147:147:147) (197:197:197)) + (PORT datac (130:130:130) (171:171:171)) + (PORT datad (135:135:135) (175:175:175)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~3) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (381:381:381)) + (PORT datab (339:339:339) (388:388:388)) + (PORT datac (374:374:374) (441:441:441)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2935:2935:2935) (2627:2627:2627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (274:274:274)) + (PORT datab (146:146:146) (196:196:196)) + (PORT datac (125:125:125) (170:170:170)) + (PORT datad (133:133:133) (171:171:171)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (141:141:141) (196:196:196)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (133:133:133) (176:176:176)) + (PORT datad (130:130:130) (168:168:168)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (186:186:186)) + (PORT datac (382:382:382) (456:456:456)) + (PORT datad (521:521:521) (617:617:617)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~2) + (DELAY + (ABSOLUTE + (PORT datac (162:162:162) (195:195:195)) + (PORT datad (128:128:128) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT asdata (372:372:372) (426:426:426)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (127:127:127) (173:173:173)) + (PORT datad (333:333:333) (388:388:388)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT asdata (687:687:687) (776:776:776)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (193:193:193)) + (PORT datac (126:126:126) (171:171:171)) + (PORT datad (332:332:332) (387:387:387)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (639:639:639)) + (PORT datab (541:541:541) (642:642:642)) + (PORT datac (539:539:539) (631:631:631)) + (PORT datad (99:99:99) (119:119:119)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datab (542:542:542) (639:639:639)) + (PORT datac (92:92:92) (114:114:114)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT dataa (383:383:383) (468:468:468)) + (PORT datab (373:373:373) (443:443:443)) + (PORT datad (390:390:390) (463:463:463)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datab (375:375:375) (445:445:445)) + (PORT datad (390:390:390) (464:464:464)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (194:194:194)) + (PORT datac (129:129:129) (170:170:170)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (285:285:285)) + (PORT datac (146:146:146) (189:189:189)) + (PORT datad (140:140:140) (182:182:182)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (610:610:610)) + (PORT datac (138:138:138) (187:187:187)) + (PORT datad (101:101:101) (123:123:123)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (192:192:192) (247:247:247)) + (PORT datad (324:324:324) (377:377:377)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (455:455:455)) + (PORT datab (364:364:364) (440:440:440)) + (PORT datac (185:185:185) (224:224:224)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT asdata (676:676:676) (756:756:756)) + (PORT clrn (851:851:851) (855:855:855)) + (PORT ena (801:801:801) (879:879:879)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (336:336:336) (404:404:404)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datac (139:139:139) (188:188:188)) + (PORT datad (101:101:101) (123:123:123)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (186:186:186)) + (PORT datac (129:129:129) (177:177:177)) + (PORT datad (201:201:201) (250:250:250)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT datac (129:129:129) (176:176:176)) + (PORT datad (200:200:200) (250:250:250)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2666:2666:2666) (2397:2397:2397)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2666:2666:2666) (2397:2397:2397)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2666:2666:2666) (2397:2397:2397)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2666:2666:2666) (2397:2397:2397)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (144:144:144) (195:195:195)) + (PORT datab (143:143:143) (192:192:192)) + (PORT datac (130:130:130) (171:171:171)) + (PORT datad (130:130:130) (167:167:167)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2773:2773:2773) (2476:2476:2476)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2773:2773:2773) (2476:2476:2476)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2773:2773:2773) (2476:2476:2476)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (881:881:881) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2773:2773:2773) (2476:2476:2476)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (PORT datab (142:142:142) (190:190:190)) + (PORT datac (128:128:128) (169:169:169)) + (PORT datad (192:192:192) (240:240:240)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2666:2666:2666) (2397:2397:2397)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2666:2666:2666) (2397:2397:2397)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2666:2666:2666) (2397:2397:2397)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2666:2666:2666) (2397:2397:2397)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (192:192:192)) + (PORT datab (142:142:142) (190:190:190)) + (PORT datac (128:128:128) (168:168:168)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2666:2666:2666) (2397:2397:2397)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2666:2666:2666) (2397:2397:2397)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2666:2666:2666) (2397:2397:2397)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (889:889:889)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2666:2666:2666) (2397:2397:2397)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (266:266:266)) + (PORT datab (145:145:145) (194:194:194)) + (PORT datac (131:131:131) (172:172:172)) + (PORT datad (131:131:131) (169:169:169)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (324:324:324) (370:370:370)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE read_valid\~0) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (397:397:397)) + (PORT datab (332:332:332) (385:385:385)) + (PORT datac (362:362:362) (427:427:427)) + (PORT datad (130:130:130) (168:168:168)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE read_valid\~1) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (422:422:422)) + (PORT datab (362:362:362) (422:422:422)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (270:270:270)) + (PORT datab (143:143:143) (191:191:191)) + (PORT datad (192:192:192) (223:223:223)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (234:234:234) (290:290:290)) + (PORT datab (165:165:165) (223:223:223)) + (PORT datac (152:152:152) (206:206:206)) + (PORT datad (125:125:125) (166:166:166)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (191:191:191)) + (PORT datab (153:153:153) (206:206:206)) + (PORT datac (125:125:125) (172:172:172)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~2) + (DELAY + (ABSOLUTE + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (143:143:143) (184:184:184)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (439:439:439)) + (PORT datab (388:388:388) (461:461:461)) + (PORT datad (327:327:327) (376:376:376)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (201:201:201)) + (PORT datab (143:143:143) (196:196:196)) + (PORT datac (128:128:128) (175:175:175)) + (PORT datad (127:127:127) (168:168:168)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT asdata (791:791:791) (889:889:889)) + (PORT clrn (859:859:859) (863:863:863)) + (PORT ena (834:834:834) (919:919:919)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (203:203:203)) + (PORT datab (512:512:512) (605:605:605)) + (PORT datad (511:511:511) (593:593:593)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT asdata (863:863:863) (978:978:978)) + (PORT clrn (867:867:867) (871:871:871)) + (PORT ena (655:655:655) (712:712:712)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (278:278:278)) + (PORT datab (214:214:214) (268:268:268)) + (PORT datad (136:136:136) (175:175:175)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (204:204:204)) + (PORT datab (225:225:225) (281:281:281)) + (PORT datad (212:212:212) (259:259:259)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT datac (163:163:163) (195:195:195)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (592:592:592)) + (PORT datab (378:378:378) (461:461:461)) + (PORT datad (132:132:132) (169:169:169)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (207:207:207) (266:266:266)) + (PORT datab (142:142:142) (190:190:190)) + (PORT datad (135:135:135) (175:175:175)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (200:200:200)) + (PORT datab (144:144:144) (192:192:192)) + (PORT datad (130:130:130) (168:168:168)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (103:103:103) (131:131:131)) + (PORT datac (90:90:90) (112:112:112)) + (PORT datad (319:319:319) (367:367:367)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (490:490:490) (561:561:561)) + (PORT datab (502:502:502) (578:578:578)) + (PORT datac (500:500:500) (578:578:578)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (193:193:193)) + (PORT datab (146:146:146) (195:195:195)) + (PORT datad (213:213:213) (264:264:264)) + (IOPATH dataa combout (181:181:181) (184:184:184)) + (IOPATH datab combout (182:182:182) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (240:240:240) (300:300:300)) + (PORT datab (148:148:148) (197:197:197)) + (PORT datad (139:139:139) (181:181:181)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT asdata (996:996:996) (1109:1109:1109)) + (PORT clrn (864:864:864) (868:868:868)) + (PORT ena (688:688:688) (745:745:745)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (353:353:353)) + (PORT datab (179:179:179) (216:216:216)) + (PORT datad (145:145:145) (183:183:183)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (160:160:160) (213:213:213)) + (PORT datab (230:230:230) (287:287:287)) + (PORT datad (211:211:211) (260:260:260)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (276:276:276)) + (PORT datab (155:155:155) (203:203:203)) + (PORT datad (209:209:209) (258:258:258)) + (IOPATH dataa combout (181:181:181) (184:184:184)) + (IOPATH datab combout (182:182:182) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (231:231:231)) + (PORT datab (206:206:206) (266:266:266)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (133:133:133) (171:171:171)) + (PORT datac (309:309:309) (360:360:360)) + (PORT datad (330:330:330) (385:385:385)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (639:639:639)) + (PORT datab (714:714:714) (838:838:838)) + (PORT datad (186:186:186) (233:233:233)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (262:262:262)) + (PORT datab (378:378:378) (460:460:460)) + (PORT datad (500:500:500) (596:596:596)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT asdata (499:499:499) (561:561:561)) + (PORT clrn (864:864:864) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (418:418:418)) + (PORT datab (148:148:148) (199:199:199)) + (PORT datad (131:131:131) (169:169:169)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (385:385:385) (444:444:444)) + (PORT datad (194:194:194) (245:245:245)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT asdata (509:509:509) (567:567:567)) + (PORT clrn (864:864:864) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (264:264:264)) + (PORT datab (403:403:403) (481:481:481)) + (PORT datad (510:510:510) (597:597:597)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (203:203:203)) + (PORT datab (125:125:125) (158:158:158)) + (PORT datac (139:139:139) (186:186:186)) + (PORT datad (139:139:139) (181:181:181)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (121:121:121) (163:163:163)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (270:270:270)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (193:193:193)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (123:123:123) (163:163:163)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (191:191:191)) + (PORT datab (137:137:137) (187:187:187)) + (PORT datac (122:122:122) (166:166:166)) + (PORT datad (124:124:124) (164:164:164)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (378:378:378)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (190:190:190)) + (PORT datab (136:136:136) (185:185:185)) + (PORT datac (122:122:122) (166:166:166)) + (PORT datad (123:123:123) (163:163:163)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (268:268:268)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout 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+ ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[15\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (233:233:233)) + (PORT datab (408:408:408) (485:485:485)) + (PORT datad (389:389:389) (448:448:448)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[14\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (479:479:479)) + (PORT datab (175:175:175) (214:214:214)) + (PORT datad (387:387:387) (456:456:456)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[13\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (477:477:477)) + (PORT datab (272:272:272) (318:318:318)) + (PORT datad (389:389:389) (458:458:458)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[12\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (404:404:404) (478:478:478)) + (PORT datab (189:189:189) (227:227:227)) + (PORT datad (389:389:389) (458:458:458)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[9\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (133:133:133) (171:171:171)) + (PORT datab (339:339:339) (389:389:389)) + (PORT datad (114:114:114) (135:135:135)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[11\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (169:169:169)) + (PORT datab (329:329:329) (383:383:383)) + (PORT datad (116:116:116) (139:139:139)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[10\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (168:168:168)) + (PORT datab (325:325:325) (379:379:379)) + (PORT datad (115:115:115) (138:138:138)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[8\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (133:133:133) (169:169:169)) + (PORT datab (345:345:345) (402:402:402)) + (PORT datad (116:116:116) (139:139:139)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[7\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (471:471:471)) + (PORT datab (190:190:190) (230:230:230)) + (PORT datad (395:395:395) (465:465:465)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (401:401:401) (474:474:474)) + (PORT datab (190:190:190) (230:230:230)) + (PORT datad (392:392:392) (462:462:462)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[5\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (475:475:475)) + (PORT datab (176:176:176) (216:216:216)) + (PORT datad (392:392:392) (461:461:461)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (476:476:476)) + (PORT datab (192:192:192) (233:233:233)) + (PORT datad (390:390:390) (460:460:460)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (219:219:219)) + (PORT datab (414:414:414) (493:493:493)) + (PORT datad (384:384:384) (442:442:442)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (234:234:234)) + (PORT datab (414:414:414) (492:492:492)) + (PORT datad (384:384:384) (442:442:442)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (176:176:176) (219:219:219)) + (PORT datab (416:416:416) (494:494:494)) + (PORT datad (383:383:383) (440:440:440)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (477:477:477)) + (PORT datab (193:193:193) (233:233:233)) + (PORT datad (390:390:390) (459:459:459)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (590:590:590)) + (PORT datab (388:388:388) (470:470:470)) + (PORT datad (212:212:212) (262:262:262)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (296:296:296)) + (PORT datab (215:215:215) (274:274:274)) + (PORT datad (365:365:365) (437:437:437)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (420:420:420)) + (PORT datab (220:220:220) (275:275:275)) + (PORT datac (354:354:354) (420:420:420)) + (PORT datad (346:346:346) (411:411:411)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (140:140:140)) + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (651:651:651) (755:755:755)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (434:434:434)) + (PORT datab (379:379:379) (457:457:457)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb\|data_wire\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (739:739:739) (850:850:850)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (390:390:390)) + (PORT datab (437:437:437) (501:501:501)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (229:229:229) (283:283:283)) + (PORT datab (203:203:203) (260:260:260)) + (PORT datad (641:641:641) (748:748:748)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (188:188:188) (223:223:223)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (161:161:161) (188:188:188)) + (PORT datad (120:120:120) (145:145:145)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (496:496:496) (593:593:593)) + (PORT datab (150:150:150) (206:206:206)) + (PORT datad (349:349:349) (419:419:419)) + (IOPATH dataa combout (181:181:181) (184:184:184)) + (IOPATH datab combout (182:182:182) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (144:144:144) (201:201:201)) + (PORT datab (370:370:370) (445:445:445)) + (PORT datac (548:548:548) (653:653:653)) + (PORT datad (131:131:131) (175:175:175)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (152:152:152) (211:211:211)) + (PORT datab (153:153:153) (209:209:209)) + (PORT datac (347:347:347) (411:411:411)) + (PORT datad (343:343:343) (412:412:412)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (414:414:414)) + (PORT datab (140:140:140) (175:175:175)) + (PORT datad (174:174:174) (207:207:207)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (418:418:418)) + (PORT datab (207:207:207) (267:267:267)) + (PORT datad (202:202:202) (253:253:253)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (458:458:458)) + (PORT datab (144:144:144) (193:193:193)) + (PORT datad (326:326:326) (386:386:386)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (151:151:151) (209:209:209)) + (PORT datab (367:367:367) (450:450:450)) + (PORT datad (344:344:344) (411:411:411)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (154:154:154) (211:211:211)) + (PORT datab (152:152:152) (204:204:204)) + (PORT datac (479:479:479) (558:558:558)) + (PORT datad (150:150:150) (192:192:192)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|rd_flag) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2962:2962:2962) (2645:2645:2645)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (196:196:196)) + (PORT datab (139:139:139) (191:191:191)) + (PORT datac (126:126:126) (171:171:171)) + (PORT datad (126:126:126) (167:167:167)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|cntr_cout\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (539:539:539) (648:648:648)) + (PORT datab (370:370:370) (445:445:445)) + (PORT datac (175:175:175) (202:202:202)) + (PORT datad (125:125:125) (164:164:164)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (PORT ena (694:694:694) (759:759:759)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (192:192:192)) + (PORT datab (138:138:138) (188:188:188)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (125:125:125) (165:165:165)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (191:191:191)) + (PORT datab (137:137:137) (187:187:187)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (124:124:124) (164:164:164)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (215:215:215)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (122:122:122) (161:161:161)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|rd_flag\~0) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (426:426:426)) + (PORT datab (396:396:396) (472:472:472)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (204:204:204)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (138:138:138) (187:187:187)) + (PORT datad (107:107:107) (132:132:132)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~13) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (570:570:570)) + (PORT datab (152:152:152) (204:204:204)) + (PORT datac (137:137:137) (183:183:183)) + (PORT datad (134:134:134) (172:172:172)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|start_nedge) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (482:482:482) (574:574:574)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (375:375:375) (453:453:453)) + (PORT datab (129:129:129) (163:163:163)) + (PORT datad (323:323:323) (387:387:387)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (584:584:584) (678:678:678)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (461:461:461) (547:547:547)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (130:130:130) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (324:324:324) (393:393:393)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (200:200:200) (250:250:250)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tx\~output) + (DELAY + (ABSOLUTE + (PORT i (1210:1210:1210) (1044:1044:1044)) + (IOPATH i o (1755:1755:1755) (1782:1782:1782)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_clk\~output) + (DELAY + (ABSOLUTE + (PORT i (745:745:745) (776:776:776)) + (IOPATH i o (1647:1647:1647) (1627:1627:1627)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_cas_n\~output) + (DELAY + (ABSOLUTE + (PORT i (897:897:897) (1012:1012:1012)) + (IOPATH i o (1667:1667:1667) (1647:1647:1647)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_ras_n\~output) + (DELAY + (ABSOLUTE + (PORT i (932:932:932) (1051:1051:1051)) + (IOPATH i o (2582:2582:2582) (2667:2667:2667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_we_n\~output) + (DELAY + (ABSOLUTE + (PORT i (998:998:998) (1147:1147:1147)) + (IOPATH i o (1687:1687:1687) (1667:1667:1667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_ba\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1395:1395:1395) (1583:1583:1583)) + (IOPATH i o (1667:1667:1667) (1647:1647:1647)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_ba\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1501:1501:1501) (1711:1711:1711)) + (IOPATH i o (1667:1667:1667) (1647:1647:1647)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1069:1069:1069) (1198:1198:1198)) + (IOPATH i o (1677:1677:1677) (1657:1657:1657)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1066:1066:1066) (1201:1201:1201)) + (IOPATH i o (1812:1812:1812) (1785:1785:1785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1066:1066:1066) (1201:1201:1201)) + (IOPATH i o (1812:1812:1812) (1785:1785:1785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1396:1396:1396) (1581:1581:1581)) + (IOPATH i o (1812:1812:1812) (1785:1785:1785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1229:1229:1229) (1382:1382:1382)) + (IOPATH i o (1812:1812:1812) (1785:1785:1785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1244:1244:1244) (1399:1399:1399)) + (IOPATH i o (1792:1792:1792) (1765:1765:1765)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1855:1855:1855) (2120:2120:2120)) + (IOPATH i o (1792:1792:1792) (1765:1765:1765)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1681:1681:1681) (1925:1925:1925)) + (IOPATH i o (1782:1782:1782) (1755:1755:1755)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1861:1861:1861) (2127:2127:2127)) + (IOPATH i o (1792:1792:1792) (1765:1765:1765)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1114:1114:1114) (1261:1261:1261)) + (IOPATH i o (1782:1782:1782) (1755:1755:1755)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1136:1136:1136) (1301:1301:1301)) + (IOPATH i o (1687:1687:1687) (1667:1667:1667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1114:1114:1114) (1261:1261:1261)) + (IOPATH i o (1792:1792:1792) (1765:1765:1765)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1322:1322:1322) (1498:1498:1498)) + (IOPATH i o (1782:1782:1782) (1755:1755:1755)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (652:652:652) (729:729:729)) + (PORT oe (688:688:688) (799:799:799)) + (IOPATH i o (1667:1667:1667) (1647:1647:1647)) + (IOPATH oe o (1686:1686:1686) (1644:1644:1644)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (629:629:629) (700:700:700)) + (PORT oe (688:688:688) (799:799:799)) + (IOPATH i o (1667:1667:1667) (1647:1647:1647)) + (IOPATH oe o (1686:1686:1686) (1644:1644:1644)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (671:671:671) (747:747:747)) + (PORT oe (828:828:828) (970:970:970)) + (IOPATH i o (1627:1627:1627) (1607:1607:1607)) + (IOPATH oe o (1686:1686:1686) (1644:1644:1644)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (458:458:458) (507:507:507)) + (PORT oe (510:510:510) (593:593:593)) + (IOPATH i o (1657:1657:1657) (1637:1637:1637)) + (IOPATH oe o (1686:1686:1686) (1644:1644:1644)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (470:470:470) (521:521:521)) + (PORT oe (510:510:510) (593:593:593)) + (IOPATH i o (1667:1667:1667) (1647:1647:1647)) + (IOPATH oe o (1686:1686:1686) (1644:1644:1644)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (644:644:644) (716:716:716)) + (PORT oe (828:828:828) (970:970:970)) + (IOPATH i o (1647:1647:1647) (1627:1627:1627)) + (IOPATH oe o (1686:1686:1686) (1644:1644:1644)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (650:650:650) (724:724:724)) + (PORT oe (688:688:688) (799:799:799)) + (IOPATH i o (1677:1677:1677) (1657:1657:1657)) + (IOPATH oe o (1686:1686:1686) (1644:1644:1644)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (503:503:503) (567:567:567)) + (PORT oe (688:688:688) (799:799:799)) + (IOPATH i o (1667:1667:1667) (1647:1647:1647)) + (IOPATH oe o (1686:1686:1686) (1644:1644:1644)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (699:699:699) (794:794:794)) + (PORT oe (1083:1083:1083) (1251:1251:1251)) + (IOPATH i o (1792:1792:1792) (1765:1765:1765)) + (IOPATH oe o (1810:1810:1810) (1750:1750:1750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (719:719:719) (806:806:806)) + (PORT oe (920:920:920) (1067:1067:1067)) + (IOPATH i o (1677:1677:1677) (1657:1657:1657)) + (IOPATH oe o (1686:1686:1686) (1644:1644:1644)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (828:828:828) (929:929:929)) + (PORT oe (781:781:781) (910:910:910)) + (IOPATH i o (1802:1802:1802) (1775:1775:1775)) + (IOPATH oe o (1810:1810:1810) (1750:1750:1750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (926:926:926) (1044:1044:1044)) + (PORT oe (923:923:923) (1070:1070:1070)) + (IOPATH i o (1782:1782:1782) (1755:1755:1755)) + (IOPATH oe o (1810:1810:1810) (1750:1750:1750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (756:756:756) (853:853:853)) + (PORT oe (946:946:946) (1102:1102:1102)) + (IOPATH i o (1772:1772:1772) (1745:1745:1745)) + (IOPATH oe o (1810:1810:1810) (1750:1750:1750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (613:613:613) (689:689:689)) + (PORT oe (954:954:954) (1111:1111:1111)) + (IOPATH i o (1782:1782:1782) (1755:1755:1755)) + (IOPATH oe o (1810:1810:1810) (1750:1750:1750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (697:697:697) (778:778:778)) + (PORT oe (954:954:954) (1111:1111:1111)) + (IOPATH i o (2596:2596:2596) (2713:2713:2713)) + (IOPATH oe o (2634:2634:2634) (2717:2717:2717)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (670:670:670) (746:746:746)) + (PORT oe (954:954:954) (1111:1111:1111)) + (IOPATH i o (1675:1675:1675) (1683:1683:1683)) + (IOPATH oe o (1714:1714:1714) (1688:1688:1688)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (273:273:273)) + (PORT datab (141:141:141) (189:189:189)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (358:358:358) (738:738:738)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (2369:2369:2369) (2369:2369:2369)) + (PORT inclk[0] (1104:1104:1104) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (1030:1030:1030) (907:907:907)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2773:2773:2773) (2476:2476:2476)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2202:2202:2202) (2492:2492:2492)) + (PORT datac (715:715:715) (598:598:598)) + (PORT datad (117:117:117) (153:153:153)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1056:1056:1056) (1177:1177:1177)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (191:191:191)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (PORT sclr (404:404:404) (473:473:473)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (192:192:192)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (PORT sclr (404:404:404) (473:473:473)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (201:201:201)) + (PORT datab (222:222:222) (277:277:277)) + (PORT datac (129:129:129) (176:176:176)) + (PORT datad (129:129:129) (171:171:171)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (PORT sclr (404:404:404) (473:473:473)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (PORT sclr (404:404:404) (473:473:473)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (PORT sclr (404:404:404) (473:473:473)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (230:230:230) (284:284:284)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (124:124:124) (163:163:163)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (PORT sclr (404:404:404) (473:473:473)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (PORT sclr (404:404:404) (473:473:473)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datac (318:318:318) (373:373:373)) + (PORT datad (203:203:203) (249:249:249)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (PORT sclr (404:404:404) (473:473:473)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (294:294:294)) + (PORT datab (233:233:233) (289:289:289)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (203:203:203) (248:248:248)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (PORT datab (171:171:171) (209:209:209)) + (PORT datac (172:172:172) (208:208:208)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (PORT sclr (404:404:404) (473:473:473)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (PORT sclr (404:404:404) (473:473:473)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (PORT sclr (404:404:404) (473:473:473)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (201:201:201)) + (PORT datab (222:222:222) (277:277:277)) + (PORT datac (129:129:129) (175:175:175)) + (PORT datad (129:129:129) (170:170:170)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (PORT sclr (404:404:404) (473:473:473)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (217:217:217) (276:276:276)) + (PORT datab (231:231:231) (285:285:285)) + (PORT datac (316:316:316) (371:371:371)) + (PORT datad (201:201:201) (245:245:245)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (230:230:230)) + (PORT datab (189:189:189) (226:226:226)) + (PORT datac (215:215:215) (270:270:270)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (188:188:188)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (192:192:192)) + (PORT datab (139:139:139) (189:189:189)) + (PORT datac (124:124:124) (169:169:169)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (203:203:203)) + (PORT datab (120:120:120) (155:155:155)) + (PORT datac (137:137:137) (186:186:186)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_flag) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_flag) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT asdata (680:680:680) (771:771:771)) + (PORT clrn (852:852:852) (856:856:856)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (207:207:207)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a0) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (PORT ena (987:987:987) (1095:1095:1095)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (203:203:203)) + (PORT datab (807:807:807) (936:936:936)) + (PORT datad (217:217:217) (267:267:267)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (234:234:234) (299:299:299)) + (PORT datab (152:152:152) (204:204:204)) + (PORT datac (130:130:130) (178:178:178)) + (PORT datad (676:676:676) (784:784:784)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (89:89:89) (107:107:107)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (128:128:128) (162:162:162)) + (PORT datad (215:215:215) (265:265:265)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~10) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (290:290:290)) + (PORT datab (154:154:154) (207:207:207)) + (PORT datac (147:147:147) (197:197:197)) + (PORT datad (218:218:218) (268:268:268)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (PORT ena (987:987:987) (1095:1095:1095)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (227:227:227)) + (PORT datab (163:163:163) (219:219:219)) + (PORT datad (214:214:214) (264:264:264)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (216:216:216)) + (PORT datab (129:129:129) (163:163:163)) + (PORT datac (147:147:147) (197:197:197)) + (PORT datad (134:134:134) (172:172:172)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (312:312:312) (362:362:362)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (172:172:172) (235:235:235)) + (PORT datad (320:320:320) (369:369:369)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (448:448:448)) + (PORT datab (151:151:151) (207:207:207)) + (PORT datac (154:154:154) (210:210:210)) + (PORT datad (147:147:147) (192:192:192)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (PORT ena (455:455:455) (491:491:491)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (162:162:162) (219:219:219)) + (PORT datab (151:151:151) (206:206:206)) + (PORT datac (155:155:155) (211:211:211)) + (PORT datad (320:320:320) (369:369:369)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8\~0) + (DELAY + (ABSOLUTE + (PORT datad (157:157:157) (182:182:182)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (162:162:162) (220:220:220)) + (PORT datab (152:152:152) (208:208:208)) + (PORT datac (154:154:154) (209:209:209)) + (PORT datad (319:319:319) (369:369:369)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10\~0) + (DELAY + (ABSOLUTE + (PORT datab (154:154:154) (209:209:209)) + (PORT datad (167:167:167) (193:193:193)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (180:180:180) (218:218:218)) + (PORT datad (139:139:139) (183:183:183)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT datab (152:152:152) (207:207:207)) + (PORT datac (127:127:127) (173:173:173)) + (PORT datad (297:297:297) (355:355:355)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (PORT ena (503:503:503) (535:535:535)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT datab (133:133:133) (182:182:182)) + (PORT datac (345:345:345) (419:419:419)) + (PORT datad (437:437:437) (513:513:513)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|parity9) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (PORT ena (987:987:987) (1095:1095:1095)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (297:297:297)) + (PORT datab (152:152:152) (203:203:203)) + (PORT datac (130:130:130) (177:177:177)) + (PORT datad (674:674:674) (782:782:782)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (157:157:157) (214:214:214)) + (PORT datab (128:128:128) (162:162:162)) + (PORT datac (147:147:147) (196:196:196)) + (PORT datad (134:134:134) (172:172:172)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (173:173:173) (236:236:236)) + (PORT datab (334:334:334) (393:393:393)) + (PORT datad (147:147:147) (192:192:192)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT asdata (305:305:305) (351:351:351)) + (PORT clrn (852:852:852) (856:856:856)) + (PORT ena (503:503:503) (535:535:535)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (196:196:196)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (135:135:135) (184:184:184)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (122:122:122) (162:162:162)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (209:209:209)) + (PORT datab (149:149:149) (204:204:204)) + (PORT datac (133:133:133) (182:182:182)) + (PORT datad (133:133:133) (177:177:177)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (328:328:328) (396:396:396)) + (PORT datab (222:222:222) (282:282:282)) + (PORT datac (192:192:192) (237:237:237)) + (PORT datad (180:180:180) (215:215:215)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (139:139:139) (183:183:183)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (PORT ena (503:503:503) (535:535:535)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT asdata (375:375:375) (425:425:425)) + (PORT clrn (852:852:852) (856:856:856)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (444:444:444) (523:523:523)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (354:354:354)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (PORT ena (503:503:503) (535:535:535)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (135:135:135) (174:174:174)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (488:488:488) (578:578:578)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (129:129:129) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (448:448:448) (523:523:523)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (277:277:277)) + (PORT datab (136:136:136) (187:187:187)) + (PORT datac (128:128:128) (175:175:175)) + (PORT datad (199:199:199) (248:248:248)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (149:149:149) (193:193:193)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (PORT ena (455:455:455) (491:491:491)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT asdata (929:929:929) (1047:1047:1047)) + (PORT clrn (852:852:852) (856:856:856)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT asdata (466:466:466) (523:523:523)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (190:190:190)) + (PORT datab (114:114:114) (147:147:147)) + (PORT datac (127:127:127) (174:174:174)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT asdata (532:532:532) (598:598:598)) + (PORT clrn (852:852:852) (856:856:856)) + (PORT ena (455:455:455) (491:491:491)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (491:491:491) (572:572:572)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (135:135:135) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (115:115:115) (147:147:147)) + (PORT datac (129:129:129) (176:176:176)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (116:116:116) (150:150:150)) + (PORT datad (510:510:510) (601:601:601)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT asdata (316:316:316) (362:362:362)) + (PORT clrn (854:854:854) (858:858:858)) + (PORT ena (987:987:987) (1095:1095:1095)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (670:670:670) (783:783:783)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT asdata (326:326:326) (375:375:375)) + (PORT clrn (854:854:854) (858:858:858)) + (PORT ena (987:987:987) (1095:1095:1095)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT asdata (659:659:659) (748:748:748)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (167:167:167) (223:223:223)) + (PORT datab (143:143:143) (192:192:192)) + (PORT datad (508:508:508) (599:599:599)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (166:166:166) (221:221:221)) + (PORT datab (115:115:115) (148:148:148)) + (PORT datac (130:130:130) (172:172:172)) + (PORT datad (509:509:509) (600:600:600)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (316:316:316) (364:364:364)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT asdata (329:329:329) (382:382:382)) + (PORT clrn (852:852:852) (856:856:856)) + (PORT ena (455:455:455) (491:491:491)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT asdata (749:749:749) (834:834:834)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (459:459:459)) + (PORT datab (154:154:154) (202:202:202)) + (PORT datad (133:133:133) (172:172:172)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT datad (152:152:152) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (PORT ena (694:694:694) (759:759:759)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (246:246:246) (301:301:301)) + (PORT datab (153:153:153) (205:205:205)) + (PORT datad (376:376:376) (443:443:443)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (453:453:453) (526:526:526)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (PORT ena (455:455:455) (491:491:491)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT asdata (973:973:973) (1108:1108:1108)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (268:268:268)) + (PORT datab (507:507:507) (605:605:605)) + (PORT datad (512:512:512) (601:601:601)) + (IOPATH dataa combout (181:181:181) (184:184:184)) + (IOPATH datab combout (182:182:182) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (484:484:484) (560:560:560)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (449:449:449) (510:510:510)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (649:649:649) (722:722:722)) + (PORT clrn (855:855:855) (858:858:858)) + (PORT ena (435:435:435) (462:462:462)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT asdata (782:782:782) (875:875:875)) + (PORT clrn (851:851:851) (855:855:855)) + (PORT ena (801:801:801) (879:879:879)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (393:393:393)) + (PORT datab (318:318:318) (378:378:378)) + (PORT datad (486:486:486) (580:580:580)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (808:808:808) (944:944:944)) + (PORT datab (231:231:231) (286:286:286)) + (PORT datad (195:195:195) (239:239:239)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (485:485:485) (563:563:563)) + (PORT datac (449:449:449) (517:517:517)) + (PORT datad (713:713:713) (807:807:807)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (89:89:89) (110:110:110)) + (PORT datad (175:175:175) (208:208:208)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (672:672:672) (757:757:757)) + (PORT clrn (855:855:855) (858:858:858)) + (PORT ena (435:435:435) (462:462:462)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (155:155:155) (211:211:211)) + (PORT datab (375:375:375) (451:451:451)) + (PORT datad (606:606:606) (697:697:697)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (542:542:542) (618:618:618)) + (PORT clrn (855:855:855) (858:858:858)) + (PORT ena (435:435:435) (462:462:462)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT asdata (315:315:315) (361:361:361)) + (PORT clrn (852:852:852) (856:856:856)) + (PORT ena (455:455:455) (491:491:491)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT asdata (473:473:473) (524:524:524)) + (PORT clrn (852:852:852) (856:856:856)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (177:177:177) (219:219:219)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datad (343:343:343) (413:413:413)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (431:431:431)) + (PORT datab (142:142:142) (190:190:190)) + (PORT datad (461:461:461) (539:539:539)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (139:139:139)) + (PORT datab (103:103:103) (133:133:133)) + (PORT datad (345:345:345) (415:415:415)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT datab (447:447:447) (518:518:518)) + (PORT datac (295:295:295) (338:338:338)) + (PORT datad (471:471:471) (534:534:534)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (595:595:595) (689:689:689)) + (PORT datab (640:640:640) (751:751:751)) + (PORT datac (303:303:303) (356:356:356)) + (PORT datad (475:475:475) (558:558:558)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT asdata (958:958:958) (1072:1072:1072)) + (PORT clrn (851:851:851) (855:855:855)) + (PORT ena (801:801:801) (879:879:879)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6\~0) + (DELAY + (ABSOLUTE + (PORT datab (120:120:120) (154:154:154)) + (PORT datad (515:515:515) (609:609:609)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (630:630:630) (697:697:697)) + (PORT clrn (855:855:855) (858:858:858)) + (PORT ena (435:435:435) (462:462:462)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (151:151:151) (209:209:209)) + (PORT datab (216:216:216) (275:275:275)) + (PORT datac (131:131:131) (173:173:173)) + (PORT datad (207:207:207) (252:252:252)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (505:505:505) (603:603:603)) + (PORT datab (148:148:148) (203:203:203)) + (PORT datac (130:130:130) (172:172:172)) + (PORT datad (97:97:97) (118:118:118)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (140:140:140) (187:187:187)) + (PORT datad (438:438:438) (503:503:503)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (807:807:807) (943:943:943)) + (PORT datac (138:138:138) (184:184:184)) + (PORT datad (437:437:437) (502:502:502)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (214:214:214) (262:262:262)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT asdata (627:627:627) (696:696:696)) + (PORT clrn (852:852:852) (856:856:856)) + (PORT ena (455:455:455) (491:491:491)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (334:334:334) (402:402:402)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (194:194:194) (243:243:243)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (455:455:455)) + (PORT datab (364:364:364) (441:441:441)) + (PORT datac (184:184:184) (223:223:223)) + (PORT datad (341:341:341) (411:411:411)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (501:501:501) (585:585:585)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (PORT ena (801:801:801) (879:879:879)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT asdata (678:678:678) (767:767:767)) + (PORT clrn (851:851:851) (855:855:855)) + (PORT ena (801:801:801) (879:879:879)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (805:805:805) (941:941:941)) + (PORT datab (221:221:221) (276:276:276)) + (PORT datac (140:140:140) (187:187:187)) + (PORT datad (437:437:437) (503:503:503)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datac (326:326:326) (394:394:394)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (180:180:180)) + (PORT datab (363:363:363) (442:442:442)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (721:721:721)) + (PORT datab (358:358:358) (432:432:432)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (433:433:433)) + (PORT datab (357:357:357) (440:440:440)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (424:424:424)) + (PORT datab (311:311:311) (371:371:371)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (394:394:394)) + (PORT datab (315:315:315) (380:380:380)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datab (143:143:143) (196:196:196)) + (PORT datac (99:99:99) (126:126:126)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (297:297:297) (363:363:363)) + (PORT datab (313:313:313) (378:378:378)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (257:257:257)) + (PORT datab (300:300:300) (363:363:363)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (107:107:107) (139:139:139)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (137:137:137)) + (PORT datab (104:104:104) (132:132:132)) + (PORT datac (91:91:91) (112:112:112)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT dataa (531:531:531) (629:629:629)) + (PORT datab (367:367:367) (447:447:447)) + (PORT datac (103:103:103) (130:130:130)) + (PORT datad (346:346:346) (413:413:413)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9\~0) + (DELAY + (ABSOLUTE + (PORT datab (110:110:110) (140:140:140)) + (PORT datad (134:134:134) (173:173:173)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (536:536:536) (608:608:608)) + (PORT clrn (855:855:855) (858:858:858)) + (PORT ena (435:435:435) (462:462:462)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT datac (140:140:140) (188:188:188)) + (PORT datad (137:137:137) (183:183:183)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT dataa (152:152:152) (212:212:212)) + (PORT datac (139:139:139) (185:185:185)) + (PORT datad (209:209:209) (255:255:255)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (275:275:275)) + (PORT datad (297:297:297) (356:356:356)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_wr_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (1055:1055:1055)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (104:104:104) (126:126:126)) + (PORT datad (105:105:105) (123:123:123)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_wr_req) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (392:392:392)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (PORT ena (455:455:455) (491:491:491)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (397:397:397)) + (PORT datab (134:134:134) (170:170:170)) + (PORT datad (212:212:212) (259:259:259)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~11) + (DELAY + (ABSOLUTE + (PORT dataa (698:698:698) (815:815:815)) + (PORT datab (700:700:700) (822:822:822)) + (PORT datac (354:354:354) (426:426:426)) + (PORT datad (849:849:849) (983:983:983)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (PORT ena (655:655:655) (712:712:712)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (124:124:124) (163:163:163)) + (PORT datab (154:154:154) (208:208:208)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~10) + (DELAY + (ABSOLUTE + (PORT dataa (358:358:358) (426:426:426)) + (PORT datab (681:681:681) (794:794:794)) + (PORT datac (337:337:337) (401:401:401)) + (PORT datad (317:317:317) (378:378:378)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (PORT ena (655:655:655) (712:712:712)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (204:204:204)) + (PORT datab (126:126:126) (158:158:158)) + (PORT datac (140:140:140) (187:187:187)) + (PORT datad (139:139:139) (181:181:181)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8\~0) + (DELAY + (ABSOLUTE + (PORT datad (312:312:312) (365:365:365)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (890:890:890)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (384:384:384)) + (PORT datad (142:142:142) (185:185:185)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (890:890:890)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (384:384:384)) + (PORT datab (156:156:156) (209:209:209)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (890:890:890)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (872:872:872)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT datab (151:151:151) (204:204:204)) + (PORT datac (135:135:135) (179:179:179)) + (PORT datad (136:136:136) (176:176:176)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (885:885:885) (890:890:890)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (868:868:868) (872:872:872)) + (PORT ena (674:674:674) (741:741:741)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT datab (131:131:131) (179:179:179)) + (PORT datac (117:117:117) (157:157:157)) + (PORT datad (496:496:496) (586:586:586)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|parity6) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (PORT ena (655:655:655) (712:712:712)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (151:151:151) (205:205:205)) + (PORT datab (141:141:141) (177:177:177)) + (PORT datac (302:302:302) (366:366:366)) + (PORT datad (207:207:207) (253:253:253)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (276:276:276)) + (PORT datab (223:223:223) (280:280:280)) + (PORT datac (108:108:108) (137:137:137)) + (PORT datad (142:142:142) (185:185:185)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5\~0) + (DELAY + (ABSOLUTE + (PORT datab (104:104:104) (133:133:133)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (227:227:227)) + (PORT datab (150:150:150) (201:201:201)) + (PORT datad (208:208:208) (256:256:256)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (416:416:416)) + (PORT datab (373:373:373) (452:452:452)) + (PORT datad (139:139:139) (180:180:180)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (161:161:161) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (864:864:864) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (284:284:284)) + (PORT datab (389:389:389) (475:475:475)) + (PORT datac (808:808:808) (927:927:927)) + (PORT datad (323:323:323) (378:378:378)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (144:144:144) (198:198:198)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|rd_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (294:294:294)) + (PORT datab (482:482:482) (573:573:573)) + (PORT datad (104:104:104) (128:128:128)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|rd_en) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (199:199:199)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (207:207:207)) + (PORT datac (133:133:133) (182:182:182)) + (PORT datad (133:133:133) (176:176:176)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (152:152:152) (204:204:204)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[5\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[8\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (147:147:147) (196:196:196)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[9\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (200:200:200)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT datac (360:360:360) (428:428:428)) + (PORT datad (373:373:373) (449:449:449)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (435:435:435)) + (PORT datab (401:401:401) (487:487:487)) + (PORT datac (332:332:332) (391:391:391)) + (PORT datad (357:357:357) (414:414:414)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datab (236:236:236) (294:294:294)) + (PORT datad (179:179:179) (211:211:211)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_CL) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (485:485:485) (564:564:564)) + (PORT datab (147:147:147) (197:197:197)) + (PORT datad (179:179:179) (210:210:210)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_DATA) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (190:190:190)) + (PORT datab (135:135:135) (184:184:184)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (122:122:122) (160:160:160)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|tread_end\~3) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (416:416:416)) + (PORT datab (377:377:377) (440:440:440)) + (PORT datac (146:146:146) (196:196:196)) + (PORT datad (339:339:339) (404:404:404)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_PRE) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT datab (194:194:194) (235:235:235)) + (PORT datad (204:204:204) (248:248:248)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_TRP) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|trp_end\~1) + (DELAY + (ABSOLUTE + (PORT datab (200:200:200) (241:241:241)) + (PORT datac (213:213:213) (266:266:266)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_END) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1058:1058:1058) (1232:1232:1232)) + (PORT datab (135:135:135) (185:185:185)) + (PORT datad (212:212:212) (269:269:269)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (1057:1057:1057) (1231:1231:1231)) + (PORT datab (136:136:136) (187:187:187)) + (PORT datad (123:123:123) (162:162:162)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_ACTIVE) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT datab (212:212:212) (271:271:271)) + (PORT datad (179:179:179) (210:210:210)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_TRCD) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|trcd_end\~1) + (DELAY + (ABSOLUTE + (PORT datab (228:228:228) (284:284:284)) + (PORT datad (180:180:180) (214:214:214)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_READ) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (295:295:295)) + (PORT datab (142:142:142) (190:190:190)) + (PORT datad (121:121:121) (158:158:158)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|tread_end\~2) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (203:203:203)) + (PORT datab (151:151:151) (203:203:203)) + (PORT datac (128:128:128) (176:176:176)) + (PORT datad (128:128:128) (172:172:172)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|tread_end\~4) + (DELAY + (ABSOLUTE + (PORT dataa (186:186:186) (228:228:228)) + (PORT datab (119:119:119) (149:149:149)) + (PORT datac (133:133:133) (177:177:177)) + (PORT datad (134:134:134) (173:173:173)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (PORT datab (144:144:144) (193:193:193)) + (PORT datac (200:200:200) (246:246:246)) + (PORT datad (385:385:385) (465:465:465)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (430:430:430)) + (PORT datab (349:349:349) (410:410:410)) + (PORT datac (161:161:161) (190:190:190)) + (PORT datad (359:359:359) (416:416:416)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~3) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (445:445:445)) + (PORT datab (462:462:462) (533:533:533)) + (PORT datac (105:105:105) (128:128:128)) + (PORT datad (309:309:309) (359:359:359)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (207:207:207)) + (PORT datab (153:153:153) (206:206:206)) + (PORT datac (133:133:133) (182:182:182)) + (PORT datad (133:133:133) (176:176:176)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (192:192:192)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|valid_wrreq\~1) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (134:134:134)) + (PORT datab (335:335:335) (392:392:392)) + (PORT datac (179:179:179) (207:207:207)) + (PORT datad (337:337:337) (394:394:394)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (864:864:864) (868:868:868)) + (PORT ena (671:671:671) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (173:173:173)) + (PORT datab (161:161:161) (215:215:215)) + (PORT datad (379:379:379) (445:445:445)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (112:112:112) (148:148:148)) + (PORT datab (163:163:163) (219:219:219)) + (PORT datad (152:152:152) (194:194:194)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (166:166:166) (219:219:219)) + (PORT datad (102:102:102) (124:124:124)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (292:292:292)) + (PORT datab (150:150:150) (201:201:201)) + (PORT datac (145:145:145) (195:195:195)) + (PORT datad (97:97:97) (118:118:118)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (284:284:284)) + (PORT datab (389:389:389) (475:475:475)) + (PORT datac (322:322:322) (365:365:365)) + (PORT datad (323:323:323) (378:378:378)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (245:245:245) (308:308:308)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (864:864:864) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (244:244:244) (307:307:307)) + (PORT datad (97:97:97) (116:116:116)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (864:864:864) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (248:248:248) (311:311:311)) + (PORT datac (134:134:134) (178:178:178)) + (PORT datad (206:206:206) (252:252:252)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (864:864:864) (868:868:868)) + (PORT ena (671:671:671) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (160:160:160) (218:218:218)) + (PORT datab (164:164:164) (216:216:216)) + (PORT datac (150:150:150) (196:196:196)) + (PORT datad (148:148:148) (192:192:192)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (PORT ena (452:452:452) (491:491:491)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (130:130:130) (178:178:178)) + (PORT datac (117:117:117) (157:157:157)) + (PORT datad (338:338:338) (398:398:398)) + (IOPATH datab combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|parity9) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (864:864:864) (868:868:868)) + (PORT ena (671:671:671) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT datad (379:379:379) (445:445:445)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a0) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (PORT ena (452:452:452) (491:491:491)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (131:131:131) (169:169:169)) + (PORT datab (164:164:164) (219:219:219)) + (PORT datac (214:214:214) (266:266:266)) + (PORT datad (378:378:378) (444:444:444)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (158:158:158) (215:215:215)) + (PORT datab (115:115:115) (148:148:148)) + (PORT datad (222:222:222) (269:269:269)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (149:149:149)) + (PORT datab (166:166:166) (218:218:218)) + (PORT datac (149:149:149) (194:194:194)) + (PORT datad (151:151:151) (195:195:195)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (159:159:159) (215:215:215)) + (PORT datab (146:146:146) (197:197:197)) + (PORT datad (93:93:93) (112:112:112)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (359:359:359) (419:419:419)) + (PORT datad (359:359:359) (427:427:427)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (864:864:864) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT asdata (387:387:387) (435:435:435)) + (PORT clrn (864:864:864) (868:868:868)) + (PORT ena (671:671:671) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT asdata (514:514:514) (571:571:571)) + (PORT clrn (864:864:864) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT asdata (828:828:828) (919:919:919)) + (PORT clrn (864:864:864) (868:868:868)) + (PORT ena (688:688:688) (745:745:745)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (707:707:707)) + (PORT datab (147:147:147) (197:197:197)) + (PORT datad (129:129:129) (166:166:166)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT asdata (310:310:310) (350:350:350)) + (PORT clrn (864:864:864) (868:868:868)) + (PORT ena (671:671:671) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT asdata (516:516:516) (580:580:580)) + (PORT clrn (864:864:864) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8\~0) + (DELAY + (ABSOLUTE + (PORT datab (151:151:151) (203:203:203)) + (PORT datac (357:357:357) (423:423:423)) + (PORT datad (146:146:146) (184:184:184)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8\~1) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (422:422:422)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (864:864:864) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT asdata (399:399:399) (459:459:459)) + (PORT clrn (864:864:864) (868:868:868)) + (PORT ena (671:671:671) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT asdata (505:505:505) (559:559:559)) + (PORT clrn (864:864:864) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (653:653:653)) + (PORT datab (546:546:546) (640:640:640)) + (PORT datad (298:298:298) (353:353:353)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (372:372:372) (430:430:430)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (461:461:461) (532:532:532)) + (PORT datab (139:139:139) (175:175:175)) + (PORT datac (139:139:139) (185:185:185)) + (PORT datad (320:320:320) (363:363:363)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT asdata (542:542:542) (611:611:611)) + (PORT clrn (867:867:867) (871:871:871)) + (PORT ena (499:499:499) (527:527:527)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (865:865:865) (977:977:977)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (202:202:202) (247:247:247)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (PORT ena (499:499:499) (527:527:527)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (718:718:718) (808:808:808)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (804:804:804)) + (PORT datab (313:313:313) (376:376:376)) + (PORT datad (541:541:541) (632:632:632)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (377:377:377) (453:453:453)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (864:864:864) (868:868:868)) + (PORT ena (671:671:671) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (667:667:667) (755:755:755)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT asdata (983:983:983) (1099:1099:1099)) + (PORT clrn (864:864:864) (868:868:868)) + (PORT ena (671:671:671) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (560:560:560) (645:645:645)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (676:676:676) (791:791:791)) + (PORT datab (778:778:778) (902:902:902)) + (PORT datad (120:120:120) (157:157:157)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (695:695:695) (796:796:796)) + (PORT datac (167:167:167) (196:196:196)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (847:847:847) (981:981:981)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (PORT ena (655:655:655) (712:712:712)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (212:212:212) (260:260:260)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (PORT ena (499:499:499) (527:527:527)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (705:705:705) (793:793:793)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdempty_eq_comp_lsb\|data_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (545:545:545) (633:633:633)) + (PORT datad (311:311:311) (372:372:372)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT asdata (533:533:533) (594:594:594)) + (PORT clrn (867:867:867) (871:871:871)) + (PORT ena (499:499:499) (527:527:527)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (862:862:862) (977:977:977)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (637:637:637)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datad (677:677:677) (771:771:771)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT asdata (861:861:861) (967:967:967)) + (PORT clrn (867:867:867) (871:871:871)) + (PORT ena (655:655:655) (712:712:712)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (644:644:644)) + (PORT datab (700:700:700) (822:822:822)) + (PORT datad (120:120:120) (158:158:158)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (354:354:354)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_en_dly) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT asdata (307:307:307) (347:347:347)) + (PORT clrn (2962:2962:2962) (2645:2645:2645)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|valid_wreq) + (DELAY + (ABSOLUTE + (PORT dataa (140:140:140) (195:195:195)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (PORT datab (391:391:391) (462:462:462)) + (IOPATH dataa combout (188:188:188) (196:196:196)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (197:197:197)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (633:633:633) (678:678:678)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Add2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (191:191:191)) + (PORT datab (146:146:146) (199:199:199)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2935:2935:2935) (2627:2627:2627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Add2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Add2\~6) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (187:187:187)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (200:200:200)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (102:102:102) (125:125:125)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2935:2935:2935) (2627:2627:2627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (330:330:330) (399:399:399)) + (PORT datab (135:135:135) (185:185:185)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (138:138:138) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3047:3047:3047) (2733:2733:2733)) + (PORT sclr (391:391:391) (452:452:452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3047:3047:3047) (2733:2733:2733)) + (PORT sclr (391:391:391) (452:452:452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3047:3047:3047) (2733:2733:2733)) + (PORT sclr (391:391:391) (452:452:452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (137:137:137) (188:188:188)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (124:124:124) (163:163:163)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3047:3047:3047) (2733:2733:2733)) + (PORT sclr (391:391:391) (452:452:452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (410:410:410)) + (PORT datab (235:235:235) (293:293:293)) + (PORT datac (207:207:207) (259:259:259)) + (PORT datad (350:350:350) (417:417:417)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (191:191:191)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3047:3047:3047) (2733:2733:2733)) + (PORT sclr (391:391:391) (452:452:452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (192:192:192) (240:240:240)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3047:3047:3047) (2733:2733:2733)) + (PORT sclr (391:391:391) (452:452:452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~3) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (235:235:235)) + (PORT datab (199:199:199) (241:241:241)) + (PORT datac (90:90:90) (111:111:111)) + (PORT datad (200:200:200) (251:251:251)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3047:3047:3047) (2733:2733:2733)) + (PORT sclr (391:391:391) (452:452:452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3047:3047:3047) (2733:2733:2733)) + (PORT sclr (391:391:391) (452:452:452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (3047:3047:3047) (2733:2733:2733)) + (PORT sclr (391:391:391) (452:452:452)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (410:410:410)) + (PORT datab (236:236:236) (294:294:294)) + (PORT datac (208:208:208) (260:260:260)) + (PORT datad (350:350:350) (418:418:418)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (181:181:181) (225:225:225)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (184:184:184) (224:224:224)) + (PORT datad (198:198:198) (250:250:250)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2935:2935:2935) (2627:2627:2627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT datab (115:115:115) (149:149:149)) + (PORT datac (131:131:131) (178:178:178)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2935:2935:2935) (2627:2627:2627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (191:191:191)) + (PORT datab (138:138:138) (189:189:189)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (124:124:124) (164:164:164)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|always5\~1) + (DELAY + (ABSOLUTE + (PORT datac (131:131:131) (178:178:178)) + (PORT datad (103:103:103) (126:126:126)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|rd_en) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2935:2935:2935) (2627:2627:2627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty\~1) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (440:440:440)) + (PORT datab (389:389:389) (462:462:462)) + (PORT datac (380:380:380) (454:454:454)) + (PORT datad (364:364:364) (442:442:442)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty\~0) + (DELAY + (ABSOLUTE + (PORT dataa (144:144:144) (200:200:200)) + (PORT datac (200:200:200) (253:253:253)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty\~2) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (405:405:405)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~4) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (342:342:342)) + (PORT datad (362:362:362) (439:439:439)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (274:274:274)) + (PORT datab (218:218:218) (276:276:276)) + (PORT datac (126:126:126) (172:172:172)) + (PORT datad (363:363:363) (440:440:440)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (882:882:882) (887:887:887)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (633:633:633) (678:678:678)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT asdata (309:309:309) (349:349:349)) + (PORT clrn (864:864:864) (868:868:868)) + (PORT ena (671:671:671) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT asdata (386:386:386) (428:428:428)) + (PORT clrn (864:864:864) (868:868:868)) + (PORT ena (671:671:671) (730:730:730)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (283:283:283)) + (PORT datab (154:154:154) (206:206:206)) + (PORT datac (130:130:130) (172:172:172)) + (PORT datad (213:213:213) (260:260:260)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (465:465:465)) + (PORT datab (408:408:408) (488:488:488)) + (PORT datac (379:379:379) (465:465:465)) + (PORT datad (356:356:356) (419:419:419)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (539:539:539) (631:631:631)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (640:640:640)) + (PORT datac (539:539:539) (631:631:631)) + (PORT datad (99:99:99) (119:119:119)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (883:883:883) (888:888:888)) + (PORT asdata (530:530:530) (600:600:600)) + (PORT clrn (867:867:867) (871:871:871)) + (PORT ena (655:655:655) (712:712:712)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (524:524:524) (608:608:608)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (524:524:524) (610:610:610)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (644:644:644) (744:744:744)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (PORT ena (834:834:834) (919:919:919)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT asdata (311:311:311) (352:352:352)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT asdata (710:710:710) (805:805:805)) + (PORT clrn (864:864:864) (868:868:868)) + (PORT ena (688:688:688) (745:745:745)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT asdata (544:544:544) (616:616:616)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT asdata (803:803:803) (893:893:893)) + (PORT clrn (864:864:864) (868:868:868)) + (PORT ena (688:688:688) (745:745:745)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (359:359:359) (427:427:427)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (362:362:362) (426:426:426)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (262:262:262)) + (PORT datab (134:134:134) (184:184:184)) + (PORT datac (126:126:126) (171:171:171)) + (PORT datad (201:201:201) (248:248:248)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (132:132:132) (184:184:184)) + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (125:125:125) (171:171:171)) + (PORT datad (101:101:101) (122:122:122)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (193:193:193)) + (PORT datab (132:132:132) (181:181:181)) + (PORT datac (126:126:126) (171:171:171)) + (PORT datad (332:332:332) (387:387:387)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT asdata (718:718:718) (804:804:804)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datac (118:118:118) (160:160:160)) + (PORT datad (91:91:91) (107:107:107)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (415:415:415)) + (PORT datab (312:312:312) (378:378:378)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (271:271:271)) + (PORT datab (347:347:347) (420:420:420)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (200:200:200) (257:257:257)) + (PORT datab (356:356:356) (431:431:431)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (167:167:167) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (134:134:134)) + (PORT datab (108:108:108) (139:139:139)) + (PORT datac (94:94:94) (117:117:117)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datab (137:137:137) (188:188:188)) + (PORT datac (125:125:125) (171:171:171)) + (PORT datad (203:203:203) (250:250:250)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (864:864:864) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT datab (136:136:136) (186:186:186)) + (PORT datac (124:124:124) (171:171:171)) + (PORT datad (101:101:101) (123:123:123)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (480:480:480) (568:568:568)) + (PORT datab (353:353:353) (434:434:434)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (426:426:426)) + (PORT datab (369:369:369) (450:450:450)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (456:456:456) (544:544:544)) + (PORT datab (356:356:356) (437:437:437)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (454:454:454)) + (PORT datab (364:364:364) (443:443:443)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (166:166:166) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (357:357:357) (417:417:417)) + (PORT datab (332:332:332) (389:389:389)) + (PORT datac (357:357:357) (421:421:421)) + (PORT datad (335:335:335) (387:387:387)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (141:141:141)) + (PORT datab (397:397:397) (473:473:473)) + (PORT datad (92:92:92) (111:111:111)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_en) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2962:2962:2962) (2645:2645:2645)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT datab (131:131:131) (179:179:179)) + (PORT datac (529:529:529) (630:630:630)) + (PORT datad (515:515:515) (610:610:610)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (150:150:150) (205:205:205)) + (PORT datab (140:140:140) (175:175:175)) + (PORT datac (305:305:305) (369:369:369)) + (PORT datad (209:209:209) (256:256:256)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (93:93:93) (110:110:110)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (162:162:162)) + (PORT datad (142:142:142) (186:186:186)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (278:278:278)) + (PORT datab (223:223:223) (280:280:280)) + (PORT datac (104:104:104) (132:132:132)) + (PORT datad (145:145:145) (188:188:188)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6\~0) + (DELAY + (ABSOLUTE + (PORT datab (125:125:125) (157:157:157)) + (PORT datad (208:208:208) (256:256:256)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (388:388:388) (460:460:460)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (864:864:864) (868:868:868)) + (PORT ena (688:688:688) (745:745:745)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT asdata (546:546:546) (613:613:613)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datac (129:129:129) (176:176:176)) + (PORT datad (97:97:97) (119:119:119)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (105:105:105) (135:135:135)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (286:286:286)) + (PORT datad (136:136:136) (179:179:179)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (880:880:880) (885:885:885)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (864:864:864) (868:868:868)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (437:437:437)) + (PORT datad (352:352:352) (425:425:425)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (135:135:135)) + (PORT datab (773:773:773) (880:880:880)) + (PORT datac (751:751:751) (846:846:846)) + (PORT datad (106:106:106) (124:124:124)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (751:751:751) (854:854:854)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (104:104:104) (127:127:127)) + (PORT datad (90:90:90) (108:108:108)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (666:666:666) (787:787:787)) + (PORT datab (361:361:361) (438:438:438)) + (PORT datac (465:465:465) (549:549:549)) + (PORT datad (133:133:133) (172:172:172)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (223:223:223) (291:291:291)) + (PORT datad (136:136:136) (176:176:176)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (119:119:119) (155:155:155)) + (PORT datab (484:484:484) (575:575:575)) + (PORT datac (616:616:616) (715:715:715)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.READ) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~7) + (DELAY + (ABSOLUTE + (PORT datab (240:240:240) (299:299:299)) + (PORT datac (194:194:194) (239:239:239)) + (PORT datad (209:209:209) (259:259:259)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (260:260:260)) + (PORT datab (155:155:155) (209:209:209)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_DATA) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|twrite_end\~0) + (DELAY + (ABSOLUTE + (PORT dataa (151:151:151) (210:210:210)) + (PORT datab (150:150:150) (205:205:205)) + (PORT datac (134:134:134) (183:183:183)) + (PORT datad (134:134:134) (178:178:178)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|twrite_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (210:210:210) (262:262:262)) + (PORT datab (132:132:132) (167:167:167)) + (PORT datac (159:159:159) (215:215:215)) + (PORT datad (291:291:291) (335:335:335)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_PRE) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (154:154:154)) + (PORT datad (207:207:207) (256:256:256)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_TRP) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|trp_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (263:263:263)) + (PORT datab (140:140:140) (193:193:193)) + (PORT datac (117:117:117) (145:145:145)) + (PORT datad (182:182:182) (216:216:216)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_END) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (614:614:614)) + (PORT datab (634:634:634) (735:735:735)) + (PORT datad (104:104:104) (127:127:127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.WRITE) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (228:228:228) (297:297:297)) + (PORT datab (145:145:145) (196:196:196)) + (PORT datac (492:492:492) (586:586:586)) + (PORT datad (132:132:132) (170:170:170)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (319:319:319) (379:379:379)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (90:90:90) (112:112:112)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.ARBIT) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT datab (490:490:490) (592:592:592)) + (PORT datac (134:134:134) (178:178:178)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (510:510:510) (602:602:602)) + (PORT datab (154:154:154) (212:212:212)) + (PORT datad (222:222:222) (275:275:275)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\~4) + (DELAY + (ABSOLUTE + (PORT datad (219:219:219) (276:276:276)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\~2) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (305:305:305)) + (PORT datad (127:127:127) (169:169:169)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (PORT ena (423:423:423) (455:455:455)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\~15) + (DELAY + (ABSOLUTE + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (124:124:124) (165:165:165)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (117:117:117) (154:154:154)) + (PORT datad (213:213:213) (262:262:262)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_TRP) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\~1) + (DELAY + (ABSOLUTE + (PORT datab (111:111:111) (142:142:142)) + (PORT datad (136:136:136) (182:182:182)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT datab (149:149:149) (203:203:203)) + (PORT datac (125:125:125) (172:172:172)) + (PORT datad (205:205:205) (257:257:257)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (242:242:242) (305:305:305)) + (PORT datab (135:135:135) (186:186:186)) + (PORT datac (101:101:101) (128:128:128)) + (PORT datad (131:131:131) (168:168:168)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (160:160:160)) + (PORT datab (144:144:144) (197:197:197)) + (PORT datad (97:97:97) (116:116:116)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\~0) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (288:288:288)) + (PORT datab (106:106:106) (137:137:137)) + (PORT datad (135:135:135) (180:180:180)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (285:285:285)) + (PORT datab (149:149:149) (204:204:204)) + (PORT datac (127:127:127) (174:174:174)) + (PORT datad (131:131:131) (174:174:174)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (133:133:133) (176:176:176)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_TRF) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\~2) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (159:159:159)) + (PORT datab (144:144:144) (197:197:197)) + (PORT datad (95:95:95) (115:115:115)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|trc_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (283:283:283)) + (PORT datab (149:149:149) (205:205:205)) + (PORT datac (128:128:128) (175:175:175)) + (PORT datad (131:131:131) (175:175:175)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (114:114:114) (149:149:149)) + (PORT datab (107:107:107) (136:136:136)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (108:108:108) (134:134:134)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AUTO_REF) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (243:243:243) (305:305:305)) + (PORT datac (135:135:135) (180:180:180)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (PORT ena (423:423:423) (455:455:455)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\~17) + (DELAY + (ABSOLUTE + (PORT dataa (122:122:122) (160:160:160)) + (PORT datab (142:142:142) (194:194:194)) + (PORT datac (122:122:122) (165:165:165)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_END) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|aref_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (491:491:491) (592:592:592)) + (PORT datac (135:135:135) (179:179:179)) + (PORT datad (219:219:219) (272:272:272)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.AREF) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (862:862:862)) + (PORT ena (408:408:408) (428:428:428)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\~3) + (DELAY + (ABSOLUTE + (PORT datad (99:99:99) (122:122:122)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (853:853:853) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\~2) + (DELAY + (ABSOLUTE + (PORT datab (170:170:170) (228:228:228)) + (PORT datad (103:103:103) (126:126:126)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (853:853:853) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT datab (152:152:152) (204:204:204)) + (PORT datac (150:150:150) (202:202:202)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (486:486:486) (578:578:578)) + (PORT datab (166:166:166) (222:222:222)) + (PORT datad (100:100:100) (122:122:122)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_TRP) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (853:853:853) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (194:194:194)) + (PORT datab (168:168:168) (226:226:226)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (99:99:99) (120:120:120)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (417:417:417)) + (PORT datad (133:133:133) (172:172:172)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (869:869:869)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (424:424:424)) + (PORT datab (354:354:354) (420:420:420)) + (PORT datac (321:321:321) (378:378:378)) + (PORT datad (352:352:352) (416:416:416)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\~0) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (378:378:378)) + (PORT datab (104:104:104) (133:133:133)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (96:96:96) (116:116:116)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (189:189:189)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (869:869:869)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (869:869:869)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (869:869:869)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (869:869:869)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (869:869:869)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (869:869:869)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~20) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (869:869:869)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~22) + (DELAY + (ABSOLUTE + (PORT dataa (137:137:137) (188:188:188)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~24) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (184:184:184)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (869:869:869)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~28) + (DELAY + (ABSOLUTE + (PORT datad (191:191:191) (238:238:238)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (869:869:869)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (878:878:878) (886:886:886)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (862:862:862) (869:869:869)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (188:188:188)) + (PORT datab (204:204:204) (260:260:260)) + (PORT datac (121:121:121) (164:164:164)) + (PORT datad (121:121:121) (160:160:160)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (403:403:403)) + (PORT datab (346:346:346) (418:418:418)) + (PORT datac (333:333:333) (391:391:391)) + (PORT datad (339:339:339) (400:400:400)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (398:398:398)) + (PORT datac (296:296:296) (337:337:337)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (422:422:422)) + (PORT datab (351:351:351) (417:417:417)) + (PORT datac (317:317:317) (374:374:374)) + (PORT datad (354:354:354) (418:418:418)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (420:420:420)) + (PORT datab (110:110:110) (141:141:141)) + (PORT datac (175:175:175) (209:209:209)) + (PORT datad (134:134:134) (173:173:173)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_IDLE\~0) + (DELAY + (ABSOLUTE + (PORT datad (96:96:96) (115:115:115)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (155:155:155) (203:203:203)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (502:502:502) (588:588:588)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\~4) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (275:275:275)) + (PORT datab (114:114:114) (147:147:147)) + (PORT datad (139:139:139) (181:181:181)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (853:853:853) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT datab (169:169:169) (227:227:227)) + (PORT datad (137:137:137) (178:178:178)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_END\~0) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (192:192:192)) + (PORT datab (166:166:166) (226:226:226)) + (PORT datad (188:188:188) (219:219:219)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_END) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (853:853:853) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (144:144:144) (196:196:196)) + (PORT datab (154:154:154) (210:210:210)) + (PORT datac (492:492:492) (575:575:575)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_PCHA) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (232:232:232) (287:287:287)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (233:233:233) (290:290:290)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (268:268:268)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (211:211:211) (263:263:263)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~4) + (DELAY + (ABSOLUTE + (PORT datac (174:174:174) (210:210:210)) + (PORT datad (127:127:127) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (641:641:641) (741:741:741)) + (PORT datad (133:133:133) (162:162:162)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (PORT ena (407:407:407) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (148:148:148) (199:199:199)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (257:257:257)) + (PORT datab (564:564:564) (664:664:664)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (148:148:148) (199:199:199)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[6\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (257:257:257)) + (PORT datab (564:564:564) (665:665:665)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (201:201:201)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[7\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (218:218:218) (262:262:262)) + (PORT datab (561:561:561) (662:662:662)) + (PORT datad (91:91:91) (108:108:108)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~0) + (DELAY + (ABSOLUTE + (PORT datac (175:175:175) (211:211:211)) + (PORT datad (131:131:131) (160:160:160)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (PORT ena (407:407:407) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~7) + (DELAY + (ABSOLUTE + (PORT datac (176:176:176) (213:213:213)) + (PORT datad (133:133:133) (162:162:162)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (PORT ena (407:407:407) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~8) + (DELAY + (ABSOLUTE + (PORT datab (143:143:143) (181:181:181)) + (PORT datad (163:163:163) (192:192:192)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (PORT ena (407:407:407) (424:424:424)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (148:148:148) (201:201:201)) + (PORT datab (147:147:147) (197:197:197)) + (PORT datac (128:128:128) (169:169:169)) + (PORT datad (130:130:130) (167:167:167)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (201:201:201)) + (PORT datab (232:232:232) (289:289:289)) + (PORT datac (92:92:92) (114:114:114)) + (PORT datad (210:210:210) (259:259:259)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|LessThan0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (215:215:215) (274:274:274)) + (PORT datab (146:146:146) (196:196:196)) + (PORT datac (213:213:213) (266:266:266)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (211:211:211) (265:265:265)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[8\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (766:766:766)) + (PORT datab (141:141:141) (178:178:178)) + (PORT datad (174:174:174) (205:205:205)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (137:137:137) (178:178:178)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[9\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (213:213:213) (257:257:257)) + (PORT datab (564:564:564) (665:665:665)) + (PORT datad (93:93:93) (111:111:111)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (883:883:883)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (863:863:863) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (231:231:231) (287:287:287)) + (PORT datab (150:150:150) (201:201:201)) + (PORT datac (132:132:132) (176:176:176)) + (PORT datad (211:211:211) (260:260:260)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (102:102:102) (131:131:131)) + (PORT datac (136:136:136) (181:181:181)) + (PORT datad (138:138:138) (178:178:178)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (451:451:451) (529:529:529)) + (PORT datab (144:144:144) (193:193:193)) + (PORT datad (435:435:435) (497:497:497)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_req) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datac (346:346:346) (416:416:416)) + (PORT datad (133:133:133) (173:173:173)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|wr_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (511:511:511) (614:614:614)) + (PORT datab (634:634:634) (735:735:735)) + (PORT datad (104:104:104) (127:127:127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|wr_en) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (610:610:610)) + (PORT datab (139:139:139) (191:191:191)) + (PORT datad (1045:1045:1045) (1207:1207:1207)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector4\~1) + (DELAY + (ABSOLUTE + (PORT datab (236:236:236) (294:294:294)) + (PORT datac (370:370:370) (435:435:435)) + (PORT datad (201:201:201) (247:247:247)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (124:124:124) (159:159:159)) + (PORT datab (143:143:143) (196:196:196)) + (PORT datac (91:91:91) (114:114:114)) + (PORT datad (198:198:198) (243:243:243)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (440:440:440)) + (PORT datab (186:186:186) (224:224:224)) + (PORT datac (89:89:89) (111:111:111)) + (PORT datad (159:159:159) (185:185:185)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (194:194:194)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (143:143:143) (198:198:198)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[8\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (191:191:191)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[9\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (PORT sclr (319:319:319) (370:370:370)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~5) + (DELAY + (ABSOLUTE + (PORT datab (238:238:238) (298:298:298)) + (PORT datad (209:209:209) (258:258:258)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (408:408:408)) + (PORT datad (325:325:325) (373:373:373)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_TRCD) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|trcd_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (211:211:211) (263:263:263)) + (PORT datab (132:132:132) (167:167:167)) + (PORT datac (212:212:212) (269:269:269)) + (PORT datad (181:181:181) (216:216:216)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_WRITE) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_ack\~2) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (208:208:208)) + (PORT datab (148:148:148) (203:203:203)) + (PORT datac (132:132:132) (181:181:181)) + (PORT datad (132:132:132) (176:176:176)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_ack\~3) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (263:263:263)) + (PORT datab (130:130:130) (164:164:164)) + (PORT datac (153:153:153) (208:208:208)) + (PORT datad (173:173:173) (205:205:205)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (628:628:628)) + (PORT datab (144:144:144) (192:192:192)) + (PORT datac (129:129:129) (171:171:171)) + (PORT datad (496:496:496) (584:584:584)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (504:504:504) (593:593:593)) + (PORT datab (612:612:612) (728:728:728)) + (PORT datac (433:433:433) (505:505:505)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (169:169:169) (225:225:225)) + (PORT datab (111:111:111) (144:144:144)) + (PORT datad (507:507:507) (598:598:598)) + (IOPATH dataa combout (188:188:188) (203:203:203)) + (IOPATH datab combout (190:190:190) (205:205:205)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~12) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (630:630:630)) + (PORT datab (367:367:367) (447:447:447)) + (PORT datac (479:479:479) (559:559:559)) + (PORT datad (346:346:346) (412:412:412)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (PORT ena (694:694:694) (759:759:759)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~11) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (457:457:457)) + (PORT datab (489:489:489) (580:580:580)) + (PORT datac (494:494:494) (582:582:582)) + (IOPATH dataa combout (195:195:195) (193:193:193)) + (IOPATH datab combout (196:196:196) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (PORT ena (435:435:435) (462:462:462)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~10) + (DELAY + (ABSOLUTE + (PORT dataa (134:134:134) (185:185:185)) + (PORT datac (116:116:116) (157:157:157)) + (PORT datad (350:350:350) (423:423:423)) + (IOPATH dataa combout (188:188:188) (193:193:193)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|parity6) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (PORT ena (694:694:694) (759:759:759)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (410:410:410)) + (PORT datab (163:163:163) (215:215:215)) + (PORT datac (140:140:140) (187:187:187)) + (PORT datad (380:380:380) (447:447:447)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (91:91:91) (109:109:109)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (147:147:147) (197:197:197)) + (PORT datac (471:471:471) (546:546:546)) + (PORT datad (379:379:379) (446:446:446)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (631:631:631)) + (PORT datab (118:118:118) (151:151:151)) + (PORT datad (345:345:345) (412:412:412)) + (IOPATH dataa combout (159:159:159) (173:173:173)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (636:636:636)) + (PORT datab (364:364:364) (444:444:444)) + (PORT datac (103:103:103) (132:132:132)) + (PORT datad (342:342:342) (408:408:408)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8\~0) + (DELAY + (ABSOLUTE + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10\~0) + (DELAY + (ABSOLUTE + (PORT datab (147:147:147) (198:198:198)) + (PORT datad (93:93:93) (113:113:113)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (876:876:876)) + (PORT asdata (649:649:649) (736:736:736)) + (PORT clrn (855:855:855) (858:858:858)) + (PORT ena (435:435:435) (462:462:462)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (469:469:469)) + (PORT datab (356:356:356) (430:430:430)) + (PORT datad (209:209:209) (255:255:255)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH datab combout (191:191:191) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (431:431:431) (502:502:502)) + (PORT datab (133:133:133) (168:168:168)) + (PORT datac (133:133:133) (183:183:183)) + (PORT datad (319:319:319) (370:370:370)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (141:141:141) (177:177:177)) + (PORT datac (165:165:165) (194:194:194)) + (PORT datad (370:370:370) (444:444:444)) + (IOPATH dataa combout (188:188:188) (184:184:184)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (868:868:868) (873:873:873)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (852:852:852) (856:856:856)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (180:180:180)) + (PORT datad (120:120:120) (157:157:157)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1120:1120:1120) (1119:1119:1119)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1120:1120:1120) (1119:1119:1119)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rx\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (348:348:348) (728:728:728)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg1\~0) + (DELAY + (ABSOLUTE + (PORT datad (1944:1944:1944) (2173:2173:2173)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg1) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (118:118:118) (154:154:154)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg2) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (160:160:160)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg3) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (348:348:348) (419:419:419)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (139:139:139)) + (PORT datab (150:150:150) (206:206:206)) + (PORT datad (104:104:104) (129:129:129)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (882:882:882)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (865:865:865)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always8\~0) + (DELAY + (ABSOLUTE + (PORT datab (120:120:120) (155:155:155)) + (PORT datac (137:137:137) (186:186:186)) + (PORT datad (132:132:132) (177:177:177)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (790:790:790) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT asdata (299:299:299) (340:340:340)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (790:790:790) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (159:159:159)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (790:790:790) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (123:123:123) (162:162:162)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (790:790:790) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (160:160:160)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (790:790:790) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (125:125:125) (164:164:164)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (790:790:790) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (125:125:125) (164:164:164)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (790:790:790) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (124:124:124) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (790:790:790) (866:866:866)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (119:119:119) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (795:795:795) (881:881:881)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|ram_address_a\[9\]) + (DELAY + (ABSOLUTE + (PORT datad (134:134:134) (174:174:174)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (510:510:510) (599:599:599)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datab (488:488:488) (579:579:579)) + (PORT datac (357:357:357) (430:430:430)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (160:160:160)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (795:795:795) (881:881:881)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (123:123:123) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (795:795:795) (881:881:881)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (125:125:125) (165:165:165)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (795:795:795) (881:881:881)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (123:123:123) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (795:795:795) (881:881:881)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (121:121:121) (160:160:160)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (795:795:795) (881:881:881)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (123:123:123) (162:162:162)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (795:795:795) (881:881:881)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT asdata (299:299:299) (341:341:341)) + (PORT clrn (856:856:856) (859:859:859)) + (PORT ena (795:795:795) (881:881:881)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (396:396:396) (471:471:471)) + (PORT d[1] (413:413:413) (494:494:494)) + (PORT d[2] (401:401:401) (468:468:468)) + (PORT d[3] (393:393:393) (466:466:466)) + (PORT d[4] (401:401:401) (477:477:477)) + (PORT d[5] (404:404:404) (480:480:480)) + (PORT d[6] (401:401:401) (468:468:468)) + (PORT d[7] (390:390:390) (464:464:464)) + (PORT d[8] (238:238:238) (279:279:279)) + (PORT clk (1057:1057:1057) (1074:1074:1074)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (556:556:556) (659:659:659)) + (PORT d[1] (669:669:669) (792:792:792)) + (PORT d[2] (578:578:578) (680:680:680)) + (PORT d[3] (725:725:725) (849:849:849)) + (PORT d[4] (547:547:547) (640:640:640)) + (PORT d[5] (574:574:574) (683:683:683)) + (PORT d[6] (702:702:702) (823:823:823)) + (PORT d[7] (535:535:535) (632:632:632)) + (PORT d[8] (567:567:567) (675:675:675)) + (PORT d[9] (482:482:482) (556:556:556)) + (PORT clk (1055:1055:1055) (1072:1072:1072)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1018:1018:1018) (1115:1115:1115)) + (PORT clk (1055:1055:1055) (1072:1072:1072)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1057:1057:1057) (1074:1074:1074)) + (PORT d[0] (1302:1302:1302) (1408:1408:1408)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1058:1058:1058) (1075:1075:1075)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (522:522:522) (600:600:600)) + (PORT d[1] (653:653:653) (768:768:768)) + (PORT d[2] (725:725:725) (844:844:844)) + (PORT d[3] (574:574:574) (670:670:670)) + (PORT d[4] (702:702:702) (817:817:817)) + (PORT d[5] (441:441:441) (522:522:522)) + (PORT d[6] (536:536:536) (625:625:625)) + (PORT d[7] (526:526:526) (622:622:622)) + (PORT d[8] (568:568:568) (669:669:669)) + (PORT d[9] (484:484:484) (553:553:553)) + (PORT clk (1014:1014:1014) (1033:1033:1033)) + (PORT aclr (1040:1040:1040) (1045:1045:1045)) + (PORT stall (801:801:801) (757:757:757)) + (IOPATH (posedge aclr) q (152:152:152) (152:152:152)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + (HOLD stall (posedge clk) (104:104:104)) + (HOLD aclr (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1014:1014:1014) (1033:1033:1033)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1034:1034:1034)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1034:1034:1034)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1015:1015:1015) (1034:1034:1034)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1013:1013:1013) (1032:1032:1032)) + (PORT ena (881:881:881) (933:933:933)) + (PORT aclr (1014:1014:1014) (1045:1045:1045)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + (IOPATH (posedge aclr) q (184:184:184) (186:186:186)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (SETUP ena (posedge clk) (25:25:25)) + (SETUP aclr (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + (HOLD ena (posedge clk) (90:90:90)) + (HOLD aclr (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_ack) + (DELAY + (ABSOLUTE + (PORT datac (434:434:434) (506:506:506)) + (PORT datad (599:599:599) (705:705:705)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_sdram_en) + (DELAY + (ABSOLUTE + (PORT clk (867:867:867) (872:872:872)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (851:851:851) (855:855:855)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (479:479:479) (558:558:558)) + (PORT d[1] (479:479:479) (558:558:558)) + (PORT d[2] (479:479:479) (558:558:558)) + (PORT d[3] (479:479:479) (558:558:558)) + (PORT d[4] (472:472:472) (550:550:550)) + (PORT d[5] (472:472:472) (550:550:550)) + (PORT d[6] (472:472:472) (550:550:550)) + (PORT clk (1051:1051:1051) (1069:1069:1069)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (803:803:803) (944:944:944)) + (PORT d[1] (420:420:420) (505:505:505)) + (PORT d[2] (1013:1013:1013) (1178:1178:1178)) + (PORT d[3] (565:565:565) (668:668:668)) + (PORT d[4] (421:421:421) (498:498:498)) + (PORT d[5] (454:454:454) (530:530:530)) + (PORT d[6] (686:686:686) (806:806:806)) + (PORT d[7] (802:802:802) (930:930:930)) + (PORT d[8] (708:708:708) (832:832:832)) + (PORT d[9] (328:328:328) (377:377:377)) + (PORT clk (1049:1049:1049) (1067:1067:1067)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1164:1164:1164) (1275:1275:1275)) + (PORT clk (1049:1049:1049) (1067:1067:1067)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1051:1051:1051) (1069:1069:1069)) + (PORT d[0] (1448:1448:1448) (1568:1568:1568)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1052:1052:1052) (1070:1070:1070)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (389:389:389) (455:455:455)) + (PORT d[1] (651:651:651) (767:767:767)) + (PORT d[2] (719:719:719) (837:837:837)) + (PORT d[3] (442:442:442) (528:528:528)) + (PORT d[4] (414:414:414) (495:495:495)) + (PORT d[5] (411:411:411) (484:484:484)) + (PORT d[6] (408:408:408) (485:485:485)) + (PORT d[7] (544:544:544) (641:641:641)) + (PORT d[8] (703:703:703) (821:821:821)) + (PORT d[9] (774:774:774) (884:884:884)) + (PORT clk (1008:1008:1008) (1028:1028:1028)) + (PORT aclr (1034:1034:1034) (1040:1040:1040)) + (PORT stall (951:951:951) (891:891:891)) + (IOPATH (posedge aclr) q (152:152:152) (152:152:152)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + (HOLD stall (posedge clk) (104:104:104)) + (HOLD aclr (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1008:1008:1008) (1028:1028:1028)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1009:1009:1009) (1029:1029:1029)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1009:1009:1009) (1029:1029:1029)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1009:1009:1009) (1029:1029:1029)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1007:1007:1007) (1027:1027:1027)) + (PORT ena (855:855:855) (904:904:904)) + (PORT aclr (1008:1008:1008) (1040:1040:1040)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + (IOPATH (posedge aclr) q (184:184:184) (186:186:186)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (SETUP ena (posedge clk) (25:25:25)) + (SETUP aclr (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + (HOLD ena (posedge clk) (90:90:90)) + (HOLD aclr (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sys_clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (97:97:97) (82:82:82)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (339:339:339) (413:413:413)) + (PORT datab (135:135:135) (185:185:185)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab combout (190:190:190) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2551:2551:2551) (2299:2299:2299)) + (PORT sclr (545:545:545) (627:627:627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (136:136:136) (189:189:189)) + (PORT datab (136:136:136) (185:185:185)) + (PORT datac (120:120:120) (163:163:163)) + (PORT datad (123:123:123) (163:163:163)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2551:2551:2551) (2299:2299:2299)) + (PORT sclr (545:545:545) (627:627:627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (377:377:377) (453:453:453)) + (PORT datab (377:377:377) (450:450:450)) + (PORT datac (320:320:320) (369:369:369)) + (PORT datad (373:373:373) (445:445:445)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (139:139:139) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2551:2551:2551) (2299:2299:2299)) + (PORT sclr (545:545:545) (627:627:627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (199:199:199)) + (PORT datab (140:140:140) (192:192:192)) + (PORT datac (128:128:128) (173:173:173)) + (PORT datad (129:129:129) (170:170:170)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|tx_flag) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT asdata (387:387:387) (443:443:443)) + (PORT clrn (2935:2935:2935) (2627:2627:2627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (452:452:452)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (190:190:190) (195:195:195)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (168:168:168) (234:234:234)) + (PORT datab (114:114:114) (146:146:146)) + (PORT datad (118:118:118) (142:142:142)) + (IOPATH dataa combout (192:192:192) (184:184:184)) + (IOPATH datab combout (182:182:182) (193:193:193)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2554:2554:2554) (2301:2301:2301)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (328:328:328)) + (PORT datab (116:116:116) (149:149:149)) + (PORT datad (114:114:114) (137:137:137)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2554:2554:2554) (2301:2301:2301)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (166:166:166) (229:229:229)) + (PORT datab (170:170:170) (227:227:227)) + (PORT datac (131:131:131) (179:179:179)) + (PORT datad (98:98:98) (119:119:119)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (547:547:547) (651:651:651)) + (PORT datad (512:512:512) (587:587:587)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (891:891:891)) + (PORT asdata (2151:2151:2151) (2399:2399:2399)) + (PORT clrn (2554:2554:2554) (2301:2301:2301)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (104:104:104) (135:135:135)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (555:555:555) (626:626:626)) + (PORT datad (460:460:460) (537:537:537)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2551:2551:2551) (2299:2299:2299)) + (PORT sclr (545:545:545) (627:627:627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (140:140:140) (192:192:192)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2551:2551:2551) (2299:2299:2299)) + (PORT sclr (545:545:545) (627:627:627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (185:185:185)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2551:2551:2551) (2299:2299:2299)) + (PORT sclr (545:545:545) (627:627:627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (139:139:139) (192:192:192)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2551:2551:2551) (2299:2299:2299)) + (PORT sclr (545:545:545) (627:627:627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (134:134:134) (184:184:184)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2551:2551:2551) (2299:2299:2299)) + (PORT sclr (545:545:545) (627:627:627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2551:2551:2551) (2299:2299:2299)) + (PORT sclr (545:545:545) (627:627:627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2551:2551:2551) (2299:2299:2299)) + (PORT sclr (545:545:545) (627:627:627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (128:128:128) (166:166:166)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (892:892:892)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2551:2551:2551) (2299:2299:2299)) + (PORT sclr (545:545:545) (627:627:627)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD sclr (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (197:197:197)) + (PORT datab (141:141:141) (193:193:193)) + (PORT datac (125:125:125) (170:170:170)) + (PORT datad (125:125:125) (167:167:167)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (245:245:245)) + (PORT datab (374:374:374) (451:451:451)) + (PORT datac (314:314:314) (360:360:360)) + (PORT datad (376:376:376) (452:452:452)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (891:891:891) (896:896:896)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2512:2512:2512) (2252:2252:2252)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (135:135:135) (187:187:187)) + (PORT datac (356:356:356) (424:424:424)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|valid_rreq) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (196:196:196)) + (PORT datad (361:361:361) (438:438:438)) + (IOPATH dataa combout (166:166:166) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (328:328:328) (707:707:707)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT asdata (2160:2160:2160) (2435:2435:2435)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_ack\~2) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (478:478:478)) + (PORT datab (348:348:348) (415:415:415)) + (PORT datac (325:325:325) (375:375:375)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT datad (333:333:333) (388:388:388)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (850:850:850) (984:984:984)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datab (145:145:145) (195:195:195)) + (PORT datac (132:132:132) (175:175:175)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (328:328:328) (707:707:707)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT asdata (2132:2132:2132) (2408:2408:2408)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT datad (329:329:329) (384:384:384)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (288:288:288) (667:667:667)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT asdata (2107:2107:2107) (2373:2373:2373)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datad (328:328:328) (382:382:382)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (697:697:697)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT asdata (2013:2013:2013) (2214:2214:2214)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT datad (335:335:335) (389:389:389)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (328:328:328) (707:707:707)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT asdata (2021:2021:2021) (2229:2229:2229)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[4\]\~1) + (DELAY + (ABSOLUTE + (PORT datad (327:327:327) (382:382:382)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (308:308:308) (687:687:687)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT asdata (2162:2162:2162) (2423:2423:2423)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (330:330:330) (385:385:385)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (338:338:338) (717:717:717)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT asdata (2221:2221:2221) (2482:2482:2482)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[6\]\~3) + (DELAY + (ABSOLUTE + (PORT datad (334:334:334) (389:389:389)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (328:328:328) (707:707:707)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (884:884:884) (888:888:888)) + (PORT asdata (2100:2100:2100) (2364:2364:2364)) + (PORT clrn (867:867:867) (871:871:871)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT datad (328:328:328) (383:383:383)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (379:379:379) (431:431:431)) + (PORT d[1] (352:352:352) (399:399:399)) + (PORT d[2] (351:351:351) (399:399:399)) + (PORT d[3] (377:377:377) (429:429:429)) + (PORT d[4] (358:358:358) (408:408:408)) + (PORT d[5] (352:352:352) (399:399:399)) + (PORT d[6] (357:357:357) (405:405:405)) + (PORT d[7] (367:367:367) (417:417:417)) + (PORT clk (1068:1068:1068) (1086:1086:1086)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (418:418:418) (487:487:487)) + (PORT d[1] (401:401:401) (475:475:475)) + (PORT d[2] (391:391:391) (466:466:466)) + (PORT d[3] (741:741:741) (860:860:860)) + (PORT d[4] (385:385:385) (463:463:463)) + (PORT d[5] (719:719:719) (846:846:846)) + (PORT d[6] (688:688:688) (794:794:794)) + (PORT d[7] (405:405:405) (483:483:483)) + (PORT d[8] (424:424:424) (505:505:505)) + (PORT d[9] (367:367:367) (428:428:428)) + (PORT clk (1066:1066:1066) (1084:1084:1084)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (539:539:539) (551:551:551)) + (PORT clk (1066:1066:1066) (1084:1084:1084)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (1068:1068:1068) (1086:1086:1086)) + (PORT d[0] (823:823:823) (844:844:844)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1069:1069:1069) (1087:1087:1087)) + (IOPATH (posedge clk) pulse (0:0:0) (987:987:987)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1069:1069:1069) (1087:1087:1087)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1069:1069:1069) (1087:1087:1087)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (1069:1069:1069) (1087:1087:1087)) + (IOPATH (posedge clk) pulse (0:0:0) (1207:1207:1207)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (204:204:204) (237:237:237)) + (PORT d[1] (396:396:396) (465:465:465)) + (PORT d[2] (752:752:752) (872:872:872)) + (PORT d[3] (835:835:835) (958:958:958)) + (PORT d[4] (809:809:809) (931:931:931)) + (PORT d[5] (824:824:824) (946:946:946)) + (PORT d[6] (415:415:415) (488:488:488)) + (PORT d[7] (432:432:432) (510:510:510)) + (PORT d[8] (693:693:693) (800:800:800)) + (PORT d[9] (373:373:373) (425:425:425)) + (PORT clk (1025:1025:1025) (1045:1045:1045)) + (PORT aclr (1051:1051:1051) (1056:1056:1056)) + (PORT stall (630:630:630) (606:606:606)) + (IOPATH (posedge aclr) q (152:152:152) (152:152:152)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (104:104:104)) + (HOLD stall (posedge clk) (104:104:104)) + (HOLD aclr (posedge clk) (104:104:104)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (1025:1025:1025) (1045:1045:1045)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1026:1026:1026) (1046:1046:1046)) + (IOPATH (posedge clk) pulse (0:0:0) (1120:1120:1120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1026:1026:1026) (1046:1046:1046)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (1026:1026:1026) (1046:1046:1046)) + (IOPATH (posedge clk) pulse (0:0:0) (1222:1222:1222)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (1024:1024:1024) (1044:1044:1044)) + (PORT ena (729:729:729) (759:759:759)) + (PORT aclr (1025:1025:1025) (1056:1056:1056)) + (IOPATH (posedge clk) q (164:164:164) (166:166:166)) + (IOPATH (posedge aclr) q (184:184:184) (186:186:186)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (25:25:25)) + (SETUP ena (posedge clk) (25:25:25)) + (SETUP aclr (posedge clk) (25:25:25)) + (HOLD d (posedge clk) (90:90:90)) + (HOLD ena (posedge clk) (90:90:90)) + (HOLD aclr (posedge clk) (90:90:90)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1120:1120:1120) (1226:1226:1226)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita1) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1120:1120:1120) (1226:1226:1226)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita2) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1120:1120:1120) (1226:1226:1226)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita3) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1120:1120:1120) (1226:1226:1226)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita4) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1120:1120:1120) (1226:1226:1226)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita5) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1120:1120:1120) (1226:1226:1226)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita6) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1120:1120:1120) (1226:1226:1226)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita7) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1120:1120:1120) (1226:1226:1226)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita8) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1120:1120:1120) (1226:1226:1226)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita9) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (876:876:876) (880:880:880)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (1120:1120:1120) (1226:1226:1226)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (920:920:920) (999:999:999)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita1) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (920:920:920) (999:999:999)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita2) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (920:920:920) (999:999:999)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita3) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (920:920:920) (999:999:999)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita4) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (920:920:920) (999:999:999)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita5) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (920:920:920) (999:999:999)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita6) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (920:920:920) (999:999:999)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita7) + (DELAY + (ABSOLUTE + (PORT datab (142:142:142) (190:190:190)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (920:920:920) (999:999:999)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita8) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (194:194:194)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (920:920:920) (999:999:999)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita9) + (DELAY + (ABSOLUTE + (PORT datad (192:192:192) (239:239:239)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (879:879:879) (884:884:884)) + (PORT d (37:37:37) (50:50:50)) + (PORT ena (920:920:920) (999:999:999)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~4) + (DELAY + (ABSOLUTE + (PORT dataa (167:167:167) (232:232:232)) + (PORT datab (151:151:151) (207:207:207)) + (PORT datac (286:286:286) (322:322:322)) + (PORT datad (154:154:154) (203:203:203)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~3) + (DELAY + (ABSOLUTE + (PORT dataa (376:376:376) (454:454:454)) + (PORT datad (129:129:129) (167:167:167)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~5) + (DELAY + (ABSOLUTE + (PORT dataa (294:294:294) (340:340:340)) + (PORT datab (112:112:112) (144:144:144)) + (PORT datac (421:421:421) (485:485:485)) + (PORT datad (161:161:161) (187:187:187)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|tx) + (DELAY + (ABSOLUTE + (PORT clk (887:887:887) (891:891:891)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2554:2554:2554) (2301:2301:2301)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[2\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1120:1120:1120) (1119:1119:1119)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT asdata (546:546:546) (620:620:620)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT asdata (505:505:505) (561:561:561)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT datab (153:153:153) (209:209:209)) + (PORT datac (517:517:517) (641:641:641)) + (PORT datad (500:500:500) (607:607:607)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT asdata (847:847:847) (959:959:959)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (157:157:157) (208:208:208)) + (PORT datab (168:168:168) (227:227:227)) + (PORT datad (191:191:191) (221:221:221)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_TRF) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (853:853:853) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (470:470:470) (545:545:545)) + (PORT datab (115:115:115) (144:144:144)) + (PORT datac (151:151:151) (204:204:204)) + (PORT datad (128:128:128) (170:170:170)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (146:146:146)) + (PORT datab (167:167:167) (226:226:226)) + (PORT datac (123:123:123) (167:167:167)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_AR) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (853:853:853) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\~0) + (DELAY + (ABSOLUTE + (PORT dataa (673:673:673) (799:799:799)) + (PORT datad (532:532:532) (625:625:625)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (454:454:454) (532:532:532)) + (PORT datab (454:454:454) (523:523:523)) + (PORT datad (118:118:118) (156:156:156)) + (IOPATH dataa combout (181:181:181) (193:193:193)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (455:455:455) (533:533:533)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~4) + (DELAY + (ABSOLUTE + (PORT datac (378:378:378) (457:457:457)) + (PORT datad (90:90:90) (107:107:107)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\~0) + (DELAY + (ABSOLUTE + (PORT dataa (684:684:684) (807:807:807)) + (PORT datac (475:475:475) (553:553:553)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\~17) + (DELAY + (ABSOLUTE + (PORT datab (108:108:108) (137:137:137)) + (PORT datad (229:229:229) (277:277:277)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_PRE) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (863:863:863)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|WideOr5) + (DELAY + (ABSOLUTE + (PORT dataa (669:669:669) (795:795:795)) + (PORT datab (546:546:546) (649:649:649)) + (PORT datad (652:652:652) (769:769:769)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\~0) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (406:406:406)) + (PORT datad (476:476:476) (554:554:554)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (451:451:451) (529:529:529)) + (PORT datab (129:129:129) (177:177:177)) + (PORT datac (440:440:440) (503:503:503)) + (PORT datad (117:117:117) (154:154:154)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (201:201:201) (257:257:257)) + (PORT datab (131:131:131) (179:179:179)) + (PORT datac (437:437:437) (501:501:501)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector5\~2) + (DELAY + (ABSOLUTE + (PORT datac (378:378:378) (457:457:457)) + (PORT datad (89:89:89) (107:107:107)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (190:190:190) (227:227:227)) + (PORT datab (156:156:156) (209:209:209)) + (PORT datac (153:153:153) (208:208:208)) + (PORT datad (212:212:212) (262:262:262)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT datac (510:510:510) (632:632:632)) + (PORT datad (507:507:507) (615:615:615)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datac (134:134:134) (178:178:178)) + (PORT datad (212:212:212) (263:263:263)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datab (199:199:199) (255:255:255)) + (PORT datac (426:426:426) (502:502:502)) + (PORT datad (184:184:184) (228:228:228)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (103:103:103) (134:134:134)) + (PORT datac (378:378:378) (457:457:457)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (432:432:432)) + (PORT datab (349:349:349) (410:410:410)) + (PORT datac (371:371:371) (451:451:451)) + (PORT datad (364:364:364) (438:438:438)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (401:401:401) (487:487:487)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (211:211:211) (262:262:262)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_addr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~6) + (DELAY + (ABSOLUTE + (PORT datad (233:233:233) (282:282:282)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT datac (485:485:485) (558:558:558)) + (PORT datad (230:230:230) (278:278:278)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (863:863:863)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~5) + (DELAY + (ABSOLUTE + (PORT datab (153:153:153) (206:206:206)) + (PORT datad (232:232:232) (280:280:280)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (863:863:863)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~4) + (DELAY + (ABSOLUTE + (PORT dataa (214:214:214) (274:274:274)) + (PORT datab (143:143:143) (195:195:195)) + (PORT datad (228:228:228) (276:276:276)) + (IOPATH dataa combout (158:158:158) (173:173:173)) + (IOPATH datab combout (160:160:160) (176:176:176)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (863:863:863)) + (PORT ena (421:421:421) (449:449:449)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + (HOLD ena (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\~15) + (DELAY + (ABSOLUTE + (PORT dataa (138:138:138) (191:191:191)) + (PORT datab (154:154:154) (207:207:207)) + (PORT datac (127:127:127) (173:173:173)) + (PORT datad (120:120:120) (159:159:159)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (204:204:204) (249:249:249)) + (PORT datab (139:139:139) (190:190:190)) + (PORT datac (151:151:151) (205:205:205)) + (PORT datad (450:450:450) (520:520:520)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_MRS) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (853:853:853) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_ba\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT asdata (655:655:655) (741:741:741)) + (PORT clrn (858:858:858) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (463:463:463) (545:545:545)) + (PORT datab (153:153:153) (209:209:209)) + (PORT datad (499:499:499) (606:606:606)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (537:537:537) (660:660:660)) + (PORT datab (531:531:531) (625:625:625)) + (PORT datac (473:473:473) (567:567:567)) + (PORT datad (188:188:188) (218:218:218)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (256:256:256)) + (PORT datab (175:175:175) (236:236:236)) + (PORT datac (194:194:194) (238:238:238)) + (PORT datad (175:175:175) (197:197:197)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (105:105:105) (137:137:137)) + (PORT datab (141:141:141) (194:194:194)) + (PORT datac (211:211:211) (268:268:268)) + (PORT datad (103:103:103) (120:120:120)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_ba\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (533:533:533) (655:655:655)) + (PORT datab (532:532:532) (627:627:627)) + (PORT datac (432:432:432) (503:503:503)) + (PORT datad (507:507:507) (614:614:614)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|WideOr7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (164:164:164) (223:223:223)) + (PORT datab (239:239:239) (298:298:298)) + (PORT datac (192:192:192) (244:244:244)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (113:113:113) (147:147:147)) + (PORT datab (113:113:113) (145:145:145)) + (PORT datad (211:211:211) (262:262:262)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_addr\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (145:145:145) (198:198:198)) + (PORT datab (135:135:135) (187:187:187)) + (PORT datad (1044:1044:1044) (1206:1206:1206)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_ACTIVE) + (DELAY + (ABSOLUTE + (PORT clk (877:877:877) (881:881:881)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (861:861:861) (864:864:864)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (392:392:392)) + (PORT datab (485:485:485) (567:567:567)) + (PORT datac (155:155:155) (210:210:210)) + (PORT datad (141:141:141) (185:185:185)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (208:208:208) (255:255:255)) + (PORT datab (187:187:187) (224:224:224)) + (PORT datac (158:158:158) (215:215:215)) + (PORT datad (92:92:92) (110:110:110)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_addr\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (874:874:874) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (861:861:861)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (130:130:130) (181:181:181)) + (PORT datab (152:152:152) (208:208:208)) + (PORT datac (316:316:316) (373:373:373)) + (PORT datad (502:502:502) (609:609:609)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (534:534:534) (657:657:657)) + (PORT datab (486:486:486) (586:586:586)) + (PORT datac (294:294:294) (351:351:351)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (172:172:172) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) +) diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_modelsim.xrf b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_modelsim.xrf new file mode 100644 index 0000000..4aec183 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_modelsim.xrf @@ -0,0 +1,1341 @@ +vendor_name = ModelSim +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/rtl/fifo_read.v +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/rtl/sdram/sdram_write.v +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/rtl/sdram/sdram_top.v +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/rtl/sdram/sdram_read.v +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/rtl/sdram/sdram_init.v +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/rtl/sdram/sdram_ctrl.v +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/rtl/sdram/sdram_arbit.v +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/rtl/sdram/sdram_a_ref.v +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/rtl/sdram/fifo_ctrl.v +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/fifo_data.qip +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/ip_core/fifo_data/fifo_data.v +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen.qip +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/ip_core/clk_gen/clk_gen.v +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/rtl/uart_tx.v +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/rtl/uart_sdram.v +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/rtl/uart_rx.v +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/read_fifo.qip +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/ip_core/read_fifo/read_fifo.v +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/uart_sdram.cbx.xml +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_pll.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/stratixii_pll.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/cycloneii_pll.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/cbx.lst +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/clk_gen_altpll.v +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/dcfifo.tdf +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/altdpram.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/a_graycounter.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/a_fefifo.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/a_gray2bin.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/dffpipe.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_sync_fifo.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_compare.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram_fifo.inc +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/dcfifo_3fk1.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/a_gray2bin_7ib.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/a_graycounter_677.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/a_graycounter_2lc.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/altsyncram_em31.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/dffpipe_pe9.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/alt_synch_pipe_vd8.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/dffpipe_qe9.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/alt_synch_pipe_0e8.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/dffpipe_re9.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/cmpr_c66.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/cmpr_b66.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/mux_j28.tdf +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/scfifo.tdf +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/a_regfifo.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/a_dpfifo.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/a_i2fifo.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/a_fffifo.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/a_f2fifo.inc +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/scfifo_un21.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/a_dpfifo_5u21.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/a_fefifo_jaf.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/cntr_op7.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/dpram_d811.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/altsyncram_c3k1.tdf +source_file = 1, E:/simiao/lc/A415/08_uart_sdram/uart_sdram/project/db/cntr_cpb.tdf +design_name = uart_sdram +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1|ram_block2a0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5] , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3] , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3], uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[3] , uart_tx_inst|baud_cnt[3], uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[4] , uart_tx_inst|baud_cnt[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~14, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~16, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[3]~16, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[5]~20, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[3]~16, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[4]~18, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[3]~19 , uart_tx_inst|baud_cnt[3]~19, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[4]~21 , uart_tx_inst|baud_cnt[4]~21, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~12, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~26, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita1, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita2, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita3, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita4, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita5, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita6, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita7, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita8, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita9, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[1] , fifo_read_inst|baud_cnt[1], uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[4] , fifo_read_inst|baud_cnt[4], uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[9] , fifo_read_inst|baud_cnt[9], uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[11] , fifo_read_inst|baud_cnt[11], uart_sdram, 1 +instance = comp, \fifo_read_inst|Add2~4 , fifo_read_inst|Add2~4, uart_sdram, 1 +instance = comp, \data_num[0] , data_num[0], uart_sdram, 1 +instance = comp, \data_num[2] , data_num[2], uart_sdram, 1 +instance = comp, \data_num[1] , data_num[1], uart_sdram, 1 +instance = comp, \data_num[3] , data_num[3], uart_sdram, 1 +instance = comp, \data_num[4] , data_num[4], uart_sdram, 1 +instance = comp, \data_num[5] , data_num[5], uart_sdram, 1 +instance = comp, \data_num[6] , data_num[6], uart_sdram, 1 +instance = comp, \data_num[7] , data_num[7], uart_sdram, 1 +instance = comp, \data_num[8] , data_num[8], uart_sdram, 1 +instance = comp, \data_num[9] , data_num[9], uart_sdram, 1 +instance = comp, \data_num[10] , data_num[10], uart_sdram, 1 +instance = comp, \data_num[11] , data_num[11], uart_sdram, 1 +instance = comp, \data_num[12] , data_num[12], uart_sdram, 1 +instance = comp, \data_num[13] , data_num[13], uart_sdram, 1 +instance = comp, \data_num[14] , data_num[14], uart_sdram, 1 +instance = comp, \data_num[15] , data_num[15], uart_sdram, 1 +instance = comp, \data_num[16] , data_num[16], uart_sdram, 1 +instance = comp, \data_num[17] , data_num[17], uart_sdram, 1 +instance = comp, \data_num[18] , data_num[18], uart_sdram, 1 +instance = comp, \data_num[19] , data_num[19], uart_sdram, 1 +instance = comp, \data_num[20] , data_num[20], uart_sdram, 1 +instance = comp, \data_num[21] , data_num[21], uart_sdram, 1 +instance = comp, \data_num[22] , data_num[22], uart_sdram, 1 +instance = comp, \data_num[23] , data_num[23], uart_sdram, 1 +instance = comp, \Add1~0 , Add1~0, uart_sdram, 1 +instance = comp, \Add1~2 , Add1~2, uart_sdram, 1 +instance = comp, \Add1~4 , Add1~4, uart_sdram, 1 +instance = comp, \Add1~6 , Add1~6, uart_sdram, 1 +instance = comp, \Add1~8 , Add1~8, uart_sdram, 1 +instance = comp, \Add1~10 , Add1~10, uart_sdram, 1 +instance = comp, \Add1~12 , Add1~12, uart_sdram, 1 +instance = comp, \Add1~14 , Add1~14, uart_sdram, 1 +instance = comp, \Add1~16 , Add1~16, uart_sdram, 1 +instance = comp, \Add1~18 , Add1~18, uart_sdram, 1 +instance = comp, \Add1~20 , Add1~20, uart_sdram, 1 +instance = comp, \Add1~22 , Add1~22, uart_sdram, 1 +instance = comp, \Add1~24 , Add1~24, uart_sdram, 1 +instance = comp, \Add1~26 , Add1~26, uart_sdram, 1 +instance = comp, \Add1~28 , Add1~28, uart_sdram, 1 +instance = comp, \Add1~30 , Add1~30, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[1]~15 , fifo_read_inst|baud_cnt[1]~15, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[4]~21 , fifo_read_inst|baud_cnt[4]~21, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[9]~31 , fifo_read_inst|baud_cnt[9]~31, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[11]~35 , fifo_read_inst|baud_cnt[11]~35, uart_sdram, 1 +instance = comp, \data_num[0]~24 , data_num[0]~24, uart_sdram, 1 +instance = comp, \data_num[1]~26 , data_num[1]~26, uart_sdram, 1 +instance = comp, \data_num[2]~28 , data_num[2]~28, uart_sdram, 1 +instance = comp, \data_num[3]~30 , data_num[3]~30, uart_sdram, 1 +instance = comp, \data_num[4]~32 , data_num[4]~32, uart_sdram, 1 +instance = comp, \data_num[5]~34 , data_num[5]~34, uart_sdram, 1 +instance = comp, \data_num[6]~36 , data_num[6]~36, uart_sdram, 1 +instance = comp, \data_num[7]~38 , data_num[7]~38, uart_sdram, 1 +instance = comp, \data_num[8]~40 , data_num[8]~40, uart_sdram, 1 +instance = comp, \data_num[9]~42 , data_num[9]~42, uart_sdram, 1 +instance = comp, \data_num[10]~44 , data_num[10]~44, uart_sdram, 1 +instance = comp, \data_num[11]~46 , data_num[11]~46, uart_sdram, 1 +instance = comp, \data_num[12]~48 , data_num[12]~48, uart_sdram, 1 +instance = comp, \data_num[13]~50 , data_num[13]~50, uart_sdram, 1 +instance = comp, \data_num[14]~52 , data_num[14]~52, uart_sdram, 1 +instance = comp, \data_num[15]~54 , data_num[15]~54, uart_sdram, 1 +instance = comp, \data_num[16]~56 , data_num[16]~56, uart_sdram, 1 +instance = comp, \data_num[17]~58 , data_num[17]~58, uart_sdram, 1 +instance = comp, \data_num[18]~60 , data_num[18]~60, uart_sdram, 1 +instance = comp, \data_num[19]~62 , data_num[19]~62, uart_sdram, 1 +instance = comp, \data_num[20]~64 , data_num[20]~64, uart_sdram, 1 +instance = comp, \data_num[21]~66 , data_num[21]~66, uart_sdram, 1 +instance = comp, \data_num[22]~68 , data_num[22]~68, uart_sdram, 1 +instance = comp, \data_num[23]~70 , data_num[23]~70, uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[1] , fifo_read_inst|cnt_read[1], uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[3] , fifo_read_inst|cnt_read[3], uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[0] , fifo_read_inst|cnt_read[0], uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[2] , fifo_read_inst|cnt_read[2], uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[4] , fifo_read_inst|cnt_read[4], uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[5] , fifo_read_inst|cnt_read[5], uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[6] , fifo_read_inst|cnt_read[6], uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[7] , fifo_read_inst|cnt_read[7], uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[8] , fifo_read_inst|cnt_read[8], uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[9] , fifo_read_inst|cnt_read[9], uart_sdram, 1 +instance = comp, \uart_rx_inst|Add1~0 , uart_rx_inst|Add1~0, uart_sdram, 1 +instance = comp, \uart_rx_inst|Add1~4 , uart_rx_inst|Add1~4, uart_sdram, 1 +instance = comp, \uart_rx_inst|Add1~6 , uart_rx_inst|Add1~6, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[4] , uart_rx_inst|baud_cnt[4], uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[0]~10 , fifo_read_inst|cnt_read[0]~10, uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[1]~12 , fifo_read_inst|cnt_read[1]~12, uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[2]~14 , fifo_read_inst|cnt_read[2]~14, uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[3]~16 , fifo_read_inst|cnt_read[3]~16, uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[4]~18 , fifo_read_inst|cnt_read[4]~18, uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[5]~20 , fifo_read_inst|cnt_read[5]~20, uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[6]~22 , fifo_read_inst|cnt_read[6]~22, uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[7]~24 , fifo_read_inst|cnt_read[7]~24, uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[8]~26 , fifo_read_inst|cnt_read[8]~26, uart_sdram, 1 +instance = comp, \fifo_read_inst|cnt_read[9]~28 , fifo_read_inst|cnt_read[9]~28, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[4]~21 , uart_rx_inst|baud_cnt[4]~21, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[2] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[0] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[0] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~0, uart_sdram, 1 +instance = comp, \uart_tx_inst|bit_cnt[0] , uart_tx_inst|bit_cnt[0], uart_sdram, 1 +instance = comp, \uart_tx_inst|Mux0~0 , uart_tx_inst|Mux0~0, uart_sdram, 1 +instance = comp, \uart_tx_inst|Mux0~1 , uart_tx_inst|Mux0~1, uart_sdram, 1 +instance = comp, \uart_tx_inst|tx~0 , uart_tx_inst|tx~0, uart_sdram, 1 +instance = comp, \uart_tx_inst|tx~1 , uart_tx_inst|tx~1, uart_sdram, 1 +instance = comp, \uart_tx_inst|tx~2 , uart_tx_inst|tx~2, uart_sdram, 1 +instance = comp, \uart_tx_inst|bit_cnt[3] , uart_tx_inst|bit_cnt[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~0, uart_sdram, 1 +instance = comp, \uart_tx_inst|Add1~0 , uart_tx_inst|Add1~0, uart_sdram, 1 +instance = comp, \uart_tx_inst|Add1~1 , uart_tx_inst|Add1~1, uart_sdram, 1 +instance = comp, \uart_tx_inst|bit_cnt[3]~4 , uart_tx_inst|bit_cnt[3]~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[2] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[4] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[3] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[2] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[1] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[0] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[5] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[6] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[7] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[9] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[8] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[5] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[4] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[3] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[2] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[1] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[0] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[6] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[7] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[8] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[9] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0 , sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1 , sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TMRD, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.IDLE~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[13] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[13], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[6] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[3] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[3], uart_sdram, 1 +instance = comp, \uart_tx_inst|Equal1~3 , uart_tx_inst|Equal1~3, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[9], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~0, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[8], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[7], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[6], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[5], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~1, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[4], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[3], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[2], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~2, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~3, uart_sdram, 1 +instance = comp, \fifo_read_inst|bit_cnt[2] , fifo_read_inst|bit_cnt[2], uart_sdram, 1 +instance = comp, \fifo_read_inst|Equal1~0 , fifo_read_inst|Equal1~0, uart_sdram, 1 +instance = comp, \fifo_read_inst|Equal1~1 , fifo_read_inst|Equal1~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor9, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor9, uart_sdram, 1 +instance = comp, \cnt_wait[15] , cnt_wait[15], uart_sdram, 1 +instance = comp, \cnt_wait[14] , cnt_wait[14], uart_sdram, 1 +instance = comp, \cnt_wait[13] , cnt_wait[13], uart_sdram, 1 +instance = comp, \cnt_wait[12] , cnt_wait[12], uart_sdram, 1 +instance = comp, \Equal0~0 , Equal0~0, uart_sdram, 1 +instance = comp, \cnt_wait[9] , cnt_wait[9], uart_sdram, 1 +instance = comp, \cnt_wait[11] , cnt_wait[11], uart_sdram, 1 +instance = comp, \cnt_wait[10] , cnt_wait[10], uart_sdram, 1 +instance = comp, \cnt_wait[8] , cnt_wait[8], uart_sdram, 1 +instance = comp, \Equal0~1 , Equal0~1, uart_sdram, 1 +instance = comp, \cnt_wait[7] , cnt_wait[7], uart_sdram, 1 +instance = comp, \cnt_wait[6] , cnt_wait[6], uart_sdram, 1 +instance = comp, \cnt_wait[5] , cnt_wait[5], uart_sdram, 1 +instance = comp, \cnt_wait[4] , cnt_wait[4], uart_sdram, 1 +instance = comp, \Equal0~2 , Equal0~2, uart_sdram, 1 +instance = comp, \cnt_wait[3] , cnt_wait[3], uart_sdram, 1 +instance = comp, \cnt_wait[2] , cnt_wait[2], uart_sdram, 1 +instance = comp, \cnt_wait[1] , cnt_wait[1], uart_sdram, 1 +instance = comp, \cnt_wait[0] , cnt_wait[0], uart_sdram, 1 +instance = comp, \Equal0~3 , Equal0~3, uart_sdram, 1 +instance = comp, \Equal0~4 , Equal0~4, uart_sdram, 1 +instance = comp, \read_valid~0 , read_valid~0, uart_sdram, 1 +instance = comp, \read_valid~1 , read_valid~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector4~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add2~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux_reg, uart_sdram, 1 +instance = comp, \fifo_read_inst|Equal1~2 , fifo_read_inst|Equal1~2, uart_sdram, 1 +instance = comp, \fifo_read_inst|Equal5~1 , fifo_read_inst|Equal5~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[2] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7, uart_sdram, 1 +instance = comp, \Equal1~0 , Equal1~0, uart_sdram, 1 +instance = comp, \Equal1~1 , Equal1~1, uart_sdram, 1 +instance = comp, \Equal1~2 , Equal1~2, uart_sdram, 1 +instance = comp, \Equal1~3 , Equal1~3, uart_sdram, 1 +instance = comp, \Equal1~4 , Equal1~4, uart_sdram, 1 +instance = comp, \Equal1~5 , Equal1~5, uart_sdram, 1 +instance = comp, \Equal1~6 , Equal1~6, uart_sdram, 1 +instance = comp, \cnt_wait[8]~0 , cnt_wait[8]~0, uart_sdram, 1 +instance = comp, \cnt_wait[15]~1 , cnt_wait[15]~1, uart_sdram, 1 +instance = comp, \cnt_wait[15]~2 , cnt_wait[15]~2, uart_sdram, 1 +instance = comp, \cnt_wait[14]~3 , cnt_wait[14]~3, uart_sdram, 1 +instance = comp, \cnt_wait[13]~4 , cnt_wait[13]~4, uart_sdram, 1 +instance = comp, \cnt_wait[12]~5 , cnt_wait[12]~5, uart_sdram, 1 +instance = comp, \cnt_wait[9]~6 , cnt_wait[9]~6, uart_sdram, 1 +instance = comp, \cnt_wait[11]~7 , cnt_wait[11]~7, uart_sdram, 1 +instance = comp, \cnt_wait[10]~8 , cnt_wait[10]~8, uart_sdram, 1 +instance = comp, \cnt_wait[8]~9 , cnt_wait[8]~9, uart_sdram, 1 +instance = comp, \cnt_wait[7]~10 , cnt_wait[7]~10, uart_sdram, 1 +instance = comp, \cnt_wait[6]~11 , cnt_wait[6]~11, uart_sdram, 1 +instance = comp, \cnt_wait[5]~12 , cnt_wait[5]~12, uart_sdram, 1 +instance = comp, \cnt_wait[4]~13 , cnt_wait[4]~13, uart_sdram, 1 +instance = comp, \cnt_wait[3]~14 , cnt_wait[3]~14, uart_sdram, 1 +instance = comp, \cnt_wait[2]~15 , cnt_wait[2]~15, uart_sdram, 1 +instance = comp, \cnt_wait[1]~16 , cnt_wait[1]~16, uart_sdram, 1 +instance = comp, \cnt_wait[0]~17 , cnt_wait[0]~17, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb|data_wire[2]~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux|result_node[0]~7, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6, uart_sdram, 1 +instance = comp, \fifo_read_inst|rd_flag , fifo_read_inst|rd_flag, uart_sdram, 1 +instance = comp, \fifo_read_inst|Equal4~2 , fifo_read_inst|Equal4~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|cntr_cout[0]~0, uart_sdram, 1 +instance = comp, \uart_rx_inst|bit_cnt[0] , uart_rx_inst|bit_cnt[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0], uart_sdram, 1 +instance = comp, \fifo_read_inst|Equal2~0 , fifo_read_inst|Equal2~0, uart_sdram, 1 +instance = comp, \fifo_read_inst|Equal2~1 , fifo_read_inst|Equal2~1, uart_sdram, 1 +instance = comp, \fifo_read_inst|Equal2~2 , fifo_read_inst|Equal2~2, uart_sdram, 1 +instance = comp, \fifo_read_inst|rd_flag~0 , fifo_read_inst|rd_flag~0, uart_sdram, 1 +instance = comp, \uart_rx_inst|bit_cnt~1 , uart_rx_inst|bit_cnt~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~13, uart_sdram, 1 +instance = comp, \uart_rx_inst|work_en , uart_rx_inst|work_en, uart_sdram, 1 +instance = comp, \uart_rx_inst|start_nedge , uart_rx_inst|start_nedge, uart_sdram, 1 +instance = comp, \uart_rx_inst|work_en~0 , uart_rx_inst|work_en~0, uart_sdram, 1 +instance = comp, \uart_rx_inst|always3~0 , uart_rx_inst|always3~0, uart_sdram, 1 +instance = comp, \uart_tx_inst|bit_cnt[0]~5 , uart_tx_inst|bit_cnt[0]~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[7]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[7]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[5]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[3]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[0]~feeder, uart_sdram, 1 +instance = comp, \tx~output , tx~output, uart_sdram, 1 +instance = comp, \sdram_clk~output , sdram_clk~output, uart_sdram, 1 +instance = comp, \sdram_cke~output , sdram_cke~output, uart_sdram, 1 +instance = comp, \sdram_cs_n~output , sdram_cs_n~output, uart_sdram, 1 +instance = comp, \sdram_cas_n~output , sdram_cas_n~output, uart_sdram, 1 +instance = comp, \sdram_ras_n~output , sdram_ras_n~output, uart_sdram, 1 +instance = comp, \sdram_we_n~output , sdram_we_n~output, uart_sdram, 1 +instance = comp, \sdram_ba[0]~output , sdram_ba[0]~output, uart_sdram, 1 +instance = comp, \sdram_ba[1]~output , sdram_ba[1]~output, uart_sdram, 1 +instance = comp, \sdram_addr[0]~output , sdram_addr[0]~output, uart_sdram, 1 +instance = comp, \sdram_addr[1]~output , sdram_addr[1]~output, uart_sdram, 1 +instance = comp, \sdram_addr[2]~output , sdram_addr[2]~output, uart_sdram, 1 +instance = comp, \sdram_addr[3]~output , sdram_addr[3]~output, uart_sdram, 1 +instance = comp, \sdram_addr[4]~output , sdram_addr[4]~output, uart_sdram, 1 +instance = comp, \sdram_addr[5]~output , sdram_addr[5]~output, uart_sdram, 1 +instance = comp, \sdram_addr[6]~output , sdram_addr[6]~output, uart_sdram, 1 +instance = comp, \sdram_addr[7]~output , sdram_addr[7]~output, uart_sdram, 1 +instance = comp, \sdram_addr[8]~output , sdram_addr[8]~output, uart_sdram, 1 +instance = comp, \sdram_addr[9]~output , sdram_addr[9]~output, uart_sdram, 1 +instance = comp, \sdram_addr[10]~output , sdram_addr[10]~output, uart_sdram, 1 +instance = comp, \sdram_addr[11]~output , sdram_addr[11]~output, uart_sdram, 1 +instance = comp, \sdram_addr[12]~output , sdram_addr[12]~output, uart_sdram, 1 +instance = comp, \sdram_dqm[0]~output , sdram_dqm[0]~output, uart_sdram, 1 +instance = comp, \sdram_dqm[1]~output , sdram_dqm[1]~output, uart_sdram, 1 +instance = comp, \sdram_dq[0]~output , sdram_dq[0]~output, uart_sdram, 1 +instance = comp, \sdram_dq[1]~output , sdram_dq[1]~output, uart_sdram, 1 +instance = comp, \sdram_dq[2]~output , sdram_dq[2]~output, uart_sdram, 1 +instance = comp, \sdram_dq[3]~output , sdram_dq[3]~output, uart_sdram, 1 +instance = comp, \sdram_dq[4]~output , sdram_dq[4]~output, uart_sdram, 1 +instance = comp, \sdram_dq[5]~output , sdram_dq[5]~output, uart_sdram, 1 +instance = comp, \sdram_dq[6]~output , sdram_dq[6]~output, uart_sdram, 1 +instance = comp, \sdram_dq[7]~output , sdram_dq[7]~output, uart_sdram, 1 +instance = comp, \sdram_dq[8]~output , sdram_dq[8]~output, uart_sdram, 1 +instance = comp, \sdram_dq[9]~output , sdram_dq[9]~output, uart_sdram, 1 +instance = comp, \sdram_dq[10]~output , sdram_dq[10]~output, uart_sdram, 1 +instance = comp, \sdram_dq[11]~output , sdram_dq[11]~output, uart_sdram, 1 +instance = comp, \sdram_dq[12]~output , sdram_dq[12]~output, uart_sdram, 1 +instance = comp, \sdram_dq[13]~output , sdram_dq[13]~output, uart_sdram, 1 +instance = comp, \sdram_dq[14]~output , sdram_dq[14]~output, uart_sdram, 1 +instance = comp, \sdram_dq[15]~output , sdram_dq[15]~output, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[0]~13 , uart_rx_inst|baud_cnt[0]~13, uart_sdram, 1 +instance = comp, \sys_clk~input , sys_clk~input, uart_sdram, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll1 , clk_gen_inst|altpll_component|auto_generated|pll1, uart_sdram, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder , clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder, uart_sdram, 1 +instance = comp, \sys_rst_n~input , sys_rst_n~input, uart_sdram, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync , clk_gen_inst|altpll_component|auto_generated|pll_lock_sync, uart_sdram, 1 +instance = comp, \rst_n~0 , rst_n~0, uart_sdram, 1 +instance = comp, \rst_n~0clkctrl , rst_n~0clkctrl, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[2]~17 , uart_rx_inst|baud_cnt[2]~17, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[3]~19 , uart_rx_inst|baud_cnt[3]~19, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[3] , uart_rx_inst|baud_cnt[3], uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[5]~23 , uart_rx_inst|baud_cnt[5]~23, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[5] , uart_rx_inst|baud_cnt[5], uart_sdram, 1 +instance = comp, \uart_rx_inst|Equal1~1 , uart_rx_inst|Equal1~1, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[6]~25 , uart_rx_inst|baud_cnt[6]~25, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[6] , uart_rx_inst|baud_cnt[6], uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[7]~27 , uart_rx_inst|baud_cnt[7]~27, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[7] , uart_rx_inst|baud_cnt[7], uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[8]~29 , uart_rx_inst|baud_cnt[8]~29, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[8] , uart_rx_inst|baud_cnt[8], uart_sdram, 1 +instance = comp, \uart_rx_inst|Equal1~0 , uart_rx_inst|Equal1~0, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[9]~31 , uart_rx_inst|baud_cnt[9]~31, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[9] , uart_rx_inst|baud_cnt[9], uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[10]~33 , uart_rx_inst|baud_cnt[10]~33, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[11]~35 , uart_rx_inst|baud_cnt[11]~35, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[11] , uart_rx_inst|baud_cnt[11], uart_sdram, 1 +instance = comp, \uart_rx_inst|Equal1~2 , uart_rx_inst|Equal1~2, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[10] , uart_rx_inst|baud_cnt[10], uart_sdram, 1 +instance = comp, \uart_rx_inst|Equal1~3 , uart_rx_inst|Equal1~3, uart_sdram, 1 +instance = comp, \uart_rx_inst|always5~0 , uart_rx_inst|always5~0, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[0] , uart_rx_inst|baud_cnt[0], uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[1]~15 , uart_rx_inst|baud_cnt[1]~15, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[1] , uart_rx_inst|baud_cnt[1], uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[2] , uart_rx_inst|baud_cnt[2], uart_sdram, 1 +instance = comp, \uart_rx_inst|Equal2~0 , uart_rx_inst|Equal2~0, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[12]~37 , uart_rx_inst|baud_cnt[12]~37, uart_sdram, 1 +instance = comp, \uart_rx_inst|baud_cnt[12] , uart_rx_inst|baud_cnt[12], uart_sdram, 1 +instance = comp, \uart_rx_inst|Equal2~1 , uart_rx_inst|Equal2~1, uart_sdram, 1 +instance = comp, \uart_rx_inst|Equal2~2 , uart_rx_inst|Equal2~2, uart_sdram, 1 +instance = comp, \uart_rx_inst|bit_flag , uart_rx_inst|bit_flag, uart_sdram, 1 +instance = comp, \uart_rx_inst|Add1~2 , uart_rx_inst|Add1~2, uart_sdram, 1 +instance = comp, \uart_rx_inst|bit_cnt[2] , uart_rx_inst|bit_cnt[2], uart_sdram, 1 +instance = comp, \uart_rx_inst|bit_cnt[1] , uart_rx_inst|bit_cnt[1], uart_sdram, 1 +instance = comp, \uart_rx_inst|always4~0 , uart_rx_inst|always4~0, uart_sdram, 1 +instance = comp, \uart_rx_inst|always4~1 , uart_rx_inst|always4~1, uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_flag , uart_rx_inst|rx_flag, uart_sdram, 1 +instance = comp, \uart_rx_inst|po_flag , uart_rx_inst|po_flag, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~10, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~9, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[10], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0]~10, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6]~22, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6] , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[10], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor7, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[5] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[4] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[4] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[7] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor7, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[3] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[2] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrptr_g[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp|dffpipe13|dffe14a[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[1] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[0] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~10, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_dgwp_gray2bin|xor6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[6] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_bwp|dffe12a[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~12, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[7] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~14, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|LessThan2~0 , sdram_top_inst|fifo_ctrl_inst|LessThan2~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|LessThan2~1 , sdram_top_inst|fifo_ctrl_inst|LessThan2~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor9, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[9] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g_gray2bin|xor8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[8] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rs_brp|dffe12a[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|op_1~18, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0 , sdram_top_inst|fifo_ctrl_inst|sdram_wr_req~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|sdram_wr_req , sdram_top_inst|fifo_ctrl_inst|sdram_wr_req, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a9, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~9, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a7, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~7, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0]~10, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|rd_en, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1]~12, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2]~14, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5]~20, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6]~22, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7]~24, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8]~26, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9]~28, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector2~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_CL, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector3~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_DATA, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_PRE, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector4~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRP, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trp_end~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_END, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector0~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_IDLE, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state~16, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_ACTIVE, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector1~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_TRCD, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|trcd_end~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_state.RD_READ, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|tread_end~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector5~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|cnt_clk[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_wrreq~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a10, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a9, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|sub_parity10a[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|parity9, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|_~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[6] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[9] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[10] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[10], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[10], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g1p|counter8a8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[8] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux|result_node[0]~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_msb_aeb, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[2] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[4] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0]~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0]~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdempty_eq_comp_lsb|data_wire[0]~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[1] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|delayed_wrptr_g[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[3] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux|result_node[0]~7, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_aeb, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_en_dly , fifo_read_inst|read_en_dly, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_wreq, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_comb_bita0, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[0], uart_sdram, 1 +instance = comp, \fifo_read_inst|Add2~0 , fifo_read_inst|Add2~0, uart_sdram, 1 +instance = comp, \fifo_read_inst|bit_cnt[0] , fifo_read_inst|bit_cnt[0], uart_sdram, 1 +instance = comp, \fifo_read_inst|Add2~2 , fifo_read_inst|Add2~2, uart_sdram, 1 +instance = comp, \fifo_read_inst|Add2~6 , fifo_read_inst|Add2~6, uart_sdram, 1 +instance = comp, \fifo_read_inst|bit_cnt~0 , fifo_read_inst|bit_cnt~0, uart_sdram, 1 +instance = comp, \fifo_read_inst|bit_cnt[3] , fifo_read_inst|bit_cnt[3], uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[0]~13 , fifo_read_inst|baud_cnt[0]~13, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[5]~23 , fifo_read_inst|baud_cnt[5]~23, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[6]~25 , fifo_read_inst|baud_cnt[6]~25, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[6] , fifo_read_inst|baud_cnt[6], uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[7]~27 , fifo_read_inst|baud_cnt[7]~27, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[7] , fifo_read_inst|baud_cnt[7], uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[8]~29 , fifo_read_inst|baud_cnt[8]~29, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[8] , fifo_read_inst|baud_cnt[8], uart_sdram, 1 +instance = comp, \fifo_read_inst|Equal4~0 , fifo_read_inst|Equal4~0, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[3]~19 , fifo_read_inst|baud_cnt[3]~19, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[3] , fifo_read_inst|baud_cnt[3], uart_sdram, 1 +instance = comp, \fifo_read_inst|Equal4~1 , fifo_read_inst|Equal4~1, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[10]~33 , fifo_read_inst|baud_cnt[10]~33, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[10] , fifo_read_inst|baud_cnt[10], uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[12]~37 , fifo_read_inst|baud_cnt[12]~37, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[12] , fifo_read_inst|baud_cnt[12], uart_sdram, 1 +instance = comp, \fifo_read_inst|Equal4~3 , fifo_read_inst|Equal4~3, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[0] , fifo_read_inst|baud_cnt[0], uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[2]~17 , fifo_read_inst|baud_cnt[2]~17, uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[2] , fifo_read_inst|baud_cnt[2], uart_sdram, 1 +instance = comp, \fifo_read_inst|baud_cnt[5] , fifo_read_inst|baud_cnt[5], uart_sdram, 1 +instance = comp, \fifo_read_inst|Equal5~0 , fifo_read_inst|Equal5~0, uart_sdram, 1 +instance = comp, \fifo_read_inst|Equal5~2 , fifo_read_inst|Equal5~2, uart_sdram, 1 +instance = comp, \fifo_read_inst|bit_flag , fifo_read_inst|bit_flag, uart_sdram, 1 +instance = comp, \fifo_read_inst|bit_cnt~1 , fifo_read_inst|bit_cnt~1, uart_sdram, 1 +instance = comp, \fifo_read_inst|bit_cnt[1] , fifo_read_inst|bit_cnt[1], uart_sdram, 1 +instance = comp, \fifo_read_inst|always5~0 , fifo_read_inst|always5~0, uart_sdram, 1 +instance = comp, \fifo_read_inst|always5~1 , fifo_read_inst|always5~1, uart_sdram, 1 +instance = comp, \fifo_read_inst|rd_en , fifo_read_inst|rd_en, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~1, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~0, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty~2, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_non_empty, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full~4, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|b_full, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|_~0, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw|counter_reg_bit[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[9] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[7] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor7, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[3] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[2] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[1] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[8] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[10], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[10], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor7, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[1] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[0] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~6, uart_sdram, 1 +instance = comp, \Equal2~1 , Equal2~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[8] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[7] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[5] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[4] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~10, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~12, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~16, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_en~0 , fifo_read_inst|read_en~0, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_en~1 , fifo_read_inst|read_en~1, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_en , fifo_read_inst|read_en, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|valid_rdreq~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6]~feeder, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp|dffpipe15|dffe16a[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_dgrp_gray2bin|xor6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[6] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_brp|dffe12a[6], uart_sdram, 1 +instance = comp, \Equal2~0 , Equal2~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|wrptr_g_gray2bin|xor9, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[9] , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|ws_bwp|dffe12a[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|op_2~18, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2 , sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3 , sdram_top_inst|fifo_ctrl_inst|sdram_rd_req~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|sdram_rd_req , sdram_top_inst|fifo_ctrl_inst|sdram_rd_req, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector3~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.READ, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~7, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector2~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_DATA, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|twrite_end~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_PRE, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector3~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRP, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trp_end~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_END, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.WRITE, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector0~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.ARBIT, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector1~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector0~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_IDLE, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~15, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector2~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRP, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[1] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector4~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[2] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector3~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_TRF, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[0] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_clk[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|trc_end~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Selector1~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AUTO_REF, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[1]~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[0] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref_aref[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~17, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_END, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|aref_en~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|state.AREF, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[0] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[1] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector1~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRP, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~10, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[5] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[0] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[1] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[2] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~8, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[4] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~14, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[7] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~16, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[8] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~18, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[9] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~20, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[10] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[10], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~22, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~24, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[12] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[12], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add0~28, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[14] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[14], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[11] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_200us[11], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal0~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Equal1~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_IDLE, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector5~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[2] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_clk[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Add1~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_END, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state~16, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_state.AREF_PCHA, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~8, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3]~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[4] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~10, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5]~10, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~12, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6]~9, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~14, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7]~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~7, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[1] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref~8, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[0] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|LessThan0~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~16, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8]~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Add0~18, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9]~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|cnt_aref[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|Equal0~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_req, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector2~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|wr_en, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector0~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_IDLE, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector4~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0] , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1]~12, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1] , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2]~14, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2] , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4]~18, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4] , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7]~24, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7] , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8]~26, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8] , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[8], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9]~28, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9] , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|cnt_clk[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Equal0~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector1~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_TRCD, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|trcd_end~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_WRITE, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a4, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~12, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~11, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|sub_parity7a[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~10, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|parity6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~7, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a7, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a8, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a10, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[10] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g[10], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux|result_node[0]~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux_reg, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|valid_wrreq~0, uart_sdram, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl , clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, uart_sdram, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl , clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[1]~clkctrl, uart_sdram, 1 +instance = comp, \rx~input , rx~input, uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_reg1~0 , uart_rx_inst|rx_reg1~0, uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_reg1 , uart_rx_inst|rx_reg1, uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_reg2~feeder , uart_rx_inst|rx_reg2~feeder, uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_reg2 , uart_rx_inst|rx_reg2, uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_reg3~feeder , uart_rx_inst|rx_reg3~feeder, uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_reg3 , uart_rx_inst|rx_reg3, uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_data[7]~0 , uart_rx_inst|rx_data[7]~0, uart_sdram, 1 +instance = comp, \uart_rx_inst|bit_cnt~0 , uart_rx_inst|bit_cnt~0, uart_sdram, 1 +instance = comp, \uart_rx_inst|bit_cnt[3] , uart_rx_inst|bit_cnt[3], uart_sdram, 1 +instance = comp, \uart_rx_inst|always8~0 , uart_rx_inst|always8~0, uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_data[7] , uart_rx_inst|rx_data[7], uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_data[6] , uart_rx_inst|rx_data[6], uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_data[5]~feeder , uart_rx_inst|rx_data[5]~feeder, uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_data[5] , uart_rx_inst|rx_data[5], uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_data[4]~feeder , uart_rx_inst|rx_data[4]~feeder, uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_data[4] , uart_rx_inst|rx_data[4], uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_data[3]~feeder , uart_rx_inst|rx_data[3]~feeder, uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_data[3] , uart_rx_inst|rx_data[3], uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_data[2]~feeder , uart_rx_inst|rx_data[2]~feeder, uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_data[2] , uart_rx_inst|rx_data[2], uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_data[1]~feeder , uart_rx_inst|rx_data[1]~feeder, uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_data[1] , uart_rx_inst|rx_data[1], uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_data[0]~feeder , uart_rx_inst|rx_data[0]~feeder, uart_sdram, 1 +instance = comp, \uart_rx_inst|rx_data[0] , uart_rx_inst|rx_data[0], uart_sdram, 1 +instance = comp, \uart_rx_inst|po_data[0]~feeder , uart_rx_inst|po_data[0]~feeder, uart_sdram, 1 +instance = comp, \uart_rx_inst|po_data[0] , uart_rx_inst|po_data[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a[9] , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|ram_address_a[9], uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0, uart_sdram, 1 +instance = comp, \uart_rx_inst|po_data[1]~feeder , uart_rx_inst|po_data[1]~feeder, uart_sdram, 1 +instance = comp, \uart_rx_inst|po_data[1] , uart_rx_inst|po_data[1], uart_sdram, 1 +instance = comp, \uart_rx_inst|po_data[2]~feeder , uart_rx_inst|po_data[2]~feeder, uart_sdram, 1 +instance = comp, \uart_rx_inst|po_data[2] , uart_rx_inst|po_data[2], uart_sdram, 1 +instance = comp, \uart_rx_inst|po_data[3]~feeder , uart_rx_inst|po_data[3]~feeder, uart_sdram, 1 +instance = comp, \uart_rx_inst|po_data[3] , uart_rx_inst|po_data[3], uart_sdram, 1 +instance = comp, \uart_rx_inst|po_data[4]~feeder , uart_rx_inst|po_data[4]~feeder, uart_sdram, 1 +instance = comp, \uart_rx_inst|po_data[4] , uart_rx_inst|po_data[4], uart_sdram, 1 +instance = comp, \uart_rx_inst|po_data[5]~feeder , uart_rx_inst|po_data[5]~feeder, uart_sdram, 1 +instance = comp, \uart_rx_inst|po_data[5] , uart_rx_inst|po_data[5], uart_sdram, 1 +instance = comp, \uart_rx_inst|po_data[6]~feeder , uart_rx_inst|po_data[6]~feeder, uart_sdram, 1 +instance = comp, \uart_rx_inst|po_data[6] , uart_rx_inst|po_data[6], uart_sdram, 1 +instance = comp, \uart_rx_inst|po_data[7] , uart_rx_inst|po_data[7], uart_sdram, 1 +instance = comp, \~GND , ~GND, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_ack, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|wr_sdram_en, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9 , sdram_top_inst|fifo_ctrl_inst|wr_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a9, uart_sdram, 1 +instance = comp, \sys_clk~inputclkctrl , sys_clk~inputclkctrl, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[0]~13 , uart_tx_inst|baud_cnt[0]~13, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[11]~35 , uart_tx_inst|baud_cnt[11]~35, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[11] , uart_tx_inst|baud_cnt[11], uart_sdram, 1 +instance = comp, \uart_tx_inst|Equal1~0 , uart_tx_inst|Equal1~0, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[9]~31 , uart_tx_inst|baud_cnt[9]~31, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[9] , uart_tx_inst|baud_cnt[9], uart_sdram, 1 +instance = comp, \uart_tx_inst|Equal1~1 , uart_tx_inst|Equal1~1, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[1]~15 , uart_tx_inst|baud_cnt[1]~15, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[1] , uart_tx_inst|baud_cnt[1], uart_sdram, 1 +instance = comp, \uart_tx_inst|Equal1~2 , uart_tx_inst|Equal1~2, uart_sdram, 1 +instance = comp, \fifo_read_inst|tx_flag , fifo_read_inst|tx_flag, uart_sdram, 1 +instance = comp, \uart_tx_inst|always3~0 , uart_tx_inst|always3~0, uart_sdram, 1 +instance = comp, \uart_tx_inst|bit_cnt[1]~2 , uart_tx_inst|bit_cnt[1]~2, uart_sdram, 1 +instance = comp, \uart_tx_inst|bit_cnt[1] , uart_tx_inst|bit_cnt[1], uart_sdram, 1 +instance = comp, \uart_tx_inst|bit_cnt[2]~3 , uart_tx_inst|bit_cnt[2]~3, uart_sdram, 1 +instance = comp, \uart_tx_inst|bit_cnt[2] , uart_tx_inst|bit_cnt[2], uart_sdram, 1 +instance = comp, \uart_tx_inst|always0~1 , uart_tx_inst|always0~1, uart_sdram, 1 +instance = comp, \uart_tx_inst|work_en~0 , uart_tx_inst|work_en~0, uart_sdram, 1 +instance = comp, \uart_tx_inst|work_en , uart_tx_inst|work_en, uart_sdram, 1 +instance = comp, \uart_tx_inst|always1~0 , uart_tx_inst|always1~0, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[0] , uart_tx_inst|baud_cnt[0], uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[2]~17 , uart_tx_inst|baud_cnt[2]~17, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[2] , uart_tx_inst|baud_cnt[2], uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[5]~23 , uart_tx_inst|baud_cnt[5]~23, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[5] , uart_tx_inst|baud_cnt[5], uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[6]~25 , uart_tx_inst|baud_cnt[6]~25, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[6] , uart_tx_inst|baud_cnt[6], uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[7]~27 , uart_tx_inst|baud_cnt[7]~27, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[7] , uart_tx_inst|baud_cnt[7], uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[8]~29 , uart_tx_inst|baud_cnt[8]~29, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[8] , uart_tx_inst|baud_cnt[8], uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[10]~33 , uart_tx_inst|baud_cnt[10]~33, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[10] , uart_tx_inst|baud_cnt[10], uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[12]~37 , uart_tx_inst|baud_cnt[12]~37, uart_sdram, 1 +instance = comp, \uart_tx_inst|baud_cnt[12] , uart_tx_inst|baud_cnt[12], uart_sdram, 1 +instance = comp, \uart_tx_inst|Equal2~0 , uart_tx_inst|Equal2~0, uart_sdram, 1 +instance = comp, \uart_tx_inst|Equal2~1 , uart_tx_inst|Equal2~1, uart_sdram, 1 +instance = comp, \uart_tx_inst|bit_flag , uart_tx_inst|bit_flag, uart_sdram, 1 +instance = comp, \uart_tx_inst|always0~0 , uart_tx_inst|always0~0, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|valid_rreq, uart_sdram, 1 +instance = comp, \sdram_dq[0]~input , sdram_dq[0]~input, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[0] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_ack~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[0]~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|counter5a0~_wirecell, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|rdptr_g1p|_~0, uart_sdram, 1 +instance = comp, \sdram_dq[1]~input , sdram_dq[1]~input, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[1] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[1]~6, uart_sdram, 1 +instance = comp, \sdram_dq[2]~input , sdram_dq[2]~input, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[2] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[2]~4, uart_sdram, 1 +instance = comp, \sdram_dq[3]~input , sdram_dq[3]~input, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[3] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[3], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[3]~2, uart_sdram, 1 +instance = comp, \sdram_dq[4]~input , sdram_dq[4]~input, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[4] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[4], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[4]~1, uart_sdram, 1 +instance = comp, \sdram_dq[5]~input , sdram_dq[5]~input, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[5] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[5], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[5]~0, uart_sdram, 1 +instance = comp, \sdram_dq[6]~input , sdram_dq[6]~input, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[6] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[6], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[6]~3, uart_sdram, 1 +instance = comp, \sdram_dq[7]~input , sdram_dq[7]~input, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[7] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_data_reg[7], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|rd_sdram_data[7]~7, uart_sdram, 1 +instance = comp, \sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0 , sdram_top_inst|fifo_ctrl_inst|rd_fifo_data|dcfifo_component|auto_generated|fifo_ram|ram_block11a0, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita0, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[0], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita1, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[1], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita2, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[2], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita3, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[3], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita4, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[4], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita5, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[5], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita6, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[6], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita7, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[7], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita8, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[8], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_comb_bita9, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|wr_ptr|counter_reg_bit[9], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita0, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[0], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita1, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[1], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita2, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[2], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita3, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[3], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita4, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[4], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita5, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[5], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita6, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[6], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita7, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[7], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita8, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[8], uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9 , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_comb_bita9, uart_sdram, 1 +instance = comp, \fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9] , fifo_read_inst|read_fifo_inst|scfifo_component|auto_generated|dpfifo|rd_ptr_count|counter_reg_bit[9], uart_sdram, 1 +instance = comp, \uart_tx_inst|tx~4 , uart_tx_inst|tx~4, uart_sdram, 1 +instance = comp, \uart_tx_inst|tx~3 , uart_tx_inst|tx~3, uart_sdram, 1 +instance = comp, \uart_tx_inst|tx~5 , uart_tx_inst|tx~5, uart_sdram, 1 +instance = comp, \uart_tx_inst|tx , uart_tx_inst|tx, uart_sdram, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl , clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[1] , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[1] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[1] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector2~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_TRF, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|Selector0~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_AR, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[1] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0 , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[2] , sdram_top_inst|sdram_ctrl_inst|sdram_a_ref_inst|aref_cmd[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~17, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_PRE, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|WideOr5, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[2] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_cmd[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[2] , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector5~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector5~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[0] , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_cmd[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector6~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector6~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[0] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_cmd[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector7~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Equal0~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector21~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[0] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~6, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[3]~3, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[0] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[0], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~5, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[1] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref~4, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[2] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|cnt_init_aref[2], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~15, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16 , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state~16, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_state.INIT_MRS, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba[1] , sdram_top_inst|sdram_ctrl_inst|sdram_init_inst|init_ba[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector9~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector6~2, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba[1] , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_ba[1], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector22~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|WideOr7~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0 , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|Selector11~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[10] , sdram_top_inst|sdram_ctrl_inst|sdram_read_inst|read_addr[10], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state~16, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_state.WR_ACTIVE, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1 , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|Selector10~1, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr[10] , sdram_top_inst|sdram_ctrl_inst|sdram_write_inst|write_addr[10], uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~0, uart_sdram, 1 +instance = comp, \sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1 , sdram_top_inst|sdram_ctrl_inst|sdram_arbit_inst|Selector12~1, uart_sdram, 1 +instance = comp, \sdram_dq[8]~input , sdram_dq[8]~input, uart_sdram, 1 +instance = comp, \sdram_dq[9]~input , sdram_dq[9]~input, uart_sdram, 1 +instance = comp, \sdram_dq[10]~input , sdram_dq[10]~input, uart_sdram, 1 +instance = comp, \sdram_dq[11]~input , sdram_dq[11]~input, uart_sdram, 1 +instance = comp, \sdram_dq[12]~input , sdram_dq[12]~input, uart_sdram, 1 +instance = comp, \sdram_dq[13]~input , sdram_dq[13]~input, uart_sdram, 1 +instance = comp, \sdram_dq[14]~input , sdram_dq[14]~input, uart_sdram, 1 +instance = comp, \sdram_dq[15]~input , sdram_dq[15]~input, uart_sdram, 1 diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_v.sdo b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_v.sdo new file mode 100644 index 0000000..5006d42 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/simulation/modelsim/uart_sdram_v.sdo @@ -0,0 +1,19618 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "uart_sdram") + (DATE "06/02/2023 04:26:31") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1692:1692:1692) (1583:1583:1583)) + (PORT d[1] (1627:1627:1627) (1518:1518:1518)) + (PORT d[2] (1737:1737:1737) (1611:1611:1611)) + (PORT d[3] (1724:1724:1724) (1602:1602:1602)) + (PORT d[4] (1667:1667:1667) (1555:1555:1555)) + (PORT d[5] (1663:1663:1663) (1554:1554:1554)) + (PORT d[6] (1729:1729:1729) (1606:1606:1606)) + (PORT d[7] (1695:1695:1695) (1579:1579:1579)) + (PORT clk (2276:2276:2276) (2303:2303:2303)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1303:1303:1303) (1270:1270:1270)) + (PORT d[1] (1383:1383:1383) (1337:1337:1337)) + (PORT d[2] (986:986:986) (980:980:980)) + (PORT d[3] (1229:1229:1229) (1175:1175:1175)) + (PORT d[4] (1022:1022:1022) (1011:1011:1011)) + (PORT d[5] (970:970:970) (967:967:967)) + (PORT d[6] (1276:1276:1276) (1208:1208:1208)) + (PORT d[7] (1337:1337:1337) (1302:1302:1302)) + (PORT d[8] (983:983:983) (981:981:981)) + (PORT d[9] (979:979:979) (977:977:977)) + (PORT clk (2272:2272:2272) (2298:2298:2298)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2060:2060:2060) (1886:1886:1886)) + (PORT clk (2272:2272:2272) (2298:2298:2298)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2276:2276:2276) (2303:2303:2303)) + (PORT d[0] (2767:2767:2767) (2600:2600:2600)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2277:2277:2277) (2304:2304:2304)) + (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2277:2277:2277) (2304:2304:2304)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2277:2277:2277) (2304:2304:2304)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2277:2277:2277) (2304:2304:2304)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (989:989:989) (979:979:979)) + (PORT d[1] (974:974:974) (952:952:952)) + (PORT d[2] (1375:1375:1375) (1321:1321:1321)) + (PORT d[3] (1735:1735:1735) (1635:1635:1635)) + (PORT d[4] (974:974:974) (965:965:965)) + (PORT d[5] (1768:1768:1768) (1761:1761:1761)) + (PORT d[6] (1757:1757:1757) (1674:1674:1674)) + (PORT d[7] (1328:1328:1328) (1287:1287:1287)) + (PORT d[8] (1003:1003:1003) (986:986:986)) + (PORT d[9] (1472:1472:1472) (1376:1376:1376)) + (PORT clk (2226:2226:2226) (2212:2212:2212)) + (PORT ena (2597:2597:2597) (2442:2442:2442)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + (HOLD ena (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (2226:2226:2226) (2212:2212:2212)) + (PORT d[0] (2597:2597:2597) (2442:2442:2442)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2227:2227:2227) (2213:2213:2213)) + (IOPATH (posedge clk) pulse (0:0:0) (3251:3251:3251)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2227:2227:2227) (2213:2213:2213)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|FIFOram\|altsyncram1\|ram_block2a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2227:2227:2227) (2213:2213:2213)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (850:850:850) (820:820:820)) + (PORT datab (539:539:539) (560:560:560)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (983:983:983) (956:956:956)) + (PORT datab (1005:1005:1005) (982:982:982)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1617:1617:1617) (1564:1564:1564)) + (PORT datab (538:538:538) (569:569:569)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (532:532:532) (571:571:571)) + (PORT datab (866:866:866) (831:831:831)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (462:462:462)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[5\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (464:464:464)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (449:449:449)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (629:629:629)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (863:863:863) (845:845:845)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~26) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita1) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (611:611:611)) + (PORT datab (956:956:956) (934:934:934)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita2) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (449:449:449)) + (PORT datab (955:955:955) (933:933:933)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita3) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (458:458:458)) + (PORT datab (955:955:955) (933:933:933)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita4) + (DELAY + (ABSOLUTE + (PORT dataa (577:577:577) (600:600:600)) + (PORT datab (955:955:955) (932:932:932)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita5) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (614:614:614)) + (PORT datab (953:953:953) (931:931:931)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita6) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (613:613:613)) + (PORT datab (953:953:953) (930:930:930)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita7) + (DELAY + (ABSOLUTE + (PORT dataa (842:842:842) (823:823:823)) + (PORT datab (952:952:952) (929:929:929)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita8) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (446:446:446)) + (PORT datab (952:952:952) (929:929:929)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita9) + (DELAY + (ABSOLUTE + (PORT datab (362:362:362) (439:439:439)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Add2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5937:5937:5937) (5718:5718:5718)) + (PORT sclr (1663:1663:1663) (1715:1715:1715)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5942:5942:5942) (5724:5724:5724)) + (PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5942:5942:5942) (5724:5724:5724)) + (PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5942:5942:5942) (5724:5724:5724)) + (PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5942:5942:5942) (5724:5724:5724)) + (PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[16\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5942:5942:5942) (5724:5724:5724)) + (PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[17\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5942:5942:5942) (5724:5724:5724)) + (PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[18\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5942:5942:5942) (5724:5724:5724)) + (PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE data_num\[19\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) 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(PORT sclr (1618:1618:1618) (1666:1666:1666)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~0) + (DELAY + (ABSOLUTE + (PORT datab (542:542:542) (573:573:573)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (615:615:615) (623:623:623)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE 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(IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (598:598:598)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (620:620:620) (629:629:629)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (627:627:627)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (937:937:937) (942:942:942)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~18) + (DELAY + (ABSOLUTE + (PORT datab (1008:1008:1008) (980:980:980)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~20) + (DELAY + (ABSOLUTE + (PORT dataa (972:972:972) (958:958:958)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~22) + (DELAY + (ABSOLUTE + (PORT datab (912:912:912) (910:910:910)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~24) + (DELAY + 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(IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Add1\~30) + (DELAY + (ABSOLUTE + (PORT datad (555:555:555) (569:569:569)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout 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(73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[0\]\~24) + (DELAY + (ABSOLUTE + (PORT dataa (1892:1892:1892) (1762:1762:1762)) + (PORT datab (341:341:341) (422:422:422)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[1\]\~26) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (430:430:430)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[2\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (433:433:433)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[3\]\~30) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (424:424:424)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[4\]\~32) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (421:421:421)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[5\]\~34) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[6\]\~36) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[7\]\~38) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (430:430:430)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[8\]\~40) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (419:419:419)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[9\]\~42) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (429:429:429)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[10\]\~44) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (421:421:421)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[11\]\~46) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (431:431:431)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[12\]\~48) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (418:418:418)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[13\]\~50) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (421:421:421)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[14\]\~52) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (420:420:420)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[15\]\~54) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (432:432:432)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[16\]\~56) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (421:421:421)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[17\]\~58) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (431:431:431)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[18\]\~60) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (434:434:434)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[19\]\~62) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[20\]\~64) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[21\]\~66) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[22\]\~68) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE data_num\[23\]\~70) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (436:436:436)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|cnt_read\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5651:5651:5651) (5409:5409:5409)) + (PORT sclr (930:930:930) (992:992:992)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (433:433:433)) + (PORT datab (369:369:369) (468:468:468)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (421:421:421)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datad (324:324:324) (411:411:411)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (883:883:883)) + (PORT datab (340:340:340) (419:419:419)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (421:421:421)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (340:340:340) (420:420:420)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[3\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (433:433:433)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[5\]\~20) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (435:435:435)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[8\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (423:423:423)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|cnt_read\[9\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (344:344:344) (427:427:427)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[4\]\~21) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (448:448:448)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT asdata (1686:1686:1686) (1628:1628:1628)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1174:1174:1174) (1083:1083:1083)) + (PORT datab (1182:1182:1182) (1098:1098:1098)) + (PORT datad (292:292:292) (362:362:362)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5192:5192:5192) (4949:4949:4949)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (788:788:788) (716:716:716)) + (PORT datab (412:412:412) (512:512:512)) + (PORT datac (784:784:784) (707:707:707)) + (PORT datad (350:350:350) (465:465:465)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Mux0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (993:993:993) (923:923:923)) + (PORT datab (928:928:928) (877:877:877)) + (PORT datac (1148:1148:1148) (1069:1069:1069)) + (PORT datad (1275:1275:1275) (1239:1239:1239)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~0) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (523:523:523)) + (PORT datab (888:888:888) (788:788:788)) + (PORT datac (1486:1486:1486) (1370:1370:1370)) + (PORT datad (369:369:369) (468:468:468)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~1) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (523:523:523)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (773:773:773) (696:696:696)) + (PORT datad (370:370:370) (470:470:470)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~2) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (941:941:941)) + (PORT datab (369:369:369) (470:470:470)) + (PORT datac (1111:1111:1111) (997:997:997)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5192:5192:5192) (4949:4949:4949)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (337:337:337) (421:421:421)) + (PORT datab (643:643:643) (658:658:658)) + (PORT datac (1220:1220:1220) (1194:1194:1194)) + (PORT datad (335:335:335) (438:438:438)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\~0) + (DELAY + (ABSOLUTE + (PORT datac (513:513:513) (554:554:554)) + (PORT datad (540:540:540) (561:561:561)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|WideOr5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1734:1734:1734) (1630:1630:1630)) + (PORT datad (1627:1627:1627) (1547:1547:1547)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (494:494:494)) + (PORT datab (370:370:370) (453:453:453)) + (PORT datac (244:244:244) (275:275:275)) + (PORT datad (988:988:988) (986:986:986)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (448:448:448)) + (PORT datab (411:411:411) (519:519:519)) + (PORT datac (901:901:901) (900:900:900)) + (PORT datad (1137:1137:1137) (1084:1084:1084)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector21\~0) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (493:493:493)) + (PORT datab (284:284:284) (316:316:316)) + (PORT datac (328:328:328) (411:411:411)) + (PORT datad (322:322:322) (393:393:393)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (397:397:397) (525:525:525)) + (PORT datac (327:327:327) (430:430:430)) + (PORT datad (369:369:369) (468:468:468)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Add1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (526:526:526)) + (PORT datab (372:372:372) (473:473:473)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (369:369:369) (468:468:468)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[3\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (292:292:292) (329:329:329)) + (PORT datad (293:293:293) (324:324:324)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT ena (1037:1037:1037) (1012:1012:1012)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (463:463:463)) + (PORT datab (369:369:369) (452:452:452)) + (PORT datac (329:329:329) (413:413:413)) + (PORT datad (330:330:330) (408:408:408)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE read_valid) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5631:5631:5631) (5380:5380:5380)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~0) + (DELAY + (ABSOLUTE + (PORT datac (245:245:245) (276:276:276)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1614:1614:1614) (1562:1562:1562)) + (PORT datab (1002:1002:1002) (983:983:983)) + (PORT datac (236:236:236) (261:261:261)) + (PORT datad (247:247:247) (272:272:272)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_TMRD) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.IDLE\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1262:1262:1262) (1239:1239:1239)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1859:1859:1859)) + (PORT ena (1080:1080:1080) (1064:1064:1064)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT datab (937:937:937) (945:945:945)) + (PORT datad (962:962:962) (949:949:949)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~0) + (DELAY + (ABSOLUTE + (PORT dataa (569:569:569) (608:608:608)) + (PORT datab (575:575:575) (608:608:608)) + (PORT datac (914:914:914) (907:907:907)) + (PORT datad (923:923:923) (933:933:933)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~1) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (615:615:615)) + (PORT datab (369:369:369) (452:452:452)) + (PORT datac (311:311:311) (400:400:400)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~2) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (450:450:450)) + (PORT datab (368:368:368) (450:450:450)) + (PORT datac (320:320:320) (399:399:399)) + (PORT datad (329:329:329) (406:406:406)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~3) + (DELAY + (ABSOLUTE + (PORT dataa (844:844:844) (785:785:785)) + (PORT datab (873:873:873) (799:799:799)) + (PORT datac (940:940:940) (927:927:927)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5949:5949:5949) (5747:5747:5747)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (580:580:580) (610:610:610)) + (PORT datab (367:367:367) (450:450:450)) + (PORT datac (308:308:308) (397:397:397)) + (PORT datad (328:328:328) (401:401:401)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (447:447:447)) + (PORT datab (280:280:280) (305:305:305)) + (PORT datac (327:327:327) (411:411:411)) + (PORT datad (321:321:321) (392:392:392)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (430:430:430)) + (PORT datac (959:959:959) (952:952:952)) + (PORT datad (1282:1282:1282) (1257:1257:1257)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~2) + (DELAY + (ABSOLUTE + (PORT datac (449:449:449) (435:435:435)) + (PORT datad (313:313:313) (359:359:359)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT asdata (983:983:983) (1016:1016:1016)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (312:312:312) (400:400:400)) + (PORT datad (856:856:856) (810:810:810)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT asdata (1704:1704:1704) (1676:1676:1676)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (439:439:439)) + (PORT datac (311:311:311) (399:399:399)) + (PORT datad (855:855:855) (809:809:809)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (1328:1328:1328) (1293:1293:1293)) + (PORT datab (1350:1350:1350) (1302:1302:1302)) + (PORT datac (1301:1301:1301) (1278:1278:1278)) + (PORT datad (255:255:255) (280:280:280)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datab (1320:1320:1320) (1297:1297:1297)) + (PORT datac (239:239:239) (265:265:265)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT dataa (951:951:951) (970:970:970)) + (PORT datab (968:968:968) (907:907:907)) + (PORT datad (969:969:969) (971:971:971)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datab (970:970:970) (910:910:910)) + (PORT datad (970:970:970) (972:972:972)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT datab (354:354:354) (440:440:440)) + (PORT datac (322:322:322) (400:400:400)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (632:632:632)) + (PORT datac (354:354:354) (440:440:440)) + (PORT datad (340:340:340) (421:421:421)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT dataa (1333:1333:1333) (1273:1273:1273)) + (PORT datac (330:330:330) (434:434:434)) + (PORT datad (257:257:257) (283:283:283)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (512:512:512) (551:551:551)) + (PORT datad (843:843:843) (794:794:794)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (959:959:959)) + (PORT datab (943:943:943) (935:935:935)) + (PORT datac (501:501:501) (485:485:485)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT asdata (1737:1737:1737) (1682:1682:1682)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (2053:2053:2053) (1939:1939:1939)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (859:859:859) (858:858:858)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datac (331:331:331) (435:435:435)) + (PORT datad (258:258:258) (283:283:283)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (313:313:313) (402:402:402)) + (PORT datad (526:526:526) (557:557:557)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT datac (313:313:313) (402:402:402)) + (PORT datad (525:525:525) (557:557:557)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (PORT datab (360:360:360) (437:437:437)) + (PORT datac (320:320:320) (398:398:398)) + (PORT datad (320:320:320) (391:391:391)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5631:5631:5631) (5380:5380:5380)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5631:5631:5631) (5380:5380:5380)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5631:5631:5631) (5380:5380:5380)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5631:5631:5631) (5380:5380:5380)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (PORT datab (359:359:359) (435:435:435)) + (PORT datac (319:319:319) (396:396:396)) + (PORT datad (509:509:509) (537:537:537)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (445:445:445)) + (PORT datab (358:358:358) (435:435:435)) + (PORT datac (318:318:318) (396:396:396)) + (PORT datad (320:320:320) (390:390:390)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE cnt_wait\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1875:1875:1875)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5452:5452:5452) (5229:5229:5229)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (589:589:589)) + (PORT datab (362:362:362) (439:439:439)) + (PORT datac (321:321:321) (399:399:399)) + (PORT datad (322:322:322) (392:392:392)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (314:314:314)) + (PORT datab (276:276:276) (300:300:300)) + (PORT datac (239:239:239) (265:265:265)) + (PORT datad (831:831:831) (765:765:765)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE read_valid\~0) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (819:819:819)) + (PORT datab (838:838:838) (798:798:798)) + (PORT datac (937:937:937) (883:883:883)) + (PORT datad (322:322:322) (392:392:392)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE read_valid\~1) + (DELAY + (ABSOLUTE + (PORT dataa (910:910:910) (863:863:863)) + (PORT datab (929:929:929) (864:864:864)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (605:605:605)) + (PORT datab (363:363:363) (440:440:440)) + (PORT datad (507:507:507) (489:489:489)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (634:634:634) (642:642:642)) + (PORT datab (400:400:400) (511:511:511)) + (PORT datac (361:361:361) (468:468:468)) + (PORT datad (309:309:309) (389:389:389)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (378:378:378) (468:468:468)) + (PORT datac (310:310:310) (401:401:401)) + (PORT datad (303:303:303) (376:376:376)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~2) + (DELAY + (ABSOLUTE + (PORT datab (279:279:279) (304:304:304)) + (PORT datac (348:348:348) (427:427:427)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (912:912:912) (923:923:923)) + (PORT datab (981:981:981) (963:963:963)) + (PORT datad (833:833:833) (777:777:777)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (452:452:452)) + (PORT datab (353:353:353) (442:442:442)) + (PORT datac (312:312:312) (401:401:401)) + (PORT datad (312:312:312) (392:392:392)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT asdata (1997:1997:1997) (1917:1917:1917)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (PORT ena (2086:2086:2086) (1974:1974:1974)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (462:462:462)) + (PORT datab (1255:1255:1255) (1234:1234:1234)) + (PORT datad (1253:1253:1253) (1214:1214:1214)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (2163:2163:2163) (2083:2083:2083)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1708:1708:1708) (1615:1615:1615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (584:584:584) (619:619:619)) + (PORT datab (570:570:570) (596:596:596)) + (PORT datad (331:331:331) (405:405:405)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (461:461:461)) + (PORT datab (593:593:593) (620:620:620)) + (PORT datad (564:564:564) (581:581:581)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT datac (447:447:447) (431:431:431)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1271:1271:1271) (1244:1244:1244)) + (PORT datab (969:969:969) (963:963:963)) + (PORT datad (323:323:323) (393:393:393)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (556:556:556) (590:590:590)) + (PORT datab (360:360:360) (436:436:436)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (368:368:368) (458:458:458)) + (PORT datab (361:361:361) (438:438:438)) + (PORT datad (321:321:321) (392:392:392)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (814:814:814) (765:765:765)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1218:1218:1218) (1130:1130:1130)) + (PORT datab (1264:1264:1264) (1171:1171:1171)) + (PORT datac (1253:1253:1253) (1164:1164:1164)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (445:445:445)) + (PORT datab (366:366:366) (449:449:449)) + (PORT datad (572:572:572) (592:592:592)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (647:647:647) (660:660:660)) + (PORT datab (368:368:368) (451:451:451)) + (PORT datad (338:338:338) (419:419:419)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (2530:2530:2530) (2385:2385:2385)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT ena (1720:1720:1720) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (772:772:772)) + (PORT datab (484:484:484) (468:468:468)) + (PORT datad (353:353:353) (427:427:427)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (395:395:395) (483:483:483)) + (PORT datab (626:626:626) (638:638:638)) + (PORT datad (564:564:564) (583:583:583)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (613:613:613)) + (PORT datab (386:386:386) (463:463:463)) + (PORT datad (560:560:560) (582:582:582)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (515:515:515)) + (PORT datab (548:548:548) (586:586:586)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (382:382:382)) + (PORT datac (780:780:780) (746:746:746)) + (PORT datad (855:855:855) (796:796:796)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1358:1358:1358) (1307:1307:1307)) + (PORT datab (1780:1780:1780) (1689:1689:1689)) + (PORT datad (499:499:499) (523:523:523)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (580:580:580)) + (PORT datab (947:947:947) (961:961:961)) + (PORT datad (1275:1275:1275) (1245:1245:1245)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (1312:1312:1312) (1309:1309:1309)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (955:955:955) (923:923:923)) + (PORT datab (368:368:368) (451:451:451)) + (PORT datad (321:321:321) (391:391:391)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (976:976:976) (910:910:910)) + (PORT datad (515:515:515) (546:546:546)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (1349:1349:1349) (1318:1318:1318)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (545:545:545) (584:584:584)) + (PORT datab (1039:1039:1039) (1008:1008:1008)) + (PORT datad (1278:1278:1278) (1236:1236:1236)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (462:462:462)) + (PORT datab (320:320:320) (357:357:357)) + (PORT datac (337:337:337) (425:425:425)) + (PORT datad (338:338:338) (418:418:418)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (602:602:602)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (302:302:302) (386:386:386)) + (PORT datad (302:302:302) (379:379:379)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (343:343:343) (425:425:425)) + (PORT datac (302:302:302) (386:386:386)) + (PORT datad (302:302:302) (379:379:379)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (433:433:433)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (789:789:789)) + (PORT datab (276:276:276) (300:300:300)) + (PORT datac (236:236:236) (261:261:261)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~5) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (435:435:435)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (303:303:303) (379:379:379)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (600:600:600)) + (PORT datab (341:341:341) (424:424:424)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[8\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (901:901:901) (842:842:842)) + (PORT datab (837:837:837) (797:797:797)) + (PORT datac (859:859:859) (812:812:812)) + (PORT datad (849:849:849) (802:802:802)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[15\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (842:842:842)) + (PORT datab (839:839:839) (799:799:799)) + (PORT datac (861:861:861) (813:813:813)) + (PORT datad (851:851:851) (803:803:803)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[15\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (552:552:552) (512:512:512)) + (PORT datab (1006:1006:1006) (986:986:986)) + (PORT datad (935:935:935) (923:923:923)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[14\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (982:982:982)) + (PORT datab (486:486:486) (466:466:466)) + (PORT datad (943:943:943) (934:934:934)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[13\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (980:980:980)) + (PORT datab (740:740:740) (682:682:682)) + (PORT datad (945:945:945) (936:936:936)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[12\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (979:979:979) (981:981:981)) + (PORT datab (540:540:540) (498:498:498)) + (PORT datad (944:944:944) (936:936:936)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[9\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (332:332:332) (381:381:381)) + (PORT datab (878:878:878) (805:805:805)) + (PORT datad (290:290:290) (317:317:317)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[11\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (381:381:381)) + (PORT datab (837:837:837) (790:790:790)) + (PORT datad (291:291:291) (319:319:319)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[10\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (381:381:381)) + (PORT datab (828:828:828) (784:784:784)) + (PORT datad (291:291:291) (319:319:319)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[8\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (381:381:381)) + (PORT datab (909:909:909) (833:833:833)) + (PORT datad (292:292:292) (319:319:319)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[7\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (974:974:974) (975:975:975)) + (PORT datab (543:543:543) (505:505:505)) + (PORT datad (950:950:950) (943:943:943)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[6\]\~11) + (DELAY + (ABSOLUTE + (PORT dataa (976:976:976) (977:977:977)) + (PORT datab (544:544:544) (507:507:507)) + (PORT datad (947:947:947) (940:940:940)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[5\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (977:977:977) (978:978:978)) + (PORT datab (489:489:489) (474:474:474)) + (PORT datad (947:947:947) (939:939:939)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[4\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (979:979:979)) + (PORT datab (547:547:547) (510:510:510)) + (PORT datad (946:946:946) (938:938:938)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[3\]\~14) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (484:484:484)) + (PORT datab (1011:1011:1011) (993:993:993)) + (PORT datad (930:930:930) (916:916:916)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[2\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (518:518:518)) + (PORT datab (1011:1011:1011) (993:993:993)) + (PORT datad (930:930:930) (917:917:917)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[1\]\~16) + (DELAY + (ABSOLUTE + (PORT dataa (492:492:492) (485:485:485)) + (PORT datab (1012:1012:1012) (995:995:995)) + (PORT datad (929:929:929) (915:915:915)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE cnt_wait\[0\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (978:978:978) (980:980:980)) + (PORT datab (548:548:548) (511:511:511)) + (PORT datad (945:945:945) (937:937:937)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1326:1326:1326) (1238:1238:1238)) + (PORT datab (1022:1022:1022) (1001:1001:1001)) + (PORT datad (569:569:569) (588:588:588)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (653:653:653)) + (PORT datab (577:577:577) (606:606:606)) + (PORT datad (951:951:951) (933:933:933)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (907:907:907) (914:914:914)) + (PORT datab (588:588:588) (611:611:611)) + (PORT datac (901:901:901) (890:890:890)) + (PORT datad (878:878:878) (878:878:878)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (283:283:283) (316:316:316)) + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (1650:1650:1650) (1527:1527:1527)) + (PORT datad (240:240:240) (258:258:258)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (899:899:899) (917:917:917)) + (PORT datab (987:987:987) (968:968:968)) + (PORT datad (320:320:320) (390:390:390)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb\|data_wire\[2\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (1912:1912:1912) (1751:1751:1751)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (852:852:852)) + (PORT datab (1154:1154:1154) (1044:1044:1044)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (622:622:622) (632:632:632)) + (PORT datab (542:542:542) (574:574:574)) + (PORT datad (1623:1623:1623) (1547:1547:1547)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (535:535:535) (494:494:494)) + (PORT datab (279:279:279) (304:304:304)) + (PORT datac (446:446:446) (417:417:417)) + (PORT datad (298:298:298) (339:339:339)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1320:1320:1320) (1253:1253:1253)) + (PORT datab (366:366:366) (466:466:466)) + (PORT datad (909:909:909) (894:894:894)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (355:355:355) (449:449:449)) + (PORT datab (965:965:965) (948:948:948)) + (PORT datac (1383:1383:1383) (1333:1333:1333)) + (PORT datad (325:325:325) (414:414:414)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (475:475:475)) + (PORT datab (368:368:368) (468:468:468)) + (PORT datac (888:888:888) (879:879:879)) + (PORT datad (881:881:881) (879:879:879)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (872:872:872)) + (PORT datab (343:343:343) (386:386:386)) + (PORT datad (486:486:486) (459:459:459)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (906:906:906) (912:912:912)) + (PORT datab (553:553:553) (585:585:585)) + (PORT datad (542:542:542) (562:562:562)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (995:995:995) (971:971:971)) + (PORT datab (362:362:362) (439:439:439)) + (PORT datad (864:864:864) (838:838:838)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (474:474:474)) + (PORT datab (981:981:981) (954:954:954)) + (PORT datad (874:874:874) (875:875:875)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (379:379:379) (472:472:472)) + (PORT datab (376:376:376) (466:466:466)) + (PORT datac (1231:1231:1231) (1184:1184:1184)) + (PORT datad (361:361:361) (441:441:441)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|rd_flag) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5995:5995:5995) (5789:5789:5789)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (447:447:447)) + (PORT datab (349:349:349) (438:438:438)) + (PORT datac (308:308:308) (398:398:398)) + (PORT datad (311:311:311) (391:391:391)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|cntr_cout\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1329:1329:1329) (1316:1316:1316)) + (PORT datab (922:922:922) (929:929:929)) + (PORT datac (477:477:477) (450:450:450)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (PORT ena (1757:1757:1757) (1679:1679:1679)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (435:435:435)) + (PORT datab (344:344:344) (426:426:426)) + (PORT datac (303:303:303) (387:387:387)) + (PORT datad (305:305:305) (382:382:382)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (343:343:343) (426:426:426)) + (PORT datac (303:303:303) (387:387:387)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (493:493:493) (471:471:471)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (302:302:302) (379:379:379)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|rd_flag\~0) + (DELAY + (ABSOLUTE + (PORT dataa (944:944:944) (882:882:882)) + (PORT datab (999:999:999) (985:985:985)) + (PORT datad (246:246:246) (271:271:271)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT dataa (366:366:366) (464:464:464)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (330:330:330) (432:432:432)) + (PORT datad (266:266:266) (302:302:302)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~13) + (DELAY + (ABSOLUTE + (PORT dataa (1237:1237:1237) (1198:1198:1198)) + (PORT datab (379:379:379) (469:469:469)) + (PORT datac (336:336:336) (426:426:426)) + (PORT datad (329:329:329) (407:407:407)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|start_nedge) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (1291:1291:1291) (1207:1207:1207)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (424:424:424)) + (PORT datad (321:321:321) (392:392:392)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (935:935:935) (945:945:945)) + (PORT datab (330:330:330) (363:363:363)) + (PORT datad (865:865:865) (859:859:859)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1504:1504:1504) (1434:1434:1434)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[7\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1180:1180:1180) (1142:1142:1142)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (323:323:323) (394:394:394)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (873:873:873) (870:870:870)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (542:542:542) (562:562:562)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE tx\~output) + (DELAY + (ABSOLUTE + (PORT i (2462:2462:2462) (2477:2477:2477)) + (IOPATH i o (3336:3336:3336) (3399:3399:3399)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_clk\~output) + (DELAY + (ABSOLUTE + (PORT i (1622:1622:1622) (1573:1573:1573)) + (IOPATH i o (3251:3251:3251) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_cas_n\~output) + (DELAY + (ABSOLUTE + (PORT i (2191:2191:2191) (2040:2040:2040)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_ras_n\~output) + (DELAY + (ABSOLUTE + (PORT i (2334:2334:2334) (2117:2117:2117)) + (IOPATH i o (4708:4708:4708) (4746:4746:4746)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_we_n\~output) + (DELAY + (ABSOLUTE + (PORT i (2385:2385:2385) (2240:2240:2240)) + (IOPATH i o (3291:3291:3291) (3194:3194:3194)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_ba\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3348:3348:3348) (3145:3145:3145)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_ba\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3636:3636:3636) (3398:3398:3398)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2660:2660:2660) (2398:2398:2398)) + (IOPATH i o (3281:3281:3281) (3184:3184:3184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2653:2653:2653) (2401:2401:2401)) + (IOPATH i o (3429:3429:3429) (3366:3366:3366)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2653:2653:2653) (2401:2401:2401)) + (IOPATH i o (3429:3429:3429) (3366:3366:3366)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3335:3335:3335) (3152:3152:3152)) + (IOPATH i o (3429:3429:3429) (3366:3366:3366)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3060:3060:3060) (2762:2762:2762)) + (IOPATH i o (3429:3429:3429) (3366:3366:3366)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3079:3079:3079) (2783:2783:2783)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (4466:4466:4466) (4181:4181:4181)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (4050:4050:4050) (3800:3800:3800)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (4473:4473:4473) (4187:4187:4187)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2666:2666:2666) (2508:2508:2508)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2685:2685:2685) (2509:2509:2509)) + (IOPATH i o (3291:3291:3291) (3194:3194:3194)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2666:2666:2666) (2508:2508:2508)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_addr\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3225:3225:3225) (2988:2988:2988)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1550:1550:1550) (1417:1417:1417)) + (PORT oe (1648:1648:1648) (1586:1586:1586)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1491:1491:1491) (1367:1367:1367)) + (PORT oe (1648:1648:1648) (1586:1586:1586)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1577:1577:1577) (1450:1450:1450)) + (PORT oe (2036:2036:2036) (1919:1919:1919)) + (IOPATH i o (3231:3231:3231) (3134:3134:3134)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1113:1113:1113) (1003:1003:1003)) + (PORT oe (1252:1252:1252) (1208:1208:1208)) + (IOPATH i o (3261:3261:3261) (3164:3164:3164)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1135:1135:1135) (1030:1030:1030)) + (PORT oe (1252:1252:1252) (1208:1208:1208)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1522:1522:1522) (1395:1395:1395)) + (PORT oe (2036:2036:2036) (1919:1919:1919)) + (IOPATH i o (3251:3251:3251) (3154:3154:3154)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1541:1541:1541) (1413:1413:1413)) + (PORT oe (1648:1648:1648) (1586:1586:1586)) + (IOPATH i o (3281:3281:3281) (3184:3184:3184)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1200:1200:1200) (1108:1108:1108)) + (PORT oe (1648:1648:1648) (1586:1586:1586)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1637:1637:1637) (1534:1534:1534)) + (PORT oe (2662:2662:2662) (2485:2485:2485)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + (IOPATH oe o (3433:3433:3433) (3294:3294:3294)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1745:1745:1745) (1590:1590:1590)) + (PORT oe (2255:2255:2255) (2128:2128:2128)) + (IOPATH i o (3281:3281:3281) (3184:3184:3184)) + (IOPATH oe o (3324:3324:3324) (3154:3154:3154)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2059:2059:2059) (1828:1828:1828)) + (PORT oe (1931:1931:1931) (1833:1833:1833)) + (IOPATH i o (3419:3419:3419) (3356:3356:3356)) + (IOPATH oe o (3433:3433:3433) (3294:3294:3294)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2200:2200:2200) (2043:2043:2043)) + (PORT oe (2276:2276:2276) (2145:2145:2145)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + (IOPATH oe o (3433:3433:3433) (3294:3294:3294)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1838:1838:1838) (1674:1674:1674)) + (PORT oe (2316:2316:2316) (2194:2194:2194)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + (IOPATH oe o (3433:3433:3433) (3294:3294:3294)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1495:1495:1495) (1364:1364:1364)) + (PORT oe (2323:2323:2323) (2202:2202:2202)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + (IOPATH oe o (3433:3433:3433) (3294:3294:3294)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1746:1746:1746) (1547:1547:1547)) + (PORT oe (2323:2323:2323) (2202:2202:2202)) + (IOPATH i o (4760:4760:4760) (4817:4817:4817)) + (IOPATH oe o (4805:4805:4805) (4785:4785:4785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE sdram_dq\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1655:1655:1655) (1474:1474:1474)) + (PORT oe (2323:2323:2323) (2202:2202:2202)) + (IOPATH i o (3291:3291:3291) (3218:3218:3218)) + (IOPATH oe o (3335:3335:3335) (3194:3194:3194)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (609:609:609)) + (PORT datab (358:358:358) (434:434:434)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (806:806:806) (852:852:852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (5286:5286:5286) (5286:5286:5286)) + (PORT inclk[0] (2340:2340:2340) (2340:2340:2340)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (2135:2135:2135) (2190:2190:2190)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5631:5631:5631) (5380:5380:5380)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (4719:4719:4719) (4925:4925:4925)) + (PORT datac (1430:1430:1430) (1466:1466:1466)) + (PORT datad (293:293:293) (362:362:362)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2483:2483:2483) (2391:2391:2391)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT datab (349:349:349) (435:435:435)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (443:443:443)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (452:452:452)) + (PORT datab (588:588:588) (611:611:611)) + (PORT datac (312:312:312) (402:402:402)) + (PORT datad (314:314:314) (394:394:394)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (630:630:630) (636:636:636)) + (PORT datab (343:343:343) (427:427:427)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT datac (848:848:848) (818:818:818)) + (PORT datad (530:530:530) (558:558:558)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal1\~3) + (DELAY + (ABSOLUTE + (PORT dataa (638:638:638) (647:647:647)) + (PORT datab (627:627:627) (636:636:636)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (534:534:534) (554:554:554)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (447:447:447)) + (PORT datab (475:475:475) (459:459:459)) + (PORT datac (483:483:483) (457:457:457)) + (PORT datad (237:237:237) (256:256:256)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (453:453:453)) + (PORT datab (589:589:589) (612:612:612)) + (PORT datac (312:312:312) (402:402:402)) + (PORT datad (314:314:314) (394:394:394)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (449:449:449)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1883:1883:1883) (1854:1854:1854)) + (PORT sclr (1155:1155:1155) (1183:1183:1183)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (574:574:574) (613:613:613)) + (PORT datab (625:625:625) (633:633:633)) + (PORT datac (848:848:848) (817:817:817)) + (PORT datad (533:533:533) (552:552:552)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Equal2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (504:504:504)) + (PORT datab (534:534:534) (496:496:496)) + (PORT datac (577:577:577) (599:599:599)) + (PORT datad (240:240:240) (258:258:258)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (430:430:430)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (345:345:345) (427:427:427)) + (PORT datac (304:304:304) (388:388:388)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (461:461:461)) + (PORT datab (305:305:305) (343:343:343)) + (PORT datac (327:327:327) (429:429:429)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_flag) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_flag) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (1718:1718:1718) (1681:1681:1681)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (465:465:465)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a0) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT ena (2467:2467:2467) (2319:2319:2319)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (364:364:364) (463:463:463)) + (PORT datab (2041:2041:2041) (1890:1890:1890)) + (PORT datad (561:561:561) (599:599:599)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (604:604:604) (653:653:653)) + (PORT datab (378:378:378) (467:467:467)) + (PORT datac (318:318:318) (414:414:414)) + (PORT datad (1679:1679:1679) (1566:1566:1566)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (236:236:236) (255:255:255)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (322:322:322) (360:360:360)) + (PORT datad (558:558:558) (589:589:589)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~10) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (645:645:645)) + (PORT datab (380:380:380) (470:470:470)) + (PORT datac (354:354:354) (453:453:453)) + (PORT datad (560:560:560) (592:592:592)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT ena (2467:2467:2467) (2319:2319:2319)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (521:521:521) (498:498:498)) + (PORT datab (397:397:397) (493:493:493)) + (PORT datad (557:557:557) (588:588:588)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (384:384:384) (480:480:480)) + (PORT datab (323:323:323) (361:361:361)) + (PORT datac (352:352:352) (451:451:451)) + (PORT datad (330:330:330) (403:403:403)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (822:822:822) (761:761:761)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (409:409:409) (521:521:521)) + (PORT datad (819:819:819) (773:773:773)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (950:950:950)) + (PORT datab (369:369:369) (467:467:467)) + (PORT datac (364:364:364) (472:472:472)) + (PORT datad (357:357:357) (447:447:447)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1141:1141:1141) (1149:1149:1149)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (497:497:497)) + (PORT datab (367:367:367) (465:465:465)) + (PORT datac (364:364:364) (472:472:472)) + (PORT datad (819:819:819) (773:773:773)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8\~0) + (DELAY + (ABSOLUTE + (PORT datad (432:432:432) (405:405:405)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (398:398:398) (497:497:497)) + (PORT datab (368:368:368) (466:466:466)) + (PORT datac (362:362:362) (469:469:469)) + (PORT datad (818:818:818) (772:772:772)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10\~0) + (DELAY + (ABSOLUTE + (PORT datab (375:375:375) (469:469:469)) + (PORT datad (457:457:457) (426:426:426)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (498:498:498) (478:478:478)) + (PORT datad (333:333:333) (424:424:424)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT datab (372:372:372) (465:465:465)) + (PORT datac (311:311:311) (402:402:402)) + (PORT datad (790:790:790) (780:780:780)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1306:1306:1306) (1246:1246:1246)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT datab (338:338:338) (416:416:416)) + (PORT datac (898:898:898) (891:891:891)) + (PORT datad (1121:1121:1121) (1075:1075:1075)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|parity9) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT ena (2467:2467:2467) (2319:2319:2319)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (601:601:601) (649:649:649)) + (PORT datab (376:376:376) (465:465:465)) + (PORT datac (317:317:317) (412:412:412)) + (PORT datad (1677:1677:1677) (1565:1565:1565)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (382:382:382) (478:478:478)) + (PORT datab (322:322:322) (360:360:360)) + (PORT datac (351:351:351) (450:450:450)) + (PORT datad (329:329:329) (403:403:403)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (410:410:410) (523:523:523)) + (PORT datab (860:860:860) (816:816:816)) + (PORT datad (356:356:356) (446:446:446)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (778:778:778) (859:859:859)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1306:1306:1306) (1246:1246:1246)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (354:354:354) (449:449:449)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (431:431:431)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (432:432:432)) + (PORT datab (341:341:341) (423:423:423)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (302:302:302) (378:378:378)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (467:467:467)) + (PORT datab (361:361:361) (458:458:458)) + (PORT datac (320:320:320) (414:414:414)) + (PORT datad (322:322:322) (405:405:405)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~8) + (DELAY + (ABSOLUTE + (PORT dataa (876:876:876) (867:867:867)) + (PORT datab (589:589:589) (622:622:622)) + (PORT datac (501:501:501) (510:510:510)) + (PORT datad (498:498:498) (472:472:472)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (333:333:333) (425:425:425)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1306:1306:1306) (1246:1246:1246)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (991:991:991) (1016:1016:1016)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1148:1148:1148) (1098:1098:1098)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (789:789:789) (779:779:779)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1306:1306:1306) (1246:1246:1246)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (332:332:332) (406:406:406)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1283:1283:1283) (1215:1215:1215)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (322:322:322) (393:393:393)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1145:1145:1145) (1104:1104:1104)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (617:617:617)) + (PORT datab (341:341:341) (423:423:423)) + (PORT datac (309:309:309) (398:398:398)) + (PORT datad (521:521:521) (553:553:553)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (358:358:358) (448:448:448)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1141:1141:1141) (1149:1149:1149)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (2366:2366:2366) (2261:2261:2261)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT asdata (1242:1242:1242) (1212:1212:1212)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (437:437:437)) + (PORT datab (295:295:295) (332:332:332)) + (PORT datac (312:312:312) (402:402:402)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (1372:1372:1372) (1359:1359:1359)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1141:1141:1141) (1149:1149:1149)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1256:1256:1256) (1213:1213:1213)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (332:332:332) (406:406:406)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (433:433:433)) + (PORT datab (295:295:295) (331:331:331)) + (PORT datac (312:312:312) (402:402:402)) + (PORT datad (294:294:294) (363:363:363)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (296:296:296) (334:334:334)) + (PORT datad (1292:1292:1292) (1256:1256:1256)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (803:803:803) (886:886:886)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT ena (2467:2467:2467) (2319:2319:2319)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1705:1705:1705) (1625:1625:1625)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT asdata (821:821:821) (912:912:912)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (PORT ena (2467:2467:2467) (2319:2319:2319)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT asdata (1711:1711:1711) (1670:1670:1670)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (502:502:502)) + (PORT datab (361:361:361) (437:437:437)) + (PORT datad (1289:1289:1289) (1253:1253:1253)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (403:403:403) (500:500:500)) + (PORT datab (294:294:294) (332:332:332)) + (PORT datac (321:321:321) (399:399:399)) + (PORT datad (1291:1291:1291) (1254:1254:1254)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5\~0) + (DELAY + (ABSOLUTE + (PORT datad (824:824:824) (767:767:767)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (827:827:827) (926:926:926)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1141:1141:1141) (1149:1149:1149)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT asdata (1943:1943:1943) (1841:1841:1841)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (984:984:984) (974:974:974)) + (PORT datab (384:384:384) (461:461:461)) + (PORT datad (328:328:328) (402:402:402)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT datad (364:364:364) (445:445:445)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (PORT ena (1757:1757:1757) (1679:1679:1679)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (662:662:662) (668:668:668)) + (PORT datab (379:379:379) (470:470:470)) + (PORT datad (964:964:964) (921:921:921)) + (IOPATH dataa combout (405:405:405) (407:407:407)) + (IOPATH datab combout (410:410:410) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (1169:1169:1169) (1119:1119:1119)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1141:1141:1141) (1149:1149:1149)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT asdata (2501:2501:2501) (2388:2388:2388)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (552:552:552) (590:590:590)) + (PORT datab (1313:1313:1313) (1280:1280:1280)) + (PORT datad (1287:1287:1287) (1255:1255:1255)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1235:1235:1235) (1166:1166:1166)) + (PORT datab (278:278:278) (304:304:304)) + (PORT datac (1178:1178:1178) (1083:1083:1083)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (1685:1685:1685) (1617:1617:1617)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (PORT ena (1106:1106:1106) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT asdata (2051:2051:2051) (1920:1920:1920)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (2053:2053:2053) (1939:1939:1939)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (852:852:852)) + (PORT datab (841:841:841) (817:817:817)) + (PORT datad (1261:1261:1261) (1212:1212:1212)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1991:1991:1991) (1909:1909:1909)) + (PORT datab (628:628:628) (636:636:636)) + (PORT datad (516:516:516) (536:536:536)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (1254:1254:1254) (1177:1177:1177)) + (PORT datac (1192:1192:1192) (1090:1090:1090)) + (PORT datad (1865:1865:1865) (1684:1684:1684)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~8) + (DELAY + (ABSOLUTE + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (487:487:487) (460:460:460)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (1738:1738:1738) (1676:1676:1676)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (PORT ena (1106:1106:1106) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (380:380:380) (473:473:473)) + (PORT datab (976:976:976) (960:960:960)) + (PORT datad (1553:1553:1553) (1445:1445:1445)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (1391:1391:1391) (1386:1386:1386)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (PORT ena (1106:1106:1106) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (794:794:794) (888:888:888)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1141:1141:1141) (1149:1149:1149)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (1260:1260:1260) (1227:1227:1227)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (487:487:487) (475:475:475)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datad (886:886:886) (882:882:882)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (909:909:909) (912:912:912)) + (PORT datab (360:360:360) (437:437:437)) + (PORT datad (1175:1175:1175) (1138:1138:1138)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (313:313:313)) + (PORT datab (277:277:277) (303:303:303)) + (PORT datad (870:870:870) (877:877:877)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT datab (1169:1169:1169) (1068:1068:1068)) + (PORT datac (779:779:779) (726:726:726)) + (PORT datad (1194:1194:1194) (1114:1114:1114)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1561:1561:1561) (1410:1410:1410)) + (PORT datab (1614:1614:1614) (1540:1540:1540)) + (PORT datac (798:798:798) (776:776:776)) + (PORT datad (1245:1245:1245) (1176:1176:1176)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT asdata (2446:2446:2446) (2316:2316:2316)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (2053:2053:2053) (1939:1939:1939)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6\~0) + (DELAY + (ABSOLUTE + (PORT datab (303:303:303) (344:344:344)) + (PORT datad (1309:1309:1309) (1266:1266:1266)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (1631:1631:1631) (1569:1569:1569)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (PORT ena (1106:1106:1106) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (369:369:369) (474:474:474)) + (PORT datab (577:577:577) (606:606:606)) + (PORT datac (321:321:321) (399:399:399)) + (PORT datad (545:545:545) (567:567:567)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (1327:1327:1327) (1265:1265:1265)) + (PORT datab (364:364:364) (463:463:463)) + (PORT datac (321:321:321) (399:399:399)) + (PORT datad (253:253:253) (277:277:277)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (340:340:340) (429:429:429)) + (PORT datad (1151:1151:1151) (1048:1048:1048)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (1991:1991:1991) (1909:1909:1909)) + (PORT datac (337:337:337) (426:426:426)) + (PORT datad (1150:1150:1150) (1047:1047:1047)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (571:571:571) (590:590:590)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT asdata (1625:1625:1625) (1569:1569:1569)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (1141:1141:1141) (1149:1149:1149)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (888:888:888) (884:884:884)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (515:515:515) (544:544:544)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp\|dffpipe13\|dffe14a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (958:958:958)) + (PORT datab (942:942:942) (934:934:934)) + (PORT datac (500:500:500) (484:484:484)) + (PORT datad (887:887:887) (876:876:876)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (1292:1292:1292) (1239:1239:1239)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (2053:2053:2053) (1939:1939:1939)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT asdata (1767:1767:1767) (1710:1710:1710)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (PORT ena (2053:2053:2053) (1939:1939:1939)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (1989:1989:1989) (1906:1906:1906)) + (PORT datab (590:590:590) (613:613:613)) + (PORT datac (338:338:338) (427:427:427)) + (PORT datad (1151:1151:1151) (1048:1048:1048)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datac (864:864:864) (867:867:867)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (417:417:417)) + (PORT datab (966:966:966) (938:938:938)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1589:1589:1589) (1501:1501:1501)) + (PORT datab (934:934:934) (920:920:920)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~6) + (DELAY + (ABSOLUTE + (PORT dataa (940:940:940) (925:925:925)) + (PORT datab (931:931:931) (932:932:932)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~8) + (DELAY + (ABSOLUTE + (PORT dataa (952:952:952) (921:921:921)) + (PORT datab (839:839:839) (807:807:807)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~10) + (DELAY + (ABSOLUTE + (PORT dataa (863:863:863) (860:860:860)) + (PORT datab (866:866:866) (829:829:829)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_dgwp_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datab (355:355:355) (441:441:441)) + (PORT datac (254:254:254) (294:294:294)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_bwp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1843:1843:1843) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (806:806:806) (785:785:785)) + (PORT datab (854:854:854) (821:821:821)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~14) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (574:574:574)) + (PORT datab (805:805:805) (783:783:783)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (314:314:314)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (238:238:238) (265:265:265)) + (PORT datad (240:240:240) (258:258:258)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (237:237:237) (256:256:256)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT dataa (1372:1372:1372) (1315:1315:1315)) + (PORT datab (982:982:982) (970:970:970)) + (PORT datac (260:260:260) (304:304:304)) + (PORT datad (920:920:920) (901:901:901)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9\~0) + (DELAY + (ABSOLUTE + (PORT datab (287:287:287) (316:316:316)) + (PORT datad (330:330:330) (407:407:407)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (1366:1366:1366) (1359:1359:1359)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (PORT ena (1106:1106:1106) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT datac (339:339:339) (430:430:430)) + (PORT datad (330:330:330) (426:426:426)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (479:479:479)) + (PORT datac (338:338:338) (428:428:428)) + (PORT datad (550:550:550) (572:572:572)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rs_brp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|op_1\~18) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (611:611:611)) + (PORT datad (793:793:793) (773:773:773)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_wr_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2267:2267:2267) (2132:2132:2132)) + (PORT datab (302:302:302) (326:326:326)) + (PORT datac (265:265:265) (290:290:290)) + (PORT datad (266:266:266) (283:283:283)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_wr_req) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (846:846:846) (840:840:840)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (PORT ena (1139:1139:1139) (1151:1151:1151)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (851:851:851) (845:845:845)) + (PORT datab (337:337:337) (384:384:384)) + (PORT datad (552:552:552) (579:579:579)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a1) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~11) + (DELAY + (ABSOLUTE + (PORT dataa (1730:1730:1730) (1656:1656:1656)) + (PORT datab (1737:1737:1737) (1662:1662:1662)) + (PORT datac (949:949:949) (928:928:928)) + (PORT datad (2095:2095:2095) (1988:1988:1988)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1708:1708:1708) (1615:1615:1615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (309:309:309) (358:358:358)) + (PORT datab (387:387:387) (473:473:473)) + (PORT datad (322:322:322) (393:393:393)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~10) + (DELAY + (ABSOLUTE + (PORT dataa (933:933:933) (916:916:916)) + (PORT datab (1720:1720:1720) (1630:1630:1630)) + (PORT datac (905:905:905) (880:880:880)) + (PORT datad (833:833:833) (827:827:827)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1708:1708:1708) (1615:1615:1615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (463:463:463)) + (PORT datab (320:320:320) (357:357:357)) + (PORT datac (337:337:337) (426:426:426)) + (PORT datad (338:338:338) (419:419:419)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8\~0) + (DELAY + (ABSOLUTE + (PORT datad (827:827:827) (766:766:766)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (807:807:807)) + (PORT datad (342:342:342) (427:427:427)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a9) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (806:806:806)) + (PORT datab (384:384:384) (471:471:471)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~9) + (DELAY + (ABSOLUTE + (PORT datab (378:378:378) (465:465:465)) + (PORT datac (331:331:331) (414:414:414)) + (PORT datad (331:331:331) (408:408:408)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1876:1876:1876)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1867:1867:1867)) + (PORT ena (1742:1742:1742) (1651:1651:1651)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (414:414:414)) + (PORT datac (295:295:295) (373:373:373)) + (PORT datad (1299:1299:1299) (1243:1243:1243)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|parity6) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1708:1708:1708) (1615:1615:1615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (373:373:373) (464:464:464)) + (PORT datab (343:343:343) (392:392:392)) + (PORT datac (800:800:800) (791:791:791)) + (PORT datad (544:544:544) (571:571:571)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (561:561:561) (607:607:607)) + (PORT datab (593:593:593) (620:620:620)) + (PORT datac (264:264:264) (309:309:309)) + (PORT datad (345:345:345) (429:429:429)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5\~0) + (DELAY + (ABSOLUTE + (PORT datab (278:278:278) (303:303:303)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a5) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (514:514:514) (501:501:501)) + (PORT datab (378:378:378) (462:462:462)) + (PORT datad (545:545:545) (574:574:574)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (918:918:918) (858:858:858)) + (PORT datab (925:925:925) (934:934:934)) + (PORT datad (340:340:340) (421:421:421)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a7) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (599:599:599) (630:630:630)) + (PORT datab (970:970:970) (978:978:978)) + (PORT datac (2000:2000:2000) (1888:1888:1888)) + (PORT datad (855:855:855) (827:827:827)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[0\]\~10) + (DELAY + (ABSOLUTE + (PORT datab (357:357:357) (447:447:447)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|rd_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (587:587:587) (645:645:645)) + (PORT datab (1212:1212:1212) (1182:1182:1182)) + (PORT datad (265:265:265) (297:297:297)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|rd_en) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT dataa (361:361:361) (453:453:453)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (465:465:465)) + (PORT datac (320:320:320) (414:414:414)) + (PORT datad (322:322:322) (405:405:405)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (376:376:376) (465:465:465)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[5\]\~20) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[6\]\~22) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[8\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (370:370:370) (450:450:450)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[9\]\~28) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (462:462:462)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT datac (903:903:903) (903:903:903)) + (PORT datad (956:956:956) (947:947:947)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~5) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (903:903:903)) + (PORT datab (1046:1046:1046) (1032:1032:1032)) + (PORT datac (858:858:858) (814:814:814)) + (PORT datad (895:895:895) (852:852:852)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datab (638:638:638) (651:651:651)) + (PORT datad (479:479:479) (462:462:462)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_CL) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1296:1296:1296) (1179:1179:1179)) + (PORT datab (370:370:370) (453:453:453)) + (PORT datad (478:478:478) (462:462:462)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_DATA) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (PORT datab (340:340:340) (423:423:423)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (301:301:301) (378:378:378)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|tread_end\~3) + (DELAY + (ABSOLUTE + (PORT dataa (938:938:938) (877:877:877)) + (PORT datab (957:957:957) (903:903:903)) + (PORT datac (349:349:349) (449:449:449)) + (PORT datad (870:870:870) (842:842:842)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_PRE) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT datab (519:519:519) (506:506:506)) + (PORT datad (539:539:539) (561:561:561)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_TRP) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|trp_end\~1) + (DELAY + (ABSOLUTE + (PORT datab (556:556:556) (521:521:521)) + (PORT datac (581:581:581) (597:597:597)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_END) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2564:2564:2564) (2442:2442:2442)) + (PORT datab (344:344:344) (427:427:427)) + (PORT datad (546:546:546) (593:593:593)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (2563:2563:2563) (2441:2441:2441)) + (PORT datab (345:345:345) (429:429:429)) + (PORT datad (305:305:305) (378:378:378)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_ACTIVE) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT datab (556:556:556) (593:593:593)) + (PORT datad (478:478:478) (462:462:462)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_TRCD) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|trcd_end\~1) + (DELAY + (ABSOLUTE + (PORT datab (628:628:628) (635:635:635)) + (PORT datad (494:494:494) (470:470:470)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_state\.RD_READ) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (586:586:586) (643:643:643)) + (PORT datab (360:360:360) (436:436:436)) + (PORT datad (302:302:302) (375:375:375)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|tread_end\~2) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (462:462:462)) + (PORT datab (374:374:374) (463:463:463)) + (PORT datac (315:315:315) (408:408:408)) + (PORT datad (317:317:317) (400:400:400)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|tread_end\~4) + (DELAY + (ABSOLUTE + (PORT dataa (508:508:508) (497:497:497)) + (PORT datab (307:307:307) (332:332:332)) + (PORT datac (327:327:327) (412:412:412)) + (PORT datad (328:328:328) (405:405:405)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (PORT datab (362:362:362) (439:439:439)) + (PORT datac (531:531:531) (553:553:553)) + (PORT datad (988:988:988) (986:986:986)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (939:939:939) (899:899:899)) + (PORT datab (908:908:908) (851:851:851)) + (PORT datac (450:450:450) (427:427:427)) + (PORT datad (897:897:897) (854:854:854)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector5\~3) + (DELAY + (ABSOLUTE + (PORT dataa (931:931:931) (943:943:943)) + (PORT datab (1220:1220:1220) (1113:1113:1113)) + (PORT datac (266:266:266) (293:293:293)) + (PORT datad (816:816:816) (753:753:753)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_ack\~1) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (464:464:464)) + (PORT datab (376:376:376) (466:466:466)) + (PORT datac (320:320:320) (414:414:414)) + (PORT datad (322:322:322) (405:405:405)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|valid_wrreq\~1) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (862:862:862) (806:806:806)) + (PORT datac (483:483:483) (460:460:460)) + (PORT datad (858:858:858) (814:814:814)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (335:335:335) (383:383:383)) + (PORT datab (396:396:396) (494:494:494)) + (PORT datad (951:951:951) (932:932:932)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a1) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (290:290:290) (330:330:330)) + (PORT datab (398:398:398) (497:497:497)) + (PORT datad (364:364:364) (449:449:449)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a2) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3\~0) + (DELAY + (ABSOLUTE + (PORT datab (405:405:405) (492:492:492)) + (PORT datad (256:256:256) (285:285:285)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a3) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (609:609:609) (645:645:645)) + (PORT datab (370:370:370) (454:454:454)) + (PORT datac (346:346:346) (444:444:444)) + (PORT datad (251:251:251) (279:279:279)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (598:598:598) (629:629:629)) + (PORT datab (970:970:970) (978:978:978)) + (PORT datac (813:813:813) (750:750:750)) + (PORT datad (854:854:854) (826:826:826)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (658:658:658) (678:678:678)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a10) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (657:657:657) (677:677:677)) + (PORT datad (248:248:248) (270:270:270)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a9) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~6) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (680:680:680)) + (PORT datac (331:331:331) (414:414:414)) + (PORT datad (537:537:537) (564:564:564)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (493:493:493)) + (PORT datab (405:405:405) (492:492:492)) + (PORT datac (363:363:363) (453:453:453)) + (PORT datad (356:356:356) (451:451:451)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|sub_parity10a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1135:1135:1135) (1146:1146:1146)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (413:413:413)) + (PORT datac (296:296:296) (374:374:374)) + (PORT datad (844:844:844) (839:839:839)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|parity9) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT datad (951:951:951) (932:932:932)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a0) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1135:1135:1135) (1146:1146:1146)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~1) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (379:379:379)) + (PORT datab (396:396:396) (494:494:494)) + (PORT datac (562:562:562) (591:591:591)) + (PORT datad (949:949:949) (929:929:929)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (389:389:389) (490:490:490)) + (PORT datab (297:297:297) (329:329:329)) + (PORT datad (571:571:571) (598:598:598)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a4) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (292:292:292) (332:332:332)) + (PORT datab (405:405:405) (493:493:493)) + (PORT datac (360:360:360) (451:451:451)) + (PORT datad (358:358:358) (453:453:453)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (390:390:390) (491:491:491)) + (PORT datab (369:369:369) (452:452:452)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a5) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (921:921:921) (861:861:861)) + (PORT datad (883:883:883) (890:890:890)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a6) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT asdata (1021:1021:1021) (1040:1040:1040)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (1352:1352:1352) (1327:1327:1327)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (2086:2086:2086) (1993:1993:1993)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT ena (1720:1720:1720) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1562:1562:1562) (1479:1479:1479)) + (PORT datab (368:368:368) (452:452:452)) + (PORT datad (319:319:319) (389:389:389)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT asdata (794:794:794) (869:869:869)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (1369:1369:1369) (1347:1347:1347)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8\~0) + (DELAY + (ABSOLUTE + (PORT datab (380:380:380) (463:463:463)) + (PORT datac (882:882:882) (879:879:879)) + (PORT datad (355:355:355) (429:429:429)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8\~1) + (DELAY + (ABSOLUTE + (PORT dataa (922:922:922) (863:863:863)) + (PORT datad (240:240:240) (258:258:258)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g1p\|counter8a8) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT asdata (1062:1062:1062) (1085:1085:1085)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (1336:1336:1336) (1314:1314:1314)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1412:1412:1412) (1348:1348:1348)) + (PORT datab (1382:1382:1382) (1317:1317:1317)) + (PORT datad (812:812:812) (777:777:777)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (311:311:311)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (930:930:930) (878:878:878)) + (PORT datad (237:237:237) (256:256:256)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1213:1213:1213) (1102:1102:1102)) + (PORT datab (341:341:341) (388:388:388)) + (PORT datac (338:338:338) (426:426:426)) + (PORT datad (805:805:805) (745:745:745)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_msb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (1441:1441:1441) (1405:1405:1405)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1293:1293:1293) (1224:1224:1224)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT asdata (2168:2168:2168) (2075:2075:2075)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (534:534:534) (557:557:557)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1293:1293:1293) (1224:1224:1224)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT asdata (1769:1769:1769) (1738:1738:1738)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1679:1679:1679) (1618:1618:1618)) + (PORT datab (854:854:854) (816:816:816)) + (PORT datad (1321:1321:1321) (1278:1278:1278)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (932:932:932) (937:937:937)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT asdata (1726:1726:1726) (1674:1674:1674)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT asdata (2464:2464:2464) (2342:2342:2342)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT asdata (1438:1438:1438) (1429:1429:1429)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1642:1642:1642) (1599:1599:1599)) + (PORT datab (1950:1950:1950) (1833:1833:1833)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (1713:1713:1713) (1587:1587:1587)) + (PORT datac (456:456:456) (430:430:430)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (2093:2093:2093) (1986:1986:1986)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1708:1708:1708) (1615:1615:1615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (567:567:567) (584:584:584)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1293:1293:1293) (1224:1224:1224)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT asdata (1746:1746:1746) (1717:1717:1717)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdempty_eq_comp_lsb\|data_wire\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT datac (1342:1342:1342) (1286:1286:1286)) + (PORT datad (837:837:837) (827:827:827)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (1401:1401:1401) (1374:1374:1374)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1293:1293:1293) (1224:1224:1224)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|delayed_wrptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT asdata (2161:2161:2161) (2076:2076:2076)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1352:1352:1352) (1302:1302:1302)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datad (1653:1653:1653) (1538:1538:1538)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (2154:2154:2154) (2068:2068:2068)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1708:1708:1708) (1615:1615:1615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (1322:1322:1322) (1305:1305:1305)) + (PORT datab (1713:1713:1713) (1656:1656:1656)) + (PORT datad (297:297:297) (367:367:367)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_mux\|result_node\[0\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (770:770:770)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (239:239:239) (265:265:265)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdemp_eq_comp_lsb_aeb) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_en_dly) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1868:1868:1868)) + (PORT asdata (788:788:788) (858:858:858)) + (PORT clrn (5995:5995:5995) (5789:5789:5789)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|valid_wreq) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (444:444:444)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (PORT datab (956:956:956) (934:934:934)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Add2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (433:433:433)) + (PORT datab (359:359:359) (450:450:450)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5949:5949:5949) (5747:5747:5747)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Add2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (430:430:430)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Add2\~6) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (426:426:426)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT datab (362:362:362) (454:454:454)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (258:258:258) (288:288:288)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5949:5949:5949) (5747:5747:5747)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (881:881:881) (855:855:855)) + (PORT datab (341:341:341) (422:422:422)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (352:352:352) (434:434:434)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (424:424:424)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (PORT datab (344:344:344) (426:426:426)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[3\]\~19) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (903:903:903)) + (PORT datab (638:638:638) (646:646:646)) + (PORT datac (545:545:545) (577:577:577)) + (PORT datad (894:894:894) (882:882:882)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (350:350:350) (438:438:438)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (509:509:509) (540:540:540)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal4\~3) + (DELAY + (ABSOLUTE + (PORT dataa (555:555:555) (515:515:515)) + (PORT datab (556:556:556) (523:523:523)) + (PORT datac (237:237:237) (263:263:263)) + (PORT datad (527:527:527) (559:559:559)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1858:1858:1858) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (6180:6180:6180) (6010:6010:6010)) + (PORT sclr (1121:1121:1121) (1138:1138:1138)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (908:908:908) (903:903:903)) + (PORT datab (638:638:638) (647:647:647)) + (PORT datac (546:546:546) (578:578:578)) + (PORT datad (895:895:895) (883:883:883)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|Equal5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (497:497:497) (490:490:490)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (507:507:507) (488:488:488)) + (PORT datad (526:526:526) (559:559:559)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5949:5949:5949) (5747:5747:5747)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|bit_cnt\~1) + (DELAY + (ABSOLUTE + (PORT datab (299:299:299) (331:331:331)) + (PORT datac (320:320:320) (416:416:416)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5949:5949:5949) (5747:5747:5747)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|always5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (345:345:345) (428:428:428)) + (PORT datac (300:300:300) (384:384:384)) + (PORT datad (304:304:304) (381:381:381)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|always5\~1) + (DELAY + (ABSOLUTE + (PORT datac (320:320:320) (416:416:416)) + (PORT datad (259:259:259) (289:289:289)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|rd_en) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5949:5949:5949) (5747:5747:5747)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty\~1) + (DELAY + (ABSOLUTE + (PORT dataa (913:913:913) (924:924:924)) + (PORT datab (982:982:982) (965:965:965)) + (PORT datac (948:948:948) (946:946:946)) + (PORT datad (918:918:918) (930:930:930)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty\~0) + (DELAY + (ABSOLUTE + (PORT dataa (356:356:356) (450:450:450)) + (PORT datac (526:526:526) (561:561:561)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty\~2) + (DELAY + (ABSOLUTE + (PORT dataa (904:904:904) (837:837:837)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_non_empty) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full\~4) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (738:738:738)) + (PORT datad (919:919:919) (929:929:929)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|b_full) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|_\~0) + (DELAY + (ABSOLUTE + (PORT dataa (566:566:566) (604:604:604)) + (PORT datab (577:577:577) (611:611:611)) + (PORT datac (309:309:309) (399:399:399)) + (PORT datad (919:919:919) (929:929:929)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|fifo_state\|count_usedw\|counter_reg_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1862:1862:1862) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (1606:1606:1606) (1509:1509:1509)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT asdata (790:790:790) (861:861:861)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT asdata (1021:1021:1021) (1029:1029:1029)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (PORT ena (1689:1689:1689) (1611:1611:1611)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (591:591:591) (628:628:628)) + (PORT datab (379:379:379) (462:462:462)) + (PORT datac (321:321:321) (399:399:399)) + (PORT datad (563:563:563) (582:582:582)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (948:948:948) (966:966:966)) + (PORT datab (1028:1028:1028) (1018:1018:1018)) + (PORT datac (967:967:967) (967:967:967)) + (PORT datad (909:909:909) (860:860:860)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor3) + (DELAY + (ABSOLUTE + (PORT datac (1300:1300:1300) (1278:1278:1278)) + (PORT datad (255:255:255) (281:281:281)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor2) + (DELAY + (ABSOLUTE + (PORT dataa (1329:1329:1329) (1294:1294:1294)) + (PORT datac (1301:1301:1301) (1278:1278:1278)) + (PORT datad (255:255:255) (281:281:281)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (1414:1414:1414) (1385:1385:1385)) + (PORT clrn (1895:1895:1895) (1865:1865:1865)) + (PORT ena (1708:1708:1708) (1615:1615:1615)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1285:1285:1285) (1241:1241:1241)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1270:1270:1270) (1242:1242:1242)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (1618:1618:1618) (1524:1524:1524)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (PORT ena (2086:2086:2086) (1974:1974:1974)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT asdata (795:795:795) (871:871:871)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (1818:1818:1818) (1758:1758:1758)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT ena (1720:1720:1720) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT asdata (1403:1403:1403) (1389:1389:1389)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT asdata (2057:2057:2057) (1942:1942:1942)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT ena (1720:1720:1720) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[10\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (899:899:899) (900:900:900)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (909:909:909) (896:896:896)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor7) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (580:580:580)) + (PORT datab (340:340:340) (422:422:422)) + (PORT datac (309:309:309) (399:399:399)) + (PORT datad (535:535:535) (558:558:558)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor4) + (DELAY + (ABSOLUTE + (PORT dataa (338:338:338) (421:421:421)) + (PORT datab (343:343:343) (425:425:425)) + (PORT datac (308:308:308) (395:395:395)) + (PORT datad (256:256:256) (281:281:281)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor1) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (437:437:437)) + (PORT datab (336:336:336) (412:412:412)) + (PORT datac (310:310:310) (398:398:398)) + (PORT datad (855:855:855) (809:809:809)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT asdata (1805:1805:1805) (1740:1740:1740)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor0) + (DELAY + (ABSOLUTE + (PORT datac (297:297:297) (375:375:375)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (882:882:882)) + (PORT datab (850:850:850) (822:822:822)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~4) + (DELAY + (ABSOLUTE + (PORT dataa (593:593:593) (605:605:605)) + (PORT datab (901:901:901) (887:887:887)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~6) + (DELAY + (ABSOLUTE + (PORT dataa (548:548:548) (572:572:572)) + (PORT datab (937:937:937) (917:917:917)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (286:286:286) (314:314:314)) + (PORT datac (245:245:245) (276:276:276)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor8) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (428:428:428)) + (PORT datac (312:312:312) (402:402:402)) + (PORT datad (539:539:539) (562:562:562)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor5) + (DELAY + (ABSOLUTE + (PORT datab (345:345:345) (428:428:428)) + (PORT datac (309:309:309) (397:397:397)) + (PORT datad (258:258:258) (283:283:283)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1862:1862:1862)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1853:1853:1853)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1263:1263:1263) (1217:1217:1217)) + (PORT datab (922:922:922) (918:918:918)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~10) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (903:903:903)) + (PORT datab (984:984:984) (957:957:957)) + (IOPATH dataa combout (461:461:461) (486:486:486)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (455:455:455) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1196:1196:1196) (1143:1143:1143)) + (PORT datab (929:929:929) (925:925:925)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (945:945:945) (949:949:949)) + (PORT datab (965:965:965) (942:942:942)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (473:473:473) (489:489:489)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (905:905:905) (858:858:858)) + (PORT datab (855:855:855) (804:804:804)) + (PORT datac (932:932:932) (877:877:877)) + (PORT datad (861:861:861) (804:804:804)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_en\~1) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (324:324:324)) + (PORT datab (1000:1000:1000) (985:985:985)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_en) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5995:5995:5995) (5789:5789:5789)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|valid_rdreq\~0) + (DELAY + (ABSOLUTE + (PORT datab (334:334:334) (410:410:410)) + (PORT datac (1312:1312:1312) (1277:1277:1277)) + (PORT datad (1296:1296:1296) (1256:1256:1256)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (374:374:374) (465:465:465)) + (PORT datab (341:341:341) (389:389:389)) + (PORT datac (803:803:803) (794:794:794)) + (PORT datad (548:548:548) (575:575:575)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (240:240:240) (258:258:258)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (356:356:356)) + (PORT datad (347:347:347) (430:430:430)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a3) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~5) + (DELAY + (ABSOLUTE + (PORT dataa (562:562:562) (609:609:609)) + (PORT datab (593:593:593) (620:620:620)) + (PORT datac (260:260:260) (304:304:304)) + (PORT datad (347:347:347) (430:430:430)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6\~0) + (DELAY + (ABSOLUTE + (PORT datab (320:320:320) (357:357:357)) + (PORT datad (545:545:545) (574:574:574)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a6) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (984:984:984) (964:964:964)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1872:1872:1872)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1863:1863:1863)) + (PORT ena (1720:1720:1720) (1638:1638:1638)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp\|dffpipe15\|dffe16a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT asdata (1406:1406:1406) (1385:1385:1385)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_dgrp_gray2bin\|xor6) + (DELAY + (ABSOLUTE + (PORT datac (314:314:314) (403:403:403)) + (PORT datad (254:254:254) (278:278:278)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_brp\|dffe12a\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1858:1858:1858)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (278:278:278) (304:304:304)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|wrptr_g_gray2bin\|xor9) + (DELAY + (ABSOLUTE + (PORT dataa (594:594:594) (631:631:631)) + (PORT datad (335:335:335) (416:416:416)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|ws_bwp\|dffe12a\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1891:1891:1891) (1862:1862:1862)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|op_2\~18) + (DELAY + (ABSOLUTE + (PORT dataa (949:949:949) (933:933:933)) + (PORT datad (889:889:889) (886:886:886)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (310:310:310)) + (PORT datab (1958:1958:1958) (1762:1762:1762)) + (PORT datac (1882:1882:1882) (1695:1695:1695)) + (PORT datad (267:267:267) (285:285:285)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1884:1884:1884) (1709:1709:1709)) + (PORT datab (303:303:303) (327:327:327)) + (PORT datac (265:265:265) (291:291:291)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|sdram_rd_req) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1864:1864:1864)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1855:1855:1855)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1643:1643:1643) (1583:1583:1583)) + (PORT datab (921:921:921) (928:928:928)) + (PORT datac (1168:1168:1168) (1141:1141:1141)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (583:583:583) (640:640:640)) + (PORT datad (331:331:331) (408:408:408)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT dataa (308:308:308) (349:349:349)) + (PORT datab (1213:1213:1213) (1184:1184:1184)) + (PORT datac (1552:1552:1552) (1461:1461:1461)) + (PORT datad (241:241:241) (260:260:260)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.READ) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~7) + (DELAY + (ABSOLUTE + (PORT datab (643:643:643) (658:658:658)) + (PORT datac (503:503:503) (515:515:515)) + (PORT datad (550:550:550) (579:579:579)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (557:557:557)) + (PORT datab (383:383:383) (471:471:471)) + (PORT datad (265:265:265) (282:282:282)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_DATA) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|twrite_end\~0) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (468:468:468)) + (PORT datab (363:363:363) (459:459:459)) + (PORT datac (321:321:321) (416:416:416)) + (PORT datad (324:324:324) (407:407:407)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|twrite_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (562:562:562)) + (PORT datab (330:330:330) (372:372:372)) + (PORT datac (369:369:369) (483:483:483)) + (PORT datad (806:806:806) (727:727:727)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_PRE) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (313:313:313) (350:350:350)) + (PORT datad (553:553:553) (578:578:578)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_TRP) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|trp_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (563:563:563)) + (PORT datab (351:351:351) (440:440:440)) + (PORT datac (289:289:289) (335:335:335)) + (PORT datad (500:500:500) (474:474:474)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_END) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1300:1300:1300) (1273:1273:1273)) + (PORT datab (1603:1603:1603) (1500:1500:1500)) + (PORT datad (264:264:264) (295:295:295)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.WRITE) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (645:645:645)) + (PORT datab (368:368:368) (447:447:447)) + (PORT datac (1253:1253:1253) (1222:1222:1222)) + (PORT datad (324:324:324) (395:395:395)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (793:793:793)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (237:237:237) (263:263:263)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.ARBIT) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT datab (1162:1162:1162) (1191:1191:1191)) + (PORT datac (331:331:331) (415:415:415)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1265:1265:1265) (1242:1242:1242)) + (PORT datab (378:378:378) (485:485:485)) + (PORT datad (585:585:585) (612:612:612)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\~4) + (DELAY + (ABSOLUTE + (PORT datad (580:580:580) (615:615:615)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\~2) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (674:674:674)) + (PORT datad (312:312:312) (393:393:393)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (PORT ena (1083:1083:1083) (1077:1077:1077)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\~15) + (DELAY + (ABSOLUTE + (PORT datac (302:302:302) (384:384:384)) + (PORT datad (309:309:309) (388:388:388)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (299:299:299) (342:342:342)) + (PORT datad (569:569:569) (588:588:588)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_TRP) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\~1) + (DELAY + (ABSOLUTE + (PORT datab (287:287:287) (318:318:318)) + (PORT datad (330:330:330) (423:423:423)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (463:463:463)) + (PORT datac (308:308:308) (395:395:395)) + (PORT datad (531:531:531) (572:572:572)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector4\~1) + (DELAY + (ABSOLUTE + (PORT dataa (648:648:648) (671:671:671)) + (PORT datab (341:341:341) (422:422:422)) + (PORT datac (254:254:254) (293:293:293)) + (PORT datad (321:321:321) (392:392:392)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (308:308:308) (357:357:357)) + (PORT datab (359:359:359) (448:448:448)) + (PORT datad (248:248:248) (270:270:270)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\~0) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (628:628:628)) + (PORT datab (283:283:283) (314:314:314)) + (PORT datad (329:329:329) (422:422:422)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (623:623:623)) + (PORT datab (369:369:369) (464:464:464)) + (PORT datac (310:310:310) (398:398:398)) + (PORT datad (320:320:320) (407:407:407)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector3\~1) + (DELAY + (ABSOLUTE + (PORT datab (279:279:279) (304:304:304)) + (PORT datac (329:329:329) (412:412:412)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_TRF) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\~2) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (356:356:356)) + (PORT datab (362:362:362) (451:451:451)) + (PORT datad (247:247:247) (269:269:269)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|trc_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (571:571:571) (621:621:621)) + (PORT datab (368:368:368) (464:464:464)) + (PORT datac (310:310:310) (398:398:398)) + (PORT datad (320:320:320) (407:407:407)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (339:339:339)) + (PORT datab (281:281:281) (307:307:307)) + (PORT datac (305:305:305) (389:389:389)) + (PORT datad (266:266:266) (306:306:306)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AUTO_REF) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\[1\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (649:649:649) (672:672:672)) + (PORT datac (331:331:331) (414:414:414)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref_aref\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (PORT ena (1083:1083:1083) (1077:1077:1077)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\~17) + (DELAY + (ABSOLUTE + (PORT dataa (308:308:308) (357:357:357)) + (PORT datab (356:356:356) (439:439:439)) + (PORT datac (304:304:304) (387:387:387)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_END) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|aref_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (1162:1162:1162) (1191:1191:1191)) + (PORT datac (330:330:330) (414:414:414)) + (PORT datad (582:582:582) (608:608:608)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|state\.AREF) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (PORT ena (1043:1043:1043) (1024:1024:1024)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\~3) + (DELAY + (ABSOLUTE + (PORT datad (254:254:254) (282:282:282)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\~2) + (DELAY + (ABSOLUTE + (PORT datab (406:406:406) (518:518:518)) + (PORT datad (258:258:258) (288:288:288)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector0\~1) + (DELAY + (ABSOLUTE + (PORT datab (377:377:377) (459:459:459)) + (PORT datac (360:360:360) (466:466:466)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1242:1242:1242) (1201:1201:1201)) + (PORT datab (403:403:403) (515:515:515)) + (PORT datad (256:256:256) (284:284:284)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_TRP) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (437:437:437)) + (PORT datab (403:403:403) (514:514:514)) + (PORT datac (303:303:303) (386:386:386)) + (PORT datad (254:254:254) (282:282:282)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (884:884:884) (886:886:886)) + (PORT datad (329:329:329) (403:403:403)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (905:905:905)) + (PORT datab (923:923:923) (892:892:892)) + (PORT datac (831:831:831) (810:810:810)) + (PORT datad (893:893:893) (884:884:884)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\~0) + (DELAY + (ABSOLUTE + (PORT dataa (862:862:862) (789:789:789)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (245:245:245) (271:271:271)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT datab (358:358:358) (434:434:434)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (435:435:435)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~20) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~22) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (433:433:433)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~24) + (DELAY + (ABSOLUTE + (PORT datab (343:343:343) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add0\~28) + (DELAY + (ABSOLUTE + (PORT datad (507:507:507) (538:538:538)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[14\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_200us\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1879:1879:1879)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1895:1895:1895) (1870:1870:1870)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (432:432:432)) + (PORT datab (544:544:544) (578:578:578)) + (PORT datac (301:301:301) (385:385:385)) + (PORT datad (301:301:301) (378:378:378)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (874:874:874) (862:862:862)) + (PORT datab (908:908:908) (890:890:890)) + (PORT datac (867:867:867) (838:838:838)) + (PORT datad (894:894:894) (857:857:857)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (853:853:853)) + (PORT datac (764:764:764) (706:706:706)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (903:903:903)) + (PORT datab (920:920:920) (889:889:889)) + (PORT datac (826:826:826) (806:806:806)) + (PORT datad (894:894:894) (885:885:885)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (890:890:890)) + (PORT datab (287:287:287) (316:316:316)) + (PORT datac (486:486:486) (463:463:463)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_IDLE\~0) + (DELAY + (ABSOLUTE + (PORT datad (246:246:246) (271:271:271)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector5\~2) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (311:311:311)) + (PORT datab (386:386:386) (464:464:464)) + (PORT datac (239:239:239) (266:266:266)) + (PORT datad (1280:1280:1280) (1223:1223:1223)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\~4) + (DELAY + (ABSOLUTE + (PORT dataa (579:579:579) (612:612:612)) + (PORT datab (295:295:295) (327:327:327)) + (PORT datad (339:339:339) (419:419:419)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT datab (403:403:403) (515:515:515)) + (PORT datad (335:335:335) (415:415:415)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_END\~0) + (DELAY + (ABSOLUTE + (PORT dataa (347:347:347) (437:437:437)) + (PORT datab (405:405:405) (510:510:510)) + (PORT datad (504:504:504) (485:485:485)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_END) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (451:451:451)) + (PORT datab (378:378:378) (485:485:485)) + (PORT datac (1219:1219:1219) (1192:1192:1192)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_state\.AREF_PCHA) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (628:628:628) (641:641:641)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (633:633:633) (644:644:644)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (576:576:576) (599:599:599)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (567:567:567) (587:587:587)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~4) + (DELAY + (ABSOLUTE + (PORT datac (492:492:492) (466:466:466)) + (PORT datad (311:311:311) (357:357:357)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[3\]\~1) + (DELAY + (ABSOLUTE + (PORT datac (1574:1574:1574) (1507:1507:1507)) + (PORT datad (318:318:318) (365:365:365)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT ena (1037:1037:1037) (1012:1012:1012)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT datab (369:369:369) (450:450:450)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[5\]\~10) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (562:562:562)) + (PORT datab (1360:1360:1360) (1352:1352:1352)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1861:1861:1861)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (370:370:370) (450:450:450)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[6\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (562:562:562)) + (PORT datab (1360:1360:1360) (1353:1353:1353)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1861:1861:1861)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (459:459:459)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[7\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (592:592:592) (567:567:567)) + (PORT datab (1358:1358:1358) (1349:1349:1349)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1861:1861:1861)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~0) + (DELAY + (ABSOLUTE + (PORT datac (494:494:494) (468:468:468)) + (PORT datad (315:315:315) (362:362:362)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT ena (1037:1037:1037) (1012:1012:1012)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~7) + (DELAY + (ABSOLUTE + (PORT datac (495:495:495) (469:469:469)) + (PORT datad (318:318:318) (365:365:365)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT ena (1037:1037:1037) (1012:1012:1012)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\~8) + (DELAY + (ABSOLUTE + (PORT datab (356:356:356) (403:403:403)) + (PORT datad (451:451:451) (429:429:429)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (PORT ena (1037:1037:1037) (1012:1012:1012)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (459:459:459)) + (PORT datab (368:368:368) (451:451:451)) + (PORT datac (318:318:318) (396:396:396)) + (PORT datad (321:321:321) (391:391:391)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|LessThan0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (460:460:460)) + (PORT datab (628:628:628) (638:638:638)) + (PORT datac (239:239:239) (265:265:265)) + (PORT datad (569:569:569) (582:582:582)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|LessThan0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (611:611:611)) + (PORT datab (367:367:367) (448:448:448)) + (PORT datac (579:579:579) (595:595:595)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (558:558:558) (589:589:589)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[8\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1618:1618:1618) (1555:1555:1555)) + (PORT datab (353:353:353) (400:400:400)) + (PORT datad (483:483:483) (451:451:451)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1860:1860:1860) (1871:1871:1871)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1862:1862:1862)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (332:332:332) (410:410:410)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[9\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (588:588:588) (562:562:562)) + (PORT datab (1361:1361:1361) (1353:1353:1353)) + (PORT datad (240:240:240) (259:259:259)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|cnt_aref\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1892:1892:1892) (1861:1861:1861)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (631:631:631) (641:641:641)) + (PORT datab (372:372:372) (453:453:453)) + (PORT datac (326:326:326) (411:411:411)) + (PORT datad (560:560:560) (584:584:584)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT datab (276:276:276) (301:301:301)) + (PORT datac (330:330:330) (416:416:416)) + (PORT datad (332:332:332) (410:410:410)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1177:1177:1177) (1090:1090:1090)) + (PORT datab (364:364:364) (441:441:441)) + (PORT datad (1115:1115:1115) (1021:1021:1021)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_req) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT datac (879:879:879) (890:890:890)) + (PORT datad (330:330:330) (404:404:404)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|wr_en\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1301:1301:1301) (1273:1273:1273)) + (PORT datab (1604:1604:1604) (1500:1500:1500)) + (PORT datad (264:264:264) (296:296:296)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|wr_en) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1297:1297:1297) (1269:1269:1269)) + (PORT datab (349:349:349) (433:433:433)) + (PORT datad (2523:2523:2523) (2391:2391:2391)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_IDLE) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector4\~1) + (DELAY + (ABSOLUTE + (PORT datab (636:636:636) (650:650:650)) + (PORT datac (907:907:907) (907:907:907)) + (PORT datad (530:530:530) (554:554:554)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (316:316:316) (354:354:354)) + (PORT datab (352:352:352) (441:441:441)) + (PORT datac (238:238:238) (264:264:264)) + (PORT datad (527:527:527) (548:548:548)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector4\~2) + (DELAY + (ABSOLUTE + (PORT dataa (980:980:980) (952:952:952)) + (PORT datab (507:507:507) (492:492:492)) + (PORT datac (236:236:236) (262:262:262)) + (PORT datad (435:435:435) (409:409:409)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[1\]\~12) + (DELAY + (ABSOLUTE + (PORT datab (356:356:356) (442:442:442)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[2\]\~14) + (DELAY + (ABSOLUTE + (PORT datab (356:356:356) (446:446:446)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[4\]\~18) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (422:422:422)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[7\]\~24) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[8\]\~26) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (438:438:438)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[9\]\~28) + (DELAY + (ABSOLUTE + (PORT datab (363:363:363) (440:440:440)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|cnt_clk\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1853:1853:1853) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (PORT sclr (903:903:903) (965:965:965)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Equal0\~5) + (DELAY + (ABSOLUTE + (PORT datab (641:641:641) (656:656:656)) + (PORT datad (548:548:548) (578:578:578)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (883:883:883)) + (PORT datad (831:831:831) (784:784:784)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_TRCD) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|trcd_end\~1) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (563:563:563)) + (PORT datab (331:331:331) (373:373:373)) + (PORT datac (560:560:560) (591:591:591)) + (PORT datad (500:500:500) (474:474:474)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_WRITE) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_ack\~2) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (465:465:465)) + (PORT datab (359:359:359) (455:455:455)) + (PORT datac (319:319:319) (413:413:413)) + (PORT datad (321:321:321) (404:404:404)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_ack\~3) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (563:563:563)) + (PORT datab (328:328:328) (369:369:369)) + (PORT datac (363:363:363) (475:475:475)) + (PORT datad (483:483:483) (451:451:451)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1356:1356:1356) (1312:1312:1312)) + (PORT datab (360:360:360) (437:437:437)) + (PORT datac (319:319:319) (397:397:397)) + (PORT datad (1274:1274:1274) (1238:1238:1238)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~4) + (DELAY + (ABSOLUTE + (PORT dataa (1276:1276:1276) (1244:1244:1244)) + (PORT datab (1567:1567:1567) (1494:1494:1494)) + (PORT datac (1139:1139:1139) (1039:1039:1039)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (408:408:408) (506:506:506)) + (PORT datab (290:290:290) (327:327:327)) + (PORT datad (1289:1289:1289) (1252:1252:1252)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a4) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~12) + (DELAY + (ABSOLUTE + (PORT dataa (1374:1374:1374) (1316:1316:1316)) + (PORT datab (982:982:982) (971:971:971)) + (PORT datac (1232:1232:1232) (1185:1185:1185)) + (PORT datad (921:921:921) (901:901:901)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (PORT ena (1757:1757:1757) (1679:1679:1679)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~11) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (948:948:948)) + (PORT datab (1259:1259:1259) (1212:1212:1212)) + (PORT datac (1271:1271:1271) (1218:1218:1218)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|sub_parity7a\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (PORT ena (1106:1106:1106) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~10) + (DELAY + (ABSOLUTE + (PORT dataa (341:341:341) (426:426:426)) + (PORT datac (295:295:295) (373:373:373)) + (PORT datad (903:903:903) (893:893:893)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|parity6) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (PORT ena (1757:1757:1757) (1679:1679:1679)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~2) + (DELAY + (ABSOLUTE + (PORT dataa (897:897:897) (901:901:901)) + (PORT datab (402:402:402) (486:486:486)) + (PORT datac (338:338:338) (428:428:428)) + (PORT datad (967:967:967) (924:924:924)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2\~0) + (DELAY + (ABSOLUTE + (PORT datad (238:238:238) (257:257:257)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a2) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~7) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (369:369:369) (449:449:449)) + (PORT datac (1193:1193:1193) (1150:1150:1150)) + (PORT datad (966:966:966) (923:923:923)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1375:1375:1375) (1318:1318:1318)) + (PORT datab (302:302:302) (342:342:342)) + (PORT datad (921:921:921) (901:901:901)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a7) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1378:1378:1378) (1322:1322:1322)) + (PORT datab (979:979:979) (967:967:967)) + (PORT datac (261:261:261) (305:305:305)) + (PORT datad (916:916:916) (896:896:896)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8\~0) + (DELAY + (ABSOLUTE + (PORT datad (237:237:237) (255:255:255)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a8) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10\~0) + (DELAY + (ABSOLUTE + (PORT datab (372:372:372) (453:453:453)) + (PORT datad (243:243:243) (268:268:268)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a10) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1857:1857:1857)) + (PORT asdata (1675:1675:1675) (1632:1632:1632)) + (PORT clrn (1877:1877:1877) (1848:1848:1848)) + (PORT ena (1106:1106:1106) (1090:1090:1090)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1003:1003:1003) (991:991:991)) + (PORT datab (913:913:913) (914:914:914)) + (PORT datad (548:548:548) (570:570:570)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (462:462:462)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1138:1138:1138) (1041:1041:1041)) + (PORT datab (337:337:337) (379:379:379)) + (PORT datac (324:324:324) (425:425:425)) + (PORT datad (832:832:832) (775:775:775)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux\|result_node\[0\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (311:311:311)) + (PORT datab (345:345:345) (389:389:389)) + (PORT datac (454:454:454) (431:431:431)) + (PORT datad (964:964:964) (952:952:952)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|wrfull_eq_comp_msb_mux_reg) + (DELAY + (ABSOLUTE + (PORT clk (1842:1842:1842) (1854:1854:1854)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1845:1845:1845)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|valid_wrreq\~0) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (417:417:417)) + (PORT datad (296:296:296) (366:366:366)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[1\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE rx\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (796:796:796) (842:842:842)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg1\~0) + (DELAY + (ABSOLUTE + (PORT datad (4105:4105:4105) (4296:4296:4296)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg1) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg2\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (296:296:296) (366:366:366)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg2) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_reg3\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_reg3) + (DELAY + (ABSOLUTE + (PORT clk (1850:1850:1850) (1860:1860:1860)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1882:1882:1882) (1851:1851:1851)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[7\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (906:906:906) (895:895:895)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|bit_cnt\~0) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (368:368:368) (467:467:467)) + (PORT datad (262:262:262) (297:297:297)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|bit_cnt\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1851:1851:1851) (1863:1863:1863)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1854:1854:1854)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|always8\~0) + (DELAY + (ABSOLUTE + (PORT datab (304:304:304) (342:342:342)) + (PORT datac (327:327:327) (428:428:428)) + (PORT datad (321:321:321) (409:409:409)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT asdata (770:770:770) (844:844:844)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (378:378:378)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (306:306:306) (380:380:380)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (376:376:376)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (308:308:308) (382:382:382)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (307:307:307) (381:381:381)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|rx_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (306:306:306) (380:380:380)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|rx_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2013:2013:2013) (1892:1892:1892)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[0\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (297:297:297) (367:367:367)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|ram_address_a\[9\]) + (DELAY + (ABSOLUTE + (PORT datad (330:330:330) (404:404:404)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (1285:1285:1285) (1253:1253:1253)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datab (1258:1258:1258) (1210:1210:1210)) + (PORT datac (897:897:897) (898:898:898)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[1\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (303:303:303) (377:377:377)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[2\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (305:305:305) (380:380:380)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[3\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (308:308:308) (383:383:383)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[4\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (306:306:306) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[5\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (304:304:304) (378:378:378)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_rx_inst\|po_data\[6\]\~feeder) + (DELAY + (ABSOLUTE + (PORT datad (306:306:306) (379:379:379)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_rx_inst\|po_data\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT asdata (770:770:770) (844:844:844)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (PORT ena (2016:2016:2016) (1942:1942:1942)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (972:972:972) (971:971:971)) + (PORT d[1] (1038:1038:1038) (1027:1027:1027)) + (PORT d[2] (985:985:985) (968:968:968)) + (PORT d[3] (970:970:970) (964:964:964)) + (PORT d[4] (997:997:997) (990:990:990)) + (PORT d[5] (1000:1000:1000) (994:994:994)) + (PORT d[6] (985:985:985) (968:968:968)) + (PORT d[7] (963:963:963) (964:964:964)) + (PORT d[8] (607:607:607) (590:590:590)) + (PORT clk (2261:2261:2261) (2289:2289:2289)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1350:1350:1350) (1313:1313:1313)) + (PORT d[1] (1573:1573:1573) (1549:1549:1549)) + (PORT d[2] (1399:1399:1399) (1369:1369:1369)) + (PORT d[3] (1767:1767:1767) (1706:1706:1706)) + (PORT d[4] (1342:1342:1342) (1310:1310:1310)) + (PORT d[5] (1406:1406:1406) (1368:1368:1368)) + (PORT d[6] (1726:1726:1726) (1667:1667:1667)) + (PORT d[7] (1330:1330:1330) (1286:1286:1286)) + (PORT d[8] (1374:1374:1374) (1352:1352:1352)) + (PORT d[9] (1214:1214:1214) (1122:1122:1122)) + (PORT clk (2257:2257:2257) (2284:2284:2284)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2463:2463:2463) (2259:2259:2259)) + (PORT clk (2257:2257:2257) (2284:2284:2284)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2261:2261:2261) (2289:2289:2289)) + (PORT d[0] (3170:3170:3170) (2973:2973:2973)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2262:2262:2262) (2290:2290:2290)) + (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2262:2262:2262) (2290:2290:2290)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2262:2262:2262) (2290:2290:2290)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2262:2262:2262) (2290:2290:2290)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1267:1267:1267) (1201:1201:1201)) + (PORT d[1] (1547:1547:1547) (1522:1522:1522)) + (PORT d[2] (1753:1753:1753) (1686:1686:1686)) + (PORT d[3] (1380:1380:1380) (1348:1348:1348)) + (PORT d[4] (1715:1715:1715) (1647:1647:1647)) + (PORT d[5] (1078:1078:1078) (1070:1070:1070)) + (PORT d[6] (1320:1320:1320) (1285:1285:1285)) + (PORT d[7] (1320:1320:1320) (1279:1279:1279)) + (PORT d[8] (1365:1365:1365) (1347:1347:1347)) + (PORT d[9] (1215:1215:1215) (1118:1118:1118)) + (PORT clk (2211:2211:2211) (2198:2198:2198)) + (PORT aclr (2253:2253:2253) (2246:2246:2246)) + (PORT stall (1610:1610:1610) (1736:1736:1736)) + (IOPATH (posedge aclr) q (396:396:396) (396:396:396)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + (HOLD stall (posedge clk) (254:254:254)) + (HOLD aclr (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (2211:2211:2211) (2198:2198:2198)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2212:2212:2212) (2199:2199:2199)) + (IOPATH (posedge clk) pulse (0:0:0) (3182:3182:3182)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2212:2212:2212) (2199:2199:2199)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2212:2212:2212) (2199:2199:2199)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (2203:2203:2203) (2194:2194:2194)) + (PORT ena (2164:2164:2164) (2043:2043:2043)) + (PORT aclr (2204:2204:2204) (2258:2258:2258)) + (IOPATH (posedge clk) q (392:392:392) (392:392:392)) + (IOPATH (posedge aclr) q (440:440:440) (440:440:440)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (64:64:64)) + (SETUP ena (posedge clk) (64:64:64)) + (SETUP aclr (posedge clk) (64:64:64)) + (HOLD d (posedge clk) (211:211:211)) + (HOLD ena (posedge clk) (211:211:211)) + (HOLD aclr (posedge clk) (211:211:211)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_ack) + (DELAY + (ABSOLUTE + (PORT datac (1140:1140:1140) (1040:1040:1040)) + (PORT datad (1527:1527:1527) (1450:1450:1450)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|wr_sdram_en) + (DELAY + (ABSOLUTE + (PORT clk (1841:1841:1841) (1853:1853:1853)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1874:1874:1874) (1844:1844:1844)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1129:1129:1129) (1098:1098:1098)) + (PORT d[1] (1129:1129:1129) (1098:1098:1098)) + (PORT d[2] (1129:1129:1129) (1098:1098:1098)) + (PORT d[3] (1129:1129:1129) (1098:1098:1098)) + (PORT d[4] (1114:1114:1114) (1082:1082:1082)) + (PORT d[5] (1114:1114:1114) (1082:1082:1082)) + (PORT d[6] (1114:1114:1114) (1082:1082:1082)) + (PORT clk (2255:2255:2255) (2284:2284:2284)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1902:1902:1902) (1840:1840:1840)) + (PORT d[1] (1020:1020:1020) (1022:1022:1022)) + (PORT d[2] (2363:2363:2363) (2282:2282:2282)) + (PORT d[3] (1372:1372:1372) (1343:1343:1343)) + (PORT d[4] (1012:1012:1012) (1017:1017:1017)) + (PORT d[5] (1163:1163:1163) (1110:1110:1110)) + (PORT d[6] (1709:1709:1709) (1649:1649:1649)) + (PORT d[7] (2052:2052:2052) (1907:1907:1907)) + (PORT d[8] (1724:1724:1724) (1675:1675:1675)) + (PORT d[9] (857:857:857) (781:781:781)) + (PORT clk (2251:2251:2251) (2279:2279:2279)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (2799:2799:2799) (2566:2566:2566)) + (PORT clk (2251:2251:2251) (2279:2279:2279)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2255:2255:2255) (2284:2284:2284)) + (PORT d[0] (3506:3506:3506) (3280:3280:3280)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2256:2256:2256) (2285:2285:2285)) + (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2256:2256:2256) (2285:2285:2285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2256:2256:2256) (2285:2285:2285)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2256:2256:2256) (2285:2285:2285)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (972:972:972) (925:925:925)) + (PORT d[1] (1550:1550:1550) (1515:1515:1515)) + (PORT d[2] (1747:1747:1747) (1679:1679:1679)) + (PORT d[3] (1090:1090:1090) (1090:1090:1090)) + (PORT d[4] (1003:1003:1003) (1011:1011:1011)) + (PORT d[5] (1020:1020:1020) (1014:1014:1014)) + (PORT d[6] (1007:1007:1007) (999:999:999)) + (PORT d[7] (1350:1350:1350) (1322:1322:1322)) + (PORT d[8] (1734:1734:1734) (1675:1675:1675)) + (PORT d[9] (1946:1946:1946) (1784:1784:1784)) + (PORT clk (2205:2205:2205) (2193:2193:2193)) + (PORT aclr (2247:2247:2247) (2241:2241:2241)) + (PORT stall (1917:1917:1917) (2070:2070:2070)) + (IOPATH (posedge aclr) q (396:396:396) (396:396:396)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + (HOLD stall (posedge clk) (254:254:254)) + (HOLD aclr (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (2205:2205:2205) (2193:2193:2193)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2206:2206:2206) (2194:2194:2194)) + (IOPATH (posedge clk) pulse (0:0:0) (3182:3182:3182)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2206:2206:2206) (2194:2194:2194)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2206:2206:2206) (2194:2194:2194)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|wr_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a9.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (2197:2197:2197) (2189:2189:2189)) + (PORT ena (2131:2131:2131) (2004:2004:2004)) + (PORT aclr (2198:2198:2198) (2253:2253:2253)) + (IOPATH (posedge clk) q (392:392:392) (392:392:392)) + (IOPATH (posedge aclr) q (440:440:440) (440:440:440)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (64:64:64)) + (SETUP ena (posedge clk) (64:64:64)) + (SETUP aclr (posedge clk) (64:64:64)) + (HOLD d (posedge clk) (211:211:211)) + (HOLD ena (posedge clk) (211:211:211)) + (HOLD aclr (posedge clk) (211:211:211)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE sys_clk\~inputclkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (200:200:200) (189:189:189)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]\~13) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (894:894:894)) + (PORT datab (341:341:341) (422:422:422)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]\~35) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[11\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (344:344:344) (434:434:434)) + (PORT datab (342:342:342) (424:424:424)) + (PORT datac (300:300:300) (383:383:383)) + (PORT datad (303:303:303) (380:380:380)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]\~31) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (959:959:959) (947:947:947)) + (PORT datab (960:960:960) (941:941:941)) + (PORT datac (826:826:826) (767:767:767)) + (PORT datad (953:953:953) (936:936:936)) + (IOPATH dataa combout (438:438:438) (448:448:448)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]\~15) + (DELAY + (ABSOLUTE + (PORT dataa (352:352:352) (441:441:441)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (354:354:354) (450:450:450)) + (PORT datab (350:350:350) (439:439:439)) + (PORT datac (311:311:311) (400:400:400)) + (PORT datad (313:313:313) (393:393:393)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|tx_flag) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1870:1870:1870)) + (PORT asdata (1030:1030:1030) (1048:1048:1048)) + (PORT clrn (5949:5949:5949) (5747:5747:5747)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always3\~0) + (DELAY + (ABSOLUTE + (PORT dataa (932:932:932) (942:942:942)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datac combout (462:462:462) (482:482:482)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (399:399:399) (527:527:527)) + (PORT datab (293:293:293) (331:331:331)) + (PORT datad (292:292:292) (322:322:322)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5192:5192:5192) (4949:4949:4949)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (774:774:774) (707:707:707)) + (PORT datab (295:295:295) (333:333:333)) + (PORT datad (288:288:288) (318:318:318)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5192:5192:5192) (4949:4949:4949)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (393:393:393) (520:520:520)) + (PORT datab (412:412:412) (513:513:513)) + (PORT datac (321:321:321) (422:422:422)) + (PORT datad (248:248:248) (275:275:275)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|work_en\~0) + (DELAY + (ABSOLUTE + (PORT datab (1371:1371:1371) (1321:1321:1321)) + (PORT datad (1269:1269:1269) (1180:1180:1180)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|work_en) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1881:1881:1881)) + (PORT asdata (5350:5350:5350) (4891:4891:4891)) + (PORT clrn (5192:5192:5192) (4949:4949:4949)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (280:280:280) (312:312:312)) + (PORT datab (303:303:303) (327:327:327)) + (PORT datac (1403:1403:1403) (1288:1288:1288)) + (PORT datad (1160:1160:1160) (1121:1121:1121)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]\~17) + (DELAY + (ABSOLUTE + (PORT datab (350:350:350) (435:435:435)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]\~23) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (425:425:425)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]\~25) + (DELAY + (ABSOLUTE + (PORT datab (350:350:350) (440:440:440)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]\~27) + (DELAY + (ABSOLUTE + (PORT datab (342:342:342) (422:422:422)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]\~29) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]\~33) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]\~37) + (DELAY + (ABSOLUTE + (PORT datad (321:321:321) (391:391:391)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|baud_cnt\[12\]) + (DELAY + (ABSOLUTE + (PORT clk (1871:1871:1871) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5187:5187:5187) (4944:4944:4944)) + (PORT sclr (1487:1487:1487) (1466:1466:1466)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD sclr (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (353:353:353) (448:448:448)) + (PORT datab (351:351:351) (440:440:440)) + (PORT datac (308:308:308) (397:397:397)) + (PORT datad (310:310:310) (389:389:389)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|Equal2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (575:575:575) (540:540:540)) + (PORT datab (936:936:936) (944:944:944)) + (PORT datac (794:794:794) (741:741:741)) + (PORT datad (962:962:962) (949:949:949)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|bit_flag) + (DELAY + (ABSOLUTE + (PORT clk (1874:1874:1874) (1885:1885:1885)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5141:5141:5141) (4901:4901:4901)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|always0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (430:430:430)) + (PORT datac (886:886:886) (891:891:891)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|valid_rreq) + (DELAY + (ABSOLUTE + (PORT dataa (365:365:365) (449:449:449)) + (PORT datad (915:915:915) (927:927:927)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[0\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (774:774:774) (821:821:821)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4629:4629:4629) (4901:4901:4901)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_ack\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1001:1001:1001) (997:997:997)) + (PORT datab (897:897:897) (855:855:855)) + (PORT datac (824:824:824) (772:772:772)) + (PORT datad (265:265:265) (282:282:282)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[0\]\~5) + (DELAY + (ABSOLUTE + (PORT datad (882:882:882) (824:824:824)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|counter5a0\~_wirecell) + (DELAY + (ABSOLUTE + (PORT datad (2096:2096:2096) (1989:1989:1989)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|rdptr_g1p\|_\~0) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (447:447:447)) + (PORT datac (326:326:326) (409:409:409)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[1\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (774:774:774) (821:821:821)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4552:4552:4552) (4818:4818:4818)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[1\]\~6) + (DELAY + (ABSOLUTE + (PORT datad (878:878:878) (820:820:820)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[2\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (734:734:734) (781:781:781)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4558:4558:4558) (4795:4795:4795)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[2\]\~4) + (DELAY + (ABSOLUTE + (PORT datad (877:877:877) (819:819:819)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[3\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (764:764:764) (811:811:811)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4349:4349:4349) (4485:4485:4485)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[3\]\~2) + (DELAY + (ABSOLUTE + (PORT datad (883:883:883) (826:826:826)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[4\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (774:774:774) (821:821:821)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4391:4391:4391) (4517:4517:4517)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[4\]\~1) + (DELAY + (ABSOLUTE + (PORT datad (876:876:876) (818:818:818)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[5\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (754:754:754) (801:801:801)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4641:4641:4641) (4868:4868:4868)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[5\]\~0) + (DELAY + (ABSOLUTE + (PORT datad (879:879:879) (822:822:822)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[6\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (784:784:784) (831:831:831)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4805:4805:4805) (4978:4978:4978)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[6\]\~3) + (DELAY + (ABSOLUTE + (PORT datad (883:883:883) (826:826:826)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sdram_dq\[7\]\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (774:774:774) (821:821:821)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_data_reg\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1863:1863:1863) (1874:1874:1874)) + (PORT asdata (4521:4521:4521) (4777:4777:4777)) + (PORT clrn (1895:1895:1895) (1866:1866:1866)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|rd_sdram_data\[7\]\~7) + (DELAY + (ABSOLUTE + (PORT datad (877:877:877) (820:820:820)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.datain_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (956:956:956) (879:879:879)) + (PORT d[1] (882:882:882) (817:817:817)) + (PORT d[2] (880:880:880) (816:816:816)) + (PORT d[3] (953:953:953) (875:875:875)) + (PORT d[4] (888:888:888) (833:833:833)) + (PORT d[5] (881:881:881) (816:816:816)) + (PORT d[6] (901:901:901) (830:830:830)) + (PORT d[7] (919:919:919) (853:853:853)) + (PORT clk (2277:2277:2277) (2305:2305:2305)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1036:1036:1036) (999:999:999)) + (PORT d[1] (984:984:984) (978:978:978)) + (PORT d[2] (955:955:955) (950:950:950)) + (PORT d[3] (1769:1769:1769) (1707:1707:1707)) + (PORT d[4] (944:944:944) (948:948:948)) + (PORT d[5] (1792:1792:1792) (1709:1709:1709)) + (PORT d[6] (1702:1702:1702) (1604:1604:1604)) + (PORT d[7] (999:999:999) (996:996:996)) + (PORT d[8] (1048:1048:1048) (1035:1035:1035)) + (PORT d[9] (921:921:921) (865:865:865)) + (PORT clk (2273:2273:2273) (2300:2300:2300)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.we_a_register) + (DELAY + (ABSOLUTE + (PORT d[0] (1312:1312:1312) (1167:1167:1167)) + (PORT clk (2273:2273:2273) (2300:2300:2300)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_a) + (DELAY + (ABSOLUTE + (PORT clk (2277:2277:2277) (2305:2305:2305)) + (PORT d[0] (2019:2019:2019) (1881:1881:1881)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.wpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2306:2306:2306)) + (IOPATH (posedge clk) pulse (0:0:0) (2750:2750:2750)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2306:2306:2306)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2306:2306:2306)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_a) + (DELAY + (ABSOLUTE + (PORT clk (2278:2278:2278) (2306:2306:2306)) + (IOPATH (posedge clk) pulse (0:0:0) (3428:3428:3428)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.addr_b_register) + (DELAY + (ABSOLUTE + (PORT d[0] (530:530:530) (500:500:500)) + (PORT d[1] (973:973:973) (958:958:958)) + (PORT d[2] (1808:1808:1808) (1728:1728:1728)) + (PORT d[3] (2013:2013:2013) (1906:1906:1906)) + (PORT d[4] (1980:1980:1980) (1869:1869:1869)) + (PORT d[5] (2026:2026:2026) (1902:1902:1902)) + (PORT d[6] (1028:1028:1028) (1005:1005:1005)) + (PORT d[7] (1068:1068:1068) (1048:1048:1048)) + (PORT d[8] (1714:1714:1714) (1625:1625:1625)) + (PORT d[9] (922:922:922) (860:860:860)) + (PORT clk (2227:2227:2227) (2214:2214:2214)) + (PORT aclr (2269:2269:2269) (2262:2262:2262)) + (PORT stall (1288:1288:1288) (1407:1407:1407)) + (IOPATH (posedge aclr) q (396:396:396) (396:396:396)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (254:254:254)) + (HOLD stall (posedge clk) (254:254:254)) + (HOLD aclr (posedge clk) (254:254:254)) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.active_core_port_b) + (DELAY + (ABSOLUTE + (PORT clk (2227:2227:2227) (2214:2214:2214)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2228:2228:2228) (2215:2215:2215)) + (IOPATH (posedge clk) pulse (0:0:0) (3182:3182:3182)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.ftpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2228:2228:2228) (2215:2215:2215)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_pulse_generator") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.rwpgen_b) + (DELAY + (ABSOLUTE + (PORT clk (2228:2228:2228) (2215:2215:2215)) + (IOPATH (posedge clk) pulse (0:0:0) (3469:3469:3469)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_ram_register") + (INSTANCE sdram_top_inst\|fifo_ctrl_inst\|rd_fifo_data\|dcfifo_component\|auto_generated\|fifo_ram\|ram_block11a0.dataout_b_register) + (DELAY + (ABSOLUTE + (PORT clk (2219:2219:2219) (2210:2210:2210)) + (PORT ena (1830:1830:1830) (1713:1713:1713)) + (PORT aclr (2220:2220:2220) (2274:2274:2274)) + (IOPATH (posedge clk) q (392:392:392) (392:392:392)) + (IOPATH (posedge aclr) q (440:440:440) (440:440:440)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (64:64:64)) + (SETUP ena (posedge clk) (64:64:64)) + (SETUP aclr (posedge clk) (64:64:64)) + (HOLD d (posedge clk) (211:211:211)) + (HOLD ena (posedge clk) (211:211:211)) + (HOLD aclr (posedge clk) (211:211:211)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita1) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (436:436:436)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita2) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita3) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita4) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita5) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita6) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita7) + (DELAY + (ABSOLUTE + (PORT datab (361:361:361) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita8) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_comb_bita9) + (DELAY + (ABSOLUTE + (PORT datab (362:362:362) (439:439:439)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|wr_ptr\|counter_reg_bit\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1857:1857:1857) (1867:1867:1867)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2742:2742:2742) (2554:2554:2554)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita0) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita1) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita2) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita3) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita4) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita5) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita6) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (447:447:447)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita7) + (DELAY + (ABSOLUTE + (PORT datab (360:360:360) (437:437:437)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita8) + (DELAY + (ABSOLUTE + (PORT dataa (363:363:363) (446:446:446)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_comb_bita9) + (DELAY + (ABSOLUTE + (PORT datad (507:507:507) (538:538:538)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE fifo_read_inst\|read_fifo_inst\|scfifo_component\|auto_generated\|dpfifo\|rd_ptr_count\|counter_reg_bit\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1859:1859:1859) (1869:1869:1869)) + (PORT d (99:99:99) (115:115:115)) + (PORT ena (2307:2307:2307) (2153:2153:2153)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~4) + (DELAY + (ABSOLUTE + (PORT dataa (396:396:396) (523:523:523)) + (PORT datab (367:367:367) (467:467:467)) + (PORT datac (740:740:740) (662:662:662)) + (PORT datad (370:370:370) (470:470:470)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~3) + (DELAY + (ABSOLUTE + (PORT dataa (934:934:934) (943:943:943)) + (PORT datad (321:321:321) (391:391:391)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE uart_tx_inst\|tx\~5) + (DELAY + (ABSOLUTE + (PORT dataa (811:811:811) (734:734:734)) + (PORT datab (291:291:291) (320:320:320)) + (PORT datac (1119:1119:1119) (1006:1006:1006)) + (PORT datad (441:441:441) (420:420:420)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE uart_tx_inst\|tx) + (DELAY + (ABSOLUTE + (PORT clk (1870:1870:1870) (1881:1881:1881)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (5192:5192:5192) (4949:4949:4949)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[2\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT asdata (1416:1416:1416) (1405:1405:1405)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT asdata (1329:1329:1329) (1301:1301:1301)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT datab (373:373:373) (479:479:479)) + (PORT datac (1230:1230:1230) (1271:1271:1271)) + (PORT datad (1186:1186:1186) (1214:1214:1214)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT asdata (2130:2130:2130) (2054:2054:2054)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector2\~0) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (476:476:476)) + (PORT datab (406:406:406) (510:510:510)) + (PORT datad (506:506:506) (487:487:487)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_TRF) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1236:1236:1236) (1124:1124:1124)) + (PORT datab (304:304:304) (328:328:328)) + (PORT datac (361:361:361) (467:467:467)) + (PORT datad (314:314:314) (394:394:394)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|Selector0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (298:298:298) (336:336:336)) + (PORT datab (405:405:405) (516:516:516)) + (PORT datac (304:304:304) (388:388:388)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_AR) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1735:1735:1735) (1631:1631:1631)) + (PORT datad (1315:1315:1315) (1286:1286:1286)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (1178:1178:1178) (1088:1088:1088)) + (PORT datab (1181:1181:1181) (1095:1095:1095)) + (PORT datad (294:294:294) (363:363:363)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~3) + (DELAY + (ABSOLUTE + (PORT dataa (1179:1179:1179) (1090:1090:1090)) + (PORT datab (331:331:331) (406:406:406)) + (PORT datad (237:237:237) (255:255:255)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~4) + (DELAY + (ABSOLUTE + (PORT datac (941:941:941) (948:948:948)) + (PORT datad (236:236:236) (254:254:254)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1706:1706:1706) (1642:1642:1642)) + (PORT datac (1220:1220:1220) (1172:1172:1172)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_a_ref_inst\|aref_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\~17) + (DELAY + (ABSOLUTE + (PORT datab (286:286:286) (314:314:314)) + (PORT datad (592:592:592) (621:621:621)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_PRE) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|WideOr5) + (DELAY + (ABSOLUTE + (PORT dataa (1731:1731:1731) (1627:1627:1627)) + (PORT datab (1355:1355:1355) (1330:1330:1330)) + (PORT datad (1628:1628:1628) (1549:1549:1549)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\~0) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (882:882:882)) + (PORT datad (1254:1254:1254) (1195:1195:1195)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1175:1175:1175) (1085:1085:1085)) + (PORT datab (332:332:332) (408:408:408)) + (PORT datac (1140:1140:1140) (1060:1060:1060)) + (PORT datad (293:293:293) (363:363:363)) + (IOPATH dataa combout (453:453:453) (472:472:472)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector5\~1) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (573:573:573)) + (PORT datab (333:333:333) (409:409:409)) + (PORT datac (1138:1138:1138) (1057:1057:1057)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector5\~2) + (DELAY + (ABSOLUTE + (PORT datac (941:941:941) (948:948:948)) + (PORT datad (236:236:236) (253:253:253)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector5\~0) + (DELAY + (ABSOLUTE + (PORT dataa (520:520:520) (497:497:497)) + (PORT datab (383:383:383) (472:472:472)) + (PORT datac (366:366:366) (479:479:479)) + (PORT datad (559:559:559) (584:584:584)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT datac (1223:1223:1223) (1263:1263:1263)) + (PORT datad (1193:1193:1193) (1222:1222:1222)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector6\~1) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (328:328:328)) + (PORT datac (330:330:330) (414:414:414)) + (PORT datad (563:563:563) (588:588:588)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_cmd\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector7\~1) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (310:310:310)) + (PORT datab (537:537:537) (566:566:566)) + (PORT datac (1112:1112:1112) (1034:1034:1034)) + (PORT datad (493:493:493) (514:514:514)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (440:440:440) (462:462:462)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector7\~2) + (DELAY + (ABSOLUTE + (PORT dataa (278:278:278) (309:309:309)) + (PORT datac (941:941:941) (948:948:948)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Equal0\~6) + (DELAY + (ABSOLUTE + (PORT dataa (941:941:941) (900:900:900)) + (PORT datab (908:908:908) (851:851:851)) + (PORT datac (969:969:969) (962:962:962)) + (PORT datad (936:936:936) (935:935:935)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector21\~1) + (DELAY + (ABSOLUTE + (PORT dataa (282:282:282) (314:314:314)) + (PORT datab (1047:1047:1047) (1032:1032:1032)) + (PORT datac (245:245:245) (276:276:276)) + (PORT datad (561:561:561) (587:587:587)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_addr\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~6) + (DELAY + (ABSOLUTE + (PORT datad (597:597:597) (626:626:626)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[3\]\~3) + (DELAY + (ABSOLUTE + (PORT datac (1238:1238:1238) (1166:1166:1166)) + (PORT datad (593:593:593) (622:622:622)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1859:1859:1859)) + (PORT ena (1080:1080:1080) (1064:1064:1064)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~5) + (DELAY + (ABSOLUTE + (PORT datab (379:379:379) (469:469:469)) + (PORT datad (596:596:596) (624:624:624)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1859:1859:1859)) + (PORT ena (1080:1080:1080) (1064:1064:1064)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\~4) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (610:610:610)) + (PORT datab (355:355:355) (442:442:442)) + (PORT datad (591:591:591) (619:619:619)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (432:432:432) (433:433:433)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|cnt_init_aref\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1852:1852:1852) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1884:1884:1884) (1859:1859:1859)) + (PORT ena (1080:1080:1080) (1064:1064:1064)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + (HOLD ena (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\~15) + (DELAY + (ABSOLUTE + (PORT dataa (346:346:346) (436:436:436)) + (PORT datab (378:378:378) (468:468:468)) + (PORT datac (310:310:310) (400:400:400)) + (PORT datad (301:301:301) (374:374:374)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (538:538:538)) + (PORT datab (353:353:353) (436:436:436)) + (PORT datac (363:363:363) (470:470:470)) + (PORT datad (1169:1169:1169) (1069:1069:1069)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_state\.INIT_MRS) + (DELAY + (ABSOLUTE + (PORT clk (1849:1849:1849) (1861:1861:1861)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1881:1881:1881) (1852:1852:1852)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_init_inst\|init_ba\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT asdata (1691:1691:1691) (1629:1629:1629)) + (PORT clrn (1886:1886:1886) (1857:1857:1857)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD asdata (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector9\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1226:1226:1226) (1171:1171:1171)) + (PORT datab (373:373:373) (479:479:479)) + (PORT datad (1186:1186:1186) (1214:1214:1214)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector9\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1291:1291:1291) (1315:1315:1315)) + (PORT datab (1336:1336:1336) (1298:1298:1298)) + (PORT datac (1117:1117:1117) (1149:1149:1149)) + (PORT datad (481:481:481) (471:471:471)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (552:552:552)) + (PORT datab (412:412:412) (520:520:520)) + (PORT datac (503:503:503) (514:514:514)) + (PORT datad (478:478:478) (443:443:443)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector6\~2) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (351:351:351) (441:441:441)) + (PORT datac (559:559:559) (589:589:589)) + (PORT datad (265:265:265) (282:282:282)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_ba\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector22\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1287:1287:1287) (1310:1310:1310)) + (PORT datab (1337:1337:1337) (1299:1299:1299)) + (PORT datac (1130:1130:1130) (1085:1085:1085)) + (PORT datad (1193:1193:1193) (1221:1221:1221)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|WideOr7\~0) + (DELAY + (ABSOLUTE + (PORT dataa (392:392:392) (495:495:495)) + (PORT datab (638:638:638) (652:652:652)) + (PORT datac (508:508:508) (548:548:548)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|Selector11\~0) + (DELAY + (ABSOLUTE + (PORT dataa (291:291:291) (330:330:330)) + (PORT datab (290:290:290) (322:322:322)) + (PORT datad (561:561:561) (586:586:586)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_read_inst\|read_addr\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\~16) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (452:452:452)) + (PORT datab (344:344:344) (427:427:427)) + (PORT datad (2522:2522:2522) (2390:2390:2390)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_state\.WR_ACTIVE) + (DELAY + (ABSOLUTE + (PORT clk (1856:1856:1856) (1868:1868:1868)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1888:1888:1888) (1859:1859:1859)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector10\~0) + (DELAY + (ABSOLUTE + (PORT dataa (871:871:871) (856:856:856)) + (PORT datab (1264:1264:1264) (1204:1204:1204)) + (PORT datac (366:366:366) (479:479:479)) + (PORT datad (340:340:340) (426:426:426)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|Selector10\~1) + (DELAY + (ABSOLUTE + (PORT dataa (578:578:578) (552:552:552)) + (PORT datab (511:511:511) (489:489:489)) + (PORT datac (370:370:370) (484:484:484)) + (PORT datad (239:239:239) (258:258:258)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_write_inst\|write_addr\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1854:1854:1854) (1865:1865:1865)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1886:1886:1886) (1856:1856:1856)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector12\~0) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (416:416:416)) + (PORT datab (373:373:373) (480:480:480)) + (PORT datac (830:830:830) (817:817:817)) + (PORT datad (1188:1188:1188) (1216:1216:1216)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE sdram_top_inst\|sdram_ctrl_inst\|sdram_arbit_inst\|Selector12\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1289:1289:1289) (1312:1312:1312)) + (PORT datab (1157:1157:1157) (1184:1184:1184)) + (PORT datac (790:790:790) (769:769:769)) + (PORT datad (238:238:238) (256:256:256)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) +) diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/uart_sdram.qpf b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/uart_sdram.qpf new file mode 100644 index 0000000..7b4a7ed --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/uart_sdram.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.0 Build 156 04/24/2013 SJ Full Version +# Date created = 17:31:57 April 12, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "17:31:57 April 12, 2019" + +# Revisions + +PROJECT_REVISION = "uart_sdram" diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/uart_sdram.qsf b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/uart_sdram.qsf new file mode 100644 index 0000000..904d70f --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/uart_sdram.qsf @@ -0,0 +1,175 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.0 Build 156 04/24/2013 SJ Full Version +# Date created = 17:31:58 April 12, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# uart_sdram_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE15F23C8 +set_global_assignment -name TOP_LEVEL_ENTITY uart_sdram +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:31:57 APRIL 12, 2019" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" + +set_location_assignment PIN_T22 -to sys_clk +set_location_assignment PIN_U20 -to sys_rst_n +set_location_assignment PIN_U1 -to tx +set_location_assignment PIN_V1 -to rx + +set_location_assignment PIN_E5 -to sdram_clk +set_location_assignment PIN_M1 -to sdram_cke +set_location_assignment PIN_A4 -to sdram_cs_n +set_location_assignment PIN_D6 -to sdram_ras_n +set_location_assignment PIN_B5 -to sdram_cas_n +set_location_assignment PIN_A5 -to sdram_we_n +set_location_assignment PIN_B4 -to sdram_ba[0] +set_location_assignment PIN_C4 -to sdram_ba[1] +set_location_assignment PIN_M2 -to sdram_addr[12] +set_location_assignment PIN_N1 -to sdram_addr[11] +set_location_assignment PIN_A3 -to sdram_addr[10] +set_location_assignment PIN_N2 -to sdram_addr[9] +set_location_assignment PIN_H1 -to sdram_addr[8] +set_location_assignment PIN_F2 -to sdram_addr[7] +set_location_assignment PIN_F1 -to sdram_addr[6] +set_location_assignment PIN_E1 -to sdram_addr[5] +set_location_assignment PIN_C2 -to sdram_addr[4] +set_location_assignment PIN_C1 -to sdram_addr[3] +set_location_assignment PIN_B2 -to sdram_addr[2] +set_location_assignment PIN_B1 -to sdram_addr[1] +set_location_assignment PIN_B3 -to sdram_addr[0] + +set_location_assignment PIN_J4 -to sdram_dq[15] +set_location_assignment PIN_J3 -to sdram_dq[14] +set_location_assignment PIN_H2 -to sdram_dq[13] +set_location_assignment PIN_G4 -to sdram_dq[12] +set_location_assignment PIN_E3 -to sdram_dq[11] +set_location_assignment PIN_D2 -to sdram_dq[10] +set_location_assignment PIN_C3 -to sdram_dq[9] +set_location_assignment PIN_J1 -to sdram_dq[8] +set_location_assignment PIN_B6 -to sdram_dq[7] +set_location_assignment PIN_A6 -to sdram_dq[6] +set_location_assignment PIN_C7 -to sdram_dq[5] +set_location_assignment PIN_A8 -to sdram_dq[4] +set_location_assignment PIN_B8 -to sdram_dq[3] +set_location_assignment PIN_C8 -to sdram_dq[2] +set_location_assignment PIN_A7 -to sdram_dq[1] +set_location_assignment PIN_B7 -to sdram_dq[0] + +set_location_assignment PIN_C6 -to sdram_dqm[0] +set_location_assignment PIN_J2 -to sdram_dqm[1] + +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb_sdram_top -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME tb_uart_sdram -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_uart_sdram +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_uart_sdram +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_uart_sdram -section_id tb_uart_sdram +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VERILOG_FILE ../rtl/fifo_read.v +set_global_assignment -name VERILOG_FILE ../rtl/sdram/sdram_write.v +set_global_assignment -name VERILOG_FILE ../rtl/sdram/sdram_top.v +set_global_assignment -name VERILOG_FILE ../rtl/sdram/sdram_read.v +set_global_assignment -name VERILOG_FILE ../rtl/sdram/sdram_init.v +set_global_assignment -name VERILOG_FILE ../rtl/sdram/sdram_ctrl.v +set_global_assignment -name VERILOG_FILE ../rtl/sdram/sdram_arbit.v +set_global_assignment -name VERILOG_FILE ../rtl/sdram/sdram_a_ref.v +set_global_assignment -name VERILOG_FILE ../rtl/sdram/fifo_ctrl.v +set_global_assignment -name QIP_FILE ip_core/fifo_data/fifo_data.qip +set_global_assignment -name QIP_FILE ip_core/clk_gen/clk_gen.qip +set_global_assignment -name VERILOG_FILE ../rtl/uart_tx.v +set_global_assignment -name VERILOG_FILE ../rtl/uart_sdram.v +set_global_assignment -name VERILOG_FILE ../rtl/uart_rx.v +set_global_assignment -name QIP_FILE ip_core/read_fifo/read_fifo.qip +set_global_assignment -name EDA_TEST_BENCH_NAME tb_sdram_init -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_sdram_init +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_sdram_init +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_sdram_init -section_id tb_sdram_init +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp/stp1.stp +set_global_assignment -name SLD_FILE "E:/sources/sdram_test/uart_sdram/project/output_files/stp/stp1_auto_stripped.stp" +set_global_assignment -name EDA_TEST_BENCH_NAME tb_sdram_a_ref -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_sdram_a_ref +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_sdram_a_ref +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_sdram_a_ref -section_id tb_sdram_a_ref +set_global_assignment -name EDA_TEST_BENCH_NAME tb_sdram_write -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_sdram_write +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_sdram_write +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_sdram_write -section_id tb_sdram_write +set_global_assignment -name EDA_TEST_BENCH_NAME tb_sdram_read -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_sdram_read +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_sdram_read +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_sdram_read -section_id tb_sdram_read +set_global_assignment -name EDA_TEST_BENCH_NAME tb_sdram_ctrl -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_sdram_ctrl +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_sdram_ctrl +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_sdram_ctrl -section_id tb_sdram_ctrl +set_global_assignment -name EDA_TEST_BENCH_NAME tb_sdram_top -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_sdram_top +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_sdram_top +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_sdram_top -section_id tb_sdram_top +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_uart_sdram.v -section_id tb_uart_sdram +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/sdram_model_plus.v -section_id tb_uart_sdram +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_sdram_init/tb_sdram_init.v -section_id tb_sdram_init +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_sdram_init/sdram_model_plus.v -section_id tb_sdram_init +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_sdram_a_ref/tb_sdram_a_ref.v -section_id tb_sdram_a_ref +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_sdram_a_ref/sdram_model_plus.v -section_id tb_sdram_a_ref +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_sdram_write/tb_sdram_write.v -section_id tb_sdram_write +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_sdram_write/sdram_model_plus.v -section_id tb_sdram_write +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_sdram_read/tb_sdram_read.v -section_id tb_sdram_read +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_sdram_read/sdram_model_plus.v -section_id tb_sdram_read +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_sdram_ctrl/tb_sdram_ctrl.v -section_id tb_sdram_ctrl +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_sdram_ctrl/sdram_model_plus.v -section_id tb_sdram_ctrl +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_sdram_top/sdram_model_plus.v -section_id tb_sdram_top +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_sdram_top/tb_sdram_top.v -section_id tb_sdram_top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/uart_sdram.qws b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/uart_sdram.qws new file mode 100644 index 0000000..d0b8df7 Binary files /dev/null and b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/project/uart_sdram.qws differ diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/fifo_read.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/fifo_read.v new file mode 100644 index 0000000..22e5aca --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/fifo_read.v @@ -0,0 +1,151 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : fifo_read +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SDRAM数据回传缓存模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module fifo_read +( + input wire sys_clk , //系统时钟，频率50MHz + input wire sys_rst_n , //复位信号,低电平有效 + input wire [9:0] rd_fifo_num , //SDRAM中读fifo中数据个数 + input wire [7:0] pi_data , //读出数据 + input wire [9:0] burst_num , //一次突发数据个数 + + output reg read_en , //SDRAM中读fifo的读使能 + output wire [7:0] tx_data , //输出数据 + output reg tx_flag //输出数据标志信号 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// + +//parameter define +parameter BAUD_CNT_END = 13'd5207 , + BAUD_CNT_END_HALF = 13'd2603 ; +parameter CNT_WAIT_MAX = 24'd4_999_999 ; + +//wire define +wire [9:0] data_num ; //fifo中数据个数 + +//reg define +reg read_en_dly ; +reg [12:0] baud_cnt ; +reg rd_en ; +reg rd_flag ; +reg [9:0] cnt_read ; +reg [3:0] bit_cnt ; +reg bit_flag ; + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//read_en:SDRAM中读fifo的读使能 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + read_en <= 1'b0; + else if(rd_fifo_num == burst_num) + read_en <= 1'b1; + else if(data_num == burst_num - 2) + read_en <= 1'b0; + +//read_en_dly:SDRAM中读fifo的读使能打拍 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + read_en_dly <= 1'b0; + else + read_en_dly <= read_en; + +//rd_flag:向tx模块发送数据使能 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rd_flag <= 1'b0; + else if(cnt_read == burst_num) + rd_flag <= 1'b0; + else if(data_num == burst_num) + rd_flag <= 1'b1; + +//baud_cnt:波特率计数器计数从0计数到BAUD_CNT_END +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + baud_cnt <= 13'd0; + else if(baud_cnt == BAUD_CNT_END) + baud_cnt <= 13'd0; + else if(rd_flag == 1'b1) + baud_cnt <= baud_cnt + 1'b1; + +//bit_flag:bit计数器计数使能 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + bit_flag <= 1'b0; + else if(baud_cnt == BAUD_CNT_END_HALF) + bit_flag <= 1'b1; + else + bit_flag <= 1'b0; + +//bit_cnt:bit计数器 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + bit_cnt <= 4'b0; + else if((bit_cnt == 4'd9) && (bit_flag == 1'b1)) + bit_cnt <= 4'b0; + else if(bit_flag == 1'b1) + bit_cnt <= bit_cnt + 1'b1; + +//rd_en:读fifo的读使能 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rd_en <= 1'b0; + else if(bit_cnt == 4'd9 && bit_flag == 1'b1) + rd_en <= 1'b1; + else + rd_en <= 1'b0; + +//cnt_read:读出数据计数 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_read <= 10'd0; + else if(cnt_read == burst_num) + cnt_read <= 10'b0; + else if(rd_en == 1'b1) + cnt_read <= cnt_read + 1'b1; + else + cnt_read <= cnt_read; + +//tx_flag:读出数据标志信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + tx_flag <= 1'b0; + else + tx_flag <= rd_en; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//-------------fifo_read_inst-------------- +read_fifo read_fifo_inst( + .clock (sys_clk ), //input clk + .data (pi_data ), //input [7 : 0] din + .wrreq (read_en_dly ), //input wr_en + .rdreq (rd_en ), //input rd_en + + .q (tx_data ), //output [7 : 0] dout + .usedw (data_num ) +); + +endmodule diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/fifo_ctrl.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/fifo_ctrl.v new file mode 100644 index 0000000..aae3f2b --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/fifo_ctrl.v @@ -0,0 +1,188 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : fifo_ctrl +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : FIFO控制模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module fifo_ctrl +( + input wire sys_clk , //系统时钟 + input wire sys_rst_n , //复位信号 +//写fifo信号 + input wire wr_fifo_wr_clk , //写FIFO写时钟 + input wire wr_fifo_wr_req , //写FIFO写请求 + input wire [15:0] wr_fifo_wr_data , //写FIFO写数据 + input wire [23:0] sdram_wr_b_addr , //写SDRAM首地址 + input wire [23:0] sdram_wr_e_addr , //写SDRAM末地址 + input wire [9:0] wr_burst_len , //写SDRAM数据突发长度 + input wire wr_rst , //写复位信号 +//读fifo信号 + input wire rd_fifo_rd_clk , //读FIFO读时钟 + input wire rd_fifo_rd_req , //读FIFO读请求 + input wire [23:0] sdram_rd_b_addr , //读SDRAM首地址 + input wire [23:0] sdram_rd_e_addr , //读SDRAM末地址 + input wire [9:0] rd_burst_len , //读SDRAM数据突发长度 + input wire rd_rst , //读复位信号 + output wire [15:0] rd_fifo_rd_data , //读FIFO读数据 + output wire [9:0] rd_fifo_num , //读fifo中的数据量 + + input wire read_valid , //SDRAM读使能 + input wire init_end , //SDRAM初始化完成标志 +//SDRAM写信号 + input wire sdram_wr_ack , //SDRAM写响应 + output reg sdram_wr_req , //SDRAM写请求 + output reg [23:0] sdram_wr_addr , //SDRAM写地址 + output wire [15:0] sdram_data_in , //写入SDRAM的数据 +//SDRAM读信号 + input wire sdram_rd_ack , //SDRAM读相应 + input wire [15:0] sdram_data_out , //读出SDRAM数据 + output reg sdram_rd_req , //SDRAM读请求 + output reg [23:0] sdram_rd_addr //SDRAM读地址 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// + +//wire define +wire wr_ack_fall ; //写响应信号下降沿 +wire rd_ack_fall ; //读相应信号下降沿 +wire [9:0] wr_fifo_num ; //写fifo中的数据量 + +//reg define +reg wr_ack_dly ; //写响应打拍 +reg rd_ack_dly ; //读响应打拍 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +//wr_ack_dly:写响应信号打拍 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + wr_ack_dly <= 1'b0; + else + wr_ack_dly <= sdram_wr_ack; + +//rd_ack_dly:读响应信号打拍 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rd_ack_dly <= 1'b0; + else + rd_ack_dly <= sdram_rd_ack; + +//wr_ack_fall,rd_ack_fall:检测读写响应信号下降沿 +assign wr_ack_fall = (wr_ack_dly & ~sdram_wr_ack); +assign rd_ack_fall = (rd_ack_dly & ~sdram_rd_ack); + +//sdram_wr_addr:sdram写地址 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + sdram_wr_addr <= 24'd0; + else if(wr_rst == 1'b1) + sdram_wr_addr <= sdram_wr_b_addr; + else if(wr_ack_fall == 1'b1) //一次突发写结束,更改写地址 + begin + if(sdram_wr_addr < (sdram_wr_e_addr - wr_burst_len)) + //不使用乒乓操作,一次突发写结束,更改写地址,未达到末地址,写地址累加 + sdram_wr_addr <= sdram_wr_addr + wr_burst_len; + else //不使用乒乓操作,到达末地址,回到写起始地址 + sdram_wr_addr <= sdram_wr_b_addr; + end + +//sdram_rd_addr:sdram读地址 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + sdram_rd_addr <= 24'd0; + else if(rd_rst == 1'b1) + sdram_rd_addr <= sdram_rd_b_addr; + else if(rd_ack_fall == 1'b1) //一次突发读结束,更改读地址 + begin + if(sdram_rd_addr < (sdram_rd_e_addr - rd_burst_len)) + //读地址未达到末地址,读地址累加 + sdram_rd_addr <= sdram_rd_addr + rd_burst_len; + else //到达末地址,回到首地址 + sdram_rd_addr <= sdram_rd_b_addr; + end + +//sdram_wr_req,sdram_rd_req:读写请求信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + sdram_wr_req <= 1'b0; + sdram_rd_req <= 1'b0; + end + else if(init_end == 1'b1) //初始化完成后响应读写请求 + begin //优先执行写操作，防止写入SDRAM中的数据丢失 + if(wr_fifo_num >= wr_burst_len) + begin //写FIFO中的数据量达到写突发长度 + sdram_wr_req <= 1'b1; //写请求有效 + sdram_rd_req <= 1'b0; + end + else if((rd_fifo_num < rd_burst_len) && (read_valid == 1'b1)) + begin //读FIFO中的数据量小于读突发长度,且读使能信号有效 + sdram_wr_req <= 1'b0; + sdram_rd_req <= 1'b1; //读请求有效 + end + else + begin + sdram_wr_req <= 1'b0; + sdram_rd_req <= 1'b0; + end + end + else + begin + sdram_wr_req <= 1'b0; + sdram_rd_req <= 1'b0; + end + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- wr_fifo_data ------------- +fifo_data wr_fifo_data( + //用户接口 + .wrclk (wr_fifo_wr_clk ), //写时钟 + .wrreq (wr_fifo_wr_req ), //写请求 + .data (wr_fifo_wr_data), //写数据 + //SDRAM接口 + .rdclk (sys_clk ), //读时钟 + .rdreq (sdram_wr_ack ), //读请求 + .q (sdram_data_in ), //读数据 + + .rdusedw (wr_fifo_num ), //FIFO中的数据量 + .wrusedw ( ), + .aclr (~sys_rst_n || wr_rst) //清零信号 + ); + +//------------- rd_fifo_data ------------- +fifo_data rd_fifo_data( + //sdram接口 + .wrclk (sys_clk ), //写时钟 + .wrreq (sdram_rd_ack ), //写请求 + .data (sdram_data_out ), //写数据 + //用户接口 + .rdclk (rd_fifo_rd_clk ), //读时钟 + .rdreq (rd_fifo_rd_req ), //读请求 + .q (rd_fifo_rd_data), //读数据 + + .rdusedw ( ), + .wrusedw (rd_fifo_num ), //FIFO中的数据量 + .aclr (~sys_rst_n || rd_rst) //清零信号 + ); + +endmodule diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_a_ref.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_a_ref.v new file mode 100644 index 0000000..3b35822 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_a_ref.v @@ -0,0 +1,208 @@ +`timescale 1ns/1ns +////////////////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : sdram_a_ref +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SDRAM自动刷新模块 +// +// Revision :V1.1 +// Additional Comments: +// +// 实验平台:野火FPGA开发板 +// 公司 :http://www.embedfire.com +// 论坛 :http://www.firebbs.cn +// 淘宝 :https://fire-stm32.taobao.com +////////////////////////////////////////////////////////////////////////////////// + +module sdram_a_ref +( + input wire sys_clk , //系统时钟,频率100MHz + input wire sys_rst_n , //复位信号,低电平有效 + input wire init_end , //初始化结束信号 + input wire aref_en , //自动刷新使能 + + output reg aref_req , //自动刷新请求 + output reg [3:0] aref_cmd , //自动刷新阶段写入sdram的指令,{cs_n,ras_n,cas_n,we_n} + output reg [1:0] aref_ba , //自动刷新阶段Bank地址 + output reg [12:0] aref_addr , //地址数据,辅助预充电操作,A12-A0,13位地址 + output wire aref_end //自动刷新结束标志 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// + +//parameter define +parameter CNT_REF_MAX = 10'd749 ; //自动刷新等待时钟数(7.5us) +parameter TRP_CLK = 3'd2 , //预充电等待周期 + TRC_CLK = 3'd7 ; //自动刷新等待周期 +parameter P_CHARGE = 4'b0010 , //预充电指令 + A_REF = 4'b0001 , //自动刷新指令 + NOP = 4'b0111 ; //空操作指令 +parameter AREF_IDLE = 3'b000 , //初始状态,等待自动刷新使能 + AREF_PCHA = 3'b001 , //预充电状态 + AREF_TRP = 3'b011 , //预充电等待 tRP + AUTO_REF = 3'b010 , //自动刷新状态 + AREF_TRF = 3'b100 , //自动刷新等待 tRC + AREF_END = 3'b101 ; //自动刷新结束 + +//wire define +wire trp_end ; //预充电等待结束标志 +wire trc_end ; //自动刷新等待结束标志 +wire aref_ack ; //自动刷新应答信号 + +//reg define +reg [9:0] cnt_aref ; //自动刷新计数器 +reg [2:0] aref_state ; //SDRAM自动刷新状态 +reg [2:0] cnt_clk ; //时钟周期计数,记录自刷新阶段各状态等待时间 +reg cnt_clk_rst ; //时钟周期计数复位标志 +reg [1:0] cnt_aref_aref ; //自动刷新次数计数器 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +//cnt_ref:刷新计数器 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_aref <= 10'd0; + else if(cnt_aref >= CNT_REF_MAX) + cnt_aref <= 10'd0; + else if(init_end == 1'b1) + cnt_aref <= cnt_aref + 1'b1; + +//aref_req:自动刷新请求 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + aref_req <= 1'b0; + else if(cnt_aref == (CNT_REF_MAX - 1'b1)) + aref_req <= 1'b1; + else if(aref_ack == 1'b1) + aref_req <= 1'b0; + +//aref_ack:自动刷新应答信号 +assign aref_ack = (aref_state == AREF_PCHA ) ? 1'b1 : 1'b0; + +//aref_end:自动刷新结束标志 +assign aref_end = (aref_state == AREF_END ) ? 1'b1 : 1'b0; + +//cnt_clk:时钟周期计数,记录初始化各状态等待时间 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_clk <= 3'd0; + else if(cnt_clk_rst == 1'b1) + cnt_clk <= 3'd0; + else + cnt_clk <= cnt_clk + 1'b1; + +//trp_end,trc_end,tmrd_end:等待结束标志 +assign trp_end = ((aref_state == AREF_TRP) + && (cnt_clk == TRP_CLK )) ? 1'b1 : 1'b0; +assign trc_end = ((aref_state == AREF_TRF) + && (cnt_clk == TRC_CLK )) ? 1'b1 : 1'b0; + +//cnt_aref_aref:初始化过程自动刷新次数计数器 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_aref_aref <= 2'd0; + else if(aref_state == AREF_IDLE) + cnt_aref_aref <= 2'd0; + else if(aref_state == AUTO_REF) + cnt_aref_aref <= cnt_aref_aref + 1'b1; + else + cnt_aref_aref <= cnt_aref_aref; + +//SDRAM自动刷新状态机 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + aref_state <= AREF_IDLE; + else + case(aref_state) + AREF_IDLE: + if((aref_en == 1'b1) && (init_end == 1'b1)) + aref_state <= AREF_PCHA; + else + aref_state <= aref_state; + AREF_PCHA: + aref_state <= AREF_TRP; + AREF_TRP: + if(trp_end == 1'b1) + aref_state <= AUTO_REF; + else + aref_state <= aref_state; + AUTO_REF: + aref_state <= AREF_TRF; + AREF_TRF: + if(trc_end == 1'b1) + if(cnt_aref_aref == 2'd2) + aref_state <= AREF_END; + else + aref_state <= AUTO_REF; + else + aref_state <= aref_state; + AREF_END: + aref_state <= AREF_IDLE; + default: + aref_state <= AREF_IDLE; + endcase + +//cnt_clk_rst:时钟周期计数复位标志 +always@(*) + begin + case (aref_state) + AREF_IDLE: cnt_clk_rst <= 1'b1; //时钟周期计数器清零 + AREF_TRP: cnt_clk_rst <= (trp_end == 1'b1) ? 1'b1 : 1'b0; + //等待结束标志有效,计数器清零 + AREF_TRF: cnt_clk_rst <= (trc_end == 1'b1) ? 1'b1 : 1'b0; + //等待结束标志有效,计数器清零 + AREF_END: cnt_clk_rst <= 1'b1; + default: cnt_clk_rst <= 1'b0; + endcase + end + +//SDRAM操作指令控制 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + aref_cmd <= NOP; + aref_ba <= 2'b11; + aref_addr <= 13'h1fff; + end + else + case(aref_state) + AREF_IDLE,AREF_TRP,AREF_TRF: //执行空操作指令 + begin + aref_cmd <= NOP; + aref_ba <= 2'b11; + aref_addr <= 13'h1fff; + end + AREF_PCHA: //预充电指令 + begin + aref_cmd <= P_CHARGE; + aref_ba <= 2'b11; + aref_addr <= 13'h1fff; + end + AUTO_REF: //自动刷新指令 + begin + aref_cmd <= A_REF; + aref_ba <= 2'b11; + aref_addr <= 13'h1fff; + end + AREF_END: //一次自动刷新完成 + begin + aref_cmd <= NOP; + aref_ba <= 2'b11; + aref_addr <= 13'h1fff; + end + default: + begin + aref_cmd <= NOP; + aref_ba <= 2'b11; + aref_addr <= 13'h1fff; + end + endcase + +endmodule diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_arbit.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_arbit.v new file mode 100644 index 0000000..710b98d --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_arbit.v @@ -0,0 +1,180 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : sdram_arbit +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SDRAM仲裁模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module sdram_arbit +( + input wire sys_clk , //系统时钟 + input wire sys_rst_n , //复位信号 +//sdram_init + input wire [3:0] init_cmd , //初始化阶段命令 + input wire init_end , //初始化结束标志 + input wire [1:0] init_ba , //初始化阶段Bank地址 + input wire [12:0] init_addr , //初始化阶段数据地址 +//sdram_auto_ref + input wire aref_req , //自刷新请求 + input wire aref_end , //自刷新结束 + input wire [3:0] aref_cmd , //自刷新阶段命令 + input wire [1:0] aref_ba , //自动刷新阶段Bank地址 + input wire [12:0] aref_addr , //自刷新阶段数据地址 +//sdram_write + input wire wr_req , //写数据请求 + input wire [1:0] wr_ba , //写阶段Bank地址 + input wire [15:0] wr_data , //写入SDRAM的数据 + input wire wr_end , //一次写结束信号 + input wire [3:0] wr_cmd , //写阶段命令 + input wire [12:0] wr_addr , //写阶段数据地址 + input wire wr_sdram_en , +//sdram_read + input wire rd_req , //读数据请求 + input wire rd_end , //一次读结束 + input wire [3:0] rd_cmd , //读阶段命令 + input wire [12:0] rd_addr , //读阶段数据地址 + input wire [1:0] rd_ba , //读阶段Bank地址 + + output reg aref_en , //自刷新使能 + output reg wr_en , //写数据使能 + output reg rd_en , //读数据使能 + + output wire sdram_cke , //SDRAM时钟使能 + output wire sdram_cs_n , //SDRAM片选信号 + output wire sdram_ras_n , //SDRAM行地址选通 + output wire sdram_cas_n , //SDRAM列地址选通 + output wire sdram_we_n , //SDRAM写使能 + output reg [1:0] sdram_ba , //SDRAM Bank地址 + output reg [12:0] sdram_addr , //SDRAM地址总线 + inout wire [15:0] sdram_dq //SDRAM数据总线 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// + +//parameter define +parameter IDLE = 5'b0_0001 , //初始状态 + ARBIT = 5'b0_0010 , //仲裁状态 + AREF = 5'b0_0100 , //自动刷新状态 + WRITE = 5'b0_1000 , //写状态 + READ = 5'b1_0000 ; //读状态 +parameter CMD_NOP = 4'b0111 ; //空操作指令 + +//reg define +reg [3:0] sdram_cmd ; //写入SDRAM命令 +reg [4:0] state ; //状态机状态 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +//state：状态机状态 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + state <= IDLE; + else case(state) + IDLE: if(init_end == 1'b1) + state <= ARBIT; + else + state <= IDLE; + ARBIT:if(aref_req == 1'b1) + state <= AREF; + else if(wr_req == 1'b1) + state <= WRITE; + else if(rd_req == 1'b1) + state <= READ; + else + state <= ARBIT; + AREF: if(aref_end == 1'b1) + state <= ARBIT; + else + state <= AREF; + WRITE: if(wr_end == 1'b1) + state <= ARBIT; + else + state <= WRITE; + READ: if(rd_end == 1'b1) + state <= ARBIT; + else + state <= READ; + default:state <= IDLE; + endcase + +//aref_en：自动刷新使能 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + aref_en <= 1'b0; + else if((state == ARBIT) && (aref_req == 1'b1)) + aref_en <= 1'b1; + else if(aref_end == 1'b1) + aref_en <= 1'b0; + +//wr_en：写数据使能 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + wr_en <= 1'b0; + else if((state == ARBIT) && (aref_req == 1'b0) && (wr_req == 1'b1)) + wr_en <= 1'b1; + else if(wr_end == 1'b1) + wr_en <= 1'b0; + +//rd_en：读数据使能 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rd_en <= 1'b0; + else if((state == ARBIT) && (aref_req == 1'b0) && (rd_req == 1'b1)) + rd_en <= 1'b1; + else if(rd_end == 1'b1) + rd_en <= 1'b0; + +//sdram_cmd:写入SDRAM命令;sdram_ba:SDRAM Bank地址;sdram_addr:SDRAM地址总线 +always@(*) + case(state) + IDLE: begin + sdram_cmd <= init_cmd; + sdram_ba <= init_ba; + sdram_addr <= init_addr; + end + AREF: begin + sdram_cmd <= aref_cmd; + sdram_ba <= aref_ba; + sdram_addr <= aref_addr; + end + WRITE: begin + sdram_cmd <= wr_cmd; + sdram_ba <= wr_ba; + sdram_addr <= wr_addr; + end + READ: begin + sdram_cmd <= rd_cmd; + sdram_ba <= rd_ba; + sdram_addr <= rd_addr; + end + default: begin + sdram_cmd <= CMD_NOP; + sdram_ba <= 2'b11; + sdram_addr <= 13'h1fff; + end + endcase + +//SDRAM时钟使能 +assign sdram_cke = 1'b1; +//SDRAM数据总线 +assign sdram_dq = (wr_sdram_en == 1'b1) ? wr_data : 16'bz; +//片选信号,行地址选通信号,列地址选通信号,写使能信号 +assign {sdram_cs_n, sdram_ras_n, sdram_cas_n, sdram_we_n} = sdram_cmd; + +endmodule diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_ctrl.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_ctrl.v new file mode 100644 index 0000000..32b78b9 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_ctrl.v @@ -0,0 +1,195 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : sdram_ctrl +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SDRAM控制模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module sdram_ctrl +( + input wire sys_clk , //系统时钟 + input wire sys_rst_n , //复位信号，低电平有效 +//SDRAM写端口 + input wire sdram_wr_req , //写SDRAM请求信号 + input wire [23:0] sdram_wr_addr , //SDRAM写操作的地址 + input wire [9:0] wr_burst_len , //写sdram时数据突发长度 + input wire [15:0] sdram_data_in , //写入SDRAM的数据 + output wire sdram_wr_ack , //写SDRAM响应信号 +//SDRAM读端口 + input wire sdram_rd_req , //读SDRAM请求信号 + input wire [23:0] sdram_rd_addr , //SDRAM读操作的地址 + input wire [9:0] rd_burst_len , //读sdram时数据突发长度 + output wire [15:0] sdram_data_out , //从SDRAM读出的数据 + output wire init_end , //SDRAM 初始化完成标志 + output wire sdram_rd_ack , //读SDRAM响应信号 +//FPGA与SDRAM硬件接口 + output wire sdram_cke , // SDRAM 时钟有效信号 + output wire sdram_cs_n , // SDRAM 片选信号 + output wire sdram_ras_n , // SDRAM 行地址选通 + output wire sdram_cas_n , // SDRAM 列地址选通 + output wire sdram_we_n , // SDRAM 写使能 + output wire [1:0] sdram_ba , // SDRAM Bank地址 + output wire [12:0] sdram_addr , // SDRAM 地址总线 + inout wire [15:0] sdram_dq // SDRAM 数据总线 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// + +//wire define +//sdram_init +wire [3:0] init_cmd ; //初始化阶段写入sdram的指令 +wire [1:0] init_ba ; //初始化阶段Bank地址 +wire [12:0] init_addr ; //初始化阶段地址数据,辅助预充电操作 +//sdram_a_ref +wire aref_req ; //自动刷新请求 +wire aref_end ; //自动刷新结束标志 +wire [3:0] aref_cmd ; //自动刷新阶段写入sdram的指令 +wire [1:0] aref_ba ; //自动刷新阶段Bank地址 +wire [12:0] aref_addr ; //地址数据,辅助预充电操作 +wire aref_en ; //自动刷新使能 +//sdram_write +wire wr_en ; //写使能 +wire wr_end ; //一次写结束信号 +wire [3:0] write_cmd ; //写阶段命令 +wire [1:0] write_ba ; //写数据阶段Bank地址 +wire [12:0] write_addr ; //写阶段数据地址 +wire wr_sdram_en ; //SDRAM写使能 +wire [15:0] wr_sdram_data; //写入SDRAM的数据 +//sdram_read +wire rd_en ; //读使能 +wire rd_end ; //一次突发读结束 +wire [3:0] read_cmd ; //读数据阶段写入sdram的指令 +wire [1:0] read_ba ; //读阶段Bank地址 +wire [12:0] read_addr ; //读阶段数据地址 + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// +//------------- sdram_init_inst ------------- +sdram_init sdram_init_inst +( + .sys_clk (sys_clk ), //系统时钟,频率100MHz + .sys_rst_n (sys_rst_n ), //复位信号,低电平有效 + + .init_cmd (init_cmd ), //初始化阶段写入sdram的指令 + .init_ba (init_ba ), //初始化阶段Bank地址 + .init_addr (init_addr ), //初始化阶段地址数据,辅助预充电操作 + .init_end (init_end ) //初始化结束信号 +); + +//------------- sdram_arbit_inst ------------- +sdram_arbit sdram_arbit_inst +( + .sys_clk (sys_clk ), //系统时钟 + .sys_rst_n (sys_rst_n ), //复位信号 +//sdram_init + .init_cmd (init_cmd ), //初始化阶段命令 + .init_end (init_end ), //初始化结束标志 + .init_ba (init_ba ), //初始化阶段Bank地址 + .init_addr (init_addr ), //初始化阶段数据地址 +//sdram_auto_ref + .aref_req (aref_req ), //自刷新请求 + .aref_end (aref_end ), //自刷新结束 + .aref_cmd (aref_cmd ), //自刷新阶段命令 + .aref_ba (aref_ba ), //自动刷新阶段Bank地址 + .aref_addr (aref_addr ), //自刷新阶段数据地址 +//sdram_write + .wr_req (sdram_wr_req ), //写数据请求 + .wr_end (wr_end ), //一次写结束信号 + .wr_cmd (write_cmd ), //写阶段命令 + .wr_ba (write_ba ), //写阶段Bank地址 + .wr_addr (write_addr ), //写阶段数据地址 + .wr_sdram_en(wr_sdram_en ), //SDRAM写使能 + .wr_data (wr_sdram_data ), //写入SDRAM的数据 +//sdram_read + .rd_req (sdram_rd_req ), //读数据请求 + .rd_end (rd_end ), //一次读结束 + .rd_cmd (read_cmd ), //读阶段命令 + .rd_addr (read_addr ), //读阶段数据地址 + .rd_ba (read_ba ), //读阶段Bank地址 + + .aref_en (aref_en ), //自刷新使能 + .wr_en (wr_en ), //写数据使能 + .rd_en (rd_en ), //读数据使能 + + .sdram_cke (sdram_cke ), //SDRAM时钟使能 + .sdram_cs_n (sdram_cs_n ), //SDRAM片选信号 + .sdram_ras_n(sdram_ras_n ), //SDRAM行地址选通 + .sdram_cas_n(sdram_cas_n ), //SDRAM列地址选通 + .sdram_we_n (sdram_we_n ), //SDRAM写使能 + .sdram_ba (sdram_ba ), //SDRAM Bank地址 + .sdram_addr (sdram_addr ), //SDRAM地址总线 + .sdram_dq (sdram_dq ) //SDRAM数据总线 +); + +//------------- sdram_a_ref_inst ------------- +sdram_a_ref sdram_a_ref_inst +( + .sys_clk (sys_clk ), //系统时钟,频率100MHz + .sys_rst_n (sys_rst_n ), //复位信号,低电平有效 + .init_end (init_end ), //初始化结束信号 + .aref_en (aref_en ), //自动刷新使能 + + .aref_req (aref_req ), //自动刷新请求 + .aref_cmd (aref_cmd ), //自动刷新阶段写入sdram的指令 + .aref_ba (aref_ba ), //自动刷新阶段Bank地址 + .aref_addr (aref_addr ), //地址数据,辅助预充电操作 + .aref_end (aref_end ) //自动刷新结束标志 +); + +//------------- sdram_write_inst ------------- +sdram_write sdram_write_inst +( + .sys_clk (sys_clk ), //系统时钟,频率100MHz + .sys_rst_n (sys_rst_n ), //复位信号,低电平有效 + .init_end (init_end ), //初始化结束信号 + .wr_en (wr_en ), //写使能 + + .wr_addr (sdram_wr_addr ), //写SDRAM地址 + .wr_data (sdram_data_in ), //待写入SDRAM的数据(写FIFO传入) + .wr_burst_len (wr_burst_len ), //写突发SDRAM字节数 + + .wr_ack (sdram_wr_ack ), //写SDRAM响应信号 + .wr_end (wr_end ), //一次突发写结束 + .write_cmd (write_cmd ), //写数据阶段写入sdram的指令 + .write_ba (write_ba ), //写数据阶段Bank地址 + .write_addr (write_addr ), //地址数据,辅助预充电操作 + .wr_sdram_en (wr_sdram_en ), //数据总线输出使能 + .wr_sdram_data (wr_sdram_data ) //写入SDRAM的数据 +); + +//------------- sdram_read_inst ------------- +sdram_read sdram_read_inst +( + .sys_clk (sys_clk ), //系统时钟,频率100MHz + .sys_rst_n (sys_rst_n ), //复位信号,低电平有效 + .init_end (init_end ), //初始化结束信号 + .rd_en (rd_en ), //读使能 + + .rd_addr (sdram_rd_addr ), //读SDRAM地址 + .rd_data (sdram_dq ), //自SDRAM中读出的数据 + .rd_burst_len (rd_burst_len ), //读突发SDRAM字节数 + + .rd_ack (sdram_rd_ack ), //读SDRAM响应信号 + .rd_end (rd_end ), //一次突发读结束 + .read_cmd (read_cmd ), //读数据阶段写入sdram的指令 + .read_ba (read_ba ), //读数据阶段Bank地址 + .read_addr (read_addr ), //地址数据,辅助预充电操作 + .rd_sdram_data (sdram_data_out ) //SDRAM读出的数据 +); + +endmodule diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_init.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_init.v new file mode 100644 index 0000000..9fc99f6 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_init.v @@ -0,0 +1,229 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : sdram_init +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SDRAM初始化模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module sdram_init +( + input wire sys_clk , //系统时钟,频率100MHz + input wire sys_rst_n , //复位信号,低电平有效 + + output reg [3:0] init_cmd , //初始化阶段写入sdram的指令,{cs_n,ras_n,cas_n,we_n} + output reg [1:0] init_ba , //初始化阶段Bank地址 + output reg [12:0] init_addr , //初始化阶段地址数据,辅助预充电操作 + //和配置模式寄存器操作,A12-A0,共13位 + output wire init_end //初始化结束信号 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// + +// parameter define +parameter T_POWER = 15'd20_000 ; //上电后等待时钟数(200us) +//SDRAM初始化用到的控制信号命令 +parameter P_CHARGE = 4'b0010 , //预充电指令 + AUTO_REF = 4'b0001 , //自动刷新指令 + NOP = 4'b0111 , //空操作指令 + M_REG_SET = 4'b0000 ; //模式寄存器设置指令 +//SDRAM初始化过程各个状态 +parameter INIT_IDLE = 3'b000 , //初始状态 + INIT_PRE = 3'b001 , //预充电状态 + INIT_TRP = 3'b011 , //预充电等待 tRP + INIT_AR = 3'b010 , //自动刷新 + INIT_TRF = 3'b100 , //自动刷新等待 tRC + INIT_MRS = 3'b101 , //模式寄存器设置 + INIT_TMRD = 3'b111 , //模式寄存器设置等待 tMRD + INIT_END = 3'b110 ; //初始化完成 +parameter TRP_CLK = 3'd2 , //预充电等待周期,20ns + TRC_CLK = 3'd7 , //自动刷新等待,70ns + TMRD_CLK = 3'd3 ; //模式寄存器设置等待周期,30ns + +// wire define +wire wait_end ; //上电后200us等待结束标志 +wire trp_end ; //预充电等待结束标志 +wire trc_end ; //自动刷新等待结束标志 +wire tmrd_end ; //模式寄存器设置等待结束标志 + +// reg define +reg [14:0] cnt_200us ; //SDRAM上电后200us稳定期计数器 +reg [2:0] init_state ; //SDRAM初始化状态 +reg [2:0] cnt_clk ; //时钟周期计数,记录初始化各状态等待周期数 +reg cnt_clk_rst ; //时钟周期计数复位标志 +reg [3:0] cnt_init_aref ; //初始化过程自动刷新次数计数器 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +//cnt_200us:SDRAM上电后200us稳定期计数器 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_200us <= 15'd0; + else if(cnt_200us == T_POWER) + cnt_200us <= T_POWER; + else + cnt_200us <= cnt_200us + 1'b1; + +//wait_end:上电后200us等待结束标志 +assign wait_end = (cnt_200us == (T_POWER - 1'b1)) ? 1'b1 : 1'b0; + +//init_end:SDRAM初始化完毕信号 +assign init_end = (init_state == INIT_END) ? 1'b1 : 1'b0; + +//cnt_clk:时钟周期计数,记录初始化各状态等待时间 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_clk <= 3'd0; + else if(cnt_clk_rst == 1'b1) + cnt_clk <= 3'd0; + else + cnt_clk <= cnt_clk + 1'b1; + +//cnt_init_aref:初始化过程自动刷新次数计数器 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_init_aref <= 4'd0; + else if(init_state == INIT_IDLE) + cnt_init_aref <= 4'd0; + else if(init_state == INIT_AR) + cnt_init_aref <= cnt_init_aref + 1'b1; + else + cnt_init_aref <= cnt_init_aref; + +//trp_end,trc_end,tmrd_end:等待结束标志 +assign trp_end = ((init_state == INIT_TRP ) + && (cnt_clk == TRP_CLK )) ? 1'b1 : 1'b0; +assign trc_end = ((init_state == INIT_TRF ) + && (cnt_clk == TRC_CLK )) ? 1'b1 : 1'b0; +assign tmrd_end = ((init_state == INIT_TMRD) + && (cnt_clk == TMRD_CLK)) ? 1'b1 : 1'b0; + +//SDRAM的初始化状态机 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + init_state <= INIT_IDLE; + else + case(init_state) + INIT_IDLE: //系统上电后,在初始状态等待200us跳转到预充电状态 + if(wait_end == 1'b1) + init_state <= INIT_PRE; + else + init_state <= init_state; + INIT_PRE: //预充电状态，直接跳转到预充电等待状态 + init_state <= INIT_TRP; + INIT_TRP: //预充电等待状态,等待结束,跳转到自动刷新状态 + if(trp_end == 1'b1) + init_state <= INIT_AR; + else + init_state <= init_state; + INIT_AR : //自动刷新状态,直接跳转到自动刷新等待状态 + init_state <= INIT_TRF; + INIT_TRF: //自动刷新等待状态,等待结束,自动跳转到模式寄存器设置状态 + if(trc_end == 1'b1) + if(cnt_init_aref == 4'd8) + init_state <= INIT_MRS; + else + init_state <= INIT_AR; + else + init_state <= init_state; + INIT_MRS: //模式寄存器设置状态,直接跳转到模式寄存器设置等待状态 + init_state <= INIT_TMRD; + INIT_TMRD: //模式寄存器设置等待状态,等待结束,跳到初始化完成状态 + if(tmrd_end == 1'b1) + init_state <= INIT_END; + else + init_state <= init_state; + INIT_END: //初始化完成状态,保持此状态 + init_state <= INIT_END; + default: init_state <= INIT_IDLE; + endcase + +//cnt_clk_rst:时钟周期计数复位标志 +always@(*) + begin + case (init_state) + INIT_IDLE: cnt_clk_rst <= 1'b1; //时钟周期计数复位信号,高有效,时钟周期计数清零 + INIT_TRP: cnt_clk_rst <= (trp_end == 1'b1) ? 1'b1 : 1'b0; + //等待结束标志有效,计数器清零 + INIT_TRF: cnt_clk_rst <= (trc_end == 1'b1) ? 1'b1 : 1'b0; + //等待结束标志有效,计数器清零 + INIT_TMRD: cnt_clk_rst <= (tmrd_end == 1'b1) ? 1'b1 : 1'b0; + //等待结束标志有效,计数器清零 + INIT_END: cnt_clk_rst <= 1'b1; //初始化完成,计数器清零 + default: cnt_clk_rst <= 1'b0; + endcase + end + +//SDRAM操作指令控制 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + init_cmd <= NOP; + init_ba <= 2'b11; + init_addr <= 13'h1fff; + end + else + case(init_state) + INIT_IDLE,INIT_TRP,INIT_TRF,INIT_TMRD: //执行空操作指令 + begin + init_cmd <= NOP; + init_ba <= 2'b11; + init_addr <= 13'h1fff; + end + INIT_PRE: //预充电指令 + begin + init_cmd <= P_CHARGE; + init_ba <= 2'b11; + init_addr <= 13'h1fff; + end + INIT_AR: //自动刷新指令 + begin + init_cmd <= AUTO_REF; + init_ba <= 2'b11; + init_addr <= 13'h1fff; + end + INIT_MRS: //模式寄存器设置指令 + begin + init_cmd <= M_REG_SET; + init_ba <= 2'b00; + init_addr <= + { //地址辅助配置模式寄存器,参数不同,配置的模式不同 + 3'b000, //A12-A10:预留 + 1'b0, //A9=0:读写方式,0:突发读&突发写,1:突发读&单写 + 2'b00, //{A8,A7}=00:标准模式,默认 + 3'b011, //{A6,A5,A4}=011:CAS潜伏期,010:2,011:3,其他:保留 + 1'b0, //A3=0:突发传输方式,0:顺序,1:隔行 + 3'b111 //{A2,A1,A0}=111:突发长度,000:单字节,001:2字节 + //010:4字节,011:8字节,111:整页,其他:保留 + }; + end + INIT_END: //SDRAM初始化完成 + begin + init_cmd <= NOP; + init_ba <= 2'b11; + init_addr <= 13'h1fff; + end + default: + begin + init_cmd <= NOP; + init_ba <= 2'b11; + init_addr <= 13'h1fff; + end + endcase + +endmodule diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_read.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_read.v new file mode 100644 index 0000000..4dcb13f --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_read.v @@ -0,0 +1,225 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : sdram_read +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SDRAM读数据模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module sdram_read +( + input wire sys_clk , //系统时钟,频率100MHz + input wire sys_rst_n , //复位信号,低电平有效 + input wire init_end , //初始化结束信号 + input wire rd_en , //读使能 + input wire [23:0] rd_addr , //读SDRAM地址 + input wire [15:0] rd_data , //自SDRAM中读出的数据 + input wire [9:0] rd_burst_len , //读突发SDRAM字节数 + + output wire rd_ack , //读SDRAM响应信号 + output wire rd_end , //一次突发读结束 + output reg [3:0] read_cmd , //读数据阶段写入sdram的指令,{cs_n,ras_n,cas_n,we_n} + output reg [1:0] read_ba , //读数据阶段Bank地址 + output reg [12:0] read_addr , //地址数据,辅助预充电操作,行、列地址,A12-A0,13位地址 + output wire [15:0] rd_sdram_data //SDRAM读出的数据 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// + +//parameter define +parameter TRCD_CLK = 10'd2 , //激活等待周期 + TCL_CLK = 10'd3 , //潜伏期 + TRP_CLK = 10'd2 ; //预充电等待周期 +parameter RD_IDLE = 4'b0000 , //空闲 + RD_ACTIVE = 4'b0001 , //激活 + RD_TRCD = 4'b0011 , //激活等待 + RD_READ = 4'b0010 , //读操作 + RD_CL = 4'b0100 , //潜伏期 + RD_DATA = 4'b0101 , //读数据 + RD_PRE = 4'b0111 , //预充电 + RD_TRP = 4'b0110 , //预充电等待 + RD_END = 4'b1100 ; //一次突发读结束 +parameter NOP = 4'b0111 , //空操作指令 + ACTIVE = 4'b0011 , //激活指令 + READ = 4'b0101 , //数据读指令 + B_STOP = 4'b0110 , //突发停止指令 + P_CHARGE = 4'b0010 ; //预充电指令 + +//wire define +wire trcd_end ; //激活等待周期结束 +wire trp_end ; //预充电等待周期结束 +wire tcl_end ; //潜伏期结束标志 +wire tread_end ; //突发读结束 +wire rdburst_end ; //读突发终止 + +//reg define +reg [3:0] read_state ; //SDRAM写状态 +reg [9:0] cnt_clk ; //时钟周期计数,记录初始化各状态等待时间 +reg cnt_clk_rst ; //时钟周期计数复位标志 +reg [15:0] rd_data_reg ; + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +//rd_data_reg +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rd_data_reg <= 16'd0; + else + rd_data_reg <= rd_data; + +//rd_end:一次突发读结束 +assign rd_end = (read_state == RD_END) ? 1'b1 : 1'b0; + +//rd_ack:读SDRAM响应信号 +assign rd_ack = (read_state == RD_DATA) + && (cnt_clk >= 10'd1) + && (cnt_clk < (rd_burst_len + 2'd1)); + +//cnt_clk:时钟周期计数,记录初始化各状态等待时间 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_clk <= 10'd0; + else if(cnt_clk_rst == 1'b1) + cnt_clk <= 10'd0; + else + cnt_clk <= cnt_clk + 1'b1; + +//trcd_end,trp_end,tcl_end,tread_end,rdburst_end:等待结束标志 +assign trcd_end = ((read_state == RD_TRCD) + && (cnt_clk == TRCD_CLK )) ? 1'b1 : 1'b0; //行选通周期结束 +assign trp_end = ((read_state == RD_TRP ) + && (cnt_clk == TRP_CLK )) ? 1'b1 : 1'b0; //预充电有效周期结束 +assign tcl_end = ((read_state == RD_CL ) + && (cnt_clk == TCL_CLK - 1 )) ? 1'b1 : 1'b0; //潜伏期结束 +assign tread_end = ((read_state == RD_DATA) + && (cnt_clk == rd_burst_len + 2)) ? 1'b1 : 1'b0; //突发读结束 +assign rdburst_end = ((read_state == RD_DATA) + && (cnt_clk == rd_burst_len - 4)) ? 1'b1 : 1'b0; //读突发终止 + +//read_state:SDRAM的工作状态机 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + read_state <= RD_IDLE; + else + case(read_state) + RD_IDLE: + if((rd_en ==1'b1) && (init_end == 1'b1)) + read_state <= RD_ACTIVE; + else + read_state <= RD_IDLE; + RD_ACTIVE: + read_state <= RD_TRCD; + RD_TRCD: + if(trcd_end == 1'b1) + read_state <= RD_READ; + else + read_state <= RD_TRCD; + RD_READ: + read_state <= RD_CL; + RD_CL: + read_state <= (tcl_end == 1'b1) ? RD_DATA : RD_CL; + RD_DATA: + read_state <= (tread_end == 1'b1) ? RD_PRE : RD_DATA; + RD_PRE: + read_state <= RD_TRP; + RD_TRP: + read_state <= (trp_end == 1'b1) ? RD_END : RD_TRP; + RD_END: + read_state <= RD_IDLE; + default: + read_state <= RD_IDLE; + endcase + +//计数器控制逻辑 +always@(*) + begin + case(read_state) + RD_IDLE: cnt_clk_rst <= 1'b1; + RD_TRCD: cnt_clk_rst <= (trcd_end == 1'b1) ? 1'b1 : 1'b0; + RD_READ: cnt_clk_rst <= 1'b1; + RD_CL: cnt_clk_rst <= (tcl_end == 1'b1) ? 1'b1 : 1'b0; + RD_DATA: cnt_clk_rst <= (tread_end == 1'b1) ? 1'b1 : 1'b0; + RD_TRP: cnt_clk_rst <= (trp_end == 1'b1) ? 1'b1 : 1'b0; + RD_END: cnt_clk_rst <= 1'b1; + default: cnt_clk_rst <= 1'b0; + endcase + end + +//SDRAM操作指令控制 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + read_cmd <= NOP; + read_ba <= 2'b11; + read_addr <= 13'h1fff; + end + else + case(read_state) + RD_IDLE,RD_TRCD,RD_TRP: + begin + read_cmd <= NOP; + read_ba <= 2'b11; + read_addr <= 13'h1fff; + end + RD_ACTIVE: //激活指令 + begin + read_cmd <= ACTIVE; + read_ba <= rd_addr[23:22]; + read_addr <= rd_addr[21:9]; + end + RD_READ: //读操作指令 + begin + read_cmd <= READ; + read_ba <= rd_addr[23:22]; + read_addr <= {4'b0000,rd_addr[8:0]}; + end + RD_DATA: //突发传输终止指令 + begin + if(rdburst_end == 1'b1) + read_cmd <= B_STOP; + else + begin + read_cmd <= NOP; + read_ba <= 2'b11; + read_addr <= 13'h1fff; + end + end + RD_PRE: //预充电指令 + begin + read_cmd <= P_CHARGE; + read_ba <= rd_addr[23:22]; + read_addr <= 13'h0400; + end + RD_END: + begin + read_cmd <= NOP; + read_ba <= 2'b11; + read_addr <= 13'h1fff; + end + default: + begin + read_cmd <= NOP; + read_ba <= 2'b11; + read_addr <= 13'h1fff; + end + endcase + +//rd_sdram_data:SDRAM读出的数据 +assign rd_sdram_data = (rd_ack == 1'b1) ? rd_data_reg : 16'b0; + +endmodule diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_top.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_top.v new file mode 100644 index 0000000..7b1655d --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_top.v @@ -0,0 +1,151 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : sdram_top +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SDRAM控制器顶层文件 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module sdram_top +( + input wire sys_clk , //系统时钟 + input wire clk_out , //相位偏移时钟 + input wire sys_rst_n , //复位信号,低有效 +//写FIFO信号 + input wire wr_fifo_wr_clk , //写FIFO写时钟 + input wire wr_fifo_wr_req , //写FIFO写请求 + input wire [15:0] wr_fifo_wr_data , //写FIFO写数据 + input wire [23:0] sdram_wr_b_addr , //写SDRAM首地址 + input wire [23:0] sdram_wr_e_addr , //写SDRAM末地址 + input wire [9:0] wr_burst_len , //写SDRAM数据突发长度 + input wire wr_rst , //写复位信号 +//读FIFO信号 + input wire rd_fifo_rd_clk , //读FIFO读时钟 + input wire rd_fifo_rd_req , //读FIFO读请求 + input wire [23:0] sdram_rd_b_addr , //读SDRAM首地址 + input wire [23:0] sdram_rd_e_addr , //读SDRAM末地址 + input wire [9:0] rd_burst_len , //读SDRAM数据突发长度 + input wire rd_rst , //读复位信号 + output wire [15:0] rd_fifo_rd_data , //读FIFO读数据 + output wire [9:0] rd_fifo_num , //读fifo中的数据量 + + input wire read_valid , //SDRAM读使能 + output wire init_end , //SDRAM初始化完成标志 +//SDRAM接口信号 + output wire sdram_clk , //SDRAM芯片时钟 + output wire sdram_cke , //SDRAM时钟有效信号 + output wire sdram_cs_n , //SDRAM片选信号 + output wire sdram_ras_n , //SDRAM行地址选通脉冲 + output wire sdram_cas_n , //SDRAM列地址选通脉冲 + output wire sdram_we_n , //SDRAM写允许位 + output wire [1:0] sdram_ba , //SDRAM的L-Bank地址线 + output wire [12:0] sdram_addr , //SDRAM地址总线 + output wire [1:0] sdram_dqm , //SDRAM数据掩码 + inout wire [15:0] sdram_dq //SDRAM数据总线 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// + +//wire define +wire sdram_wr_req ; //sdram 写请求 +wire sdram_wr_ack ; //sdram 写响应 +wire [23:0] sdram_wr_addr ; //sdram 写地址 +wire [15:0] sdram_data_in ; //写入sdram中的数据 + +wire sdram_rd_req ; //sdram 读请求 +wire sdram_rd_ack ; //sdram 读响应 +wire [23:0] sdram_rd_addr ; //sdram 读地址 +wire [15:0] sdram_data_out ; //从sdram中读出的数据 + +//sdram_clk:SDRAM芯片时钟 +assign sdram_clk = clk_out; +//sdram_dqm:SDRAM数据掩码 +assign sdram_dqm = 2'b00; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- fifo_ctrl_inst ------------- +fifo_ctrl fifo_ctrl_inst( + +//system signal + .sys_clk (sys_clk ), //SDRAM控制时钟 + .sys_rst_n (sys_rst_n ), //复位信号 +//write fifo signal + .wr_fifo_wr_clk (wr_fifo_wr_clk ), //写FIFO写时钟 + .wr_fifo_wr_req (wr_fifo_wr_req ), //写FIFO写请求 + .wr_fifo_wr_data(wr_fifo_wr_data), //写FIFO写数据 + .sdram_wr_b_addr(sdram_wr_b_addr), //写SDRAM首地址 + .sdram_wr_e_addr(sdram_wr_e_addr), //写SDRAM末地址 + .wr_burst_len (wr_burst_len ), //写SDRAM数据突发长度 + .wr_rst (wr_rst ), //写清零信号 +//read fifo signal + .rd_fifo_rd_clk (rd_fifo_rd_clk ), //读FIFO读时钟 + .rd_fifo_rd_req (rd_fifo_rd_req ), //读FIFO读请求 + .rd_fifo_rd_data(rd_fifo_rd_data), //读FIFO读数据 + .rd_fifo_num (rd_fifo_num ), //读FIFO中的数据量 + .sdram_rd_b_addr(sdram_rd_b_addr), //读SDRAM首地址 + .sdram_rd_e_addr(sdram_rd_e_addr), //读SDRAM末地址 + .rd_burst_len (rd_burst_len ), //读SDRAM数据突发长度 + .rd_rst (rd_rst ), //读清零信号 +//USER ctrl signal + .read_valid (read_valid ), //SDRAM读使能 + .init_end (init_end ), //SDRAM初始化完成标志 +//SDRAM ctrl of write + .sdram_wr_ack (sdram_wr_ack ), //SDRAM写响应 + .sdram_wr_req (sdram_wr_req ), //SDRAM写请求 + .sdram_wr_addr (sdram_wr_addr ), //SDRAM写地址 + .sdram_data_in (sdram_data_in ), //写入SDRAM的数据 +//SDRAM ctrl of read + .sdram_rd_ack (sdram_rd_ack ), //SDRAM读请求 + .sdram_data_out (sdram_data_out ), //SDRAM读响应 + .sdram_rd_req (sdram_rd_req ), //SDRAM读地址 + .sdram_rd_addr (sdram_rd_addr ) //读出SDRAM数据 + +); + +//------------- sdram_ctrl_inst ------------- +sdram_ctrl sdram_ctrl_inst( + + .sys_clk (sys_clk ), //系统时钟 + .sys_rst_n (sys_rst_n ), //复位信号，低电平有效 +//SDRAM 控制器写端口 + .sdram_wr_req (sdram_wr_req ), //写SDRAM请求信号 + .sdram_wr_addr (sdram_wr_addr ), //SDRAM写操作的地址 + .wr_burst_len (wr_burst_len ), //写sdram时数据突发长度 + .sdram_data_in (sdram_data_in ), //写入SDRAM的数据 + .sdram_wr_ack (sdram_wr_ack ), //写SDRAM响应信号 +//SDRAM 控制器读端口 + .sdram_rd_req (sdram_rd_req ), //读SDRAM请求信号 + .sdram_rd_addr (sdram_rd_addr ), //SDRAM写操作的地址 + .rd_burst_len (rd_burst_len ), //读sdram时数据突发长度 + .sdram_data_out (sdram_data_out ), //从SDRAM读出的数据 + .init_end (init_end ), //SDRAM 初始化完成标志 + .sdram_rd_ack (sdram_rd_ack ), //读SDRAM响应信号 +//FPGA与SDRAM硬件接口 + .sdram_cke (sdram_cke ), // SDRAM 时钟有效信号 + .sdram_cs_n (sdram_cs_n ), // SDRAM 片选信号 + .sdram_ras_n (sdram_ras_n ), // SDRAM 行地址选通脉冲 + .sdram_cas_n (sdram_cas_n ), // SDRAM 列地址选通脉冲 + .sdram_we_n (sdram_we_n ), // SDRAM 写允许位 + .sdram_ba (sdram_ba ), // SDRAM L-Bank地址线 + .sdram_addr (sdram_addr ), // SDRAM 地址总线 + .sdram_dq (sdram_dq ) // SDRAM 数据总线 + +); + +endmodule diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_write.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_write.v new file mode 100644 index 0000000..4febd1f --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/sdram/sdram_write.v @@ -0,0 +1,221 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : sdram_write +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SDRAM写数据模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module sdram_write +( + input wire sys_clk , //系统时钟,频率100MHz + input wire sys_rst_n , //复位信号,低电平有效 + input wire init_end , //初始化结束信号 + input wire wr_en , //写使能 + input wire [23:0] wr_addr , //写SDRAM地址 + input wire [15:0] wr_data , //待写入SDRAM的数据(写FIFO传入) + input wire [9:0] wr_burst_len , //写突发SDRAM字节数 + + output wire wr_ack , //写SDRAM响应信号 + output wire wr_end , //一次突发写结束 + output reg [3:0] write_cmd , //写数据阶段写入sdram的指令,{cs_n,ras_n,cas_n,we_n} + output reg [1:0] write_ba , //写数据阶段Bank地址 + output reg [12:0] write_addr , //地址数据,辅助预充电操作,行、列地址,A12-A0,13位地址 + output reg wr_sdram_en , //数据总线输出使能 + output wire [15:0] wr_sdram_data //写入SDRAM的数据 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// + +//parameter define +parameter TRCD_CLK = 10'd2 , //激活周期 + TRP_CLK = 10'd2 ; //预充电周期 +parameter WR_IDLE = 4'b0000 , //初始状态 + WR_ACTIVE = 4'b0001 , //激活 + WR_TRCD = 4'b0011 , //激活等待 + WR_WRITE = 4'b0010 , //写操作 + WR_DATA = 4'b0100 , //写数据 + WR_PRE = 4'b0101 , //预充电 + WR_TRP = 4'b0111 , //预充电等待 + WR_END = 4'b0110 ; //一次突发写结束 +parameter NOP = 4'b0111 , //空操作指令 + ACTIVE = 4'b0011 , //激活指令 + WRITE = 4'b0100 , //数据写指令 + B_STOP = 4'b0110 , //突发停止指令 + P_CHARGE = 4'b0010 ; //预充电指令 + +//wire define +wire trcd_end ; //激活等待周期结束 +wire twrite_end ; //突发写结束 +wire trp_end ; //预充电有效周期结束 + +//reg define +reg [3:0] write_state ; //SDRAM写状态 +reg [9:0] cnt_clk ; //时钟周期计数,记录写数据阶段各状态等待时间 +reg cnt_clk_rst ; //时钟周期计数复位标志 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +//wr_end:一次突发写结束 +assign wr_end = (write_state == WR_END) ? 1'b1 : 1'b0; + +//wr_ack:写SDRAM响应信号 +assign wr_ack = ( write_state == WR_WRITE) + || ((write_state == WR_DATA) + && (cnt_clk <= (wr_burst_len - 2'd2))); + +//cnt_clk:时钟周期计数,记录初始化各状态等待时间 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_clk <= 10'd0; + else if(cnt_clk_rst == 1'b1) + cnt_clk <= 10'd0; + else + cnt_clk <= cnt_clk + 1'b1; + +//trcd_end,twrite_end,trp_end:等待结束标志 +assign trcd_end = ((write_state == WR_TRCD) + &&(cnt_clk == TRCD_CLK )) ? 1'b1 : 1'b0; //激活周期结束 +assign twrite_end = ((write_state == WR_DATA) + &&(cnt_clk == wr_burst_len - 1)) ? 1'b1 : 1'b0; //突发写结束 +assign trp_end = ((write_state == WR_TRP ) + &&(cnt_clk == TRP_CLK )) ? 1'b1 : 1'b0; //预充电等待周期结束 + +//write_state:SDRAM的工作状态机 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + write_state <= WR_IDLE; + else + case(write_state) + WR_IDLE: + if((wr_en ==1'b1) && (init_end == 1'b1)) + write_state <= WR_ACTIVE; + else + write_state <= write_state; + WR_ACTIVE: + write_state <= WR_TRCD; + WR_TRCD: + if(trcd_end == 1'b1) + write_state <= WR_WRITE; + else + write_state <= write_state; + WR_WRITE: + write_state <= WR_DATA; + WR_DATA: + if(twrite_end == 1'b1) + write_state <= WR_PRE; + else + write_state <= write_state; + WR_PRE: + write_state <= WR_TRP; + WR_TRP: + if(trp_end == 1'b1) + write_state <= WR_END; + else + write_state <= write_state; + + WR_END: + write_state <= WR_IDLE; + default: + write_state <= WR_IDLE; + endcase + +//计数器控制逻辑 +always@(*) + begin + case(write_state) + WR_IDLE: cnt_clk_rst <= 1'b1; + WR_TRCD: cnt_clk_rst <= (trcd_end == 1'b1) ? 1'b1 : 1'b0; + WR_WRITE: cnt_clk_rst <= 1'b1; + WR_DATA: cnt_clk_rst <= (twrite_end == 1'b1) ? 1'b1 : 1'b0; + WR_TRP: cnt_clk_rst <= (trp_end == 1'b1) ? 1'b1 : 1'b0; + WR_END: cnt_clk_rst <= 1'b1; + default: cnt_clk_rst <= 1'b0; + endcase + end + +//SDRAM操作指令控制 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + begin + write_cmd <= NOP; + write_ba <= 2'b11; + write_addr <= 13'h1fff; + end + else + case(write_state) + WR_IDLE,WR_TRCD,WR_TRP: + begin + write_cmd <= NOP; + write_ba <= 2'b11; + write_addr <= 13'h1fff; + end + WR_ACTIVE: //激活指令 + begin + write_cmd <= ACTIVE; + write_ba <= wr_addr[23:22]; + write_addr <= wr_addr[21:9]; + end + WR_WRITE: //写操作指令 + begin + write_cmd <= WRITE; + write_ba <= wr_addr[23:22]; + write_addr <= {4'b0000,wr_addr[8:0]}; + end + WR_DATA: //突发传输终止指令 + begin + if(twrite_end == 1'b1) + write_cmd <= B_STOP; + else + begin + write_cmd <= NOP; + write_ba <= 2'b11; + write_addr <= 13'h1fff; + end + end + WR_PRE: //预充电指令 + begin + write_cmd <= P_CHARGE; + write_ba <= wr_addr[23:22]; + write_addr <= 13'h0400; + end + WR_END: + begin + write_cmd <= NOP; + write_ba <= 2'b11; + write_addr <= 13'h1fff; + end + default: + begin + write_cmd <= NOP; + write_ba <= 2'b11; + write_addr <= 13'h1fff; + end + endcase + +//wr_sdram_en:数据总线输出使能 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + wr_sdram_en <= 1'b0; + else + wr_sdram_en <= wr_ack; + +//wr_sdram_data:写入SDRAM的数据 +assign wr_sdram_data = (wr_sdram_en == 1'b1) ? wr_data : 16'd0; + +endmodule diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/uart_rx.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/uart_rx.v new file mode 100644 index 0000000..01bd165 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/uart_rx.v @@ -0,0 +1,154 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +//Create Date : 2019/06/12 +// Module Name : uart_rx +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module uart_rx +#( + parameter UART_BPS = 'd9600, //串口波特率 + parameter CLK_FREQ = 'd50_000_000 //时钟频率 +) +( + input wire sys_clk , //系统时钟50MHz + input wire sys_rst_n , //全局复位 + input wire rx , //串口接收数据 + + output reg [7:0] po_data , //串转并后的8bit数据 + output reg po_flag //串转并后的数据有效标志信号 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//localparam define +localparam BAUD_CNT_MAX = CLK_FREQ/UART_BPS ; + +//reg define +reg rx_reg1 ; +reg rx_reg2 ; +reg rx_reg3 ; +reg start_nedge ; +reg work_en ; +reg [12:0] baud_cnt ; +reg bit_flag ; +reg [3:0] bit_cnt ; +reg [7:0] rx_data ; +reg rx_flag ; + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//插入两级寄存器进行数据同步，用来消除亚稳态 +//rx_reg1:第一级寄存器，寄存器空闲状态复位为1 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rx_reg1 <= 1'b1; + else + rx_reg1 <= rx; + +//rx_reg2:第二级寄存器，寄存器空闲状态复位为1 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rx_reg2 <= 1'b1; + else + rx_reg2 <= rx_reg1; + +//rx_reg3:第三级寄存器和第二级寄存器共同构成下降沿检测 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rx_reg3 <= 1'b1; + else + rx_reg3 <= rx_reg2; + +//start_nedge:检测到下降沿时start_nedge产生一个时钟的高电平 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + start_nedge <= 1'b0; + else if((~rx_reg2) && (rx_reg3)) + start_nedge <= 1'b1; + else + start_nedge <= 1'b0; + +//work_en:接收数据工作使能信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + work_en <= 1'b0; + else if(start_nedge == 1'b1) + work_en <= 1'b1; + else if((bit_cnt == 4'd8) && (bit_flag == 1'b1)) + work_en <= 1'b0; + +//baud_cnt:波特率计数器计数，从0计数到BAUD_CNT_MAX - 1 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + baud_cnt <= 13'b0; + else if((baud_cnt == BAUD_CNT_MAX - 1) || (work_en == 1'b0)) + baud_cnt <= 13'b0; + else if(work_en == 1'b1) + baud_cnt <= baud_cnt + 1'b1; + +//bit_flag:当baud_cnt计数器计数到中间数时采样的数据最稳定， +//此时拉高一个标志信号表示数据可以被取走 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + bit_flag <= 1'b0; + else if(baud_cnt == BAUD_CNT_MAX/2 - 1) + bit_flag <= 1'b1; + else + bit_flag <= 1'b0; + +//bit_cnt:有效数据个数计数器，当8个有效数据（不含起始位和停止位） +//都接收完成后计数器清零 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + bit_cnt <= 4'b0; + else if((bit_cnt == 4'd8) && (bit_flag == 1'b1)) + bit_cnt <= 4'b0; + else if(bit_flag ==1'b1) + bit_cnt <= bit_cnt + 1'b1; + +//rx_data:输入数据进行移位 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rx_data <= 8'b0; + else if((bit_cnt >= 4'd1)&&(bit_cnt <= 4'd8)&&(bit_flag == 1'b1)) + rx_data <= {rx_reg3, rx_data[7:1]}; + +//rx_flag:输入数据移位完成时rx_flag拉高一个时钟的高电平 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + rx_flag <= 1'b0; + else if((bit_cnt == 4'd8) && (bit_flag == 1'b1)) + rx_flag <= 1'b1; + else + rx_flag <= 1'b0; + +//po_data:输出完整的8位有效数据 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + po_data <= 8'b0; + else if(rx_flag == 1'b1) + po_data <= rx_data; + +//po_flag:输出数据有效标志（比rx_flag延后一个时钟周期，为了和po_data同步） +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + po_flag <= 1'b0; + else + po_flag <= rx_flag; + +endmodule diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/uart_sdram.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/uart_sdram.v new file mode 100644 index 0000000..d50ebcb --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/uart_sdram.v @@ -0,0 +1,208 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : uart_sdram +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : uart_sdram顶层模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module uart_sdram +( + input wire sys_clk , //时钟信号 + input wire sys_rst_n , //复位信号 + input wire rx , //串口接收数据 + + output wire tx , //串口发送数据 + + output wire sdram_clk , //SDRAM 芯片时钟 + output wire sdram_cke , //SDRAM 时钟有效 + output wire sdram_cs_n , //SDRAM 片选 + output wire sdram_cas_n , //SDRAM 行有效 + output wire sdram_ras_n , //SDRAM 列有效 + output wire sdram_we_n , //SDRAM 写有效 + output wire [1:0] sdram_ba , //SDRAM Bank地址 + output wire [12:0] sdram_addr , //SDRAM 行/列地址 + output wire [1:0] sdram_dqm , //SDRAM 数据掩码 + inout wire [15:0] sdram_dq //SDRAM 数据 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter DATA_NUM = 24'd10 ; //写入SDRAM数据个数 +parameter WAIT_MAX = 16'd750 ; //等待计数最大值 +parameter UART_BPS = 14'd9600 , //比特率 + CLK_FREQ = 26'd50_000_000 ; //时钟频率 + +// wire define +//uart_rx +wire [ 7:0] rx_data ; //串口接收模块拼接后的8位数据 +wire rx_flag ; //数据标志信号 + +//fifo_read +wire [ 7:0] rfifo_wr_data ; //读fifo发热写入数据 +wire rfifo_wr_en ; //读fifo的写使能 +wire [ 7:0] rfifo_rd_data ; //读fifo的读数据 +wire rfifo_rd_en ; //读fifo的读使能 +wire [9:0] rd_fifo_num ; //读fifo中的数据量 + +//clk_gen +wire clk_50m ; +wire clk_100m ; +wire clk_100m_shift ; //pll产生时钟 +wire locked ; //pll锁定信号 +wire rst_n ; //复位信号 + +//sdram_top_inst +reg [23:0] data_num ; //写入SDRAM数据个数计数 +reg read_valid ; //数据读使能 +reg [15:0] cnt_wait ; //等待计数器 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//rst_n:复位信号 +assign rst_n = sys_rst_n & locked; + +//data_num:写入SDRAM数据个数计数 +always@(posedge clk_50m or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + data_num <= 24'd0; + else if(read_valid == 1'b1) + data_num <= 24'd0; + else if(rx_flag == 1'b1) + data_num <= data_num + 1'b1; + else + data_num <= data_num; + +//cnt_wait:等待计数器 +always@(posedge clk_50m or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_wait <= 16'd0; + else if(cnt_wait == WAIT_MAX) + cnt_wait <= 16'd0; + else if(data_num == DATA_NUM) + cnt_wait <= cnt_wait + 1'b1; + +//read_valid:数据读使能 +always@(posedge clk_50m or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + read_valid <= 1'b0; + else if(cnt_wait == WAIT_MAX) + read_valid <= 1'b1; + else if(rd_fifo_num == DATA_NUM) + read_valid <= 1'b0; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// +//------------- clk_gen_inst ------------- +clk_gen clk_gen_inst ( + .inclk0 (sys_clk ), + .areset (~sys_rst_n ), + .c0 (clk_50m ), + .c1 (clk_100m ), + .c2 (clk_100m_shift ), + + .locked (locked ) +); + +//-------------uart_rx_inst------------- +uart_rx +#( + .UART_BPS (UART_BPS ), //串口波特率 + .CLK_FREQ (CLK_FREQ ) //时钟频率 +) +uart_rx_inst +( + .sys_clk (clk_50m ), //input sys_clk + .sys_rst_n (rst_n ), //input sys_rst_n + .rx (rx ), //input rx + + .po_data (rx_data ), //output [7:0] rx_data + .po_flag (rx_flag ) //output rx_flag +); + +//------------- sdram_top_inst ------------- +sdram_top sdram_top_inst +( + .sys_clk (clk_100m ), //sdram 控制器参考时钟 + .clk_out (clk_100m_shift ), //用于输出的相位偏移时钟 + .sys_rst_n (rst_n ), //系统复位 +//用户写端口 + .wr_fifo_wr_clk (clk_50m ), //写端口FIFO: 写时钟 + .wr_fifo_wr_req (rx_flag ), //写端口FIFO: 写使能 + .wr_fifo_wr_data ({8'b0,rx_data} ), //写端口FIFO: 写数据 + .sdram_wr_b_addr (24'd0 ), //写SDRAM的起始地址 + .sdram_wr_e_addr (DATA_NUM ), //写SDRAM的结束地址 + .wr_burst_len (DATA_NUM ), //写SDRAM时的数据突发长度 + .wr_rst ( ), //写复位 +//用户读端口 + .rd_fifo_rd_clk (clk_50m ), //读端口FIFO: 读时钟 + .rd_fifo_rd_req (rfifo_wr_en ), //读端口FIFO: 读使能 + .rd_fifo_rd_data (rfifo_wr_data ), //读端口FIFO: 读数据 + .sdram_rd_b_addr (24'd0 ), //读SDRAM的起始地址 + .sdram_rd_e_addr (DATA_NUM ), //读SDRAM的结束地址 + .rd_burst_len (DATA_NUM ), //从SDRAM中读数据时的突发长度 + .rd_rst ( ), //读复位 + .rd_fifo_num (rd_fifo_num ), //读fifo中的数据量 +//用户控制端口 + .read_valid (read_valid ), //SDRAM 读使能 + .init_end ( ), //SDRAM 初始化完成标志 +//SDRAM 芯片接口 + .sdram_clk (sdram_clk ), //SDRAM 芯片时钟 + .sdram_cke (sdram_cke ), //SDRAM 时钟有效 + .sdram_cs_n (sdram_cs_n ), //SDRAM 片选 + .sdram_ras_n (sdram_ras_n ), //SDRAM 行有效 + .sdram_cas_n (sdram_cas_n ), //SDRAM 列有效 + .sdram_we_n (sdram_we_n ), //SDRAM 写有效 + .sdram_ba (sdram_ba ), //SDRAM Bank地址 + .sdram_addr (sdram_addr ), //SDRAM 行/列地址 + .sdram_dq (sdram_dq ), //SDRAM 数据 + .sdram_dqm (sdram_dqm ) //SDRAM 数据掩码 +); + +//------------- fifo_read_inst -------------- +fifo_read fifo_read_inst +( + .sys_clk (clk_50m ), //input sys_clk + .sys_rst_n (sys_rst_n ), //input sys_rst_n + .rd_fifo_num (rd_fifo_num ), + .pi_data (rfifo_wr_data ), //input [7:0] pi_data + .burst_num (DATA_NUM ), + + .read_en (rfifo_wr_en ), //input pi_flag + .tx_data (rfifo_rd_data ), //output [7:0] tx_data + .tx_flag (rfifo_rd_en ) //output tx_flag + +); + +//-------------uart_tx_inst------------- +uart_tx +#( + .UART_BPS (UART_BPS ), //串口波特率 + .CLK_FREQ (CLK_FREQ ) //时钟频率 +) +uart_tx_inst +( + .sys_clk (sys_clk ), //input sys_clk + .sys_rst_n (sys_rst_n ), //input sys_rst_n + .pi_data (rfifo_rd_data ), //input [7:0] pi_data + .pi_flag (rfifo_rd_en ), //input pi_flag + + .tx (tx ) //output tx +); + +endmodule \ No newline at end of file diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/uart_tx.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/uart_tx.v new file mode 100644 index 0000000..9447945 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/rtl/uart_tx.v @@ -0,0 +1,104 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/06/12 +// Module Name : uart_tx +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module uart_tx +#( + parameter UART_BPS = 'd9600, //串口波特率 + parameter CLK_FREQ = 'd50_000_000 //时钟频率 +) +( + input wire sys_clk , //系统时钟50MHz + input wire sys_rst_n , //全局复位 + input wire [7:0] pi_data , //模块输入的8bit数据 + input wire pi_flag , //并行数据有效标志信号 + + output reg tx //串转并后的1bit数据 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//localparam define +localparam BAUD_CNT_MAX = CLK_FREQ/UART_BPS ; + +//reg define +reg [12:0] baud_cnt; +reg bit_flag; +reg [3:0] bit_cnt ; +reg work_en ; + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// +//work_en:接收数据工作使能信号 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + work_en <= 1'b0; + else if(pi_flag == 1'b1) + work_en <= 1'b1; + else if((bit_flag == 1'b1) && (bit_cnt == 4'd9)) + work_en <= 1'b0; + +//baud_cnt:波特率计数器计数，从0计数到BAUD_CNT_MAX - 1 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + baud_cnt <= 13'b0; + else if((baud_cnt == BAUD_CNT_MAX - 1) || (work_en == 1'b0)) + baud_cnt <= 13'b0; + else if(work_en == 1'b1) + baud_cnt <= baud_cnt + 1'b1; + +//bit_flag:当baud_cnt计数器计数到1时让bit_flag拉高一个时钟的高电平 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + bit_flag <= 1'b0; + else if(baud_cnt == 13'd1) + bit_flag <= 1'b1; + else + bit_flag <= 1'b0; + +//bit_cnt:数据位数个数计数，10个有效数据（含起始位和停止位）到来后计数器清零 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + bit_cnt <= 4'b0; + else if((bit_flag == 1'b1) && (bit_cnt == 4'd9)) + bit_cnt <= 4'b0; + else if((bit_flag == 1'b1) && (work_en == 1'b1)) + bit_cnt <= bit_cnt + 1'b1; + +//tx:输出数据在满足rs232协议（起始位为0，停止位为1）的情况下一位一位输出 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + tx <= 1'b1; //空闲状态时为高电平 + else if(bit_flag == 1'b1) + case(bit_cnt) + 0 : tx <= 1'b0; + 1 : tx <= pi_data[0]; + 2 : tx <= pi_data[1]; + 3 : tx <= pi_data[2]; + 4 : tx <= pi_data[3]; + 5 : tx <= pi_data[4]; + 6 : tx <= pi_data[5]; + 7 : tx <= pi_data[6]; + 8 : tx <= pi_data[7]; + 9 : tx <= 1'b1; + default : tx <= 1'b1; + endcase + +endmodule diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/sdram_model_plus.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/sdram_model_plus.v new file mode 100644 index 0000000..4e51287 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/sdram_model_plus.v @@ -0,0 +1,1131 @@ +/*************************************************************************************** +ߣ +2003-08-27 V0.1 + + ڴģ鵹չܣⲿҪ¼sdram_r ,SDRAMݽᰴBank ˳damp out ļ + sdram_data.txt +*/ +//2004-03-04 ˿ ޸ԭнBANKתTXTļĸʽ +//2004-03-16 ˿ ޸SDRAM ijʼ +//2004/04/06 ˿ SDRAMIJַʽʾԱMODELSIM +//2004/04/19 ˿ ޸IJ parameter tAC = 8; +//2010/09/17 ޸sdramĴСλdqm; +/**************************************************************************************** +* +* File Name: sdram_model.V +* Version: 0.0f +* Date: July 8th, 1999 +* Model: BUS Functional +* Simulator: Model Technology (PC version 5.2e PE) +* +* Dependencies: None +* +* Author: Son P. Huynh +* Email: sphuynh@micron.com +* Phone: (208) 368-3825 +* Company: Micron Technology, Inc. +* Model: sdram_model (1Meg x 16 x 4 Banks) +* +* Description: 64Mb SDRAM Verilog model +* +* Limitation: - Doesn't check for 4096 cycle refresh +* +* Note: - Set simulator resolution to "ps" accuracy +* - Set Debug = 0 to disable $display messages +* +* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +* +* Copyright ?1998 Micron Semiconductor Products, Inc. +* All rights researved +* +* Rev Author Phone Date Changes +* ---- ---------------------------- ---------- --------------------------------------- +* 0.0f Son Huynh 208-368-3825 07/08/1999 - Fix tWR = 1 Clk + 7.5 ns (Auto) +* Micron Technology Inc. - Fix tWR = 15 ns (Manual) +* - Fix tRP (Autoprecharge to AutoRefresh) +* +* 0.0a Son Huynh 208-368-3825 05/13/1998 - First Release (from 64Mb rev 0.0e) +* Micron Technology Inc. +****************************************************************************************/ + +`timescale 1ns / 100ps + +module sdram_model_plus (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm,Debug); + + parameter addr_bits = 11; + parameter data_bits = 32; + parameter col_bits = 8; + parameter mem_sizes = 1048576*2-1;//1 Meg + + inout [data_bits - 1 : 0] Dq; + input [addr_bits - 1 : 0] Addr; + input [1 : 0] Ba; + input Clk; + input Cke; + input Cs_n; + input Ras_n; + input Cas_n; + input We_n; + input [3 : 0] Dqm; //ߵ͸8bit + //added by xzli + input Debug; + + reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];//洢 + reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes]; + + reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline + reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline + reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline + reg [3 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline + reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr; + + reg [addr_bits - 1 : 0] Mode_reg; + reg [data_bits - 1 : 0] Dq_reg, Dq_dqm; + reg [col_bits - 1 : 0] Col_temp, Burst_counter; + + reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate + reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge + + reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command + reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks) + reg Auto_precharge [0 : 3]; // RW AutoPrecharge (Bank) + reg Read_precharge [0 : 3]; // R AutoPrecharge + reg Write_precharge [0 : 3]; // W AutoPrecharge + integer Count_precharge [0 : 3]; // RW AutoPrecharge (Counter) + reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge + reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge + + reg Data_in_enable; + reg Data_out_enable; + + reg [1 : 0] Bank, Previous_bank; + reg [addr_bits - 1 : 0] Row; + reg [col_bits - 1 : 0] Col, Col_brst; + + // Internal system clock + reg CkeZ, Sys_clk; + + reg [21:0] dd; + + // Commands Decode + wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n; + wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n; + wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n; + wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n; + wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n; + wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n; + wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n; + + // Burst Length Decode + wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0]; + wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; + + // CAS Latency Decode + wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4]; + wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4]; + + // Write Burst Mode + wire Write_burst_mode = Mode_reg[9]; + + wire Debug; // Debug messages : 1 = On; 0 = Off + wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ + + reg [31:0] mem_d; + + event sdram_r,sdram_w,compare; + + + + + assign Dq = Dq_reg; // DQ buffer + + // Commands Operation + `define ACT 0 + `define NOP 1 + `define READ 2 + `define READ_A 3 + `define WRITE 4 + `define WRITE_A 5 + `define PRECH 6 + `define A_REF 7 + `define BST 8 + `define LMR 9 + +// // Timing Parameters for -75 (PC133) and CAS Latency = 2 +// parameter tAC = 8; //test 6.5 +// parameter tHZ = 7.0; +// parameter tOH = 2.7; +// parameter tMRD = 2.0; // 2 Clk Cycles +// parameter tRAS = 44.0; +// parameter tRC = 66.0; +// parameter tRCD = 20.0; +// parameter tRP = 20.0; +// parameter tRRD = 15.0; +// parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) +// parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns) + + // Timing Parameters for -7 (PC143) and CAS Latency = 3 + parameter tAC = 6.5; //test 6.5 + parameter tHZ = 5.5; + parameter tOH = 2; + parameter tMRD = 2.0; // 2 Clk Cycles + parameter tRAS = 48.0; + parameter tRC = 70.0; + parameter tRCD = 20.0; + parameter tRP = 20.0; + parameter tRRD = 14.0; + parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) + parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns) + + // Timing Check variable + integer MRD_chk; + integer WR_counter [0 : 3]; + time WR_chk [0 : 3]; + time RC_chk, RRD_chk; + time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3; + time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; + time RP_chk0, RP_chk1, RP_chk2, RP_chk3; + + integer test_file; + + //*****display the command of the sdram************************************** + + parameter Mode_Reg_Set =4'b0000; + parameter Auto_Refresh =4'b0001; + parameter Row_Active =4'b0011; + parameter Pre_Charge =4'b0010; + parameter PreCharge_All =4'b0010; + parameter Write =4'b0100; + parameter Write_Pre =4'b0100; + parameter Read =4'b0101; + parameter Read_Pre =4'b0101; + parameter Burst_Stop =4'b0110; + parameter Nop =4'b0111; + parameter Dsel =4'b1111; + + wire [3:0] sdram_control; + reg cke_temp; + reg [8*13:1] sdram_command; + + always@(posedge Clk) + cke_temp<=Cke; + + assign sdram_control={Cs_n,Ras_n,Cas_n,We_n}; + + always@(sdram_control or cke_temp) + begin + case(sdram_control) + Mode_Reg_Set: sdram_command<="Mode_Reg_Set"; + Auto_Refresh: sdram_command<="Auto_Refresh"; + Row_Active: sdram_command<="Row_Active"; + Pre_Charge: sdram_command<="Pre_Charge"; + Burst_Stop: sdram_command<="Burst_Stop"; + Dsel: sdram_command<="Dsel"; + + Write: if(cke_temp==1) + sdram_command<="Write"; + else + sdram_command<="Write_suspend"; + + Read: if(cke_temp==1) + sdram_command<="Read"; + else + sdram_command<="Read_suspend"; + + Nop: if(cke_temp==1) + sdram_command<="Nop"; + else + sdram_command<="Self_refresh"; + + default: sdram_command<="Power_down"; + endcase + end + + //***************************************************** + + initial + begin + //test_file=$fopen("test_file.txt"); + end + + initial + begin + Dq_reg = {data_bits{1'bz}}; + {Data_in_enable, Data_out_enable} = 0; + {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000; + {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000; + {WR_chk[0], WR_chk[1], WR_chk[2], WR_chk[3]} = 0; + {WR_counter[0], WR_counter[1], WR_counter[2], WR_counter[3]} = 0; + {RW_interrupt_read[0], RW_interrupt_read[1], RW_interrupt_read[2], RW_interrupt_read[3]} = 0; + {RW_interrupt_write[0], RW_interrupt_write[1], RW_interrupt_write[2], RW_interrupt_write[3]} = 0; + {MRD_chk, RC_chk, RRD_chk} = 0; + {RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0; + {RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0; + {RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0; + $timeformat (-9, 0, " ns", 12); + //$readmemh("bank0.txt", Bank0); + //$readmemh("bank1.txt", Bank1); + //$readmemh("bank2.txt", Bank2); + //$readmemh("bank3.txt", Bank3); +/* + for(dd=0;dd<=mem_sizes;dd=dd+1) + begin + Bank0[dd]=dd[data_bits - 1 : 0]; + Bank1[dd]=dd[data_bits - 1 : 0]+1; + Bank2[dd]=dd[data_bits - 1 : 0]+2; + Bank3[dd]=dd[data_bits - 1 : 0]+3; + end +*/ + initial_sdram(0); + end + + task initial_sdram; + + input data_sign; + reg [3:0] data_sign; + + for(dd=0;dd<=mem_sizes;dd=dd+1) + begin + mem_d = {data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign}; + if(data_bits==16) + begin + Bank0[dd]=mem_d[15:0]; + Bank1[dd]=mem_d[15:0]; + Bank2[dd]=mem_d[15:0]; + Bank3[dd]=mem_d[15:0]; + end + else if(data_bits==32) + begin + Bank0[dd]=mem_d[31:0]; + Bank1[dd]=mem_d[31:0]; + Bank2[dd]=mem_d[31:0]; + Bank3[dd]=mem_d[31:0]; + end + end + + endtask + + // System clock generator + always + begin + @(posedge Clk) + begin + Sys_clk = CkeZ; + CkeZ = Cke; + end + @(negedge Clk) + begin + Sys_clk = 1'b0; + end + end + + always @ (posedge Sys_clk) begin + // Internal Commamd Pipelined + Command[0] = Command[1]; + Command[1] = Command[2]; + Command[2] = Command[3]; + Command[3] = `NOP; + + Col_addr[0] = Col_addr[1]; + Col_addr[1] = Col_addr[2]; + Col_addr[2] = Col_addr[3]; + Col_addr[3] = {col_bits{1'b0}}; + + Bank_addr[0] = Bank_addr[1]; + Bank_addr[1] = Bank_addr[2]; + Bank_addr[2] = Bank_addr[3]; + Bank_addr[3] = 2'b0; + + Bank_precharge[0] = Bank_precharge[1]; + Bank_precharge[1] = Bank_precharge[2]; + Bank_precharge[2] = Bank_precharge[3]; + Bank_precharge[3] = 2'b0; + + A10_precharge[0] = A10_precharge[1]; + A10_precharge[1] = A10_precharge[2]; + A10_precharge[2] = A10_precharge[3]; + A10_precharge[3] = 1'b0; + + // Dqm pipeline for Read + Dqm_reg0 = Dqm_reg1; + Dqm_reg1 = Dqm; + + // Read or Write with Auto Precharge Counter + if (Auto_precharge[0] == 1'b1) begin + Count_precharge[0] = Count_precharge[0] + 1; + end + if (Auto_precharge[1] == 1'b1) begin + Count_precharge[1] = Count_precharge[1] + 1; + end + if (Auto_precharge[2] == 1'b1) begin + Count_precharge[2] = Count_precharge[2] + 1; + end + if (Auto_precharge[3] == 1'b1) begin + Count_precharge[3] = Count_precharge[3] + 1; + end + + // tMRD Counter + MRD_chk = MRD_chk + 1; + + // tWR Counter for Write + WR_counter[0] = WR_counter[0] + 1; + WR_counter[1] = WR_counter[1] + 1; + WR_counter[2] = WR_counter[2] + 1; + WR_counter[3] = WR_counter[3] + 1; + + // Auto Refresh + if (Aref_enable == 1'b1) begin + if (Debug) $display ("at time %t AREF : Auto Refresh", $time); + // Auto Refresh to Auto Refresh + if (($time - RC_chk < tRC)&&Debug) begin + $display ("at time %t ERROR: tRC violation during Auto Refresh", $time); + end + // Precharge to Auto Refresh + if (($time - RP_chk0 < tRP || $time - RP_chk1 < tRP || $time - RP_chk2 < tRP || $time - RP_chk3 < tRP)&&Debug) begin + $display ("at time %t ERROR: tRP violation during Auto Refresh", $time); + end + // Precharge to Refresh + if (Pc_b0 == 1'b0 || Pc_b1 == 1'b0 || Pc_b2 == 1'b0 || Pc_b3 == 1'b0) begin + $display ("at time %t ERROR: All banks must be Precharge before Auto Refresh", $time); + end + // Record Current tRC time + RC_chk = $time; + end + + // Load Mode Register + if (Mode_reg_enable == 1'b1) begin + // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode + if (Pc_b0 == 1'b1 && Pc_b1 == 1'b1 && Pc_b2 == 1'b1 && Pc_b3 == 1'b1) begin + Mode_reg = Addr; + if (Debug) begin + $display ("at time %t LMR : Load Mode Register", $time); + // CAS Latency + if (Addr[6 : 4] == 3'b010) + $display (" CAS Latency = 2"); + else if (Addr[6 : 4] == 3'b011) + $display (" CAS Latency = 3"); + else + $display (" CAS Latency = Reserved"); + // Burst Length + if (Addr[2 : 0] == 3'b000) + $display (" Burst Length = 1"); + else if (Addr[2 : 0] == 3'b001) + $display (" Burst Length = 2"); + else if (Addr[2 : 0] == 3'b010) + $display (" Burst Length = 4"); + else if (Addr[2 : 0] == 3'b011) + $display (" Burst Length = 8"); + else if (Addr[3 : 0] == 4'b0111) + $display (" Burst Length = Full"); + else + $display (" Burst Length = Reserved"); + // Burst Type + if (Addr[3] == 1'b0) + $display (" Burst Type = Sequential"); + else if (Addr[3] == 1'b1) + $display (" Burst Type = Interleaved"); + else + $display (" Burst Type = Reserved"); + // Write Burst Mode + if (Addr[9] == 1'b0) + $display (" Write Burst Mode = Programmed Burst Length"); + else if (Addr[9] == 1'b1) + $display (" Write Burst Mode = Single Location Access"); + else + $display (" Write Burst Mode = Reserved"); + end + end else begin + $display ("at time %t ERROR: all banks must be Precharge before Load Mode Register", $time); + end + // REF to LMR + if ($time - RC_chk < tRC) begin + $display ("at time %t ERROR: tRC violation during Load Mode Register", $time); + end + // LMR to LMR + if (MRD_chk < tMRD) begin + $display ("at time %t ERROR: tMRD violation during Load Mode Register", $time); + end + MRD_chk = 0; + end + + // Active Block (Latch Bank Address and Row Address) + if (Active_enable == 1'b1) begin + if (Ba == 2'b00 && Pc_b0 == 1'b1) begin + {Act_b0, Pc_b0} = 2'b10; + B0_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk0 = $time; + RAS_chk0 = $time; + if (Debug) $display ("at time %t ACT : Bank = 0 Row = %d", $time, Addr); + // Precharge to Activate Bank 0 + if ($time - RP_chk0 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 0", $time); + end + end else if (Ba == 2'b01 && Pc_b1 == 1'b1) begin + {Act_b1, Pc_b1} = 2'b10; + B1_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk1 = $time; + RAS_chk1 = $time; + if (Debug) $display ("at time %t ACT : Bank = 1 Row = %d", $time, Addr); + // Precharge to Activate Bank 1 + if ($time - RP_chk1 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 1", $time); + end + end else if (Ba == 2'b10 && Pc_b2 == 1'b1) begin + {Act_b2, Pc_b2} = 2'b10; + B2_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk2 = $time; + RAS_chk2 = $time; + if (Debug) $display ("at time %t ACT : Bank = 2 Row = %d", $time, Addr); + // Precharge to Activate Bank 2 + if ($time - RP_chk2 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 2", $time); + end + end else if (Ba == 2'b11 && Pc_b3 == 1'b1) begin + {Act_b3, Pc_b3} = 2'b10; + B3_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk3 = $time; + RAS_chk3 = $time; + if (Debug) $display ("at time %t ACT : Bank = 3 Row = %d", $time, Addr); + // Precharge to Activate Bank 3 + if ($time - RP_chk3 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 3", $time); + end + end else if (Ba == 2'b00 && Pc_b0 == 1'b0) begin + $display ("at time %t ERROR: Bank 0 is not Precharged.", $time); + end else if (Ba == 2'b01 && Pc_b1 == 1'b0) begin + $display ("at time %t ERROR: Bank 1 is not Precharged.", $time); + end else if (Ba == 2'b10 && Pc_b2 == 1'b0) begin + $display ("at time %t ERROR: Bank 2 is not Precharged.", $time); + end else if (Ba == 2'b11 && Pc_b3 == 1'b0) begin + $display ("at time %t ERROR: Bank 3 is not Precharged.", $time); + end + // Active Bank A to Active Bank B + if ((Previous_bank != Ba) && ($time - RRD_chk < tRRD)) begin + $display ("at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba); + end + // Load Mode Register to Active + if (MRD_chk < tMRD ) begin + $display ("at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba); + end + // Auto Refresh to Activate + if (($time - RC_chk < tRC)&&Debug) begin + $display ("at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba); + end + // Record variables for checking violation + RRD_chk = $time; + Previous_bank = Ba; + end + + // Precharge Block + if (Prech_enable == 1'b1) begin + if (Addr[10] == 1'b1) begin + {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b1111; + {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000; + RP_chk0 = $time; + RP_chk1 = $time; + RP_chk2 = $time; + RP_chk3 = $time; + if (Debug) $display ("at time %t PRE : Bank = ALL",$time); + // Activate to Precharge all banks + if (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) || + ($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin + $display ("at time %t ERROR: tRAS violation during Precharge all bank", $time); + end + // tWR violation check for write + if (($time - WR_chk[0] < tWRp) || ($time - WR_chk[1] < tWRp) || + ($time - WR_chk[2] < tWRp) || ($time - WR_chk[3] < tWRp)) begin + $display ("at time %t ERROR: tWR violation during Precharge all bank", $time); + end + end else if (Addr[10] == 1'b0) begin + if (Ba == 2'b00) begin + {Pc_b0, Act_b0} = 2'b10; + RP_chk0 = $time; + if (Debug) $display ("at time %t PRE : Bank = 0",$time); + // Activate to Precharge Bank 0 + if ($time - RAS_chk0 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 0", $time); + end + end else if (Ba == 2'b01) begin + {Pc_b1, Act_b1} = 2'b10; + RP_chk1 = $time; + if (Debug) $display ("at time %t PRE : Bank = 1",$time); + // Activate to Precharge Bank 1 + if ($time - RAS_chk1 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 1", $time); + end + end else if (Ba == 2'b10) begin + {Pc_b2, Act_b2} = 2'b10; + RP_chk2 = $time; + if (Debug) $display ("at time %t PRE : Bank = 2",$time); + // Activate to Precharge Bank 2 + if ($time - RAS_chk2 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 2", $time); + end + end else if (Ba == 2'b11) begin + {Pc_b3, Act_b3} = 2'b10; + RP_chk3 = $time; + if (Debug) $display ("at time %t PRE : Bank = 3",$time); + // Activate to Precharge Bank 3 + if ($time - RAS_chk3 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 3", $time); + end + end + // tWR violation check for write + if ($time - WR_chk[Ba] < tWRp) begin + $display ("at time %t ERROR: tWR violation during Precharge bank %d", $time, Ba); + end + end + // Terminate a Write Immediately (if same bank or all banks) + if (Data_in_enable == 1'b1 && (Bank == Ba || Addr[10] == 1'b1)) begin + Data_in_enable = 1'b0; + end + // Precharge Command Pipeline for Read + if (Cas_latency_3 == 1'b1) begin + Command[2] = `PRECH; + Bank_precharge[2] = Ba; + A10_precharge[2] = Addr[10]; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `PRECH; + Bank_precharge[1] = Ba; + A10_precharge[1] = Addr[10]; + end + end + + // Burst terminate + if (Burst_term == 1'b1) begin + // Terminate a Write Immediately + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + // Terminate a Read Depend on CAS Latency + if (Cas_latency_3 == 1'b1) begin + Command[2] = `BST; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `BST; + end + if (Debug) $display ("at time %t BST : Burst Terminate",$time); + end + + // Read, Write, Column Latch + if (Read_enable == 1'b1 || Write_enable == 1'b1) begin + // Check to see if bank is open (ACT) + if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || + (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin + $display("at time %t ERROR: Cannot Read or Write - Bank %d is not Activated", $time, Ba); + end + // Activate to Read or Write + if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 0", $time); + if ((Ba == 2'b01) && ($time - RCD_chk1 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 1", $time); + if ((Ba == 2'b10) && ($time - RCD_chk2 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 2", $time); + if ((Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 3", $time); + // Read Command + if (Read_enable == 1'b1) begin + // CAS Latency pipeline + if (Cas_latency_3 == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[2] = `READ_A; + end else begin + Command[2] = `READ; + end + Col_addr[2] = Addr; + Bank_addr[2] = Ba; + end else if (Cas_latency_2 == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[1] = `READ_A; + end else begin + Command[1] = `READ; + end + Col_addr[1] = Addr; + Bank_addr[1] = Ba; + end + + // Read interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Write Command + end else if (Write_enable == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[0] = `WRITE_A; + end else begin + Command[0] = `WRITE; + end + Col_addr[0] = Addr; + Bank_addr[0] = Ba; + + // Write interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Write interrupt Read (terminate Read immediately) + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + // Interrupting a Write with Autoprecharge + if (Auto_precharge[Bank] == 1'b1 && Write_precharge[Bank] == 1'b1) begin + RW_interrupt_write[Bank] = 1'b1; + if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, Bank); + end + + // Interrupting a Read with Autoprecharge + if (Auto_precharge[Bank] == 1'b1 && Read_precharge[Bank] == 1'b1) begin + RW_interrupt_read[Bank] = 1'b1; + if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, Bank); + end + + // Read or Write with Auto Precharge + if (Addr[10] == 1'b1) begin + Auto_precharge[Ba] = 1'b1; + Count_precharge[Ba] = 0; + if (Read_enable == 1'b1) begin + Read_precharge[Ba] = 1'b1; + end else if (Write_enable == 1'b1) begin + Write_precharge[Ba] = 1'b1; + end + end + end + + // Read with Auto Precharge Calculation + // The device start internal precharge: + // 1. CAS Latency - 1 cycles before last burst + // and 2. Meet minimum tRAS requirement + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 2 + ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 1 + (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) || + (RW_interrupt_read[0] == 1'b1)) begin // Case 3 + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + Auto_precharge[0] = 1'b0; + Read_precharge[0] = 1'b0; + RW_interrupt_read[0] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) || + (RW_interrupt_read[1] == 1'b1)) begin + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + Auto_precharge[1] = 1'b0; + Read_precharge[1] = 1'b0; + RW_interrupt_read[1] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) || + (RW_interrupt_read[2] == 1'b1)) begin + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + Auto_precharge[2] = 1'b0; + Read_precharge[2] = 1'b0; + RW_interrupt_read[2] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) || + (RW_interrupt_read[3] == 1'b1)) begin + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + Auto_precharge[3] = 1'b0; + Read_precharge[3] = 1'b0; + RW_interrupt_read[3] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + + // Internal Precharge or Bst + if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks + if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + end else if (Command[0] == `BST) begin // BST terminate a read to current bank + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + if (Data_out_enable == 1'b0) begin + Dq_reg <= #tOH {data_bits{1'bz}}; + end + + // Detect Read or Write command + if (Command[0] == `READ || Command[0] == `READ_A) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + if (Bank_addr[0] == 2'b00) begin + Row = B0_row_addr; + end else if (Bank_addr[0] == 2'b01) begin + Row = B1_row_addr; + end else if (Bank_addr[0] == 2'b10) begin + Row = B2_row_addr; + end else if (Bank_addr[0] == 2'b11) begin + Row = B3_row_addr; + end + Burst_counter = 0; + Data_in_enable = 1'b0; + Data_out_enable = 1'b1; + end else if (Command[0] == `WRITE || Command[0] == `WRITE_A) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + if (Bank_addr[0] == 2'b00) begin + Row = B0_row_addr; + end else if (Bank_addr[0] == 2'b01) begin + Row = B1_row_addr; + end else if (Bank_addr[0] == 2'b10) begin + Row = B2_row_addr; + end else if (Bank_addr[0] == 2'b11) begin + Row = B3_row_addr; + end + Burst_counter = 0; + Data_in_enable = 1'b1; + Data_out_enable = 1'b0; + end + + // DQ buffer (Driver/Receiver) + if (Data_in_enable == 1'b1) begin // Writing Data to Memory + // Array buffer + if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}]; + if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}]; + if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}]; + if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}]; + // Dqm operation + if (Dqm[0] == 1'b0) Dq_dqm [ 7 : 0] = Dq [ 7 : 0]; + if (Dqm[1] == 1'b0) Dq_dqm [15 : 8] = Dq [15 : 8]; + //if (Dqm[2] == 1'b0) Dq_dqm [23 : 16] = Dq [23 : 16]; + // if (Dqm[3] == 1'b0) Dq_dqm [31 : 24] = Dq [31 : 24]; + // Write to memory + if (Bank == 2'b00) Bank0 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b01) Bank1 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b10) Bank2 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b11) Bank3 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b11 && Row==10'h3 && Col[7:4]==4'h4) + $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + //$fdisplay(test_file,"bank:%h row:%h col:%h write:%h",Bank,Row,Col,Dq_dqm); + // Output result + if (Dqm == 4'b1111) begin + if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end else begin + if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_dqm, Dqm); + // Record tWR time and reset counter + WR_chk [Bank] = $time; + WR_counter [Bank] = 0; + end + // Advance burst counter subroutine + #tHZ Burst; + end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory + //$display("%h , %h, %h",Bank0,Row,Col); + // Array buffer + if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}]; + if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}]; + if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}]; + if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}]; + + // Dqm operation + if (Dqm_reg0[0] == 1'b1) Dq_dqm [ 7 : 0] = 8'bz; + if (Dqm_reg0[1] == 1'b1) Dq_dqm [15 : 8] = 8'bz; + if (Dqm_reg0[2] == 1'b1) Dq_dqm [23 : 16] = 8'bz; + if (Dqm_reg0[3] == 1'b1) Dq_dqm [31 : 24] = 8'bz; + // Display result + Dq_reg [data_bits - 1 : 0] = #tAC Dq_dqm [data_bits - 1 : 0]; + if (Dqm_reg0 == 4'b1111) begin + if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end else begin + if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_reg, Dqm_reg0); + end + // Advance burst counter subroutine + Burst; + end + end + + // Write with Auto Precharge Calculation + // The device start internal precharge: + // 1. tWR Clock after last burst + // and 2. Meet minimum tRAS requirement + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + always @ (WR_counter[0]) begin + if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 2 + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 1 + (Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) || + (RW_interrupt_write[0] == 1'b1 && WR_counter[0] >= 2)) begin // Case 3 (stop count when interrupt) + Auto_precharge[0] = 1'b0; + Write_precharge[0] = 1'b0; + RW_interrupt_write[0] = 1'b0; + #tWRa; // Wait for tWR + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + end + always @ (WR_counter[1]) begin + if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) || + (RW_interrupt_write[1] == 1'b1 && WR_counter[1] >= 2)) begin + Auto_precharge[1] = 1'b0; + Write_precharge[1] = 1'b0; + RW_interrupt_write[1] = 1'b0; + #tWRa; // Wait for tWR + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + end + always @ (WR_counter[2]) begin + if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) || + (RW_interrupt_write[2] == 1'b1 && WR_counter[2] >= 2)) begin + Auto_precharge[2] = 1'b0; + Write_precharge[2] = 1'b0; + RW_interrupt_write[2] = 1'b0; + #tWRa; // Wait for tWR + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + end + always @ (WR_counter[3]) begin + if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) || + (RW_interrupt_write[3] == 1'b1 && WR_counter[3] >= 2)) begin + Auto_precharge[3] = 1'b0; + Write_precharge[3] = 1'b0; + RW_interrupt_write[3] = 1'b0; + #tWRa; // Wait for tWR + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + end + + task Burst; + begin + // Advance Burst Counter + Burst_counter = Burst_counter + 1; + + // Burst Type + if (Mode_reg[3] == 1'b0) begin // Sequential Burst + Col_temp = Col + 1; + end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst + Col_temp[2] = Burst_counter[2] ^ Col_brst[2]; + Col_temp[1] = Burst_counter[1] ^ Col_brst[1]; + Col_temp[0] = Burst_counter[0] ^ Col_brst[0]; + end + + // Burst Length + if (Burst_length_2) begin // Burst Length = 2 + Col [0] = Col_temp [0]; + end else if (Burst_length_4) begin // Burst Length = 4 + Col [1 : 0] = Col_temp [1 : 0]; + end else if (Burst_length_8) begin // Burst Length = 8 + Col [2 : 0] = Col_temp [2 : 0]; + end else begin // Burst Length = FULL + Col = Col_temp; + end + + // Burst Read Single Write + if (Write_burst_mode == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Data Counter + if (Burst_length_1 == 1'b1) begin + if (Burst_counter >= 1) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_2 == 1'b1) begin + if (Burst_counter >= 2) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_4 == 1'b1) begin + if (Burst_counter >= 4) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_8 == 1'b1) begin + if (Burst_counter >= 8) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end + end + endtask + + //**********************SDRAMڵֱⲿļ*******************************// + +/* + integer sdram_data,ind; + + + always@(sdram_r) + begin + sdram_data=$fopen("sdram_data.txt"); + $display("Sdram dampout begin ",sdram_data); +// $fdisplay(sdram_data,"Bank0"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank0[ind]); +// $fdisplay(sdram_data,"Bank1"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank1[ind]); +// $fdisplay(sdram_data,"Bank2"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank2[ind]); +// $fdisplay(sdram_data,"Bank3"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank3[ind]); + + $fclose("sdram_data.txt"); + //->compare; + end +*/ + integer sdram_data,sdram_mem; + reg [23:0] aa,cc; + reg [18:0] bb,ee; + + always@(sdram_r) + begin + $display("Sdram dampout begin ",$realtime); + sdram_data=$fopen("sdram_data.txt"); + for(aa=0;aa<4*(mem_sizes+1);aa=aa+1) + begin + bb=aa[18:0]; + if(aa<=mem_sizes) + $fdisplay(sdram_data,"%0d %0h",aa,Bank0[bb]); + else if(aa<=2*mem_sizes+1) + $fdisplay(sdram_data,"%0d %0h",aa,Bank1[bb]); + else if(aa<=3*mem_sizes+2) + $fdisplay(sdram_data,"%0d %0h",aa,Bank2[bb]); + else + $fdisplay(sdram_data,"%0d %0h",aa,Bank3[bb]); + end + $fclose("sdram_data.txt"); + + sdram_mem=$fopen("sdram_mem.txt"); + for(cc=0;cc<4*(mem_sizes+1);cc=cc+1) + begin + ee=cc[18:0]; + if(cc<=mem_sizes) + $fdisplay(sdram_mem,"%0h",Bank0[ee]); + else if(cc<=2*mem_sizes+1) + $fdisplay(sdram_mem,"%0h",Bank1[ee]); + else if(cc<=3*mem_sizes+2) + $fdisplay(sdram_mem,"%0h",Bank2[ee]); + else + $fdisplay(sdram_mem,"%0h",Bank3[ee]); + end + $fclose("sdram_mem.txt"); + + end + + + +// // Timing Parameters for -75 (PC133) and CAS Latency = 2 +// specify +// specparam +//// tAH = 0.8, // Addr, Ba Hold Time +//// tAS = 1.5, // Addr, Ba Setup Time +//// tCH = 2.5, // Clock High-Level Width +//// tCL = 2.5, // Clock Low-Level Width +////// tCK = 10.0, // Clock Cycle Time 100mhz +////// tCK = 7.5, // Clock Cycle Time 133mhz +//// tCK = 7, // Clock Cycle Time 143mhz +//// tDH = 0.8, // Data-in Hold Time +//// tDS = 1.5, // Data-in Setup Time +//// tCKH = 0.8, // CKE Hold Time +//// tCKS = 1.5, // CKE Setup Time +//// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time +//// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time +// tAH = 1, // Addr, Ba Hold Time +// tAS = 1.5, // Addr, Ba Setup Time +// tCH = 1, // Clock High-Level Width +// tCL = 3, // Clock Low-Level Width +//// tCK = 10.0, // Clock Cycle Time 100mhz +//// tCK = 7.5, // Clock Cycle Time 133mhz +// tCK = 7, // Clock Cycle Time 143mhz +// tDH = 1, // Data-in Hold Time +// tDS = 2, // Data-in Setup Time +// tCKH = 1, // CKE Hold Time +// tCKS = 2, // CKE Setup Time +// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time +// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time +// $width (posedge Clk, tCH); +// $width (negedge Clk, tCL); +// $period (negedge Clk, tCK); +// $period (posedge Clk, tCK); +// $setuphold(posedge Clk, Cke, tCKS, tCKH); +// $setuphold(posedge Clk, Cs_n, tCMS, tCMH); +// $setuphold(posedge Clk, Cas_n, tCMS, tCMH); +// $setuphold(posedge Clk, Ras_n, tCMS, tCMH); +// $setuphold(posedge Clk, We_n, tCMS, tCMH); +// $setuphold(posedge Clk, Addr, tAS, tAH); +// $setuphold(posedge Clk, Ba, tAS, tAH); +// $setuphold(posedge Clk, Dqm, tCMS, tCMH); +// $setuphold(posedge Dq_chk, Dq, tDS, tDH); +// endspecify + +endmodule + diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_a_ref/sdram_model_plus.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_a_ref/sdram_model_plus.v new file mode 100644 index 0000000..4e51287 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_a_ref/sdram_model_plus.v @@ -0,0 +1,1131 @@ +/*************************************************************************************** +ߣ +2003-08-27 V0.1 + + ڴģ鵹չܣⲿҪ¼sdram_r ,SDRAMݽᰴBank ˳damp out ļ + sdram_data.txt +*/ +//2004-03-04 ˿ ޸ԭнBANKתTXTļĸʽ +//2004-03-16 ˿ ޸SDRAM ijʼ +//2004/04/06 ˿ SDRAMIJַʽʾԱMODELSIM +//2004/04/19 ˿ ޸IJ parameter tAC = 8; +//2010/09/17 ޸sdramĴСλdqm; +/**************************************************************************************** +* +* File Name: sdram_model.V +* Version: 0.0f +* Date: July 8th, 1999 +* Model: BUS Functional +* Simulator: Model Technology (PC version 5.2e PE) +* +* Dependencies: None +* +* Author: Son P. Huynh +* Email: sphuynh@micron.com +* Phone: (208) 368-3825 +* Company: Micron Technology, Inc. +* Model: sdram_model (1Meg x 16 x 4 Banks) +* +* Description: 64Mb SDRAM Verilog model +* +* Limitation: - Doesn't check for 4096 cycle refresh +* +* Note: - Set simulator resolution to "ps" accuracy +* - Set Debug = 0 to disable $display messages +* +* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +* +* Copyright ?1998 Micron Semiconductor Products, Inc. +* All rights researved +* +* Rev Author Phone Date Changes +* ---- ---------------------------- ---------- --------------------------------------- +* 0.0f Son Huynh 208-368-3825 07/08/1999 - Fix tWR = 1 Clk + 7.5 ns (Auto) +* Micron Technology Inc. - Fix tWR = 15 ns (Manual) +* - Fix tRP (Autoprecharge to AutoRefresh) +* +* 0.0a Son Huynh 208-368-3825 05/13/1998 - First Release (from 64Mb rev 0.0e) +* Micron Technology Inc. +****************************************************************************************/ + +`timescale 1ns / 100ps + +module sdram_model_plus (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm,Debug); + + parameter addr_bits = 11; + parameter data_bits = 32; + parameter col_bits = 8; + parameter mem_sizes = 1048576*2-1;//1 Meg + + inout [data_bits - 1 : 0] Dq; + input [addr_bits - 1 : 0] Addr; + input [1 : 0] Ba; + input Clk; + input Cke; + input Cs_n; + input Ras_n; + input Cas_n; + input We_n; + input [3 : 0] Dqm; //ߵ͸8bit + //added by xzli + input Debug; + + reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];//洢 + reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes]; + + reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline + reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline + reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline + reg [3 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline + reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr; + + reg [addr_bits - 1 : 0] Mode_reg; + reg [data_bits - 1 : 0] Dq_reg, Dq_dqm; + reg [col_bits - 1 : 0] Col_temp, Burst_counter; + + reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate + reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge + + reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command + reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks) + reg Auto_precharge [0 : 3]; // RW AutoPrecharge (Bank) + reg Read_precharge [0 : 3]; // R AutoPrecharge + reg Write_precharge [0 : 3]; // W AutoPrecharge + integer Count_precharge [0 : 3]; // RW AutoPrecharge (Counter) + reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge + reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge + + reg Data_in_enable; + reg Data_out_enable; + + reg [1 : 0] Bank, Previous_bank; + reg [addr_bits - 1 : 0] Row; + reg [col_bits - 1 : 0] Col, Col_brst; + + // Internal system clock + reg CkeZ, Sys_clk; + + reg [21:0] dd; + + // Commands Decode + wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n; + wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n; + wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n; + wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n; + wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n; + wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n; + wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n; + + // Burst Length Decode + wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0]; + wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; + + // CAS Latency Decode + wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4]; + wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4]; + + // Write Burst Mode + wire Write_burst_mode = Mode_reg[9]; + + wire Debug; // Debug messages : 1 = On; 0 = Off + wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ + + reg [31:0] mem_d; + + event sdram_r,sdram_w,compare; + + + + + assign Dq = Dq_reg; // DQ buffer + + // Commands Operation + `define ACT 0 + `define NOP 1 + `define READ 2 + `define READ_A 3 + `define WRITE 4 + `define WRITE_A 5 + `define PRECH 6 + `define A_REF 7 + `define BST 8 + `define LMR 9 + +// // Timing Parameters for -75 (PC133) and CAS Latency = 2 +// parameter tAC = 8; //test 6.5 +// parameter tHZ = 7.0; +// parameter tOH = 2.7; +// parameter tMRD = 2.0; // 2 Clk Cycles +// parameter tRAS = 44.0; +// parameter tRC = 66.0; +// parameter tRCD = 20.0; +// parameter tRP = 20.0; +// parameter tRRD = 15.0; +// parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) +// parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns) + + // Timing Parameters for -7 (PC143) and CAS Latency = 3 + parameter tAC = 6.5; //test 6.5 + parameter tHZ = 5.5; + parameter tOH = 2; + parameter tMRD = 2.0; // 2 Clk Cycles + parameter tRAS = 48.0; + parameter tRC = 70.0; + parameter tRCD = 20.0; + parameter tRP = 20.0; + parameter tRRD = 14.0; + parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) + parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns) + + // Timing Check variable + integer MRD_chk; + integer WR_counter [0 : 3]; + time WR_chk [0 : 3]; + time RC_chk, RRD_chk; + time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3; + time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; + time RP_chk0, RP_chk1, RP_chk2, RP_chk3; + + integer test_file; + + //*****display the command of the sdram************************************** + + parameter Mode_Reg_Set =4'b0000; + parameter Auto_Refresh =4'b0001; + parameter Row_Active =4'b0011; + parameter Pre_Charge =4'b0010; + parameter PreCharge_All =4'b0010; + parameter Write =4'b0100; + parameter Write_Pre =4'b0100; + parameter Read =4'b0101; + parameter Read_Pre =4'b0101; + parameter Burst_Stop =4'b0110; + parameter Nop =4'b0111; + parameter Dsel =4'b1111; + + wire [3:0] sdram_control; + reg cke_temp; + reg [8*13:1] sdram_command; + + always@(posedge Clk) + cke_temp<=Cke; + + assign sdram_control={Cs_n,Ras_n,Cas_n,We_n}; + + always@(sdram_control or cke_temp) + begin + case(sdram_control) + Mode_Reg_Set: sdram_command<="Mode_Reg_Set"; + Auto_Refresh: sdram_command<="Auto_Refresh"; + Row_Active: sdram_command<="Row_Active"; + Pre_Charge: sdram_command<="Pre_Charge"; + Burst_Stop: sdram_command<="Burst_Stop"; + Dsel: sdram_command<="Dsel"; + + Write: if(cke_temp==1) + sdram_command<="Write"; + else + sdram_command<="Write_suspend"; + + Read: if(cke_temp==1) + sdram_command<="Read"; + else + sdram_command<="Read_suspend"; + + Nop: if(cke_temp==1) + sdram_command<="Nop"; + else + sdram_command<="Self_refresh"; + + default: sdram_command<="Power_down"; + endcase + end + + //***************************************************** + + initial + begin + //test_file=$fopen("test_file.txt"); + end + + initial + begin + Dq_reg = {data_bits{1'bz}}; + {Data_in_enable, Data_out_enable} = 0; + {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000; + {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000; + {WR_chk[0], WR_chk[1], WR_chk[2], WR_chk[3]} = 0; + {WR_counter[0], WR_counter[1], WR_counter[2], WR_counter[3]} = 0; + {RW_interrupt_read[0], RW_interrupt_read[1], RW_interrupt_read[2], RW_interrupt_read[3]} = 0; + {RW_interrupt_write[0], RW_interrupt_write[1], RW_interrupt_write[2], RW_interrupt_write[3]} = 0; + {MRD_chk, RC_chk, RRD_chk} = 0; + {RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0; + {RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0; + {RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0; + $timeformat (-9, 0, " ns", 12); + //$readmemh("bank0.txt", Bank0); + //$readmemh("bank1.txt", Bank1); + //$readmemh("bank2.txt", Bank2); + //$readmemh("bank3.txt", Bank3); +/* + for(dd=0;dd<=mem_sizes;dd=dd+1) + begin + Bank0[dd]=dd[data_bits - 1 : 0]; + Bank1[dd]=dd[data_bits - 1 : 0]+1; + Bank2[dd]=dd[data_bits - 1 : 0]+2; + Bank3[dd]=dd[data_bits - 1 : 0]+3; + end +*/ + initial_sdram(0); + end + + task initial_sdram; + + input data_sign; + reg [3:0] data_sign; + + for(dd=0;dd<=mem_sizes;dd=dd+1) + begin + mem_d = {data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign}; + if(data_bits==16) + begin + Bank0[dd]=mem_d[15:0]; + Bank1[dd]=mem_d[15:0]; + Bank2[dd]=mem_d[15:0]; + Bank3[dd]=mem_d[15:0]; + end + else if(data_bits==32) + begin + Bank0[dd]=mem_d[31:0]; + Bank1[dd]=mem_d[31:0]; + Bank2[dd]=mem_d[31:0]; + Bank3[dd]=mem_d[31:0]; + end + end + + endtask + + // System clock generator + always + begin + @(posedge Clk) + begin + Sys_clk = CkeZ; + CkeZ = Cke; + end + @(negedge Clk) + begin + Sys_clk = 1'b0; + end + end + + always @ (posedge Sys_clk) begin + // Internal Commamd Pipelined + Command[0] = Command[1]; + Command[1] = Command[2]; + Command[2] = Command[3]; + Command[3] = `NOP; + + Col_addr[0] = Col_addr[1]; + Col_addr[1] = Col_addr[2]; + Col_addr[2] = Col_addr[3]; + Col_addr[3] = {col_bits{1'b0}}; + + Bank_addr[0] = Bank_addr[1]; + Bank_addr[1] = Bank_addr[2]; + Bank_addr[2] = Bank_addr[3]; + Bank_addr[3] = 2'b0; + + Bank_precharge[0] = Bank_precharge[1]; + Bank_precharge[1] = Bank_precharge[2]; + Bank_precharge[2] = Bank_precharge[3]; + Bank_precharge[3] = 2'b0; + + A10_precharge[0] = A10_precharge[1]; + A10_precharge[1] = A10_precharge[2]; + A10_precharge[2] = A10_precharge[3]; + A10_precharge[3] = 1'b0; + + // Dqm pipeline for Read + Dqm_reg0 = Dqm_reg1; + Dqm_reg1 = Dqm; + + // Read or Write with Auto Precharge Counter + if (Auto_precharge[0] == 1'b1) begin + Count_precharge[0] = Count_precharge[0] + 1; + end + if (Auto_precharge[1] == 1'b1) begin + Count_precharge[1] = Count_precharge[1] + 1; + end + if (Auto_precharge[2] == 1'b1) begin + Count_precharge[2] = Count_precharge[2] + 1; + end + if (Auto_precharge[3] == 1'b1) begin + Count_precharge[3] = Count_precharge[3] + 1; + end + + // tMRD Counter + MRD_chk = MRD_chk + 1; + + // tWR Counter for Write + WR_counter[0] = WR_counter[0] + 1; + WR_counter[1] = WR_counter[1] + 1; + WR_counter[2] = WR_counter[2] + 1; + WR_counter[3] = WR_counter[3] + 1; + + // Auto Refresh + if (Aref_enable == 1'b1) begin + if (Debug) $display ("at time %t AREF : Auto Refresh", $time); + // Auto Refresh to Auto Refresh + if (($time - RC_chk < tRC)&&Debug) begin + $display ("at time %t ERROR: tRC violation during Auto Refresh", $time); + end + // Precharge to Auto Refresh + if (($time - RP_chk0 < tRP || $time - RP_chk1 < tRP || $time - RP_chk2 < tRP || $time - RP_chk3 < tRP)&&Debug) begin + $display ("at time %t ERROR: tRP violation during Auto Refresh", $time); + end + // Precharge to Refresh + if (Pc_b0 == 1'b0 || Pc_b1 == 1'b0 || Pc_b2 == 1'b0 || Pc_b3 == 1'b0) begin + $display ("at time %t ERROR: All banks must be Precharge before Auto Refresh", $time); + end + // Record Current tRC time + RC_chk = $time; + end + + // Load Mode Register + if (Mode_reg_enable == 1'b1) begin + // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode + if (Pc_b0 == 1'b1 && Pc_b1 == 1'b1 && Pc_b2 == 1'b1 && Pc_b3 == 1'b1) begin + Mode_reg = Addr; + if (Debug) begin + $display ("at time %t LMR : Load Mode Register", $time); + // CAS Latency + if (Addr[6 : 4] == 3'b010) + $display (" CAS Latency = 2"); + else if (Addr[6 : 4] == 3'b011) + $display (" CAS Latency = 3"); + else + $display (" CAS Latency = Reserved"); + // Burst Length + if (Addr[2 : 0] == 3'b000) + $display (" Burst Length = 1"); + else if (Addr[2 : 0] == 3'b001) + $display (" Burst Length = 2"); + else if (Addr[2 : 0] == 3'b010) + $display (" Burst Length = 4"); + else if (Addr[2 : 0] == 3'b011) + $display (" Burst Length = 8"); + else if (Addr[3 : 0] == 4'b0111) + $display (" Burst Length = Full"); + else + $display (" Burst Length = Reserved"); + // Burst Type + if (Addr[3] == 1'b0) + $display (" Burst Type = Sequential"); + else if (Addr[3] == 1'b1) + $display (" Burst Type = Interleaved"); + else + $display (" Burst Type = Reserved"); + // Write Burst Mode + if (Addr[9] == 1'b0) + $display (" Write Burst Mode = Programmed Burst Length"); + else if (Addr[9] == 1'b1) + $display (" Write Burst Mode = Single Location Access"); + else + $display (" Write Burst Mode = Reserved"); + end + end else begin + $display ("at time %t ERROR: all banks must be Precharge before Load Mode Register", $time); + end + // REF to LMR + if ($time - RC_chk < tRC) begin + $display ("at time %t ERROR: tRC violation during Load Mode Register", $time); + end + // LMR to LMR + if (MRD_chk < tMRD) begin + $display ("at time %t ERROR: tMRD violation during Load Mode Register", $time); + end + MRD_chk = 0; + end + + // Active Block (Latch Bank Address and Row Address) + if (Active_enable == 1'b1) begin + if (Ba == 2'b00 && Pc_b0 == 1'b1) begin + {Act_b0, Pc_b0} = 2'b10; + B0_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk0 = $time; + RAS_chk0 = $time; + if (Debug) $display ("at time %t ACT : Bank = 0 Row = %d", $time, Addr); + // Precharge to Activate Bank 0 + if ($time - RP_chk0 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 0", $time); + end + end else if (Ba == 2'b01 && Pc_b1 == 1'b1) begin + {Act_b1, Pc_b1} = 2'b10; + B1_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk1 = $time; + RAS_chk1 = $time; + if (Debug) $display ("at time %t ACT : Bank = 1 Row = %d", $time, Addr); + // Precharge to Activate Bank 1 + if ($time - RP_chk1 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 1", $time); + end + end else if (Ba == 2'b10 && Pc_b2 == 1'b1) begin + {Act_b2, Pc_b2} = 2'b10; + B2_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk2 = $time; + RAS_chk2 = $time; + if (Debug) $display ("at time %t ACT : Bank = 2 Row = %d", $time, Addr); + // Precharge to Activate Bank 2 + if ($time - RP_chk2 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 2", $time); + end + end else if (Ba == 2'b11 && Pc_b3 == 1'b1) begin + {Act_b3, Pc_b3} = 2'b10; + B3_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk3 = $time; + RAS_chk3 = $time; + if (Debug) $display ("at time %t ACT : Bank = 3 Row = %d", $time, Addr); + // Precharge to Activate Bank 3 + if ($time - RP_chk3 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 3", $time); + end + end else if (Ba == 2'b00 && Pc_b0 == 1'b0) begin + $display ("at time %t ERROR: Bank 0 is not Precharged.", $time); + end else if (Ba == 2'b01 && Pc_b1 == 1'b0) begin + $display ("at time %t ERROR: Bank 1 is not Precharged.", $time); + end else if (Ba == 2'b10 && Pc_b2 == 1'b0) begin + $display ("at time %t ERROR: Bank 2 is not Precharged.", $time); + end else if (Ba == 2'b11 && Pc_b3 == 1'b0) begin + $display ("at time %t ERROR: Bank 3 is not Precharged.", $time); + end + // Active Bank A to Active Bank B + if ((Previous_bank != Ba) && ($time - RRD_chk < tRRD)) begin + $display ("at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba); + end + // Load Mode Register to Active + if (MRD_chk < tMRD ) begin + $display ("at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba); + end + // Auto Refresh to Activate + if (($time - RC_chk < tRC)&&Debug) begin + $display ("at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba); + end + // Record variables for checking violation + RRD_chk = $time; + Previous_bank = Ba; + end + + // Precharge Block + if (Prech_enable == 1'b1) begin + if (Addr[10] == 1'b1) begin + {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b1111; + {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000; + RP_chk0 = $time; + RP_chk1 = $time; + RP_chk2 = $time; + RP_chk3 = $time; + if (Debug) $display ("at time %t PRE : Bank = ALL",$time); + // Activate to Precharge all banks + if (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) || + ($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin + $display ("at time %t ERROR: tRAS violation during Precharge all bank", $time); + end + // tWR violation check for write + if (($time - WR_chk[0] < tWRp) || ($time - WR_chk[1] < tWRp) || + ($time - WR_chk[2] < tWRp) || ($time - WR_chk[3] < tWRp)) begin + $display ("at time %t ERROR: tWR violation during Precharge all bank", $time); + end + end else if (Addr[10] == 1'b0) begin + if (Ba == 2'b00) begin + {Pc_b0, Act_b0} = 2'b10; + RP_chk0 = $time; + if (Debug) $display ("at time %t PRE : Bank = 0",$time); + // Activate to Precharge Bank 0 + if ($time - RAS_chk0 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 0", $time); + end + end else if (Ba == 2'b01) begin + {Pc_b1, Act_b1} = 2'b10; + RP_chk1 = $time; + if (Debug) $display ("at time %t PRE : Bank = 1",$time); + // Activate to Precharge Bank 1 + if ($time - RAS_chk1 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 1", $time); + end + end else if (Ba == 2'b10) begin + {Pc_b2, Act_b2} = 2'b10; + RP_chk2 = $time; + if (Debug) $display ("at time %t PRE : Bank = 2",$time); + // Activate to Precharge Bank 2 + if ($time - RAS_chk2 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 2", $time); + end + end else if (Ba == 2'b11) begin + {Pc_b3, Act_b3} = 2'b10; + RP_chk3 = $time; + if (Debug) $display ("at time %t PRE : Bank = 3",$time); + // Activate to Precharge Bank 3 + if ($time - RAS_chk3 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 3", $time); + end + end + // tWR violation check for write + if ($time - WR_chk[Ba] < tWRp) begin + $display ("at time %t ERROR: tWR violation during Precharge bank %d", $time, Ba); + end + end + // Terminate a Write Immediately (if same bank or all banks) + if (Data_in_enable == 1'b1 && (Bank == Ba || Addr[10] == 1'b1)) begin + Data_in_enable = 1'b0; + end + // Precharge Command Pipeline for Read + if (Cas_latency_3 == 1'b1) begin + Command[2] = `PRECH; + Bank_precharge[2] = Ba; + A10_precharge[2] = Addr[10]; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `PRECH; + Bank_precharge[1] = Ba; + A10_precharge[1] = Addr[10]; + end + end + + // Burst terminate + if (Burst_term == 1'b1) begin + // Terminate a Write Immediately + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + // Terminate a Read Depend on CAS Latency + if (Cas_latency_3 == 1'b1) begin + Command[2] = `BST; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `BST; + end + if (Debug) $display ("at time %t BST : Burst Terminate",$time); + end + + // Read, Write, Column Latch + if (Read_enable == 1'b1 || Write_enable == 1'b1) begin + // Check to see if bank is open (ACT) + if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || + (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin + $display("at time %t ERROR: Cannot Read or Write - Bank %d is not Activated", $time, Ba); + end + // Activate to Read or Write + if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 0", $time); + if ((Ba == 2'b01) && ($time - RCD_chk1 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 1", $time); + if ((Ba == 2'b10) && ($time - RCD_chk2 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 2", $time); + if ((Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 3", $time); + // Read Command + if (Read_enable == 1'b1) begin + // CAS Latency pipeline + if (Cas_latency_3 == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[2] = `READ_A; + end else begin + Command[2] = `READ; + end + Col_addr[2] = Addr; + Bank_addr[2] = Ba; + end else if (Cas_latency_2 == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[1] = `READ_A; + end else begin + Command[1] = `READ; + end + Col_addr[1] = Addr; + Bank_addr[1] = Ba; + end + + // Read interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Write Command + end else if (Write_enable == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[0] = `WRITE_A; + end else begin + Command[0] = `WRITE; + end + Col_addr[0] = Addr; + Bank_addr[0] = Ba; + + // Write interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Write interrupt Read (terminate Read immediately) + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + // Interrupting a Write with Autoprecharge + if (Auto_precharge[Bank] == 1'b1 && Write_precharge[Bank] == 1'b1) begin + RW_interrupt_write[Bank] = 1'b1; + if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, Bank); + end + + // Interrupting a Read with Autoprecharge + if (Auto_precharge[Bank] == 1'b1 && Read_precharge[Bank] == 1'b1) begin + RW_interrupt_read[Bank] = 1'b1; + if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, Bank); + end + + // Read or Write with Auto Precharge + if (Addr[10] == 1'b1) begin + Auto_precharge[Ba] = 1'b1; + Count_precharge[Ba] = 0; + if (Read_enable == 1'b1) begin + Read_precharge[Ba] = 1'b1; + end else if (Write_enable == 1'b1) begin + Write_precharge[Ba] = 1'b1; + end + end + end + + // Read with Auto Precharge Calculation + // The device start internal precharge: + // 1. CAS Latency - 1 cycles before last burst + // and 2. Meet minimum tRAS requirement + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 2 + ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 1 + (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) || + (RW_interrupt_read[0] == 1'b1)) begin // Case 3 + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + Auto_precharge[0] = 1'b0; + Read_precharge[0] = 1'b0; + RW_interrupt_read[0] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) || + (RW_interrupt_read[1] == 1'b1)) begin + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + Auto_precharge[1] = 1'b0; + Read_precharge[1] = 1'b0; + RW_interrupt_read[1] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) || + (RW_interrupt_read[2] == 1'b1)) begin + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + Auto_precharge[2] = 1'b0; + Read_precharge[2] = 1'b0; + RW_interrupt_read[2] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) || + (RW_interrupt_read[3] == 1'b1)) begin + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + Auto_precharge[3] = 1'b0; + Read_precharge[3] = 1'b0; + RW_interrupt_read[3] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + + // Internal Precharge or Bst + if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks + if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + end else if (Command[0] == `BST) begin // BST terminate a read to current bank + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + if (Data_out_enable == 1'b0) begin + Dq_reg <= #tOH {data_bits{1'bz}}; + end + + // Detect Read or Write command + if (Command[0] == `READ || Command[0] == `READ_A) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + if (Bank_addr[0] == 2'b00) begin + Row = B0_row_addr; + end else if (Bank_addr[0] == 2'b01) begin + Row = B1_row_addr; + end else if (Bank_addr[0] == 2'b10) begin + Row = B2_row_addr; + end else if (Bank_addr[0] == 2'b11) begin + Row = B3_row_addr; + end + Burst_counter = 0; + Data_in_enable = 1'b0; + Data_out_enable = 1'b1; + end else if (Command[0] == `WRITE || Command[0] == `WRITE_A) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + if (Bank_addr[0] == 2'b00) begin + Row = B0_row_addr; + end else if (Bank_addr[0] == 2'b01) begin + Row = B1_row_addr; + end else if (Bank_addr[0] == 2'b10) begin + Row = B2_row_addr; + end else if (Bank_addr[0] == 2'b11) begin + Row = B3_row_addr; + end + Burst_counter = 0; + Data_in_enable = 1'b1; + Data_out_enable = 1'b0; + end + + // DQ buffer (Driver/Receiver) + if (Data_in_enable == 1'b1) begin // Writing Data to Memory + // Array buffer + if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}]; + if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}]; + if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}]; + if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}]; + // Dqm operation + if (Dqm[0] == 1'b0) Dq_dqm [ 7 : 0] = Dq [ 7 : 0]; + if (Dqm[1] == 1'b0) Dq_dqm [15 : 8] = Dq [15 : 8]; + //if (Dqm[2] == 1'b0) Dq_dqm [23 : 16] = Dq [23 : 16]; + // if (Dqm[3] == 1'b0) Dq_dqm [31 : 24] = Dq [31 : 24]; + // Write to memory + if (Bank == 2'b00) Bank0 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b01) Bank1 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b10) Bank2 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b11) Bank3 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b11 && Row==10'h3 && Col[7:4]==4'h4) + $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + //$fdisplay(test_file,"bank:%h row:%h col:%h write:%h",Bank,Row,Col,Dq_dqm); + // Output result + if (Dqm == 4'b1111) begin + if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end else begin + if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_dqm, Dqm); + // Record tWR time and reset counter + WR_chk [Bank] = $time; + WR_counter [Bank] = 0; + end + // Advance burst counter subroutine + #tHZ Burst; + end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory + //$display("%h , %h, %h",Bank0,Row,Col); + // Array buffer + if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}]; + if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}]; + if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}]; + if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}]; + + // Dqm operation + if (Dqm_reg0[0] == 1'b1) Dq_dqm [ 7 : 0] = 8'bz; + if (Dqm_reg0[1] == 1'b1) Dq_dqm [15 : 8] = 8'bz; + if (Dqm_reg0[2] == 1'b1) Dq_dqm [23 : 16] = 8'bz; + if (Dqm_reg0[3] == 1'b1) Dq_dqm [31 : 24] = 8'bz; + // Display result + Dq_reg [data_bits - 1 : 0] = #tAC Dq_dqm [data_bits - 1 : 0]; + if (Dqm_reg0 == 4'b1111) begin + if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end else begin + if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_reg, Dqm_reg0); + end + // Advance burst counter subroutine + Burst; + end + end + + // Write with Auto Precharge Calculation + // The device start internal precharge: + // 1. tWR Clock after last burst + // and 2. Meet minimum tRAS requirement + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + always @ (WR_counter[0]) begin + if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 2 + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 1 + (Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) || + (RW_interrupt_write[0] == 1'b1 && WR_counter[0] >= 2)) begin // Case 3 (stop count when interrupt) + Auto_precharge[0] = 1'b0; + Write_precharge[0] = 1'b0; + RW_interrupt_write[0] = 1'b0; + #tWRa; // Wait for tWR + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + end + always @ (WR_counter[1]) begin + if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) || + (RW_interrupt_write[1] == 1'b1 && WR_counter[1] >= 2)) begin + Auto_precharge[1] = 1'b0; + Write_precharge[1] = 1'b0; + RW_interrupt_write[1] = 1'b0; + #tWRa; // Wait for tWR + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + end + always @ (WR_counter[2]) begin + if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) || + (RW_interrupt_write[2] == 1'b1 && WR_counter[2] >= 2)) begin + Auto_precharge[2] = 1'b0; + Write_precharge[2] = 1'b0; + RW_interrupt_write[2] = 1'b0; + #tWRa; // Wait for tWR + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + end + always @ (WR_counter[3]) begin + if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) || + (RW_interrupt_write[3] == 1'b1 && WR_counter[3] >= 2)) begin + Auto_precharge[3] = 1'b0; + Write_precharge[3] = 1'b0; + RW_interrupt_write[3] = 1'b0; + #tWRa; // Wait for tWR + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + end + + task Burst; + begin + // Advance Burst Counter + Burst_counter = Burst_counter + 1; + + // Burst Type + if (Mode_reg[3] == 1'b0) begin // Sequential Burst + Col_temp = Col + 1; + end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst + Col_temp[2] = Burst_counter[2] ^ Col_brst[2]; + Col_temp[1] = Burst_counter[1] ^ Col_brst[1]; + Col_temp[0] = Burst_counter[0] ^ Col_brst[0]; + end + + // Burst Length + if (Burst_length_2) begin // Burst Length = 2 + Col [0] = Col_temp [0]; + end else if (Burst_length_4) begin // Burst Length = 4 + Col [1 : 0] = Col_temp [1 : 0]; + end else if (Burst_length_8) begin // Burst Length = 8 + Col [2 : 0] = Col_temp [2 : 0]; + end else begin // Burst Length = FULL + Col = Col_temp; + end + + // Burst Read Single Write + if (Write_burst_mode == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Data Counter + if (Burst_length_1 == 1'b1) begin + if (Burst_counter >= 1) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_2 == 1'b1) begin + if (Burst_counter >= 2) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_4 == 1'b1) begin + if (Burst_counter >= 4) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_8 == 1'b1) begin + if (Burst_counter >= 8) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end + end + endtask + + //**********************SDRAMڵֱⲿļ*******************************// + +/* + integer sdram_data,ind; + + + always@(sdram_r) + begin + sdram_data=$fopen("sdram_data.txt"); + $display("Sdram dampout begin ",sdram_data); +// $fdisplay(sdram_data,"Bank0"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank0[ind]); +// $fdisplay(sdram_data,"Bank1"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank1[ind]); +// $fdisplay(sdram_data,"Bank2"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank2[ind]); +// $fdisplay(sdram_data,"Bank3"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank3[ind]); + + $fclose("sdram_data.txt"); + //->compare; + end +*/ + integer sdram_data,sdram_mem; + reg [23:0] aa,cc; + reg [18:0] bb,ee; + + always@(sdram_r) + begin + $display("Sdram dampout begin ",$realtime); + sdram_data=$fopen("sdram_data.txt"); + for(aa=0;aa<4*(mem_sizes+1);aa=aa+1) + begin + bb=aa[18:0]; + if(aa<=mem_sizes) + $fdisplay(sdram_data,"%0d %0h",aa,Bank0[bb]); + else if(aa<=2*mem_sizes+1) + $fdisplay(sdram_data,"%0d %0h",aa,Bank1[bb]); + else if(aa<=3*mem_sizes+2) + $fdisplay(sdram_data,"%0d %0h",aa,Bank2[bb]); + else + $fdisplay(sdram_data,"%0d %0h",aa,Bank3[bb]); + end + $fclose("sdram_data.txt"); + + sdram_mem=$fopen("sdram_mem.txt"); + for(cc=0;cc<4*(mem_sizes+1);cc=cc+1) + begin + ee=cc[18:0]; + if(cc<=mem_sizes) + $fdisplay(sdram_mem,"%0h",Bank0[ee]); + else if(cc<=2*mem_sizes+1) + $fdisplay(sdram_mem,"%0h",Bank1[ee]); + else if(cc<=3*mem_sizes+2) + $fdisplay(sdram_mem,"%0h",Bank2[ee]); + else + $fdisplay(sdram_mem,"%0h",Bank3[ee]); + end + $fclose("sdram_mem.txt"); + + end + + + +// // Timing Parameters for -75 (PC133) and CAS Latency = 2 +// specify +// specparam +//// tAH = 0.8, // Addr, Ba Hold Time +//// tAS = 1.5, // Addr, Ba Setup Time +//// tCH = 2.5, // Clock High-Level Width +//// tCL = 2.5, // Clock Low-Level Width +////// tCK = 10.0, // Clock Cycle Time 100mhz +////// tCK = 7.5, // Clock Cycle Time 133mhz +//// tCK = 7, // Clock Cycle Time 143mhz +//// tDH = 0.8, // Data-in Hold Time +//// tDS = 1.5, // Data-in Setup Time +//// tCKH = 0.8, // CKE Hold Time +//// tCKS = 1.5, // CKE Setup Time +//// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time +//// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time +// tAH = 1, // Addr, Ba Hold Time +// tAS = 1.5, // Addr, Ba Setup Time +// tCH = 1, // Clock High-Level Width +// tCL = 3, // Clock Low-Level Width +//// tCK = 10.0, // Clock Cycle Time 100mhz +//// tCK = 7.5, // Clock Cycle Time 133mhz +// tCK = 7, // Clock Cycle Time 143mhz +// tDH = 1, // Data-in Hold Time +// tDS = 2, // Data-in Setup Time +// tCKH = 1, // CKE Hold Time +// tCKS = 2, // CKE Setup Time +// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time +// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time +// $width (posedge Clk, tCH); +// $width (negedge Clk, tCL); +// $period (negedge Clk, tCK); +// $period (posedge Clk, tCK); +// $setuphold(posedge Clk, Cke, tCKS, tCKH); +// $setuphold(posedge Clk, Cs_n, tCMS, tCMH); +// $setuphold(posedge Clk, Cas_n, tCMS, tCMH); +// $setuphold(posedge Clk, Ras_n, tCMS, tCMH); +// $setuphold(posedge Clk, We_n, tCMS, tCMH); +// $setuphold(posedge Clk, Addr, tAS, tAH); +// $setuphold(posedge Clk, Ba, tAS, tAH); +// $setuphold(posedge Clk, Dqm, tCMS, tCMH); +// $setuphold(posedge Dq_chk, Dq, tDS, tDH); +// endspecify + +endmodule + diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_a_ref/tb_sdram_a_ref.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_a_ref/tb_sdram_a_ref.v new file mode 100644 index 0000000..a0fb5bf --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_a_ref/tb_sdram_a_ref.v @@ -0,0 +1,153 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : tb_sdram_a_ref +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SDRAM自刷新模块仿真 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module tb_sdram_a_ref(); + +//********************************************************************// +//****************** Internal Signal and Defparam ********************// +//********************************************************************// + +//wire define +//sdram +wire [3:0] sdram_cmd ; //SDRAM操作指令 +wire [1:0] sdram_ba ; //SDRAM L-Bank地址 +wire [12:0] sdram_addr ; //SDRAM地址总线 +//clk_gen +wire clk_50m ; //PLL输出50M时钟 +wire clk_100m ; //PLL输出100M时钟 +wire clk_100m_shift ; //PLL输出100M时钟,相位偏移-30deg +wire locked ; //PLL时钟锁定信号 +wire rst_n ; //复位信号,低有效 +//sdram_init +wire [3:0] init_cmd ; //初始化阶段指令 +wire [1:0] init_ba ; //初始化阶段L-Bank地址 +wire [12:0] init_addr ; //初始化阶段地址总线 +wire init_end ; //初始化完成信号 +//sdram_a_ref +wire aref_req ; //自动刷新请求 +wire aref_end ; //自动刷新结束 +wire [3:0] aref_cmd ; //自动刷新阶段指令 +wire [1:0] aref_ba ; //自动刷新阶段L-Bank地址 +wire [12:0] aref_addr ; //自动刷新阶段地址总线 + +//reg define +reg sys_clk ; //系统时钟 +reg sys_rst_n ; //复位信号 +reg aref_en ; //自动刷新使能 + +//defparam +//重定义仿真模型中的相关参数 +defparam sdram_model_plus_inst.addr_bits = 13; //地址位宽 +defparam sdram_model_plus_inst.data_bits = 16; //数据位宽 +defparam sdram_model_plus_inst.col_bits = 9; //列地址位宽 +defparam sdram_model_plus_inst.mem_sizes = 2*1024*1024; //L-Bank容量 + +//********************************************************************// +//**************************** Clk And Rst ***************************// +//********************************************************************// + +//时钟、复位信号 +initial + begin + sys_clk = 1'b1 ; + sys_rst_n <= 1'b0 ; + #200 + sys_rst_n <= 1'b1 ; + end + +always #10 sys_clk = ~sys_clk; + +//rst_n:复位信号 +assign rst_n = sys_rst_n & locked; + +//aref_en:自动刷新使能 +always@(posedge clk_100m or negedge rst_n) + if(rst_n == 1'b0) + aref_en <= 1'b0; + else if((init_end == 1'b1) && (aref_req == 1'b1)) + aref_en <= 1'b1; + else if(aref_end == 1'b1) + aref_en <= 1'b0; + +//sdram_cmd,sdram_ba,sdram_addr +assign sdram_cmd = (init_end == 1'b1) ? aref_cmd : init_cmd; +assign sdram_ba = (init_end == 1'b1) ? aref_ba : init_ba; +assign sdram_addr = (init_end == 1'b1) ? aref_addr : init_addr; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- clk_gen_inst ------------- +clk_gen clk_gen_inst ( + .inclk0 (sys_clk ), + .areset (~sys_rst_n ), + .c0 (clk_50m ), + .c1 (clk_100m ), + .c2 (clk_100m_shift ), + + .locked (locked ) +); + +//------------- sdram_init_inst ------------- +sdram_init sdram_init_inst( + + .sys_clk (clk_100m ), + .sys_rst_n (rst_n ), + + .init_cmd (init_cmd ), + .init_ba (init_ba ), + .init_addr (init_addr ), + .init_end (init_end ) + +); + +//------------- sdram_a_ref_inst ------------- +sdram_a_ref sdram_a_ref_inst( + + .sys_clk (clk_100m ), + .sys_rst_n (rst_n ), + .init_end (init_end ), + .aref_en (aref_en ), + + .aref_req (aref_req ), + .aref_cmd (aref_cmd ), + .aref_ba (aref_ba ), + .aref_addr (aref_addr ), + .aref_end (aref_end ) + +); + +//-------------sdram_model_plus_inst------------- +sdram_model_plus sdram_model_plus_inst( + .Dq ( ), + .Addr (sdram_addr ), + .Ba (sdram_ba ), + .Clk (clk_100m_shift ), + .Cke (1'b1 ), + .Cs_n (sdram_cmd[3] ), + .Ras_n (sdram_cmd[2] ), + .Cas_n (sdram_cmd[1] ), + .We_n (sdram_cmd[0] ), + .Dqm (2'b0 ), + .Debug (1'b1 ) + +); + +endmodule \ No newline at end of file diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_ctrl/sdram_model_plus.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_ctrl/sdram_model_plus.v new file mode 100644 index 0000000..4e51287 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_ctrl/sdram_model_plus.v @@ -0,0 +1,1131 @@ +/*************************************************************************************** +ߣ +2003-08-27 V0.1 + + ڴģ鵹չܣⲿҪ¼sdram_r ,SDRAMݽᰴBank ˳damp out ļ + sdram_data.txt +*/ +//2004-03-04 ˿ ޸ԭнBANKתTXTļĸʽ +//2004-03-16 ˿ ޸SDRAM ijʼ +//2004/04/06 ˿ SDRAMIJַʽʾԱMODELSIM +//2004/04/19 ˿ ޸IJ parameter tAC = 8; +//2010/09/17 ޸sdramĴСλdqm; +/**************************************************************************************** +* +* File Name: sdram_model.V +* Version: 0.0f +* Date: July 8th, 1999 +* Model: BUS Functional +* Simulator: Model Technology (PC version 5.2e PE) +* +* Dependencies: None +* +* Author: Son P. Huynh +* Email: sphuynh@micron.com +* Phone: (208) 368-3825 +* Company: Micron Technology, Inc. +* Model: sdram_model (1Meg x 16 x 4 Banks) +* +* Description: 64Mb SDRAM Verilog model +* +* Limitation: - Doesn't check for 4096 cycle refresh +* +* Note: - Set simulator resolution to "ps" accuracy +* - Set Debug = 0 to disable $display messages +* +* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +* +* Copyright ?1998 Micron Semiconductor Products, Inc. +* All rights researved +* +* Rev Author Phone Date Changes +* ---- ---------------------------- ---------- --------------------------------------- +* 0.0f Son Huynh 208-368-3825 07/08/1999 - Fix tWR = 1 Clk + 7.5 ns (Auto) +* Micron Technology Inc. - Fix tWR = 15 ns (Manual) +* - Fix tRP (Autoprecharge to AutoRefresh) +* +* 0.0a Son Huynh 208-368-3825 05/13/1998 - First Release (from 64Mb rev 0.0e) +* Micron Technology Inc. +****************************************************************************************/ + +`timescale 1ns / 100ps + +module sdram_model_plus (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm,Debug); + + parameter addr_bits = 11; + parameter data_bits = 32; + parameter col_bits = 8; + parameter mem_sizes = 1048576*2-1;//1 Meg + + inout [data_bits - 1 : 0] Dq; + input [addr_bits - 1 : 0] Addr; + input [1 : 0] Ba; + input Clk; + input Cke; + input Cs_n; + input Ras_n; + input Cas_n; + input We_n; + input [3 : 0] Dqm; //ߵ͸8bit + //added by xzli + input Debug; + + reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];//洢 + reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes]; + + reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline + reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline + reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline + reg [3 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline + reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr; + + reg [addr_bits - 1 : 0] Mode_reg; + reg [data_bits - 1 : 0] Dq_reg, Dq_dqm; + reg [col_bits - 1 : 0] Col_temp, Burst_counter; + + reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate + reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge + + reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command + reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks) + reg Auto_precharge [0 : 3]; // RW AutoPrecharge (Bank) + reg Read_precharge [0 : 3]; // R AutoPrecharge + reg Write_precharge [0 : 3]; // W AutoPrecharge + integer Count_precharge [0 : 3]; // RW AutoPrecharge (Counter) + reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge + reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge + + reg Data_in_enable; + reg Data_out_enable; + + reg [1 : 0] Bank, Previous_bank; + reg [addr_bits - 1 : 0] Row; + reg [col_bits - 1 : 0] Col, Col_brst; + + // Internal system clock + reg CkeZ, Sys_clk; + + reg [21:0] dd; + + // Commands Decode + wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n; + wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n; + wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n; + wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n; + wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n; + wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n; + wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n; + + // Burst Length Decode + wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0]; + wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; + + // CAS Latency Decode + wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4]; + wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4]; + + // Write Burst Mode + wire Write_burst_mode = Mode_reg[9]; + + wire Debug; // Debug messages : 1 = On; 0 = Off + wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ + + reg [31:0] mem_d; + + event sdram_r,sdram_w,compare; + + + + + assign Dq = Dq_reg; // DQ buffer + + // Commands Operation + `define ACT 0 + `define NOP 1 + `define READ 2 + `define READ_A 3 + `define WRITE 4 + `define WRITE_A 5 + `define PRECH 6 + `define A_REF 7 + `define BST 8 + `define LMR 9 + +// // Timing Parameters for -75 (PC133) and CAS Latency = 2 +// parameter tAC = 8; //test 6.5 +// parameter tHZ = 7.0; +// parameter tOH = 2.7; +// parameter tMRD = 2.0; // 2 Clk Cycles +// parameter tRAS = 44.0; +// parameter tRC = 66.0; +// parameter tRCD = 20.0; +// parameter tRP = 20.0; +// parameter tRRD = 15.0; +// parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) +// parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns) + + // Timing Parameters for -7 (PC143) and CAS Latency = 3 + parameter tAC = 6.5; //test 6.5 + parameter tHZ = 5.5; + parameter tOH = 2; + parameter tMRD = 2.0; // 2 Clk Cycles + parameter tRAS = 48.0; + parameter tRC = 70.0; + parameter tRCD = 20.0; + parameter tRP = 20.0; + parameter tRRD = 14.0; + parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) + parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns) + + // Timing Check variable + integer MRD_chk; + integer WR_counter [0 : 3]; + time WR_chk [0 : 3]; + time RC_chk, RRD_chk; + time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3; + time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; + time RP_chk0, RP_chk1, RP_chk2, RP_chk3; + + integer test_file; + + //*****display the command of the sdram************************************** + + parameter Mode_Reg_Set =4'b0000; + parameter Auto_Refresh =4'b0001; + parameter Row_Active =4'b0011; + parameter Pre_Charge =4'b0010; + parameter PreCharge_All =4'b0010; + parameter Write =4'b0100; + parameter Write_Pre =4'b0100; + parameter Read =4'b0101; + parameter Read_Pre =4'b0101; + parameter Burst_Stop =4'b0110; + parameter Nop =4'b0111; + parameter Dsel =4'b1111; + + wire [3:0] sdram_control; + reg cke_temp; + reg [8*13:1] sdram_command; + + always@(posedge Clk) + cke_temp<=Cke; + + assign sdram_control={Cs_n,Ras_n,Cas_n,We_n}; + + always@(sdram_control or cke_temp) + begin + case(sdram_control) + Mode_Reg_Set: sdram_command<="Mode_Reg_Set"; + Auto_Refresh: sdram_command<="Auto_Refresh"; + Row_Active: sdram_command<="Row_Active"; + Pre_Charge: sdram_command<="Pre_Charge"; + Burst_Stop: sdram_command<="Burst_Stop"; + Dsel: sdram_command<="Dsel"; + + Write: if(cke_temp==1) + sdram_command<="Write"; + else + sdram_command<="Write_suspend"; + + Read: if(cke_temp==1) + sdram_command<="Read"; + else + sdram_command<="Read_suspend"; + + Nop: if(cke_temp==1) + sdram_command<="Nop"; + else + sdram_command<="Self_refresh"; + + default: sdram_command<="Power_down"; + endcase + end + + //***************************************************** + + initial + begin + //test_file=$fopen("test_file.txt"); + end + + initial + begin + Dq_reg = {data_bits{1'bz}}; + {Data_in_enable, Data_out_enable} = 0; + {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000; + {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000; + {WR_chk[0], WR_chk[1], WR_chk[2], WR_chk[3]} = 0; + {WR_counter[0], WR_counter[1], WR_counter[2], WR_counter[3]} = 0; + {RW_interrupt_read[0], RW_interrupt_read[1], RW_interrupt_read[2], RW_interrupt_read[3]} = 0; + {RW_interrupt_write[0], RW_interrupt_write[1], RW_interrupt_write[2], RW_interrupt_write[3]} = 0; + {MRD_chk, RC_chk, RRD_chk} = 0; + {RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0; + {RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0; + {RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0; + $timeformat (-9, 0, " ns", 12); + //$readmemh("bank0.txt", Bank0); + //$readmemh("bank1.txt", Bank1); + //$readmemh("bank2.txt", Bank2); + //$readmemh("bank3.txt", Bank3); +/* + for(dd=0;dd<=mem_sizes;dd=dd+1) + begin + Bank0[dd]=dd[data_bits - 1 : 0]; + Bank1[dd]=dd[data_bits - 1 : 0]+1; + Bank2[dd]=dd[data_bits - 1 : 0]+2; + Bank3[dd]=dd[data_bits - 1 : 0]+3; + end +*/ + initial_sdram(0); + end + + task initial_sdram; + + input data_sign; + reg [3:0] data_sign; + + for(dd=0;dd<=mem_sizes;dd=dd+1) + begin + mem_d = {data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign}; + if(data_bits==16) + begin + Bank0[dd]=mem_d[15:0]; + Bank1[dd]=mem_d[15:0]; + Bank2[dd]=mem_d[15:0]; + Bank3[dd]=mem_d[15:0]; + end + else if(data_bits==32) + begin + Bank0[dd]=mem_d[31:0]; + Bank1[dd]=mem_d[31:0]; + Bank2[dd]=mem_d[31:0]; + Bank3[dd]=mem_d[31:0]; + end + end + + endtask + + // System clock generator + always + begin + @(posedge Clk) + begin + Sys_clk = CkeZ; + CkeZ = Cke; + end + @(negedge Clk) + begin + Sys_clk = 1'b0; + end + end + + always @ (posedge Sys_clk) begin + // Internal Commamd Pipelined + Command[0] = Command[1]; + Command[1] = Command[2]; + Command[2] = Command[3]; + Command[3] = `NOP; + + Col_addr[0] = Col_addr[1]; + Col_addr[1] = Col_addr[2]; + Col_addr[2] = Col_addr[3]; + Col_addr[3] = {col_bits{1'b0}}; + + Bank_addr[0] = Bank_addr[1]; + Bank_addr[1] = Bank_addr[2]; + Bank_addr[2] = Bank_addr[3]; + Bank_addr[3] = 2'b0; + + Bank_precharge[0] = Bank_precharge[1]; + Bank_precharge[1] = Bank_precharge[2]; + Bank_precharge[2] = Bank_precharge[3]; + Bank_precharge[3] = 2'b0; + + A10_precharge[0] = A10_precharge[1]; + A10_precharge[1] = A10_precharge[2]; + A10_precharge[2] = A10_precharge[3]; + A10_precharge[3] = 1'b0; + + // Dqm pipeline for Read + Dqm_reg0 = Dqm_reg1; + Dqm_reg1 = Dqm; + + // Read or Write with Auto Precharge Counter + if (Auto_precharge[0] == 1'b1) begin + Count_precharge[0] = Count_precharge[0] + 1; + end + if (Auto_precharge[1] == 1'b1) begin + Count_precharge[1] = Count_precharge[1] + 1; + end + if (Auto_precharge[2] == 1'b1) begin + Count_precharge[2] = Count_precharge[2] + 1; + end + if (Auto_precharge[3] == 1'b1) begin + Count_precharge[3] = Count_precharge[3] + 1; + end + + // tMRD Counter + MRD_chk = MRD_chk + 1; + + // tWR Counter for Write + WR_counter[0] = WR_counter[0] + 1; + WR_counter[1] = WR_counter[1] + 1; + WR_counter[2] = WR_counter[2] + 1; + WR_counter[3] = WR_counter[3] + 1; + + // Auto Refresh + if (Aref_enable == 1'b1) begin + if (Debug) $display ("at time %t AREF : Auto Refresh", $time); + // Auto Refresh to Auto Refresh + if (($time - RC_chk < tRC)&&Debug) begin + $display ("at time %t ERROR: tRC violation during Auto Refresh", $time); + end + // Precharge to Auto Refresh + if (($time - RP_chk0 < tRP || $time - RP_chk1 < tRP || $time - RP_chk2 < tRP || $time - RP_chk3 < tRP)&&Debug) begin + $display ("at time %t ERROR: tRP violation during Auto Refresh", $time); + end + // Precharge to Refresh + if (Pc_b0 == 1'b0 || Pc_b1 == 1'b0 || Pc_b2 == 1'b0 || Pc_b3 == 1'b0) begin + $display ("at time %t ERROR: All banks must be Precharge before Auto Refresh", $time); + end + // Record Current tRC time + RC_chk = $time; + end + + // Load Mode Register + if (Mode_reg_enable == 1'b1) begin + // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode + if (Pc_b0 == 1'b1 && Pc_b1 == 1'b1 && Pc_b2 == 1'b1 && Pc_b3 == 1'b1) begin + Mode_reg = Addr; + if (Debug) begin + $display ("at time %t LMR : Load Mode Register", $time); + // CAS Latency + if (Addr[6 : 4] == 3'b010) + $display (" CAS Latency = 2"); + else if (Addr[6 : 4] == 3'b011) + $display (" CAS Latency = 3"); + else + $display (" CAS Latency = Reserved"); + // Burst Length + if (Addr[2 : 0] == 3'b000) + $display (" Burst Length = 1"); + else if (Addr[2 : 0] == 3'b001) + $display (" Burst Length = 2"); + else if (Addr[2 : 0] == 3'b010) + $display (" Burst Length = 4"); + else if (Addr[2 : 0] == 3'b011) + $display (" Burst Length = 8"); + else if (Addr[3 : 0] == 4'b0111) + $display (" Burst Length = Full"); + else + $display (" Burst Length = Reserved"); + // Burst Type + if (Addr[3] == 1'b0) + $display (" Burst Type = Sequential"); + else if (Addr[3] == 1'b1) + $display (" Burst Type = Interleaved"); + else + $display (" Burst Type = Reserved"); + // Write Burst Mode + if (Addr[9] == 1'b0) + $display (" Write Burst Mode = Programmed Burst Length"); + else if (Addr[9] == 1'b1) + $display (" Write Burst Mode = Single Location Access"); + else + $display (" Write Burst Mode = Reserved"); + end + end else begin + $display ("at time %t ERROR: all banks must be Precharge before Load Mode Register", $time); + end + // REF to LMR + if ($time - RC_chk < tRC) begin + $display ("at time %t ERROR: tRC violation during Load Mode Register", $time); + end + // LMR to LMR + if (MRD_chk < tMRD) begin + $display ("at time %t ERROR: tMRD violation during Load Mode Register", $time); + end + MRD_chk = 0; + end + + // Active Block (Latch Bank Address and Row Address) + if (Active_enable == 1'b1) begin + if (Ba == 2'b00 && Pc_b0 == 1'b1) begin + {Act_b0, Pc_b0} = 2'b10; + B0_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk0 = $time; + RAS_chk0 = $time; + if (Debug) $display ("at time %t ACT : Bank = 0 Row = %d", $time, Addr); + // Precharge to Activate Bank 0 + if ($time - RP_chk0 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 0", $time); + end + end else if (Ba == 2'b01 && Pc_b1 == 1'b1) begin + {Act_b1, Pc_b1} = 2'b10; + B1_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk1 = $time; + RAS_chk1 = $time; + if (Debug) $display ("at time %t ACT : Bank = 1 Row = %d", $time, Addr); + // Precharge to Activate Bank 1 + if ($time - RP_chk1 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 1", $time); + end + end else if (Ba == 2'b10 && Pc_b2 == 1'b1) begin + {Act_b2, Pc_b2} = 2'b10; + B2_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk2 = $time; + RAS_chk2 = $time; + if (Debug) $display ("at time %t ACT : Bank = 2 Row = %d", $time, Addr); + // Precharge to Activate Bank 2 + if ($time - RP_chk2 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 2", $time); + end + end else if (Ba == 2'b11 && Pc_b3 == 1'b1) begin + {Act_b3, Pc_b3} = 2'b10; + B3_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk3 = $time; + RAS_chk3 = $time; + if (Debug) $display ("at time %t ACT : Bank = 3 Row = %d", $time, Addr); + // Precharge to Activate Bank 3 + if ($time - RP_chk3 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 3", $time); + end + end else if (Ba == 2'b00 && Pc_b0 == 1'b0) begin + $display ("at time %t ERROR: Bank 0 is not Precharged.", $time); + end else if (Ba == 2'b01 && Pc_b1 == 1'b0) begin + $display ("at time %t ERROR: Bank 1 is not Precharged.", $time); + end else if (Ba == 2'b10 && Pc_b2 == 1'b0) begin + $display ("at time %t ERROR: Bank 2 is not Precharged.", $time); + end else if (Ba == 2'b11 && Pc_b3 == 1'b0) begin + $display ("at time %t ERROR: Bank 3 is not Precharged.", $time); + end + // Active Bank A to Active Bank B + if ((Previous_bank != Ba) && ($time - RRD_chk < tRRD)) begin + $display ("at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba); + end + // Load Mode Register to Active + if (MRD_chk < tMRD ) begin + $display ("at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba); + end + // Auto Refresh to Activate + if (($time - RC_chk < tRC)&&Debug) begin + $display ("at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba); + end + // Record variables for checking violation + RRD_chk = $time; + Previous_bank = Ba; + end + + // Precharge Block + if (Prech_enable == 1'b1) begin + if (Addr[10] == 1'b1) begin + {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b1111; + {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000; + RP_chk0 = $time; + RP_chk1 = $time; + RP_chk2 = $time; + RP_chk3 = $time; + if (Debug) $display ("at time %t PRE : Bank = ALL",$time); + // Activate to Precharge all banks + if (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) || + ($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin + $display ("at time %t ERROR: tRAS violation during Precharge all bank", $time); + end + // tWR violation check for write + if (($time - WR_chk[0] < tWRp) || ($time - WR_chk[1] < tWRp) || + ($time - WR_chk[2] < tWRp) || ($time - WR_chk[3] < tWRp)) begin + $display ("at time %t ERROR: tWR violation during Precharge all bank", $time); + end + end else if (Addr[10] == 1'b0) begin + if (Ba == 2'b00) begin + {Pc_b0, Act_b0} = 2'b10; + RP_chk0 = $time; + if (Debug) $display ("at time %t PRE : Bank = 0",$time); + // Activate to Precharge Bank 0 + if ($time - RAS_chk0 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 0", $time); + end + end else if (Ba == 2'b01) begin + {Pc_b1, Act_b1} = 2'b10; + RP_chk1 = $time; + if (Debug) $display ("at time %t PRE : Bank = 1",$time); + // Activate to Precharge Bank 1 + if ($time - RAS_chk1 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 1", $time); + end + end else if (Ba == 2'b10) begin + {Pc_b2, Act_b2} = 2'b10; + RP_chk2 = $time; + if (Debug) $display ("at time %t PRE : Bank = 2",$time); + // Activate to Precharge Bank 2 + if ($time - RAS_chk2 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 2", $time); + end + end else if (Ba == 2'b11) begin + {Pc_b3, Act_b3} = 2'b10; + RP_chk3 = $time; + if (Debug) $display ("at time %t PRE : Bank = 3",$time); + // Activate to Precharge Bank 3 + if ($time - RAS_chk3 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 3", $time); + end + end + // tWR violation check for write + if ($time - WR_chk[Ba] < tWRp) begin + $display ("at time %t ERROR: tWR violation during Precharge bank %d", $time, Ba); + end + end + // Terminate a Write Immediately (if same bank or all banks) + if (Data_in_enable == 1'b1 && (Bank == Ba || Addr[10] == 1'b1)) begin + Data_in_enable = 1'b0; + end + // Precharge Command Pipeline for Read + if (Cas_latency_3 == 1'b1) begin + Command[2] = `PRECH; + Bank_precharge[2] = Ba; + A10_precharge[2] = Addr[10]; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `PRECH; + Bank_precharge[1] = Ba; + A10_precharge[1] = Addr[10]; + end + end + + // Burst terminate + if (Burst_term == 1'b1) begin + // Terminate a Write Immediately + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + // Terminate a Read Depend on CAS Latency + if (Cas_latency_3 == 1'b1) begin + Command[2] = `BST; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `BST; + end + if (Debug) $display ("at time %t BST : Burst Terminate",$time); + end + + // Read, Write, Column Latch + if (Read_enable == 1'b1 || Write_enable == 1'b1) begin + // Check to see if bank is open (ACT) + if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || + (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin + $display("at time %t ERROR: Cannot Read or Write - Bank %d is not Activated", $time, Ba); + end + // Activate to Read or Write + if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 0", $time); + if ((Ba == 2'b01) && ($time - RCD_chk1 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 1", $time); + if ((Ba == 2'b10) && ($time - RCD_chk2 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 2", $time); + if ((Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 3", $time); + // Read Command + if (Read_enable == 1'b1) begin + // CAS Latency pipeline + if (Cas_latency_3 == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[2] = `READ_A; + end else begin + Command[2] = `READ; + end + Col_addr[2] = Addr; + Bank_addr[2] = Ba; + end else if (Cas_latency_2 == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[1] = `READ_A; + end else begin + Command[1] = `READ; + end + Col_addr[1] = Addr; + Bank_addr[1] = Ba; + end + + // Read interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Write Command + end else if (Write_enable == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[0] = `WRITE_A; + end else begin + Command[0] = `WRITE; + end + Col_addr[0] = Addr; + Bank_addr[0] = Ba; + + // Write interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Write interrupt Read (terminate Read immediately) + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + // Interrupting a Write with Autoprecharge + if (Auto_precharge[Bank] == 1'b1 && Write_precharge[Bank] == 1'b1) begin + RW_interrupt_write[Bank] = 1'b1; + if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, Bank); + end + + // Interrupting a Read with Autoprecharge + if (Auto_precharge[Bank] == 1'b1 && Read_precharge[Bank] == 1'b1) begin + RW_interrupt_read[Bank] = 1'b1; + if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, Bank); + end + + // Read or Write with Auto Precharge + if (Addr[10] == 1'b1) begin + Auto_precharge[Ba] = 1'b1; + Count_precharge[Ba] = 0; + if (Read_enable == 1'b1) begin + Read_precharge[Ba] = 1'b1; + end else if (Write_enable == 1'b1) begin + Write_precharge[Ba] = 1'b1; + end + end + end + + // Read with Auto Precharge Calculation + // The device start internal precharge: + // 1. CAS Latency - 1 cycles before last burst + // and 2. Meet minimum tRAS requirement + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 2 + ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 1 + (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) || + (RW_interrupt_read[0] == 1'b1)) begin // Case 3 + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + Auto_precharge[0] = 1'b0; + Read_precharge[0] = 1'b0; + RW_interrupt_read[0] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) || + (RW_interrupt_read[1] == 1'b1)) begin + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + Auto_precharge[1] = 1'b0; + Read_precharge[1] = 1'b0; + RW_interrupt_read[1] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) || + (RW_interrupt_read[2] == 1'b1)) begin + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + Auto_precharge[2] = 1'b0; + Read_precharge[2] = 1'b0; + RW_interrupt_read[2] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) || + (RW_interrupt_read[3] == 1'b1)) begin + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + Auto_precharge[3] = 1'b0; + Read_precharge[3] = 1'b0; + RW_interrupt_read[3] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + + // Internal Precharge or Bst + if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks + if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + end else if (Command[0] == `BST) begin // BST terminate a read to current bank + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + if (Data_out_enable == 1'b0) begin + Dq_reg <= #tOH {data_bits{1'bz}}; + end + + // Detect Read or Write command + if (Command[0] == `READ || Command[0] == `READ_A) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + if (Bank_addr[0] == 2'b00) begin + Row = B0_row_addr; + end else if (Bank_addr[0] == 2'b01) begin + Row = B1_row_addr; + end else if (Bank_addr[0] == 2'b10) begin + Row = B2_row_addr; + end else if (Bank_addr[0] == 2'b11) begin + Row = B3_row_addr; + end + Burst_counter = 0; + Data_in_enable = 1'b0; + Data_out_enable = 1'b1; + end else if (Command[0] == `WRITE || Command[0] == `WRITE_A) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + if (Bank_addr[0] == 2'b00) begin + Row = B0_row_addr; + end else if (Bank_addr[0] == 2'b01) begin + Row = B1_row_addr; + end else if (Bank_addr[0] == 2'b10) begin + Row = B2_row_addr; + end else if (Bank_addr[0] == 2'b11) begin + Row = B3_row_addr; + end + Burst_counter = 0; + Data_in_enable = 1'b1; + Data_out_enable = 1'b0; + end + + // DQ buffer (Driver/Receiver) + if (Data_in_enable == 1'b1) begin // Writing Data to Memory + // Array buffer + if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}]; + if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}]; + if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}]; + if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}]; + // Dqm operation + if (Dqm[0] == 1'b0) Dq_dqm [ 7 : 0] = Dq [ 7 : 0]; + if (Dqm[1] == 1'b0) Dq_dqm [15 : 8] = Dq [15 : 8]; + //if (Dqm[2] == 1'b0) Dq_dqm [23 : 16] = Dq [23 : 16]; + // if (Dqm[3] == 1'b0) Dq_dqm [31 : 24] = Dq [31 : 24]; + // Write to memory + if (Bank == 2'b00) Bank0 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b01) Bank1 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b10) Bank2 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b11) Bank3 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b11 && Row==10'h3 && Col[7:4]==4'h4) + $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + //$fdisplay(test_file,"bank:%h row:%h col:%h write:%h",Bank,Row,Col,Dq_dqm); + // Output result + if (Dqm == 4'b1111) begin + if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end else begin + if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_dqm, Dqm); + // Record tWR time and reset counter + WR_chk [Bank] = $time; + WR_counter [Bank] = 0; + end + // Advance burst counter subroutine + #tHZ Burst; + end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory + //$display("%h , %h, %h",Bank0,Row,Col); + // Array buffer + if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}]; + if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}]; + if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}]; + if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}]; + + // Dqm operation + if (Dqm_reg0[0] == 1'b1) Dq_dqm [ 7 : 0] = 8'bz; + if (Dqm_reg0[1] == 1'b1) Dq_dqm [15 : 8] = 8'bz; + if (Dqm_reg0[2] == 1'b1) Dq_dqm [23 : 16] = 8'bz; + if (Dqm_reg0[3] == 1'b1) Dq_dqm [31 : 24] = 8'bz; + // Display result + Dq_reg [data_bits - 1 : 0] = #tAC Dq_dqm [data_bits - 1 : 0]; + if (Dqm_reg0 == 4'b1111) begin + if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end else begin + if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_reg, Dqm_reg0); + end + // Advance burst counter subroutine + Burst; + end + end + + // Write with Auto Precharge Calculation + // The device start internal precharge: + // 1. tWR Clock after last burst + // and 2. Meet minimum tRAS requirement + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + always @ (WR_counter[0]) begin + if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 2 + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 1 + (Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) || + (RW_interrupt_write[0] == 1'b1 && WR_counter[0] >= 2)) begin // Case 3 (stop count when interrupt) + Auto_precharge[0] = 1'b0; + Write_precharge[0] = 1'b0; + RW_interrupt_write[0] = 1'b0; + #tWRa; // Wait for tWR + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + end + always @ (WR_counter[1]) begin + if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) || + (RW_interrupt_write[1] == 1'b1 && WR_counter[1] >= 2)) begin + Auto_precharge[1] = 1'b0; + Write_precharge[1] = 1'b0; + RW_interrupt_write[1] = 1'b0; + #tWRa; // Wait for tWR + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + end + always @ (WR_counter[2]) begin + if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) || + (RW_interrupt_write[2] == 1'b1 && WR_counter[2] >= 2)) begin + Auto_precharge[2] = 1'b0; + Write_precharge[2] = 1'b0; + RW_interrupt_write[2] = 1'b0; + #tWRa; // Wait for tWR + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + end + always @ (WR_counter[3]) begin + if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) || + (RW_interrupt_write[3] == 1'b1 && WR_counter[3] >= 2)) begin + Auto_precharge[3] = 1'b0; + Write_precharge[3] = 1'b0; + RW_interrupt_write[3] = 1'b0; + #tWRa; // Wait for tWR + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + end + + task Burst; + begin + // Advance Burst Counter + Burst_counter = Burst_counter + 1; + + // Burst Type + if (Mode_reg[3] == 1'b0) begin // Sequential Burst + Col_temp = Col + 1; + end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst + Col_temp[2] = Burst_counter[2] ^ Col_brst[2]; + Col_temp[1] = Burst_counter[1] ^ Col_brst[1]; + Col_temp[0] = Burst_counter[0] ^ Col_brst[0]; + end + + // Burst Length + if (Burst_length_2) begin // Burst Length = 2 + Col [0] = Col_temp [0]; + end else if (Burst_length_4) begin // Burst Length = 4 + Col [1 : 0] = Col_temp [1 : 0]; + end else if (Burst_length_8) begin // Burst Length = 8 + Col [2 : 0] = Col_temp [2 : 0]; + end else begin // Burst Length = FULL + Col = Col_temp; + end + + // Burst Read Single Write + if (Write_burst_mode == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Data Counter + if (Burst_length_1 == 1'b1) begin + if (Burst_counter >= 1) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_2 == 1'b1) begin + if (Burst_counter >= 2) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_4 == 1'b1) begin + if (Burst_counter >= 4) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_8 == 1'b1) begin + if (Burst_counter >= 8) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end + end + endtask + + //**********************SDRAMڵֱⲿļ*******************************// + +/* + integer sdram_data,ind; + + + always@(sdram_r) + begin + sdram_data=$fopen("sdram_data.txt"); + $display("Sdram dampout begin ",sdram_data); +// $fdisplay(sdram_data,"Bank0"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank0[ind]); +// $fdisplay(sdram_data,"Bank1"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank1[ind]); +// $fdisplay(sdram_data,"Bank2"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank2[ind]); +// $fdisplay(sdram_data,"Bank3"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank3[ind]); + + $fclose("sdram_data.txt"); + //->compare; + end +*/ + integer sdram_data,sdram_mem; + reg [23:0] aa,cc; + reg [18:0] bb,ee; + + always@(sdram_r) + begin + $display("Sdram dampout begin ",$realtime); + sdram_data=$fopen("sdram_data.txt"); + for(aa=0;aa<4*(mem_sizes+1);aa=aa+1) + begin + bb=aa[18:0]; + if(aa<=mem_sizes) + $fdisplay(sdram_data,"%0d %0h",aa,Bank0[bb]); + else if(aa<=2*mem_sizes+1) + $fdisplay(sdram_data,"%0d %0h",aa,Bank1[bb]); + else if(aa<=3*mem_sizes+2) + $fdisplay(sdram_data,"%0d %0h",aa,Bank2[bb]); + else + $fdisplay(sdram_data,"%0d %0h",aa,Bank3[bb]); + end + $fclose("sdram_data.txt"); + + sdram_mem=$fopen("sdram_mem.txt"); + for(cc=0;cc<4*(mem_sizes+1);cc=cc+1) + begin + ee=cc[18:0]; + if(cc<=mem_sizes) + $fdisplay(sdram_mem,"%0h",Bank0[ee]); + else if(cc<=2*mem_sizes+1) + $fdisplay(sdram_mem,"%0h",Bank1[ee]); + else if(cc<=3*mem_sizes+2) + $fdisplay(sdram_mem,"%0h",Bank2[ee]); + else + $fdisplay(sdram_mem,"%0h",Bank3[ee]); + end + $fclose("sdram_mem.txt"); + + end + + + +// // Timing Parameters for -75 (PC133) and CAS Latency = 2 +// specify +// specparam +//// tAH = 0.8, // Addr, Ba Hold Time +//// tAS = 1.5, // Addr, Ba Setup Time +//// tCH = 2.5, // Clock High-Level Width +//// tCL = 2.5, // Clock Low-Level Width +////// tCK = 10.0, // Clock Cycle Time 100mhz +////// tCK = 7.5, // Clock Cycle Time 133mhz +//// tCK = 7, // Clock Cycle Time 143mhz +//// tDH = 0.8, // Data-in Hold Time +//// tDS = 1.5, // Data-in Setup Time +//// tCKH = 0.8, // CKE Hold Time +//// tCKS = 1.5, // CKE Setup Time +//// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time +//// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time +// tAH = 1, // Addr, Ba Hold Time +// tAS = 1.5, // Addr, Ba Setup Time +// tCH = 1, // Clock High-Level Width +// tCL = 3, // Clock Low-Level Width +//// tCK = 10.0, // Clock Cycle Time 100mhz +//// tCK = 7.5, // Clock Cycle Time 133mhz +// tCK = 7, // Clock Cycle Time 143mhz +// tDH = 1, // Data-in Hold Time +// tDS = 2, // Data-in Setup Time +// tCKH = 1, // CKE Hold Time +// tCKS = 2, // CKE Setup Time +// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time +// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time +// $width (posedge Clk, tCH); +// $width (negedge Clk, tCL); +// $period (negedge Clk, tCK); +// $period (posedge Clk, tCK); +// $setuphold(posedge Clk, Cke, tCKS, tCKH); +// $setuphold(posedge Clk, Cs_n, tCMS, tCMH); +// $setuphold(posedge Clk, Cas_n, tCMS, tCMH); +// $setuphold(posedge Clk, Ras_n, tCMS, tCMH); +// $setuphold(posedge Clk, We_n, tCMS, tCMH); +// $setuphold(posedge Clk, Addr, tAS, tAH); +// $setuphold(posedge Clk, Ba, tAS, tAH); +// $setuphold(posedge Clk, Dqm, tCMS, tCMH); +// $setuphold(posedge Dq_chk, Dq, tDS, tDH); +// endspecify + +endmodule + diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_ctrl/tb_sdram_ctrl.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_ctrl/tb_sdram_ctrl.v new file mode 100644 index 0000000..5a1b6bf --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_ctrl/tb_sdram_ctrl.v @@ -0,0 +1,172 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : tb_sdram_ctrl +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SDRAM控制模块仿真 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module tb_sdram_ctrl(); + +//********************************************************************// +//****************** Internal Signal and Defparam ********************// +//********************************************************************// + +//wire define +//clk_gen +wire clk_50m ; //PLL输出50M时钟 +wire clk_100m ; //PLL输出100M时钟 +wire clk_100m_shift ; //PLL输出100M时钟,相位偏移-75deg +wire locked ; //PLL时钟锁定信号 +wire rst_n ; //复位信号,低有效 +//sdram +wire sdram_cke ; //SDRAM时钟使能信号 +wire sdram_cs_n ; //SDRAM片选信号 +wire sdram_ras_n ; //SDRAM行选通信号 +wire sdram_cas_n ; //SDRAM列选题信号 +wire sdram_we_n ; //SDRAM写使能信号 +wire [1:0] sdram_ba ; //SDRAM L-Bank地址 +wire [12:0] sdram_addr ; //SDRAM地址总线 +wire [15:0] sdram_dq ; //SDRAM数据总线 +//sdram_ctrl +wire init_end ; //初始化完成信号 +wire sdram_wr_ack ; //数据写阶段写响应 +wire sdram_rd_ack ; //数据读阶段响应 + +//reg define +reg sys_clk ; //系统时钟 +reg sys_rst_n ; //复位信号 +reg wr_en ; //写使能 +reg [15:0] wr_data_in ; //写数据 +reg rd_en ; //读使能 + +//defparam +//重定义仿真模型中的相关参数 +defparam sdram_model_plus_inst.addr_bits = 13; //地址位宽 +defparam sdram_model_plus_inst.data_bits = 16; //数据位宽 +defparam sdram_model_plus_inst.col_bits = 9; //列地址位宽 +defparam sdram_model_plus_inst.mem_sizes = 2*1024*1024; //L-Bank容量 + +//重定义自动刷新模块自动刷新间隔时间计数最大值 +defparam sdram_ctrl_inst.sdram_a_ref_inst.CNT_REF_MAX = 39; + +//********************************************************************// +//**************************** Clk And Rst ***************************// +//********************************************************************// + +//时钟、复位信号 +initial + begin + sys_clk = 1'b1 ; + sys_rst_n <= 1'b0 ; + #200 + sys_rst_n <= 1'b1 ; + end + +always #10 sys_clk = ~sys_clk; + +//rst_n:复位信号 +assign rst_n = sys_rst_n & locked; + +//wr_en：写数据使能 +always@(posedge clk_100m or negedge rst_n) + if(rst_n == 1'b0) + wr_en <= 1'b1; + else if(wr_data_in == 10'd10) + wr_en <= 1'b0; + else + wr_en <= wr_en; + +//wr_data_in:写数据 +always@(posedge clk_100m or negedge rst_n) + if(rst_n == 1'b0) + wr_data_in <= 16'd0; + else if(wr_data_in == 16'd10) + wr_data_in <= 16'd0; + else if(sdram_wr_ack == 1'b1) + wr_data_in <= wr_data_in + 1'b1; + else + wr_data_in <= wr_data_in; + +//rd_en:读数据使能 +always@(posedge clk_100m or negedge rst_n) + if(rst_n == 1'b0) + rd_en <= 1'b0; + else if(wr_en == 1'b0) + rd_en <= 1'b1; + else + rd_en <= rd_en; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- clk_gen_inst ------------- +clk_gen clk_gen_inst ( + .inclk0 (sys_clk ), + .areset (~sys_rst_n ), + .c0 (clk_50m ), + .c1 (clk_100m ), + .c2 (clk_100m_shift ), + + .locked (locked ) +); + +//------------- sdram_ctrl_inst ------------- +sdram_ctrl sdram_ctrl_inst( + + .sys_clk (clk_100m ), //系统时钟 + .sys_rst_n (rst_n ), //复位信号，低电平有效 +//SDRAM 控制器写端口 + .sdram_wr_req (wr_en ), //写SDRAM请求信号 + .sdram_wr_addr (24'h000_000 ), //SDRAM写操作的地址 + .wr_burst_len (10'd10 ), //写sdram时数据突发长度 + .sdram_data_in (wr_data_in ), //写入SDRAM的数据 + .sdram_wr_ack (sdram_wr_ack ), //写SDRAM响应信号 +//SDRAM 控制器读端口 + .sdram_rd_req (rd_en ), //读SDRAM请求信号 + .sdram_rd_addr (24'h000_000 ), //SDRAM写操作的地址 + .rd_burst_len (10'd10 ), //读sdram时数据突发长度 + .sdram_data_out (sdram_data_out ), //从SDRAM读出的数据 + .init_end (init_end ), //SDRAM 初始化完成标志 + .sdram_rd_ack (sdram_rd_ack ), //读SDRAM响应信号 +//FPGA与SDRAM硬件接口 + .sdram_cke (sdram_cke ), // SDRAM 时钟有效信号 + .sdram_cs_n (sdram_cs_n ), // SDRAM 片选信号 + .sdram_ras_n (sdram_ras_n ), // SDRAM 行地址选通脉冲 + .sdram_cas_n (sdram_cas_n ), // SDRAM 列地址选通脉冲 + .sdram_we_n (sdram_we_n ), // SDRAM 写允许位 + .sdram_ba (sdram_ba ), // SDRAM L-Bank地址线 + .sdram_addr (sdram_addr ), // SDRAM 地址总线 + .sdram_dq (sdram_dq ) // SDRAM 数据总线 + +); + +//-------------sdram_model_plus_inst------------- +sdram_model_plus sdram_model_plus_inst( + .Dq (sdram_dq ), + .Addr (sdram_addr ), + .Ba (sdram_ba ), + .Clk (clk_100m_shift ), + .Cke (sdram_cke ), + .Cs_n (sdram_cs_n ), + .Ras_n (sdram_ras_n ), + .Cas_n (sdram_cas_n ), + .We_n (sdram_we_n ), + .Dqm (2'b0 ), + .Debug (1'b1 ) + +); + +endmodule \ No newline at end of file diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_init/sdram_model_plus.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_init/sdram_model_plus.v new file mode 100644 index 0000000..4e51287 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_init/sdram_model_plus.v @@ -0,0 +1,1131 @@ +/*************************************************************************************** +ߣ +2003-08-27 V0.1 + + ڴģ鵹չܣⲿҪ¼sdram_r ,SDRAMݽᰴBank ˳damp out ļ + sdram_data.txt +*/ +//2004-03-04 ˿ ޸ԭнBANKתTXTļĸʽ +//2004-03-16 ˿ ޸SDRAM ijʼ +//2004/04/06 ˿ SDRAMIJַʽʾԱMODELSIM +//2004/04/19 ˿ ޸IJ parameter tAC = 8; +//2010/09/17 ޸sdramĴСλdqm; +/**************************************************************************************** +* +* File Name: sdram_model.V +* Version: 0.0f +* Date: July 8th, 1999 +* Model: BUS Functional +* Simulator: Model Technology (PC version 5.2e PE) +* +* Dependencies: None +* +* Author: Son P. Huynh +* Email: sphuynh@micron.com +* Phone: (208) 368-3825 +* Company: Micron Technology, Inc. +* Model: sdram_model (1Meg x 16 x 4 Banks) +* +* Description: 64Mb SDRAM Verilog model +* +* Limitation: - Doesn't check for 4096 cycle refresh +* +* Note: - Set simulator resolution to "ps" accuracy +* - Set Debug = 0 to disable $display messages +* +* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +* +* Copyright ?1998 Micron Semiconductor Products, Inc. +* All rights researved +* +* Rev Author Phone Date Changes +* ---- ---------------------------- ---------- --------------------------------------- +* 0.0f Son Huynh 208-368-3825 07/08/1999 - Fix tWR = 1 Clk + 7.5 ns (Auto) +* Micron Technology Inc. - Fix tWR = 15 ns (Manual) +* - Fix tRP (Autoprecharge to AutoRefresh) +* +* 0.0a Son Huynh 208-368-3825 05/13/1998 - First Release (from 64Mb rev 0.0e) +* Micron Technology Inc. +****************************************************************************************/ + +`timescale 1ns / 100ps + +module sdram_model_plus (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm,Debug); + + parameter addr_bits = 11; + parameter data_bits = 32; + parameter col_bits = 8; + parameter mem_sizes = 1048576*2-1;//1 Meg + + inout [data_bits - 1 : 0] Dq; + input [addr_bits - 1 : 0] Addr; + input [1 : 0] Ba; + input Clk; + input Cke; + input Cs_n; + input Ras_n; + input Cas_n; + input We_n; + input [3 : 0] Dqm; //ߵ͸8bit + //added by xzli + input Debug; + + reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];//洢 + reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes]; + + reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline + reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline + reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline + reg [3 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline + reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr; + + reg [addr_bits - 1 : 0] Mode_reg; + reg [data_bits - 1 : 0] Dq_reg, Dq_dqm; + reg [col_bits - 1 : 0] Col_temp, Burst_counter; + + reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate + reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge + + reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command + reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks) + reg Auto_precharge [0 : 3]; // RW AutoPrecharge (Bank) + reg Read_precharge [0 : 3]; // R AutoPrecharge + reg Write_precharge [0 : 3]; // W AutoPrecharge + integer Count_precharge [0 : 3]; // RW AutoPrecharge (Counter) + reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge + reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge + + reg Data_in_enable; + reg Data_out_enable; + + reg [1 : 0] Bank, Previous_bank; + reg [addr_bits - 1 : 0] Row; + reg [col_bits - 1 : 0] Col, Col_brst; + + // Internal system clock + reg CkeZ, Sys_clk; + + reg [21:0] dd; + + // Commands Decode + wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n; + wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n; + wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n; + wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n; + wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n; + wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n; + wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n; + + // Burst Length Decode + wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0]; + wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; + + // CAS Latency Decode + wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4]; + wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4]; + + // Write Burst Mode + wire Write_burst_mode = Mode_reg[9]; + + wire Debug; // Debug messages : 1 = On; 0 = Off + wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ + + reg [31:0] mem_d; + + event sdram_r,sdram_w,compare; + + + + + assign Dq = Dq_reg; // DQ buffer + + // Commands Operation + `define ACT 0 + `define NOP 1 + `define READ 2 + `define READ_A 3 + `define WRITE 4 + `define WRITE_A 5 + `define PRECH 6 + `define A_REF 7 + `define BST 8 + `define LMR 9 + +// // Timing Parameters for -75 (PC133) and CAS Latency = 2 +// parameter tAC = 8; //test 6.5 +// parameter tHZ = 7.0; +// parameter tOH = 2.7; +// parameter tMRD = 2.0; // 2 Clk Cycles +// parameter tRAS = 44.0; +// parameter tRC = 66.0; +// parameter tRCD = 20.0; +// parameter tRP = 20.0; +// parameter tRRD = 15.0; +// parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) +// parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns) + + // Timing Parameters for -7 (PC143) and CAS Latency = 3 + parameter tAC = 6.5; //test 6.5 + parameter tHZ = 5.5; + parameter tOH = 2; + parameter tMRD = 2.0; // 2 Clk Cycles + parameter tRAS = 48.0; + parameter tRC = 70.0; + parameter tRCD = 20.0; + parameter tRP = 20.0; + parameter tRRD = 14.0; + parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) + parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns) + + // Timing Check variable + integer MRD_chk; + integer WR_counter [0 : 3]; + time WR_chk [0 : 3]; + time RC_chk, RRD_chk; + time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3; + time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; + time RP_chk0, RP_chk1, RP_chk2, RP_chk3; + + integer test_file; + + //*****display the command of the sdram************************************** + + parameter Mode_Reg_Set =4'b0000; + parameter Auto_Refresh =4'b0001; + parameter Row_Active =4'b0011; + parameter Pre_Charge =4'b0010; + parameter PreCharge_All =4'b0010; + parameter Write =4'b0100; + parameter Write_Pre =4'b0100; + parameter Read =4'b0101; + parameter Read_Pre =4'b0101; + parameter Burst_Stop =4'b0110; + parameter Nop =4'b0111; + parameter Dsel =4'b1111; + + wire [3:0] sdram_control; + reg cke_temp; + reg [8*13:1] sdram_command; + + always@(posedge Clk) + cke_temp<=Cke; + + assign sdram_control={Cs_n,Ras_n,Cas_n,We_n}; + + always@(sdram_control or cke_temp) + begin + case(sdram_control) + Mode_Reg_Set: sdram_command<="Mode_Reg_Set"; + Auto_Refresh: sdram_command<="Auto_Refresh"; + Row_Active: sdram_command<="Row_Active"; + Pre_Charge: sdram_command<="Pre_Charge"; + Burst_Stop: sdram_command<="Burst_Stop"; + Dsel: sdram_command<="Dsel"; + + Write: if(cke_temp==1) + sdram_command<="Write"; + else + sdram_command<="Write_suspend"; + + Read: if(cke_temp==1) + sdram_command<="Read"; + else + sdram_command<="Read_suspend"; + + Nop: if(cke_temp==1) + sdram_command<="Nop"; + else + sdram_command<="Self_refresh"; + + default: sdram_command<="Power_down"; + endcase + end + + //***************************************************** + + initial + begin + //test_file=$fopen("test_file.txt"); + end + + initial + begin + Dq_reg = {data_bits{1'bz}}; + {Data_in_enable, Data_out_enable} = 0; + {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000; + {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000; + {WR_chk[0], WR_chk[1], WR_chk[2], WR_chk[3]} = 0; + {WR_counter[0], WR_counter[1], WR_counter[2], WR_counter[3]} = 0; + {RW_interrupt_read[0], RW_interrupt_read[1], RW_interrupt_read[2], RW_interrupt_read[3]} = 0; + {RW_interrupt_write[0], RW_interrupt_write[1], RW_interrupt_write[2], RW_interrupt_write[3]} = 0; + {MRD_chk, RC_chk, RRD_chk} = 0; + {RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0; + {RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0; + {RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0; + $timeformat (-9, 0, " ns", 12); + //$readmemh("bank0.txt", Bank0); + //$readmemh("bank1.txt", Bank1); + //$readmemh("bank2.txt", Bank2); + //$readmemh("bank3.txt", Bank3); +/* + for(dd=0;dd<=mem_sizes;dd=dd+1) + begin + Bank0[dd]=dd[data_bits - 1 : 0]; + Bank1[dd]=dd[data_bits - 1 : 0]+1; + Bank2[dd]=dd[data_bits - 1 : 0]+2; + Bank3[dd]=dd[data_bits - 1 : 0]+3; + end +*/ + initial_sdram(0); + end + + task initial_sdram; + + input data_sign; + reg [3:0] data_sign; + + for(dd=0;dd<=mem_sizes;dd=dd+1) + begin + mem_d = {data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign}; + if(data_bits==16) + begin + Bank0[dd]=mem_d[15:0]; + Bank1[dd]=mem_d[15:0]; + Bank2[dd]=mem_d[15:0]; + Bank3[dd]=mem_d[15:0]; + end + else if(data_bits==32) + begin + Bank0[dd]=mem_d[31:0]; + Bank1[dd]=mem_d[31:0]; + Bank2[dd]=mem_d[31:0]; + Bank3[dd]=mem_d[31:0]; + end + end + + endtask + + // System clock generator + always + begin + @(posedge Clk) + begin + Sys_clk = CkeZ; + CkeZ = Cke; + end + @(negedge Clk) + begin + Sys_clk = 1'b0; + end + end + + always @ (posedge Sys_clk) begin + // Internal Commamd Pipelined + Command[0] = Command[1]; + Command[1] = Command[2]; + Command[2] = Command[3]; + Command[3] = `NOP; + + Col_addr[0] = Col_addr[1]; + Col_addr[1] = Col_addr[2]; + Col_addr[2] = Col_addr[3]; + Col_addr[3] = {col_bits{1'b0}}; + + Bank_addr[0] = Bank_addr[1]; + Bank_addr[1] = Bank_addr[2]; + Bank_addr[2] = Bank_addr[3]; + Bank_addr[3] = 2'b0; + + Bank_precharge[0] = Bank_precharge[1]; + Bank_precharge[1] = Bank_precharge[2]; + Bank_precharge[2] = Bank_precharge[3]; + Bank_precharge[3] = 2'b0; + + A10_precharge[0] = A10_precharge[1]; + A10_precharge[1] = A10_precharge[2]; + A10_precharge[2] = A10_precharge[3]; + A10_precharge[3] = 1'b0; + + // Dqm pipeline for Read + Dqm_reg0 = Dqm_reg1; + Dqm_reg1 = Dqm; + + // Read or Write with Auto Precharge Counter + if (Auto_precharge[0] == 1'b1) begin + Count_precharge[0] = Count_precharge[0] + 1; + end + if (Auto_precharge[1] == 1'b1) begin + Count_precharge[1] = Count_precharge[1] + 1; + end + if (Auto_precharge[2] == 1'b1) begin + Count_precharge[2] = Count_precharge[2] + 1; + end + if (Auto_precharge[3] == 1'b1) begin + Count_precharge[3] = Count_precharge[3] + 1; + end + + // tMRD Counter + MRD_chk = MRD_chk + 1; + + // tWR Counter for Write + WR_counter[0] = WR_counter[0] + 1; + WR_counter[1] = WR_counter[1] + 1; + WR_counter[2] = WR_counter[2] + 1; + WR_counter[3] = WR_counter[3] + 1; + + // Auto Refresh + if (Aref_enable == 1'b1) begin + if (Debug) $display ("at time %t AREF : Auto Refresh", $time); + // Auto Refresh to Auto Refresh + if (($time - RC_chk < tRC)&&Debug) begin + $display ("at time %t ERROR: tRC violation during Auto Refresh", $time); + end + // Precharge to Auto Refresh + if (($time - RP_chk0 < tRP || $time - RP_chk1 < tRP || $time - RP_chk2 < tRP || $time - RP_chk3 < tRP)&&Debug) begin + $display ("at time %t ERROR: tRP violation during Auto Refresh", $time); + end + // Precharge to Refresh + if (Pc_b0 == 1'b0 || Pc_b1 == 1'b0 || Pc_b2 == 1'b0 || Pc_b3 == 1'b0) begin + $display ("at time %t ERROR: All banks must be Precharge before Auto Refresh", $time); + end + // Record Current tRC time + RC_chk = $time; + end + + // Load Mode Register + if (Mode_reg_enable == 1'b1) begin + // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode + if (Pc_b0 == 1'b1 && Pc_b1 == 1'b1 && Pc_b2 == 1'b1 && Pc_b3 == 1'b1) begin + Mode_reg = Addr; + if (Debug) begin + $display ("at time %t LMR : Load Mode Register", $time); + // CAS Latency + if (Addr[6 : 4] == 3'b010) + $display (" CAS Latency = 2"); + else if (Addr[6 : 4] == 3'b011) + $display (" CAS Latency = 3"); + else + $display (" CAS Latency = Reserved"); + // Burst Length + if (Addr[2 : 0] == 3'b000) + $display (" Burst Length = 1"); + else if (Addr[2 : 0] == 3'b001) + $display (" Burst Length = 2"); + else if (Addr[2 : 0] == 3'b010) + $display (" Burst Length = 4"); + else if (Addr[2 : 0] == 3'b011) + $display (" Burst Length = 8"); + else if (Addr[3 : 0] == 4'b0111) + $display (" Burst Length = Full"); + else + $display (" Burst Length = Reserved"); + // Burst Type + if (Addr[3] == 1'b0) + $display (" Burst Type = Sequential"); + else if (Addr[3] == 1'b1) + $display (" Burst Type = Interleaved"); + else + $display (" Burst Type = Reserved"); + // Write Burst Mode + if (Addr[9] == 1'b0) + $display (" Write Burst Mode = Programmed Burst Length"); + else if (Addr[9] == 1'b1) + $display (" Write Burst Mode = Single Location Access"); + else + $display (" Write Burst Mode = Reserved"); + end + end else begin + $display ("at time %t ERROR: all banks must be Precharge before Load Mode Register", $time); + end + // REF to LMR + if ($time - RC_chk < tRC) begin + $display ("at time %t ERROR: tRC violation during Load Mode Register", $time); + end + // LMR to LMR + if (MRD_chk < tMRD) begin + $display ("at time %t ERROR: tMRD violation during Load Mode Register", $time); + end + MRD_chk = 0; + end + + // Active Block (Latch Bank Address and Row Address) + if (Active_enable == 1'b1) begin + if (Ba == 2'b00 && Pc_b0 == 1'b1) begin + {Act_b0, Pc_b0} = 2'b10; + B0_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk0 = $time; + RAS_chk0 = $time; + if (Debug) $display ("at time %t ACT : Bank = 0 Row = %d", $time, Addr); + // Precharge to Activate Bank 0 + if ($time - RP_chk0 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 0", $time); + end + end else if (Ba == 2'b01 && Pc_b1 == 1'b1) begin + {Act_b1, Pc_b1} = 2'b10; + B1_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk1 = $time; + RAS_chk1 = $time; + if (Debug) $display ("at time %t ACT : Bank = 1 Row = %d", $time, Addr); + // Precharge to Activate Bank 1 + if ($time - RP_chk1 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 1", $time); + end + end else if (Ba == 2'b10 && Pc_b2 == 1'b1) begin + {Act_b2, Pc_b2} = 2'b10; + B2_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk2 = $time; + RAS_chk2 = $time; + if (Debug) $display ("at time %t ACT : Bank = 2 Row = %d", $time, Addr); + // Precharge to Activate Bank 2 + if ($time - RP_chk2 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 2", $time); + end + end else if (Ba == 2'b11 && Pc_b3 == 1'b1) begin + {Act_b3, Pc_b3} = 2'b10; + B3_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk3 = $time; + RAS_chk3 = $time; + if (Debug) $display ("at time %t ACT : Bank = 3 Row = %d", $time, Addr); + // Precharge to Activate Bank 3 + if ($time - RP_chk3 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 3", $time); + end + end else if (Ba == 2'b00 && Pc_b0 == 1'b0) begin + $display ("at time %t ERROR: Bank 0 is not Precharged.", $time); + end else if (Ba == 2'b01 && Pc_b1 == 1'b0) begin + $display ("at time %t ERROR: Bank 1 is not Precharged.", $time); + end else if (Ba == 2'b10 && Pc_b2 == 1'b0) begin + $display ("at time %t ERROR: Bank 2 is not Precharged.", $time); + end else if (Ba == 2'b11 && Pc_b3 == 1'b0) begin + $display ("at time %t ERROR: Bank 3 is not Precharged.", $time); + end + // Active Bank A to Active Bank B + if ((Previous_bank != Ba) && ($time - RRD_chk < tRRD)) begin + $display ("at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba); + end + // Load Mode Register to Active + if (MRD_chk < tMRD ) begin + $display ("at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba); + end + // Auto Refresh to Activate + if (($time - RC_chk < tRC)&&Debug) begin + $display ("at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba); + end + // Record variables for checking violation + RRD_chk = $time; + Previous_bank = Ba; + end + + // Precharge Block + if (Prech_enable == 1'b1) begin + if (Addr[10] == 1'b1) begin + {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b1111; + {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000; + RP_chk0 = $time; + RP_chk1 = $time; + RP_chk2 = $time; + RP_chk3 = $time; + if (Debug) $display ("at time %t PRE : Bank = ALL",$time); + // Activate to Precharge all banks + if (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) || + ($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin + $display ("at time %t ERROR: tRAS violation during Precharge all bank", $time); + end + // tWR violation check for write + if (($time - WR_chk[0] < tWRp) || ($time - WR_chk[1] < tWRp) || + ($time - WR_chk[2] < tWRp) || ($time - WR_chk[3] < tWRp)) begin + $display ("at time %t ERROR: tWR violation during Precharge all bank", $time); + end + end else if (Addr[10] == 1'b0) begin + if (Ba == 2'b00) begin + {Pc_b0, Act_b0} = 2'b10; + RP_chk0 = $time; + if (Debug) $display ("at time %t PRE : Bank = 0",$time); + // Activate to Precharge Bank 0 + if ($time - RAS_chk0 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 0", $time); + end + end else if (Ba == 2'b01) begin + {Pc_b1, Act_b1} = 2'b10; + RP_chk1 = $time; + if (Debug) $display ("at time %t PRE : Bank = 1",$time); + // Activate to Precharge Bank 1 + if ($time - RAS_chk1 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 1", $time); + end + end else if (Ba == 2'b10) begin + {Pc_b2, Act_b2} = 2'b10; + RP_chk2 = $time; + if (Debug) $display ("at time %t PRE : Bank = 2",$time); + // Activate to Precharge Bank 2 + if ($time - RAS_chk2 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 2", $time); + end + end else if (Ba == 2'b11) begin + {Pc_b3, Act_b3} = 2'b10; + RP_chk3 = $time; + if (Debug) $display ("at time %t PRE : Bank = 3",$time); + // Activate to Precharge Bank 3 + if ($time - RAS_chk3 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 3", $time); + end + end + // tWR violation check for write + if ($time - WR_chk[Ba] < tWRp) begin + $display ("at time %t ERROR: tWR violation during Precharge bank %d", $time, Ba); + end + end + // Terminate a Write Immediately (if same bank or all banks) + if (Data_in_enable == 1'b1 && (Bank == Ba || Addr[10] == 1'b1)) begin + Data_in_enable = 1'b0; + end + // Precharge Command Pipeline for Read + if (Cas_latency_3 == 1'b1) begin + Command[2] = `PRECH; + Bank_precharge[2] = Ba; + A10_precharge[2] = Addr[10]; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `PRECH; + Bank_precharge[1] = Ba; + A10_precharge[1] = Addr[10]; + end + end + + // Burst terminate + if (Burst_term == 1'b1) begin + // Terminate a Write Immediately + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + // Terminate a Read Depend on CAS Latency + if (Cas_latency_3 == 1'b1) begin + Command[2] = `BST; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `BST; + end + if (Debug) $display ("at time %t BST : Burst Terminate",$time); + end + + // Read, Write, Column Latch + if (Read_enable == 1'b1 || Write_enable == 1'b1) begin + // Check to see if bank is open (ACT) + if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || + (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin + $display("at time %t ERROR: Cannot Read or Write - Bank %d is not Activated", $time, Ba); + end + // Activate to Read or Write + if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 0", $time); + if ((Ba == 2'b01) && ($time - RCD_chk1 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 1", $time); + if ((Ba == 2'b10) && ($time - RCD_chk2 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 2", $time); + if ((Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 3", $time); + // Read Command + if (Read_enable == 1'b1) begin + // CAS Latency pipeline + if (Cas_latency_3 == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[2] = `READ_A; + end else begin + Command[2] = `READ; + end + Col_addr[2] = Addr; + Bank_addr[2] = Ba; + end else if (Cas_latency_2 == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[1] = `READ_A; + end else begin + Command[1] = `READ; + end + Col_addr[1] = Addr; + Bank_addr[1] = Ba; + end + + // Read interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Write Command + end else if (Write_enable == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[0] = `WRITE_A; + end else begin + Command[0] = `WRITE; + end + Col_addr[0] = Addr; + Bank_addr[0] = Ba; + + // Write interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Write interrupt Read (terminate Read immediately) + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + // Interrupting a Write with Autoprecharge + if (Auto_precharge[Bank] == 1'b1 && Write_precharge[Bank] == 1'b1) begin + RW_interrupt_write[Bank] = 1'b1; + if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, Bank); + end + + // Interrupting a Read with Autoprecharge + if (Auto_precharge[Bank] == 1'b1 && Read_precharge[Bank] == 1'b1) begin + RW_interrupt_read[Bank] = 1'b1; + if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, Bank); + end + + // Read or Write with Auto Precharge + if (Addr[10] == 1'b1) begin + Auto_precharge[Ba] = 1'b1; + Count_precharge[Ba] = 0; + if (Read_enable == 1'b1) begin + Read_precharge[Ba] = 1'b1; + end else if (Write_enable == 1'b1) begin + Write_precharge[Ba] = 1'b1; + end + end + end + + // Read with Auto Precharge Calculation + // The device start internal precharge: + // 1. CAS Latency - 1 cycles before last burst + // and 2. Meet minimum tRAS requirement + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 2 + ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 1 + (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) || + (RW_interrupt_read[0] == 1'b1)) begin // Case 3 + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + Auto_precharge[0] = 1'b0; + Read_precharge[0] = 1'b0; + RW_interrupt_read[0] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) || + (RW_interrupt_read[1] == 1'b1)) begin + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + Auto_precharge[1] = 1'b0; + Read_precharge[1] = 1'b0; + RW_interrupt_read[1] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) || + (RW_interrupt_read[2] == 1'b1)) begin + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + Auto_precharge[2] = 1'b0; + Read_precharge[2] = 1'b0; + RW_interrupt_read[2] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) || + (RW_interrupt_read[3] == 1'b1)) begin + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + Auto_precharge[3] = 1'b0; + Read_precharge[3] = 1'b0; + RW_interrupt_read[3] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + + // Internal Precharge or Bst + if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks + if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + end else if (Command[0] == `BST) begin // BST terminate a read to current bank + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + if (Data_out_enable == 1'b0) begin + Dq_reg <= #tOH {data_bits{1'bz}}; + end + + // Detect Read or Write command + if (Command[0] == `READ || Command[0] == `READ_A) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + if (Bank_addr[0] == 2'b00) begin + Row = B0_row_addr; + end else if (Bank_addr[0] == 2'b01) begin + Row = B1_row_addr; + end else if (Bank_addr[0] == 2'b10) begin + Row = B2_row_addr; + end else if (Bank_addr[0] == 2'b11) begin + Row = B3_row_addr; + end + Burst_counter = 0; + Data_in_enable = 1'b0; + Data_out_enable = 1'b1; + end else if (Command[0] == `WRITE || Command[0] == `WRITE_A) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + if (Bank_addr[0] == 2'b00) begin + Row = B0_row_addr; + end else if (Bank_addr[0] == 2'b01) begin + Row = B1_row_addr; + end else if (Bank_addr[0] == 2'b10) begin + Row = B2_row_addr; + end else if (Bank_addr[0] == 2'b11) begin + Row = B3_row_addr; + end + Burst_counter = 0; + Data_in_enable = 1'b1; + Data_out_enable = 1'b0; + end + + // DQ buffer (Driver/Receiver) + if (Data_in_enable == 1'b1) begin // Writing Data to Memory + // Array buffer + if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}]; + if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}]; + if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}]; + if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}]; + // Dqm operation + if (Dqm[0] == 1'b0) Dq_dqm [ 7 : 0] = Dq [ 7 : 0]; + if (Dqm[1] == 1'b0) Dq_dqm [15 : 8] = Dq [15 : 8]; + //if (Dqm[2] == 1'b0) Dq_dqm [23 : 16] = Dq [23 : 16]; + // if (Dqm[3] == 1'b0) Dq_dqm [31 : 24] = Dq [31 : 24]; + // Write to memory + if (Bank == 2'b00) Bank0 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b01) Bank1 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b10) Bank2 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b11) Bank3 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b11 && Row==10'h3 && Col[7:4]==4'h4) + $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + //$fdisplay(test_file,"bank:%h row:%h col:%h write:%h",Bank,Row,Col,Dq_dqm); + // Output result + if (Dqm == 4'b1111) begin + if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end else begin + if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_dqm, Dqm); + // Record tWR time and reset counter + WR_chk [Bank] = $time; + WR_counter [Bank] = 0; + end + // Advance burst counter subroutine + #tHZ Burst; + end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory + //$display("%h , %h, %h",Bank0,Row,Col); + // Array buffer + if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}]; + if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}]; + if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}]; + if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}]; + + // Dqm operation + if (Dqm_reg0[0] == 1'b1) Dq_dqm [ 7 : 0] = 8'bz; + if (Dqm_reg0[1] == 1'b1) Dq_dqm [15 : 8] = 8'bz; + if (Dqm_reg0[2] == 1'b1) Dq_dqm [23 : 16] = 8'bz; + if (Dqm_reg0[3] == 1'b1) Dq_dqm [31 : 24] = 8'bz; + // Display result + Dq_reg [data_bits - 1 : 0] = #tAC Dq_dqm [data_bits - 1 : 0]; + if (Dqm_reg0 == 4'b1111) begin + if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end else begin + if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_reg, Dqm_reg0); + end + // Advance burst counter subroutine + Burst; + end + end + + // Write with Auto Precharge Calculation + // The device start internal precharge: + // 1. tWR Clock after last burst + // and 2. Meet minimum tRAS requirement + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + always @ (WR_counter[0]) begin + if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 2 + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 1 + (Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) || + (RW_interrupt_write[0] == 1'b1 && WR_counter[0] >= 2)) begin // Case 3 (stop count when interrupt) + Auto_precharge[0] = 1'b0; + Write_precharge[0] = 1'b0; + RW_interrupt_write[0] = 1'b0; + #tWRa; // Wait for tWR + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + end + always @ (WR_counter[1]) begin + if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) || + (RW_interrupt_write[1] == 1'b1 && WR_counter[1] >= 2)) begin + Auto_precharge[1] = 1'b0; + Write_precharge[1] = 1'b0; + RW_interrupt_write[1] = 1'b0; + #tWRa; // Wait for tWR + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + end + always @ (WR_counter[2]) begin + if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) || + (RW_interrupt_write[2] == 1'b1 && WR_counter[2] >= 2)) begin + Auto_precharge[2] = 1'b0; + Write_precharge[2] = 1'b0; + RW_interrupt_write[2] = 1'b0; + #tWRa; // Wait for tWR + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + end + always @ (WR_counter[3]) begin + if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) || + (RW_interrupt_write[3] == 1'b1 && WR_counter[3] >= 2)) begin + Auto_precharge[3] = 1'b0; + Write_precharge[3] = 1'b0; + RW_interrupt_write[3] = 1'b0; + #tWRa; // Wait for tWR + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + end + + task Burst; + begin + // Advance Burst Counter + Burst_counter = Burst_counter + 1; + + // Burst Type + if (Mode_reg[3] == 1'b0) begin // Sequential Burst + Col_temp = Col + 1; + end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst + Col_temp[2] = Burst_counter[2] ^ Col_brst[2]; + Col_temp[1] = Burst_counter[1] ^ Col_brst[1]; + Col_temp[0] = Burst_counter[0] ^ Col_brst[0]; + end + + // Burst Length + if (Burst_length_2) begin // Burst Length = 2 + Col [0] = Col_temp [0]; + end else if (Burst_length_4) begin // Burst Length = 4 + Col [1 : 0] = Col_temp [1 : 0]; + end else if (Burst_length_8) begin // Burst Length = 8 + Col [2 : 0] = Col_temp [2 : 0]; + end else begin // Burst Length = FULL + Col = Col_temp; + end + + // Burst Read Single Write + if (Write_burst_mode == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Data Counter + if (Burst_length_1 == 1'b1) begin + if (Burst_counter >= 1) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_2 == 1'b1) begin + if (Burst_counter >= 2) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_4 == 1'b1) begin + if (Burst_counter >= 4) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_8 == 1'b1) begin + if (Burst_counter >= 8) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end + end + endtask + + //**********************SDRAMڵֱⲿļ*******************************// + +/* + integer sdram_data,ind; + + + always@(sdram_r) + begin + sdram_data=$fopen("sdram_data.txt"); + $display("Sdram dampout begin ",sdram_data); +// $fdisplay(sdram_data,"Bank0"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank0[ind]); +// $fdisplay(sdram_data,"Bank1"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank1[ind]); +// $fdisplay(sdram_data,"Bank2"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank2[ind]); +// $fdisplay(sdram_data,"Bank3"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank3[ind]); + + $fclose("sdram_data.txt"); + //->compare; + end +*/ + integer sdram_data,sdram_mem; + reg [23:0] aa,cc; + reg [18:0] bb,ee; + + always@(sdram_r) + begin + $display("Sdram dampout begin ",$realtime); + sdram_data=$fopen("sdram_data.txt"); + for(aa=0;aa<4*(mem_sizes+1);aa=aa+1) + begin + bb=aa[18:0]; + if(aa<=mem_sizes) + $fdisplay(sdram_data,"%0d %0h",aa,Bank0[bb]); + else if(aa<=2*mem_sizes+1) + $fdisplay(sdram_data,"%0d %0h",aa,Bank1[bb]); + else if(aa<=3*mem_sizes+2) + $fdisplay(sdram_data,"%0d %0h",aa,Bank2[bb]); + else + $fdisplay(sdram_data,"%0d %0h",aa,Bank3[bb]); + end + $fclose("sdram_data.txt"); + + sdram_mem=$fopen("sdram_mem.txt"); + for(cc=0;cc<4*(mem_sizes+1);cc=cc+1) + begin + ee=cc[18:0]; + if(cc<=mem_sizes) + $fdisplay(sdram_mem,"%0h",Bank0[ee]); + else if(cc<=2*mem_sizes+1) + $fdisplay(sdram_mem,"%0h",Bank1[ee]); + else if(cc<=3*mem_sizes+2) + $fdisplay(sdram_mem,"%0h",Bank2[ee]); + else + $fdisplay(sdram_mem,"%0h",Bank3[ee]); + end + $fclose("sdram_mem.txt"); + + end + + + +// // Timing Parameters for -75 (PC133) and CAS Latency = 2 +// specify +// specparam +//// tAH = 0.8, // Addr, Ba Hold Time +//// tAS = 1.5, // Addr, Ba Setup Time +//// tCH = 2.5, // Clock High-Level Width +//// tCL = 2.5, // Clock Low-Level Width +////// tCK = 10.0, // Clock Cycle Time 100mhz +////// tCK = 7.5, // Clock Cycle Time 133mhz +//// tCK = 7, // Clock Cycle Time 143mhz +//// tDH = 0.8, // Data-in Hold Time +//// tDS = 1.5, // Data-in Setup Time +//// tCKH = 0.8, // CKE Hold Time +//// tCKS = 1.5, // CKE Setup Time +//// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time +//// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time +// tAH = 1, // Addr, Ba Hold Time +// tAS = 1.5, // Addr, Ba Setup Time +// tCH = 1, // Clock High-Level Width +// tCL = 3, // Clock Low-Level Width +//// tCK = 10.0, // Clock Cycle Time 100mhz +//// tCK = 7.5, // Clock Cycle Time 133mhz +// tCK = 7, // Clock Cycle Time 143mhz +// tDH = 1, // Data-in Hold Time +// tDS = 2, // Data-in Setup Time +// tCKH = 1, // CKE Hold Time +// tCKS = 2, // CKE Setup Time +// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time +// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time +// $width (posedge Clk, tCH); +// $width (negedge Clk, tCL); +// $period (negedge Clk, tCK); +// $period (posedge Clk, tCK); +// $setuphold(posedge Clk, Cke, tCKS, tCKH); +// $setuphold(posedge Clk, Cs_n, tCMS, tCMH); +// $setuphold(posedge Clk, Cas_n, tCMS, tCMH); +// $setuphold(posedge Clk, Ras_n, tCMS, tCMH); +// $setuphold(posedge Clk, We_n, tCMS, tCMH); +// $setuphold(posedge Clk, Addr, tAS, tAH); +// $setuphold(posedge Clk, Ba, tAS, tAH); +// $setuphold(posedge Clk, Dqm, tCMS, tCMH); +// $setuphold(posedge Dq_chk, Dq, tDS, tDH); +// endspecify + +endmodule + diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_init/tb_sdram_init.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_init/tb_sdram_init.v new file mode 100644 index 0000000..8a1d976 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_init/tb_sdram_init.v @@ -0,0 +1,112 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : tb_sdram_init +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SDRAM初始化模块仿真 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module tb_sdram_init(); + +//********************************************************************// +//****************** Internal Signal and Defparam ********************// +//********************************************************************// + +//wire define +//clk_gen +wire clk_50m ; //PLL输出50M时钟 +wire clk_100m ; //PLL输出100M时钟 +wire clk_100m_shift ; //PLL输出100M时钟,相位偏移-30deg +wire locked ; //PLL时钟锁定信号 +wire rst_n ; //复位信号,低有效 +//sdram_init +wire [3:0] init_cmd ; //初始化阶段指令 +wire [1:0] init_ba ; //初始化阶段L-Bank地址 +wire [12:0] init_addr ; //初始化阶段地址总线 +wire init_end ; //初始化完成信号 + +//reg define +reg sys_clk ; //系统时钟 +reg sys_rst_n ; //复位信号 + +//defparam +//重定义仿真模型中的相关参数 +defparam sdram_model_plus_inst.addr_bits = 13; //地址位宽 +defparam sdram_model_plus_inst.data_bits = 16; //数据位宽 +defparam sdram_model_plus_inst.col_bits = 9; //列地址位宽 +defparam sdram_model_plus_inst.mem_sizes = 2*1024*1024; //L-Bank容量 + +//********************************************************************// +//**************************** Clk And Rst ***************************// +//********************************************************************// + +//时钟、复位信号 +initial + begin + sys_clk = 1'b1 ; + sys_rst_n <= 1'b0 ; + #200 + sys_rst_n <= 1'b1 ; + end + +always #10 sys_clk = ~sys_clk; + +//rst_n:复位信号 +assign rst_n = sys_rst_n & locked; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- clk_gen_inst ------------- +clk_gen clk_gen_inst ( + .inclk0 (sys_clk ), + .areset (~sys_rst_n ), + .c0 (clk_50m ), + .c1 (clk_100m ), + .c2 (clk_100m_shift ), + + .locked (locked ) +); + +//------------- sdram_init_inst ------------- +sdram_init sdram_init_inst( + + .sys_clk (clk_100m ), + .sys_rst_n (rst_n ), + + .init_cmd (init_cmd ), + .init_ba (init_ba ), + .init_addr (init_addr ), + .init_end (init_end ) + +); + +//-------------sdram_model_plus_inst------------- +sdram_model_plus sdram_model_plus_inst( + .Dq ( ), + .Addr (init_addr ), + .Ba (init_ba ), + .Clk (clk_100m_shift ), + .Cke (1'b1 ), + .Cs_n (init_cmd[3] ), + .Ras_n (init_cmd[2] ), + .Cas_n (init_cmd[1] ), + .We_n (init_cmd[0] ), + .Dqm (2'b0 ), + .Debug (1'b1 ) + +); + +endmodule \ No newline at end of file diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_read/sdram_model_plus.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_read/sdram_model_plus.v new file mode 100644 index 0000000..4e51287 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_read/sdram_model_plus.v @@ -0,0 +1,1131 @@ +/*************************************************************************************** +ߣ +2003-08-27 V0.1 + + ڴģ鵹չܣⲿҪ¼sdram_r ,SDRAMݽᰴBank ˳damp out ļ + sdram_data.txt +*/ +//2004-03-04 ˿ ޸ԭнBANKתTXTļĸʽ +//2004-03-16 ˿ ޸SDRAM ijʼ +//2004/04/06 ˿ SDRAMIJַʽʾԱMODELSIM +//2004/04/19 ˿ ޸IJ parameter tAC = 8; +//2010/09/17 ޸sdramĴСλdqm; +/**************************************************************************************** +* +* File Name: sdram_model.V +* Version: 0.0f +* Date: July 8th, 1999 +* Model: BUS Functional +* Simulator: Model Technology (PC version 5.2e PE) +* +* Dependencies: None +* +* Author: Son P. Huynh +* Email: sphuynh@micron.com +* Phone: (208) 368-3825 +* Company: Micron Technology, Inc. +* Model: sdram_model (1Meg x 16 x 4 Banks) +* +* Description: 64Mb SDRAM Verilog model +* +* Limitation: - Doesn't check for 4096 cycle refresh +* +* Note: - Set simulator resolution to "ps" accuracy +* - Set Debug = 0 to disable $display messages +* +* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +* +* Copyright ?1998 Micron Semiconductor Products, Inc. +* All rights researved +* +* Rev Author Phone Date Changes +* ---- ---------------------------- ---------- --------------------------------------- +* 0.0f Son Huynh 208-368-3825 07/08/1999 - Fix tWR = 1 Clk + 7.5 ns (Auto) +* Micron Technology Inc. - Fix tWR = 15 ns (Manual) +* - Fix tRP (Autoprecharge to AutoRefresh) +* +* 0.0a Son Huynh 208-368-3825 05/13/1998 - First Release (from 64Mb rev 0.0e) +* Micron Technology Inc. +****************************************************************************************/ + +`timescale 1ns / 100ps + +module sdram_model_plus (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm,Debug); + + parameter addr_bits = 11; + parameter data_bits = 32; + parameter col_bits = 8; + parameter mem_sizes = 1048576*2-1;//1 Meg + + inout [data_bits - 1 : 0] Dq; + input [addr_bits - 1 : 0] Addr; + input [1 : 0] Ba; + input Clk; + input Cke; + input Cs_n; + input Ras_n; + input Cas_n; + input We_n; + input [3 : 0] Dqm; //ߵ͸8bit + //added by xzli + input Debug; + + reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];//洢 + reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes]; + + reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline + reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline + reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline + reg [3 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline + reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr; + + reg [addr_bits - 1 : 0] Mode_reg; + reg [data_bits - 1 : 0] Dq_reg, Dq_dqm; + reg [col_bits - 1 : 0] Col_temp, Burst_counter; + + reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate + reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge + + reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command + reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks) + reg Auto_precharge [0 : 3]; // RW AutoPrecharge (Bank) + reg Read_precharge [0 : 3]; // R AutoPrecharge + reg Write_precharge [0 : 3]; // W AutoPrecharge + integer Count_precharge [0 : 3]; // RW AutoPrecharge (Counter) + reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge + reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge + + reg Data_in_enable; + reg Data_out_enable; + + reg [1 : 0] Bank, Previous_bank; + reg [addr_bits - 1 : 0] Row; + reg [col_bits - 1 : 0] Col, Col_brst; + + // Internal system clock + reg CkeZ, Sys_clk; + + reg [21:0] dd; + + // Commands Decode + wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n; + wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n; + wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n; + wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n; + wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n; + wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n; + wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n; + + // Burst Length Decode + wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0]; + wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; + + // CAS Latency Decode + wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4]; + wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4]; + + // Write Burst Mode + wire Write_burst_mode = Mode_reg[9]; + + wire Debug; // Debug messages : 1 = On; 0 = Off + wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ + + reg [31:0] mem_d; + + event sdram_r,sdram_w,compare; + + + + + assign Dq = Dq_reg; // DQ buffer + + // Commands Operation + `define ACT 0 + `define NOP 1 + `define READ 2 + `define READ_A 3 + `define WRITE 4 + `define WRITE_A 5 + `define PRECH 6 + `define A_REF 7 + `define BST 8 + `define LMR 9 + +// // Timing Parameters for -75 (PC133) and CAS Latency = 2 +// parameter tAC = 8; //test 6.5 +// parameter tHZ = 7.0; +// parameter tOH = 2.7; +// parameter tMRD = 2.0; // 2 Clk Cycles +// parameter tRAS = 44.0; +// parameter tRC = 66.0; +// parameter tRCD = 20.0; +// parameter tRP = 20.0; +// parameter tRRD = 15.0; +// parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) +// parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns) + + // Timing Parameters for -7 (PC143) and CAS Latency = 3 + parameter tAC = 6.5; //test 6.5 + parameter tHZ = 5.5; + parameter tOH = 2; + parameter tMRD = 2.0; // 2 Clk Cycles + parameter tRAS = 48.0; + parameter tRC = 70.0; + parameter tRCD = 20.0; + parameter tRP = 20.0; + parameter tRRD = 14.0; + parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) + parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns) + + // Timing Check variable + integer MRD_chk; + integer WR_counter [0 : 3]; + time WR_chk [0 : 3]; + time RC_chk, RRD_chk; + time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3; + time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; + time RP_chk0, RP_chk1, RP_chk2, RP_chk3; + + integer test_file; + + //*****display the command of the sdram************************************** + + parameter Mode_Reg_Set =4'b0000; + parameter Auto_Refresh =4'b0001; + parameter Row_Active =4'b0011; + parameter Pre_Charge =4'b0010; + parameter PreCharge_All =4'b0010; + parameter Write =4'b0100; + parameter Write_Pre =4'b0100; + parameter Read =4'b0101; + parameter Read_Pre =4'b0101; + parameter Burst_Stop =4'b0110; + parameter Nop =4'b0111; + parameter Dsel =4'b1111; + + wire [3:0] sdram_control; + reg cke_temp; + reg [8*13:1] sdram_command; + + always@(posedge Clk) + cke_temp<=Cke; + + assign sdram_control={Cs_n,Ras_n,Cas_n,We_n}; + + always@(sdram_control or cke_temp) + begin + case(sdram_control) + Mode_Reg_Set: sdram_command<="Mode_Reg_Set"; + Auto_Refresh: sdram_command<="Auto_Refresh"; + Row_Active: sdram_command<="Row_Active"; + Pre_Charge: sdram_command<="Pre_Charge"; + Burst_Stop: sdram_command<="Burst_Stop"; + Dsel: sdram_command<="Dsel"; + + Write: if(cke_temp==1) + sdram_command<="Write"; + else + sdram_command<="Write_suspend"; + + Read: if(cke_temp==1) + sdram_command<="Read"; + else + sdram_command<="Read_suspend"; + + Nop: if(cke_temp==1) + sdram_command<="Nop"; + else + sdram_command<="Self_refresh"; + + default: sdram_command<="Power_down"; + endcase + end + + //***************************************************** + + initial + begin + //test_file=$fopen("test_file.txt"); + end + + initial + begin + Dq_reg = {data_bits{1'bz}}; + {Data_in_enable, Data_out_enable} = 0; + {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000; + {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000; + {WR_chk[0], WR_chk[1], WR_chk[2], WR_chk[3]} = 0; + {WR_counter[0], WR_counter[1], WR_counter[2], WR_counter[3]} = 0; + {RW_interrupt_read[0], RW_interrupt_read[1], RW_interrupt_read[2], RW_interrupt_read[3]} = 0; + {RW_interrupt_write[0], RW_interrupt_write[1], RW_interrupt_write[2], RW_interrupt_write[3]} = 0; + {MRD_chk, RC_chk, RRD_chk} = 0; + {RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0; + {RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0; + {RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0; + $timeformat (-9, 0, " ns", 12); + //$readmemh("bank0.txt", Bank0); + //$readmemh("bank1.txt", Bank1); + //$readmemh("bank2.txt", Bank2); + //$readmemh("bank3.txt", Bank3); +/* + for(dd=0;dd<=mem_sizes;dd=dd+1) + begin + Bank0[dd]=dd[data_bits - 1 : 0]; + Bank1[dd]=dd[data_bits - 1 : 0]+1; + Bank2[dd]=dd[data_bits - 1 : 0]+2; + Bank3[dd]=dd[data_bits - 1 : 0]+3; + end +*/ + initial_sdram(0); + end + + task initial_sdram; + + input data_sign; + reg [3:0] data_sign; + + for(dd=0;dd<=mem_sizes;dd=dd+1) + begin + mem_d = {data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign}; + if(data_bits==16) + begin + Bank0[dd]=mem_d[15:0]; + Bank1[dd]=mem_d[15:0]; + Bank2[dd]=mem_d[15:0]; + Bank3[dd]=mem_d[15:0]; + end + else if(data_bits==32) + begin + Bank0[dd]=mem_d[31:0]; + Bank1[dd]=mem_d[31:0]; + Bank2[dd]=mem_d[31:0]; + Bank3[dd]=mem_d[31:0]; + end + end + + endtask + + // System clock generator + always + begin + @(posedge Clk) + begin + Sys_clk = CkeZ; + CkeZ = Cke; + end + @(negedge Clk) + begin + Sys_clk = 1'b0; + end + end + + always @ (posedge Sys_clk) begin + // Internal Commamd Pipelined + Command[0] = Command[1]; + Command[1] = Command[2]; + Command[2] = Command[3]; + Command[3] = `NOP; + + Col_addr[0] = Col_addr[1]; + Col_addr[1] = Col_addr[2]; + Col_addr[2] = Col_addr[3]; + Col_addr[3] = {col_bits{1'b0}}; + + Bank_addr[0] = Bank_addr[1]; + Bank_addr[1] = Bank_addr[2]; + Bank_addr[2] = Bank_addr[3]; + Bank_addr[3] = 2'b0; + + Bank_precharge[0] = Bank_precharge[1]; + Bank_precharge[1] = Bank_precharge[2]; + Bank_precharge[2] = Bank_precharge[3]; + Bank_precharge[3] = 2'b0; + + A10_precharge[0] = A10_precharge[1]; + A10_precharge[1] = A10_precharge[2]; + A10_precharge[2] = A10_precharge[3]; + A10_precharge[3] = 1'b0; + + // Dqm pipeline for Read + Dqm_reg0 = Dqm_reg1; + Dqm_reg1 = Dqm; + + // Read or Write with Auto Precharge Counter + if (Auto_precharge[0] == 1'b1) begin + Count_precharge[0] = Count_precharge[0] + 1; + end + if (Auto_precharge[1] == 1'b1) begin + Count_precharge[1] = Count_precharge[1] + 1; + end + if (Auto_precharge[2] == 1'b1) begin + Count_precharge[2] = Count_precharge[2] + 1; + end + if (Auto_precharge[3] == 1'b1) begin + Count_precharge[3] = Count_precharge[3] + 1; + end + + // tMRD Counter + MRD_chk = MRD_chk + 1; + + // tWR Counter for Write + WR_counter[0] = WR_counter[0] + 1; + WR_counter[1] = WR_counter[1] + 1; + WR_counter[2] = WR_counter[2] + 1; + WR_counter[3] = WR_counter[3] + 1; + + // Auto Refresh + if (Aref_enable == 1'b1) begin + if (Debug) $display ("at time %t AREF : Auto Refresh", $time); + // Auto Refresh to Auto Refresh + if (($time - RC_chk < tRC)&&Debug) begin + $display ("at time %t ERROR: tRC violation during Auto Refresh", $time); + end + // Precharge to Auto Refresh + if (($time - RP_chk0 < tRP || $time - RP_chk1 < tRP || $time - RP_chk2 < tRP || $time - RP_chk3 < tRP)&&Debug) begin + $display ("at time %t ERROR: tRP violation during Auto Refresh", $time); + end + // Precharge to Refresh + if (Pc_b0 == 1'b0 || Pc_b1 == 1'b0 || Pc_b2 == 1'b0 || Pc_b3 == 1'b0) begin + $display ("at time %t ERROR: All banks must be Precharge before Auto Refresh", $time); + end + // Record Current tRC time + RC_chk = $time; + end + + // Load Mode Register + if (Mode_reg_enable == 1'b1) begin + // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode + if (Pc_b0 == 1'b1 && Pc_b1 == 1'b1 && Pc_b2 == 1'b1 && Pc_b3 == 1'b1) begin + Mode_reg = Addr; + if (Debug) begin + $display ("at time %t LMR : Load Mode Register", $time); + // CAS Latency + if (Addr[6 : 4] == 3'b010) + $display (" CAS Latency = 2"); + else if (Addr[6 : 4] == 3'b011) + $display (" CAS Latency = 3"); + else + $display (" CAS Latency = Reserved"); + // Burst Length + if (Addr[2 : 0] == 3'b000) + $display (" Burst Length = 1"); + else if (Addr[2 : 0] == 3'b001) + $display (" Burst Length = 2"); + else if (Addr[2 : 0] == 3'b010) + $display (" Burst Length = 4"); + else if (Addr[2 : 0] == 3'b011) + $display (" Burst Length = 8"); + else if (Addr[3 : 0] == 4'b0111) + $display (" Burst Length = Full"); + else + $display (" Burst Length = Reserved"); + // Burst Type + if (Addr[3] == 1'b0) + $display (" Burst Type = Sequential"); + else if (Addr[3] == 1'b1) + $display (" Burst Type = Interleaved"); + else + $display (" Burst Type = Reserved"); + // Write Burst Mode + if (Addr[9] == 1'b0) + $display (" Write Burst Mode = Programmed Burst Length"); + else if (Addr[9] == 1'b1) + $display (" Write Burst Mode = Single Location Access"); + else + $display (" Write Burst Mode = Reserved"); + end + end else begin + $display ("at time %t ERROR: all banks must be Precharge before Load Mode Register", $time); + end + // REF to LMR + if ($time - RC_chk < tRC) begin + $display ("at time %t ERROR: tRC violation during Load Mode Register", $time); + end + // LMR to LMR + if (MRD_chk < tMRD) begin + $display ("at time %t ERROR: tMRD violation during Load Mode Register", $time); + end + MRD_chk = 0; + end + + // Active Block (Latch Bank Address and Row Address) + if (Active_enable == 1'b1) begin + if (Ba == 2'b00 && Pc_b0 == 1'b1) begin + {Act_b0, Pc_b0} = 2'b10; + B0_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk0 = $time; + RAS_chk0 = $time; + if (Debug) $display ("at time %t ACT : Bank = 0 Row = %d", $time, Addr); + // Precharge to Activate Bank 0 + if ($time - RP_chk0 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 0", $time); + end + end else if (Ba == 2'b01 && Pc_b1 == 1'b1) begin + {Act_b1, Pc_b1} = 2'b10; + B1_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk1 = $time; + RAS_chk1 = $time; + if (Debug) $display ("at time %t ACT : Bank = 1 Row = %d", $time, Addr); + // Precharge to Activate Bank 1 + if ($time - RP_chk1 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 1", $time); + end + end else if (Ba == 2'b10 && Pc_b2 == 1'b1) begin + {Act_b2, Pc_b2} = 2'b10; + B2_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk2 = $time; + RAS_chk2 = $time; + if (Debug) $display ("at time %t ACT : Bank = 2 Row = %d", $time, Addr); + // Precharge to Activate Bank 2 + if ($time - RP_chk2 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 2", $time); + end + end else if (Ba == 2'b11 && Pc_b3 == 1'b1) begin + {Act_b3, Pc_b3} = 2'b10; + B3_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk3 = $time; + RAS_chk3 = $time; + if (Debug) $display ("at time %t ACT : Bank = 3 Row = %d", $time, Addr); + // Precharge to Activate Bank 3 + if ($time - RP_chk3 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 3", $time); + end + end else if (Ba == 2'b00 && Pc_b0 == 1'b0) begin + $display ("at time %t ERROR: Bank 0 is not Precharged.", $time); + end else if (Ba == 2'b01 && Pc_b1 == 1'b0) begin + $display ("at time %t ERROR: Bank 1 is not Precharged.", $time); + end else if (Ba == 2'b10 && Pc_b2 == 1'b0) begin + $display ("at time %t ERROR: Bank 2 is not Precharged.", $time); + end else if (Ba == 2'b11 && Pc_b3 == 1'b0) begin + $display ("at time %t ERROR: Bank 3 is not Precharged.", $time); + end + // Active Bank A to Active Bank B + if ((Previous_bank != Ba) && ($time - RRD_chk < tRRD)) begin + $display ("at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba); + end + // Load Mode Register to Active + if (MRD_chk < tMRD ) begin + $display ("at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba); + end + // Auto Refresh to Activate + if (($time - RC_chk < tRC)&&Debug) begin + $display ("at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba); + end + // Record variables for checking violation + RRD_chk = $time; + Previous_bank = Ba; + end + + // Precharge Block + if (Prech_enable == 1'b1) begin + if (Addr[10] == 1'b1) begin + {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b1111; + {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000; + RP_chk0 = $time; + RP_chk1 = $time; + RP_chk2 = $time; + RP_chk3 = $time; + if (Debug) $display ("at time %t PRE : Bank = ALL",$time); + // Activate to Precharge all banks + if (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) || + ($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin + $display ("at time %t ERROR: tRAS violation during Precharge all bank", $time); + end + // tWR violation check for write + if (($time - WR_chk[0] < tWRp) || ($time - WR_chk[1] < tWRp) || + ($time - WR_chk[2] < tWRp) || ($time - WR_chk[3] < tWRp)) begin + $display ("at time %t ERROR: tWR violation during Precharge all bank", $time); + end + end else if (Addr[10] == 1'b0) begin + if (Ba == 2'b00) begin + {Pc_b0, Act_b0} = 2'b10; + RP_chk0 = $time; + if (Debug) $display ("at time %t PRE : Bank = 0",$time); + // Activate to Precharge Bank 0 + if ($time - RAS_chk0 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 0", $time); + end + end else if (Ba == 2'b01) begin + {Pc_b1, Act_b1} = 2'b10; + RP_chk1 = $time; + if (Debug) $display ("at time %t PRE : Bank = 1",$time); + // Activate to Precharge Bank 1 + if ($time - RAS_chk1 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 1", $time); + end + end else if (Ba == 2'b10) begin + {Pc_b2, Act_b2} = 2'b10; + RP_chk2 = $time; + if (Debug) $display ("at time %t PRE : Bank = 2",$time); + // Activate to Precharge Bank 2 + if ($time - RAS_chk2 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 2", $time); + end + end else if (Ba == 2'b11) begin + {Pc_b3, Act_b3} = 2'b10; + RP_chk3 = $time; + if (Debug) $display ("at time %t PRE : Bank = 3",$time); + // Activate to Precharge Bank 3 + if ($time - RAS_chk3 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 3", $time); + end + end + // tWR violation check for write + if ($time - WR_chk[Ba] < tWRp) begin + $display ("at time %t ERROR: tWR violation during Precharge bank %d", $time, Ba); + end + end + // Terminate a Write Immediately (if same bank or all banks) + if (Data_in_enable == 1'b1 && (Bank == Ba || Addr[10] == 1'b1)) begin + Data_in_enable = 1'b0; + end + // Precharge Command Pipeline for Read + if (Cas_latency_3 == 1'b1) begin + Command[2] = `PRECH; + Bank_precharge[2] = Ba; + A10_precharge[2] = Addr[10]; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `PRECH; + Bank_precharge[1] = Ba; + A10_precharge[1] = Addr[10]; + end + end + + // Burst terminate + if (Burst_term == 1'b1) begin + // Terminate a Write Immediately + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + // Terminate a Read Depend on CAS Latency + if (Cas_latency_3 == 1'b1) begin + Command[2] = `BST; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `BST; + end + if (Debug) $display ("at time %t BST : Burst Terminate",$time); + end + + // Read, Write, Column Latch + if (Read_enable == 1'b1 || Write_enable == 1'b1) begin + // Check to see if bank is open (ACT) + if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || + (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin + $display("at time %t ERROR: Cannot Read or Write - Bank %d is not Activated", $time, Ba); + end + // Activate to Read or Write + if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 0", $time); + if ((Ba == 2'b01) && ($time - RCD_chk1 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 1", $time); + if ((Ba == 2'b10) && ($time - RCD_chk2 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 2", $time); + if ((Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 3", $time); + // Read Command + if (Read_enable == 1'b1) begin + // CAS Latency pipeline + if (Cas_latency_3 == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[2] = `READ_A; + end else begin + Command[2] = `READ; + end + Col_addr[2] = Addr; + Bank_addr[2] = Ba; + end else if (Cas_latency_2 == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[1] = `READ_A; + end else begin + Command[1] = `READ; + end + Col_addr[1] = Addr; + Bank_addr[1] = Ba; + end + + // Read interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Write Command + end else if (Write_enable == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[0] = `WRITE_A; + end else begin + Command[0] = `WRITE; + end + Col_addr[0] = Addr; + Bank_addr[0] = Ba; + + // Write interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Write interrupt Read (terminate Read immediately) + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + // Interrupting a Write with Autoprecharge + if (Auto_precharge[Bank] == 1'b1 && Write_precharge[Bank] == 1'b1) begin + RW_interrupt_write[Bank] = 1'b1; + if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, Bank); + end + + // Interrupting a Read with Autoprecharge + if (Auto_precharge[Bank] == 1'b1 && Read_precharge[Bank] == 1'b1) begin + RW_interrupt_read[Bank] = 1'b1; + if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, Bank); + end + + // Read or Write with Auto Precharge + if (Addr[10] == 1'b1) begin + Auto_precharge[Ba] = 1'b1; + Count_precharge[Ba] = 0; + if (Read_enable == 1'b1) begin + Read_precharge[Ba] = 1'b1; + end else if (Write_enable == 1'b1) begin + Write_precharge[Ba] = 1'b1; + end + end + end + + // Read with Auto Precharge Calculation + // The device start internal precharge: + // 1. CAS Latency - 1 cycles before last burst + // and 2. Meet minimum tRAS requirement + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 2 + ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 1 + (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) || + (RW_interrupt_read[0] == 1'b1)) begin // Case 3 + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + Auto_precharge[0] = 1'b0; + Read_precharge[0] = 1'b0; + RW_interrupt_read[0] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) || + (RW_interrupt_read[1] == 1'b1)) begin + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + Auto_precharge[1] = 1'b0; + Read_precharge[1] = 1'b0; + RW_interrupt_read[1] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) || + (RW_interrupt_read[2] == 1'b1)) begin + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + Auto_precharge[2] = 1'b0; + Read_precharge[2] = 1'b0; + RW_interrupt_read[2] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) || + (RW_interrupt_read[3] == 1'b1)) begin + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + Auto_precharge[3] = 1'b0; + Read_precharge[3] = 1'b0; + RW_interrupt_read[3] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + + // Internal Precharge or Bst + if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks + if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + end else if (Command[0] == `BST) begin // BST terminate a read to current bank + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + if (Data_out_enable == 1'b0) begin + Dq_reg <= #tOH {data_bits{1'bz}}; + end + + // Detect Read or Write command + if (Command[0] == `READ || Command[0] == `READ_A) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + if (Bank_addr[0] == 2'b00) begin + Row = B0_row_addr; + end else if (Bank_addr[0] == 2'b01) begin + Row = B1_row_addr; + end else if (Bank_addr[0] == 2'b10) begin + Row = B2_row_addr; + end else if (Bank_addr[0] == 2'b11) begin + Row = B3_row_addr; + end + Burst_counter = 0; + Data_in_enable = 1'b0; + Data_out_enable = 1'b1; + end else if (Command[0] == `WRITE || Command[0] == `WRITE_A) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + if (Bank_addr[0] == 2'b00) begin + Row = B0_row_addr; + end else if (Bank_addr[0] == 2'b01) begin + Row = B1_row_addr; + end else if (Bank_addr[0] == 2'b10) begin + Row = B2_row_addr; + end else if (Bank_addr[0] == 2'b11) begin + Row = B3_row_addr; + end + Burst_counter = 0; + Data_in_enable = 1'b1; + Data_out_enable = 1'b0; + end + + // DQ buffer (Driver/Receiver) + if (Data_in_enable == 1'b1) begin // Writing Data to Memory + // Array buffer + if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}]; + if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}]; + if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}]; + if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}]; + // Dqm operation + if (Dqm[0] == 1'b0) Dq_dqm [ 7 : 0] = Dq [ 7 : 0]; + if (Dqm[1] == 1'b0) Dq_dqm [15 : 8] = Dq [15 : 8]; + //if (Dqm[2] == 1'b0) Dq_dqm [23 : 16] = Dq [23 : 16]; + // if (Dqm[3] == 1'b0) Dq_dqm [31 : 24] = Dq [31 : 24]; + // Write to memory + if (Bank == 2'b00) Bank0 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b01) Bank1 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b10) Bank2 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b11) Bank3 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b11 && Row==10'h3 && Col[7:4]==4'h4) + $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + //$fdisplay(test_file,"bank:%h row:%h col:%h write:%h",Bank,Row,Col,Dq_dqm); + // Output result + if (Dqm == 4'b1111) begin + if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end else begin + if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_dqm, Dqm); + // Record tWR time and reset counter + WR_chk [Bank] = $time; + WR_counter [Bank] = 0; + end + // Advance burst counter subroutine + #tHZ Burst; + end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory + //$display("%h , %h, %h",Bank0,Row,Col); + // Array buffer + if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}]; + if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}]; + if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}]; + if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}]; + + // Dqm operation + if (Dqm_reg0[0] == 1'b1) Dq_dqm [ 7 : 0] = 8'bz; + if (Dqm_reg0[1] == 1'b1) Dq_dqm [15 : 8] = 8'bz; + if (Dqm_reg0[2] == 1'b1) Dq_dqm [23 : 16] = 8'bz; + if (Dqm_reg0[3] == 1'b1) Dq_dqm [31 : 24] = 8'bz; + // Display result + Dq_reg [data_bits - 1 : 0] = #tAC Dq_dqm [data_bits - 1 : 0]; + if (Dqm_reg0 == 4'b1111) begin + if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end else begin + if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_reg, Dqm_reg0); + end + // Advance burst counter subroutine + Burst; + end + end + + // Write with Auto Precharge Calculation + // The device start internal precharge: + // 1. tWR Clock after last burst + // and 2. Meet minimum tRAS requirement + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + always @ (WR_counter[0]) begin + if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 2 + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 1 + (Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) || + (RW_interrupt_write[0] == 1'b1 && WR_counter[0] >= 2)) begin // Case 3 (stop count when interrupt) + Auto_precharge[0] = 1'b0; + Write_precharge[0] = 1'b0; + RW_interrupt_write[0] = 1'b0; + #tWRa; // Wait for tWR + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + end + always @ (WR_counter[1]) begin + if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) || + (RW_interrupt_write[1] == 1'b1 && WR_counter[1] >= 2)) begin + Auto_precharge[1] = 1'b0; + Write_precharge[1] = 1'b0; + RW_interrupt_write[1] = 1'b0; + #tWRa; // Wait for tWR + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + end + always @ (WR_counter[2]) begin + if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) || + (RW_interrupt_write[2] == 1'b1 && WR_counter[2] >= 2)) begin + Auto_precharge[2] = 1'b0; + Write_precharge[2] = 1'b0; + RW_interrupt_write[2] = 1'b0; + #tWRa; // Wait for tWR + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + end + always @ (WR_counter[3]) begin + if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) || + (RW_interrupt_write[3] == 1'b1 && WR_counter[3] >= 2)) begin + Auto_precharge[3] = 1'b0; + Write_precharge[3] = 1'b0; + RW_interrupt_write[3] = 1'b0; + #tWRa; // Wait for tWR + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + end + + task Burst; + begin + // Advance Burst Counter + Burst_counter = Burst_counter + 1; + + // Burst Type + if (Mode_reg[3] == 1'b0) begin // Sequential Burst + Col_temp = Col + 1; + end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst + Col_temp[2] = Burst_counter[2] ^ Col_brst[2]; + Col_temp[1] = Burst_counter[1] ^ Col_brst[1]; + Col_temp[0] = Burst_counter[0] ^ Col_brst[0]; + end + + // Burst Length + if (Burst_length_2) begin // Burst Length = 2 + Col [0] = Col_temp [0]; + end else if (Burst_length_4) begin // Burst Length = 4 + Col [1 : 0] = Col_temp [1 : 0]; + end else if (Burst_length_8) begin // Burst Length = 8 + Col [2 : 0] = Col_temp [2 : 0]; + end else begin // Burst Length = FULL + Col = Col_temp; + end + + // Burst Read Single Write + if (Write_burst_mode == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Data Counter + if (Burst_length_1 == 1'b1) begin + if (Burst_counter >= 1) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_2 == 1'b1) begin + if (Burst_counter >= 2) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_4 == 1'b1) begin + if (Burst_counter >= 4) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_8 == 1'b1) begin + if (Burst_counter >= 8) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end + end + endtask + + //**********************SDRAMڵֱⲿļ*******************************// + +/* + integer sdram_data,ind; + + + always@(sdram_r) + begin + sdram_data=$fopen("sdram_data.txt"); + $display("Sdram dampout begin ",sdram_data); +// $fdisplay(sdram_data,"Bank0"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank0[ind]); +// $fdisplay(sdram_data,"Bank1"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank1[ind]); +// $fdisplay(sdram_data,"Bank2"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank2[ind]); +// $fdisplay(sdram_data,"Bank3"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank3[ind]); + + $fclose("sdram_data.txt"); + //->compare; + end +*/ + integer sdram_data,sdram_mem; + reg [23:0] aa,cc; + reg [18:0] bb,ee; + + always@(sdram_r) + begin + $display("Sdram dampout begin ",$realtime); + sdram_data=$fopen("sdram_data.txt"); + for(aa=0;aa<4*(mem_sizes+1);aa=aa+1) + begin + bb=aa[18:0]; + if(aa<=mem_sizes) + $fdisplay(sdram_data,"%0d %0h",aa,Bank0[bb]); + else if(aa<=2*mem_sizes+1) + $fdisplay(sdram_data,"%0d %0h",aa,Bank1[bb]); + else if(aa<=3*mem_sizes+2) + $fdisplay(sdram_data,"%0d %0h",aa,Bank2[bb]); + else + $fdisplay(sdram_data,"%0d %0h",aa,Bank3[bb]); + end + $fclose("sdram_data.txt"); + + sdram_mem=$fopen("sdram_mem.txt"); + for(cc=0;cc<4*(mem_sizes+1);cc=cc+1) + begin + ee=cc[18:0]; + if(cc<=mem_sizes) + $fdisplay(sdram_mem,"%0h",Bank0[ee]); + else if(cc<=2*mem_sizes+1) + $fdisplay(sdram_mem,"%0h",Bank1[ee]); + else if(cc<=3*mem_sizes+2) + $fdisplay(sdram_mem,"%0h",Bank2[ee]); + else + $fdisplay(sdram_mem,"%0h",Bank3[ee]); + end + $fclose("sdram_mem.txt"); + + end + + + +// // Timing Parameters for -75 (PC133) and CAS Latency = 2 +// specify +// specparam +//// tAH = 0.8, // Addr, Ba Hold Time +//// tAS = 1.5, // Addr, Ba Setup Time +//// tCH = 2.5, // Clock High-Level Width +//// tCL = 2.5, // Clock Low-Level Width +////// tCK = 10.0, // Clock Cycle Time 100mhz +////// tCK = 7.5, // Clock Cycle Time 133mhz +//// tCK = 7, // Clock Cycle Time 143mhz +//// tDH = 0.8, // Data-in Hold Time +//// tDS = 1.5, // Data-in Setup Time +//// tCKH = 0.8, // CKE Hold Time +//// tCKS = 1.5, // CKE Setup Time +//// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time +//// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time +// tAH = 1, // Addr, Ba Hold Time +// tAS = 1.5, // Addr, Ba Setup Time +// tCH = 1, // Clock High-Level Width +// tCL = 3, // Clock Low-Level Width +//// tCK = 10.0, // Clock Cycle Time 100mhz +//// tCK = 7.5, // Clock Cycle Time 133mhz +// tCK = 7, // Clock Cycle Time 143mhz +// tDH = 1, // Data-in Hold Time +// tDS = 2, // Data-in Setup Time +// tCKH = 1, // CKE Hold Time +// tCKS = 2, // CKE Setup Time +// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time +// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time +// $width (posedge Clk, tCH); +// $width (negedge Clk, tCL); +// $period (negedge Clk, tCK); +// $period (posedge Clk, tCK); +// $setuphold(posedge Clk, Cke, tCKS, tCKH); +// $setuphold(posedge Clk, Cs_n, tCMS, tCMH); +// $setuphold(posedge Clk, Cas_n, tCMS, tCMH); +// $setuphold(posedge Clk, Ras_n, tCMS, tCMH); +// $setuphold(posedge Clk, We_n, tCMS, tCMH); +// $setuphold(posedge Clk, Addr, tAS, tAH); +// $setuphold(posedge Clk, Ba, tAS, tAH); +// $setuphold(posedge Clk, Dqm, tCMS, tCMH); +// $setuphold(posedge Dq_chk, Dq, tDS, tDH); +// endspecify + +endmodule + diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_read/tb_sdram_read.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_read/tb_sdram_read.v new file mode 100644 index 0000000..1420491 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_read/tb_sdram_read.v @@ -0,0 +1,226 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : tb_sdram_read +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SDRAM数据读模块仿真 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module tb_sdram_read(); + +//********************************************************************// +//****************** Internal Signal and Defparam ********************// +//********************************************************************// + +//wire define +//clk_gen +wire clk_50m ; //PLL输出50M时钟 +wire clk_100m ; //PLL输出100M时钟 +wire clk_100m_shift ; //PLL输出100M时钟,相位偏移-30deg +wire locked ; //PLL时钟锁定信号 +wire rst_n ; //复位信号,低有效 +//sdram_init +wire [3:0] init_cmd ; //初始化阶段指令 +wire [1:0] init_ba ; //初始化阶段L-Bank地址 +wire [12:0] init_addr ; //初始化阶段地址总线 +wire init_end ; //初始化完成信号 +//sdram_write +wire [12:0] write_addr ; //数据写阶段地址总线 +wire [1:0] write_ba ; //数据写阶段L-Bank地址 +wire [3:0] write_cmd ; //数据写阶段指令 +wire [15:0] wr_sdram_data ; //数据写阶段写入SDRAM数据 +wire wr_sdram_en ; //数据写阶段写数据有效使能信号 +wire wr_end ; //数据写阶段一次突发写结束 +//sdram_read +wire [12:0] read_addr ; //数据读阶段地址总线 +wire [1:0] read_ba ; //数据读阶段L-Bank地址 +wire [3:0] read_cmd ; //数据读阶段指令 +wire [15:0] sdram_data_out ; //数据读阶段写入SDRAM数据 +wire rd_end ; //数据读阶段一次突发写结束 +wire sdram_wr_ack ; //数据写阶段写响应 +//sdram_addr +wire [12:0] sdram_addr ; //SDRAM地址总线 +wire [1:0] sdram_ba ; //SDRAML-Bank地址 +wire [3:0] sdram_cmd ; //SDRAM指令 +wire [15:0] sdram_dq ; //SDRAM数据总线 + +wire [12:0] w_r_addr ; //数据读阶段地址总线 +wire [1:0] w_r_ba ; //数据读阶段L-Bank地址 +wire [3:0] w_r_cmd ; //数据读阶段指令 + +//reg define +reg sys_clk ; //系统时钟 +reg sys_rst_n ; //复位信号 +reg wr_en ; //写使能 +reg [15:0] wr_data_in ; //写数据 +reg rd_en ; //读使能 + + +//defparam +//重定义仿真模型中的相关参数 +defparam sdram_model_plus_inst.addr_bits = 13; //地址位宽 +defparam sdram_model_plus_inst.data_bits = 16; //数据位宽 +defparam sdram_model_plus_inst.col_bits = 9; //列地址位宽 +defparam sdram_model_plus_inst.mem_sizes = 2*1024*1024; //L-Bank容量 + +//********************************************************************// +//**************************** Clk And Rst ***************************// +//********************************************************************// + +//时钟、复位信号 +initial + begin + sys_clk = 1'b1 ; + sys_rst_n <= 1'b0 ; + #200 + sys_rst_n <= 1'b1 ; + end + +always #10 sys_clk = ~sys_clk; + +//rst_n:复位信号 +assign rst_n = sys_rst_n & locked; + +//wr_en：写数据使能 +always@(posedge clk_100m or negedge rst_n) + if(rst_n == 1'b0) + wr_en <= 1'b1; + else if(wr_end == 1'b1) + wr_en <= 1'b0; + else + wr_en <= wr_en; + +//wr_data_in:写数据 +always@(posedge clk_100m or negedge rst_n) + if(rst_n == 1'b0) + wr_data_in <= 16'd0; + else if(wr_data_in == 16'd10) + wr_data_in <= 16'd0; + else if(sdram_wr_ack == 1'b1) + wr_data_in <= wr_data_in + 1'b1; + else + wr_data_in <= wr_data_in; + +//rd_en:读数据使能 +always@(posedge clk_100m or negedge rst_n) + if(rst_n == 1'b0) + rd_en <= 1'b0; + else if(rd_end == 1'b1) + rd_en <= 1'b0; + else if(wr_en == 1'b0) + rd_en <= 1'b1; + else + rd_en <= rd_en; + +//sdram_cmd,sdram_ba,sdram_addr +assign sdram_cmd = (init_end == 1'b1) ? w_r_cmd : init_cmd; +assign sdram_ba = (init_end == 1'b1) ? w_r_ba : init_ba; +assign sdram_addr = (init_end == 1'b1) ? w_r_addr : init_addr; + +//w_r_cmd,w_r_ba,w_r_addr +assign w_r_cmd = (wr_en == 1'b1) ? write_cmd : read_cmd; +assign w_r_ba = (wr_en == 1'b1) ? write_ba : read_ba; +assign w_r_addr = (wr_en == 1'b1) ? write_addr : read_addr; + +//wr_sdram_data +assign sdram_dq = (wr_sdram_en == 1'b1) ? wr_sdram_data : 16'hz; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- clk_gen_inst ------------- +clk_gen clk_gen_inst ( + .inclk0 (sys_clk ), + .areset (~sys_rst_n ), + .c0 (clk_50m ), + .c1 (clk_100m ), + .c2 (clk_100m_shift ), + + .locked (locked ) +); + +//------------- sdram_init_inst ------------- +sdram_init sdram_init_inst( + + .sys_clk (clk_100m ), + .sys_rst_n (rst_n ), + + .init_cmd (init_cmd ), + .init_ba (init_ba ), + .init_addr (init_addr ), + .init_end (init_end ) + +); + +//------------- sdram_write_inst ------------- +sdram_write sdram_write_inst( + + .sys_clk (clk_100m ), + .sys_rst_n (rst_n ), + .init_end (init_end ), + .wr_en (wr_en ), + + .wr_addr (24'h000_000 ), + .wr_data (wr_data_in ), + .wr_burst_len (10'd10 ), + + .wr_ack (sdram_wr_ack ), + .wr_end (wr_end ), + .write_cmd (write_cmd ), + .write_ba (write_ba ), + .write_addr (write_addr ), + .wr_sdram_en (wr_sdram_en ), + .wr_sdram_data (wr_sdram_data ) + +); + +//------------- sdram_read_inst ------------- +sdram_read sdram_read_inst( + + .sys_clk (clk_100m ), + .sys_rst_n (rst_n ), + .init_end (init_end ), + .rd_en (rd_en ), + + .rd_addr (24'h000_000 ), + .rd_data (sdram_dq ), + .rd_burst_len (10'd10 ), + + .rd_ack ( ), + .rd_end (rd_end ), + .read_cmd (read_cmd ), + .read_ba (read_ba ), + .read_addr (read_addr ), + .rd_sdram_data (sdram_data_out ) + +); + +//-------------sdram_model_plus_inst------------- +sdram_model_plus sdram_model_plus_inst( + .Dq (sdram_dq ), + .Addr (sdram_addr ), + .Ba (sdram_ba ), + .Clk (clk_100m_shift ), + .Cke (1'b1 ), + .Cs_n (sdram_cmd[3] ), + .Ras_n (sdram_cmd[2] ), + .Cas_n (sdram_cmd[1] ), + .We_n (sdram_cmd[0] ), + .Dqm (2'b0 ), + .Debug (1'b1 ) + +); + +endmodule \ No newline at end of file diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_top/sdram_model_plus.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_top/sdram_model_plus.v new file mode 100644 index 0000000..4e51287 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_top/sdram_model_plus.v @@ -0,0 +1,1131 @@ +/*************************************************************************************** +ߣ +2003-08-27 V0.1 + + ڴģ鵹չܣⲿҪ¼sdram_r ,SDRAMݽᰴBank ˳damp out ļ + sdram_data.txt +*/ +//2004-03-04 ˿ ޸ԭнBANKתTXTļĸʽ +//2004-03-16 ˿ ޸SDRAM ijʼ +//2004/04/06 ˿ SDRAMIJַʽʾԱMODELSIM +//2004/04/19 ˿ ޸IJ parameter tAC = 8; +//2010/09/17 ޸sdramĴСλdqm; +/**************************************************************************************** +* +* File Name: sdram_model.V +* Version: 0.0f +* Date: July 8th, 1999 +* Model: BUS Functional +* Simulator: Model Technology (PC version 5.2e PE) +* +* Dependencies: None +* +* Author: Son P. Huynh +* Email: sphuynh@micron.com +* Phone: (208) 368-3825 +* Company: Micron Technology, Inc. +* Model: sdram_model (1Meg x 16 x 4 Banks) +* +* Description: 64Mb SDRAM Verilog model +* +* Limitation: - Doesn't check for 4096 cycle refresh +* +* Note: - Set simulator resolution to "ps" accuracy +* - Set Debug = 0 to disable $display messages +* +* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +* +* Copyright ?1998 Micron Semiconductor Products, Inc. +* All rights researved +* +* Rev Author Phone Date Changes +* ---- ---------------------------- ---------- --------------------------------------- +* 0.0f Son Huynh 208-368-3825 07/08/1999 - Fix tWR = 1 Clk + 7.5 ns (Auto) +* Micron Technology Inc. - Fix tWR = 15 ns (Manual) +* - Fix tRP (Autoprecharge to AutoRefresh) +* +* 0.0a Son Huynh 208-368-3825 05/13/1998 - First Release (from 64Mb rev 0.0e) +* Micron Technology Inc. +****************************************************************************************/ + +`timescale 1ns / 100ps + +module sdram_model_plus (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm,Debug); + + parameter addr_bits = 11; + parameter data_bits = 32; + parameter col_bits = 8; + parameter mem_sizes = 1048576*2-1;//1 Meg + + inout [data_bits - 1 : 0] Dq; + input [addr_bits - 1 : 0] Addr; + input [1 : 0] Ba; + input Clk; + input Cke; + input Cs_n; + input Ras_n; + input Cas_n; + input We_n; + input [3 : 0] Dqm; //ߵ͸8bit + //added by xzli + input Debug; + + reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];//洢 + reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes]; + + reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline + reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline + reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline + reg [3 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline + reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr; + + reg [addr_bits - 1 : 0] Mode_reg; + reg [data_bits - 1 : 0] Dq_reg, Dq_dqm; + reg [col_bits - 1 : 0] Col_temp, Burst_counter; + + reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate + reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge + + reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command + reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks) + reg Auto_precharge [0 : 3]; // RW AutoPrecharge (Bank) + reg Read_precharge [0 : 3]; // R AutoPrecharge + reg Write_precharge [0 : 3]; // W AutoPrecharge + integer Count_precharge [0 : 3]; // RW AutoPrecharge (Counter) + reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge + reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge + + reg Data_in_enable; + reg Data_out_enable; + + reg [1 : 0] Bank, Previous_bank; + reg [addr_bits - 1 : 0] Row; + reg [col_bits - 1 : 0] Col, Col_brst; + + // Internal system clock + reg CkeZ, Sys_clk; + + reg [21:0] dd; + + // Commands Decode + wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n; + wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n; + wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n; + wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n; + wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n; + wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n; + wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n; + + // Burst Length Decode + wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0]; + wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; + + // CAS Latency Decode + wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4]; + wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4]; + + // Write Burst Mode + wire Write_burst_mode = Mode_reg[9]; + + wire Debug; // Debug messages : 1 = On; 0 = Off + wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ + + reg [31:0] mem_d; + + event sdram_r,sdram_w,compare; + + + + + assign Dq = Dq_reg; // DQ buffer + + // Commands Operation + `define ACT 0 + `define NOP 1 + `define READ 2 + `define READ_A 3 + `define WRITE 4 + `define WRITE_A 5 + `define PRECH 6 + `define A_REF 7 + `define BST 8 + `define LMR 9 + +// // Timing Parameters for -75 (PC133) and CAS Latency = 2 +// parameter tAC = 8; //test 6.5 +// parameter tHZ = 7.0; +// parameter tOH = 2.7; +// parameter tMRD = 2.0; // 2 Clk Cycles +// parameter tRAS = 44.0; +// parameter tRC = 66.0; +// parameter tRCD = 20.0; +// parameter tRP = 20.0; +// parameter tRRD = 15.0; +// parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) +// parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns) + + // Timing Parameters for -7 (PC143) and CAS Latency = 3 + parameter tAC = 6.5; //test 6.5 + parameter tHZ = 5.5; + parameter tOH = 2; + parameter tMRD = 2.0; // 2 Clk Cycles + parameter tRAS = 48.0; + parameter tRC = 70.0; + parameter tRCD = 20.0; + parameter tRP = 20.0; + parameter tRRD = 14.0; + parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) + parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns) + + // Timing Check variable + integer MRD_chk; + integer WR_counter [0 : 3]; + time WR_chk [0 : 3]; + time RC_chk, RRD_chk; + time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3; + time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; + time RP_chk0, RP_chk1, RP_chk2, RP_chk3; + + integer test_file; + + //*****display the command of the sdram************************************** + + parameter Mode_Reg_Set =4'b0000; + parameter Auto_Refresh =4'b0001; + parameter Row_Active =4'b0011; + parameter Pre_Charge =4'b0010; + parameter PreCharge_All =4'b0010; + parameter Write =4'b0100; + parameter Write_Pre =4'b0100; + parameter Read =4'b0101; + parameter Read_Pre =4'b0101; + parameter Burst_Stop =4'b0110; + parameter Nop =4'b0111; + parameter Dsel =4'b1111; + + wire [3:0] sdram_control; + reg cke_temp; + reg [8*13:1] sdram_command; + + always@(posedge Clk) + cke_temp<=Cke; + + assign sdram_control={Cs_n,Ras_n,Cas_n,We_n}; + + always@(sdram_control or cke_temp) + begin + case(sdram_control) + Mode_Reg_Set: sdram_command<="Mode_Reg_Set"; + Auto_Refresh: sdram_command<="Auto_Refresh"; + Row_Active: sdram_command<="Row_Active"; + Pre_Charge: sdram_command<="Pre_Charge"; + Burst_Stop: sdram_command<="Burst_Stop"; + Dsel: sdram_command<="Dsel"; + + Write: if(cke_temp==1) + sdram_command<="Write"; + else + sdram_command<="Write_suspend"; + + Read: if(cke_temp==1) + sdram_command<="Read"; + else + sdram_command<="Read_suspend"; + + Nop: if(cke_temp==1) + sdram_command<="Nop"; + else + sdram_command<="Self_refresh"; + + default: sdram_command<="Power_down"; + endcase + end + + //***************************************************** + + initial + begin + //test_file=$fopen("test_file.txt"); + end + + initial + begin + Dq_reg = {data_bits{1'bz}}; + {Data_in_enable, Data_out_enable} = 0; + {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000; + {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000; + {WR_chk[0], WR_chk[1], WR_chk[2], WR_chk[3]} = 0; + {WR_counter[0], WR_counter[1], WR_counter[2], WR_counter[3]} = 0; + {RW_interrupt_read[0], RW_interrupt_read[1], RW_interrupt_read[2], RW_interrupt_read[3]} = 0; + {RW_interrupt_write[0], RW_interrupt_write[1], RW_interrupt_write[2], RW_interrupt_write[3]} = 0; + {MRD_chk, RC_chk, RRD_chk} = 0; + {RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0; + {RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0; + {RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0; + $timeformat (-9, 0, " ns", 12); + //$readmemh("bank0.txt", Bank0); + //$readmemh("bank1.txt", Bank1); + //$readmemh("bank2.txt", Bank2); + //$readmemh("bank3.txt", Bank3); +/* + for(dd=0;dd<=mem_sizes;dd=dd+1) + begin + Bank0[dd]=dd[data_bits - 1 : 0]; + Bank1[dd]=dd[data_bits - 1 : 0]+1; + Bank2[dd]=dd[data_bits - 1 : 0]+2; + Bank3[dd]=dd[data_bits - 1 : 0]+3; + end +*/ + initial_sdram(0); + end + + task initial_sdram; + + input data_sign; + reg [3:0] data_sign; + + for(dd=0;dd<=mem_sizes;dd=dd+1) + begin + mem_d = {data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign}; + if(data_bits==16) + begin + Bank0[dd]=mem_d[15:0]; + Bank1[dd]=mem_d[15:0]; + Bank2[dd]=mem_d[15:0]; + Bank3[dd]=mem_d[15:0]; + end + else if(data_bits==32) + begin + Bank0[dd]=mem_d[31:0]; + Bank1[dd]=mem_d[31:0]; + Bank2[dd]=mem_d[31:0]; + Bank3[dd]=mem_d[31:0]; + end + end + + endtask + + // System clock generator + always + begin + @(posedge Clk) + begin + Sys_clk = CkeZ; + CkeZ = Cke; + end + @(negedge Clk) + begin + Sys_clk = 1'b0; + end + end + + always @ (posedge Sys_clk) begin + // Internal Commamd Pipelined + Command[0] = Command[1]; + Command[1] = Command[2]; + Command[2] = Command[3]; + Command[3] = `NOP; + + Col_addr[0] = Col_addr[1]; + Col_addr[1] = Col_addr[2]; + Col_addr[2] = Col_addr[3]; + Col_addr[3] = {col_bits{1'b0}}; + + Bank_addr[0] = Bank_addr[1]; + Bank_addr[1] = Bank_addr[2]; + Bank_addr[2] = Bank_addr[3]; + Bank_addr[3] = 2'b0; + + Bank_precharge[0] = Bank_precharge[1]; + Bank_precharge[1] = Bank_precharge[2]; + Bank_precharge[2] = Bank_precharge[3]; + Bank_precharge[3] = 2'b0; + + A10_precharge[0] = A10_precharge[1]; + A10_precharge[1] = A10_precharge[2]; + A10_precharge[2] = A10_precharge[3]; + A10_precharge[3] = 1'b0; + + // Dqm pipeline for Read + Dqm_reg0 = Dqm_reg1; + Dqm_reg1 = Dqm; + + // Read or Write with Auto Precharge Counter + if (Auto_precharge[0] == 1'b1) begin + Count_precharge[0] = Count_precharge[0] + 1; + end + if (Auto_precharge[1] == 1'b1) begin + Count_precharge[1] = Count_precharge[1] + 1; + end + if (Auto_precharge[2] == 1'b1) begin + Count_precharge[2] = Count_precharge[2] + 1; + end + if (Auto_precharge[3] == 1'b1) begin + Count_precharge[3] = Count_precharge[3] + 1; + end + + // tMRD Counter + MRD_chk = MRD_chk + 1; + + // tWR Counter for Write + WR_counter[0] = WR_counter[0] + 1; + WR_counter[1] = WR_counter[1] + 1; + WR_counter[2] = WR_counter[2] + 1; + WR_counter[3] = WR_counter[3] + 1; + + // Auto Refresh + if (Aref_enable == 1'b1) begin + if (Debug) $display ("at time %t AREF : Auto Refresh", $time); + // Auto Refresh to Auto Refresh + if (($time - RC_chk < tRC)&&Debug) begin + $display ("at time %t ERROR: tRC violation during Auto Refresh", $time); + end + // Precharge to Auto Refresh + if (($time - RP_chk0 < tRP || $time - RP_chk1 < tRP || $time - RP_chk2 < tRP || $time - RP_chk3 < tRP)&&Debug) begin + $display ("at time %t ERROR: tRP violation during Auto Refresh", $time); + end + // Precharge to Refresh + if (Pc_b0 == 1'b0 || Pc_b1 == 1'b0 || Pc_b2 == 1'b0 || Pc_b3 == 1'b0) begin + $display ("at time %t ERROR: All banks must be Precharge before Auto Refresh", $time); + end + // Record Current tRC time + RC_chk = $time; + end + + // Load Mode Register + if (Mode_reg_enable == 1'b1) begin + // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode + if (Pc_b0 == 1'b1 && Pc_b1 == 1'b1 && Pc_b2 == 1'b1 && Pc_b3 == 1'b1) begin + Mode_reg = Addr; + if (Debug) begin + $display ("at time %t LMR : Load Mode Register", $time); + // CAS Latency + if (Addr[6 : 4] == 3'b010) + $display (" CAS Latency = 2"); + else if (Addr[6 : 4] == 3'b011) + $display (" CAS Latency = 3"); + else + $display (" CAS Latency = Reserved"); + // Burst Length + if (Addr[2 : 0] == 3'b000) + $display (" Burst Length = 1"); + else if (Addr[2 : 0] == 3'b001) + $display (" Burst Length = 2"); + else if (Addr[2 : 0] == 3'b010) + $display (" Burst Length = 4"); + else if (Addr[2 : 0] == 3'b011) + $display (" Burst Length = 8"); + else if (Addr[3 : 0] == 4'b0111) + $display (" Burst Length = Full"); + else + $display (" Burst Length = Reserved"); + // Burst Type + if (Addr[3] == 1'b0) + $display (" Burst Type = Sequential"); + else if (Addr[3] == 1'b1) + $display (" Burst Type = Interleaved"); + else + $display (" Burst Type = Reserved"); + // Write Burst Mode + if (Addr[9] == 1'b0) + $display (" Write Burst Mode = Programmed Burst Length"); + else if (Addr[9] == 1'b1) + $display (" Write Burst Mode = Single Location Access"); + else + $display (" Write Burst Mode = Reserved"); + end + end else begin + $display ("at time %t ERROR: all banks must be Precharge before Load Mode Register", $time); + end + // REF to LMR + if ($time - RC_chk < tRC) begin + $display ("at time %t ERROR: tRC violation during Load Mode Register", $time); + end + // LMR to LMR + if (MRD_chk < tMRD) begin + $display ("at time %t ERROR: tMRD violation during Load Mode Register", $time); + end + MRD_chk = 0; + end + + // Active Block (Latch Bank Address and Row Address) + if (Active_enable == 1'b1) begin + if (Ba == 2'b00 && Pc_b0 == 1'b1) begin + {Act_b0, Pc_b0} = 2'b10; + B0_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk0 = $time; + RAS_chk0 = $time; + if (Debug) $display ("at time %t ACT : Bank = 0 Row = %d", $time, Addr); + // Precharge to Activate Bank 0 + if ($time - RP_chk0 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 0", $time); + end + end else if (Ba == 2'b01 && Pc_b1 == 1'b1) begin + {Act_b1, Pc_b1} = 2'b10; + B1_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk1 = $time; + RAS_chk1 = $time; + if (Debug) $display ("at time %t ACT : Bank = 1 Row = %d", $time, Addr); + // Precharge to Activate Bank 1 + if ($time - RP_chk1 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 1", $time); + end + end else if (Ba == 2'b10 && Pc_b2 == 1'b1) begin + {Act_b2, Pc_b2} = 2'b10; + B2_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk2 = $time; + RAS_chk2 = $time; + if (Debug) $display ("at time %t ACT : Bank = 2 Row = %d", $time, Addr); + // Precharge to Activate Bank 2 + if ($time - RP_chk2 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 2", $time); + end + end else if (Ba == 2'b11 && Pc_b3 == 1'b1) begin + {Act_b3, Pc_b3} = 2'b10; + B3_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk3 = $time; + RAS_chk3 = $time; + if (Debug) $display ("at time %t ACT : Bank = 3 Row = %d", $time, Addr); + // Precharge to Activate Bank 3 + if ($time - RP_chk3 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 3", $time); + end + end else if (Ba == 2'b00 && Pc_b0 == 1'b0) begin + $display ("at time %t ERROR: Bank 0 is not Precharged.", $time); + end else if (Ba == 2'b01 && Pc_b1 == 1'b0) begin + $display ("at time %t ERROR: Bank 1 is not Precharged.", $time); + end else if (Ba == 2'b10 && Pc_b2 == 1'b0) begin + $display ("at time %t ERROR: Bank 2 is not Precharged.", $time); + end else if (Ba == 2'b11 && Pc_b3 == 1'b0) begin + $display ("at time %t ERROR: Bank 3 is not Precharged.", $time); + end + // Active Bank A to Active Bank B + if ((Previous_bank != Ba) && ($time - RRD_chk < tRRD)) begin + $display ("at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba); + end + // Load Mode Register to Active + if (MRD_chk < tMRD ) begin + $display ("at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba); + end + // Auto Refresh to Activate + if (($time - RC_chk < tRC)&&Debug) begin + $display ("at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba); + end + // Record variables for checking violation + RRD_chk = $time; + Previous_bank = Ba; + end + + // Precharge Block + if (Prech_enable == 1'b1) begin + if (Addr[10] == 1'b1) begin + {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b1111; + {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000; + RP_chk0 = $time; + RP_chk1 = $time; + RP_chk2 = $time; + RP_chk3 = $time; + if (Debug) $display ("at time %t PRE : Bank = ALL",$time); + // Activate to Precharge all banks + if (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) || + ($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin + $display ("at time %t ERROR: tRAS violation during Precharge all bank", $time); + end + // tWR violation check for write + if (($time - WR_chk[0] < tWRp) || ($time - WR_chk[1] < tWRp) || + ($time - WR_chk[2] < tWRp) || ($time - WR_chk[3] < tWRp)) begin + $display ("at time %t ERROR: tWR violation during Precharge all bank", $time); + end + end else if (Addr[10] == 1'b0) begin + if (Ba == 2'b00) begin + {Pc_b0, Act_b0} = 2'b10; + RP_chk0 = $time; + if (Debug) $display ("at time %t PRE : Bank = 0",$time); + // Activate to Precharge Bank 0 + if ($time - RAS_chk0 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 0", $time); + end + end else if (Ba == 2'b01) begin + {Pc_b1, Act_b1} = 2'b10; + RP_chk1 = $time; + if (Debug) $display ("at time %t PRE : Bank = 1",$time); + // Activate to Precharge Bank 1 + if ($time - RAS_chk1 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 1", $time); + end + end else if (Ba == 2'b10) begin + {Pc_b2, Act_b2} = 2'b10; + RP_chk2 = $time; + if (Debug) $display ("at time %t PRE : Bank = 2",$time); + // Activate to Precharge Bank 2 + if ($time - RAS_chk2 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 2", $time); + end + end else if (Ba == 2'b11) begin + {Pc_b3, Act_b3} = 2'b10; + RP_chk3 = $time; + if (Debug) $display ("at time %t PRE : Bank = 3",$time); + // Activate to Precharge Bank 3 + if ($time - RAS_chk3 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 3", $time); + end + end + // tWR violation check for write + if ($time - WR_chk[Ba] < tWRp) begin + $display ("at time %t ERROR: tWR violation during Precharge bank %d", $time, Ba); + end + end + // Terminate a Write Immediately (if same bank or all banks) + if (Data_in_enable == 1'b1 && (Bank == Ba || Addr[10] == 1'b1)) begin + Data_in_enable = 1'b0; + end + // Precharge Command Pipeline for Read + if (Cas_latency_3 == 1'b1) begin + Command[2] = `PRECH; + Bank_precharge[2] = Ba; + A10_precharge[2] = Addr[10]; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `PRECH; + Bank_precharge[1] = Ba; + A10_precharge[1] = Addr[10]; + end + end + + // Burst terminate + if (Burst_term == 1'b1) begin + // Terminate a Write Immediately + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + // Terminate a Read Depend on CAS Latency + if (Cas_latency_3 == 1'b1) begin + Command[2] = `BST; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `BST; + end + if (Debug) $display ("at time %t BST : Burst Terminate",$time); + end + + // Read, Write, Column Latch + if (Read_enable == 1'b1 || Write_enable == 1'b1) begin + // Check to see if bank is open (ACT) + if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || + (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin + $display("at time %t ERROR: Cannot Read or Write - Bank %d is not Activated", $time, Ba); + end + // Activate to Read or Write + if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 0", $time); + if ((Ba == 2'b01) && ($time - RCD_chk1 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 1", $time); + if ((Ba == 2'b10) && ($time - RCD_chk2 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 2", $time); + if ((Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 3", $time); + // Read Command + if (Read_enable == 1'b1) begin + // CAS Latency pipeline + if (Cas_latency_3 == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[2] = `READ_A; + end else begin + Command[2] = `READ; + end + Col_addr[2] = Addr; + Bank_addr[2] = Ba; + end else if (Cas_latency_2 == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[1] = `READ_A; + end else begin + Command[1] = `READ; + end + Col_addr[1] = Addr; + Bank_addr[1] = Ba; + end + + // Read interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Write Command + end else if (Write_enable == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[0] = `WRITE_A; + end else begin + Command[0] = `WRITE; + end + Col_addr[0] = Addr; + Bank_addr[0] = Ba; + + // Write interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Write interrupt Read (terminate Read immediately) + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + // Interrupting a Write with Autoprecharge + if (Auto_precharge[Bank] == 1'b1 && Write_precharge[Bank] == 1'b1) begin + RW_interrupt_write[Bank] = 1'b1; + if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, Bank); + end + + // Interrupting a Read with Autoprecharge + if (Auto_precharge[Bank] == 1'b1 && Read_precharge[Bank] == 1'b1) begin + RW_interrupt_read[Bank] = 1'b1; + if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, Bank); + end + + // Read or Write with Auto Precharge + if (Addr[10] == 1'b1) begin + Auto_precharge[Ba] = 1'b1; + Count_precharge[Ba] = 0; + if (Read_enable == 1'b1) begin + Read_precharge[Ba] = 1'b1; + end else if (Write_enable == 1'b1) begin + Write_precharge[Ba] = 1'b1; + end + end + end + + // Read with Auto Precharge Calculation + // The device start internal precharge: + // 1. CAS Latency - 1 cycles before last burst + // and 2. Meet minimum tRAS requirement + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 2 + ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 1 + (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) || + (RW_interrupt_read[0] == 1'b1)) begin // Case 3 + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + Auto_precharge[0] = 1'b0; + Read_precharge[0] = 1'b0; + RW_interrupt_read[0] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) || + (RW_interrupt_read[1] == 1'b1)) begin + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + Auto_precharge[1] = 1'b0; + Read_precharge[1] = 1'b0; + RW_interrupt_read[1] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) || + (RW_interrupt_read[2] == 1'b1)) begin + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + Auto_precharge[2] = 1'b0; + Read_precharge[2] = 1'b0; + RW_interrupt_read[2] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) || + (RW_interrupt_read[3] == 1'b1)) begin + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + Auto_precharge[3] = 1'b0; + Read_precharge[3] = 1'b0; + RW_interrupt_read[3] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + + // Internal Precharge or Bst + if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks + if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + end else if (Command[0] == `BST) begin // BST terminate a read to current bank + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + if (Data_out_enable == 1'b0) begin + Dq_reg <= #tOH {data_bits{1'bz}}; + end + + // Detect Read or Write command + if (Command[0] == `READ || Command[0] == `READ_A) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + if (Bank_addr[0] == 2'b00) begin + Row = B0_row_addr; + end else if (Bank_addr[0] == 2'b01) begin + Row = B1_row_addr; + end else if (Bank_addr[0] == 2'b10) begin + Row = B2_row_addr; + end else if (Bank_addr[0] == 2'b11) begin + Row = B3_row_addr; + end + Burst_counter = 0; + Data_in_enable = 1'b0; + Data_out_enable = 1'b1; + end else if (Command[0] == `WRITE || Command[0] == `WRITE_A) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + if (Bank_addr[0] == 2'b00) begin + Row = B0_row_addr; + end else if (Bank_addr[0] == 2'b01) begin + Row = B1_row_addr; + end else if (Bank_addr[0] == 2'b10) begin + Row = B2_row_addr; + end else if (Bank_addr[0] == 2'b11) begin + Row = B3_row_addr; + end + Burst_counter = 0; + Data_in_enable = 1'b1; + Data_out_enable = 1'b0; + end + + // DQ buffer (Driver/Receiver) + if (Data_in_enable == 1'b1) begin // Writing Data to Memory + // Array buffer + if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}]; + if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}]; + if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}]; + if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}]; + // Dqm operation + if (Dqm[0] == 1'b0) Dq_dqm [ 7 : 0] = Dq [ 7 : 0]; + if (Dqm[1] == 1'b0) Dq_dqm [15 : 8] = Dq [15 : 8]; + //if (Dqm[2] == 1'b0) Dq_dqm [23 : 16] = Dq [23 : 16]; + // if (Dqm[3] == 1'b0) Dq_dqm [31 : 24] = Dq [31 : 24]; + // Write to memory + if (Bank == 2'b00) Bank0 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b01) Bank1 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b10) Bank2 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b11) Bank3 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b11 && Row==10'h3 && Col[7:4]==4'h4) + $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + //$fdisplay(test_file,"bank:%h row:%h col:%h write:%h",Bank,Row,Col,Dq_dqm); + // Output result + if (Dqm == 4'b1111) begin + if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end else begin + if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_dqm, Dqm); + // Record tWR time and reset counter + WR_chk [Bank] = $time; + WR_counter [Bank] = 0; + end + // Advance burst counter subroutine + #tHZ Burst; + end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory + //$display("%h , %h, %h",Bank0,Row,Col); + // Array buffer + if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}]; + if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}]; + if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}]; + if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}]; + + // Dqm operation + if (Dqm_reg0[0] == 1'b1) Dq_dqm [ 7 : 0] = 8'bz; + if (Dqm_reg0[1] == 1'b1) Dq_dqm [15 : 8] = 8'bz; + if (Dqm_reg0[2] == 1'b1) Dq_dqm [23 : 16] = 8'bz; + if (Dqm_reg0[3] == 1'b1) Dq_dqm [31 : 24] = 8'bz; + // Display result + Dq_reg [data_bits - 1 : 0] = #tAC Dq_dqm [data_bits - 1 : 0]; + if (Dqm_reg0 == 4'b1111) begin + if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end else begin + if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_reg, Dqm_reg0); + end + // Advance burst counter subroutine + Burst; + end + end + + // Write with Auto Precharge Calculation + // The device start internal precharge: + // 1. tWR Clock after last burst + // and 2. Meet minimum tRAS requirement + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + always @ (WR_counter[0]) begin + if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 2 + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 1 + (Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) || + (RW_interrupt_write[0] == 1'b1 && WR_counter[0] >= 2)) begin // Case 3 (stop count when interrupt) + Auto_precharge[0] = 1'b0; + Write_precharge[0] = 1'b0; + RW_interrupt_write[0] = 1'b0; + #tWRa; // Wait for tWR + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + end + always @ (WR_counter[1]) begin + if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) || + (RW_interrupt_write[1] == 1'b1 && WR_counter[1] >= 2)) begin + Auto_precharge[1] = 1'b0; + Write_precharge[1] = 1'b0; + RW_interrupt_write[1] = 1'b0; + #tWRa; // Wait for tWR + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + end + always @ (WR_counter[2]) begin + if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) || + (RW_interrupt_write[2] == 1'b1 && WR_counter[2] >= 2)) begin + Auto_precharge[2] = 1'b0; + Write_precharge[2] = 1'b0; + RW_interrupt_write[2] = 1'b0; + #tWRa; // Wait for tWR + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + end + always @ (WR_counter[3]) begin + if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) || + (RW_interrupt_write[3] == 1'b1 && WR_counter[3] >= 2)) begin + Auto_precharge[3] = 1'b0; + Write_precharge[3] = 1'b0; + RW_interrupt_write[3] = 1'b0; + #tWRa; // Wait for tWR + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + end + + task Burst; + begin + // Advance Burst Counter + Burst_counter = Burst_counter + 1; + + // Burst Type + if (Mode_reg[3] == 1'b0) begin // Sequential Burst + Col_temp = Col + 1; + end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst + Col_temp[2] = Burst_counter[2] ^ Col_brst[2]; + Col_temp[1] = Burst_counter[1] ^ Col_brst[1]; + Col_temp[0] = Burst_counter[0] ^ Col_brst[0]; + end + + // Burst Length + if (Burst_length_2) begin // Burst Length = 2 + Col [0] = Col_temp [0]; + end else if (Burst_length_4) begin // Burst Length = 4 + Col [1 : 0] = Col_temp [1 : 0]; + end else if (Burst_length_8) begin // Burst Length = 8 + Col [2 : 0] = Col_temp [2 : 0]; + end else begin // Burst Length = FULL + Col = Col_temp; + end + + // Burst Read Single Write + if (Write_burst_mode == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Data Counter + if (Burst_length_1 == 1'b1) begin + if (Burst_counter >= 1) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_2 == 1'b1) begin + if (Burst_counter >= 2) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_4 == 1'b1) begin + if (Burst_counter >= 4) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_8 == 1'b1) begin + if (Burst_counter >= 8) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end + end + endtask + + //**********************SDRAMڵֱⲿļ*******************************// + +/* + integer sdram_data,ind; + + + always@(sdram_r) + begin + sdram_data=$fopen("sdram_data.txt"); + $display("Sdram dampout begin ",sdram_data); +// $fdisplay(sdram_data,"Bank0"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank0[ind]); +// $fdisplay(sdram_data,"Bank1"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank1[ind]); +// $fdisplay(sdram_data,"Bank2"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank2[ind]); +// $fdisplay(sdram_data,"Bank3"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank3[ind]); + + $fclose("sdram_data.txt"); + //->compare; + end +*/ + integer sdram_data,sdram_mem; + reg [23:0] aa,cc; + reg [18:0] bb,ee; + + always@(sdram_r) + begin + $display("Sdram dampout begin ",$realtime); + sdram_data=$fopen("sdram_data.txt"); + for(aa=0;aa<4*(mem_sizes+1);aa=aa+1) + begin + bb=aa[18:0]; + if(aa<=mem_sizes) + $fdisplay(sdram_data,"%0d %0h",aa,Bank0[bb]); + else if(aa<=2*mem_sizes+1) + $fdisplay(sdram_data,"%0d %0h",aa,Bank1[bb]); + else if(aa<=3*mem_sizes+2) + $fdisplay(sdram_data,"%0d %0h",aa,Bank2[bb]); + else + $fdisplay(sdram_data,"%0d %0h",aa,Bank3[bb]); + end + $fclose("sdram_data.txt"); + + sdram_mem=$fopen("sdram_mem.txt"); + for(cc=0;cc<4*(mem_sizes+1);cc=cc+1) + begin + ee=cc[18:0]; + if(cc<=mem_sizes) + $fdisplay(sdram_mem,"%0h",Bank0[ee]); + else if(cc<=2*mem_sizes+1) + $fdisplay(sdram_mem,"%0h",Bank1[ee]); + else if(cc<=3*mem_sizes+2) + $fdisplay(sdram_mem,"%0h",Bank2[ee]); + else + $fdisplay(sdram_mem,"%0h",Bank3[ee]); + end + $fclose("sdram_mem.txt"); + + end + + + +// // Timing Parameters for -75 (PC133) and CAS Latency = 2 +// specify +// specparam +//// tAH = 0.8, // Addr, Ba Hold Time +//// tAS = 1.5, // Addr, Ba Setup Time +//// tCH = 2.5, // Clock High-Level Width +//// tCL = 2.5, // Clock Low-Level Width +////// tCK = 10.0, // Clock Cycle Time 100mhz +////// tCK = 7.5, // Clock Cycle Time 133mhz +//// tCK = 7, // Clock Cycle Time 143mhz +//// tDH = 0.8, // Data-in Hold Time +//// tDS = 1.5, // Data-in Setup Time +//// tCKH = 0.8, // CKE Hold Time +//// tCKS = 1.5, // CKE Setup Time +//// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time +//// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time +// tAH = 1, // Addr, Ba Hold Time +// tAS = 1.5, // Addr, Ba Setup Time +// tCH = 1, // Clock High-Level Width +// tCL = 3, // Clock Low-Level Width +//// tCK = 10.0, // Clock Cycle Time 100mhz +//// tCK = 7.5, // Clock Cycle Time 133mhz +// tCK = 7, // Clock Cycle Time 143mhz +// tDH = 1, // Data-in Hold Time +// tDS = 2, // Data-in Setup Time +// tCKH = 1, // CKE Hold Time +// tCKS = 2, // CKE Setup Time +// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time +// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time +// $width (posedge Clk, tCH); +// $width (negedge Clk, tCL); +// $period (negedge Clk, tCK); +// $period (posedge Clk, tCK); +// $setuphold(posedge Clk, Cke, tCKS, tCKH); +// $setuphold(posedge Clk, Cs_n, tCMS, tCMH); +// $setuphold(posedge Clk, Cas_n, tCMS, tCMH); +// $setuphold(posedge Clk, Ras_n, tCMS, tCMH); +// $setuphold(posedge Clk, We_n, tCMS, tCMH); +// $setuphold(posedge Clk, Addr, tAS, tAH); +// $setuphold(posedge Clk, Ba, tAS, tAH); +// $setuphold(posedge Clk, Dqm, tCMS, tCMH); +// $setuphold(posedge Dq_chk, Dq, tDS, tDH); +// endspecify + +endmodule + diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_top/tb_sdram_top.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_top/tb_sdram_top.v new file mode 100644 index 0000000..c9a04b6 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_top/tb_sdram_top.v @@ -0,0 +1,231 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : tb_sdram_top +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SDRAM控制器顶层模块仿真 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module tb_sdram_top(); + +//********************************************************************// +//****************** Internal Signal and Defparam ********************// +//********************************************************************// +//wire define +//clk_gen +wire clk_50m ; //PLL输出50M时钟 +wire clk_100m ; //PLL输出100M时钟 +wire clk_100m_shift ; //PLL输出100M时钟,相位偏移-30deg +wire locked ; //PLL时钟锁定信号 +wire rst_n ; //复位信号,低有效 +//sdram +wire sdram_clk ; //SDRAM时钟 +wire sdram_cke ; //SDRAM时钟使能信号 +wire sdram_cs_n ; //SDRAM片选信号 +wire sdram_ras_n ; //SDRAM行选通信号 +wire sdram_cas_n ; //SDRAM列选题信号 +wire sdram_we_n ; //SDRAM写使能信号 +wire [1:0] sdram_ba ; //SDRAM L-Bank地址 +wire [12:0] sdram_addr ; //SDRAM地址总线 +wire [15:0] sdram_dq ; //SDRAM数据总线 +wire sdram_dqm ; //SDRAM数据总线 +//sdram_ctrl +wire init_end ; //初始化完成信号 +wire sdram_wr_ack ; //数据写阶段写响应 +wire sdram_rd_ack ; //数据读阶段响应 + +wire [9:0] rd_fifo_num ; //fifo_ctrl模块中读fifo中的数据量 +wire [15:0] rfifo_rd_data ; //fifo_ctrl模块中读fifo读数据 + +//reg define +reg sys_clk ; //系统时钟 +reg sys_rst_n ; //复位信号 +reg wr_en ; //写使能 +reg wr_en_dly ; //写使能打拍 +reg [15:0] wr_data_in ; //写数据 +reg rd_en ; //读使能 +reg [2:0] cnt_wr_wait ; //数据写入间隔计数 +reg [3:0] cnt_rd_data ; //读出数据计数 +reg wr_data_flag ; //fifo_ctrl模块中写fifo写使能 +reg read_valid ; //读有效信号 + +//defparam +//重定义仿真模型中的相关参数 +defparam sdram_model_plus_inst.addr_bits = 13; //地址位宽 +defparam sdram_model_plus_inst.data_bits = 16; //数据位宽 +defparam sdram_model_plus_inst.col_bits = 9; //列地址位宽 +defparam sdram_model_plus_inst.mem_sizes = 2*1024*1024; //L-Bank容量 + +//重定义自动刷新模块自动刷新间隔时间计数最大值 +defparam sdram_top_inst.sdram_ctrl_inst.sdram_a_ref_inst.CNT_REF_MAX = 40; + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +//时钟、复位信号 +initial + begin + sys_clk = 1'b1 ; + sys_rst_n <= 1'b0 ; + #200 + sys_rst_n <= 1'b1 ; + end + +always #10 sys_clk = ~sys_clk; + +//rst_n:复位信号 +assign rst_n = sys_rst_n & locked; + +//wr_en:写数据使能 +always@(posedge clk_50m or negedge rst_n) + if(rst_n == 1'b0) + wr_en <= 1'b1; + else if(wr_data_in == 10'd10) + wr_en <= 1'b0; + else + wr_en <= wr_en; + +//cnt_wr_wait:数据写入间隔计数 +always@(posedge clk_50m or negedge rst_n) + if(rst_n == 1'b0) + cnt_wr_wait <= 3'd0; + else if(wr_en == 1'b1) + cnt_wr_wait <= cnt_wr_wait + 1'b1; + else + cnt_wr_wait <= 3'd0; + +//wr_data_flag:fifo_ctrl模块中写fifo写使能 +always@(posedge clk_50m or negedge rst_n) + if(rst_n == 1'b0) + wr_data_flag <= 1'b0; + else if(cnt_wr_wait == 3'd7) + wr_data_flag <= 1'b1; + else + wr_data_flag <= 1'b0; + +//read_valid:数据读使能 +always@(posedge clk_50m or negedge rst_n) + if(rst_n == 1'b0) + read_valid <= 1'b1; + else if(rd_fifo_num == 10'd10) + read_valid <= 1'b0; + +//wr_en_dly:写数据使能打拍 +always@(posedge clk_50m or negedge rst_n) + if(rst_n == 1'b0) + wr_en_dly <= 1'b0; + else + wr_en_dly <= wr_en; + +//wr_data_in:写数据 +always@(posedge clk_50m or negedge rst_n) + if(rst_n == 1'b0) + wr_data_in <= 16'd0; + else if(cnt_wr_wait == 3'd7) + wr_data_in <= wr_data_in + 1'b1; + else + wr_data_in <= wr_data_in; + +//rd_en:读数据使能 +always@(posedge clk_50m or negedge rst_n) + if(rst_n == 1'b0) + rd_en <= 1'b0; + else if(cnt_rd_data == 4'd9) + rd_en <= 1'd0; + else if((wr_en == 1'b0) && (rd_fifo_num == 10'd10)) + rd_en <= 1'b1; + else + rd_en <= rd_en; + +//cnt_rd_data:读出数据计数 +always@(posedge clk_50m or negedge rst_n) + if(rst_n == 1'b0) + cnt_rd_data <= 4'd0; + else if(rd_en == 1'b1) + cnt_rd_data <= cnt_rd_data + 1'b1; + else + cnt_rd_data <= 4'd0; + + + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- clk_gen_inst ------------- +clk_gen clk_gen_inst ( + .inclk0 (sys_clk ), + .areset (~sys_rst_n ), + .c0 (clk_50m ), + .c1 (clk_100m ), + .c2 (clk_100m_shift ), + + .locked (locked ) +); + +//------------- sdram_top_inst ------------- +sdram_top sdram_top_inst( + .sys_clk (clk_100m ), //sdram 控制器参考时钟 + .clk_out (clk_100m_shift ), //用于输出的相位偏移时钟 + .sys_rst_n (rst_n ), //系统复位 +//用户写端口 + .wr_fifo_wr_clk (clk_50m ), //写端口FIFO: 写时钟 + .wr_fifo_wr_req (wr_data_flag ), //写端口FIFO: 写使能 + .wr_fifo_wr_data (wr_data_in ), //写端口FIFO: 写数据 + .sdram_wr_b_addr (24'd0 ), //写SDRAM的首地址 + .sdram_wr_e_addr (24'd10 ), //写SDRAM的末地址 + .wr_burst_len (10'd10 ), //写SDRAM时的数据突发长度 + .wr_rst (~rst_n ), //写地址复位信号 +//用户读端口 + .rd_fifo_rd_clk (clk_50m ), //读端口FIFO: 读时钟 + .rd_fifo_rd_req (rd_en ), //读端口FIFO: 读使能 + .rd_fifo_rd_data (rfifo_rd_data ), //读端口FIFO: 读数据 + .sdram_rd_b_addr (24'd0 ), //读SDRAM的首地址 + .sdram_rd_e_addr (24'd10 ), //读SDRAM的末地址 + .rd_burst_len (10'd10 ), //从SDRAM中读数据时的突发长度 + .rd_rst (~rst_n ), //读地址复位信号 + .rd_fifo_num (rd_fifo_num ), //读fifo中的数据量 +//用户控制端口 + .read_valid (read_valid ), //SDRAM 读使能 +//SDRAM 芯片接口 + .sdram_clk (sdram_clk ), //SDRAM 芯片时钟 + .sdram_cke (sdram_cke ), //SDRAM 时钟有效 + .sdram_cs_n (sdram_cs_n ), //SDRAM 片选 + .sdram_ras_n (sdram_ras_n ), //SDRAM 行有效 + .sdram_cas_n (sdram_cas_n ), //SDRAM 列有效 + .sdram_we_n (sdram_we_n ), //SDRAM 写有效 + .sdram_ba (sdram_ba ), //SDRAM Bank地址 + .sdram_addr (sdram_addr ), //SDRAM 行/列地址 + .sdram_dq (sdram_dq ), //SDRAM 数据 + .sdram_dqm (sdram_dqm ) //SDRAM 数据掩码 +); + +//-------------sdram_model_plus_inst------------- +sdram_model_plus sdram_model_plus_inst( + .Dq (sdram_dq ), + .Addr (sdram_addr ), + .Ba (sdram_ba ), + .Clk (sdram_clk ), + .Cke (sdram_cke ), + .Cs_n (sdram_cs_n ), + .Ras_n (sdram_ras_n ), + .Cas_n (sdram_cas_n ), + .We_n (sdram_we_n ), + .Dqm (2'b0 ), + .Debug (1'b1 ) + +); + +endmodule \ No newline at end of file diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_write/sdram_model_plus.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_write/sdram_model_plus.v new file mode 100644 index 0000000..4e51287 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_write/sdram_model_plus.v @@ -0,0 +1,1131 @@ +/*************************************************************************************** +ߣ +2003-08-27 V0.1 + + ڴģ鵹չܣⲿҪ¼sdram_r ,SDRAMݽᰴBank ˳damp out ļ + sdram_data.txt +*/ +//2004-03-04 ˿ ޸ԭнBANKתTXTļĸʽ +//2004-03-16 ˿ ޸SDRAM ijʼ +//2004/04/06 ˿ SDRAMIJַʽʾԱMODELSIM +//2004/04/19 ˿ ޸IJ parameter tAC = 8; +//2010/09/17 ޸sdramĴСλdqm; +/**************************************************************************************** +* +* File Name: sdram_model.V +* Version: 0.0f +* Date: July 8th, 1999 +* Model: BUS Functional +* Simulator: Model Technology (PC version 5.2e PE) +* +* Dependencies: None +* +* Author: Son P. Huynh +* Email: sphuynh@micron.com +* Phone: (208) 368-3825 +* Company: Micron Technology, Inc. +* Model: sdram_model (1Meg x 16 x 4 Banks) +* +* Description: 64Mb SDRAM Verilog model +* +* Limitation: - Doesn't check for 4096 cycle refresh +* +* Note: - Set simulator resolution to "ps" accuracy +* - Set Debug = 0 to disable $display messages +* +* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +* WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +* +* Copyright ?1998 Micron Semiconductor Products, Inc. +* All rights researved +* +* Rev Author Phone Date Changes +* ---- ---------------------------- ---------- --------------------------------------- +* 0.0f Son Huynh 208-368-3825 07/08/1999 - Fix tWR = 1 Clk + 7.5 ns (Auto) +* Micron Technology Inc. - Fix tWR = 15 ns (Manual) +* - Fix tRP (Autoprecharge to AutoRefresh) +* +* 0.0a Son Huynh 208-368-3825 05/13/1998 - First Release (from 64Mb rev 0.0e) +* Micron Technology Inc. +****************************************************************************************/ + +`timescale 1ns / 100ps + +module sdram_model_plus (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm,Debug); + + parameter addr_bits = 11; + parameter data_bits = 32; + parameter col_bits = 8; + parameter mem_sizes = 1048576*2-1;//1 Meg + + inout [data_bits - 1 : 0] Dq; + input [addr_bits - 1 : 0] Addr; + input [1 : 0] Ba; + input Clk; + input Cke; + input Cs_n; + input Ras_n; + input Cas_n; + input We_n; + input [3 : 0] Dqm; //ߵ͸8bit + //added by xzli + input Debug; + + reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];//洢 + reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes]; + reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes]; + + reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline + reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline + reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline + reg [3 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline + reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr; + + reg [addr_bits - 1 : 0] Mode_reg; + reg [data_bits - 1 : 0] Dq_reg, Dq_dqm; + reg [col_bits - 1 : 0] Col_temp, Burst_counter; + + reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate + reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge + + reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command + reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks) + reg Auto_precharge [0 : 3]; // RW AutoPrecharge (Bank) + reg Read_precharge [0 : 3]; // R AutoPrecharge + reg Write_precharge [0 : 3]; // W AutoPrecharge + integer Count_precharge [0 : 3]; // RW AutoPrecharge (Counter) + reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge + reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge + + reg Data_in_enable; + reg Data_out_enable; + + reg [1 : 0] Bank, Previous_bank; + reg [addr_bits - 1 : 0] Row; + reg [col_bits - 1 : 0] Col, Col_brst; + + // Internal system clock + reg CkeZ, Sys_clk; + + reg [21:0] dd; + + // Commands Decode + wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n; + wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n; + wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n; + wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n; + wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n; + wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n; + wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n; + + // Burst Length Decode + wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0]; + wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0]; + wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0]; + + // CAS Latency Decode + wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4]; + wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4]; + + // Write Burst Mode + wire Write_burst_mode = Mode_reg[9]; + + wire Debug; // Debug messages : 1 = On; 0 = Off + wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ + + reg [31:0] mem_d; + + event sdram_r,sdram_w,compare; + + + + + assign Dq = Dq_reg; // DQ buffer + + // Commands Operation + `define ACT 0 + `define NOP 1 + `define READ 2 + `define READ_A 3 + `define WRITE 4 + `define WRITE_A 5 + `define PRECH 6 + `define A_REF 7 + `define BST 8 + `define LMR 9 + +// // Timing Parameters for -75 (PC133) and CAS Latency = 2 +// parameter tAC = 8; //test 6.5 +// parameter tHZ = 7.0; +// parameter tOH = 2.7; +// parameter tMRD = 2.0; // 2 Clk Cycles +// parameter tRAS = 44.0; +// parameter tRC = 66.0; +// parameter tRCD = 20.0; +// parameter tRP = 20.0; +// parameter tRRD = 15.0; +// parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) +// parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns) + + // Timing Parameters for -7 (PC143) and CAS Latency = 3 + parameter tAC = 6.5; //test 6.5 + parameter tHZ = 5.5; + parameter tOH = 2; + parameter tMRD = 2.0; // 2 Clk Cycles + parameter tRAS = 48.0; + parameter tRC = 70.0; + parameter tRCD = 20.0; + parameter tRP = 20.0; + parameter tRRD = 14.0; + parameter tWRa = 7.5; // A2 Version - Auto precharge mode only (1 Clk + 7.5 ns) + parameter tWRp = 0.0; // A2 Version - Precharge mode only (15 ns) + + // Timing Check variable + integer MRD_chk; + integer WR_counter [0 : 3]; + time WR_chk [0 : 3]; + time RC_chk, RRD_chk; + time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3; + time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; + time RP_chk0, RP_chk1, RP_chk2, RP_chk3; + + integer test_file; + + //*****display the command of the sdram************************************** + + parameter Mode_Reg_Set =4'b0000; + parameter Auto_Refresh =4'b0001; + parameter Row_Active =4'b0011; + parameter Pre_Charge =4'b0010; + parameter PreCharge_All =4'b0010; + parameter Write =4'b0100; + parameter Write_Pre =4'b0100; + parameter Read =4'b0101; + parameter Read_Pre =4'b0101; + parameter Burst_Stop =4'b0110; + parameter Nop =4'b0111; + parameter Dsel =4'b1111; + + wire [3:0] sdram_control; + reg cke_temp; + reg [8*13:1] sdram_command; + + always@(posedge Clk) + cke_temp<=Cke; + + assign sdram_control={Cs_n,Ras_n,Cas_n,We_n}; + + always@(sdram_control or cke_temp) + begin + case(sdram_control) + Mode_Reg_Set: sdram_command<="Mode_Reg_Set"; + Auto_Refresh: sdram_command<="Auto_Refresh"; + Row_Active: sdram_command<="Row_Active"; + Pre_Charge: sdram_command<="Pre_Charge"; + Burst_Stop: sdram_command<="Burst_Stop"; + Dsel: sdram_command<="Dsel"; + + Write: if(cke_temp==1) + sdram_command<="Write"; + else + sdram_command<="Write_suspend"; + + Read: if(cke_temp==1) + sdram_command<="Read"; + else + sdram_command<="Read_suspend"; + + Nop: if(cke_temp==1) + sdram_command<="Nop"; + else + sdram_command<="Self_refresh"; + + default: sdram_command<="Power_down"; + endcase + end + + //***************************************************** + + initial + begin + //test_file=$fopen("test_file.txt"); + end + + initial + begin + Dq_reg = {data_bits{1'bz}}; + {Data_in_enable, Data_out_enable} = 0; + {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000; + {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000; + {WR_chk[0], WR_chk[1], WR_chk[2], WR_chk[3]} = 0; + {WR_counter[0], WR_counter[1], WR_counter[2], WR_counter[3]} = 0; + {RW_interrupt_read[0], RW_interrupt_read[1], RW_interrupt_read[2], RW_interrupt_read[3]} = 0; + {RW_interrupt_write[0], RW_interrupt_write[1], RW_interrupt_write[2], RW_interrupt_write[3]} = 0; + {MRD_chk, RC_chk, RRD_chk} = 0; + {RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0; + {RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0; + {RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0; + $timeformat (-9, 0, " ns", 12); + //$readmemh("bank0.txt", Bank0); + //$readmemh("bank1.txt", Bank1); + //$readmemh("bank2.txt", Bank2); + //$readmemh("bank3.txt", Bank3); +/* + for(dd=0;dd<=mem_sizes;dd=dd+1) + begin + Bank0[dd]=dd[data_bits - 1 : 0]; + Bank1[dd]=dd[data_bits - 1 : 0]+1; + Bank2[dd]=dd[data_bits - 1 : 0]+2; + Bank3[dd]=dd[data_bits - 1 : 0]+3; + end +*/ + initial_sdram(0); + end + + task initial_sdram; + + input data_sign; + reg [3:0] data_sign; + + for(dd=0;dd<=mem_sizes;dd=dd+1) + begin + mem_d = {data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign,data_sign}; + if(data_bits==16) + begin + Bank0[dd]=mem_d[15:0]; + Bank1[dd]=mem_d[15:0]; + Bank2[dd]=mem_d[15:0]; + Bank3[dd]=mem_d[15:0]; + end + else if(data_bits==32) + begin + Bank0[dd]=mem_d[31:0]; + Bank1[dd]=mem_d[31:0]; + Bank2[dd]=mem_d[31:0]; + Bank3[dd]=mem_d[31:0]; + end + end + + endtask + + // System clock generator + always + begin + @(posedge Clk) + begin + Sys_clk = CkeZ; + CkeZ = Cke; + end + @(negedge Clk) + begin + Sys_clk = 1'b0; + end + end + + always @ (posedge Sys_clk) begin + // Internal Commamd Pipelined + Command[0] = Command[1]; + Command[1] = Command[2]; + Command[2] = Command[3]; + Command[3] = `NOP; + + Col_addr[0] = Col_addr[1]; + Col_addr[1] = Col_addr[2]; + Col_addr[2] = Col_addr[3]; + Col_addr[3] = {col_bits{1'b0}}; + + Bank_addr[0] = Bank_addr[1]; + Bank_addr[1] = Bank_addr[2]; + Bank_addr[2] = Bank_addr[3]; + Bank_addr[3] = 2'b0; + + Bank_precharge[0] = Bank_precharge[1]; + Bank_precharge[1] = Bank_precharge[2]; + Bank_precharge[2] = Bank_precharge[3]; + Bank_precharge[3] = 2'b0; + + A10_precharge[0] = A10_precharge[1]; + A10_precharge[1] = A10_precharge[2]; + A10_precharge[2] = A10_precharge[3]; + A10_precharge[3] = 1'b0; + + // Dqm pipeline for Read + Dqm_reg0 = Dqm_reg1; + Dqm_reg1 = Dqm; + + // Read or Write with Auto Precharge Counter + if (Auto_precharge[0] == 1'b1) begin + Count_precharge[0] = Count_precharge[0] + 1; + end + if (Auto_precharge[1] == 1'b1) begin + Count_precharge[1] = Count_precharge[1] + 1; + end + if (Auto_precharge[2] == 1'b1) begin + Count_precharge[2] = Count_precharge[2] + 1; + end + if (Auto_precharge[3] == 1'b1) begin + Count_precharge[3] = Count_precharge[3] + 1; + end + + // tMRD Counter + MRD_chk = MRD_chk + 1; + + // tWR Counter for Write + WR_counter[0] = WR_counter[0] + 1; + WR_counter[1] = WR_counter[1] + 1; + WR_counter[2] = WR_counter[2] + 1; + WR_counter[3] = WR_counter[3] + 1; + + // Auto Refresh + if (Aref_enable == 1'b1) begin + if (Debug) $display ("at time %t AREF : Auto Refresh", $time); + // Auto Refresh to Auto Refresh + if (($time - RC_chk < tRC)&&Debug) begin + $display ("at time %t ERROR: tRC violation during Auto Refresh", $time); + end + // Precharge to Auto Refresh + if (($time - RP_chk0 < tRP || $time - RP_chk1 < tRP || $time - RP_chk2 < tRP || $time - RP_chk3 < tRP)&&Debug) begin + $display ("at time %t ERROR: tRP violation during Auto Refresh", $time); + end + // Precharge to Refresh + if (Pc_b0 == 1'b0 || Pc_b1 == 1'b0 || Pc_b2 == 1'b0 || Pc_b3 == 1'b0) begin + $display ("at time %t ERROR: All banks must be Precharge before Auto Refresh", $time); + end + // Record Current tRC time + RC_chk = $time; + end + + // Load Mode Register + if (Mode_reg_enable == 1'b1) begin + // Decode CAS Latency, Burst Length, Burst Type, and Write Burst Mode + if (Pc_b0 == 1'b1 && Pc_b1 == 1'b1 && Pc_b2 == 1'b1 && Pc_b3 == 1'b1) begin + Mode_reg = Addr; + if (Debug) begin + $display ("at time %t LMR : Load Mode Register", $time); + // CAS Latency + if (Addr[6 : 4] == 3'b010) + $display (" CAS Latency = 2"); + else if (Addr[6 : 4] == 3'b011) + $display (" CAS Latency = 3"); + else + $display (" CAS Latency = Reserved"); + // Burst Length + if (Addr[2 : 0] == 3'b000) + $display (" Burst Length = 1"); + else if (Addr[2 : 0] == 3'b001) + $display (" Burst Length = 2"); + else if (Addr[2 : 0] == 3'b010) + $display (" Burst Length = 4"); + else if (Addr[2 : 0] == 3'b011) + $display (" Burst Length = 8"); + else if (Addr[3 : 0] == 4'b0111) + $display (" Burst Length = Full"); + else + $display (" Burst Length = Reserved"); + // Burst Type + if (Addr[3] == 1'b0) + $display (" Burst Type = Sequential"); + else if (Addr[3] == 1'b1) + $display (" Burst Type = Interleaved"); + else + $display (" Burst Type = Reserved"); + // Write Burst Mode + if (Addr[9] == 1'b0) + $display (" Write Burst Mode = Programmed Burst Length"); + else if (Addr[9] == 1'b1) + $display (" Write Burst Mode = Single Location Access"); + else + $display (" Write Burst Mode = Reserved"); + end + end else begin + $display ("at time %t ERROR: all banks must be Precharge before Load Mode Register", $time); + end + // REF to LMR + if ($time - RC_chk < tRC) begin + $display ("at time %t ERROR: tRC violation during Load Mode Register", $time); + end + // LMR to LMR + if (MRD_chk < tMRD) begin + $display ("at time %t ERROR: tMRD violation during Load Mode Register", $time); + end + MRD_chk = 0; + end + + // Active Block (Latch Bank Address and Row Address) + if (Active_enable == 1'b1) begin + if (Ba == 2'b00 && Pc_b0 == 1'b1) begin + {Act_b0, Pc_b0} = 2'b10; + B0_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk0 = $time; + RAS_chk0 = $time; + if (Debug) $display ("at time %t ACT : Bank = 0 Row = %d", $time, Addr); + // Precharge to Activate Bank 0 + if ($time - RP_chk0 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 0", $time); + end + end else if (Ba == 2'b01 && Pc_b1 == 1'b1) begin + {Act_b1, Pc_b1} = 2'b10; + B1_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk1 = $time; + RAS_chk1 = $time; + if (Debug) $display ("at time %t ACT : Bank = 1 Row = %d", $time, Addr); + // Precharge to Activate Bank 1 + if ($time - RP_chk1 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 1", $time); + end + end else if (Ba == 2'b10 && Pc_b2 == 1'b1) begin + {Act_b2, Pc_b2} = 2'b10; + B2_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk2 = $time; + RAS_chk2 = $time; + if (Debug) $display ("at time %t ACT : Bank = 2 Row = %d", $time, Addr); + // Precharge to Activate Bank 2 + if ($time - RP_chk2 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 2", $time); + end + end else if (Ba == 2'b11 && Pc_b3 == 1'b1) begin + {Act_b3, Pc_b3} = 2'b10; + B3_row_addr = Addr [addr_bits - 1 : 0]; + RCD_chk3 = $time; + RAS_chk3 = $time; + if (Debug) $display ("at time %t ACT : Bank = 3 Row = %d", $time, Addr); + // Precharge to Activate Bank 3 + if ($time - RP_chk3 < tRP) begin + $display ("at time %t ERROR: tRP violation during Activate bank 3", $time); + end + end else if (Ba == 2'b00 && Pc_b0 == 1'b0) begin + $display ("at time %t ERROR: Bank 0 is not Precharged.", $time); + end else if (Ba == 2'b01 && Pc_b1 == 1'b0) begin + $display ("at time %t ERROR: Bank 1 is not Precharged.", $time); + end else if (Ba == 2'b10 && Pc_b2 == 1'b0) begin + $display ("at time %t ERROR: Bank 2 is not Precharged.", $time); + end else if (Ba == 2'b11 && Pc_b3 == 1'b0) begin + $display ("at time %t ERROR: Bank 3 is not Precharged.", $time); + end + // Active Bank A to Active Bank B + if ((Previous_bank != Ba) && ($time - RRD_chk < tRRD)) begin + $display ("at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba); + end + // Load Mode Register to Active + if (MRD_chk < tMRD ) begin + $display ("at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba); + end + // Auto Refresh to Activate + if (($time - RC_chk < tRC)&&Debug) begin + $display ("at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba); + end + // Record variables for checking violation + RRD_chk = $time; + Previous_bank = Ba; + end + + // Precharge Block + if (Prech_enable == 1'b1) begin + if (Addr[10] == 1'b1) begin + {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b1111; + {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b0000; + RP_chk0 = $time; + RP_chk1 = $time; + RP_chk2 = $time; + RP_chk3 = $time; + if (Debug) $display ("at time %t PRE : Bank = ALL",$time); + // Activate to Precharge all banks + if (($time - RAS_chk0 < tRAS) || ($time - RAS_chk1 < tRAS) || + ($time - RAS_chk2 < tRAS) || ($time - RAS_chk3 < tRAS)) begin + $display ("at time %t ERROR: tRAS violation during Precharge all bank", $time); + end + // tWR violation check for write + if (($time - WR_chk[0] < tWRp) || ($time - WR_chk[1] < tWRp) || + ($time - WR_chk[2] < tWRp) || ($time - WR_chk[3] < tWRp)) begin + $display ("at time %t ERROR: tWR violation during Precharge all bank", $time); + end + end else if (Addr[10] == 1'b0) begin + if (Ba == 2'b00) begin + {Pc_b0, Act_b0} = 2'b10; + RP_chk0 = $time; + if (Debug) $display ("at time %t PRE : Bank = 0",$time); + // Activate to Precharge Bank 0 + if ($time - RAS_chk0 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 0", $time); + end + end else if (Ba == 2'b01) begin + {Pc_b1, Act_b1} = 2'b10; + RP_chk1 = $time; + if (Debug) $display ("at time %t PRE : Bank = 1",$time); + // Activate to Precharge Bank 1 + if ($time - RAS_chk1 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 1", $time); + end + end else if (Ba == 2'b10) begin + {Pc_b2, Act_b2} = 2'b10; + RP_chk2 = $time; + if (Debug) $display ("at time %t PRE : Bank = 2",$time); + // Activate to Precharge Bank 2 + if ($time - RAS_chk2 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 2", $time); + end + end else if (Ba == 2'b11) begin + {Pc_b3, Act_b3} = 2'b10; + RP_chk3 = $time; + if (Debug) $display ("at time %t PRE : Bank = 3",$time); + // Activate to Precharge Bank 3 + if ($time - RAS_chk3 < tRAS) begin + $display ("at time %t ERROR: tRAS violation during Precharge bank 3", $time); + end + end + // tWR violation check for write + if ($time - WR_chk[Ba] < tWRp) begin + $display ("at time %t ERROR: tWR violation during Precharge bank %d", $time, Ba); + end + end + // Terminate a Write Immediately (if same bank or all banks) + if (Data_in_enable == 1'b1 && (Bank == Ba || Addr[10] == 1'b1)) begin + Data_in_enable = 1'b0; + end + // Precharge Command Pipeline for Read + if (Cas_latency_3 == 1'b1) begin + Command[2] = `PRECH; + Bank_precharge[2] = Ba; + A10_precharge[2] = Addr[10]; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `PRECH; + Bank_precharge[1] = Ba; + A10_precharge[1] = Addr[10]; + end + end + + // Burst terminate + if (Burst_term == 1'b1) begin + // Terminate a Write Immediately + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + // Terminate a Read Depend on CAS Latency + if (Cas_latency_3 == 1'b1) begin + Command[2] = `BST; + end else if (Cas_latency_2 == 1'b1) begin + Command[1] = `BST; + end + if (Debug) $display ("at time %t BST : Burst Terminate",$time); + end + + // Read, Write, Column Latch + if (Read_enable == 1'b1 || Write_enable == 1'b1) begin + // Check to see if bank is open (ACT) + if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) || + (Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin + $display("at time %t ERROR: Cannot Read or Write - Bank %d is not Activated", $time, Ba); + end + // Activate to Read or Write + if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 0", $time); + if ((Ba == 2'b01) && ($time - RCD_chk1 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 1", $time); + if ((Ba == 2'b10) && ($time - RCD_chk2 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 2", $time); + if ((Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) + $display("at time %t ERROR: tRCD violation during Read or Write to Bank 3", $time); + // Read Command + if (Read_enable == 1'b1) begin + // CAS Latency pipeline + if (Cas_latency_3 == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[2] = `READ_A; + end else begin + Command[2] = `READ; + end + Col_addr[2] = Addr; + Bank_addr[2] = Ba; + end else if (Cas_latency_2 == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[1] = `READ_A; + end else begin + Command[1] = `READ; + end + Col_addr[1] = Addr; + Bank_addr[1] = Ba; + end + + // Read interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Write Command + end else if (Write_enable == 1'b1) begin + if (Addr[10] == 1'b1) begin + Command[0] = `WRITE_A; + end else begin + Command[0] = `WRITE; + end + Col_addr[0] = Addr; + Bank_addr[0] = Ba; + + // Write interrupt Write (terminate Write immediately) + if (Data_in_enable == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Write interrupt Read (terminate Read immediately) + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + // Interrupting a Write with Autoprecharge + if (Auto_precharge[Bank] == 1'b1 && Write_precharge[Bank] == 1'b1) begin + RW_interrupt_write[Bank] = 1'b1; + if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Write Bank %d with Autoprecharge", $time, Ba, Bank); + end + + // Interrupting a Read with Autoprecharge + if (Auto_precharge[Bank] == 1'b1 && Read_precharge[Bank] == 1'b1) begin + RW_interrupt_read[Bank] = 1'b1; + if (Debug) $display ("at time %t NOTE : Read/Write Bank %d interrupt Read Bank %d with Autoprecharge", $time, Ba, Bank); + end + + // Read or Write with Auto Precharge + if (Addr[10] == 1'b1) begin + Auto_precharge[Ba] = 1'b1; + Count_precharge[Ba] = 0; + if (Read_enable == 1'b1) begin + Read_precharge[Ba] = 1'b1; + end else if (Write_enable == 1'b1) begin + Write_precharge[Ba] = 1'b1; + end + end + end + + // Read with Auto Precharge Calculation + // The device start internal precharge: + // 1. CAS Latency - 1 cycles before last burst + // and 2. Meet minimum tRAS requirement + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 2 + ((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) || // Case 1 + (Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) || + (RW_interrupt_read[0] == 1'b1)) begin // Case 3 + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + Auto_precharge[0] = 1'b0; + Read_precharge[0] = 1'b0; + RW_interrupt_read[0] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) || + (RW_interrupt_read[1] == 1'b1)) begin + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + Auto_precharge[1] = 1'b0; + Read_precharge[1] = 1'b0; + RW_interrupt_read[1] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) || + (RW_interrupt_read[2] == 1'b1)) begin + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + Auto_precharge[2] = 1'b0; + Read_precharge[2] = 1'b0; + RW_interrupt_read[2] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + ((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) || + (RW_interrupt_read[3] == 1'b1)) begin + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + Auto_precharge[3] = 1'b0; + Read_precharge[3] = 1'b0; + RW_interrupt_read[3] = 1'b0; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + + // Internal Precharge or Bst + if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks + if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + end else if (Command[0] == `BST) begin // BST terminate a read to current bank + if (Data_out_enable == 1'b1) begin + Data_out_enable = 1'b0; + end + end + + if (Data_out_enable == 1'b0) begin + Dq_reg <= #tOH {data_bits{1'bz}}; + end + + // Detect Read or Write command + if (Command[0] == `READ || Command[0] == `READ_A) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + if (Bank_addr[0] == 2'b00) begin + Row = B0_row_addr; + end else if (Bank_addr[0] == 2'b01) begin + Row = B1_row_addr; + end else if (Bank_addr[0] == 2'b10) begin + Row = B2_row_addr; + end else if (Bank_addr[0] == 2'b11) begin + Row = B3_row_addr; + end + Burst_counter = 0; + Data_in_enable = 1'b0; + Data_out_enable = 1'b1; + end else if (Command[0] == `WRITE || Command[0] == `WRITE_A) begin + Bank = Bank_addr[0]; + Col = Col_addr[0]; + Col_brst = Col_addr[0]; + if (Bank_addr[0] == 2'b00) begin + Row = B0_row_addr; + end else if (Bank_addr[0] == 2'b01) begin + Row = B1_row_addr; + end else if (Bank_addr[0] == 2'b10) begin + Row = B2_row_addr; + end else if (Bank_addr[0] == 2'b11) begin + Row = B3_row_addr; + end + Burst_counter = 0; + Data_in_enable = 1'b1; + Data_out_enable = 1'b0; + end + + // DQ buffer (Driver/Receiver) + if (Data_in_enable == 1'b1) begin // Writing Data to Memory + // Array buffer + if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}]; + if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}]; + if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}]; + if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}]; + // Dqm operation + if (Dqm[0] == 1'b0) Dq_dqm [ 7 : 0] = Dq [ 7 : 0]; + if (Dqm[1] == 1'b0) Dq_dqm [15 : 8] = Dq [15 : 8]; + //if (Dqm[2] == 1'b0) Dq_dqm [23 : 16] = Dq [23 : 16]; + // if (Dqm[3] == 1'b0) Dq_dqm [31 : 24] = Dq [31 : 24]; + // Write to memory + if (Bank == 2'b00) Bank0 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b01) Bank1 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b10) Bank2 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b11) Bank3 [{Row, Col}] = Dq_dqm [data_bits - 1 : 0]; + if (Bank == 2'b11 && Row==10'h3 && Col[7:4]==4'h4) + $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + //$fdisplay(test_file,"bank:%h row:%h col:%h write:%h",Bank,Row,Col,Dq_dqm); + // Output result + if (Dqm == 4'b1111) begin + if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end else begin + if (Debug) $display("at time %t WRITE: Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_dqm, Dqm); + // Record tWR time and reset counter + WR_chk [Bank] = $time; + WR_counter [Bank] = 0; + end + // Advance burst counter subroutine + #tHZ Burst; + end else if (Data_out_enable == 1'b1) begin // Reading Data from Memory + //$display("%h , %h, %h",Bank0,Row,Col); + // Array buffer + if (Bank == 2'b00) Dq_dqm [data_bits - 1 : 0] = Bank0 [{Row, Col}]; + if (Bank == 2'b01) Dq_dqm [data_bits - 1 : 0] = Bank1 [{Row, Col}]; + if (Bank == 2'b10) Dq_dqm [data_bits - 1 : 0] = Bank2 [{Row, Col}]; + if (Bank == 2'b11) Dq_dqm [data_bits - 1 : 0] = Bank3 [{Row, Col}]; + + // Dqm operation + if (Dqm_reg0[0] == 1'b1) Dq_dqm [ 7 : 0] = 8'bz; + if (Dqm_reg0[1] == 1'b1) Dq_dqm [15 : 8] = 8'bz; + if (Dqm_reg0[2] == 1'b1) Dq_dqm [23 : 16] = 8'bz; + if (Dqm_reg0[3] == 1'b1) Dq_dqm [31 : 24] = 8'bz; + // Display result + Dq_reg [data_bits - 1 : 0] = #tAC Dq_dqm [data_bits - 1 : 0]; + if (Dqm_reg0 == 4'b1111) begin + if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = Hi-Z due to DQM", $time, Bank, Row, Col); + end else begin + if (Debug) $display("at time %t READ : Bank = %d Row = %d, Col = %d, Data = %d, Dqm = %b", $time, Bank, Row, Col, Dq_reg, Dqm_reg0); + end + // Advance burst counter subroutine + Burst; + end + end + + // Write with Auto Precharge Calculation + // The device start internal precharge: + // 1. tWR Clock after last burst + // and 2. Meet minimum tRAS requirement + // or 3. Interrupt by a Read or Write (with or without AutoPrecharge) + always @ (WR_counter[0]) begin + if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1)) begin + if ((($time - RAS_chk0 >= tRAS) && // Case 2 + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 1 + (Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) || + (RW_interrupt_write[0] == 1'b1 && WR_counter[0] >= 2)) begin // Case 3 (stop count when interrupt) + Auto_precharge[0] = 1'b0; + Write_precharge[0] = 1'b0; + RW_interrupt_write[0] = 1'b0; + #tWRa; // Wait for tWR + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 0", $time); + end + end + end + always @ (WR_counter[1]) begin + if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1)) begin + if ((($time - RAS_chk1 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) || + (RW_interrupt_write[1] == 1'b1 && WR_counter[1] >= 2)) begin + Auto_precharge[1] = 1'b0; + Write_precharge[1] = 1'b0; + RW_interrupt_write[1] = 1'b0; + #tWRa; // Wait for tWR + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 1", $time); + end + end + end + always @ (WR_counter[2]) begin + if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1)) begin + if ((($time - RAS_chk2 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) || + (RW_interrupt_write[2] == 1'b1 && WR_counter[2] >= 2)) begin + Auto_precharge[2] = 1'b0; + Write_precharge[2] = 1'b0; + RW_interrupt_write[2] = 1'b0; + #tWRa; // Wait for tWR + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 2", $time); + end + end + end + always @ (WR_counter[3]) begin + if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1)) begin + if ((($time - RAS_chk3 >= tRAS) && + (((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || + (Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) || + (Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) || + (Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) || + (RW_interrupt_write[3] == 1'b1 && WR_counter[3] >= 2)) begin + Auto_precharge[3] = 1'b0; + Write_precharge[3] = 1'b0; + RW_interrupt_write[3] = 1'b0; + #tWRa; // Wait for tWR + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + if (Debug) $display ("at time %t NOTE : Start Internal Auto Precharge for Bank 3", $time); + end + end + end + + task Burst; + begin + // Advance Burst Counter + Burst_counter = Burst_counter + 1; + + // Burst Type + if (Mode_reg[3] == 1'b0) begin // Sequential Burst + Col_temp = Col + 1; + end else if (Mode_reg[3] == 1'b1) begin // Interleaved Burst + Col_temp[2] = Burst_counter[2] ^ Col_brst[2]; + Col_temp[1] = Burst_counter[1] ^ Col_brst[1]; + Col_temp[0] = Burst_counter[0] ^ Col_brst[0]; + end + + // Burst Length + if (Burst_length_2) begin // Burst Length = 2 + Col [0] = Col_temp [0]; + end else if (Burst_length_4) begin // Burst Length = 4 + Col [1 : 0] = Col_temp [1 : 0]; + end else if (Burst_length_8) begin // Burst Length = 8 + Col [2 : 0] = Col_temp [2 : 0]; + end else begin // Burst Length = FULL + Col = Col_temp; + end + + // Burst Read Single Write + if (Write_burst_mode == 1'b1) begin + Data_in_enable = 1'b0; + end + + // Data Counter + if (Burst_length_1 == 1'b1) begin + if (Burst_counter >= 1) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_2 == 1'b1) begin + if (Burst_counter >= 2) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_4 == 1'b1) begin + if (Burst_counter >= 4) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end else if (Burst_length_8 == 1'b1) begin + if (Burst_counter >= 8) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + end + end + end + endtask + + //**********************SDRAMڵֱⲿļ*******************************// + +/* + integer sdram_data,ind; + + + always@(sdram_r) + begin + sdram_data=$fopen("sdram_data.txt"); + $display("Sdram dampout begin ",sdram_data); +// $fdisplay(sdram_data,"Bank0"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank0[ind]); +// $fdisplay(sdram_data,"Bank1"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank1[ind]); +// $fdisplay(sdram_data,"Bank2"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank2[ind]); +// $fdisplay(sdram_data,"Bank3"); + for(ind=0;ind<=mem_sizes;ind=ind+1) + $fdisplay(sdram_data,"%h %b",ind,Bank3[ind]); + + $fclose("sdram_data.txt"); + //->compare; + end +*/ + integer sdram_data,sdram_mem; + reg [23:0] aa,cc; + reg [18:0] bb,ee; + + always@(sdram_r) + begin + $display("Sdram dampout begin ",$realtime); + sdram_data=$fopen("sdram_data.txt"); + for(aa=0;aa<4*(mem_sizes+1);aa=aa+1) + begin + bb=aa[18:0]; + if(aa<=mem_sizes) + $fdisplay(sdram_data,"%0d %0h",aa,Bank0[bb]); + else if(aa<=2*mem_sizes+1) + $fdisplay(sdram_data,"%0d %0h",aa,Bank1[bb]); + else if(aa<=3*mem_sizes+2) + $fdisplay(sdram_data,"%0d %0h",aa,Bank2[bb]); + else + $fdisplay(sdram_data,"%0d %0h",aa,Bank3[bb]); + end + $fclose("sdram_data.txt"); + + sdram_mem=$fopen("sdram_mem.txt"); + for(cc=0;cc<4*(mem_sizes+1);cc=cc+1) + begin + ee=cc[18:0]; + if(cc<=mem_sizes) + $fdisplay(sdram_mem,"%0h",Bank0[ee]); + else if(cc<=2*mem_sizes+1) + $fdisplay(sdram_mem,"%0h",Bank1[ee]); + else if(cc<=3*mem_sizes+2) + $fdisplay(sdram_mem,"%0h",Bank2[ee]); + else + $fdisplay(sdram_mem,"%0h",Bank3[ee]); + end + $fclose("sdram_mem.txt"); + + end + + + +// // Timing Parameters for -75 (PC133) and CAS Latency = 2 +// specify +// specparam +//// tAH = 0.8, // Addr, Ba Hold Time +//// tAS = 1.5, // Addr, Ba Setup Time +//// tCH = 2.5, // Clock High-Level Width +//// tCL = 2.5, // Clock Low-Level Width +////// tCK = 10.0, // Clock Cycle Time 100mhz +////// tCK = 7.5, // Clock Cycle Time 133mhz +//// tCK = 7, // Clock Cycle Time 143mhz +//// tDH = 0.8, // Data-in Hold Time +//// tDS = 1.5, // Data-in Setup Time +//// tCKH = 0.8, // CKE Hold Time +//// tCKS = 1.5, // CKE Setup Time +//// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time +//// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time +// tAH = 1, // Addr, Ba Hold Time +// tAS = 1.5, // Addr, Ba Setup Time +// tCH = 1, // Clock High-Level Width +// tCL = 3, // Clock Low-Level Width +//// tCK = 10.0, // Clock Cycle Time 100mhz +//// tCK = 7.5, // Clock Cycle Time 133mhz +// tCK = 7, // Clock Cycle Time 143mhz +// tDH = 1, // Data-in Hold Time +// tDS = 2, // Data-in Setup Time +// tCKH = 1, // CKE Hold Time +// tCKS = 2, // CKE Setup Time +// tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time +// tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time +// $width (posedge Clk, tCH); +// $width (negedge Clk, tCL); +// $period (negedge Clk, tCK); +// $period (posedge Clk, tCK); +// $setuphold(posedge Clk, Cke, tCKS, tCKH); +// $setuphold(posedge Clk, Cs_n, tCMS, tCMH); +// $setuphold(posedge Clk, Cas_n, tCMS, tCMH); +// $setuphold(posedge Clk, Ras_n, tCMS, tCMH); +// $setuphold(posedge Clk, We_n, tCMS, tCMH); +// $setuphold(posedge Clk, Addr, tAS, tAH); +// $setuphold(posedge Clk, Ba, tAS, tAH); +// $setuphold(posedge Clk, Dqm, tCMS, tCMH); +// $setuphold(posedge Dq_chk, Dq, tDS, tDH); +// endspecify + +endmodule + diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_write/tb_sdram_write.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_write/tb_sdram_write.v new file mode 100644 index 0000000..108f7ca --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_sdram_write/tb_sdram_write.v @@ -0,0 +1,178 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : tb_sdram_write +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : SDRAM数据写模块仿真 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module tb_sdram_write(); + +//********************************************************************// +//****************** Internal Signal and Defparam ********************// +//********************************************************************// + +//wire define +//clk_gen +wire clk_50m ; //PLL输出50M时钟 +wire clk_100m ; //PLL输出100M时钟 +wire clk_100m_shift ; //PLL输出100M时钟,相位偏移-30deg +wire locked ; //PLL时钟锁定信号 +wire rst_n ; //复位信号,低有效 +//sdram_init +wire [3:0] init_cmd ; //初始化阶段指令 +wire [1:0] init_ba ; //初始化阶段L-Bank地址 +wire [12:0] init_addr ; //初始化阶段地址总线 +wire init_end ; //初始化完成信号 +//sdram_write +wire [12:0] write_addr ; //数据写阶段地址总线 +wire [1:0] write_ba ; //数据写阶段L-Bank地址 +wire [3:0] write_cmd ; //数据写阶段指令 +wire [15:0] wr_sdram_data ; //数据写阶段写入SDRAM数据 +wire wr_sdram_en ; //数据写阶段写数据有效使能信号 +wire wr_end ; //数据写阶段一次突发写结束 +wire sdram_wr_ack ; //数据写阶段写响应 +//sdram_addr +wire [12:0] sdram_addr ; //SDRAM地址总线 +wire [1:0] sdram_ba ; //SDRAML-Bank地址 +wire [3:0] sdram_cmd ; //SDRAM指令 +wire [15:0] sdram_dq ; //SDRAM数据总线 +//reg define +reg sys_clk ; //系统时钟 +reg sys_rst_n ; //复位信号 +reg wr_en ; //写使能 +reg [15:0] wr_data_in ; //写数据 + +//defparam +//重定义仿真模型中的相关参数 +defparam sdram_model_plus_inst.addr_bits = 13; //地址位宽 +defparam sdram_model_plus_inst.data_bits = 16; //数据位宽 +defparam sdram_model_plus_inst.col_bits = 9; //列地址位宽 +defparam sdram_model_plus_inst.mem_sizes = 2*1024*1024; //L-Bank容量 + +//********************************************************************// +//**************************** Clk And Rst ***************************// +//********************************************************************// + +//时钟、复位信号 +initial + begin + sys_clk = 1'b1 ; + sys_rst_n <= 1'b0 ; + #200 + sys_rst_n <= 1'b1 ; + end + +always #10 sys_clk = ~sys_clk; + +//rst_n:复位信号 +assign rst_n = sys_rst_n & locked; + +//wr_en：写数据使能 +always@(posedge clk_100m or negedge rst_n) + if(rst_n == 1'b0) + wr_en <= 1'b0; + else if(wr_end == 1'b1) + wr_en <= 1'b0; + else if(init_end == 1'b1) + wr_en <= 1'b1; + else + wr_en <= wr_en; + +//wr_data_in:写数据 +always@(posedge clk_100m or negedge rst_n) + if(rst_n == 1'b0) + wr_data_in <= 16'd0; + else if(wr_data_in == 16'd10) + wr_data_in <= 16'd0; + else if(sdram_wr_ack == 1'b1) + wr_data_in <= wr_data_in + 1'b1; + else + wr_data_in <= wr_data_in; + +//sdram_cmd,sdram_ba,sdram_addr +assign sdram_cmd = (init_end == 1'b1) ? write_cmd : init_cmd; +assign sdram_ba = (init_end == 1'b1) ? write_ba : init_ba; +assign sdram_addr = (init_end == 1'b1) ? write_addr : init_addr; + +//wr_sdram_data +assign sdram_dq = (wr_sdram_en == 1'b1) ? wr_sdram_data : 16'hz; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- clk_gen_inst ------------- +clk_gen clk_gen_inst ( + .inclk0 (sys_clk ), + .areset (~sys_rst_n ), + .c0 (clk_50m ), + .c1 (clk_100m ), + .c2 (clk_100m_shift ), + + .locked (locked ) +); + +//------------- sdram_init_inst ------------- +sdram_init sdram_init_inst( + + .sys_clk (clk_100m ), + .sys_rst_n (rst_n ), + + .init_cmd (init_cmd ), + .init_ba (init_ba ), + .init_addr (init_addr ), + .init_end (init_end ) + +); + +//------------- sdram_write_inst ------------- +sdram_write sdram_write_inst( + + .sys_clk (clk_100m ), + .sys_rst_n (rst_n ), + .init_end (init_end ), + .wr_en (wr_en ), + + .wr_addr (24'h000_000 ), + .wr_data (wr_data_in ), + .wr_burst_len (10'd10 ), + + .wr_ack (sdram_wr_ack ), + .wr_end (wr_end ), + .write_cmd (write_cmd ), + .write_ba (write_ba ), + .write_addr (write_addr ), + .wr_sdram_en (wr_sdram_en ), + .wr_sdram_data (wr_sdram_data ) + +); + +//-------------sdram_model_plus_inst------------- +sdram_model_plus sdram_model_plus_inst( + .Dq (sdram_dq ), + .Addr (sdram_addr ), + .Ba (sdram_ba ), + .Clk (clk_100m_shift ), + .Cke (1'b1 ), + .Cs_n (sdram_cmd[3] ), + .Ras_n (sdram_cmd[2] ), + .Cas_n (sdram_cmd[1] ), + .We_n (sdram_cmd[0] ), + .Dqm (2'b0 ), + .Debug (1'b1 ) + +); + +endmodule \ No newline at end of file diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_uart_sdram.v b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_uart_sdram.v new file mode 100644 index 0000000..18133b2 --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/tb_uart_sdram.v @@ -0,0 +1,150 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/08/25 +// Module Name : tb_uart_sdram +// Project Name : uart_sdram +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : uart_sdram模块仿真文件 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module tb_uart_sdram(); + +//********************************************************************// +//****************** Internal Signal and Defparam ********************// +//********************************************************************// + +//wire define +wire tx ; +wire sdram_clk ; +wire sdram_cke ; +wire sdram_cs_n ; +wire sdram_cas_n ; +wire sdram_ras_n ; +wire sdram_we_n ; +wire [1:0] sdram_ba ; +wire [12:0] sdram_addr ; +wire [1:0] sdram_dqm ; +wire [15:0] sdram_dq ; + +//reg define +reg sys_clk ; +reg sys_rst_n ; +reg rx ; +reg [7:0] data_mem [9:0] ; //data_mem是一个存储器，相当于一个ram + +//********************************************************************// +//**************************** Clk And Rst ***************************// +//********************************************************************// + +//读取sim文件夹下面的data.txt文件，并把读出的数据定义为data_mem +initial + $readmemh("E:/sources/sdram_test/uart_sdram/sim/test_data.txt",data_mem); + +//时钟、复位信号 +initial + begin + sys_clk = 1'b1 ; + sys_rst_n <= 1'b0 ; + #200 + sys_rst_n <= 1'b1 ; + end + +always #10 sys_clk = ~sys_clk; + + +initial + begin + rx <= 1'b1; + #200 + rx_byte(); + end + +task rx_byte(); + integer j; + for(j=0;j<10;j=j+1) + rx_bit(data_mem[j]); +endtask + +task rx_bit(input[7:0] data); //data是data_mem[j]的值。 + integer i; + for(i=0;i<10;i=i+1) + begin + case(i) + 0: rx <= 1'b0 ; //起始位 + 1: rx <= data[0]; + 2: rx <= data[1]; + 3: rx <= data[2]; + 4: rx <= data[3]; + 5: rx <= data[4]; + 6: rx <= data[5]; + 7: rx <= data[6]; + 8: rx <= data[7]; //上面8个发送的是数据位 + 9: rx <= 1'b1 ; //停止位 + endcase + #1040; //一个波特时间=ssys_clk周期*波特计数器 + end +endtask + +//重定义defparam,用于修改参数,缩短仿真时间 +defparam uart_sdram_inst.uart_rx_inst.BAUD_CNT_END = 52; +defparam uart_sdram_inst.uart_rx_inst.BAUD_CNT_END_HALF = 26; +defparam uart_sdram_inst.uart_tx_inst.BAUD_CNT_END = 52; +defparam uart_sdram_inst.fifo_read_inst.BAUD_CNT_END_HALF = 26; +defparam uart_sdram_inst.fifo_read_inst.BAUD_CNT_END = 52; +defparam sdram_model_plus_inst.addr_bits = 13; +defparam sdram_model_plus_inst.data_bits = 16; +defparam sdram_model_plus_inst.col_bits = 9; +defparam sdram_model_plus_inst.mem_sizes = 2*1024*1024; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//-------------uart_sdram_inst------------- +uart_sdram uart_sdram_inst( + + .sys_clk (sys_clk ), + .sys_rst_n (sys_rst_n ), + .rx (rx ), + + .tx (tx ), + + .sdram_clk (sdram_clk ), + .sdram_cke (sdram_cke ), + .sdram_cs_n (sdram_cs_n ), + .sdram_cas_n (sdram_cas_n ), + .sdram_ras_n (sdram_ras_n ), + .sdram_we_n (sdram_we_n ), + .sdram_ba (sdram_ba ), + .sdram_addr (sdram_addr ), + .sdram_dqm (sdram_dqm ), + .sdram_dq (sdram_dq ) + +); + +//-------------sdram_model_plus_inst------------- +sdram_model_plus sdram_model_plus_inst( + .Dq (sdram_dq ), + .Addr (sdram_addr ), + .Ba (sdram_ba ), + .Clk (sdram_clk ), + .Cke (sdram_cke ), + .Cs_n (sdram_cs_n ), + .Ras_n (sdram_ras_n ), + .Cas_n (sdram_cas_n ), + .We_n (sdram_we_n ), + .Dqm (sdram_dqm ), + .Debug (1'b1 ) +); + +endmodule \ No newline at end of file diff --git a/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/test_data.txt b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/test_data.txt new file mode 100644 index 0000000..f81cb6e --- /dev/null +++ b/smh-ac415-fpga/examples/08_uart_sdram/uart_sdram/sim/test_data.txt @@ -0,0 +1 @@ +01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 \ No newline at end of file diff --git "a/smh-ac415-fpga/examples/08_uart_sdram/\345\256\236\351\252\214\347\216\260\350\261\241.txt" "b/smh-ac415-fpga/examples/08_uart_sdram/\345\256\236\351\252\214\347\216\260\350\261\241.txt" new file mode 100644 index 0000000..165e40b --- /dev/null +++ "b/smh-ac415-fpga/examples/08_uart_sdram/\345\256\236\351\252\214\347\216\260\350\261\241.txt" @@ -0,0 +1,5 @@ +现象：把usb插入电脑，预先安装ch340串口驱动，打开某个串口软件，波特率选择9600，接收发送均选择hex，发送框输入“00112233445566778899”，即10个字节，接收框会显示这10个字节，此中会先把这10个字节存入sdram，在从sdram取出返回给串口显示出来。此例程参考野火fpga例程修改而来。具体可参考野火教程。 + +测试：可以测试sdram是否正常。 + + diff --git "a/smh-ac415-fpga/examples/09_vga/vga/doc/VESA VGA\346\227\266\345\272\217\346\240\207\345\207\206.pdf" "b/smh-ac415-fpga/examples/09_vga/vga/doc/VESA VGA\346\227\266\345\272\217\346\240\207\345\207\206.pdf" new file mode 100644 index 0000000..b0b4015 Binary files /dev/null and "b/smh-ac415-fpga/examples/09_vga/vga/doc/VESA VGA\346\227\266\345\272\217\346\240\207\345\207\206.pdf" differ diff --git a/smh-ac415-fpga/examples/09_vga/vga/doc/vga_colorbar.vsdx b/smh-ac415-fpga/examples/09_vga/vga/doc/vga_colorbar.vsdx new file mode 100644 index 0000000..99486d0 Binary files /dev/null and b/smh-ac415-fpga/examples/09_vga/vga/doc/vga_colorbar.vsdx differ diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/PLLJ_PLLSPE_INFO.txt b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/PLLJ_PLLSPE_INFO.txt new file mode 100644 index 0000000..790cae7 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/PLLJ_PLLSPE_INFO.txt @@ -0,0 +1,5 @@ +PLL_Name clk_gen:clk_gen_inst|altpll:altpll_component|clk_gen_altpll:auto_generated|pll1 +PLLJITTER 30 +PLLSPEmax 84 +PLLSPEmin -53 + diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.ppf b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.ppf new file mode 100644 index 0000000..30a8de7 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.qip b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.qip new file mode 100644 index 0000000..433e305 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clk_gen.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clk_gen.ppf"] diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.v b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.v new file mode 100644 index 0000000..9bf99ee --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.v @@ -0,0 +1,320 @@ +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module clk_gen ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire sub_wire0; + wire [4:0] sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire locked = sub_wire0; + wire [0:0] sub_wire2 = sub_wire1[0:0]; + wire c0 = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .areset (areset), + .inclk (sub_wire4), + .locked (sub_wire0), + .clk (sub_wire1), + .activeclock (), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 2, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 1, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 20000, + altpll_component.intended_device_family = "Cyclone IV E", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clk_gen", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_USED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena2 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.self_reset_on_loss_lock = "OFF", + altpll_component.width_clock = 5; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen_bb.v b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen_bb.v new file mode 100644 index 0000000..1892505 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen_bb.v @@ -0,0 +1,210 @@ +// megafunction wizard: %ALTPLL%VBB% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: clk_gen.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.0 Build 156 04/24/2013 SJ Full Version +// ************************************************************ + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + +module clk_gen ( + areset, + inclk0, + c0, + locked); + + input areset; + input inclk0; + output c0; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 areset; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_gen.mif" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_inst.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_gen_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen_inst.v b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen_inst.v new file mode 100644 index 0000000..9d75f00 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen_inst.v @@ -0,0 +1,6 @@ +clk_gen clk_gen_inst ( + .areset ( areset_sig ), + .inclk0 ( inclk0_sig ), + .c0 ( c0_sig ), + .locked ( locked_sig ) + ); diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..0eb724d --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/ip_core/clk_gen/greybox_tmp/cbx_args.txt @@ -0,0 +1,61 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=2 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=1 +CLK0_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=20000 +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_USED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_USED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_UNUSED +PORT_clk2=PORT_UNUSED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +SELF_RESET_ON_LOSS_LOCK=OFF +WIDTH_CLOCK=5 +DEVICE_FAMILY="Cyclone IV E" +CBX_AUTO_BLACKBOX=ALL +areset +inclk +inclk +clk +locked diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar.sft b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar.sft new file mode 100644 index 0000000..57ef981 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar.sft @@ -0,0 +1,6 @@ +set tool_name "ModelSim (Verilog)" +set corner_file_list { + {{"Slow -8 1.2V 85 Model"} {vga_colorbar_8_1200mv_85c_slow.vo vga_colorbar_8_1200mv_85c_v_slow.sdo}} + {{"Slow -8 1.2V 0 Model"} {vga_colorbar_8_1200mv_0c_slow.vo vga_colorbar_8_1200mv_0c_v_slow.sdo}} + {{"Fast -M 1.2V 0 Model"} {vga_colorbar_min_1200mv_0c_fast.vo vga_colorbar_min_1200mv_0c_v_fast.sdo}} +} diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar.vo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar.vo new file mode 100644 index 0000000..31317fc --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar.vo @@ -0,0 +1,2833 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:42:20" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module vga_colorbar ( + sys_clk, + sys_rst_n, + hsync, + vsync, + rgb); +input sys_clk; +input sys_rst_n; +output hsync; +output vsync; +output [15:0] rgb; + +// Design Ports Information +// hsync => Location: PIN_AA18, I/O Standard: 2.5 V, Current Strength: Default +// vsync => Location: PIN_AB17, I/O Standard: 2.5 V, Current Strength: Default +// rgb[0] => Location: PIN_AB18, I/O Standard: 2.5 V, Current Strength: Default +// rgb[1] => Location: PIN_AA19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[2] => Location: PIN_AB19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[3] => Location: PIN_Y21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[4] => Location: PIN_W19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[5] => Location: PIN_W20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[6] => Location: PIN_U21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[7] => Location: PIN_U22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[8] => Location: PIN_N20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[9] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[10] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[11] => Location: PIN_M22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[12] => Location: PIN_L21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[13] => Location: PIN_L22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[14] => Location: PIN_K21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[15] => Location: PIN_J21, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("vga_colorbar_v.sdo"); +// synopsys translate_on + +wire \vga_ctrl_inst|Add0~4_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \vga_ctrl_inst|Add1~0_combout ; +wire \vga_ctrl_inst|Add1~2_combout ; +wire \vga_ctrl_inst|Add1~4_combout ; +wire \vga_ctrl_inst|Add1~6_combout ; +wire \vga_ctrl_inst|Add1~8_combout ; +wire \vga_ctrl_inst|Add1~10_combout ; +wire \vga_ctrl_inst|Add1~12_combout ; +wire \vga_ctrl_inst|Add1~16_combout ; +wire \vga_ctrl_inst|Equal0~0_combout ; +wire \vga_ctrl_inst|cnt_v[8]~3_combout ; +wire \vga_pic_inst|pix_data[4]~5_combout ; +wire \vga_pic_inst|pix_data~8_combout ; +wire \vga_pic_inst|pix_data~15_combout ; +wire \vga_pic_inst|pix_data~17_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~1 ; +wire \vga_ctrl_inst|Add0~3 ; +wire \vga_ctrl_inst|Add0~5 ; +wire \vga_ctrl_inst|Add0~6_combout ; +wire \vga_ctrl_inst|Add0~7 ; +wire \vga_ctrl_inst|Add0~8_combout ; +wire \vga_ctrl_inst|Add0~9 ; +wire \vga_ctrl_inst|Add0~11 ; +wire \vga_ctrl_inst|Add0~12_combout ; +wire \vga_ctrl_inst|Add0~13 ; +wire \vga_ctrl_inst|Add0~14_combout ; +wire \vga_ctrl_inst|Add0~15 ; +wire \vga_ctrl_inst|Add0~16_combout ; +wire \vga_ctrl_inst|Add0~17 ; +wire \vga_ctrl_inst|Add0~18_combout ; +wire \vga_ctrl_inst|cnt_h~1_combout ; +wire \vga_ctrl_inst|Add0~10_combout ; +wire \vga_ctrl_inst|cnt_h~0_combout ; +wire \vga_ctrl_inst|Equal0~2_combout ; +wire \vga_ctrl_inst|Add0~2_combout ; +wire \vga_ctrl_inst|Equal0~1_combout ; +wire \vga_ctrl_inst|Equal0~3_combout ; +wire \vga_ctrl_inst|cnt_h~2_combout ; +wire \vga_ctrl_inst|LessThan2~0_combout ; +wire \vga_ctrl_inst|LessThan0~0_combout ; +wire \vga_ctrl_inst|cnt_v[0]~9_combout ; +wire \vga_ctrl_inst|cnt_v[2]~8_combout ; +wire \vga_ctrl_inst|cnt_v[4]~6_combout ; +wire \vga_ctrl_inst|always1~1_combout ; +wire \vga_ctrl_inst|cnt_v[1]~0_combout ; +wire \vga_ctrl_inst|always1~2_combout ; +wire \vga_ctrl_inst|cnt_v[3]~7_combout ; +wire \vga_ctrl_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|cnt_v[5]~2_combout ; +wire \vga_ctrl_inst|Add1~1 ; +wire \vga_ctrl_inst|Add1~3 ; +wire \vga_ctrl_inst|Add1~5 ; +wire \vga_ctrl_inst|Add1~7 ; +wire \vga_ctrl_inst|Add1~9 ; +wire \vga_ctrl_inst|Add1~11 ; +wire \vga_ctrl_inst|Add1~13 ; +wire \vga_ctrl_inst|Add1~14_combout ; +wire \vga_ctrl_inst|cnt_v[7]~4_combout ; +wire \vga_ctrl_inst|Add1~15 ; +wire \vga_ctrl_inst|Add1~17 ; +wire \vga_ctrl_inst|Add1~18_combout ; +wire \vga_ctrl_inst|cnt_v[9]~1_combout ; +wire \vga_ctrl_inst|cnt_v[6]~5_combout ; +wire \vga_ctrl_inst|always1~0_combout ; +wire \vga_ctrl_inst|LessThan1~0_combout ; +wire \vga_ctrl_inst|LessThan6~1_combout ; +wire \vga_ctrl_inst|pix_data_req~1_combout ; +wire \vga_ctrl_inst|pix_data_req~2_combout ; +wire \vga_ctrl_inst|LessThan2~1_combout ; +wire \vga_ctrl_inst|rgb_valid~0_combout ; +wire \vga_ctrl_inst|Add2~1_cout ; +wire \vga_ctrl_inst|Add2~3_cout ; +wire \vga_ctrl_inst|Add2~5_cout ; +wire \vga_ctrl_inst|Add2~7_cout ; +wire \vga_ctrl_inst|Add2~9_cout ; +wire \vga_ctrl_inst|Add2~11 ; +wire \vga_ctrl_inst|Add2~12_combout ; +wire \vga_ctrl_inst|Add2~10_combout ; +wire \vga_pic_inst|LessThan14~0_combout ; +wire \vga_ctrl_inst|Add2~13 ; +wire \vga_ctrl_inst|Add2~15 ; +wire \vga_ctrl_inst|Add2~16_combout ; +wire \vga_ctrl_inst|Add2~14_combout ; +wire \vga_pic_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|pix_data_req~0_combout ; +wire \vga_ctrl_inst|LessThan4~0_combout ; +wire \vga_ctrl_inst|pix_data_req~3_combout ; +wire \vga_ctrl_inst|pix_data_req~4_combout ; +wire \vga_pic_inst|pix_data~4_combout ; +wire \vga_pic_inst|pix_data~9_combout ; +wire \vga_pic_inst|LessThan17~0_combout ; +wire \vga_pic_inst|pix_data~6_combout ; +wire \vga_pic_inst|pix_data[4]~10_combout ; +wire \vga_pic_inst|pix_data~11_combout ; +wire \vga_pic_inst|pix_data~12_combout ; +wire \vga_pic_inst|pix_data~13_combout ; +wire \vga_ctrl_inst|rgb[0]~0_combout ; +wire \vga_pic_inst|pix_data[4]~7_combout ; +wire \vga_pic_inst|pix_data~16_combout ; +wire \vga_ctrl_inst|rgb[1]~1_combout ; +wire \vga_pic_inst|pix_data~25_combout ; +wire \vga_ctrl_inst|rgb[5]~2_combout ; +wire \vga_pic_inst|pix_data~18_combout ; +wire \vga_pic_inst|pix_data~14_combout ; +wire \vga_pic_inst|pix_data~26_combout ; +wire \vga_pic_inst|pix_data~19_combout ; +wire \vga_ctrl_inst|rgb[7]~3_combout ; +wire \vga_pic_inst|LessThan2~2_combout ; +wire \vga_pic_inst|pix_data~20_combout ; +wire \vga_pic_inst|pix_data~21_combout ; +wire \vga_ctrl_inst|rgb[10]~4_combout ; +wire \vga_pic_inst|pix_data~22_combout ; +wire \vga_pic_inst|pix_data~23_combout ; +wire \vga_ctrl_inst|rgb[11]~5_combout ; +wire \vga_pic_inst|pix_data~24_combout ; +wire \vga_ctrl_inst|rgb[12]~6_combout ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [9:0] \vga_ctrl_inst|cnt_v ; +wire [9:0] \vga_ctrl_inst|cnt_h ; +wire [15:0] \vga_pic_inst|pix_data ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: LCCOMB_X35_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~4 ( +// Equation(s): +// \vga_ctrl_inst|Add0~4_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|Add0~3 $ (GND))) # (!\vga_ctrl_inst|cnt_h [2] & (!\vga_ctrl_inst|Add0~3 & VCC)) +// \vga_ctrl_inst|Add0~5 = CARRY((\vga_ctrl_inst|cnt_h [2] & !\vga_ctrl_inst|Add0~3 )) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~3 ), + .combout(\vga_ctrl_inst|Add0~4_combout ), + .cout(\vga_ctrl_inst|Add0~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 6891; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~0 ( +// Equation(s): +// \vga_ctrl_inst|Add1~0_combout = \vga_ctrl_inst|cnt_v [0] $ (VCC) +// \vga_ctrl_inst|Add1~1 = CARRY(\vga_ctrl_inst|cnt_v [0]) + + .dataa(\vga_ctrl_inst|cnt_v [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add1~0_combout ), + .cout(\vga_ctrl_inst|Add1~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~0 .lut_mask = 16'h55AA; +defparam \vga_ctrl_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~2 ( +// Equation(s): +// \vga_ctrl_inst|Add1~2_combout = (\vga_ctrl_inst|cnt_v [1] & (!\vga_ctrl_inst|Add1~1 )) # (!\vga_ctrl_inst|cnt_v [1] & ((\vga_ctrl_inst|Add1~1 ) # (GND))) +// \vga_ctrl_inst|Add1~3 = CARRY((!\vga_ctrl_inst|Add1~1 ) # (!\vga_ctrl_inst|cnt_v [1])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~1 ), + .combout(\vga_ctrl_inst|Add1~2_combout ), + .cout(\vga_ctrl_inst|Add1~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~4 ( +// Equation(s): +// \vga_ctrl_inst|Add1~4_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|Add1~3 $ (GND))) # (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|Add1~3 & VCC)) +// \vga_ctrl_inst|Add1~5 = CARRY((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Add1~3 )) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~3 ), + .combout(\vga_ctrl_inst|Add1~4_combout ), + .cout(\vga_ctrl_inst|Add1~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~6 ( +// Equation(s): +// \vga_ctrl_inst|Add1~6_combout = (\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|Add1~5 )) # (!\vga_ctrl_inst|cnt_v [3] & ((\vga_ctrl_inst|Add1~5 ) # (GND))) +// \vga_ctrl_inst|Add1~7 = CARRY((!\vga_ctrl_inst|Add1~5 ) # (!\vga_ctrl_inst|cnt_v [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~5 ), + .combout(\vga_ctrl_inst|Add1~6_combout ), + .cout(\vga_ctrl_inst|Add1~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~8 ( +// Equation(s): +// \vga_ctrl_inst|Add1~8_combout = (\vga_ctrl_inst|cnt_v [4] & (\vga_ctrl_inst|Add1~7 $ (GND))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|Add1~7 & VCC)) +// \vga_ctrl_inst|Add1~9 = CARRY((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Add1~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~7 ), + .combout(\vga_ctrl_inst|Add1~8_combout ), + .cout(\vga_ctrl_inst|Add1~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~10 ( +// Equation(s): +// \vga_ctrl_inst|Add1~10_combout = (\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|Add1~9 )) # (!\vga_ctrl_inst|cnt_v [5] & ((\vga_ctrl_inst|Add1~9 ) # (GND))) +// \vga_ctrl_inst|Add1~11 = CARRY((!\vga_ctrl_inst|Add1~9 ) # (!\vga_ctrl_inst|cnt_v [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~9 ), + .combout(\vga_ctrl_inst|Add1~10_combout ), + .cout(\vga_ctrl_inst|Add1~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~10 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~12 ( +// Equation(s): +// \vga_ctrl_inst|Add1~12_combout = (\vga_ctrl_inst|cnt_v [6] & (\vga_ctrl_inst|Add1~11 $ (GND))) # (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|Add1~11 & VCC)) +// \vga_ctrl_inst|Add1~13 = CARRY((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Add1~11 )) + + .dataa(\vga_ctrl_inst|cnt_v [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~11 ), + .combout(\vga_ctrl_inst|Add1~12_combout ), + .cout(\vga_ctrl_inst|Add1~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~16 ( +// Equation(s): +// \vga_ctrl_inst|Add1~16_combout = (\vga_ctrl_inst|cnt_v [8] & (\vga_ctrl_inst|Add1~15 $ (GND))) # (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|Add1~15 & VCC)) +// \vga_ctrl_inst|Add1~17 = CARRY((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Add1~15 )) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~15 ), + .combout(\vga_ctrl_inst|Add1~16_combout ), + .cout(\vga_ctrl_inst|Add1~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~16 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y23_N13 +dffeas \vga_ctrl_inst|cnt_v[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~0 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~0_combout = (\vga_ctrl_inst|cnt_h [8] & \vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~0 .lut_mask = 16'hCC00; +defparam \vga_ctrl_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N13 +dffeas \vga_ctrl_inst|cnt_h[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[8]~3 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[8]~3_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~16_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [8])))) + + .dataa(\vga_ctrl_inst|Add1~16_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [8]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8]~3 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[8]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~5 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~5_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~16_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~16_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~5 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~8 ( +// Equation(s): +// \vga_pic_inst|pix_data~8_combout = (\vga_ctrl_inst|Add2~16_combout ) # (((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) # (!\vga_ctrl_inst|Add2~10_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~8 .lut_mask = 16'hFBFF; +defparam \vga_pic_inst|pix_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N10 +cycloneive_lcell_comb \vga_pic_inst|pix_data~15 ( +// Equation(s): +// \vga_pic_inst|pix_data~15_combout = (\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|pix_data~11_combout & ((!\vga_pic_inst|pix_data[4]~10_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_pic_inst|pix_data~11_combout ), + .datab(\vga_pic_inst|pix_data~14_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data[4]~5_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~15_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~15 .lut_mask = 16'h0ACC; +defparam \vga_pic_inst|pix_data~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~17 ( +// Equation(s): +// \vga_pic_inst|pix_data~17_combout = (\vga_ctrl_inst|Add2~12_combout & (!\vga_ctrl_inst|Add2~14_combout )) # (!\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|Add2~14_combout & !\vga_ctrl_inst|Add2~10_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~17_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~17 .lut_mask = 16'h0C3C; +defparam \vga_pic_inst|pix_data~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N30 +cycloneive_io_obuf \hsync~output ( + .i(!\vga_ctrl_inst|LessThan0~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(hsync), + .obar()); +// synopsys translate_off +defparam \hsync~output .bus_hold = "false"; +defparam \hsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X28_Y0_N2 +cycloneive_io_obuf \vsync~output ( + .i(!\vga_ctrl_inst|LessThan1~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(vsync), + .obar()); +// synopsys translate_off +defparam \vsync~output .bus_hold = "false"; +defparam \vsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X32_Y0_N2 +cycloneive_io_obuf \rgb[0]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[0]), + .obar()); +// synopsys translate_off +defparam \rgb[0]~output .bus_hold = "false"; +defparam \rgb[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N23 +cycloneive_io_obuf \rgb[1]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[1]), + .obar()); +// synopsys translate_off +defparam \rgb[1]~output .bus_hold = "false"; +defparam \rgb[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N16 +cycloneive_io_obuf \rgb[2]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[2]), + .obar()); +// synopsys translate_off +defparam \rgb[2]~output .bus_hold = "false"; +defparam \rgb[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y4_N9 +cycloneive_io_obuf \rgb[3]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[3]), + .obar()); +// synopsys translate_off +defparam \rgb[3]~output .bus_hold = "false"; +defparam \rgb[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N9 +cycloneive_io_obuf \rgb[4]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[4]), + .obar()); +// synopsys translate_off +defparam \rgb[4]~output .bus_hold = "false"; +defparam \rgb[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N16 +cycloneive_io_obuf \rgb[5]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[5]), + .obar()); +// synopsys translate_off +defparam \rgb[5]~output .bus_hold = "false"; +defparam \rgb[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N2 +cycloneive_io_obuf \rgb[6]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[6]), + .obar()); +// synopsys translate_off +defparam \rgb[6]~output .bus_hold = "false"; +defparam \rgb[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N9 +cycloneive_io_obuf \rgb[7]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[7]), + .obar()); +// synopsys translate_off +defparam \rgb[7]~output .bus_hold = "false"; +defparam \rgb[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y12_N16 +cycloneive_io_obuf \rgb[8]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[8]), + .obar()); +// synopsys translate_off +defparam \rgb[8]~output .bus_hold = "false"; +defparam \rgb[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N9 +cycloneive_io_obuf \rgb[9]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[9]), + .obar()); +// synopsys translate_off +defparam \rgb[9]~output .bus_hold = "false"; +defparam \rgb[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y14_N23 +cycloneive_io_obuf \rgb[10]~output ( + .i(\vga_ctrl_inst|rgb[10]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[10]), + .obar()); +// synopsys translate_off +defparam \rgb[10]~output .bus_hold = "false"; +defparam \rgb[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N2 +cycloneive_io_obuf \rgb[11]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[11]), + .obar()); +// synopsys translate_off +defparam \rgb[11]~output .bus_hold = "false"; +defparam \rgb[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N16 +cycloneive_io_obuf \rgb[12]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[12]), + .obar()); +// synopsys translate_off +defparam \rgb[12]~output .bus_hold = "false"; +defparam \rgb[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N23 +cycloneive_io_obuf \rgb[13]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[13]), + .obar()); +// synopsys translate_off +defparam \rgb[13]~output .bus_hold = "false"; +defparam \rgb[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y19_N9 +cycloneive_io_obuf \rgb[14]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[14]), + .obar()); +// synopsys translate_off +defparam \rgb[14]~output .bus_hold = "false"; +defparam \rgb[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y20_N23 +cycloneive_io_obuf \rgb[15]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[15]), + .obar()); +// synopsys translate_off +defparam \rgb[15]~output .bus_hold = "false"; +defparam \rgb[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~0 ( +// Equation(s): +// \vga_ctrl_inst|Add0~0_combout = \vga_ctrl_inst|cnt_h [0] $ (VCC) +// \vga_ctrl_inst|Add0~1 = CARRY(\vga_ctrl_inst|cnt_h [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add0~0_combout ), + .cout(\vga_ctrl_inst|Add0~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X35_Y3_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N10 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\sys_rst_n~input_o ) # (!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .datac(\sys_rst_n~input_o ), + .datad(gnd), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h7F7F; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X35_Y23_N9 +dffeas \vga_ctrl_inst|cnt_h[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~2 ( +// Equation(s): +// \vga_ctrl_inst|Add0~2_combout = (\vga_ctrl_inst|cnt_h [1] & (!\vga_ctrl_inst|Add0~1 )) # (!\vga_ctrl_inst|cnt_h [1] & ((\vga_ctrl_inst|Add0~1 ) # (GND))) +// \vga_ctrl_inst|Add0~3 = CARRY((!\vga_ctrl_inst|Add0~1 ) # (!\vga_ctrl_inst|cnt_h [1])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~1 ), + .combout(\vga_ctrl_inst|Add0~2_combout ), + .cout(\vga_ctrl_inst|Add0~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~6 ( +// Equation(s): +// \vga_ctrl_inst|Add0~6_combout = (\vga_ctrl_inst|cnt_h [3] & (!\vga_ctrl_inst|Add0~5 )) # (!\vga_ctrl_inst|cnt_h [3] & ((\vga_ctrl_inst|Add0~5 ) # (GND))) +// \vga_ctrl_inst|Add0~7 = CARRY((!\vga_ctrl_inst|Add0~5 ) # (!\vga_ctrl_inst|cnt_h [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~5 ), + .combout(\vga_ctrl_inst|Add0~6_combout ), + .cout(\vga_ctrl_inst|Add0~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N15 +dffeas \vga_ctrl_inst|cnt_h[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~8 ( +// Equation(s): +// \vga_ctrl_inst|Add0~8_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Add0~7 $ (GND))) # (!\vga_ctrl_inst|cnt_h [4] & (!\vga_ctrl_inst|Add0~7 & VCC)) +// \vga_ctrl_inst|Add0~9 = CARRY((\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add0~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~7 ), + .combout(\vga_ctrl_inst|Add0~8_combout ), + .cout(\vga_ctrl_inst|Add0~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N17 +dffeas \vga_ctrl_inst|cnt_h[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~10 ( +// Equation(s): +// \vga_ctrl_inst|Add0~10_combout = (\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|Add0~9 )) # (!\vga_ctrl_inst|cnt_h [5] & ((\vga_ctrl_inst|Add0~9 ) # (GND))) +// \vga_ctrl_inst|Add0~11 = CARRY((!\vga_ctrl_inst|Add0~9 ) # (!\vga_ctrl_inst|cnt_h [5])) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~9 ), + .combout(\vga_ctrl_inst|Add0~10_combout ), + .cout(\vga_ctrl_inst|Add0~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~12 ( +// Equation(s): +// \vga_ctrl_inst|Add0~12_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add0~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add0~11 & VCC)) +// \vga_ctrl_inst|Add0~13 = CARRY((\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add0~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~11 ), + .combout(\vga_ctrl_inst|Add0~12_combout ), + .cout(\vga_ctrl_inst|Add0~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N21 +dffeas \vga_ctrl_inst|cnt_h[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~14 ( +// Equation(s): +// \vga_ctrl_inst|Add0~14_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add0~13 )) # (!\vga_ctrl_inst|cnt_h [7] & ((\vga_ctrl_inst|Add0~13 ) # (GND))) +// \vga_ctrl_inst|Add0~15 = CARRY((!\vga_ctrl_inst|Add0~13 ) # (!\vga_ctrl_inst|cnt_h [7])) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~13 ), + .combout(\vga_ctrl_inst|Add0~14_combout ), + .cout(\vga_ctrl_inst|Add0~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N23 +dffeas \vga_ctrl_inst|cnt_h[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~16 ( +// Equation(s): +// \vga_ctrl_inst|Add0~16_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add0~15 $ (GND))) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add0~15 & VCC)) +// \vga_ctrl_inst|Add0~17 = CARRY((\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add0~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~15 ), + .combout(\vga_ctrl_inst|Add0~16_combout ), + .cout(\vga_ctrl_inst|Add0~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~18 ( +// Equation(s): +// \vga_ctrl_inst|Add0~18_combout = \vga_ctrl_inst|Add0~17 $ (\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(\vga_ctrl_inst|Add0~17 ), + .combout(\vga_ctrl_inst|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~1_combout = (!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|Add0~18_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|Add0~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~1 .lut_mask = 16'h3030; +defparam \vga_ctrl_inst|cnt_h~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N1 +dffeas \vga_ctrl_inst|cnt_h[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~0_combout = (\vga_ctrl_inst|Add0~10_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~10_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~0 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N25 +dffeas \vga_ctrl_inst|cnt_h[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~2 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~2_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|cnt_h [9] & (!\vga_ctrl_inst|cnt_h [5] & !\vga_ctrl_inst|cnt_h [6]))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [9]), + .datac(\vga_ctrl_inst|cnt_h [5]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~2 .lut_mask = 16'h0008; +defparam \vga_ctrl_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N11 +dffeas \vga_ctrl_inst|cnt_h[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~1 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~1_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|cnt_h [3] & (\vga_ctrl_inst|cnt_h [0] & \vga_ctrl_inst|cnt_h [1]))) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(\vga_ctrl_inst|cnt_h [0]), + .datad(\vga_ctrl_inst|cnt_h [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~3 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~3_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Equal0~2_combout & (\vga_ctrl_inst|Equal0~1_combout & !\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(\vga_ctrl_inst|Equal0~2_combout ), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|cnt_h [7]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~3 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~2_combout = (\vga_ctrl_inst|Add0~16_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~16_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~2 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N3 +dffeas \vga_ctrl_inst|cnt_h[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~0_combout = (!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~0 .lut_mask = 16'h0033; +defparam \vga_ctrl_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~0_combout = (\vga_ctrl_inst|cnt_h [7]) # (((\vga_ctrl_inst|cnt_h [6] & \vga_ctrl_inst|cnt_h [5])) # (!\vga_ctrl_inst|LessThan2~0_combout )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~0 .lut_mask = 16'hEFAF; +defparam \vga_ctrl_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[0]~9 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[0]~9_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~0_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [0])))) + + .dataa(\vga_ctrl_inst|Add1~0_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0]~9 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N29 +dffeas \vga_ctrl_inst|cnt_v[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[2]~8 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[2]~8_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~4_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [2])))) + + .dataa(\vga_ctrl_inst|Add1~4_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2]~8 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N5 +dffeas \vga_ctrl_inst|cnt_v[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[4]~6 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[4]~6_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~8_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [4])))) + + .dataa(\vga_ctrl_inst|Add1~8_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [4]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4]~6 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[4]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N1 +dffeas \vga_ctrl_inst|cnt_v[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|always1~1 ( +// Equation(s): +// \vga_ctrl_inst|always1~1_combout = (\vga_ctrl_inst|cnt_v [9] & (\vga_ctrl_inst|cnt_v [3] & (\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4]))) + + .dataa(\vga_ctrl_inst|cnt_v [9]), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~1 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|always1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[1]~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[1]~0_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~2_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [1])))) + + .dataa(\vga_ctrl_inst|Add1~2_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1]~0 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N17 +dffeas \vga_ctrl_inst|cnt_v[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|always1~2 ( +// Equation(s): +// \vga_ctrl_inst|always1~2_combout = (\vga_ctrl_inst|always1~0_combout & (!\vga_ctrl_inst|cnt_v [0] & (\vga_ctrl_inst|always1~1_combout & !\vga_ctrl_inst|cnt_v [1]))) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(\vga_ctrl_inst|always1~1_combout ), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~2 .lut_mask = 16'h0020; +defparam \vga_ctrl_inst|always1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[3]~7 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[3]~7_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~6_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [3])))) + + .dataa(\vga_ctrl_inst|Add1~6_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3]~7 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N3 +dffeas \vga_ctrl_inst|cnt_v[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~0_combout = (!\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~0 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[5]~2_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~10_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [5])))) + + .dataa(\vga_ctrl_inst|Add1~10_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5]~2 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N19 +dffeas \vga_ctrl_inst|cnt_v[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~14 ( +// Equation(s): +// \vga_ctrl_inst|Add1~14_combout = (\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|Add1~13 )) # (!\vga_ctrl_inst|cnt_v [7] & ((\vga_ctrl_inst|Add1~13 ) # (GND))) +// \vga_ctrl_inst|Add1~15 = CARRY((!\vga_ctrl_inst|Add1~13 ) # (!\vga_ctrl_inst|cnt_v [7])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~13 ), + .combout(\vga_ctrl_inst|Add1~14_combout ), + .cout(\vga_ctrl_inst|Add1~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~14 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[7]~4 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[7]~4_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~14_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [7])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~14_combout ), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7]~4 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N3 +dffeas \vga_ctrl_inst|cnt_v[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~18 ( +// Equation(s): +// \vga_ctrl_inst|Add1~18_combout = \vga_ctrl_inst|Add1~17 $ (\vga_ctrl_inst|cnt_v [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [9]), + .cin(\vga_ctrl_inst|Add1~17 ), + .combout(\vga_ctrl_inst|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[9]~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[9]~1_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~18_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [9])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~18_combout ), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9]~1 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N1 +dffeas \vga_ctrl_inst|cnt_v[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[6]~5 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[6]~5_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~12_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [6])))) + + .dataa(\vga_ctrl_inst|Add1~12_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6]~5 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N5 +dffeas \vga_ctrl_inst|cnt_v[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|always1~0 ( +// Equation(s): +// \vga_ctrl_inst|always1~0_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan1~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan1~0_combout = ((\vga_ctrl_inst|cnt_v [1]) # ((\vga_ctrl_inst|cnt_v [9]) # (!\vga_ctrl_inst|always1~0_combout ))) # (!\vga_ctrl_inst|LessThan6~0_combout ) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan1~0 .lut_mask = 16'hFDFF; +defparam \vga_ctrl_inst|LessThan1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~1_combout = (!\vga_ctrl_inst|cnt_v [1]) # (!\vga_ctrl_inst|cnt_v [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~1 .lut_mask = 16'h33FF; +defparam \vga_ctrl_inst|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N30 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~1_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~1 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~2 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~2_combout = (\vga_ctrl_inst|LessThan6~0_combout & ((\vga_ctrl_inst|LessThan6~1_combout & (\vga_ctrl_inst|pix_data_req~1_combout )) # (!\vga_ctrl_inst|LessThan6~1_combout & ((\vga_ctrl_inst|always1~0_combout ))))) # +// (!\vga_ctrl_inst|LessThan6~0_combout & (((\vga_ctrl_inst|always1~0_combout )))) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|LessThan6~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~2 .lut_mask = 16'hF780; +defparam \vga_ctrl_inst|pix_data_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~1_combout = (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~1 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|rgb_valid~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb_valid~0_combout = (\vga_ctrl_inst|Equal0~0_combout & (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|LessThan2~0_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout & (((\vga_ctrl_inst|cnt_h [7] & +// !\vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|LessThan2~0_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb_valid~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb_valid~0 .lut_mask = 16'h0745; +defparam \vga_ctrl_inst|rgb_valid~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~1 ( +// Equation(s): +// \vga_ctrl_inst|Add2~1_cout = CARRY((\vga_ctrl_inst|cnt_h [1] & \vga_ctrl_inst|cnt_h [0])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\vga_ctrl_inst|Add2~1_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~1 .lut_mask = 16'h0088; +defparam \vga_ctrl_inst|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~3 ( +// Equation(s): +// \vga_ctrl_inst|Add2~3_cout = CARRY((!\vga_ctrl_inst|Add2~1_cout ) # (!\vga_ctrl_inst|cnt_h [2])) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~1_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~3_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~3 .lut_mask = 16'h005F; +defparam \vga_ctrl_inst|Add2~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~5 ( +// Equation(s): +// \vga_ctrl_inst|Add2~5_cout = CARRY((\vga_ctrl_inst|cnt_h [3] & !\vga_ctrl_inst|Add2~3_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~3_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~5_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~5 .lut_mask = 16'h000A; +defparam \vga_ctrl_inst|Add2~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~7 ( +// Equation(s): +// \vga_ctrl_inst|Add2~7_cout = CARRY((!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add2~5_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~5_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~7_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~7 .lut_mask = 16'h0005; +defparam \vga_ctrl_inst|Add2~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~9 ( +// Equation(s): +// \vga_ctrl_inst|Add2~9_cout = CARRY((\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|Add2~7_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~7_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~9_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~9 .lut_mask = 16'h00AF; +defparam \vga_ctrl_inst|Add2~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~10 ( +// Equation(s): +// \vga_ctrl_inst|Add2~10_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add2~9_cout & VCC)) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add2~9_cout )) +// \vga_ctrl_inst|Add2~11 = CARRY((!\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add2~9_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~9_cout ), + .combout(\vga_ctrl_inst|Add2~10_combout ), + .cout(\vga_ctrl_inst|Add2~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~10 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~12 ( +// Equation(s): +// \vga_ctrl_inst|Add2~12_combout = (\vga_ctrl_inst|cnt_h [7] & (\vga_ctrl_inst|Add2~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add2~11 & VCC)) +// \vga_ctrl_inst|Add2~13 = CARRY((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|Add2~11 )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~11 ), + .combout(\vga_ctrl_inst|Add2~12_combout ), + .cout(\vga_ctrl_inst|Add2~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N24 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~0 ( +// Equation(s): +// \vga_pic_inst|LessThan14~0_combout = (\vga_ctrl_inst|Add2~12_combout & \vga_ctrl_inst|Add2~10_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~0 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|LessThan14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~14 ( +// Equation(s): +// \vga_ctrl_inst|Add2~14_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add2~13 & VCC)) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add2~13 )) +// \vga_ctrl_inst|Add2~15 = CARRY((!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add2~13 )) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~13 ), + .combout(\vga_ctrl_inst|Add2~14_combout ), + .cout(\vga_ctrl_inst|Add2~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~14 .lut_mask = 16'hA505; +defparam \vga_ctrl_inst|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~16 ( +// Equation(s): +// \vga_ctrl_inst|Add2~16_combout = \vga_ctrl_inst|cnt_h [9] $ (\vga_ctrl_inst|Add2~15 ) + + .dataa(\vga_ctrl_inst|cnt_h [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\vga_ctrl_inst|Add2~15 ), + .combout(\vga_ctrl_inst|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~16 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|Add2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N2 +cycloneive_lcell_comb \vga_pic_inst|LessThan6~0 ( +// Equation(s): +// \vga_pic_inst|LessThan6~0_combout = ((\vga_pic_inst|LessThan14~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (\vga_ctrl_inst|Add2~14_combout ))) # (!\vga_ctrl_inst|pix_data_req~4_combout ) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|LessThan14~0_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan6~0 .lut_mask = 16'hFFFD; +defparam \vga_pic_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~0_combout = (!\vga_ctrl_inst|always1~0_combout & \vga_ctrl_inst|cnt_v [9]) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~0 .lut_mask = 16'h5050; +defparam \vga_ctrl_inst|pix_data_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan4~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan4~0_combout = (\vga_ctrl_inst|LessThan2~0_combout & (((!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan4~0 .lut_mask = 16'h7030; +defparam \vga_ctrl_inst|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~3 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~3_combout = ((!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout ) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~3 .lut_mask = 16'h5755; +defparam \vga_ctrl_inst|pix_data_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~4 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (!\vga_ctrl_inst|LessThan4~0_combout & \vga_ctrl_inst|pix_data_req~3_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|LessThan4~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~4 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|pix_data_req~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~4 ( +// Equation(s): +// \vga_pic_inst|pix_data~4_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~4 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~9 ( +// Equation(s): +// \vga_pic_inst|pix_data~9_combout = (\vga_pic_inst|pix_data~8_combout & ((\vga_pic_inst|LessThan6~0_combout ) # ((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data~8_combout & +// (((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) + + .dataa(\vga_pic_inst|pix_data~8_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~9 .lut_mask = 16'h8F88; +defparam \vga_pic_inst|pix_data~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N8 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~0 ( +// Equation(s): +// \vga_pic_inst|LessThan17~0_combout = (\vga_ctrl_inst|Add2~12_combout ) # ((\vga_ctrl_inst|Add2~10_combout ) # ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout ))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~0 .lut_mask = 16'hFEFF; +defparam \vga_pic_inst|LessThan17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~6 ( +// Equation(s): +// \vga_pic_inst|pix_data~6_combout = ((\vga_pic_inst|LessThan17~0_combout & ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|pix_data~4_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~6 .lut_mask = 16'hF755; +defparam \vga_pic_inst|pix_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N22 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~10 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~10_combout = (!\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|Add2~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~10 .lut_mask = 16'h0FFF; +defparam \vga_pic_inst|pix_data[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~11 ( +// Equation(s): +// \vga_pic_inst|pix_data~11_combout = (\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~10_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~11 .lut_mask = 16'h0080; +defparam \vga_pic_inst|pix_data~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data~12 ( +// Equation(s): +// \vga_pic_inst|pix_data~12_combout = (\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data[4]~10_combout ) # (!\vga_pic_inst|pix_data~11_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|LessThan17~0_combout )) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan17~0_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~12 .lut_mask = 16'hE4EE; +defparam \vga_pic_inst|pix_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N16 +cycloneive_lcell_comb \vga_pic_inst|pix_data~13 ( +// Equation(s): +// \vga_pic_inst|pix_data~13_combout = ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~7_combout ), + .datab(\vga_pic_inst|pix_data~9_combout ), + .datac(\vga_pic_inst|pix_data~6_combout ), + .datad(\vga_pic_inst|pix_data~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~13 .lut_mask = 16'h80FF; +defparam \vga_pic_inst|pix_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N17 +dffeas \vga_pic_inst|pix_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[0] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[0]~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb[0]~0_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_ctrl_inst|rgb_valid~0_combout & (\vga_pic_inst|pix_data [0] & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|rgb_valid~0_combout ), + .datac(\vga_pic_inst|pix_data [0]), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[0]~0 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~7 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~7_combout = (!\vga_ctrl_inst|Add2~16_combout & (\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|Add2~12_combout )))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~7 .lut_mask = 16'h0700; +defparam \vga_pic_inst|pix_data[4]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~16 ( +// Equation(s): +// \vga_pic_inst|pix_data~16_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~9_combout ), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~16 .lut_mask = 16'hEAAA; +defparam \vga_pic_inst|pix_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N19 +dffeas \vga_pic_inst|pix_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[1]~1 ( +// Equation(s): +// \vga_ctrl_inst|rgb[1]~1_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [4]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[1]~1 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~25 ( +// Equation(s): +// \vga_pic_inst|pix_data~25_combout = (\vga_ctrl_inst|Add2~16_combout & (((!\vga_pic_inst|LessThan17~0_combout )))) # (!\vga_ctrl_inst|Add2~16_combout & ((\vga_ctrl_inst|pix_data_req~4_combout & (\vga_pic_inst|pix_data~17_combout )) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_pic_inst|LessThan17~0_combout ))))) + + .dataa(\vga_pic_inst|pix_data~17_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~25_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~25 .lut_mask = 16'h20EF; +defparam \vga_pic_inst|pix_data~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N13 +dffeas \vga_pic_inst|pix_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[8] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|rgb[5]~2_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [8]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[5]~2 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~18 ( +// Equation(s): +// \vga_pic_inst|pix_data~18_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~12_combout & !\vga_ctrl_inst|Add2~10_combout )) # (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout +// )))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~18 .lut_mask = 16'h4060; +defparam \vga_pic_inst|pix_data~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~14 ( +// Equation(s): +// \vga_pic_inst|pix_data~14_combout = (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~14_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~14 .lut_mask = 16'h0030; +defparam \vga_pic_inst|pix_data~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~26 ( +// Equation(s): +// \vga_pic_inst|pix_data~26_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~16_combout & ((\vga_pic_inst|pix_data~14_combout ))) # (!\vga_ctrl_inst|Add2~16_combout & (\vga_pic_inst|pix_data~18_combout )))) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|pix_data~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|pix_data~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~26_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~26 .lut_mask = 16'hFD08; +defparam \vga_pic_inst|pix_data~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~19 ( +// Equation(s): +// \vga_pic_inst|pix_data~19_combout = (\vga_pic_inst|pix_data~26_combout & \vga_pic_inst|pix_data~6_combout ) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(gnd), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~19_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~19 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|pix_data~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N1 +dffeas \vga_pic_inst|pix_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[7]~3 ( +// Equation(s): +// \vga_ctrl_inst|rgb[7]~3_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [9]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[7]~3 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N6 +cycloneive_lcell_comb \vga_pic_inst|LessThan2~2 ( +// Equation(s): +// \vga_pic_inst|LessThan2~2_combout = (\vga_pic_inst|LessThan17~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_pic_inst|LessThan17~0_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan2~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan2~2 .lut_mask = 16'hEEFF; +defparam \vga_pic_inst|LessThan2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~20 ( +// Equation(s): +// \vga_pic_inst|pix_data~20_combout = (!\vga_ctrl_inst|Add2~16_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~20 .lut_mask = 16'h0500; +defparam \vga_pic_inst|pix_data~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~21 ( +// Equation(s): +// \vga_pic_inst|pix_data~21_combout = (\vga_pic_inst|LessThan2~2_combout & ((\vga_pic_inst|pix_data~26_combout ) # ((\vga_pic_inst|pix_data~4_combout & \vga_pic_inst|pix_data~20_combout )))) + + .dataa(\vga_pic_inst|pix_data~4_combout ), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(\vga_pic_inst|LessThan2~2_combout ), + .datad(\vga_pic_inst|pix_data~20_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~21_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~21 .lut_mask = 16'hE0C0; +defparam \vga_pic_inst|pix_data~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N27 +dffeas \vga_pic_inst|pix_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[10] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[10]~4 ( +// Equation(s): +// \vga_ctrl_inst|rgb[10]~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [10]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [10]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[10]~4 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N20 +cycloneive_lcell_comb \vga_pic_inst|pix_data~22 ( +// Equation(s): +// \vga_pic_inst|pix_data~22_combout = ((\vga_pic_inst|pix_data[4]~5_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout ))) # (!\vga_pic_inst|LessThan6~0_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~22 .lut_mask = 16'h3B33; +defparam \vga_pic_inst|pix_data~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~23 ( +// Equation(s): +// \vga_pic_inst|pix_data~23_combout = ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|LessThan2~2_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|pix_data[4]~7_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~23_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~23 .lut_mask = 16'hF733; +defparam \vga_pic_inst|pix_data~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N29 +dffeas \vga_pic_inst|pix_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[11]~5 ( +// Equation(s): +// \vga_ctrl_inst|rgb[11]~5_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [13] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [13]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[11]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[11]~5 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[11]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~24 ( +// Equation(s): +// \vga_pic_inst|pix_data~24_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|LessThan2~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~24_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~24 .lut_mask = 16'hEAEE; +defparam \vga_pic_inst|pix_data~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N31 +dffeas \vga_pic_inst|pix_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[15] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[12]~6 ( +// Equation(s): +// \vga_ctrl_inst|rgb[12]~6_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [15] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [15]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[12]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[12]~6 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[12]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_0c_slow.vo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_0c_slow.vo new file mode 100644 index 0000000..d5b549e --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_0c_slow.vo @@ -0,0 +1,2833 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:42:20" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module vga_colorbar ( + sys_clk, + sys_rst_n, + hsync, + vsync, + rgb); +input sys_clk; +input sys_rst_n; +output hsync; +output vsync; +output [15:0] rgb; + +// Design Ports Information +// hsync => Location: PIN_AA18, I/O Standard: 2.5 V, Current Strength: Default +// vsync => Location: PIN_AB17, I/O Standard: 2.5 V, Current Strength: Default +// rgb[0] => Location: PIN_AB18, I/O Standard: 2.5 V, Current Strength: Default +// rgb[1] => Location: PIN_AA19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[2] => Location: PIN_AB19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[3] => Location: PIN_Y21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[4] => Location: PIN_W19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[5] => Location: PIN_W20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[6] => Location: PIN_U21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[7] => Location: PIN_U22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[8] => Location: PIN_N20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[9] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[10] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[11] => Location: PIN_M22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[12] => Location: PIN_L21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[13] => Location: PIN_L22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[14] => Location: PIN_K21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[15] => Location: PIN_J21, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("vga_colorbar_8_1200mv_0c_v_slow.sdo"); +// synopsys translate_on + +wire \vga_ctrl_inst|Add0~4_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \vga_ctrl_inst|Add1~0_combout ; +wire \vga_ctrl_inst|Add1~2_combout ; +wire \vga_ctrl_inst|Add1~4_combout ; +wire \vga_ctrl_inst|Add1~6_combout ; +wire \vga_ctrl_inst|Add1~8_combout ; +wire \vga_ctrl_inst|Add1~10_combout ; +wire \vga_ctrl_inst|Add1~12_combout ; +wire \vga_ctrl_inst|Add1~16_combout ; +wire \vga_ctrl_inst|Equal0~0_combout ; +wire \vga_ctrl_inst|cnt_v[8]~3_combout ; +wire \vga_pic_inst|pix_data[4]~5_combout ; +wire \vga_pic_inst|pix_data~8_combout ; +wire \vga_pic_inst|pix_data~15_combout ; +wire \vga_pic_inst|pix_data~17_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~1 ; +wire \vga_ctrl_inst|Add0~3 ; +wire \vga_ctrl_inst|Add0~5 ; +wire \vga_ctrl_inst|Add0~6_combout ; +wire \vga_ctrl_inst|Add0~7 ; +wire \vga_ctrl_inst|Add0~8_combout ; +wire \vga_ctrl_inst|Add0~9 ; +wire \vga_ctrl_inst|Add0~11 ; +wire \vga_ctrl_inst|Add0~12_combout ; +wire \vga_ctrl_inst|Add0~13 ; +wire \vga_ctrl_inst|Add0~14_combout ; +wire \vga_ctrl_inst|Add0~15 ; +wire \vga_ctrl_inst|Add0~16_combout ; +wire \vga_ctrl_inst|Add0~17 ; +wire \vga_ctrl_inst|Add0~18_combout ; +wire \vga_ctrl_inst|cnt_h~1_combout ; +wire \vga_ctrl_inst|Add0~10_combout ; +wire \vga_ctrl_inst|cnt_h~0_combout ; +wire \vga_ctrl_inst|Equal0~2_combout ; +wire \vga_ctrl_inst|Add0~2_combout ; +wire \vga_ctrl_inst|Equal0~1_combout ; +wire \vga_ctrl_inst|Equal0~3_combout ; +wire \vga_ctrl_inst|cnt_h~2_combout ; +wire \vga_ctrl_inst|LessThan2~0_combout ; +wire \vga_ctrl_inst|LessThan0~0_combout ; +wire \vga_ctrl_inst|cnt_v[0]~9_combout ; +wire \vga_ctrl_inst|cnt_v[2]~8_combout ; +wire \vga_ctrl_inst|cnt_v[4]~6_combout ; +wire \vga_ctrl_inst|always1~1_combout ; +wire \vga_ctrl_inst|cnt_v[1]~0_combout ; +wire \vga_ctrl_inst|always1~2_combout ; +wire \vga_ctrl_inst|cnt_v[3]~7_combout ; +wire \vga_ctrl_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|cnt_v[5]~2_combout ; +wire \vga_ctrl_inst|Add1~1 ; +wire \vga_ctrl_inst|Add1~3 ; +wire \vga_ctrl_inst|Add1~5 ; +wire \vga_ctrl_inst|Add1~7 ; +wire \vga_ctrl_inst|Add1~9 ; +wire \vga_ctrl_inst|Add1~11 ; +wire \vga_ctrl_inst|Add1~13 ; +wire \vga_ctrl_inst|Add1~14_combout ; +wire \vga_ctrl_inst|cnt_v[7]~4_combout ; +wire \vga_ctrl_inst|Add1~15 ; +wire \vga_ctrl_inst|Add1~17 ; +wire \vga_ctrl_inst|Add1~18_combout ; +wire \vga_ctrl_inst|cnt_v[9]~1_combout ; +wire \vga_ctrl_inst|cnt_v[6]~5_combout ; +wire \vga_ctrl_inst|always1~0_combout ; +wire \vga_ctrl_inst|LessThan1~0_combout ; +wire \vga_ctrl_inst|LessThan6~1_combout ; +wire \vga_ctrl_inst|pix_data_req~1_combout ; +wire \vga_ctrl_inst|pix_data_req~2_combout ; +wire \vga_ctrl_inst|LessThan2~1_combout ; +wire \vga_ctrl_inst|rgb_valid~0_combout ; +wire \vga_ctrl_inst|Add2~1_cout ; +wire \vga_ctrl_inst|Add2~3_cout ; +wire \vga_ctrl_inst|Add2~5_cout ; +wire \vga_ctrl_inst|Add2~7_cout ; +wire \vga_ctrl_inst|Add2~9_cout ; +wire \vga_ctrl_inst|Add2~11 ; +wire \vga_ctrl_inst|Add2~12_combout ; +wire \vga_ctrl_inst|Add2~10_combout ; +wire \vga_pic_inst|LessThan14~0_combout ; +wire \vga_ctrl_inst|Add2~13 ; +wire \vga_ctrl_inst|Add2~15 ; +wire \vga_ctrl_inst|Add2~16_combout ; +wire \vga_ctrl_inst|Add2~14_combout ; +wire \vga_pic_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|pix_data_req~0_combout ; +wire \vga_ctrl_inst|LessThan4~0_combout ; +wire \vga_ctrl_inst|pix_data_req~3_combout ; +wire \vga_ctrl_inst|pix_data_req~4_combout ; +wire \vga_pic_inst|pix_data~4_combout ; +wire \vga_pic_inst|pix_data~9_combout ; +wire \vga_pic_inst|LessThan17~0_combout ; +wire \vga_pic_inst|pix_data~6_combout ; +wire \vga_pic_inst|pix_data[4]~10_combout ; +wire \vga_pic_inst|pix_data~11_combout ; +wire \vga_pic_inst|pix_data~12_combout ; +wire \vga_pic_inst|pix_data~13_combout ; +wire \vga_ctrl_inst|rgb[0]~0_combout ; +wire \vga_pic_inst|pix_data[4]~7_combout ; +wire \vga_pic_inst|pix_data~16_combout ; +wire \vga_ctrl_inst|rgb[1]~1_combout ; +wire \vga_pic_inst|pix_data~25_combout ; +wire \vga_ctrl_inst|rgb[5]~2_combout ; +wire \vga_pic_inst|pix_data~18_combout ; +wire \vga_pic_inst|pix_data~14_combout ; +wire \vga_pic_inst|pix_data~26_combout ; +wire \vga_pic_inst|pix_data~19_combout ; +wire \vga_ctrl_inst|rgb[7]~3_combout ; +wire \vga_pic_inst|LessThan2~2_combout ; +wire \vga_pic_inst|pix_data~20_combout ; +wire \vga_pic_inst|pix_data~21_combout ; +wire \vga_ctrl_inst|rgb[10]~4_combout ; +wire \vga_pic_inst|pix_data~22_combout ; +wire \vga_pic_inst|pix_data~23_combout ; +wire \vga_ctrl_inst|rgb[11]~5_combout ; +wire \vga_pic_inst|pix_data~24_combout ; +wire \vga_ctrl_inst|rgb[12]~6_combout ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [9:0] \vga_ctrl_inst|cnt_v ; +wire [9:0] \vga_ctrl_inst|cnt_h ; +wire [15:0] \vga_pic_inst|pix_data ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: LCCOMB_X35_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~4 ( +// Equation(s): +// \vga_ctrl_inst|Add0~4_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|Add0~3 $ (GND))) # (!\vga_ctrl_inst|cnt_h [2] & (!\vga_ctrl_inst|Add0~3 & VCC)) +// \vga_ctrl_inst|Add0~5 = CARRY((\vga_ctrl_inst|cnt_h [2] & !\vga_ctrl_inst|Add0~3 )) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~3 ), + .combout(\vga_ctrl_inst|Add0~4_combout ), + .cout(\vga_ctrl_inst|Add0~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 5989; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~0 ( +// Equation(s): +// \vga_ctrl_inst|Add1~0_combout = \vga_ctrl_inst|cnt_v [0] $ (VCC) +// \vga_ctrl_inst|Add1~1 = CARRY(\vga_ctrl_inst|cnt_v [0]) + + .dataa(\vga_ctrl_inst|cnt_v [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add1~0_combout ), + .cout(\vga_ctrl_inst|Add1~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~0 .lut_mask = 16'h55AA; +defparam \vga_ctrl_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~2 ( +// Equation(s): +// \vga_ctrl_inst|Add1~2_combout = (\vga_ctrl_inst|cnt_v [1] & (!\vga_ctrl_inst|Add1~1 )) # (!\vga_ctrl_inst|cnt_v [1] & ((\vga_ctrl_inst|Add1~1 ) # (GND))) +// \vga_ctrl_inst|Add1~3 = CARRY((!\vga_ctrl_inst|Add1~1 ) # (!\vga_ctrl_inst|cnt_v [1])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~1 ), + .combout(\vga_ctrl_inst|Add1~2_combout ), + .cout(\vga_ctrl_inst|Add1~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~4 ( +// Equation(s): +// \vga_ctrl_inst|Add1~4_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|Add1~3 $ (GND))) # (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|Add1~3 & VCC)) +// \vga_ctrl_inst|Add1~5 = CARRY((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Add1~3 )) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~3 ), + .combout(\vga_ctrl_inst|Add1~4_combout ), + .cout(\vga_ctrl_inst|Add1~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~6 ( +// Equation(s): +// \vga_ctrl_inst|Add1~6_combout = (\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|Add1~5 )) # (!\vga_ctrl_inst|cnt_v [3] & ((\vga_ctrl_inst|Add1~5 ) # (GND))) +// \vga_ctrl_inst|Add1~7 = CARRY((!\vga_ctrl_inst|Add1~5 ) # (!\vga_ctrl_inst|cnt_v [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~5 ), + .combout(\vga_ctrl_inst|Add1~6_combout ), + .cout(\vga_ctrl_inst|Add1~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~8 ( +// Equation(s): +// \vga_ctrl_inst|Add1~8_combout = (\vga_ctrl_inst|cnt_v [4] & (\vga_ctrl_inst|Add1~7 $ (GND))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|Add1~7 & VCC)) +// \vga_ctrl_inst|Add1~9 = CARRY((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Add1~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~7 ), + .combout(\vga_ctrl_inst|Add1~8_combout ), + .cout(\vga_ctrl_inst|Add1~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~10 ( +// Equation(s): +// \vga_ctrl_inst|Add1~10_combout = (\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|Add1~9 )) # (!\vga_ctrl_inst|cnt_v [5] & ((\vga_ctrl_inst|Add1~9 ) # (GND))) +// \vga_ctrl_inst|Add1~11 = CARRY((!\vga_ctrl_inst|Add1~9 ) # (!\vga_ctrl_inst|cnt_v [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~9 ), + .combout(\vga_ctrl_inst|Add1~10_combout ), + .cout(\vga_ctrl_inst|Add1~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~10 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~12 ( +// Equation(s): +// \vga_ctrl_inst|Add1~12_combout = (\vga_ctrl_inst|cnt_v [6] & (\vga_ctrl_inst|Add1~11 $ (GND))) # (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|Add1~11 & VCC)) +// \vga_ctrl_inst|Add1~13 = CARRY((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Add1~11 )) + + .dataa(\vga_ctrl_inst|cnt_v [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~11 ), + .combout(\vga_ctrl_inst|Add1~12_combout ), + .cout(\vga_ctrl_inst|Add1~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~16 ( +// Equation(s): +// \vga_ctrl_inst|Add1~16_combout = (\vga_ctrl_inst|cnt_v [8] & (\vga_ctrl_inst|Add1~15 $ (GND))) # (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|Add1~15 & VCC)) +// \vga_ctrl_inst|Add1~17 = CARRY((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Add1~15 )) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~15 ), + .combout(\vga_ctrl_inst|Add1~16_combout ), + .cout(\vga_ctrl_inst|Add1~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~16 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y23_N13 +dffeas \vga_ctrl_inst|cnt_v[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~0 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~0_combout = (\vga_ctrl_inst|cnt_h [8] & \vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~0 .lut_mask = 16'hCC00; +defparam \vga_ctrl_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N13 +dffeas \vga_ctrl_inst|cnt_h[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[8]~3 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[8]~3_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~16_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [8])))) + + .dataa(\vga_ctrl_inst|Add1~16_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [8]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8]~3 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[8]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~5 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~5_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~16_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~16_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~5 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~8 ( +// Equation(s): +// \vga_pic_inst|pix_data~8_combout = (\vga_ctrl_inst|Add2~16_combout ) # (((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) # (!\vga_ctrl_inst|Add2~10_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~8 .lut_mask = 16'hFBFF; +defparam \vga_pic_inst|pix_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N10 +cycloneive_lcell_comb \vga_pic_inst|pix_data~15 ( +// Equation(s): +// \vga_pic_inst|pix_data~15_combout = (\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|pix_data~11_combout & ((!\vga_pic_inst|pix_data[4]~10_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_pic_inst|pix_data~11_combout ), + .datab(\vga_pic_inst|pix_data~14_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data[4]~5_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~15_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~15 .lut_mask = 16'h0ACC; +defparam \vga_pic_inst|pix_data~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~17 ( +// Equation(s): +// \vga_pic_inst|pix_data~17_combout = (\vga_ctrl_inst|Add2~12_combout & (!\vga_ctrl_inst|Add2~14_combout )) # (!\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|Add2~14_combout & !\vga_ctrl_inst|Add2~10_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~17_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~17 .lut_mask = 16'h0C3C; +defparam \vga_pic_inst|pix_data~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N30 +cycloneive_io_obuf \hsync~output ( + .i(!\vga_ctrl_inst|LessThan0~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(hsync), + .obar()); +// synopsys translate_off +defparam \hsync~output .bus_hold = "false"; +defparam \hsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X28_Y0_N2 +cycloneive_io_obuf \vsync~output ( + .i(!\vga_ctrl_inst|LessThan1~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(vsync), + .obar()); +// synopsys translate_off +defparam \vsync~output .bus_hold = "false"; +defparam \vsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X32_Y0_N2 +cycloneive_io_obuf \rgb[0]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[0]), + .obar()); +// synopsys translate_off +defparam \rgb[0]~output .bus_hold = "false"; +defparam \rgb[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N23 +cycloneive_io_obuf \rgb[1]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[1]), + .obar()); +// synopsys translate_off +defparam \rgb[1]~output .bus_hold = "false"; +defparam \rgb[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N16 +cycloneive_io_obuf \rgb[2]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[2]), + .obar()); +// synopsys translate_off +defparam \rgb[2]~output .bus_hold = "false"; +defparam \rgb[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y4_N9 +cycloneive_io_obuf \rgb[3]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[3]), + .obar()); +// synopsys translate_off +defparam \rgb[3]~output .bus_hold = "false"; +defparam \rgb[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N9 +cycloneive_io_obuf \rgb[4]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[4]), + .obar()); +// synopsys translate_off +defparam \rgb[4]~output .bus_hold = "false"; +defparam \rgb[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N16 +cycloneive_io_obuf \rgb[5]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[5]), + .obar()); +// synopsys translate_off +defparam \rgb[5]~output .bus_hold = "false"; +defparam \rgb[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N2 +cycloneive_io_obuf \rgb[6]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[6]), + .obar()); +// synopsys translate_off +defparam \rgb[6]~output .bus_hold = "false"; +defparam \rgb[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N9 +cycloneive_io_obuf \rgb[7]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[7]), + .obar()); +// synopsys translate_off +defparam \rgb[7]~output .bus_hold = "false"; +defparam \rgb[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y12_N16 +cycloneive_io_obuf \rgb[8]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[8]), + .obar()); +// synopsys translate_off +defparam \rgb[8]~output .bus_hold = "false"; +defparam \rgb[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N9 +cycloneive_io_obuf \rgb[9]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[9]), + .obar()); +// synopsys translate_off +defparam \rgb[9]~output .bus_hold = "false"; +defparam \rgb[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y14_N23 +cycloneive_io_obuf \rgb[10]~output ( + .i(\vga_ctrl_inst|rgb[10]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[10]), + .obar()); +// synopsys translate_off +defparam \rgb[10]~output .bus_hold = "false"; +defparam \rgb[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N2 +cycloneive_io_obuf \rgb[11]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[11]), + .obar()); +// synopsys translate_off +defparam \rgb[11]~output .bus_hold = "false"; +defparam \rgb[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N16 +cycloneive_io_obuf \rgb[12]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[12]), + .obar()); +// synopsys translate_off +defparam \rgb[12]~output .bus_hold = "false"; +defparam \rgb[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N23 +cycloneive_io_obuf \rgb[13]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[13]), + .obar()); +// synopsys translate_off +defparam \rgb[13]~output .bus_hold = "false"; +defparam \rgb[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y19_N9 +cycloneive_io_obuf \rgb[14]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[14]), + .obar()); +// synopsys translate_off +defparam \rgb[14]~output .bus_hold = "false"; +defparam \rgb[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y20_N23 +cycloneive_io_obuf \rgb[15]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[15]), + .obar()); +// synopsys translate_off +defparam \rgb[15]~output .bus_hold = "false"; +defparam \rgb[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~0 ( +// Equation(s): +// \vga_ctrl_inst|Add0~0_combout = \vga_ctrl_inst|cnt_h [0] $ (VCC) +// \vga_ctrl_inst|Add0~1 = CARRY(\vga_ctrl_inst|cnt_h [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add0~0_combout ), + .cout(\vga_ctrl_inst|Add0~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X35_Y3_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N10 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\sys_rst_n~input_o ) # (!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .datac(\sys_rst_n~input_o ), + .datad(gnd), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h7F7F; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X35_Y23_N9 +dffeas \vga_ctrl_inst|cnt_h[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~2 ( +// Equation(s): +// \vga_ctrl_inst|Add0~2_combout = (\vga_ctrl_inst|cnt_h [1] & (!\vga_ctrl_inst|Add0~1 )) # (!\vga_ctrl_inst|cnt_h [1] & ((\vga_ctrl_inst|Add0~1 ) # (GND))) +// \vga_ctrl_inst|Add0~3 = CARRY((!\vga_ctrl_inst|Add0~1 ) # (!\vga_ctrl_inst|cnt_h [1])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~1 ), + .combout(\vga_ctrl_inst|Add0~2_combout ), + .cout(\vga_ctrl_inst|Add0~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~6 ( +// Equation(s): +// \vga_ctrl_inst|Add0~6_combout = (\vga_ctrl_inst|cnt_h [3] & (!\vga_ctrl_inst|Add0~5 )) # (!\vga_ctrl_inst|cnt_h [3] & ((\vga_ctrl_inst|Add0~5 ) # (GND))) +// \vga_ctrl_inst|Add0~7 = CARRY((!\vga_ctrl_inst|Add0~5 ) # (!\vga_ctrl_inst|cnt_h [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~5 ), + .combout(\vga_ctrl_inst|Add0~6_combout ), + .cout(\vga_ctrl_inst|Add0~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N15 +dffeas \vga_ctrl_inst|cnt_h[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~8 ( +// Equation(s): +// \vga_ctrl_inst|Add0~8_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Add0~7 $ (GND))) # (!\vga_ctrl_inst|cnt_h [4] & (!\vga_ctrl_inst|Add0~7 & VCC)) +// \vga_ctrl_inst|Add0~9 = CARRY((\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add0~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~7 ), + .combout(\vga_ctrl_inst|Add0~8_combout ), + .cout(\vga_ctrl_inst|Add0~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N17 +dffeas \vga_ctrl_inst|cnt_h[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~10 ( +// Equation(s): +// \vga_ctrl_inst|Add0~10_combout = (\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|Add0~9 )) # (!\vga_ctrl_inst|cnt_h [5] & ((\vga_ctrl_inst|Add0~9 ) # (GND))) +// \vga_ctrl_inst|Add0~11 = CARRY((!\vga_ctrl_inst|Add0~9 ) # (!\vga_ctrl_inst|cnt_h [5])) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~9 ), + .combout(\vga_ctrl_inst|Add0~10_combout ), + .cout(\vga_ctrl_inst|Add0~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~12 ( +// Equation(s): +// \vga_ctrl_inst|Add0~12_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add0~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add0~11 & VCC)) +// \vga_ctrl_inst|Add0~13 = CARRY((\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add0~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~11 ), + .combout(\vga_ctrl_inst|Add0~12_combout ), + .cout(\vga_ctrl_inst|Add0~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N21 +dffeas \vga_ctrl_inst|cnt_h[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~14 ( +// Equation(s): +// \vga_ctrl_inst|Add0~14_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add0~13 )) # (!\vga_ctrl_inst|cnt_h [7] & ((\vga_ctrl_inst|Add0~13 ) # (GND))) +// \vga_ctrl_inst|Add0~15 = CARRY((!\vga_ctrl_inst|Add0~13 ) # (!\vga_ctrl_inst|cnt_h [7])) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~13 ), + .combout(\vga_ctrl_inst|Add0~14_combout ), + .cout(\vga_ctrl_inst|Add0~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N23 +dffeas \vga_ctrl_inst|cnt_h[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~16 ( +// Equation(s): +// \vga_ctrl_inst|Add0~16_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add0~15 $ (GND))) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add0~15 & VCC)) +// \vga_ctrl_inst|Add0~17 = CARRY((\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add0~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~15 ), + .combout(\vga_ctrl_inst|Add0~16_combout ), + .cout(\vga_ctrl_inst|Add0~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~18 ( +// Equation(s): +// \vga_ctrl_inst|Add0~18_combout = \vga_ctrl_inst|Add0~17 $ (\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(\vga_ctrl_inst|Add0~17 ), + .combout(\vga_ctrl_inst|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~1_combout = (!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|Add0~18_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|Add0~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~1 .lut_mask = 16'h3030; +defparam \vga_ctrl_inst|cnt_h~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N1 +dffeas \vga_ctrl_inst|cnt_h[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~0_combout = (\vga_ctrl_inst|Add0~10_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~10_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~0 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N25 +dffeas \vga_ctrl_inst|cnt_h[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~2 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~2_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|cnt_h [9] & (!\vga_ctrl_inst|cnt_h [5] & !\vga_ctrl_inst|cnt_h [6]))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [9]), + .datac(\vga_ctrl_inst|cnt_h [5]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~2 .lut_mask = 16'h0008; +defparam \vga_ctrl_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N11 +dffeas \vga_ctrl_inst|cnt_h[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~1 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~1_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|cnt_h [3] & (\vga_ctrl_inst|cnt_h [0] & \vga_ctrl_inst|cnt_h [1]))) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(\vga_ctrl_inst|cnt_h [0]), + .datad(\vga_ctrl_inst|cnt_h [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~3 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~3_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Equal0~2_combout & (\vga_ctrl_inst|Equal0~1_combout & !\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(\vga_ctrl_inst|Equal0~2_combout ), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|cnt_h [7]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~3 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~2_combout = (\vga_ctrl_inst|Add0~16_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~16_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~2 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N3 +dffeas \vga_ctrl_inst|cnt_h[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~0_combout = (!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~0 .lut_mask = 16'h0033; +defparam \vga_ctrl_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~0_combout = (\vga_ctrl_inst|cnt_h [7]) # (((\vga_ctrl_inst|cnt_h [6] & \vga_ctrl_inst|cnt_h [5])) # (!\vga_ctrl_inst|LessThan2~0_combout )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~0 .lut_mask = 16'hEFAF; +defparam \vga_ctrl_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[0]~9 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[0]~9_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~0_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [0])))) + + .dataa(\vga_ctrl_inst|Add1~0_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0]~9 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N29 +dffeas \vga_ctrl_inst|cnt_v[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[2]~8 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[2]~8_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~4_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [2])))) + + .dataa(\vga_ctrl_inst|Add1~4_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2]~8 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N5 +dffeas \vga_ctrl_inst|cnt_v[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[4]~6 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[4]~6_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~8_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [4])))) + + .dataa(\vga_ctrl_inst|Add1~8_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [4]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4]~6 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[4]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N1 +dffeas \vga_ctrl_inst|cnt_v[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|always1~1 ( +// Equation(s): +// \vga_ctrl_inst|always1~1_combout = (\vga_ctrl_inst|cnt_v [9] & (\vga_ctrl_inst|cnt_v [3] & (\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4]))) + + .dataa(\vga_ctrl_inst|cnt_v [9]), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~1 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|always1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[1]~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[1]~0_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~2_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [1])))) + + .dataa(\vga_ctrl_inst|Add1~2_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1]~0 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N17 +dffeas \vga_ctrl_inst|cnt_v[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|always1~2 ( +// Equation(s): +// \vga_ctrl_inst|always1~2_combout = (\vga_ctrl_inst|always1~0_combout & (!\vga_ctrl_inst|cnt_v [0] & (\vga_ctrl_inst|always1~1_combout & !\vga_ctrl_inst|cnt_v [1]))) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(\vga_ctrl_inst|always1~1_combout ), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~2 .lut_mask = 16'h0020; +defparam \vga_ctrl_inst|always1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[3]~7 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[3]~7_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~6_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [3])))) + + .dataa(\vga_ctrl_inst|Add1~6_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3]~7 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N3 +dffeas \vga_ctrl_inst|cnt_v[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~0_combout = (!\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~0 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[5]~2_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~10_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [5])))) + + .dataa(\vga_ctrl_inst|Add1~10_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5]~2 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N19 +dffeas \vga_ctrl_inst|cnt_v[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~14 ( +// Equation(s): +// \vga_ctrl_inst|Add1~14_combout = (\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|Add1~13 )) # (!\vga_ctrl_inst|cnt_v [7] & ((\vga_ctrl_inst|Add1~13 ) # (GND))) +// \vga_ctrl_inst|Add1~15 = CARRY((!\vga_ctrl_inst|Add1~13 ) # (!\vga_ctrl_inst|cnt_v [7])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~13 ), + .combout(\vga_ctrl_inst|Add1~14_combout ), + .cout(\vga_ctrl_inst|Add1~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~14 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[7]~4 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[7]~4_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~14_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [7])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~14_combout ), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7]~4 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N3 +dffeas \vga_ctrl_inst|cnt_v[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~18 ( +// Equation(s): +// \vga_ctrl_inst|Add1~18_combout = \vga_ctrl_inst|Add1~17 $ (\vga_ctrl_inst|cnt_v [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [9]), + .cin(\vga_ctrl_inst|Add1~17 ), + .combout(\vga_ctrl_inst|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[9]~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[9]~1_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~18_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [9])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~18_combout ), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9]~1 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N1 +dffeas \vga_ctrl_inst|cnt_v[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[6]~5 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[6]~5_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~12_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [6])))) + + .dataa(\vga_ctrl_inst|Add1~12_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6]~5 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N5 +dffeas \vga_ctrl_inst|cnt_v[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|always1~0 ( +// Equation(s): +// \vga_ctrl_inst|always1~0_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan1~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan1~0_combout = ((\vga_ctrl_inst|cnt_v [1]) # ((\vga_ctrl_inst|cnt_v [9]) # (!\vga_ctrl_inst|always1~0_combout ))) # (!\vga_ctrl_inst|LessThan6~0_combout ) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan1~0 .lut_mask = 16'hFDFF; +defparam \vga_ctrl_inst|LessThan1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~1_combout = (!\vga_ctrl_inst|cnt_v [1]) # (!\vga_ctrl_inst|cnt_v [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~1 .lut_mask = 16'h33FF; +defparam \vga_ctrl_inst|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N30 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~1_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~1 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~2 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~2_combout = (\vga_ctrl_inst|LessThan6~0_combout & ((\vga_ctrl_inst|LessThan6~1_combout & (\vga_ctrl_inst|pix_data_req~1_combout )) # (!\vga_ctrl_inst|LessThan6~1_combout & ((\vga_ctrl_inst|always1~0_combout ))))) # +// (!\vga_ctrl_inst|LessThan6~0_combout & (((\vga_ctrl_inst|always1~0_combout )))) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|LessThan6~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~2 .lut_mask = 16'hF780; +defparam \vga_ctrl_inst|pix_data_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~1_combout = (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~1 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|rgb_valid~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb_valid~0_combout = (\vga_ctrl_inst|Equal0~0_combout & (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|LessThan2~0_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout & (((\vga_ctrl_inst|cnt_h [7] & +// !\vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|LessThan2~0_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb_valid~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb_valid~0 .lut_mask = 16'h0745; +defparam \vga_ctrl_inst|rgb_valid~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~1 ( +// Equation(s): +// \vga_ctrl_inst|Add2~1_cout = CARRY((\vga_ctrl_inst|cnt_h [1] & \vga_ctrl_inst|cnt_h [0])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\vga_ctrl_inst|Add2~1_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~1 .lut_mask = 16'h0088; +defparam \vga_ctrl_inst|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~3 ( +// Equation(s): +// \vga_ctrl_inst|Add2~3_cout = CARRY((!\vga_ctrl_inst|Add2~1_cout ) # (!\vga_ctrl_inst|cnt_h [2])) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~1_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~3_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~3 .lut_mask = 16'h005F; +defparam \vga_ctrl_inst|Add2~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~5 ( +// Equation(s): +// \vga_ctrl_inst|Add2~5_cout = CARRY((\vga_ctrl_inst|cnt_h [3] & !\vga_ctrl_inst|Add2~3_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~3_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~5_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~5 .lut_mask = 16'h000A; +defparam \vga_ctrl_inst|Add2~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~7 ( +// Equation(s): +// \vga_ctrl_inst|Add2~7_cout = CARRY((!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add2~5_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~5_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~7_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~7 .lut_mask = 16'h0005; +defparam \vga_ctrl_inst|Add2~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~9 ( +// Equation(s): +// \vga_ctrl_inst|Add2~9_cout = CARRY((\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|Add2~7_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~7_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~9_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~9 .lut_mask = 16'h00AF; +defparam \vga_ctrl_inst|Add2~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~10 ( +// Equation(s): +// \vga_ctrl_inst|Add2~10_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add2~9_cout & VCC)) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add2~9_cout )) +// \vga_ctrl_inst|Add2~11 = CARRY((!\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add2~9_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~9_cout ), + .combout(\vga_ctrl_inst|Add2~10_combout ), + .cout(\vga_ctrl_inst|Add2~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~10 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~12 ( +// Equation(s): +// \vga_ctrl_inst|Add2~12_combout = (\vga_ctrl_inst|cnt_h [7] & (\vga_ctrl_inst|Add2~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add2~11 & VCC)) +// \vga_ctrl_inst|Add2~13 = CARRY((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|Add2~11 )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~11 ), + .combout(\vga_ctrl_inst|Add2~12_combout ), + .cout(\vga_ctrl_inst|Add2~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N24 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~0 ( +// Equation(s): +// \vga_pic_inst|LessThan14~0_combout = (\vga_ctrl_inst|Add2~12_combout & \vga_ctrl_inst|Add2~10_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~0 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|LessThan14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~14 ( +// Equation(s): +// \vga_ctrl_inst|Add2~14_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add2~13 & VCC)) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add2~13 )) +// \vga_ctrl_inst|Add2~15 = CARRY((!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add2~13 )) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~13 ), + .combout(\vga_ctrl_inst|Add2~14_combout ), + .cout(\vga_ctrl_inst|Add2~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~14 .lut_mask = 16'hA505; +defparam \vga_ctrl_inst|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~16 ( +// Equation(s): +// \vga_ctrl_inst|Add2~16_combout = \vga_ctrl_inst|cnt_h [9] $ (\vga_ctrl_inst|Add2~15 ) + + .dataa(\vga_ctrl_inst|cnt_h [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\vga_ctrl_inst|Add2~15 ), + .combout(\vga_ctrl_inst|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~16 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|Add2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N2 +cycloneive_lcell_comb \vga_pic_inst|LessThan6~0 ( +// Equation(s): +// \vga_pic_inst|LessThan6~0_combout = ((\vga_pic_inst|LessThan14~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (\vga_ctrl_inst|Add2~14_combout ))) # (!\vga_ctrl_inst|pix_data_req~4_combout ) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|LessThan14~0_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan6~0 .lut_mask = 16'hFFFD; +defparam \vga_pic_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~0_combout = (!\vga_ctrl_inst|always1~0_combout & \vga_ctrl_inst|cnt_v [9]) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~0 .lut_mask = 16'h5050; +defparam \vga_ctrl_inst|pix_data_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan4~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan4~0_combout = (\vga_ctrl_inst|LessThan2~0_combout & (((!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan4~0 .lut_mask = 16'h7030; +defparam \vga_ctrl_inst|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~3 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~3_combout = ((!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout ) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~3 .lut_mask = 16'h5755; +defparam \vga_ctrl_inst|pix_data_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~4 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (!\vga_ctrl_inst|LessThan4~0_combout & \vga_ctrl_inst|pix_data_req~3_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|LessThan4~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~4 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|pix_data_req~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~4 ( +// Equation(s): +// \vga_pic_inst|pix_data~4_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~4 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~9 ( +// Equation(s): +// \vga_pic_inst|pix_data~9_combout = (\vga_pic_inst|pix_data~8_combout & ((\vga_pic_inst|LessThan6~0_combout ) # ((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data~8_combout & +// (((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) + + .dataa(\vga_pic_inst|pix_data~8_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~9 .lut_mask = 16'h8F88; +defparam \vga_pic_inst|pix_data~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N8 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~0 ( +// Equation(s): +// \vga_pic_inst|LessThan17~0_combout = (\vga_ctrl_inst|Add2~12_combout ) # ((\vga_ctrl_inst|Add2~10_combout ) # ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout ))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~0 .lut_mask = 16'hFEFF; +defparam \vga_pic_inst|LessThan17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~6 ( +// Equation(s): +// \vga_pic_inst|pix_data~6_combout = ((\vga_pic_inst|LessThan17~0_combout & ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|pix_data~4_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~6 .lut_mask = 16'hF755; +defparam \vga_pic_inst|pix_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N22 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~10 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~10_combout = (!\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|Add2~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~10 .lut_mask = 16'h0FFF; +defparam \vga_pic_inst|pix_data[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~11 ( +// Equation(s): +// \vga_pic_inst|pix_data~11_combout = (\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~10_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~11 .lut_mask = 16'h0080; +defparam \vga_pic_inst|pix_data~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data~12 ( +// Equation(s): +// \vga_pic_inst|pix_data~12_combout = (\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data[4]~10_combout ) # (!\vga_pic_inst|pix_data~11_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|LessThan17~0_combout )) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan17~0_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~12 .lut_mask = 16'hE4EE; +defparam \vga_pic_inst|pix_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N16 +cycloneive_lcell_comb \vga_pic_inst|pix_data~13 ( +// Equation(s): +// \vga_pic_inst|pix_data~13_combout = ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~7_combout ), + .datab(\vga_pic_inst|pix_data~9_combout ), + .datac(\vga_pic_inst|pix_data~6_combout ), + .datad(\vga_pic_inst|pix_data~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~13 .lut_mask = 16'h80FF; +defparam \vga_pic_inst|pix_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N17 +dffeas \vga_pic_inst|pix_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[0] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[0]~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb[0]~0_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_ctrl_inst|rgb_valid~0_combout & (\vga_pic_inst|pix_data [0] & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|rgb_valid~0_combout ), + .datac(\vga_pic_inst|pix_data [0]), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[0]~0 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~7 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~7_combout = (!\vga_ctrl_inst|Add2~16_combout & (\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|Add2~12_combout )))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~7 .lut_mask = 16'h0700; +defparam \vga_pic_inst|pix_data[4]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~16 ( +// Equation(s): +// \vga_pic_inst|pix_data~16_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~9_combout ), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~16 .lut_mask = 16'hEAAA; +defparam \vga_pic_inst|pix_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N19 +dffeas \vga_pic_inst|pix_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[1]~1 ( +// Equation(s): +// \vga_ctrl_inst|rgb[1]~1_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [4]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[1]~1 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~25 ( +// Equation(s): +// \vga_pic_inst|pix_data~25_combout = (\vga_ctrl_inst|Add2~16_combout & (((!\vga_pic_inst|LessThan17~0_combout )))) # (!\vga_ctrl_inst|Add2~16_combout & ((\vga_ctrl_inst|pix_data_req~4_combout & (\vga_pic_inst|pix_data~17_combout )) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_pic_inst|LessThan17~0_combout ))))) + + .dataa(\vga_pic_inst|pix_data~17_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~25_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~25 .lut_mask = 16'h20EF; +defparam \vga_pic_inst|pix_data~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N13 +dffeas \vga_pic_inst|pix_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[8] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|rgb[5]~2_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [8]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[5]~2 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~18 ( +// Equation(s): +// \vga_pic_inst|pix_data~18_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~12_combout & !\vga_ctrl_inst|Add2~10_combout )) # (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout +// )))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~18 .lut_mask = 16'h4060; +defparam \vga_pic_inst|pix_data~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~14 ( +// Equation(s): +// \vga_pic_inst|pix_data~14_combout = (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~14_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~14 .lut_mask = 16'h0030; +defparam \vga_pic_inst|pix_data~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~26 ( +// Equation(s): +// \vga_pic_inst|pix_data~26_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~16_combout & ((\vga_pic_inst|pix_data~14_combout ))) # (!\vga_ctrl_inst|Add2~16_combout & (\vga_pic_inst|pix_data~18_combout )))) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|pix_data~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|pix_data~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~26_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~26 .lut_mask = 16'hFD08; +defparam \vga_pic_inst|pix_data~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~19 ( +// Equation(s): +// \vga_pic_inst|pix_data~19_combout = (\vga_pic_inst|pix_data~26_combout & \vga_pic_inst|pix_data~6_combout ) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(gnd), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~19_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~19 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|pix_data~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N1 +dffeas \vga_pic_inst|pix_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[7]~3 ( +// Equation(s): +// \vga_ctrl_inst|rgb[7]~3_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [9]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[7]~3 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N6 +cycloneive_lcell_comb \vga_pic_inst|LessThan2~2 ( +// Equation(s): +// \vga_pic_inst|LessThan2~2_combout = (\vga_pic_inst|LessThan17~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_pic_inst|LessThan17~0_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan2~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan2~2 .lut_mask = 16'hEEFF; +defparam \vga_pic_inst|LessThan2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~20 ( +// Equation(s): +// \vga_pic_inst|pix_data~20_combout = (!\vga_ctrl_inst|Add2~16_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~20 .lut_mask = 16'h0500; +defparam \vga_pic_inst|pix_data~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~21 ( +// Equation(s): +// \vga_pic_inst|pix_data~21_combout = (\vga_pic_inst|LessThan2~2_combout & ((\vga_pic_inst|pix_data~26_combout ) # ((\vga_pic_inst|pix_data~4_combout & \vga_pic_inst|pix_data~20_combout )))) + + .dataa(\vga_pic_inst|pix_data~4_combout ), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(\vga_pic_inst|LessThan2~2_combout ), + .datad(\vga_pic_inst|pix_data~20_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~21_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~21 .lut_mask = 16'hE0C0; +defparam \vga_pic_inst|pix_data~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N27 +dffeas \vga_pic_inst|pix_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[10] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[10]~4 ( +// Equation(s): +// \vga_ctrl_inst|rgb[10]~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [10]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [10]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[10]~4 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N20 +cycloneive_lcell_comb \vga_pic_inst|pix_data~22 ( +// Equation(s): +// \vga_pic_inst|pix_data~22_combout = ((\vga_pic_inst|pix_data[4]~5_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout ))) # (!\vga_pic_inst|LessThan6~0_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~22 .lut_mask = 16'h3B33; +defparam \vga_pic_inst|pix_data~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~23 ( +// Equation(s): +// \vga_pic_inst|pix_data~23_combout = ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|LessThan2~2_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|pix_data[4]~7_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~23_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~23 .lut_mask = 16'hF733; +defparam \vga_pic_inst|pix_data~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N29 +dffeas \vga_pic_inst|pix_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[11]~5 ( +// Equation(s): +// \vga_ctrl_inst|rgb[11]~5_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [13] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [13]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[11]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[11]~5 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[11]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~24 ( +// Equation(s): +// \vga_pic_inst|pix_data~24_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|LessThan2~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~24_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~24 .lut_mask = 16'hEAEE; +defparam \vga_pic_inst|pix_data~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N31 +dffeas \vga_pic_inst|pix_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[15] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[12]~6 ( +// Equation(s): +// \vga_ctrl_inst|rgb[12]~6_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [15] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [15]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[12]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[12]~6 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[12]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_0c_v_slow.sdo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_0c_v_slow.sdo new file mode 100644 index 0000000..56cf675 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_0c_v_slow.sdo @@ -0,0 +1,2108 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "vga_colorbar") + (DATE "06/02/2023 04:42:20") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (350:350:350) (414:414:414)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (3921:3921:3921) (3921:3921:3921)) + (PORT inclk[0] (2063:2063:2063) (2063:2063:2063)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (930:930:930) (857:857:857)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (936:936:936) (846:846:846)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (946:946:946) (850:850:850)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datab (976:976:976) (871:871:871)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (553:553:553) (535:535:535)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT datab (928:928:928) (836:836:836)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (539:539:539)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (929:929:929) (860:860:860)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1630:1630:1630)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT datab (376:376:376) (436:436:436)) + (PORT datad (318:318:318) (383:383:383)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (702:702:702)) + (PORT datab (854:854:854) (735:735:735)) + (PORT datad (295:295:295) (323:323:323)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (1192:1192:1192) (1014:1014:1014)) + (PORT datad (897:897:897) (776:776:776)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1125:1125:1125) (953:953:953)) + (PORT datab (944:944:944) (799:799:799)) + (PORT datac (901:901:901) (814:814:814)) + (PORT datad (1146:1146:1146) (972:972:972)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~15) + (DELAY + (ABSOLUTE + (PORT dataa (816:816:816) (714:714:714)) + (PORT datab (502:502:502) (440:440:440)) + (PORT datac (233:233:233) (251:251:251)) + (PORT datad (253:253:253) (275:275:275)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~17) + (DELAY + (ABSOLUTE + (PORT datab (324:324:324) (343:343:343)) + (PORT datac (833:833:833) (685:685:685)) + (PORT datad (272:272:272) (289:289:289)) + (IOPATH datab combout (437:437:437) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (788:788:788) (813:813:813)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2044:2044:2044) (2012:2012:2012)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE hsync\~output) + (DELAY + (ABSOLUTE + (PORT i (1890:1890:1890) (2195:2195:2195)) + (IOPATH i o (2832:2832:2832) (2912:2912:2912)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE vsync\~output) + (DELAY + (ABSOLUTE + (PORT i (1656:1656:1656) (1999:1999:1999)) + (IOPATH i o (2842:2842:2842) (2922:2922:2922)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2831:2831:2831) (2423:2423:2423)) + (IOPATH i o (2912:2912:2912) (2832:2832:2832)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2775:2775:2775) (2366:2366:2366)) + (IOPATH i o (2922:2922:2922) (2842:2842:2842)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3072:3072:3072) (2605:2605:2605)) + (IOPATH i o (2922:2922:2922) (2842:2842:2842)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3427:3427:3427) (2865:2865:2865)) + (IOPATH i o (3043:3043:3043) (2991:2991:2991)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3421:3421:3421) (2863:2863:2863)) + (IOPATH i o (3023:3023:3023) (2971:2971:2971)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1488:1488:1488) (1307:1307:1307)) + (IOPATH i o (3023:3023:3023) (2971:2971:2971)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1531:1531:1531) (1319:1319:1319)) + (IOPATH i o (3023:3023:3023) (2971:2971:2971)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2076:2076:2076) (1758:1758:1758)) + (IOPATH i o (3033:3033:3033) (2981:2981:2981)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1883:1883:1883) (1625:1625:1625)) + (IOPATH i o (2993:2993:2993) (2941:2941:2941)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1877:1877:1877) (1595:1595:1595)) + (IOPATH i o (3013:3013:3013) (2961:2961:2961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1823:1823:1823) (1522:1522:1522)) + (IOPATH i o (3003:3003:3003) (2951:2951:2951)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1783:1783:1783) (1502:1502:1502)) + (IOPATH i o (3003:3003:3003) (2951:2951:2951)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1438:1438:1438) (1189:1189:1189)) + (IOPATH i o (3013:3013:3013) (2961:2961:2961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1456:1456:1456) (1192:1192:1192)) + (IOPATH i o (3003:3003:3003) (2951:2951:2951)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1057:1057:1057) (866:866:866)) + (IOPATH i o (3013:3013:3013) (2961:2961:2961)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1090:1090:1090) (891:891:891)) + (IOPATH i o (3003:3003:3003) (2951:2951:2951)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (346:346:346) (403:403:403)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (748:748:748) (773:773:773)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (2611:2611:2611) (2849:2849:2849)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (4061:4061:4061) (3964:3964:3964)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1998:1998:1998) (2217:2217:2217)) + (PORT datab (316:316:316) (370:370:370)) + (PORT datac (3330:3330:3330) (3369:3369:3369)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2132:2132:2132) (1906:1906:1906)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (410:410:410)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (348:348:348) (406:406:406)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (339:339:339) (395:395:395)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (898:898:898) (788:788:788)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (405:405:405)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (342:342:342) (402:402:402)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (381:381:381) (442:442:442)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (326:326:326) (392:392:392)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~1) + (DELAY + (ABSOLUTE + (PORT datab (841:841:841) (693:693:693)) + (PORT datac (229:229:229) (244:244:244)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~0) + (DELAY + (ABSOLUTE + (PORT datab (783:783:783) (625:625:625)) + (PORT datac (249:249:249) (266:266:266)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (645:645:645) (596:596:596)) + (PORT datab (366:366:366) (429:429:429)) + (PORT datac (839:839:839) (745:745:745)) + (PORT datad (306:306:306) (366:366:366)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (351:351:351) (415:415:415)) + (PORT datab (348:348:348) (406:406:406)) + (PORT datac (306:306:306) (372:372:372)) + (PORT datad (308:308:308) (368:368:368)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (868:868:868) (778:778:778)) + (PORT datab (732:732:732) (605:605:605)) + (PORT datac (711:711:711) (589:589:589)) + (PORT datad (892:892:892) (802:802:802)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~2) + (DELAY + (ABSOLUTE + (PORT datab (270:270:270) (277:277:277)) + (PORT datac (799:799:799) (659:659:659)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1646:1646:1646) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1678:1678:1678) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT datab (375:375:375) (435:435:435)) + (PORT datad (317:317:317) (382:382:382)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (750:750:750)) + (PORT datab (904:904:904) (785:785:785)) + (PORT datac (753:753:753) (626:626:626)) + (PORT datad (304:304:304) (363:363:363)) + (IOPATH dataa combout (420:420:420) (400:400:400)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (712:712:712)) + (PORT datab (858:858:858) (739:739:739)) + (PORT datad (291:291:291) (319:319:319)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1630:1630:1630)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (738:738:738)) + (PORT datab (852:852:852) (733:733:733)) + (PORT datad (296:296:296) (324:324:324)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1630:1630:1630)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1093:1093:1093) (902:902:902)) + (PORT datab (852:852:852) (732:732:732)) + (PORT datad (297:297:297) (325:325:325)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1630:1630:1630)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (988:988:988) (890:890:890)) + (PORT datab (346:346:346) (404:404:404)) + (PORT datac (303:303:303) (370:370:370)) + (PORT datad (304:304:304) (363:363:363)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1168:1168:1168) (956:956:956)) + (PORT datab (856:856:856) (736:736:736)) + (PORT datad (293:293:293) (321:321:321)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1630:1630:1630)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (317:317:317)) + (PORT datab (347:347:347) (405:405:405)) + (PORT datac (443:443:443) (380:380:380)) + (PORT datad (314:314:314) (376:376:376)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (926:926:926) (775:775:775)) + (PORT datab (852:852:852) (732:732:732)) + (PORT datad (296:296:296) (324:324:324)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1630:1630:1630)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (405:405:405)) + (PORT datac (305:305:305) (371:371:371)) + (PORT datad (306:306:306) (365:365:365)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (872:872:872) (735:735:735)) + (PORT datab (856:856:856) (737:737:737)) + (PORT datad (293:293:293) (321:321:321)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1644:1644:1644) (1665:1665:1665)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1676:1676:1676) (1630:1630:1630)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (553:553:553) (535:535:535)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (755:755:755)) + (PORT datab (270:270:270) (277:277:277)) + (PORT datad (1181:1181:1181) (989:989:989)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datad (311:311:311) (372:372:372)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (859:859:859) (756:756:756)) + (PORT datab (271:271:271) (279:279:279)) + (PORT datad (1181:1181:1181) (990:990:990)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (272:272:272) (284:284:284)) + (PORT datab (1241:1241:1241) (1030:1030:1030)) + (PORT datad (817:817:817) (712:712:712)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (431:431:431)) + (IOPATH datac combout (415:415:415) (429:429:429)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1631:1631:1631)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (340:340:340) (399:399:399)) + (PORT datab (338:338:338) (393:393:393)) + (PORT datac (842:842:842) (777:777:777)) + (PORT datad (865:865:865) (793:793:793)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (295:295:295)) + (PORT datab (353:353:353) (414:414:414)) + (PORT datac (930:930:930) (847:847:847)) + (PORT datad (250:250:250) (271:271:271)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT datab (347:347:347) (405:405:405)) + (PORT datad (313:313:313) (375:375:375)) + (IOPATH datab combout (384:384:384) (398:398:398)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (927:927:927) (858:858:858)) + (PORT datab (349:349:349) (408:408:408)) + (PORT datac (511:511:511) (502:502:502)) + (PORT datad (501:501:501) (496:496:496)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (406:406:406) (453:453:453)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (277:277:277) (292:292:292)) + (PORT datab (268:268:268) (275:275:275)) + (PORT datac (691:691:691) (555:555:555)) + (PORT datad (254:254:254) (275:275:275)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT datab (902:902:902) (782:782:782)) + (PORT datac (821:821:821) (736:736:736)) + (PORT datad (303:303:303) (362:362:362)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb_valid\~0) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (604:604:604)) + (PORT datab (950:950:950) (840:840:840)) + (PORT datac (751:751:751) (625:625:625)) + (PORT datad (241:241:241) (255:255:255)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (423:423:423) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (556:556:556)) + (PORT datab (810:810:810) (721:721:721)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datab cout (497:497:497) (381:381:381)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (605:605:605) (557:557:557)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (532:532:532)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~7) + (DELAY + (ABSOLUTE + (PORT dataa (559:559:559) (540:540:540)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (831:831:831) (743:743:743)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT datab (603:603:603) (555:555:555)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datab cout (497:497:497) (381:381:381)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (823:823:823) (747:747:747)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~0) + (DELAY + (ABSOLUTE + (PORT datab (324:324:324) (343:343:343)) + (PORT datad (271:271:271) (289:289:289)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (627:627:627) (578:578:578)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH dataa cout (486:486:486) (375:375:375)) + (IOPATH datad combout (167:167:167) (143:143:143)) + (IOPATH cin combout (549:549:549) (519:519:519)) + (IOPATH cin cout (63:63:63) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (606:606:606) (557:557:557)) + (IOPATH dataa combout (435:435:435) (444:444:444)) + (IOPATH cin combout (549:549:549) (519:519:519)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (705:705:705)) + (PORT datab (269:269:269) (276:276:276)) + (PORT datac (257:257:257) (276:276:276)) + (PORT datad (260:260:260) (272:272:272)) + (IOPATH dataa combout (404:404:404) (450:450:450)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (317:317:317)) + (PORT datac (926:926:926) (842:842:842)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datac combout (305:305:305) (285:285:285)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (755:755:755) (628:628:628)) + (PORT datab (951:951:951) (842:842:842)) + (PORT datac (750:750:750) (623:623:623)) + (PORT datad (244:244:244) (258:258:258)) + (IOPATH dataa combout (374:374:374) (392:392:392)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (728:728:728) (604:604:604)) + (PORT datab (951:951:951) (842:842:842)) + (PORT datac (710:710:710) (588:588:588)) + (PORT datad (242:242:242) (256:256:256)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~4) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (721:721:721)) + (PORT datab (902:902:902) (752:752:752)) + (PORT datac (226:226:226) (242:242:242)) + (PORT datad (227:227:227) (235:235:235)) + (IOPATH dataa combout (349:349:349) (377:377:377)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~4) + (DELAY + (ABSOLUTE + (PORT datab (1194:1194:1194) (1016:1016:1016)) + (PORT datad (824:824:824) (721:721:721)) + (IOPATH datab combout (437:437:437) (425:425:425)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~9) + (DELAY + (ABSOLUTE + (PORT dataa (271:271:271) (283:283:283)) + (PORT datab (867:867:867) (729:729:729)) + (PORT datac (897:897:897) (809:809:809)) + (PORT datad (262:262:262) (277:277:277)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (763:763:763)) + (PORT datab (943:943:943) (798:798:798)) + (PORT datac (898:898:898) (810:810:810)) + (PORT datad (1151:1151:1151) (977:977:977)) + (IOPATH dataa combout (375:375:375) (371:371:371)) + (IOPATH datab combout (377:377:377) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~6) + (DELAY + (ABSOLUTE + (PORT dataa (295:295:295) (317:317:317)) + (PORT datab (304:304:304) (317:317:317)) + (PORT datac (899:899:899) (811:811:811)) + (PORT datad (472:472:472) (420:420:420)) + (IOPATH dataa combout (428:428:428) (450:450:450)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT datac (900:900:900) (813:813:813)) + (PORT datad (823:823:823) (719:719:719)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~11) + (DELAY + (ABSOLUTE + (PORT dataa (892:892:892) (727:727:727)) + (PORT datab (325:325:325) (345:345:345)) + (PORT datac (780:780:780) (666:666:666)) + (PORT datad (271:271:271) (289:289:289)) + (IOPATH dataa combout (394:394:394) (400:400:400)) + (IOPATH datab combout (400:400:400) (391:391:391)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (319:319:319)) + (PORT datab (291:291:291) (299:299:299)) + (PORT datac (232:232:232) (250:250:250)) + (PORT datad (778:778:778) (673:673:673)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~13) + (DELAY + (ABSOLUTE + (PORT dataa (567:567:567) (475:475:475)) + (PORT datab (276:276:276) (286:286:286)) + (PORT datac (271:271:271) (287:287:287)) + (PORT datad (235:235:235) (245:245:245)) + (IOPATH dataa combout (351:351:351) (371:371:371)) + (IOPATH datab combout (357:357:357) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (724:724:724)) + (PORT datab (318:318:318) (341:341:341)) + (PORT datac (822:822:822) (751:751:751)) + (PORT datad (846:846:846) (719:719:719)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (866:866:866) (764:764:764)) + (PORT datab (951:951:951) (842:842:842)) + (PORT datac (1086:1086:1086) (919:919:919)) + (PORT datad (1154:1154:1154) (980:980:980)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (384:384:384) (386:386:386)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~16) + (DELAY + (ABSOLUTE + (PORT dataa (279:279:279) (295:295:295)) + (PORT datab (307:307:307) (322:322:322)) + (PORT datac (234:234:234) (253:253:253)) + (PORT datad (488:488:488) (418:418:418)) + (IOPATH dataa combout (435:435:435) (425:425:425)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (719:719:719)) + (PORT datab (900:900:900) (750:750:750)) + (PORT datac (274:274:274) (308:308:308)) + (PORT datad (883:883:883) (795:795:795)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~25) + (DELAY + (ABSOLUTE + (PORT dataa (541:541:541) (447:447:447)) + (PORT datab (501:501:501) (443:443:443)) + (PORT datac (248:248:248) (264:264:264)) + (PORT datad (791:791:791) (683:683:683)) + (IOPATH dataa combout (420:420:420) (371:371:371)) + (IOPATH datab combout (423:423:423) (398:398:398)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1647:1647:1647) (1666:1666:1666)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1679:1679:1679) (1632:1632:1632)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (824:824:824) (719:719:719)) + (PORT datab (900:900:900) (749:749:749)) + (PORT datac (275:275:275) (308:308:308)) + (PORT datad (277:277:277) (332:332:332)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~18) + (DELAY + (ABSOLUTE + (PORT dataa (891:891:891) (727:727:727)) + (PORT datab (323:323:323) (343:343:343)) + (PORT datac (774:774:774) (661:661:661)) + (PORT datad (271:271:271) (289:289:289)) + (IOPATH dataa combout (420:420:420) (444:444:444)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~14) + (DELAY + (ABSOLUTE + (PORT datab (300:300:300) (310:310:310)) + (PORT datac (781:781:781) (668:668:668)) + (PORT datad (285:285:285) (307:307:307)) + (IOPATH datab combout (423:423:423) (451:451:451)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~26) + (DELAY + (ABSOLUTE + (PORT dataa (818:818:818) (699:699:699)) + (PORT datab (266:266:266) (272:272:272)) + (PORT datac (255:255:255) (273:273:273)) + (PORT datad (252:252:252) (261:261:261)) + (IOPATH dataa combout (408:408:408) (425:425:425)) + (IOPATH datab combout (415:415:415) (425:425:425)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~19) + (DELAY + (ABSOLUTE + (PORT datab (910:910:910) (765:765:765)) + (PORT datad (484:484:484) (412:412:412)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (826:826:826) (721:721:721)) + (PORT datab (903:903:903) (753:753:753)) + (PORT datac (274:274:274) (307:307:307)) + (PORT datad (801:801:801) (739:739:739)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (512:512:512) (463:463:463)) + (PORT datab (959:959:959) (818:818:818)) + (PORT datad (1152:1152:1152) (978:978:978)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (380:380:380) (380:380:380)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~20) + (DELAY + (ABSOLUTE + (PORT dataa (860:860:860) (749:749:749)) + (PORT datac (819:819:819) (709:709:709)) + (PORT datad (882:882:882) (754:754:754)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~21) + (DELAY + (ABSOLUTE + (PORT dataa (557:557:557) (463:463:463)) + (PORT datab (907:907:907) (762:762:762)) + (PORT datac (460:460:460) (399:399:399)) + (PORT datad (228:228:228) (235:235:235)) + (IOPATH dataa combout (377:377:377) (371:371:371)) + (IOPATH datab combout (423:423:423) (391:391:391)) + (IOPATH datac combout (305:305:305) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (828:828:828) (724:724:724)) + (PORT datab (907:907:907) (758:758:758)) + (PORT datac (273:273:273) (306:306:306)) + (PORT datad (903:903:903) (814:814:814)) + (IOPATH dataa combout (350:350:350) (371:371:371)) + (IOPATH datab combout (354:354:354) (380:380:380)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~22) + (DELAY + (ABSOLUTE + (PORT dataa (296:296:296) (319:319:319)) + (PORT datab (866:866:866) (728:728:728)) + (PORT datac (900:900:900) (813:813:813)) + (PORT datad (266:266:266) (280:280:280)) + (IOPATH dataa combout (349:349:349) (371:371:371)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~23) + (DELAY + (ABSOLUTE + (PORT dataa (302:302:302) (318:318:318)) + (PORT datab (273:273:273) (282:282:282)) + (PORT datac (448:448:448) (384:384:384)) + (PORT datad (270:270:270) (287:287:287)) + (IOPATH dataa combout (373:373:373) (380:380:380)) + (IOPATH datab combout (438:438:438) (455:455:455)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[11\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (825:825:825) (720:720:720)) + (PORT datab (889:889:889) (814:814:814)) + (PORT datac (274:274:274) (308:308:308)) + (PORT datad (840:840:840) (712:712:712)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~24) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (297:297:297)) + (PORT datab (311:311:311) (325:325:325)) + (PORT datac (448:448:448) (384:384:384)) + (PORT datad (261:261:261) (275:275:275)) + (IOPATH dataa combout (435:435:435) (407:407:407)) + (IOPATH datab combout (437:437:437) (407:407:407)) + (IOPATH datac combout (301:301:301) (285:285:285)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1648:1648:1648) (1668:1668:1668)) + (PORT d (90:90:90) (101:101:101)) + (PORT clrn (1680:1680:1680) (1633:1633:1633)) + (IOPATH (posedge clk) q (240:240:240) (240:240:240)) + (IOPATH (negedge clrn) q (222:222:222) (222:222:222)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (195:195:195)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[12\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (827:827:827) (723:723:723)) + (PORT datab (831:831:831) (724:724:724)) + (PORT datac (273:273:273) (307:307:307)) + (PORT datad (844:844:844) (717:717:717)) + (IOPATH dataa combout (414:414:414) (444:444:444)) + (IOPATH datab combout (423:423:423) (380:380:380)) + (IOPATH datac combout (305:305:305) (283:283:283)) + (IOPATH datad combout (167:167:167) (143:143:143)) + ) + ) + ) +) diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_85c_slow.vo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_85c_slow.vo new file mode 100644 index 0000000..cb1e982 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_85c_slow.vo @@ -0,0 +1,2833 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:42:20" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module vga_colorbar ( + sys_clk, + sys_rst_n, + hsync, + vsync, + rgb); +input sys_clk; +input sys_rst_n; +output hsync; +output vsync; +output [15:0] rgb; + +// Design Ports Information +// hsync => Location: PIN_AA18, I/O Standard: 2.5 V, Current Strength: Default +// vsync => Location: PIN_AB17, I/O Standard: 2.5 V, Current Strength: Default +// rgb[0] => Location: PIN_AB18, I/O Standard: 2.5 V, Current Strength: Default +// rgb[1] => Location: PIN_AA19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[2] => Location: PIN_AB19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[3] => Location: PIN_Y21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[4] => Location: PIN_W19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[5] => Location: PIN_W20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[6] => Location: PIN_U21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[7] => Location: PIN_U22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[8] => Location: PIN_N20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[9] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[10] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[11] => Location: PIN_M22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[12] => Location: PIN_L21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[13] => Location: PIN_L22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[14] => Location: PIN_K21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[15] => Location: PIN_J21, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("vga_colorbar_8_1200mv_85c_v_slow.sdo"); +// synopsys translate_on + +wire \vga_ctrl_inst|Add0~4_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \vga_ctrl_inst|Add1~0_combout ; +wire \vga_ctrl_inst|Add1~2_combout ; +wire \vga_ctrl_inst|Add1~4_combout ; +wire \vga_ctrl_inst|Add1~6_combout ; +wire \vga_ctrl_inst|Add1~8_combout ; +wire \vga_ctrl_inst|Add1~10_combout ; +wire \vga_ctrl_inst|Add1~12_combout ; +wire \vga_ctrl_inst|Add1~16_combout ; +wire \vga_ctrl_inst|Equal0~0_combout ; +wire \vga_ctrl_inst|cnt_v[8]~3_combout ; +wire \vga_pic_inst|pix_data[4]~5_combout ; +wire \vga_pic_inst|pix_data~8_combout ; +wire \vga_pic_inst|pix_data~15_combout ; +wire \vga_pic_inst|pix_data~17_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~1 ; +wire \vga_ctrl_inst|Add0~3 ; +wire \vga_ctrl_inst|Add0~5 ; +wire \vga_ctrl_inst|Add0~6_combout ; +wire \vga_ctrl_inst|Add0~7 ; +wire \vga_ctrl_inst|Add0~8_combout ; +wire \vga_ctrl_inst|Add0~9 ; +wire \vga_ctrl_inst|Add0~11 ; +wire \vga_ctrl_inst|Add0~12_combout ; +wire \vga_ctrl_inst|Add0~13 ; +wire \vga_ctrl_inst|Add0~14_combout ; +wire \vga_ctrl_inst|Add0~15 ; +wire \vga_ctrl_inst|Add0~16_combout ; +wire \vga_ctrl_inst|Add0~17 ; +wire \vga_ctrl_inst|Add0~18_combout ; +wire \vga_ctrl_inst|cnt_h~1_combout ; +wire \vga_ctrl_inst|Add0~10_combout ; +wire \vga_ctrl_inst|cnt_h~0_combout ; +wire \vga_ctrl_inst|Equal0~2_combout ; +wire \vga_ctrl_inst|Add0~2_combout ; +wire \vga_ctrl_inst|Equal0~1_combout ; +wire \vga_ctrl_inst|Equal0~3_combout ; +wire \vga_ctrl_inst|cnt_h~2_combout ; +wire \vga_ctrl_inst|LessThan2~0_combout ; +wire \vga_ctrl_inst|LessThan0~0_combout ; +wire \vga_ctrl_inst|cnt_v[0]~9_combout ; +wire \vga_ctrl_inst|cnt_v[2]~8_combout ; +wire \vga_ctrl_inst|cnt_v[4]~6_combout ; +wire \vga_ctrl_inst|always1~1_combout ; +wire \vga_ctrl_inst|cnt_v[1]~0_combout ; +wire \vga_ctrl_inst|always1~2_combout ; +wire \vga_ctrl_inst|cnt_v[3]~7_combout ; +wire \vga_ctrl_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|cnt_v[5]~2_combout ; +wire \vga_ctrl_inst|Add1~1 ; +wire \vga_ctrl_inst|Add1~3 ; +wire \vga_ctrl_inst|Add1~5 ; +wire \vga_ctrl_inst|Add1~7 ; +wire \vga_ctrl_inst|Add1~9 ; +wire \vga_ctrl_inst|Add1~11 ; +wire \vga_ctrl_inst|Add1~13 ; +wire \vga_ctrl_inst|Add1~14_combout ; +wire \vga_ctrl_inst|cnt_v[7]~4_combout ; +wire \vga_ctrl_inst|Add1~15 ; +wire \vga_ctrl_inst|Add1~17 ; +wire \vga_ctrl_inst|Add1~18_combout ; +wire \vga_ctrl_inst|cnt_v[9]~1_combout ; +wire \vga_ctrl_inst|cnt_v[6]~5_combout ; +wire \vga_ctrl_inst|always1~0_combout ; +wire \vga_ctrl_inst|LessThan1~0_combout ; +wire \vga_ctrl_inst|LessThan6~1_combout ; +wire \vga_ctrl_inst|pix_data_req~1_combout ; +wire \vga_ctrl_inst|pix_data_req~2_combout ; +wire \vga_ctrl_inst|LessThan2~1_combout ; +wire \vga_ctrl_inst|rgb_valid~0_combout ; +wire \vga_ctrl_inst|Add2~1_cout ; +wire \vga_ctrl_inst|Add2~3_cout ; +wire \vga_ctrl_inst|Add2~5_cout ; +wire \vga_ctrl_inst|Add2~7_cout ; +wire \vga_ctrl_inst|Add2~9_cout ; +wire \vga_ctrl_inst|Add2~11 ; +wire \vga_ctrl_inst|Add2~12_combout ; +wire \vga_ctrl_inst|Add2~10_combout ; +wire \vga_pic_inst|LessThan14~0_combout ; +wire \vga_ctrl_inst|Add2~13 ; +wire \vga_ctrl_inst|Add2~15 ; +wire \vga_ctrl_inst|Add2~16_combout ; +wire \vga_ctrl_inst|Add2~14_combout ; +wire \vga_pic_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|pix_data_req~0_combout ; +wire \vga_ctrl_inst|LessThan4~0_combout ; +wire \vga_ctrl_inst|pix_data_req~3_combout ; +wire \vga_ctrl_inst|pix_data_req~4_combout ; +wire \vga_pic_inst|pix_data~4_combout ; +wire \vga_pic_inst|pix_data~9_combout ; +wire \vga_pic_inst|LessThan17~0_combout ; +wire \vga_pic_inst|pix_data~6_combout ; +wire \vga_pic_inst|pix_data[4]~10_combout ; +wire \vga_pic_inst|pix_data~11_combout ; +wire \vga_pic_inst|pix_data~12_combout ; +wire \vga_pic_inst|pix_data~13_combout ; +wire \vga_ctrl_inst|rgb[0]~0_combout ; +wire \vga_pic_inst|pix_data[4]~7_combout ; +wire \vga_pic_inst|pix_data~16_combout ; +wire \vga_ctrl_inst|rgb[1]~1_combout ; +wire \vga_pic_inst|pix_data~25_combout ; +wire \vga_ctrl_inst|rgb[5]~2_combout ; +wire \vga_pic_inst|pix_data~18_combout ; +wire \vga_pic_inst|pix_data~14_combout ; +wire \vga_pic_inst|pix_data~26_combout ; +wire \vga_pic_inst|pix_data~19_combout ; +wire \vga_ctrl_inst|rgb[7]~3_combout ; +wire \vga_pic_inst|LessThan2~2_combout ; +wire \vga_pic_inst|pix_data~20_combout ; +wire \vga_pic_inst|pix_data~21_combout ; +wire \vga_ctrl_inst|rgb[10]~4_combout ; +wire \vga_pic_inst|pix_data~22_combout ; +wire \vga_pic_inst|pix_data~23_combout ; +wire \vga_ctrl_inst|rgb[11]~5_combout ; +wire \vga_pic_inst|pix_data~24_combout ; +wire \vga_ctrl_inst|rgb[12]~6_combout ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [9:0] \vga_ctrl_inst|cnt_v ; +wire [9:0] \vga_ctrl_inst|cnt_h ; +wire [15:0] \vga_pic_inst|pix_data ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: LCCOMB_X35_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~4 ( +// Equation(s): +// \vga_ctrl_inst|Add0~4_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|Add0~3 $ (GND))) # (!\vga_ctrl_inst|cnt_h [2] & (!\vga_ctrl_inst|Add0~3 & VCC)) +// \vga_ctrl_inst|Add0~5 = CARRY((\vga_ctrl_inst|cnt_h [2] & !\vga_ctrl_inst|Add0~3 )) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~3 ), + .combout(\vga_ctrl_inst|Add0~4_combout ), + .cout(\vga_ctrl_inst|Add0~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 6891; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~0 ( +// Equation(s): +// \vga_ctrl_inst|Add1~0_combout = \vga_ctrl_inst|cnt_v [0] $ (VCC) +// \vga_ctrl_inst|Add1~1 = CARRY(\vga_ctrl_inst|cnt_v [0]) + + .dataa(\vga_ctrl_inst|cnt_v [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add1~0_combout ), + .cout(\vga_ctrl_inst|Add1~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~0 .lut_mask = 16'h55AA; +defparam \vga_ctrl_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~2 ( +// Equation(s): +// \vga_ctrl_inst|Add1~2_combout = (\vga_ctrl_inst|cnt_v [1] & (!\vga_ctrl_inst|Add1~1 )) # (!\vga_ctrl_inst|cnt_v [1] & ((\vga_ctrl_inst|Add1~1 ) # (GND))) +// \vga_ctrl_inst|Add1~3 = CARRY((!\vga_ctrl_inst|Add1~1 ) # (!\vga_ctrl_inst|cnt_v [1])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~1 ), + .combout(\vga_ctrl_inst|Add1~2_combout ), + .cout(\vga_ctrl_inst|Add1~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~4 ( +// Equation(s): +// \vga_ctrl_inst|Add1~4_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|Add1~3 $ (GND))) # (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|Add1~3 & VCC)) +// \vga_ctrl_inst|Add1~5 = CARRY((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Add1~3 )) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~3 ), + .combout(\vga_ctrl_inst|Add1~4_combout ), + .cout(\vga_ctrl_inst|Add1~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~6 ( +// Equation(s): +// \vga_ctrl_inst|Add1~6_combout = (\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|Add1~5 )) # (!\vga_ctrl_inst|cnt_v [3] & ((\vga_ctrl_inst|Add1~5 ) # (GND))) +// \vga_ctrl_inst|Add1~7 = CARRY((!\vga_ctrl_inst|Add1~5 ) # (!\vga_ctrl_inst|cnt_v [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~5 ), + .combout(\vga_ctrl_inst|Add1~6_combout ), + .cout(\vga_ctrl_inst|Add1~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~8 ( +// Equation(s): +// \vga_ctrl_inst|Add1~8_combout = (\vga_ctrl_inst|cnt_v [4] & (\vga_ctrl_inst|Add1~7 $ (GND))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|Add1~7 & VCC)) +// \vga_ctrl_inst|Add1~9 = CARRY((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Add1~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~7 ), + .combout(\vga_ctrl_inst|Add1~8_combout ), + .cout(\vga_ctrl_inst|Add1~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~10 ( +// Equation(s): +// \vga_ctrl_inst|Add1~10_combout = (\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|Add1~9 )) # (!\vga_ctrl_inst|cnt_v [5] & ((\vga_ctrl_inst|Add1~9 ) # (GND))) +// \vga_ctrl_inst|Add1~11 = CARRY((!\vga_ctrl_inst|Add1~9 ) # (!\vga_ctrl_inst|cnt_v [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~9 ), + .combout(\vga_ctrl_inst|Add1~10_combout ), + .cout(\vga_ctrl_inst|Add1~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~10 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~12 ( +// Equation(s): +// \vga_ctrl_inst|Add1~12_combout = (\vga_ctrl_inst|cnt_v [6] & (\vga_ctrl_inst|Add1~11 $ (GND))) # (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|Add1~11 & VCC)) +// \vga_ctrl_inst|Add1~13 = CARRY((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Add1~11 )) + + .dataa(\vga_ctrl_inst|cnt_v [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~11 ), + .combout(\vga_ctrl_inst|Add1~12_combout ), + .cout(\vga_ctrl_inst|Add1~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~16 ( +// Equation(s): +// \vga_ctrl_inst|Add1~16_combout = (\vga_ctrl_inst|cnt_v [8] & (\vga_ctrl_inst|Add1~15 $ (GND))) # (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|Add1~15 & VCC)) +// \vga_ctrl_inst|Add1~17 = CARRY((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Add1~15 )) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~15 ), + .combout(\vga_ctrl_inst|Add1~16_combout ), + .cout(\vga_ctrl_inst|Add1~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~16 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y23_N13 +dffeas \vga_ctrl_inst|cnt_v[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~0 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~0_combout = (\vga_ctrl_inst|cnt_h [8] & \vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~0 .lut_mask = 16'hCC00; +defparam \vga_ctrl_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N13 +dffeas \vga_ctrl_inst|cnt_h[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[8]~3 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[8]~3_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~16_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [8])))) + + .dataa(\vga_ctrl_inst|Add1~16_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [8]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8]~3 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[8]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~5 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~5_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~16_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~16_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~5 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~8 ( +// Equation(s): +// \vga_pic_inst|pix_data~8_combout = (\vga_ctrl_inst|Add2~16_combout ) # (((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) # (!\vga_ctrl_inst|Add2~10_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~8 .lut_mask = 16'hFBFF; +defparam \vga_pic_inst|pix_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N10 +cycloneive_lcell_comb \vga_pic_inst|pix_data~15 ( +// Equation(s): +// \vga_pic_inst|pix_data~15_combout = (\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|pix_data~11_combout & ((!\vga_pic_inst|pix_data[4]~10_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_pic_inst|pix_data~11_combout ), + .datab(\vga_pic_inst|pix_data~14_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data[4]~5_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~15_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~15 .lut_mask = 16'h0ACC; +defparam \vga_pic_inst|pix_data~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~17 ( +// Equation(s): +// \vga_pic_inst|pix_data~17_combout = (\vga_ctrl_inst|Add2~12_combout & (!\vga_ctrl_inst|Add2~14_combout )) # (!\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|Add2~14_combout & !\vga_ctrl_inst|Add2~10_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~17_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~17 .lut_mask = 16'h0C3C; +defparam \vga_pic_inst|pix_data~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N30 +cycloneive_io_obuf \hsync~output ( + .i(!\vga_ctrl_inst|LessThan0~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(hsync), + .obar()); +// synopsys translate_off +defparam \hsync~output .bus_hold = "false"; +defparam \hsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X28_Y0_N2 +cycloneive_io_obuf \vsync~output ( + .i(!\vga_ctrl_inst|LessThan1~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(vsync), + .obar()); +// synopsys translate_off +defparam \vsync~output .bus_hold = "false"; +defparam \vsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X32_Y0_N2 +cycloneive_io_obuf \rgb[0]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[0]), + .obar()); +// synopsys translate_off +defparam \rgb[0]~output .bus_hold = "false"; +defparam \rgb[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N23 +cycloneive_io_obuf \rgb[1]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[1]), + .obar()); +// synopsys translate_off +defparam \rgb[1]~output .bus_hold = "false"; +defparam \rgb[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N16 +cycloneive_io_obuf \rgb[2]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[2]), + .obar()); +// synopsys translate_off +defparam \rgb[2]~output .bus_hold = "false"; +defparam \rgb[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y4_N9 +cycloneive_io_obuf \rgb[3]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[3]), + .obar()); +// synopsys translate_off +defparam \rgb[3]~output .bus_hold = "false"; +defparam \rgb[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N9 +cycloneive_io_obuf \rgb[4]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[4]), + .obar()); +// synopsys translate_off +defparam \rgb[4]~output .bus_hold = "false"; +defparam \rgb[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N16 +cycloneive_io_obuf \rgb[5]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[5]), + .obar()); +// synopsys translate_off +defparam \rgb[5]~output .bus_hold = "false"; +defparam \rgb[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N2 +cycloneive_io_obuf \rgb[6]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[6]), + .obar()); +// synopsys translate_off +defparam \rgb[6]~output .bus_hold = "false"; +defparam \rgb[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N9 +cycloneive_io_obuf \rgb[7]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[7]), + .obar()); +// synopsys translate_off +defparam \rgb[7]~output .bus_hold = "false"; +defparam \rgb[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y12_N16 +cycloneive_io_obuf \rgb[8]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[8]), + .obar()); +// synopsys translate_off +defparam \rgb[8]~output .bus_hold = "false"; +defparam \rgb[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N9 +cycloneive_io_obuf \rgb[9]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[9]), + .obar()); +// synopsys translate_off +defparam \rgb[9]~output .bus_hold = "false"; +defparam \rgb[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y14_N23 +cycloneive_io_obuf \rgb[10]~output ( + .i(\vga_ctrl_inst|rgb[10]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[10]), + .obar()); +// synopsys translate_off +defparam \rgb[10]~output .bus_hold = "false"; +defparam \rgb[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N2 +cycloneive_io_obuf \rgb[11]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[11]), + .obar()); +// synopsys translate_off +defparam \rgb[11]~output .bus_hold = "false"; +defparam \rgb[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N16 +cycloneive_io_obuf \rgb[12]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[12]), + .obar()); +// synopsys translate_off +defparam \rgb[12]~output .bus_hold = "false"; +defparam \rgb[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N23 +cycloneive_io_obuf \rgb[13]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[13]), + .obar()); +// synopsys translate_off +defparam \rgb[13]~output .bus_hold = "false"; +defparam \rgb[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y19_N9 +cycloneive_io_obuf \rgb[14]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[14]), + .obar()); +// synopsys translate_off +defparam \rgb[14]~output .bus_hold = "false"; +defparam \rgb[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y20_N23 +cycloneive_io_obuf \rgb[15]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[15]), + .obar()); +// synopsys translate_off +defparam \rgb[15]~output .bus_hold = "false"; +defparam \rgb[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~0 ( +// Equation(s): +// \vga_ctrl_inst|Add0~0_combout = \vga_ctrl_inst|cnt_h [0] $ (VCC) +// \vga_ctrl_inst|Add0~1 = CARRY(\vga_ctrl_inst|cnt_h [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add0~0_combout ), + .cout(\vga_ctrl_inst|Add0~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X35_Y3_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N10 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\sys_rst_n~input_o ) # (!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .datac(\sys_rst_n~input_o ), + .datad(gnd), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h7F7F; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X35_Y23_N9 +dffeas \vga_ctrl_inst|cnt_h[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~2 ( +// Equation(s): +// \vga_ctrl_inst|Add0~2_combout = (\vga_ctrl_inst|cnt_h [1] & (!\vga_ctrl_inst|Add0~1 )) # (!\vga_ctrl_inst|cnt_h [1] & ((\vga_ctrl_inst|Add0~1 ) # (GND))) +// \vga_ctrl_inst|Add0~3 = CARRY((!\vga_ctrl_inst|Add0~1 ) # (!\vga_ctrl_inst|cnt_h [1])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~1 ), + .combout(\vga_ctrl_inst|Add0~2_combout ), + .cout(\vga_ctrl_inst|Add0~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~6 ( +// Equation(s): +// \vga_ctrl_inst|Add0~6_combout = (\vga_ctrl_inst|cnt_h [3] & (!\vga_ctrl_inst|Add0~5 )) # (!\vga_ctrl_inst|cnt_h [3] & ((\vga_ctrl_inst|Add0~5 ) # (GND))) +// \vga_ctrl_inst|Add0~7 = CARRY((!\vga_ctrl_inst|Add0~5 ) # (!\vga_ctrl_inst|cnt_h [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~5 ), + .combout(\vga_ctrl_inst|Add0~6_combout ), + .cout(\vga_ctrl_inst|Add0~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N15 +dffeas \vga_ctrl_inst|cnt_h[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~8 ( +// Equation(s): +// \vga_ctrl_inst|Add0~8_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Add0~7 $ (GND))) # (!\vga_ctrl_inst|cnt_h [4] & (!\vga_ctrl_inst|Add0~7 & VCC)) +// \vga_ctrl_inst|Add0~9 = CARRY((\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add0~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~7 ), + .combout(\vga_ctrl_inst|Add0~8_combout ), + .cout(\vga_ctrl_inst|Add0~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N17 +dffeas \vga_ctrl_inst|cnt_h[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~10 ( +// Equation(s): +// \vga_ctrl_inst|Add0~10_combout = (\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|Add0~9 )) # (!\vga_ctrl_inst|cnt_h [5] & ((\vga_ctrl_inst|Add0~9 ) # (GND))) +// \vga_ctrl_inst|Add0~11 = CARRY((!\vga_ctrl_inst|Add0~9 ) # (!\vga_ctrl_inst|cnt_h [5])) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~9 ), + .combout(\vga_ctrl_inst|Add0~10_combout ), + .cout(\vga_ctrl_inst|Add0~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~12 ( +// Equation(s): +// \vga_ctrl_inst|Add0~12_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add0~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add0~11 & VCC)) +// \vga_ctrl_inst|Add0~13 = CARRY((\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add0~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~11 ), + .combout(\vga_ctrl_inst|Add0~12_combout ), + .cout(\vga_ctrl_inst|Add0~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N21 +dffeas \vga_ctrl_inst|cnt_h[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~14 ( +// Equation(s): +// \vga_ctrl_inst|Add0~14_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add0~13 )) # (!\vga_ctrl_inst|cnt_h [7] & ((\vga_ctrl_inst|Add0~13 ) # (GND))) +// \vga_ctrl_inst|Add0~15 = CARRY((!\vga_ctrl_inst|Add0~13 ) # (!\vga_ctrl_inst|cnt_h [7])) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~13 ), + .combout(\vga_ctrl_inst|Add0~14_combout ), + .cout(\vga_ctrl_inst|Add0~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N23 +dffeas \vga_ctrl_inst|cnt_h[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~16 ( +// Equation(s): +// \vga_ctrl_inst|Add0~16_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add0~15 $ (GND))) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add0~15 & VCC)) +// \vga_ctrl_inst|Add0~17 = CARRY((\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add0~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~15 ), + .combout(\vga_ctrl_inst|Add0~16_combout ), + .cout(\vga_ctrl_inst|Add0~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~18 ( +// Equation(s): +// \vga_ctrl_inst|Add0~18_combout = \vga_ctrl_inst|Add0~17 $ (\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(\vga_ctrl_inst|Add0~17 ), + .combout(\vga_ctrl_inst|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~1_combout = (!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|Add0~18_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|Add0~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~1 .lut_mask = 16'h3030; +defparam \vga_ctrl_inst|cnt_h~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N1 +dffeas \vga_ctrl_inst|cnt_h[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~0_combout = (\vga_ctrl_inst|Add0~10_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~10_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~0 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N25 +dffeas \vga_ctrl_inst|cnt_h[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~2 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~2_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|cnt_h [9] & (!\vga_ctrl_inst|cnt_h [5] & !\vga_ctrl_inst|cnt_h [6]))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [9]), + .datac(\vga_ctrl_inst|cnt_h [5]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~2 .lut_mask = 16'h0008; +defparam \vga_ctrl_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N11 +dffeas \vga_ctrl_inst|cnt_h[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~1 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~1_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|cnt_h [3] & (\vga_ctrl_inst|cnt_h [0] & \vga_ctrl_inst|cnt_h [1]))) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(\vga_ctrl_inst|cnt_h [0]), + .datad(\vga_ctrl_inst|cnt_h [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~3 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~3_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Equal0~2_combout & (\vga_ctrl_inst|Equal0~1_combout & !\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(\vga_ctrl_inst|Equal0~2_combout ), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|cnt_h [7]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~3 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~2_combout = (\vga_ctrl_inst|Add0~16_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~16_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~2 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N3 +dffeas \vga_ctrl_inst|cnt_h[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~0_combout = (!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~0 .lut_mask = 16'h0033; +defparam \vga_ctrl_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~0_combout = (\vga_ctrl_inst|cnt_h [7]) # (((\vga_ctrl_inst|cnt_h [6] & \vga_ctrl_inst|cnt_h [5])) # (!\vga_ctrl_inst|LessThan2~0_combout )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~0 .lut_mask = 16'hEFAF; +defparam \vga_ctrl_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[0]~9 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[0]~9_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~0_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [0])))) + + .dataa(\vga_ctrl_inst|Add1~0_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0]~9 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N29 +dffeas \vga_ctrl_inst|cnt_v[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[2]~8 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[2]~8_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~4_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [2])))) + + .dataa(\vga_ctrl_inst|Add1~4_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2]~8 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N5 +dffeas \vga_ctrl_inst|cnt_v[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[4]~6 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[4]~6_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~8_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [4])))) + + .dataa(\vga_ctrl_inst|Add1~8_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [4]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4]~6 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[4]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N1 +dffeas \vga_ctrl_inst|cnt_v[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|always1~1 ( +// Equation(s): +// \vga_ctrl_inst|always1~1_combout = (\vga_ctrl_inst|cnt_v [9] & (\vga_ctrl_inst|cnt_v [3] & (\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4]))) + + .dataa(\vga_ctrl_inst|cnt_v [9]), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~1 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|always1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[1]~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[1]~0_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~2_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [1])))) + + .dataa(\vga_ctrl_inst|Add1~2_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1]~0 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N17 +dffeas \vga_ctrl_inst|cnt_v[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|always1~2 ( +// Equation(s): +// \vga_ctrl_inst|always1~2_combout = (\vga_ctrl_inst|always1~0_combout & (!\vga_ctrl_inst|cnt_v [0] & (\vga_ctrl_inst|always1~1_combout & !\vga_ctrl_inst|cnt_v [1]))) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(\vga_ctrl_inst|always1~1_combout ), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~2 .lut_mask = 16'h0020; +defparam \vga_ctrl_inst|always1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[3]~7 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[3]~7_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~6_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [3])))) + + .dataa(\vga_ctrl_inst|Add1~6_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3]~7 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N3 +dffeas \vga_ctrl_inst|cnt_v[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~0_combout = (!\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~0 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[5]~2_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~10_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [5])))) + + .dataa(\vga_ctrl_inst|Add1~10_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5]~2 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N19 +dffeas \vga_ctrl_inst|cnt_v[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~14 ( +// Equation(s): +// \vga_ctrl_inst|Add1~14_combout = (\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|Add1~13 )) # (!\vga_ctrl_inst|cnt_v [7] & ((\vga_ctrl_inst|Add1~13 ) # (GND))) +// \vga_ctrl_inst|Add1~15 = CARRY((!\vga_ctrl_inst|Add1~13 ) # (!\vga_ctrl_inst|cnt_v [7])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~13 ), + .combout(\vga_ctrl_inst|Add1~14_combout ), + .cout(\vga_ctrl_inst|Add1~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~14 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[7]~4 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[7]~4_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~14_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [7])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~14_combout ), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7]~4 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N3 +dffeas \vga_ctrl_inst|cnt_v[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~18 ( +// Equation(s): +// \vga_ctrl_inst|Add1~18_combout = \vga_ctrl_inst|Add1~17 $ (\vga_ctrl_inst|cnt_v [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [9]), + .cin(\vga_ctrl_inst|Add1~17 ), + .combout(\vga_ctrl_inst|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[9]~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[9]~1_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~18_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [9])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~18_combout ), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9]~1 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N1 +dffeas \vga_ctrl_inst|cnt_v[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[6]~5 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[6]~5_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~12_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [6])))) + + .dataa(\vga_ctrl_inst|Add1~12_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6]~5 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N5 +dffeas \vga_ctrl_inst|cnt_v[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|always1~0 ( +// Equation(s): +// \vga_ctrl_inst|always1~0_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan1~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan1~0_combout = ((\vga_ctrl_inst|cnt_v [1]) # ((\vga_ctrl_inst|cnt_v [9]) # (!\vga_ctrl_inst|always1~0_combout ))) # (!\vga_ctrl_inst|LessThan6~0_combout ) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan1~0 .lut_mask = 16'hFDFF; +defparam \vga_ctrl_inst|LessThan1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~1_combout = (!\vga_ctrl_inst|cnt_v [1]) # (!\vga_ctrl_inst|cnt_v [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~1 .lut_mask = 16'h33FF; +defparam \vga_ctrl_inst|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N30 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~1_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~1 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~2 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~2_combout = (\vga_ctrl_inst|LessThan6~0_combout & ((\vga_ctrl_inst|LessThan6~1_combout & (\vga_ctrl_inst|pix_data_req~1_combout )) # (!\vga_ctrl_inst|LessThan6~1_combout & ((\vga_ctrl_inst|always1~0_combout ))))) # +// (!\vga_ctrl_inst|LessThan6~0_combout & (((\vga_ctrl_inst|always1~0_combout )))) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|LessThan6~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~2 .lut_mask = 16'hF780; +defparam \vga_ctrl_inst|pix_data_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~1_combout = (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~1 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|rgb_valid~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb_valid~0_combout = (\vga_ctrl_inst|Equal0~0_combout & (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|LessThan2~0_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout & (((\vga_ctrl_inst|cnt_h [7] & +// !\vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|LessThan2~0_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb_valid~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb_valid~0 .lut_mask = 16'h0745; +defparam \vga_ctrl_inst|rgb_valid~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~1 ( +// Equation(s): +// \vga_ctrl_inst|Add2~1_cout = CARRY((\vga_ctrl_inst|cnt_h [1] & \vga_ctrl_inst|cnt_h [0])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\vga_ctrl_inst|Add2~1_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~1 .lut_mask = 16'h0088; +defparam \vga_ctrl_inst|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~3 ( +// Equation(s): +// \vga_ctrl_inst|Add2~3_cout = CARRY((!\vga_ctrl_inst|Add2~1_cout ) # (!\vga_ctrl_inst|cnt_h [2])) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~1_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~3_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~3 .lut_mask = 16'h005F; +defparam \vga_ctrl_inst|Add2~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~5 ( +// Equation(s): +// \vga_ctrl_inst|Add2~5_cout = CARRY((\vga_ctrl_inst|cnt_h [3] & !\vga_ctrl_inst|Add2~3_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~3_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~5_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~5 .lut_mask = 16'h000A; +defparam \vga_ctrl_inst|Add2~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~7 ( +// Equation(s): +// \vga_ctrl_inst|Add2~7_cout = CARRY((!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add2~5_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~5_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~7_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~7 .lut_mask = 16'h0005; +defparam \vga_ctrl_inst|Add2~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~9 ( +// Equation(s): +// \vga_ctrl_inst|Add2~9_cout = CARRY((\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|Add2~7_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~7_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~9_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~9 .lut_mask = 16'h00AF; +defparam \vga_ctrl_inst|Add2~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~10 ( +// Equation(s): +// \vga_ctrl_inst|Add2~10_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add2~9_cout & VCC)) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add2~9_cout )) +// \vga_ctrl_inst|Add2~11 = CARRY((!\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add2~9_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~9_cout ), + .combout(\vga_ctrl_inst|Add2~10_combout ), + .cout(\vga_ctrl_inst|Add2~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~10 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~12 ( +// Equation(s): +// \vga_ctrl_inst|Add2~12_combout = (\vga_ctrl_inst|cnt_h [7] & (\vga_ctrl_inst|Add2~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add2~11 & VCC)) +// \vga_ctrl_inst|Add2~13 = CARRY((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|Add2~11 )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~11 ), + .combout(\vga_ctrl_inst|Add2~12_combout ), + .cout(\vga_ctrl_inst|Add2~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N24 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~0 ( +// Equation(s): +// \vga_pic_inst|LessThan14~0_combout = (\vga_ctrl_inst|Add2~12_combout & \vga_ctrl_inst|Add2~10_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~0 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|LessThan14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~14 ( +// Equation(s): +// \vga_ctrl_inst|Add2~14_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add2~13 & VCC)) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add2~13 )) +// \vga_ctrl_inst|Add2~15 = CARRY((!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add2~13 )) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~13 ), + .combout(\vga_ctrl_inst|Add2~14_combout ), + .cout(\vga_ctrl_inst|Add2~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~14 .lut_mask = 16'hA505; +defparam \vga_ctrl_inst|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~16 ( +// Equation(s): +// \vga_ctrl_inst|Add2~16_combout = \vga_ctrl_inst|cnt_h [9] $ (\vga_ctrl_inst|Add2~15 ) + + .dataa(\vga_ctrl_inst|cnt_h [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\vga_ctrl_inst|Add2~15 ), + .combout(\vga_ctrl_inst|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~16 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|Add2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N2 +cycloneive_lcell_comb \vga_pic_inst|LessThan6~0 ( +// Equation(s): +// \vga_pic_inst|LessThan6~0_combout = ((\vga_pic_inst|LessThan14~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (\vga_ctrl_inst|Add2~14_combout ))) # (!\vga_ctrl_inst|pix_data_req~4_combout ) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|LessThan14~0_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan6~0 .lut_mask = 16'hFFFD; +defparam \vga_pic_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~0_combout = (!\vga_ctrl_inst|always1~0_combout & \vga_ctrl_inst|cnt_v [9]) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~0 .lut_mask = 16'h5050; +defparam \vga_ctrl_inst|pix_data_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan4~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan4~0_combout = (\vga_ctrl_inst|LessThan2~0_combout & (((!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan4~0 .lut_mask = 16'h7030; +defparam \vga_ctrl_inst|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~3 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~3_combout = ((!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout ) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~3 .lut_mask = 16'h5755; +defparam \vga_ctrl_inst|pix_data_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~4 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (!\vga_ctrl_inst|LessThan4~0_combout & \vga_ctrl_inst|pix_data_req~3_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|LessThan4~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~4 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|pix_data_req~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~4 ( +// Equation(s): +// \vga_pic_inst|pix_data~4_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~4 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~9 ( +// Equation(s): +// \vga_pic_inst|pix_data~9_combout = (\vga_pic_inst|pix_data~8_combout & ((\vga_pic_inst|LessThan6~0_combout ) # ((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data~8_combout & +// (((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) + + .dataa(\vga_pic_inst|pix_data~8_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~9 .lut_mask = 16'h8F88; +defparam \vga_pic_inst|pix_data~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N8 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~0 ( +// Equation(s): +// \vga_pic_inst|LessThan17~0_combout = (\vga_ctrl_inst|Add2~12_combout ) # ((\vga_ctrl_inst|Add2~10_combout ) # ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout ))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~0 .lut_mask = 16'hFEFF; +defparam \vga_pic_inst|LessThan17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~6 ( +// Equation(s): +// \vga_pic_inst|pix_data~6_combout = ((\vga_pic_inst|LessThan17~0_combout & ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|pix_data~4_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~6 .lut_mask = 16'hF755; +defparam \vga_pic_inst|pix_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N22 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~10 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~10_combout = (!\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|Add2~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~10 .lut_mask = 16'h0FFF; +defparam \vga_pic_inst|pix_data[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~11 ( +// Equation(s): +// \vga_pic_inst|pix_data~11_combout = (\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~10_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~11 .lut_mask = 16'h0080; +defparam \vga_pic_inst|pix_data~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data~12 ( +// Equation(s): +// \vga_pic_inst|pix_data~12_combout = (\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data[4]~10_combout ) # (!\vga_pic_inst|pix_data~11_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|LessThan17~0_combout )) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan17~0_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~12 .lut_mask = 16'hE4EE; +defparam \vga_pic_inst|pix_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N16 +cycloneive_lcell_comb \vga_pic_inst|pix_data~13 ( +// Equation(s): +// \vga_pic_inst|pix_data~13_combout = ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~7_combout ), + .datab(\vga_pic_inst|pix_data~9_combout ), + .datac(\vga_pic_inst|pix_data~6_combout ), + .datad(\vga_pic_inst|pix_data~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~13 .lut_mask = 16'h80FF; +defparam \vga_pic_inst|pix_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N17 +dffeas \vga_pic_inst|pix_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[0] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[0]~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb[0]~0_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_ctrl_inst|rgb_valid~0_combout & (\vga_pic_inst|pix_data [0] & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|rgb_valid~0_combout ), + .datac(\vga_pic_inst|pix_data [0]), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[0]~0 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~7 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~7_combout = (!\vga_ctrl_inst|Add2~16_combout & (\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|Add2~12_combout )))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~7 .lut_mask = 16'h0700; +defparam \vga_pic_inst|pix_data[4]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~16 ( +// Equation(s): +// \vga_pic_inst|pix_data~16_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~9_combout ), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~16 .lut_mask = 16'hEAAA; +defparam \vga_pic_inst|pix_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N19 +dffeas \vga_pic_inst|pix_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[1]~1 ( +// Equation(s): +// \vga_ctrl_inst|rgb[1]~1_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [4]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[1]~1 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~25 ( +// Equation(s): +// \vga_pic_inst|pix_data~25_combout = (\vga_ctrl_inst|Add2~16_combout & (((!\vga_pic_inst|LessThan17~0_combout )))) # (!\vga_ctrl_inst|Add2~16_combout & ((\vga_ctrl_inst|pix_data_req~4_combout & (\vga_pic_inst|pix_data~17_combout )) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_pic_inst|LessThan17~0_combout ))))) + + .dataa(\vga_pic_inst|pix_data~17_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~25_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~25 .lut_mask = 16'h20EF; +defparam \vga_pic_inst|pix_data~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N13 +dffeas \vga_pic_inst|pix_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[8] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|rgb[5]~2_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [8]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[5]~2 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~18 ( +// Equation(s): +// \vga_pic_inst|pix_data~18_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~12_combout & !\vga_ctrl_inst|Add2~10_combout )) # (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout +// )))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~18 .lut_mask = 16'h4060; +defparam \vga_pic_inst|pix_data~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~14 ( +// Equation(s): +// \vga_pic_inst|pix_data~14_combout = (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~14_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~14 .lut_mask = 16'h0030; +defparam \vga_pic_inst|pix_data~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~26 ( +// Equation(s): +// \vga_pic_inst|pix_data~26_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~16_combout & ((\vga_pic_inst|pix_data~14_combout ))) # (!\vga_ctrl_inst|Add2~16_combout & (\vga_pic_inst|pix_data~18_combout )))) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|pix_data~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|pix_data~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~26_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~26 .lut_mask = 16'hFD08; +defparam \vga_pic_inst|pix_data~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~19 ( +// Equation(s): +// \vga_pic_inst|pix_data~19_combout = (\vga_pic_inst|pix_data~26_combout & \vga_pic_inst|pix_data~6_combout ) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(gnd), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~19_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~19 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|pix_data~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N1 +dffeas \vga_pic_inst|pix_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[7]~3 ( +// Equation(s): +// \vga_ctrl_inst|rgb[7]~3_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [9]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[7]~3 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N6 +cycloneive_lcell_comb \vga_pic_inst|LessThan2~2 ( +// Equation(s): +// \vga_pic_inst|LessThan2~2_combout = (\vga_pic_inst|LessThan17~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_pic_inst|LessThan17~0_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan2~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan2~2 .lut_mask = 16'hEEFF; +defparam \vga_pic_inst|LessThan2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~20 ( +// Equation(s): +// \vga_pic_inst|pix_data~20_combout = (!\vga_ctrl_inst|Add2~16_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~20 .lut_mask = 16'h0500; +defparam \vga_pic_inst|pix_data~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~21 ( +// Equation(s): +// \vga_pic_inst|pix_data~21_combout = (\vga_pic_inst|LessThan2~2_combout & ((\vga_pic_inst|pix_data~26_combout ) # ((\vga_pic_inst|pix_data~4_combout & \vga_pic_inst|pix_data~20_combout )))) + + .dataa(\vga_pic_inst|pix_data~4_combout ), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(\vga_pic_inst|LessThan2~2_combout ), + .datad(\vga_pic_inst|pix_data~20_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~21_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~21 .lut_mask = 16'hE0C0; +defparam \vga_pic_inst|pix_data~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N27 +dffeas \vga_pic_inst|pix_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[10] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[10]~4 ( +// Equation(s): +// \vga_ctrl_inst|rgb[10]~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [10]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [10]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[10]~4 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N20 +cycloneive_lcell_comb \vga_pic_inst|pix_data~22 ( +// Equation(s): +// \vga_pic_inst|pix_data~22_combout = ((\vga_pic_inst|pix_data[4]~5_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout ))) # (!\vga_pic_inst|LessThan6~0_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~22 .lut_mask = 16'h3B33; +defparam \vga_pic_inst|pix_data~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~23 ( +// Equation(s): +// \vga_pic_inst|pix_data~23_combout = ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|LessThan2~2_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|pix_data[4]~7_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~23_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~23 .lut_mask = 16'hF733; +defparam \vga_pic_inst|pix_data~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N29 +dffeas \vga_pic_inst|pix_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[11]~5 ( +// Equation(s): +// \vga_ctrl_inst|rgb[11]~5_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [13] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [13]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[11]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[11]~5 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[11]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~24 ( +// Equation(s): +// \vga_pic_inst|pix_data~24_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|LessThan2~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~24_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~24 .lut_mask = 16'hEAEE; +defparam \vga_pic_inst|pix_data~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N31 +dffeas \vga_pic_inst|pix_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[15] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[12]~6 ( +// Equation(s): +// \vga_ctrl_inst|rgb[12]~6_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [15] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [15]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[12]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[12]~6 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[12]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_85c_v_slow.sdo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_85c_v_slow.sdo new file mode 100644 index 0000000..3c460d1 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_8_1200mv_85c_v_slow.sdo @@ -0,0 +1,2108 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "vga_colorbar") + (DATE "06/02/2023 04:42:20") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (460:460:460)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (4503:4503:4503) (4503:4503:4503)) + (PORT inclk[0] (2340:2340:2340) (2340:2340:2340)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (961:961:961)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (971:971:971) (950:950:950)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (953:953:953)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datab (1006:1006:1006) (978:978:978)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (569:569:569) (599:599:599)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT datab (960:960:960) (939:939:939)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (603:603:603)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (962:962:962)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT datab (397:397:397) (486:486:486)) + (PORT datad (343:343:343) (426:426:426)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (788:788:788)) + (PORT datab (858:858:858) (836:836:836)) + (PORT datad (316:316:316) (356:356:356)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (1230:1230:1230) (1146:1146:1146)) + (PORT datad (924:924:924) (874:874:874)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1082:1082:1082)) + (PORT datab (967:967:967) (899:899:899)) + (PORT datac (937:937:937) (910:910:910)) + (PORT datad (1184:1184:1184) (1098:1098:1098)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~15) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (803:803:803)) + (PORT datab (509:509:509) (494:494:494)) + (PORT datac (245:245:245) (275:275:275)) + (PORT datad (262:262:262) (300:300:300)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~17) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (383:383:383)) + (PORT datac (842:842:842) (776:776:776)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (806:806:806) (852:852:852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE hsync\~output) + (DELAY + (ABSOLUTE + (PORT i (2108:2108:2108) (2266:2266:2266)) + (IOPATH i o (3174:3174:3174) (3271:3271:3271)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE vsync\~output) + (DELAY + (ABSOLUTE + (PORT i (1864:1864:1864) (2034:2034:2034)) + (IOPATH i o (3184:3184:3184) (3281:3281:3281)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2928:2928:2928) (2696:2696:2696)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2872:2872:2872) (2631:2631:2631)) + (IOPATH i o (3281:3281:3281) (3184:3184:3184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3183:3183:3183) (2900:2900:2900)) + (IOPATH i o (3281:3281:3281) (3184:3184:3184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3530:3530:3530) (3206:3206:3206)) + (IOPATH i o (3429:3429:3429) (3366:3366:3366)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3524:3524:3524) (3201:3201:3201)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1540:1540:1540) (1460:1460:1460)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1581:1581:1581) (1475:1475:1475)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2139:2139:2139) (1969:1969:1969)) + (IOPATH i o (3419:3419:3419) (3356:3356:3356)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1953:1953:1953) (1815:1815:1815)) + (IOPATH i o (3379:3379:3379) (3316:3316:3316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1947:1947:1947) (1781:1781:1781)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1885:1885:1885) (1698:1698:1698)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1851:1851:1851) (1680:1680:1680)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1486:1486:1486) (1329:1329:1329)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1506:1506:1506) (1334:1334:1334)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1091:1091:1091) (970:970:970)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1123:1123:1123) (999:999:999)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (366:366:366) (447:447:447)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (2921:2921:2921) (2960:2960:2960)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (4667:4667:4667) (4459:4459:4459)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2254:2254:2254) (2277:2277:2277)) + (PORT datab (332:332:332) (408:408:408)) + (PORT datac (3743:3743:3743) (3918:3918:3918)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2220:2220:2220) (2115:2115:2115)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (456:456:456)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (450:450:450)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (889:889:889)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (369:369:369) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (402:402:402) (492:492:492)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (350:350:350) (435:435:435)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~1) + (DELAY + (ABSOLUTE + (PORT datab (848:848:848) (777:777:777)) + (PORT datac (240:240:240) (266:266:266)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~0) + (DELAY + (ABSOLUTE + (PORT datab (789:789:789) (706:706:706)) + (PORT datac (265:265:265) (291:291:291)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (668:668:668)) + (PORT datab (390:390:390) (477:477:477)) + (PORT datac (853:853:853) (839:839:839)) + (PORT datad (328:328:328) (405:405:405)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (461:461:461)) + (PORT datab (368:368:368) (451:451:451)) + (PORT datac (327:327:327) (412:412:412)) + (PORT datad (329:329:329) (405:405:405)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (876:876:876)) + (PORT datab (741:741:741) (680:680:680)) + (PORT datac (724:724:724) (663:663:663)) + (PORT datad (917:917:917) (899:899:899)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~2) + (DELAY + (ABSOLUTE + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (806:806:806) (740:740:740)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT datab (396:396:396) (485:485:485)) + (PORT datad (342:342:342) (425:425:425)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (841:841:841)) + (PORT datab (933:933:933) (885:885:885)) + (PORT datac (767:767:767) (704:704:704)) + (PORT datad (328:328:328) (401:401:401)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (802:802:802)) + (PORT datab (862:862:862) (841:841:841)) + (PORT datad (313:313:313) (352:352:352)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (832:832:832)) + (PORT datab (857:857:857) (834:834:834)) + (PORT datad (317:317:317) (358:358:358)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1019:1019:1019)) + (PORT datab (856:856:856) (834:834:834)) + (PORT datad (318:318:318) (359:359:359)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1021:1021:1021) (997:997:997)) + (PORT datab (366:366:366) (449:449:449)) + (PORT datac (326:326:326) (408:408:408)) + (PORT datad (327:327:327) (401:401:401)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1079:1079:1079)) + (PORT datab (860:860:860) (838:838:838)) + (PORT datad (315:315:315) (355:355:355)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (351:351:351)) + (PORT datab (367:367:367) (450:450:450)) + (PORT datac (450:450:450) (427:427:427)) + (PORT datad (337:337:337) (417:417:417)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (877:877:877)) + (PORT datab (856:856:856) (834:834:834)) + (PORT datad (318:318:318) (358:358:358)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (450:450:450)) + (PORT datac (327:327:327) (409:409:409)) + (PORT datad (329:329:329) (402:402:402)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (829:829:829)) + (PORT datab (860:860:860) (839:839:839)) + (PORT datad (315:315:315) (354:354:354)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (569:569:569) (597:597:597)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (846:846:846)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datad (1206:1206:1206) (1115:1115:1115)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datad (333:333:333) (411:411:411)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (846:846:846)) + (PORT datab (280:280:280) (306:306:306)) + (PORT datad (1207:1207:1207) (1116:1116:1116)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (1265:1265:1265) (1163:1163:1163)) + (PORT datad (838:838:838) (794:794:794)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (443:443:443)) + (PORT datab (359:359:359) (435:435:435)) + (PORT datac (872:872:872) (866:866:866)) + (PORT datad (893:893:893) (890:890:890)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (326:326:326)) + (PORT datab (377:377:377) (459:459:459)) + (PORT datac (959:959:959) (948:948:948)) + (PORT datad (261:261:261) (296:296:296)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (449:449:449)) + (PORT datad (336:336:336) (416:416:416)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (961:961:961)) + (PORT datab (371:371:371) (451:451:451)) + (PORT datac (528:528:528) (560:560:560)) + (PORT datad (517:517:517) (552:552:552)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (323:323:323)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (698:698:698) (629:629:629)) + (PORT datad (265:265:265) (300:300:300)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT datab (930:930:930) (883:883:883)) + (PORT datac (848:848:848) (826:826:826)) + (PORT datad (326:326:326) (400:400:400)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb_valid\~0) + (DELAY + (ABSOLUTE + (PORT dataa (735:735:735) (684:684:684)) + (PORT datab (974:974:974) (944:944:944)) + (PORT datac (765:765:765) (703:703:703)) + (PORT datad (254:254:254) (280:280:280)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (455:455:455) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (628:628:628)) + (PORT datab (837:837:837) (806:806:806)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (628:628:628)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (597:597:597)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~7) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (607:607:607)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (839:839:839)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT datab (620:620:620) (627:627:627)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (837:837:837)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~0) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (383:383:383)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (650:650:650)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (628:628:628)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (801:801:801)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (273:273:273) (303:303:303)) + (PORT datad (274:274:274) (299:299:299)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (306:306:306) (351:351:351)) + (PORT datac (955:955:955) (943:943:943)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (710:710:710)) + (PORT datab (976:976:976) (946:946:946)) + (PORT datac (764:764:764) (701:701:701)) + (PORT datad (257:257:257) (283:283:283)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (684:684:684)) + (PORT datab (976:976:976) (946:946:946)) + (PORT datac (723:723:723) (662:662:662)) + (PORT datad (256:256:256) (281:281:281)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~4) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (812:812:812)) + (PORT datab (918:918:918) (854:854:854)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~4) + (DELAY + (ABSOLUTE + (PORT datab (1232:1232:1232) (1148:1148:1148)) + (PORT datad (847:847:847) (804:804:804)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~9) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (888:888:888) (823:823:823)) + (PORT datac (934:934:934) (907:907:907)) + (PORT datad (279:279:279) (305:305:305)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (855:855:855)) + (PORT datab (966:966:966) (898:898:898)) + (PORT datac (934:934:934) (907:907:907)) + (PORT datad (1188:1188:1188) (1104:1104:1104)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~6) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (351:351:351)) + (PORT datab (320:320:320) (350:350:350)) + (PORT datac (935:935:935) (908:908:908)) + (PORT datad (487:487:487) (468:468:468)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT datac (936:936:936) (910:910:910)) + (PORT datad (846:846:846) (803:803:803)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~11) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (824:824:824)) + (PORT datab (338:338:338) (384:384:384)) + (PORT datac (795:795:795) (753:753:753)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (353:353:353)) + (PORT datab (304:304:304) (329:329:329)) + (PORT datac (243:243:243) (274:274:274)) + (PORT datad (802:802:802) (754:754:754)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~13) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (537:537:537)) + (PORT datab (285:285:285) (315:315:315)) + (PORT datac (288:288:288) (315:315:315)) + (PORT datad (245:245:245) (270:270:270)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (815:815:815)) + (PORT datab (327:327:327) (381:381:381)) + (PORT datac (852:852:852) (839:839:839)) + (PORT datad (863:863:863) (814:814:814)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (856:856:856)) + (PORT datab (988:988:988) (944:944:944)) + (PORT datac (1120:1120:1120) (1040:1040:1040)) + (PORT datad (1190:1190:1190) (1106:1106:1106)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~16) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (326:326:326)) + (PORT datab (322:322:322) (356:356:356)) + (PORT datac (245:245:245) (278:278:278)) + (PORT datad (501:501:501) (465:465:465)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (810:810:810)) + (PORT datab (917:917:917) (852:852:852)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (912:912:912) (892:892:892)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~25) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (510:510:510)) + (PORT datab (511:511:511) (499:499:499)) + (PORT datac (263:263:263) (289:289:289)) + (PORT datad (817:817:817) (766:766:766)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (810:810:810)) + (PORT datab (916:916:916) (852:852:852)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (295:295:295) (365:365:365)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~18) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (824:824:824)) + (PORT datab (336:336:336) (382:382:382)) + (PORT datac (790:790:790) (746:746:746)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~14) + (DELAY + (ABSOLUTE + (PORT datab (314:314:314) (342:342:342)) + (PORT datac (796:796:796) (754:754:754)) + (PORT datad (299:299:299) (343:343:343)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~26) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (794:794:794)) + (PORT datab (275:275:275) (299:299:299)) + (PORT datac (270:270:270) (300:300:300)) + (PORT datad (267:267:267) (285:285:285)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~19) + (DELAY + (ABSOLUTE + (PORT datab (930:930:930) (864:864:864)) + (PORT datad (500:500:500) (460:460:460)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (812:812:812)) + (PORT datab (919:919:919) (856:856:856)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (829:829:829) (827:827:827)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (519:519:519)) + (PORT datab (984:984:984) (924:924:924)) + (PORT datad (1189:1189:1189) (1104:1104:1104)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~20) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (843:843:843)) + (PORT datac (849:849:849) (795:795:795)) + (PORT datad (908:908:908) (849:849:849)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~21) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (524:524:524)) + (PORT datab (928:928:928) (861:861:861)) + (PORT datac (475:475:475) (447:447:447)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (815:815:815)) + (PORT datab (924:924:924) (861:861:861)) + (PORT datac (283:283:283) (342:342:342)) + (PORT datad (931:931:931) (915:915:915)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~22) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (353:353:353)) + (PORT datab (886:886:886) (822:822:822)) + (PORT datac (936:936:936) (910:910:910)) + (PORT datad (282:282:282) (309:309:309)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~23) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (352:352:352)) + (PORT datab (283:283:283) (311:311:311)) + (PORT datac (455:455:455) (430:430:430)) + (PORT datad (285:285:285) (317:317:317)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[11\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (811:811:811)) + (PORT datab (918:918:918) (911:911:911)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (857:857:857) (807:807:807)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~24) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (328:328:328)) + (PORT datab (325:325:325) (360:360:360)) + (PORT datac (455:455:455) (430:430:430)) + (PORT datad (276:276:276) (301:301:301)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[12\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (814:814:814)) + (PORT datab (844:844:844) (810:810:810)) + (PORT datac (283:283:283) (342:342:342)) + (PORT datad (862:862:862) (812:812:812)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) +) diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_min_1200mv_0c_fast.vo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_min_1200mv_0c_fast.vo new file mode 100644 index 0000000..3bcdef2 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_min_1200mv_0c_fast.vo @@ -0,0 +1,2833 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version" + +// DATE "06/02/2023 04:42:20" + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module vga_colorbar ( + sys_clk, + sys_rst_n, + hsync, + vsync, + rgb); +input sys_clk; +input sys_rst_n; +output hsync; +output vsync; +output [15:0] rgb; + +// Design Ports Information +// hsync => Location: PIN_AA18, I/O Standard: 2.5 V, Current Strength: Default +// vsync => Location: PIN_AB17, I/O Standard: 2.5 V, Current Strength: Default +// rgb[0] => Location: PIN_AB18, I/O Standard: 2.5 V, Current Strength: Default +// rgb[1] => Location: PIN_AA19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[2] => Location: PIN_AB19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[3] => Location: PIN_Y21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[4] => Location: PIN_W19, I/O Standard: 2.5 V, Current Strength: Default +// rgb[5] => Location: PIN_W20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[6] => Location: PIN_U21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[7] => Location: PIN_U22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[8] => Location: PIN_N20, I/O Standard: 2.5 V, Current Strength: Default +// rgb[9] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[10] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[11] => Location: PIN_M22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[12] => Location: PIN_L21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[13] => Location: PIN_L22, I/O Standard: 2.5 V, Current Strength: Default +// rgb[14] => Location: PIN_K21, I/O Standard: 2.5 V, Current Strength: Default +// rgb[15] => Location: PIN_J21, I/O Standard: 2.5 V, Current Strength: Default +// sys_rst_n => Location: PIN_U20, I/O Standard: 2.5 V, Current Strength: Default +// sys_clk => Location: PIN_T22, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +// synopsys translate_off +initial $sdf_annotate("vga_colorbar_min_1200mv_0c_v_fast.sdo"); +// synopsys translate_on + +wire \vga_ctrl_inst|Add0~4_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ; +wire \vga_ctrl_inst|Add1~0_combout ; +wire \vga_ctrl_inst|Add1~2_combout ; +wire \vga_ctrl_inst|Add1~4_combout ; +wire \vga_ctrl_inst|Add1~6_combout ; +wire \vga_ctrl_inst|Add1~8_combout ; +wire \vga_ctrl_inst|Add1~10_combout ; +wire \vga_ctrl_inst|Add1~12_combout ; +wire \vga_ctrl_inst|Add1~16_combout ; +wire \vga_ctrl_inst|Equal0~0_combout ; +wire \vga_ctrl_inst|cnt_v[8]~3_combout ; +wire \vga_pic_inst|pix_data[4]~5_combout ; +wire \vga_pic_inst|pix_data~8_combout ; +wire \vga_pic_inst|pix_data~15_combout ; +wire \vga_pic_inst|pix_data~17_combout ; +wire \sys_clk~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~0_combout ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ; +wire \sys_rst_n~input_o ; +wire \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ; +wire \rst_n~0_combout ; +wire \rst_n~0clkctrl_outclk ; +wire \vga_ctrl_inst|Add0~1 ; +wire \vga_ctrl_inst|Add0~3 ; +wire \vga_ctrl_inst|Add0~5 ; +wire \vga_ctrl_inst|Add0~6_combout ; +wire \vga_ctrl_inst|Add0~7 ; +wire \vga_ctrl_inst|Add0~8_combout ; +wire \vga_ctrl_inst|Add0~9 ; +wire \vga_ctrl_inst|Add0~11 ; +wire \vga_ctrl_inst|Add0~12_combout ; +wire \vga_ctrl_inst|Add0~13 ; +wire \vga_ctrl_inst|Add0~14_combout ; +wire \vga_ctrl_inst|Add0~15 ; +wire \vga_ctrl_inst|Add0~16_combout ; +wire \vga_ctrl_inst|Add0~17 ; +wire \vga_ctrl_inst|Add0~18_combout ; +wire \vga_ctrl_inst|cnt_h~1_combout ; +wire \vga_ctrl_inst|Add0~10_combout ; +wire \vga_ctrl_inst|cnt_h~0_combout ; +wire \vga_ctrl_inst|Equal0~2_combout ; +wire \vga_ctrl_inst|Add0~2_combout ; +wire \vga_ctrl_inst|Equal0~1_combout ; +wire \vga_ctrl_inst|Equal0~3_combout ; +wire \vga_ctrl_inst|cnt_h~2_combout ; +wire \vga_ctrl_inst|LessThan2~0_combout ; +wire \vga_ctrl_inst|LessThan0~0_combout ; +wire \vga_ctrl_inst|cnt_v[0]~9_combout ; +wire \vga_ctrl_inst|cnt_v[2]~8_combout ; +wire \vga_ctrl_inst|cnt_v[4]~6_combout ; +wire \vga_ctrl_inst|always1~1_combout ; +wire \vga_ctrl_inst|cnt_v[1]~0_combout ; +wire \vga_ctrl_inst|always1~2_combout ; +wire \vga_ctrl_inst|cnt_v[3]~7_combout ; +wire \vga_ctrl_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|cnt_v[5]~2_combout ; +wire \vga_ctrl_inst|Add1~1 ; +wire \vga_ctrl_inst|Add1~3 ; +wire \vga_ctrl_inst|Add1~5 ; +wire \vga_ctrl_inst|Add1~7 ; +wire \vga_ctrl_inst|Add1~9 ; +wire \vga_ctrl_inst|Add1~11 ; +wire \vga_ctrl_inst|Add1~13 ; +wire \vga_ctrl_inst|Add1~14_combout ; +wire \vga_ctrl_inst|cnt_v[7]~4_combout ; +wire \vga_ctrl_inst|Add1~15 ; +wire \vga_ctrl_inst|Add1~17 ; +wire \vga_ctrl_inst|Add1~18_combout ; +wire \vga_ctrl_inst|cnt_v[9]~1_combout ; +wire \vga_ctrl_inst|cnt_v[6]~5_combout ; +wire \vga_ctrl_inst|always1~0_combout ; +wire \vga_ctrl_inst|LessThan1~0_combout ; +wire \vga_ctrl_inst|LessThan6~1_combout ; +wire \vga_ctrl_inst|pix_data_req~1_combout ; +wire \vga_ctrl_inst|pix_data_req~2_combout ; +wire \vga_ctrl_inst|LessThan2~1_combout ; +wire \vga_ctrl_inst|rgb_valid~0_combout ; +wire \vga_ctrl_inst|Add2~1_cout ; +wire \vga_ctrl_inst|Add2~3_cout ; +wire \vga_ctrl_inst|Add2~5_cout ; +wire \vga_ctrl_inst|Add2~7_cout ; +wire \vga_ctrl_inst|Add2~9_cout ; +wire \vga_ctrl_inst|Add2~11 ; +wire \vga_ctrl_inst|Add2~12_combout ; +wire \vga_ctrl_inst|Add2~10_combout ; +wire \vga_pic_inst|LessThan14~0_combout ; +wire \vga_ctrl_inst|Add2~13 ; +wire \vga_ctrl_inst|Add2~15 ; +wire \vga_ctrl_inst|Add2~16_combout ; +wire \vga_ctrl_inst|Add2~14_combout ; +wire \vga_pic_inst|LessThan6~0_combout ; +wire \vga_ctrl_inst|pix_data_req~0_combout ; +wire \vga_ctrl_inst|LessThan4~0_combout ; +wire \vga_ctrl_inst|pix_data_req~3_combout ; +wire \vga_ctrl_inst|pix_data_req~4_combout ; +wire \vga_pic_inst|pix_data~4_combout ; +wire \vga_pic_inst|pix_data~9_combout ; +wire \vga_pic_inst|LessThan17~0_combout ; +wire \vga_pic_inst|pix_data~6_combout ; +wire \vga_pic_inst|pix_data[4]~10_combout ; +wire \vga_pic_inst|pix_data~11_combout ; +wire \vga_pic_inst|pix_data~12_combout ; +wire \vga_pic_inst|pix_data~13_combout ; +wire \vga_ctrl_inst|rgb[0]~0_combout ; +wire \vga_pic_inst|pix_data[4]~7_combout ; +wire \vga_pic_inst|pix_data~16_combout ; +wire \vga_ctrl_inst|rgb[1]~1_combout ; +wire \vga_pic_inst|pix_data~25_combout ; +wire \vga_ctrl_inst|rgb[5]~2_combout ; +wire \vga_pic_inst|pix_data~18_combout ; +wire \vga_pic_inst|pix_data~14_combout ; +wire \vga_pic_inst|pix_data~26_combout ; +wire \vga_pic_inst|pix_data~19_combout ; +wire \vga_ctrl_inst|rgb[7]~3_combout ; +wire \vga_pic_inst|LessThan2~2_combout ; +wire \vga_pic_inst|pix_data~20_combout ; +wire \vga_pic_inst|pix_data~21_combout ; +wire \vga_ctrl_inst|rgb[10]~4_combout ; +wire \vga_pic_inst|pix_data~22_combout ; +wire \vga_pic_inst|pix_data~23_combout ; +wire \vga_ctrl_inst|rgb[11]~5_combout ; +wire \vga_pic_inst|pix_data~24_combout ; +wire \vga_ctrl_inst|rgb[12]~6_combout ; +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk ; +wire [9:0] \vga_ctrl_inst|cnt_v ; +wire [9:0] \vga_ctrl_inst|cnt_h ; +wire [15:0] \vga_pic_inst|pix_data ; + +wire [4:0] \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ; + +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [0]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [1] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [1]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [2] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [2]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [3] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [3]; +assign \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [4] = \clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus [4]; + +// Location: LCCOMB_X35_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~4 ( +// Equation(s): +// \vga_ctrl_inst|Add0~4_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|Add0~3 $ (GND))) # (!\vga_ctrl_inst|cnt_h [2] & (!\vga_ctrl_inst|Add0~3 & VCC)) +// \vga_ctrl_inst|Add0~5 = CARRY((\vga_ctrl_inst|cnt_h [2] & !\vga_ctrl_inst|Add0~3 )) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~3 ), + .combout(\vga_ctrl_inst|Add0~4_combout ), + .cout(\vga_ctrl_inst|Add0~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add0~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: PLL_2 +cycloneive_pll \clk_gen_inst|altpll_component|auto_generated|pll1 ( + .areset(!\sys_rst_n~input_o ), + .pfdena(vcc), + .fbin(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .phaseupdown(gnd), + .phasestep(gnd), + .scandata(gnd), + .scanclk(gnd), + .scanclkena(vcc), + .configupdate(gnd), + .clkswitch(gnd), + .inclk({gnd,\sys_clk~input_o }), + .phasecounterselect(3'b000), + .phasedone(), + .scandataout(), + .scandone(), + .activeclock(), + .locked(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .vcooverrange(), + .vcounderrange(), + .fbout(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_fbout ), + .clk(\clk_gen_inst|altpll_component|auto_generated|pll1_CLK_bus ), + .clkbad()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .auto_settings = "false"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .bandwidth_type = "medium"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_high = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_low = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_mode = "even"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c0_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c1_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c2_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c3_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_high = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_initial = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_low = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_mode = "bypass"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .c4_use_casc_in = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .charge_pump_current_bits = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_counter = "c0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_divide_by = 2; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_multiply_by = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk0_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk1_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk2_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk3_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_counter = "unused"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_duty_cycle = 50; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .clk4_phase_shift = "0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .compensate_clock = "clock0"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk0_input_frequency = 20000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .inclk1_input_frequency = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_c_bits = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .loop_filter_r_bits = 27; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m = 12; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_initial = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .m_ph = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .n = 1; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .operation_mode = "normal"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_max = 200000; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pfd_min = 3076; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .pll_compensation_delay = 3334; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .self_reset_on_loss_lock = "off"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .simulation_type = "timing"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .switch_over_type = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_center = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_divide_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_frequency_control = "auto"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_max = 3333; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_min = 1538; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_multiply_by = 0; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_phase_shift_step = 208; +defparam \clk_gen_inst|altpll_component|auto_generated|pll1 .vco_post_scale = 2; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~0 ( +// Equation(s): +// \vga_ctrl_inst|Add1~0_combout = \vga_ctrl_inst|cnt_v [0] $ (VCC) +// \vga_ctrl_inst|Add1~1 = CARRY(\vga_ctrl_inst|cnt_v [0]) + + .dataa(\vga_ctrl_inst|cnt_v [0]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add1~0_combout ), + .cout(\vga_ctrl_inst|Add1~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~0 .lut_mask = 16'h55AA; +defparam \vga_ctrl_inst|Add1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~2 ( +// Equation(s): +// \vga_ctrl_inst|Add1~2_combout = (\vga_ctrl_inst|cnt_v [1] & (!\vga_ctrl_inst|Add1~1 )) # (!\vga_ctrl_inst|cnt_v [1] & ((\vga_ctrl_inst|Add1~1 ) # (GND))) +// \vga_ctrl_inst|Add1~3 = CARRY((!\vga_ctrl_inst|Add1~1 ) # (!\vga_ctrl_inst|cnt_v [1])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~1 ), + .combout(\vga_ctrl_inst|Add1~2_combout ), + .cout(\vga_ctrl_inst|Add1~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~2 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~4 ( +// Equation(s): +// \vga_ctrl_inst|Add1~4_combout = (\vga_ctrl_inst|cnt_v [2] & (\vga_ctrl_inst|Add1~3 $ (GND))) # (!\vga_ctrl_inst|cnt_v [2] & (!\vga_ctrl_inst|Add1~3 & VCC)) +// \vga_ctrl_inst|Add1~5 = CARRY((\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|Add1~3 )) + + .dataa(\vga_ctrl_inst|cnt_v [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~3 ), + .combout(\vga_ctrl_inst|Add1~4_combout ), + .cout(\vga_ctrl_inst|Add1~5 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~4 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~4 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~6 ( +// Equation(s): +// \vga_ctrl_inst|Add1~6_combout = (\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|Add1~5 )) # (!\vga_ctrl_inst|cnt_v [3] & ((\vga_ctrl_inst|Add1~5 ) # (GND))) +// \vga_ctrl_inst|Add1~7 = CARRY((!\vga_ctrl_inst|Add1~5 ) # (!\vga_ctrl_inst|cnt_v [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~5 ), + .combout(\vga_ctrl_inst|Add1~6_combout ), + .cout(\vga_ctrl_inst|Add1~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~8 ( +// Equation(s): +// \vga_ctrl_inst|Add1~8_combout = (\vga_ctrl_inst|cnt_v [4] & (\vga_ctrl_inst|Add1~7 $ (GND))) # (!\vga_ctrl_inst|cnt_v [4] & (!\vga_ctrl_inst|Add1~7 & VCC)) +// \vga_ctrl_inst|Add1~9 = CARRY((\vga_ctrl_inst|cnt_v [4] & !\vga_ctrl_inst|Add1~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~7 ), + .combout(\vga_ctrl_inst|Add1~8_combout ), + .cout(\vga_ctrl_inst|Add1~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add1~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~10 ( +// Equation(s): +// \vga_ctrl_inst|Add1~10_combout = (\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|Add1~9 )) # (!\vga_ctrl_inst|cnt_v [5] & ((\vga_ctrl_inst|Add1~9 ) # (GND))) +// \vga_ctrl_inst|Add1~11 = CARRY((!\vga_ctrl_inst|Add1~9 ) # (!\vga_ctrl_inst|cnt_v [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~9 ), + .combout(\vga_ctrl_inst|Add1~10_combout ), + .cout(\vga_ctrl_inst|Add1~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~10 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~12 ( +// Equation(s): +// \vga_ctrl_inst|Add1~12_combout = (\vga_ctrl_inst|cnt_v [6] & (\vga_ctrl_inst|Add1~11 $ (GND))) # (!\vga_ctrl_inst|cnt_v [6] & (!\vga_ctrl_inst|Add1~11 & VCC)) +// \vga_ctrl_inst|Add1~13 = CARRY((\vga_ctrl_inst|cnt_v [6] & !\vga_ctrl_inst|Add1~11 )) + + .dataa(\vga_ctrl_inst|cnt_v [6]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~11 ), + .combout(\vga_ctrl_inst|Add1~12_combout ), + .cout(\vga_ctrl_inst|Add1~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~16 ( +// Equation(s): +// \vga_ctrl_inst|Add1~16_combout = (\vga_ctrl_inst|cnt_v [8] & (\vga_ctrl_inst|Add1~15 $ (GND))) # (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|Add1~15 & VCC)) +// \vga_ctrl_inst|Add1~17 = CARRY((\vga_ctrl_inst|cnt_v [8] & !\vga_ctrl_inst|Add1~15 )) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~15 ), + .combout(\vga_ctrl_inst|Add1~16_combout ), + .cout(\vga_ctrl_inst|Add1~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~16 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add1~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X33_Y23_N13 +dffeas \vga_ctrl_inst|cnt_v[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~0 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~0_combout = (\vga_ctrl_inst|cnt_h [8] & \vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~0 .lut_mask = 16'hCC00; +defparam \vga_ctrl_inst|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N13 +dffeas \vga_ctrl_inst|cnt_h[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[8]~3 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[8]~3_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~16_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [8])))) + + .dataa(\vga_ctrl_inst|Add1~16_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [8]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[8]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[8]~3 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[8]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~5 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~5_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~16_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~16_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~5 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data[4]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~8 ( +// Equation(s): +// \vga_pic_inst|pix_data~8_combout = (\vga_ctrl_inst|Add2~16_combout ) # (((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) # (!\vga_ctrl_inst|Add2~10_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~8 .lut_mask = 16'hFBFF; +defparam \vga_pic_inst|pix_data~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N10 +cycloneive_lcell_comb \vga_pic_inst|pix_data~15 ( +// Equation(s): +// \vga_pic_inst|pix_data~15_combout = (\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|pix_data~11_combout & ((!\vga_pic_inst|pix_data[4]~10_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_pic_inst|pix_data~11_combout ), + .datab(\vga_pic_inst|pix_data~14_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data[4]~5_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~15_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~15 .lut_mask = 16'h0ACC; +defparam \vga_pic_inst|pix_data~15 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~17 ( +// Equation(s): +// \vga_pic_inst|pix_data~17_combout = (\vga_ctrl_inst|Add2~12_combout & (!\vga_ctrl_inst|Add2~14_combout )) # (!\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|Add2~14_combout & !\vga_ctrl_inst|Add2~10_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~17_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~17 .lut_mask = 16'h0C3C; +defparam \vga_pic_inst|pix_data~17 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y15_N22 +cycloneive_io_ibuf \sys_clk~input ( + .i(sys_clk), + .ibar(gnd), + .o(\sys_clk~input_o )); +// synopsys translate_off +defparam \sys_clk~input .bus_hold = "false"; +defparam \sys_clk~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: CLKCTRL_G8 +cycloneive_clkctrl \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk [0]}), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk )); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .clock_type = "global clock"; +defparam \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N30 +cycloneive_io_obuf \hsync~output ( + .i(!\vga_ctrl_inst|LessThan0~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(hsync), + .obar()); +// synopsys translate_off +defparam \hsync~output .bus_hold = "false"; +defparam \hsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X28_Y0_N2 +cycloneive_io_obuf \vsync~output ( + .i(!\vga_ctrl_inst|LessThan1~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(vsync), + .obar()); +// synopsys translate_off +defparam \vsync~output .bus_hold = "false"; +defparam \vsync~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X32_Y0_N2 +cycloneive_io_obuf \rgb[0]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[0]), + .obar()); +// synopsys translate_off +defparam \rgb[0]~output .bus_hold = "false"; +defparam \rgb[0]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N23 +cycloneive_io_obuf \rgb[1]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[1]), + .obar()); +// synopsys translate_off +defparam \rgb[1]~output .bus_hold = "false"; +defparam \rgb[1]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X35_Y0_N16 +cycloneive_io_obuf \rgb[2]~output ( + .i(\vga_ctrl_inst|rgb[0]~0_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[2]), + .obar()); +// synopsys translate_off +defparam \rgb[2]~output .bus_hold = "false"; +defparam \rgb[2]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y4_N9 +cycloneive_io_obuf \rgb[3]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[3]), + .obar()); +// synopsys translate_off +defparam \rgb[3]~output .bus_hold = "false"; +defparam \rgb[3]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N9 +cycloneive_io_obuf \rgb[4]~output ( + .i(\vga_ctrl_inst|rgb[1]~1_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[4]), + .obar()); +// synopsys translate_off +defparam \rgb[4]~output .bus_hold = "false"; +defparam \rgb[4]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y3_N16 +cycloneive_io_obuf \rgb[5]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[5]), + .obar()); +// synopsys translate_off +defparam \rgb[5]~output .bus_hold = "false"; +defparam \rgb[5]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N2 +cycloneive_io_obuf \rgb[6]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[6]), + .obar()); +// synopsys translate_off +defparam \rgb[6]~output .bus_hold = "false"; +defparam \rgb[6]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y8_N9 +cycloneive_io_obuf \rgb[7]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[7]), + .obar()); +// synopsys translate_off +defparam \rgb[7]~output .bus_hold = "false"; +defparam \rgb[7]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y12_N16 +cycloneive_io_obuf \rgb[8]~output ( + .i(\vga_ctrl_inst|rgb[5]~2_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[8]), + .obar()); +// synopsys translate_off +defparam \rgb[8]~output .bus_hold = "false"; +defparam \rgb[8]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N9 +cycloneive_io_obuf \rgb[9]~output ( + .i(\vga_ctrl_inst|rgb[7]~3_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[9]), + .obar()); +// synopsys translate_off +defparam \rgb[9]~output .bus_hold = "false"; +defparam \rgb[9]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y14_N23 +cycloneive_io_obuf \rgb[10]~output ( + .i(\vga_ctrl_inst|rgb[10]~4_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[10]), + .obar()); +// synopsys translate_off +defparam \rgb[10]~output .bus_hold = "false"; +defparam \rgb[10]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y13_N2 +cycloneive_io_obuf \rgb[11]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[11]), + .obar()); +// synopsys translate_off +defparam \rgb[11]~output .bus_hold = "false"; +defparam \rgb[11]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N16 +cycloneive_io_obuf \rgb[12]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[12]), + .obar()); +// synopsys translate_off +defparam \rgb[12]~output .bus_hold = "false"; +defparam \rgb[12]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y18_N23 +cycloneive_io_obuf \rgb[13]~output ( + .i(\vga_ctrl_inst|rgb[11]~5_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[13]), + .obar()); +// synopsys translate_off +defparam \rgb[13]~output .bus_hold = "false"; +defparam \rgb[13]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y19_N9 +cycloneive_io_obuf \rgb[14]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[14]), + .obar()); +// synopsys translate_off +defparam \rgb[14]~output .bus_hold = "false"; +defparam \rgb[14]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X41_Y20_N23 +cycloneive_io_obuf \rgb[15]~output ( + .i(\vga_ctrl_inst|rgb[12]~6_combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(rgb[15]), + .obar()); +// synopsys translate_off +defparam \rgb[15]~output .bus_hold = "false"; +defparam \rgb[15]~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~0 ( +// Equation(s): +// \vga_ctrl_inst|Add0~0_combout = \vga_ctrl_inst|cnt_h [0] $ (VCC) +// \vga_ctrl_inst|Add0~1 = CARRY(\vga_ctrl_inst|cnt_h [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(\vga_ctrl_inst|Add0~0_combout ), + .cout(\vga_ctrl_inst|Add0~1 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~0 .lut_mask = 16'h33CC; +defparam \vga_ctrl_inst|Add0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N0 +cycloneive_lcell_comb \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder ( +// Equation(s): +// \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout = VCC + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(gnd), + .combout(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: IOIBUF_X41_Y4_N1 +cycloneive_io_ibuf \sys_rst_n~input ( + .i(sys_rst_n), + .ibar(gnd), + .o(\sys_rst_n~input_o )); +// synopsys translate_off +defparam \sys_rst_n~input .bus_hold = "false"; +defparam \sys_rst_n~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: FF_X35_Y3_N1 +dffeas \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .d(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder_combout ), + .asdata(vcc), + .clrn(\sys_rst_n~input_o ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .prn(vcc)); +// synopsys translate_off +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .is_wysiwyg = "true"; +defparam \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y3_N10 +cycloneive_lcell_comb \rst_n~0 ( +// Equation(s): +// \rst_n~0_combout = ((!\sys_rst_n~input_o ) # (!\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q )) # (!\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ) + + .dataa(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_locked ), + .datab(\clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~q ), + .datac(\sys_rst_n~input_o ), + .datad(gnd), + .cin(gnd), + .combout(\rst_n~0_combout ), + .cout()); +// synopsys translate_off +defparam \rst_n~0 .lut_mask = 16'h7F7F; +defparam \rst_n~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: CLKCTRL_G16 +cycloneive_clkctrl \rst_n~0clkctrl ( + .ena(vcc), + .inclk({vcc,vcc,vcc,\rst_n~0_combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst_n~0clkctrl_outclk )); +// synopsys translate_off +defparam \rst_n~0clkctrl .clock_type = "global clock"; +defparam \rst_n~0clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: FF_X35_Y23_N9 +dffeas \vga_ctrl_inst|cnt_h[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~2 ( +// Equation(s): +// \vga_ctrl_inst|Add0~2_combout = (\vga_ctrl_inst|cnt_h [1] & (!\vga_ctrl_inst|Add0~1 )) # (!\vga_ctrl_inst|cnt_h [1] & ((\vga_ctrl_inst|Add0~1 ) # (GND))) +// \vga_ctrl_inst|Add0~3 = CARRY((!\vga_ctrl_inst|Add0~1 ) # (!\vga_ctrl_inst|cnt_h [1])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~1 ), + .combout(\vga_ctrl_inst|Add0~2_combout ), + .cout(\vga_ctrl_inst|Add0~3 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~2 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~2 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~6 ( +// Equation(s): +// \vga_ctrl_inst|Add0~6_combout = (\vga_ctrl_inst|cnt_h [3] & (!\vga_ctrl_inst|Add0~5 )) # (!\vga_ctrl_inst|cnt_h [3] & ((\vga_ctrl_inst|Add0~5 ) # (GND))) +// \vga_ctrl_inst|Add0~7 = CARRY((!\vga_ctrl_inst|Add0~5 ) # (!\vga_ctrl_inst|cnt_h [3])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~5 ), + .combout(\vga_ctrl_inst|Add0~6_combout ), + .cout(\vga_ctrl_inst|Add0~7 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~6 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add0~6 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N15 +dffeas \vga_ctrl_inst|cnt_h[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~8 ( +// Equation(s): +// \vga_ctrl_inst|Add0~8_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Add0~7 $ (GND))) # (!\vga_ctrl_inst|cnt_h [4] & (!\vga_ctrl_inst|Add0~7 & VCC)) +// \vga_ctrl_inst|Add0~9 = CARRY((\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add0~7 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [4]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~7 ), + .combout(\vga_ctrl_inst|Add0~8_combout ), + .cout(\vga_ctrl_inst|Add0~9 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~8 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~8 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N17 +dffeas \vga_ctrl_inst|cnt_h[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~10 ( +// Equation(s): +// \vga_ctrl_inst|Add0~10_combout = (\vga_ctrl_inst|cnt_h [5] & (!\vga_ctrl_inst|Add0~9 )) # (!\vga_ctrl_inst|cnt_h [5] & ((\vga_ctrl_inst|Add0~9 ) # (GND))) +// \vga_ctrl_inst|Add0~11 = CARRY((!\vga_ctrl_inst|Add0~9 ) # (!\vga_ctrl_inst|cnt_h [5])) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~9 ), + .combout(\vga_ctrl_inst|Add0~10_combout ), + .cout(\vga_ctrl_inst|Add0~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~10 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~12 ( +// Equation(s): +// \vga_ctrl_inst|Add0~12_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add0~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add0~11 & VCC)) +// \vga_ctrl_inst|Add0~13 = CARRY((\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add0~11 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~11 ), + .combout(\vga_ctrl_inst|Add0~12_combout ), + .cout(\vga_ctrl_inst|Add0~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~12 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N21 +dffeas \vga_ctrl_inst|cnt_h[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~12_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~14 ( +// Equation(s): +// \vga_ctrl_inst|Add0~14_combout = (\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add0~13 )) # (!\vga_ctrl_inst|cnt_h [7] & ((\vga_ctrl_inst|Add0~13 ) # (GND))) +// \vga_ctrl_inst|Add0~15 = CARRY((!\vga_ctrl_inst|Add0~13 ) # (!\vga_ctrl_inst|cnt_h [7])) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~13 ), + .combout(\vga_ctrl_inst|Add0~14_combout ), + .cout(\vga_ctrl_inst|Add0~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~14 .lut_mask = 16'h5A5F; +defparam \vga_ctrl_inst|Add0~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: FF_X35_Y23_N23 +dffeas \vga_ctrl_inst|cnt_h[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~14_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~16 ( +// Equation(s): +// \vga_ctrl_inst|Add0~16_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add0~15 $ (GND))) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add0~15 & VCC)) +// \vga_ctrl_inst|Add0~17 = CARRY((\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add0~15 )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add0~15 ), + .combout(\vga_ctrl_inst|Add0~16_combout ), + .cout(\vga_ctrl_inst|Add0~17 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~16 .lut_mask = 16'hC30C; +defparam \vga_ctrl_inst|Add0~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|Add0~18 ( +// Equation(s): +// \vga_ctrl_inst|Add0~18_combout = \vga_ctrl_inst|Add0~17 $ (\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(\vga_ctrl_inst|Add0~17 ), + .combout(\vga_ctrl_inst|Add0~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add0~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add0~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~1_combout = (!\vga_ctrl_inst|Equal0~3_combout & \vga_ctrl_inst|Add0~18_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|Add0~18_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~1 .lut_mask = 16'h3030; +defparam \vga_ctrl_inst|cnt_h~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N1 +dffeas \vga_ctrl_inst|cnt_h[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~0_combout = (\vga_ctrl_inst|Add0~10_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~10_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~0 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N25 +dffeas \vga_ctrl_inst|cnt_h[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~2 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~2_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|cnt_h [9] & (!\vga_ctrl_inst|cnt_h [5] & !\vga_ctrl_inst|cnt_h [6]))) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(\vga_ctrl_inst|cnt_h [9]), + .datac(\vga_ctrl_inst|cnt_h [5]), + .datad(\vga_ctrl_inst|cnt_h [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~2 .lut_mask = 16'h0008; +defparam \vga_ctrl_inst|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N11 +dffeas \vga_ctrl_inst|cnt_h[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|Add0~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~1 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~1_combout = (\vga_ctrl_inst|cnt_h [2] & (\vga_ctrl_inst|cnt_h [3] & (\vga_ctrl_inst|cnt_h [0] & \vga_ctrl_inst|cnt_h [1]))) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(\vga_ctrl_inst|cnt_h [3]), + .datac(\vga_ctrl_inst|cnt_h [0]), + .datad(\vga_ctrl_inst|cnt_h [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~1 .lut_mask = 16'h8000; +defparam \vga_ctrl_inst|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Equal0~3 ( +// Equation(s): +// \vga_ctrl_inst|Equal0~3_combout = (\vga_ctrl_inst|cnt_h [4] & (\vga_ctrl_inst|Equal0~2_combout & (\vga_ctrl_inst|Equal0~1_combout & !\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(\vga_ctrl_inst|Equal0~2_combout ), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|cnt_h [7]), + .cin(gnd), + .combout(\vga_ctrl_inst|Equal0~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Equal0~3 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|Equal0~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_h~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_h~2_combout = (\vga_ctrl_inst|Add0~16_combout & !\vga_ctrl_inst|Equal0~3_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add0~16_combout ), + .datac(\vga_ctrl_inst|Equal0~3_combout ), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_h~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h~2 .lut_mask = 16'h0C0C; +defparam \vga_ctrl_inst|cnt_h~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X35_Y23_N3 +dffeas \vga_ctrl_inst|cnt_h[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_h~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_h [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_h[8] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_h[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X35_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~0_combout = (!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|cnt_h [9]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [8]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_h [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~0 .lut_mask = 16'h0033; +defparam \vga_ctrl_inst|LessThan2~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan0~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan0~0_combout = (\vga_ctrl_inst|cnt_h [7]) # (((\vga_ctrl_inst|cnt_h [6] & \vga_ctrl_inst|cnt_h [5])) # (!\vga_ctrl_inst|LessThan2~0_combout )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan0~0 .lut_mask = 16'hEFAF; +defparam \vga_ctrl_inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[0]~9 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[0]~9_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~0_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [0])))) + + .dataa(\vga_ctrl_inst|Add1~0_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [0]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0]~9 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[0]~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N29 +dffeas \vga_ctrl_inst|cnt_v[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[0]~9_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[0] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[2]~8 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[2]~8_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~4_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [2])))) + + .dataa(\vga_ctrl_inst|Add1~4_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2]~8 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[2]~8 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N5 +dffeas \vga_ctrl_inst|cnt_v[2] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[2]~8_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [2]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[2] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[2] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[4]~6 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[4]~6_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~8_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [4])))) + + .dataa(\vga_ctrl_inst|Add1~8_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [4]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4]~6 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[4]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N1 +dffeas \vga_ctrl_inst|cnt_v[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[4]~6_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[4] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|always1~1 ( +// Equation(s): +// \vga_ctrl_inst|always1~1_combout = (\vga_ctrl_inst|cnt_v [9] & (\vga_ctrl_inst|cnt_v [3] & (\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4]))) + + .dataa(\vga_ctrl_inst|cnt_v [9]), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~1 .lut_mask = 16'h0080; +defparam \vga_ctrl_inst|always1~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[1]~0 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[1]~0_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~2_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [1])))) + + .dataa(\vga_ctrl_inst|Add1~2_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [1]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1]~0 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N17 +dffeas \vga_ctrl_inst|cnt_v[1] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[1]~0_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [1]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[1] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[1] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|always1~2 ( +// Equation(s): +// \vga_ctrl_inst|always1~2_combout = (\vga_ctrl_inst|always1~0_combout & (!\vga_ctrl_inst|cnt_v [0] & (\vga_ctrl_inst|always1~1_combout & !\vga_ctrl_inst|cnt_v [1]))) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(\vga_ctrl_inst|always1~1_combout ), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~2 .lut_mask = 16'h0020; +defparam \vga_ctrl_inst|always1~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[3]~7 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[3]~7_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~6_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [3])))) + + .dataa(\vga_ctrl_inst|Add1~6_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [3]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3]~7 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[3]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N3 +dffeas \vga_ctrl_inst|cnt_v[3] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[3]~7_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [3]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[3] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[3] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~0_combout = (!\vga_ctrl_inst|cnt_v [3] & (!\vga_ctrl_inst|cnt_v [2] & !\vga_ctrl_inst|cnt_v [4])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [3]), + .datac(\vga_ctrl_inst|cnt_v [2]), + .datad(\vga_ctrl_inst|cnt_v [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~0 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[5]~2_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~10_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [5])))) + + .dataa(\vga_ctrl_inst|Add1~10_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [5]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5]~2 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y23_N19 +dffeas \vga_ctrl_inst|cnt_v[5] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[5]~2_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [5]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[5] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[5] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N24 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~14 ( +// Equation(s): +// \vga_ctrl_inst|Add1~14_combout = (\vga_ctrl_inst|cnt_v [7] & (!\vga_ctrl_inst|Add1~13 )) # (!\vga_ctrl_inst|cnt_v [7] & ((\vga_ctrl_inst|Add1~13 ) # (GND))) +// \vga_ctrl_inst|Add1~15 = CARRY((!\vga_ctrl_inst|Add1~13 ) # (!\vga_ctrl_inst|cnt_v [7])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [7]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add1~13 ), + .combout(\vga_ctrl_inst|Add1~14_combout ), + .cout(\vga_ctrl_inst|Add1~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~14 .lut_mask = 16'h3C3F; +defparam \vga_ctrl_inst|Add1~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N2 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[7]~4 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[7]~4_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~14_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [7])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~14_combout ), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7]~4 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[7]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N3 +dffeas \vga_ctrl_inst|cnt_v[7] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[7]~4_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [7]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[7] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[7] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N28 +cycloneive_lcell_comb \vga_ctrl_inst|Add1~18 ( +// Equation(s): +// \vga_ctrl_inst|Add1~18_combout = \vga_ctrl_inst|Add1~17 $ (\vga_ctrl_inst|cnt_v [9]) + + .dataa(gnd), + .datab(gnd), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [9]), + .cin(\vga_ctrl_inst|Add1~17 ), + .combout(\vga_ctrl_inst|Add1~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add1~18 .lut_mask = 16'h0FF0; +defparam \vga_ctrl_inst|Add1~18 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N0 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[9]~1 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[9]~1_combout = (\vga_ctrl_inst|Equal0~3_combout & (!\vga_ctrl_inst|always1~2_combout & (\vga_ctrl_inst|Add1~18_combout ))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [9])))) + + .dataa(\vga_ctrl_inst|always1~2_combout ), + .datab(\vga_ctrl_inst|Add1~18_combout ), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|Equal0~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9]~1 .lut_mask = 16'h44F0; +defparam \vga_ctrl_inst|cnt_v[9]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N1 +dffeas \vga_ctrl_inst|cnt_v[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[9]~1_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[9] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N4 +cycloneive_lcell_comb \vga_ctrl_inst|cnt_v[6]~5 ( +// Equation(s): +// \vga_ctrl_inst|cnt_v[6]~5_combout = (\vga_ctrl_inst|Equal0~3_combout & (\vga_ctrl_inst|Add1~12_combout & ((!\vga_ctrl_inst|always1~2_combout )))) # (!\vga_ctrl_inst|Equal0~3_combout & (((\vga_ctrl_inst|cnt_v [6])))) + + .dataa(\vga_ctrl_inst|Add1~12_combout ), + .datab(\vga_ctrl_inst|Equal0~3_combout ), + .datac(\vga_ctrl_inst|cnt_v [6]), + .datad(\vga_ctrl_inst|always1~2_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6]~5 .lut_mask = 16'h30B8; +defparam \vga_ctrl_inst|cnt_v[6]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X33_Y24_N5 +dffeas \vga_ctrl_inst|cnt_v[6] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_ctrl_inst|cnt_v[6]~5_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_ctrl_inst|cnt_v [6]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_ctrl_inst|cnt_v[6] .is_wysiwyg = "true"; +defparam \vga_ctrl_inst|cnt_v[6] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|always1~0 ( +// Equation(s): +// \vga_ctrl_inst|always1~0_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [5] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [5]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|always1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|always1~0 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|always1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan1~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan1~0_combout = ((\vga_ctrl_inst|cnt_v [1]) # ((\vga_ctrl_inst|cnt_v [9]) # (!\vga_ctrl_inst|always1~0_combout ))) # (!\vga_ctrl_inst|LessThan6~0_combout ) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|cnt_v [1]), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan1~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan1~0 .lut_mask = 16'hFDFF; +defparam \vga_ctrl_inst|LessThan1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan6~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan6~1_combout = (!\vga_ctrl_inst|cnt_v [1]) # (!\vga_ctrl_inst|cnt_v [0]) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_v [0]), + .datac(gnd), + .datad(\vga_ctrl_inst|cnt_v [1]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan6~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan6~1 .lut_mask = 16'h33FF; +defparam \vga_ctrl_inst|LessThan6~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y24_N30 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~1 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~1_combout = (!\vga_ctrl_inst|cnt_v [8] & (!\vga_ctrl_inst|cnt_v [9] & (!\vga_ctrl_inst|cnt_v [7] & !\vga_ctrl_inst|cnt_v [6]))) + + .dataa(\vga_ctrl_inst|cnt_v [8]), + .datab(\vga_ctrl_inst|cnt_v [9]), + .datac(\vga_ctrl_inst|cnt_v [7]), + .datad(\vga_ctrl_inst|cnt_v [6]), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~1 .lut_mask = 16'h0001; +defparam \vga_ctrl_inst|pix_data_req~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N24 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~2 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~2_combout = (\vga_ctrl_inst|LessThan6~0_combout & ((\vga_ctrl_inst|LessThan6~1_combout & (\vga_ctrl_inst|pix_data_req~1_combout )) # (!\vga_ctrl_inst|LessThan6~1_combout & ((\vga_ctrl_inst|always1~0_combout ))))) # +// (!\vga_ctrl_inst|LessThan6~0_combout & (((\vga_ctrl_inst|always1~0_combout )))) + + .dataa(\vga_ctrl_inst|LessThan6~0_combout ), + .datab(\vga_ctrl_inst|LessThan6~1_combout ), + .datac(\vga_ctrl_inst|pix_data_req~1_combout ), + .datad(\vga_ctrl_inst|always1~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~2 .lut_mask = 16'hF780; +defparam \vga_ctrl_inst|pix_data_req~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N28 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan2~1 ( +// Equation(s): +// \vga_ctrl_inst|LessThan2~1_combout = (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|cnt_h [5])) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(\vga_ctrl_inst|cnt_h [4]), + .datad(\vga_ctrl_inst|cnt_h [5]), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan2~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan2~1 .lut_mask = 16'h0003; +defparam \vga_ctrl_inst|LessThan2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|rgb_valid~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb_valid~0_combout = (\vga_ctrl_inst|Equal0~0_combout & (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|LessThan2~0_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout & (((\vga_ctrl_inst|cnt_h [7] & +// !\vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|LessThan2~0_combout ))) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb_valid~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb_valid~0 .lut_mask = 16'h0745; +defparam \vga_ctrl_inst|rgb_valid~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~1 ( +// Equation(s): +// \vga_ctrl_inst|Add2~1_cout = CARRY((\vga_ctrl_inst|cnt_h [1] & \vga_ctrl_inst|cnt_h [0])) + + .dataa(\vga_ctrl_inst|cnt_h [1]), + .datab(\vga_ctrl_inst|cnt_h [0]), + .datac(gnd), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\vga_ctrl_inst|Add2~1_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~1 .lut_mask = 16'h0088; +defparam \vga_ctrl_inst|Add2~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N8 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~3 ( +// Equation(s): +// \vga_ctrl_inst|Add2~3_cout = CARRY((!\vga_ctrl_inst|Add2~1_cout ) # (!\vga_ctrl_inst|cnt_h [2])) + + .dataa(\vga_ctrl_inst|cnt_h [2]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~1_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~3_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~3 .lut_mask = 16'h005F; +defparam \vga_ctrl_inst|Add2~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~5 ( +// Equation(s): +// \vga_ctrl_inst|Add2~5_cout = CARRY((\vga_ctrl_inst|cnt_h [3] & !\vga_ctrl_inst|Add2~3_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [3]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~3_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~5_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~5 .lut_mask = 16'h000A; +defparam \vga_ctrl_inst|Add2~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N12 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~7 ( +// Equation(s): +// \vga_ctrl_inst|Add2~7_cout = CARRY((!\vga_ctrl_inst|cnt_h [4] & !\vga_ctrl_inst|Add2~5_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [4]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~5_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~7_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~7 .lut_mask = 16'h0005; +defparam \vga_ctrl_inst|Add2~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N14 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~9 ( +// Equation(s): +// \vga_ctrl_inst|Add2~9_cout = CARRY((\vga_ctrl_inst|cnt_h [5]) # (!\vga_ctrl_inst|Add2~7_cout )) + + .dataa(\vga_ctrl_inst|cnt_h [5]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~7_cout ), + .combout(), + .cout(\vga_ctrl_inst|Add2~9_cout )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~9 .lut_mask = 16'h00AF; +defparam \vga_ctrl_inst|Add2~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~10 ( +// Equation(s): +// \vga_ctrl_inst|Add2~10_combout = (\vga_ctrl_inst|cnt_h [6] & (\vga_ctrl_inst|Add2~9_cout & VCC)) # (!\vga_ctrl_inst|cnt_h [6] & (!\vga_ctrl_inst|Add2~9_cout )) +// \vga_ctrl_inst|Add2~11 = CARRY((!\vga_ctrl_inst|cnt_h [6] & !\vga_ctrl_inst|Add2~9_cout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|cnt_h [6]), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~9_cout ), + .combout(\vga_ctrl_inst|Add2~10_combout ), + .cout(\vga_ctrl_inst|Add2~11 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~10 .lut_mask = 16'hC303; +defparam \vga_ctrl_inst|Add2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N18 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~12 ( +// Equation(s): +// \vga_ctrl_inst|Add2~12_combout = (\vga_ctrl_inst|cnt_h [7] & (\vga_ctrl_inst|Add2~11 $ (GND))) # (!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Add2~11 & VCC)) +// \vga_ctrl_inst|Add2~13 = CARRY((\vga_ctrl_inst|cnt_h [7] & !\vga_ctrl_inst|Add2~11 )) + + .dataa(\vga_ctrl_inst|cnt_h [7]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~11 ), + .combout(\vga_ctrl_inst|Add2~12_combout ), + .cout(\vga_ctrl_inst|Add2~13 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~12 .lut_mask = 16'hA50A; +defparam \vga_ctrl_inst|Add2~12 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N24 +cycloneive_lcell_comb \vga_pic_inst|LessThan14~0 ( +// Equation(s): +// \vga_pic_inst|LessThan14~0_combout = (\vga_ctrl_inst|Add2~12_combout & \vga_ctrl_inst|Add2~10_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan14~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan14~0 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|LessThan14~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~14 ( +// Equation(s): +// \vga_ctrl_inst|Add2~14_combout = (\vga_ctrl_inst|cnt_h [8] & (\vga_ctrl_inst|Add2~13 & VCC)) # (!\vga_ctrl_inst|cnt_h [8] & (!\vga_ctrl_inst|Add2~13 )) +// \vga_ctrl_inst|Add2~15 = CARRY((!\vga_ctrl_inst|cnt_h [8] & !\vga_ctrl_inst|Add2~13 )) + + .dataa(\vga_ctrl_inst|cnt_h [8]), + .datab(gnd), + .datac(gnd), + .datad(vcc), + .cin(\vga_ctrl_inst|Add2~13 ), + .combout(\vga_ctrl_inst|Add2~14_combout ), + .cout(\vga_ctrl_inst|Add2~15 )); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~14 .lut_mask = 16'hA505; +defparam \vga_ctrl_inst|Add2~14 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|Add2~16 ( +// Equation(s): +// \vga_ctrl_inst|Add2~16_combout = \vga_ctrl_inst|cnt_h [9] $ (\vga_ctrl_inst|Add2~15 ) + + .dataa(\vga_ctrl_inst|cnt_h [9]), + .datab(gnd), + .datac(gnd), + .datad(gnd), + .cin(\vga_ctrl_inst|Add2~15 ), + .combout(\vga_ctrl_inst|Add2~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|Add2~16 .lut_mask = 16'h5A5A; +defparam \vga_ctrl_inst|Add2~16 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N2 +cycloneive_lcell_comb \vga_pic_inst|LessThan6~0 ( +// Equation(s): +// \vga_pic_inst|LessThan6~0_combout = ((\vga_pic_inst|LessThan14~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (\vga_ctrl_inst|Add2~14_combout ))) # (!\vga_ctrl_inst|pix_data_req~4_combout ) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|LessThan14~0_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|Add2~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan6~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan6~0 .lut_mask = 16'hFFFD; +defparam \vga_pic_inst|LessThan6~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X33_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~0 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~0_combout = (!\vga_ctrl_inst|always1~0_combout & \vga_ctrl_inst|cnt_v [9]) + + .dataa(\vga_ctrl_inst|always1~0_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|cnt_v [9]), + .datad(gnd), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~0 .lut_mask = 16'h5050; +defparam \vga_ctrl_inst|pix_data_req~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N4 +cycloneive_lcell_comb \vga_ctrl_inst|LessThan4~0 ( +// Equation(s): +// \vga_ctrl_inst|LessThan4~0_combout = (\vga_ctrl_inst|LessThan2~0_combout & (((!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout )) # (!\vga_ctrl_inst|cnt_h [7]))) + + .dataa(\vga_ctrl_inst|Equal0~1_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|LessThan2~0_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|LessThan4~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|LessThan4~0 .lut_mask = 16'h7030; +defparam \vga_ctrl_inst|LessThan4~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N10 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~3 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~3_combout = ((!\vga_ctrl_inst|cnt_h [7] & (!\vga_ctrl_inst|Equal0~1_combout & \vga_ctrl_inst|LessThan2~1_combout ))) # (!\vga_ctrl_inst|Equal0~0_combout ) + + .dataa(\vga_ctrl_inst|Equal0~0_combout ), + .datab(\vga_ctrl_inst|cnt_h [7]), + .datac(\vga_ctrl_inst|Equal0~1_combout ), + .datad(\vga_ctrl_inst|LessThan2~1_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~3 .lut_mask = 16'h5755; +defparam \vga_ctrl_inst|pix_data_req~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N22 +cycloneive_lcell_comb \vga_ctrl_inst|pix_data_req~4 ( +// Equation(s): +// \vga_ctrl_inst|pix_data_req~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (!\vga_ctrl_inst|LessThan4~0_combout & \vga_ctrl_inst|pix_data_req~3_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|LessThan4~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~3_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|pix_data_req~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|pix_data_req~4 .lut_mask = 16'h0100; +defparam \vga_ctrl_inst|pix_data_req~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N2 +cycloneive_lcell_comb \vga_pic_inst|pix_data~4 ( +// Equation(s): +// \vga_pic_inst|pix_data~4_combout = (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout ) + + .dataa(gnd), + .datab(\vga_ctrl_inst|pix_data_req~4_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~4 .lut_mask = 16'h00CC; +defparam \vga_pic_inst|pix_data~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~9 ( +// Equation(s): +// \vga_pic_inst|pix_data~9_combout = (\vga_pic_inst|pix_data~8_combout & ((\vga_pic_inst|LessThan6~0_combout ) # ((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data~8_combout & +// (((!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout )))) + + .dataa(\vga_pic_inst|pix_data~8_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~9_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~9 .lut_mask = 16'h8F88; +defparam \vga_pic_inst|pix_data~9 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N8 +cycloneive_lcell_comb \vga_pic_inst|LessThan17~0 ( +// Equation(s): +// \vga_pic_inst|LessThan17~0_combout = (\vga_ctrl_inst|Add2~12_combout ) # ((\vga_ctrl_inst|Add2~10_combout ) # ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout ))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~10_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan17~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan17~0 .lut_mask = 16'hFEFF; +defparam \vga_pic_inst|LessThan17~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N14 +cycloneive_lcell_comb \vga_pic_inst|pix_data~6 ( +// Equation(s): +// \vga_pic_inst|pix_data~6_combout = ((\vga_pic_inst|LessThan17~0_combout & ((\vga_ctrl_inst|Add2~14_combout ) # (!\vga_pic_inst|pix_data~4_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|pix_data~4_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~6 .lut_mask = 16'hF755; +defparam \vga_pic_inst|pix_data~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N22 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~10 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~10_combout = (!\vga_ctrl_inst|Add2~12_combout ) # (!\vga_ctrl_inst|Add2~14_combout ) + + .dataa(gnd), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~10_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~10 .lut_mask = 16'h0FFF; +defparam \vga_pic_inst|pix_data[4]~10 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N4 +cycloneive_lcell_comb \vga_pic_inst|pix_data~11 ( +// Equation(s): +// \vga_pic_inst|pix_data~11_combout = (\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~10_combout ))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~11_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~11 .lut_mask = 16'h0080; +defparam \vga_pic_inst|pix_data~11 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N24 +cycloneive_lcell_comb \vga_pic_inst|pix_data~12 ( +// Equation(s): +// \vga_pic_inst|pix_data~12_combout = (\vga_pic_inst|pix_data[4]~5_combout & (((\vga_pic_inst|pix_data[4]~10_combout ) # (!\vga_pic_inst|pix_data~11_combout )))) # (!\vga_pic_inst|pix_data[4]~5_combout & (\vga_pic_inst|LessThan17~0_combout )) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan17~0_combout ), + .datac(\vga_pic_inst|pix_data[4]~10_combout ), + .datad(\vga_pic_inst|pix_data~11_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~12_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~12 .lut_mask = 16'hE4EE; +defparam \vga_pic_inst|pix_data~12 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N16 +cycloneive_lcell_comb \vga_pic_inst|pix_data~13 ( +// Equation(s): +// \vga_pic_inst|pix_data~13_combout = ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~7_combout ), + .datab(\vga_pic_inst|pix_data~9_combout ), + .datac(\vga_pic_inst|pix_data~6_combout ), + .datad(\vga_pic_inst|pix_data~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~13_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~13 .lut_mask = 16'h80FF; +defparam \vga_pic_inst|pix_data~13 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N17 +dffeas \vga_pic_inst|pix_data[0] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~13_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [0]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[0] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[0] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N0 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[0]~0 ( +// Equation(s): +// \vga_ctrl_inst|rgb[0]~0_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_ctrl_inst|rgb_valid~0_combout & (\vga_pic_inst|pix_data [0] & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|rgb_valid~0_combout ), + .datac(\vga_pic_inst|pix_data [0]), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[0]~0 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data[4]~7 ( +// Equation(s): +// \vga_pic_inst|pix_data[4]~7_combout = (!\vga_ctrl_inst|Add2~16_combout & (\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_ctrl_inst|Add2~14_combout ) # (!\vga_ctrl_inst|Add2~12_combout )))) + + .dataa(\vga_ctrl_inst|Add2~12_combout ), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data[4]~7_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4]~7 .lut_mask = 16'h0700; +defparam \vga_pic_inst|pix_data[4]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N18 +cycloneive_lcell_comb \vga_pic_inst|pix_data~16 ( +// Equation(s): +// \vga_pic_inst|pix_data~16_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & (\vga_pic_inst|pix_data~9_combout & \vga_pic_inst|pix_data~6_combout ))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~9_combout ), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~16_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~16 .lut_mask = 16'hEAAA; +defparam \vga_pic_inst|pix_data~16 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N19 +dffeas \vga_pic_inst|pix_data[4] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~16_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [4]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[4] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[4] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N26 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[1]~1 ( +// Equation(s): +// \vga_ctrl_inst|rgb[1]~1_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [4]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [4]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[1]~1_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[1]~1 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[1]~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~25 ( +// Equation(s): +// \vga_pic_inst|pix_data~25_combout = (\vga_ctrl_inst|Add2~16_combout & (((!\vga_pic_inst|LessThan17~0_combout )))) # (!\vga_ctrl_inst|Add2~16_combout & ((\vga_ctrl_inst|pix_data_req~4_combout & (\vga_pic_inst|pix_data~17_combout )) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & ((!\vga_pic_inst|LessThan17~0_combout ))))) + + .dataa(\vga_pic_inst|pix_data~17_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_pic_inst|LessThan17~0_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~25_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~25 .lut_mask = 16'h20EF; +defparam \vga_pic_inst|pix_data~25 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y23_N13 +dffeas \vga_pic_inst|pix_data[8] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~25_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [8]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[8] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[8] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N30 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[5]~2 ( +// Equation(s): +// \vga_ctrl_inst|rgb[5]~2_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [8]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [8]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[5]~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[5]~2 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[5]~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~18 ( +// Equation(s): +// \vga_pic_inst|pix_data~18_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~14_combout & (!\vga_ctrl_inst|Add2~12_combout & !\vga_ctrl_inst|Add2~10_combout )) # (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|Add2~12_combout +// )))) + + .dataa(\vga_ctrl_inst|Add2~14_combout ), + .datab(\vga_ctrl_inst|Add2~12_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~10_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~18_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~18 .lut_mask = 16'h4060; +defparam \vga_pic_inst|pix_data~18 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~14 ( +// Equation(s): +// \vga_pic_inst|pix_data~14_combout = (!\vga_ctrl_inst|Add2~14_combout & (\vga_ctrl_inst|pix_data_req~4_combout & !\vga_ctrl_inst|Add2~12_combout )) + + .dataa(gnd), + .datab(\vga_ctrl_inst|Add2~14_combout ), + .datac(\vga_ctrl_inst|pix_data_req~4_combout ), + .datad(\vga_ctrl_inst|Add2~12_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~14_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~14 .lut_mask = 16'h0030; +defparam \vga_pic_inst|pix_data~14 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y23_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~26 ( +// Equation(s): +// \vga_pic_inst|pix_data~26_combout = (\vga_ctrl_inst|pix_data_req~4_combout & ((\vga_ctrl_inst|Add2~16_combout & ((\vga_pic_inst|pix_data~14_combout ))) # (!\vga_ctrl_inst|Add2~16_combout & (\vga_pic_inst|pix_data~18_combout )))) # +// (!\vga_ctrl_inst|pix_data_req~4_combout & (((\vga_pic_inst|pix_data~14_combout )))) + + .dataa(\vga_ctrl_inst|pix_data_req~4_combout ), + .datab(\vga_pic_inst|pix_data~18_combout ), + .datac(\vga_ctrl_inst|Add2~16_combout ), + .datad(\vga_pic_inst|pix_data~14_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~26_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~26 .lut_mask = 16'hFD08; +defparam \vga_pic_inst|pix_data~26 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N0 +cycloneive_lcell_comb \vga_pic_inst|pix_data~19 ( +// Equation(s): +// \vga_pic_inst|pix_data~19_combout = (\vga_pic_inst|pix_data~26_combout & \vga_pic_inst|pix_data~6_combout ) + + .dataa(gnd), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(gnd), + .datad(\vga_pic_inst|pix_data~6_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~19_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~19 .lut_mask = 16'hCC00; +defparam \vga_pic_inst|pix_data~19 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N1 +dffeas \vga_pic_inst|pix_data[9] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~19_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [9]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[9] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[9] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N16 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[7]~3 ( +// Equation(s): +// \vga_ctrl_inst|rgb[7]~3_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [9]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [9]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[7]~3_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[7]~3 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[7]~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N6 +cycloneive_lcell_comb \vga_pic_inst|LessThan2~2 ( +// Equation(s): +// \vga_pic_inst|LessThan2~2_combout = (\vga_pic_inst|LessThan17~0_combout ) # ((\vga_ctrl_inst|Add2~16_combout ) # (!\vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_pic_inst|LessThan17~0_combout ), + .datab(\vga_ctrl_inst|Add2~16_combout ), + .datac(gnd), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|LessThan2~2_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|LessThan2~2 .lut_mask = 16'hEEFF; +defparam \vga_pic_inst|LessThan2~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N12 +cycloneive_lcell_comb \vga_pic_inst|pix_data~20 ( +// Equation(s): +// \vga_pic_inst|pix_data~20_combout = (!\vga_ctrl_inst|Add2~16_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_ctrl_inst|pix_data_req~4_combout )) + + .dataa(\vga_ctrl_inst|Add2~16_combout ), + .datab(gnd), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_ctrl_inst|pix_data_req~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~20_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~20 .lut_mask = 16'h0500; +defparam \vga_pic_inst|pix_data~20 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y24_N26 +cycloneive_lcell_comb \vga_pic_inst|pix_data~21 ( +// Equation(s): +// \vga_pic_inst|pix_data~21_combout = (\vga_pic_inst|LessThan2~2_combout & ((\vga_pic_inst|pix_data~26_combout ) # ((\vga_pic_inst|pix_data~4_combout & \vga_pic_inst|pix_data~20_combout )))) + + .dataa(\vga_pic_inst|pix_data~4_combout ), + .datab(\vga_pic_inst|pix_data~26_combout ), + .datac(\vga_pic_inst|LessThan2~2_combout ), + .datad(\vga_pic_inst|pix_data~20_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~21_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~21 .lut_mask = 16'hE0C0; +defparam \vga_pic_inst|pix_data~21 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X37_Y24_N27 +dffeas \vga_pic_inst|pix_data[10] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~21_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [10]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[10] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[10] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N2 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[10]~4 ( +// Equation(s): +// \vga_ctrl_inst|rgb[10]~4_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (!\vga_ctrl_inst|pix_data_req~0_combout & (\vga_ctrl_inst|rgb_valid~0_combout & \vga_pic_inst|pix_data [10]))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_ctrl_inst|pix_data_req~0_combout ), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_pic_inst|pix_data [10]), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[10]~4_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[10]~4 .lut_mask = 16'h1000; +defparam \vga_ctrl_inst|rgb[10]~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N20 +cycloneive_lcell_comb \vga_pic_inst|pix_data~22 ( +// Equation(s): +// \vga_pic_inst|pix_data~22_combout = ((\vga_pic_inst|pix_data[4]~5_combout & (!\vga_ctrl_inst|Add2~14_combout & \vga_pic_inst|pix_data~4_combout ))) # (!\vga_pic_inst|LessThan6~0_combout ) + + .dataa(\vga_pic_inst|pix_data[4]~5_combout ), + .datab(\vga_pic_inst|LessThan6~0_combout ), + .datac(\vga_ctrl_inst|Add2~14_combout ), + .datad(\vga_pic_inst|pix_data~4_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~22_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~22 .lut_mask = 16'h3B33; +defparam \vga_pic_inst|pix_data~22 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N28 +cycloneive_lcell_comb \vga_pic_inst|pix_data~23 ( +// Equation(s): +// \vga_pic_inst|pix_data~23_combout = ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) # (!\vga_pic_inst|pix_data~12_combout ) + + .dataa(\vga_pic_inst|LessThan2~2_combout ), + .datab(\vga_pic_inst|pix_data~12_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|pix_data[4]~7_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~23_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~23 .lut_mask = 16'hF733; +defparam \vga_pic_inst|pix_data~23 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N29 +dffeas \vga_pic_inst|pix_data[13] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~23_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [13]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[13] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[13] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N20 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[11]~5 ( +// Equation(s): +// \vga_ctrl_inst|rgb[11]~5_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [13] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [13]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[11]~5_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[11]~5 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[11]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X36_Y24_N30 +cycloneive_lcell_comb \vga_pic_inst|pix_data~24 ( +// Equation(s): +// \vga_pic_inst|pix_data~24_combout = (\vga_pic_inst|pix_data~15_combout ) # ((\vga_pic_inst|pix_data[4]~7_combout & ((\vga_pic_inst|pix_data~22_combout ) # (!\vga_pic_inst|LessThan2~2_combout )))) + + .dataa(\vga_pic_inst|pix_data~15_combout ), + .datab(\vga_pic_inst|pix_data[4]~7_combout ), + .datac(\vga_pic_inst|pix_data~22_combout ), + .datad(\vga_pic_inst|LessThan2~2_combout ), + .cin(gnd), + .combout(\vga_pic_inst|pix_data~24_combout ), + .cout()); +// synopsys translate_off +defparam \vga_pic_inst|pix_data~24 .lut_mask = 16'hEAEE; +defparam \vga_pic_inst|pix_data~24 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: FF_X36_Y24_N31 +dffeas \vga_pic_inst|pix_data[15] ( + .clk(\clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl_outclk ), + .d(\vga_pic_inst|pix_data~24_combout ), + .asdata(vcc), + .clrn(!\rst_n~0clkctrl_outclk ), + .aload(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .q(\vga_pic_inst|pix_data [15]), + .prn(vcc)); +// synopsys translate_off +defparam \vga_pic_inst|pix_data[15] .is_wysiwyg = "true"; +defparam \vga_pic_inst|pix_data[15] .power_up = "low"; +// synopsys translate_on + +// Location: LCCOMB_X37_Y23_N6 +cycloneive_lcell_comb \vga_ctrl_inst|rgb[12]~6 ( +// Equation(s): +// \vga_ctrl_inst|rgb[12]~6_combout = (!\vga_ctrl_inst|pix_data_req~2_combout & (\vga_pic_inst|pix_data [15] & (\vga_ctrl_inst|rgb_valid~0_combout & !\vga_ctrl_inst|pix_data_req~0_combout ))) + + .dataa(\vga_ctrl_inst|pix_data_req~2_combout ), + .datab(\vga_pic_inst|pix_data [15]), + .datac(\vga_ctrl_inst|rgb_valid~0_combout ), + .datad(\vga_ctrl_inst|pix_data_req~0_combout ), + .cin(gnd), + .combout(\vga_ctrl_inst|rgb[12]~6_combout ), + .cout()); +// synopsys translate_off +defparam \vga_ctrl_inst|rgb[12]~6 .lut_mask = 16'h0040; +defparam \vga_ctrl_inst|rgb[12]~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +endmodule diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_min_1200mv_0c_v_fast.sdo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_min_1200mv_0c_v_fast.sdo new file mode 100644 index 0000000..3c10c0b --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_min_1200mv_0c_v_fast.sdo @@ -0,0 +1,2108 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Fast Corner delays for the design using part EP4CE15F23C8, +// with speed grade M, core voltage 1.2V, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "vga_colorbar") + (DATE "06/02/2023 04:42:20") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (147:147:147) (199:199:199)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (2024:2024:2024) (2024:2024:2024)) + (PORT inclk[0] (1104:1104:1104) (1104:1104:1104)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (367:367:367) (451:451:451)) + (IOPATH dataa combout (186:186:186) (180:180:180)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (371:371:371) (445:445:445)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (372:372:372) (445:445:445)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datab (381:381:381) (460:460:460)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (214:214:214) (270:270:270)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT datab (366:366:366) (442:442:442)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (209:209:209) (275:275:275)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (454:454:454)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT datab (162:162:162) (213:213:213)) + (PORT datad (139:139:139) (183:183:183)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (377:377:377)) + (PORT datab (336:336:336) (392:392:392)) + (PORT datad (128:128:128) (157:157:157)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (474:474:474) (551:551:551)) + (PORT datad (354:354:354) (415:415:415)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (444:444:444) (512:512:512)) + (PORT datab (363:363:363) (428:428:428)) + (PORT datac (376:376:376) (445:445:445)) + (PORT datad (456:456:456) (524:524:524)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~15) + (DELAY + (ABSOLUTE + (PORT dataa (322:322:322) (383:383:383)) + (PORT datab (188:188:188) (225:225:225)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (105:105:105) (128:128:128)) + (IOPATH dataa combout (165:165:165) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~17) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (170:170:170)) + (PORT datac (305:305:305) (361:361:361)) + (PORT datad (115:115:115) (138:138:138)) + (IOPATH datab combout (196:196:196) (205:205:205)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (358:358:358) (738:738:738)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (1120:1120:1120) (1119:1119:1119)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE hsync\~output) + (DELAY + (ABSOLUTE + (PORT i (1064:1064:1064) (938:938:938)) + (IOPATH i o (1647:1647:1647) (1667:1667:1667)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE vsync\~output) + (DELAY + (ABSOLUTE + (PORT i (913:913:913) (809:809:809)) + (IOPATH i o (1657:1657:1657) (1677:1677:1677)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1225:1225:1225) (1372:1372:1372)) + (IOPATH i o (1667:1667:1667) (1647:1647:1647)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1200:1200:1200) (1338:1338:1338)) + (IOPATH i o (1677:1677:1677) (1657:1657:1657)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1318:1318:1318) (1471:1471:1471)) + (IOPATH i o (1677:1677:1677) (1657:1657:1657)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1443:1443:1443) (1614:1614:1614)) + (IOPATH i o (1812:1812:1812) (1785:1785:1785)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1444:1444:1444) (1617:1617:1617)) + (IOPATH i o (1792:1792:1792) (1765:1765:1765)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (636:636:636) (726:726:726)) + (IOPATH i o (1792:1792:1792) (1765:1765:1765)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (644:644:644) (734:734:734)) + (IOPATH i o (1792:1792:1792) (1765:1765:1765)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (865:865:865) (976:976:976)) + (IOPATH i o (1802:1802:1802) (1775:1775:1775)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (802:802:802) (910:910:910)) + (IOPATH i o (1762:1762:1762) (1735:1735:1735)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (792:792:792) (896:896:896)) + (IOPATH i o (1782:1782:1782) (1755:1755:1755)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (755:755:755) (852:852:852)) + (IOPATH i o (1772:1772:1772) (1745:1745:1745)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (748:748:748) (836:836:836)) + (IOPATH i o (1772:1772:1772) (1745:1745:1745)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (592:592:592) (654:654:654)) + (IOPATH i o (1782:1782:1782) (1755:1755:1755)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (586:586:586) (650:650:650)) + (IOPATH i o (1772:1772:1772) (1745:1745:1745)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (428:428:428) (469:469:469)) + (IOPATH i o (1782:1782:1782) (1755:1755:1755)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (438:438:438) (484:484:484)) + (IOPATH i o (1772:1772:1772) (1745:1745:1745)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (196:196:196)) + (IOPATH datab combout (192:192:192) (181:181:181)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (1411:1411:1411) (1239:1239:1239)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (2263:2263:2263) (2046:2046:2046)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1116:1116:1116) (942:942:942)) + (PORT datab (130:130:130) (178:178:178)) + (PORT datac (1749:1749:1749) (1960:1960:1960)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (910:910:910) (1027:1027:1027)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (146:146:146) (198:198:198)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (196:196:196)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (141:141:141) (190:190:190)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (411:411:411)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (146:146:146) (195:195:195)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (143:143:143) (193:193:193)) + (IOPATH dataa combout (165:165:165) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (167:167:167) (219:219:219)) + (IOPATH datab combout (192:192:192) (177:177:177)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (146:146:146) (190:190:190)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~1) + (DELAY + (ABSOLUTE + (PORT datab (312:312:312) (362:362:362)) + (PORT datac (93:93:93) (115:115:115)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~0) + (DELAY + (ABSOLUTE + (PORT datab (287:287:287) (330:330:330)) + (PORT datac (104:104:104) (125:125:125)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (247:247:247) (303:303:303)) + (PORT datab (160:160:160) (214:214:214)) + (PORT datac (322:322:322) (386:386:386)) + (PORT datad (134:134:134) (173:173:173)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (149:149:149) (202:202:202)) + (PORT datab (147:147:147) (197:197:197)) + (PORT datac (134:134:134) (177:177:177)) + (PORT datad (135:135:135) (175:175:175)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (333:333:333) (404:404:404)) + (PORT datab (276:276:276) (321:321:321)) + (PORT datac (273:273:273) (312:312:312)) + (PORT datad (349:349:349) (419:419:419)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~2) + (DELAY + (ABSOLUTE + (PORT datab (106:106:106) (135:135:135)) + (PORT datac (298:298:298) (341:341:341)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (125:125:125)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (871:871:871) (875:875:875)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (855:855:855) (858:858:858)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT datab (161:161:161) (213:213:213)) + (PORT datad (139:139:139) (182:182:182)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (388:388:388)) + (PORT datab (342:342:342) (409:409:409)) + (PORT datac (286:286:286) (333:333:333)) + (PORT datad (133:133:133) (171:171:171)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (381:381:381)) + (PORT datab (340:340:340) (397:397:397)) + (PORT datad (126:126:126) (150:150:150)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (331:331:331) (397:397:397)) + (PORT datab (334:334:334) (390:390:390)) + (PORT datad (130:130:130) (158:158:158)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (424:424:424) (489:489:489)) + (PORT datab (333:333:333) (390:390:390)) + (PORT datad (131:131:131) (159:159:159)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (391:391:391) (472:472:472)) + (PORT datab (146:146:146) (197:197:197)) + (PORT datac (132:132:132) (176:176:176)) + (PORT datad (133:133:133) (172:172:172)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (442:442:442) (510:510:510)) + (PORT datab (337:337:337) (394:394:394)) + (PORT datad (127:127:127) (152:152:152)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (158:158:158)) + (PORT datab (147:147:147) (198:198:198)) + (PORT datac (162:162:162) (191:191:191)) + (PORT datad (137:137:137) (178:178:178)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (414:414:414)) + (PORT datab (334:334:334) (390:390:390)) + (PORT datad (131:131:131) (159:159:159)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT datab (148:148:148) (198:198:198)) + (PORT datac (134:134:134) (177:177:177)) + (PORT datad (135:135:135) (174:174:174)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (334:334:334) (392:392:392)) + (PORT datab (338:338:338) (394:394:394)) + (PORT datad (127:127:127) (151:151:151)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (870:870:870) (874:874:874)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (854:854:854) (857:857:857)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (214:214:214) (274:274:274)) + (IOPATH datab combout (166:166:166) (176:176:176)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (405:405:405)) + (PORT datab (106:106:106) (135:135:135)) + (PORT datad (466:466:466) (539:539:539)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datad (138:138:138) (179:179:179)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (345:345:345) (405:405:405)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datad (467:467:467) (539:539:539)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (484:484:484) (562:562:562)) + (PORT datad (331:331:331) (379:379:379)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (190:190:190) (188:188:188)) + (IOPATH datac combout (190:190:190) (195:195:195)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (873:873:873) (878:878:878)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (857:857:857) (860:860:860)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (142:142:142) (192:192:192)) + (PORT datab (142:142:142) (190:190:190)) + (PORT datac (340:340:340) (408:408:408)) + (PORT datad (344:344:344) (418:418:418)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (110:110:110) (143:143:143)) + (PORT datab (150:150:150) (201:201:201)) + (PORT datac (368:368:368) (448:448:448)) + (PORT datad (103:103:103) (127:127:127)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT datab (147:147:147) (198:198:198)) + (PORT datad (136:136:136) (177:177:177)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (454:454:454)) + (PORT datab (150:150:150) (201:201:201)) + (PORT datac (200:200:200) (253:253:253)) + (PORT datad (197:197:197) (250:250:250)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (108:108:108) (140:140:140)) + (PORT datab (103:103:103) (132:132:132)) + (PORT datac (253:253:253) (288:288:288)) + (PORT datad (107:107:107) (132:132:132)) + (IOPATH dataa combout (181:181:181) (175:175:175)) + (IOPATH datab combout (182:182:182) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT datab (341:341:341) (408:408:408)) + (PORT datac (315:315:315) (377:377:377)) + (PORT datad (132:132:132) (170:170:170)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb_valid\~0) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (319:319:319)) + (PORT datab (366:366:366) (441:441:441)) + (PORT datac (285:285:285) (331:331:331)) + (PORT datad (99:99:99) (122:122:122)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (280:280:280)) + (PORT datab (312:312:312) (370:370:370)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datab cout (227:227:227) (175:175:175)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (226:226:226) (280:280:280)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (212:212:212) (266:266:266)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~7) + (DELAY + (ABSOLUTE + (PORT dataa (216:216:216) (272:272:272)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (320:320:320) (387:387:387)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT datab (227:227:227) (282:282:282)) + (IOPATH datab combout (167:167:167) (174:174:174)) + (IOPATH datab cout (227:227:227) (175:175:175)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (385:385:385)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~0) + (DELAY + (ABSOLUTE + (PORT datab (135:135:135) (169:169:169)) + (PORT datad (115:115:115) (137:137:137)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (238:238:238) (291:291:291)) + (IOPATH dataa combout (166:166:166) (173:173:173)) + (IOPATH dataa cout (226:226:226) (171:171:171)) + (IOPATH datad combout (68:68:68) (63:63:63)) + (IOPATH cin combout (187:187:187) (204:204:204)) + (IOPATH cin cout (34:34:34) (34:34:34)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (227:227:227) (281:281:281)) + (IOPATH dataa combout (195:195:195) (203:203:203)) + (IOPATH cin combout (187:187:187) (204:204:204)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (321:321:321) (375:375:375)) + (PORT datab (105:105:105) (134:134:134)) + (PORT datac (108:108:108) (132:132:132)) + (PORT datad (110:110:110) (130:130:130)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (158:158:158)) + (PORT datac (365:365:365) (444:444:444)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (124:124:124)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (336:336:336)) + (PORT datab (368:368:368) (444:444:444)) + (PORT datac (283:283:283) (329:329:329)) + (PORT datad (101:101:101) (124:124:124)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (274:274:274) (319:319:319)) + (PORT datab (367:367:367) (443:443:443)) + (PORT datac (272:272:272) (311:311:311)) + (PORT datad (100:100:100) (123:123:123)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~4) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (385:385:385)) + (PORT datab (344:344:344) (409:409:409)) + (PORT datac (91:91:91) (113:113:113)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~4) + (DELAY + (ABSOLUTE + (PORT datab (476:476:476) (553:553:553)) + (PORT datad (334:334:334) (384:384:384)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~9) + (DELAY + (ABSOLUTE + (PORT dataa (106:106:106) (138:138:138)) + (PORT datab (336:336:336) (394:394:394)) + (PORT datac (372:372:372) (441:441:441)) + (PORT datad (110:110:110) (131:131:131)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (348:348:348) (409:409:409)) + (PORT datab (363:363:363) (427:427:427)) + (PORT datac (372:372:372) (442:442:442)) + (PORT datad (460:460:460) (529:529:529)) + (IOPATH dataa combout (165:165:165) (159:159:159)) + (IOPATH datab combout (166:166:166) (158:158:158)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~6) + (DELAY + (ABSOLUTE + (PORT dataa (118:118:118) (156:156:156)) + (PORT datab (125:125:125) (157:157:157)) + (PORT datac (373:373:373) (443:443:443)) + (PORT datad (182:182:182) (213:213:213)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT datac (375:375:375) (445:445:445)) + (PORT datad (334:334:334) (383:383:383)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~11) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (384:384:384)) + (PORT datab (136:136:136) (171:171:171)) + (PORT datac (304:304:304) (352:352:352)) + (PORT datad (115:115:115) (138:138:138)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (157:157:157)) + (PORT datab (117:117:117) (145:145:145)) + (PORT datac (93:93:93) (116:116:116)) + (PORT datad (312:312:312) (361:361:361)) + (IOPATH dataa combout (186:186:186) (175:175:175)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~13) + (DELAY + (ABSOLUTE + (PORT dataa (206:206:206) (242:242:242)) + (PORT datab (109:109:109) (140:140:140)) + (PORT datac (114:114:114) (135:135:135)) + (PORT datad (95:95:95) (114:114:114)) + (IOPATH dataa combout (159:159:159) (163:163:163)) + (IOPATH datab combout (161:161:161) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (388:388:388)) + (PORT datab (134:134:134) (172:172:172)) + (PORT datac (329:329:329) (393:393:393)) + (PORT datad (330:330:330) (390:390:390)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (349:349:349) (410:410:410)) + (PORT datab (390:390:390) (461:461:461)) + (PORT datac (433:433:433) (493:493:493)) + (PORT datad (462:462:462) (531:531:531)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~16) + (DELAY + (ABSOLUTE + (PORT dataa (109:109:109) (144:144:144)) + (PORT datab (127:127:127) (161:161:161)) + (PORT datac (95:95:95) (119:119:119)) + (PORT datad (185:185:185) (207:207:207)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (167:167:167) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (383:383:383)) + (PORT datab (342:342:342) (408:408:408)) + (PORT datac (117:117:117) (152:152:152)) + (PORT datad (347:347:347) (420:420:420)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~25) + (DELAY + (ABSOLUTE + (PORT dataa (192:192:192) (230:230:230)) + (PORT datab (189:189:189) (227:227:227)) + (PORT datac (103:103:103) (124:124:124)) + (PORT datad (319:319:319) (364:364:364)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (872:872:872) (876:876:876)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (856:856:856) (859:859:859)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (323:323:323) (383:383:383)) + (PORT datab (341:341:341) (407:407:407)) + (PORT datac (118:118:118) (153:153:153)) + (PORT datad (119:119:119) (155:155:155)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~18) + (DELAY + (ABSOLUTE + (PORT dataa (326:326:326) (383:383:383)) + (PORT datab (135:135:135) (170:170:170)) + (PORT datac (299:299:299) (345:345:345)) + (PORT datad (115:115:115) (138:138:138)) + (IOPATH dataa combout (188:188:188) (179:179:179)) + (IOPATH datab combout (188:188:188) (177:177:177)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~14) + (DELAY + (ABSOLUTE + (PORT datab (123:123:123) (153:153:153)) + (PORT datac (305:305:305) (353:353:353)) + (PORT datad (123:123:123) (147:147:147)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~26) + (DELAY + (ABSOLUTE + (PORT dataa (314:314:314) (368:368:368)) + (PORT datab (102:102:102) (130:130:130)) + (PORT datac (106:106:106) (129:129:129)) + (PORT datad (106:106:106) (124:124:124)) + (IOPATH dataa combout (170:170:170) (165:165:165)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~19) + (DELAY + (ABSOLUTE + (PORT datab (349:349:349) (413:413:413)) + (PORT datad (185:185:185) (206:206:206)) + (IOPATH datab combout (167:167:167) (167:167:167)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (325:325:325) (385:385:385)) + (PORT datab (345:345:345) (411:411:411)) + (PORT datac (115:115:115) (151:151:151)) + (PORT datad (322:322:322) (388:388:388)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (194:194:194) (237:237:237)) + (PORT datab (373:373:373) (440:440:440)) + (PORT datad (461:461:461) (530:530:530)) + (IOPATH dataa combout (166:166:166) (159:159:159)) + (IOPATH datab combout (167:167:167) (158:158:158)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~20) + (DELAY + (ABSOLUTE + (PORT dataa (343:343:343) (401:401:401)) + (PORT datac (330:330:330) (377:377:377)) + (PORT datad (345:345:345) (401:401:401)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~21) + (DELAY + (ABSOLUTE + (PORT dataa (203:203:203) (238:238:238)) + (PORT datab (347:347:347) (410:410:410)) + (PORT datac (175:175:175) (202:202:202)) + (PORT datad (91:91:91) (109:109:109)) + (IOPATH dataa combout (166:166:166) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (859:859:859) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (388:388:388)) + (PORT datab (350:350:350) (416:416:416)) + (PORT datac (116:116:116) (151:151:151)) + (PORT datad (354:354:354) (430:430:430)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~22) + (DELAY + (ABSOLUTE + (PORT dataa (119:119:119) (157:157:157)) + (PORT datab (335:335:335) (393:393:393)) + (PORT datac (375:375:375) (445:445:445)) + (PORT datad (113:113:113) (135:135:135)) + (IOPATH dataa combout (158:158:158) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (125:125:125)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~23) + (DELAY + (ABSOLUTE + (PORT dataa (123:123:123) (157:157:157)) + (PORT datab (106:106:106) (136:136:136)) + (PORT datac (165:165:165) (194:194:194)) + (PORT datad (116:116:116) (140:140:140)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[11\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (324:324:324) (385:385:385)) + (PORT datab (351:351:351) (431:431:431)) + (PORT datac (116:116:116) (152:152:152)) + (PORT datad (324:324:324) (383:383:383)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~24) + (DELAY + (ABSOLUTE + (PORT dataa (111:111:111) (145:145:145)) + (PORT datab (130:130:130) (163:163:163)) + (PORT datac (165:165:165) (194:194:194)) + (PORT datad (111:111:111) (132:132:132)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (875:875:875) (879:879:879)) + (PORT d (37:37:37) (50:50:50)) + (PORT clrn (858:858:858) (862:862:862)) + (IOPATH (posedge clk) q (105:105:105) (105:105:105)) + (IOPATH (negedge clrn) q (110:110:110) (110:110:110)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (84:84:84)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[12\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (327:327:327) (388:388:388)) + (PORT datab (311:311:311) (371:371:371)) + (PORT datac (116:116:116) (150:150:150)) + (PORT datad (329:329:329) (388:388:388)) + (IOPATH dataa combout (158:158:158) (157:157:157)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) +) diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_modelsim.xrf b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_modelsim.xrf new file mode 100644 index 0000000..b3b9b6c --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_modelsim.xrf @@ -0,0 +1,166 @@ +vendor_name = ModelSim +source_file = 1, E:/simiao/lc/A415/09_vga/vga/sim/tb_vga_ctrl.v +source_file = 1, E:/simiao/lc/A415/09_vga/vga/sim/tb_vga_colorbar.v +source_file = 1, E:/simiao/lc/A415/09_vga/vga/rtl/vga_pic.v +source_file = 1, E:/simiao/lc/A415/09_vga/vga/rtl/vga_ctrl.v +source_file = 1, E:/simiao/lc/A415/09_vga/vga/rtl/vga_colorbar.v +source_file = 1, E:/simiao/lc/A415/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.qip +source_file = 1, E:/simiao/lc/A415/09_vga/vga/quartus_prj/ip_core/clk_gen/clk_gen.v +source_file = 1, E:/simiao/lc/A415/09_vga/vga/quartus_prj/db/vga_colorbar.cbx.xml +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/altpll.tdf +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_pll.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/stratixii_pll.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/cycloneii_pll.inc +source_file = 1, c:/altera/13.0sp1/quartus/libraries/megafunctions/cbx.lst +source_file = 1, E:/simiao/lc/A415/09_vga/vga/quartus_prj/db/clk_gen_altpll.v +design_name = vga_colorbar +instance = comp, \vga_ctrl_inst|Add0~4 , vga_ctrl_inst|Add0~4, vga_colorbar, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll1 , clk_gen_inst|altpll_component|auto_generated|pll1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~0 , vga_ctrl_inst|Add1~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~2 , vga_ctrl_inst|Add1~2, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~4 , vga_ctrl_inst|Add1~4, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~6 , vga_ctrl_inst|Add1~6, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~8 , vga_ctrl_inst|Add1~8, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~10 , vga_ctrl_inst|Add1~10, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~12 , vga_ctrl_inst|Add1~12, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~16 , vga_ctrl_inst|Add1~16, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[8] , vga_ctrl_inst|cnt_v[8], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Equal0~0 , vga_ctrl_inst|Equal0~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[2] , vga_ctrl_inst|cnt_h[2], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[8]~3 , vga_ctrl_inst|cnt_v[8]~3, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[4]~5 , vga_pic_inst|pix_data[4]~5, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~8 , vga_pic_inst|pix_data~8, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~15 , vga_pic_inst|pix_data~15, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~17 , vga_pic_inst|pix_data~17, vga_colorbar, 1 +instance = comp, \sys_clk~input , sys_clk~input, vga_colorbar, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl , clk_gen_inst|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, vga_colorbar, 1 +instance = comp, \hsync~output , hsync~output, vga_colorbar, 1 +instance = comp, \vsync~output , vsync~output, vga_colorbar, 1 +instance = comp, \rgb[0]~output , rgb[0]~output, vga_colorbar, 1 +instance = comp, \rgb[1]~output , rgb[1]~output, vga_colorbar, 1 +instance = comp, \rgb[2]~output , rgb[2]~output, vga_colorbar, 1 +instance = comp, \rgb[3]~output , rgb[3]~output, vga_colorbar, 1 +instance = comp, \rgb[4]~output , rgb[4]~output, vga_colorbar, 1 +instance = comp, \rgb[5]~output , rgb[5]~output, vga_colorbar, 1 +instance = comp, \rgb[6]~output , rgb[6]~output, vga_colorbar, 1 +instance = comp, \rgb[7]~output , rgb[7]~output, vga_colorbar, 1 +instance = comp, \rgb[8]~output , rgb[8]~output, vga_colorbar, 1 +instance = comp, \rgb[9]~output , rgb[9]~output, vga_colorbar, 1 +instance = comp, \rgb[10]~output , rgb[10]~output, vga_colorbar, 1 +instance = comp, \rgb[11]~output , rgb[11]~output, vga_colorbar, 1 +instance = comp, \rgb[12]~output , rgb[12]~output, vga_colorbar, 1 +instance = comp, \rgb[13]~output , rgb[13]~output, vga_colorbar, 1 +instance = comp, \rgb[14]~output , rgb[14]~output, vga_colorbar, 1 +instance = comp, \rgb[15]~output , rgb[15]~output, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~0 , vga_ctrl_inst|Add0~0, vga_colorbar, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder , clk_gen_inst|altpll_component|auto_generated|pll_lock_sync~feeder, vga_colorbar, 1 +instance = comp, \sys_rst_n~input , sys_rst_n~input, vga_colorbar, 1 +instance = comp, \clk_gen_inst|altpll_component|auto_generated|pll_lock_sync , clk_gen_inst|altpll_component|auto_generated|pll_lock_sync, vga_colorbar, 1 +instance = comp, \rst_n~0 , rst_n~0, vga_colorbar, 1 +instance = comp, \rst_n~0clkctrl , rst_n~0clkctrl, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[0] , vga_ctrl_inst|cnt_h[0], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~2 , vga_ctrl_inst|Add0~2, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~6 , vga_ctrl_inst|Add0~6, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[3] , vga_ctrl_inst|cnt_h[3], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~8 , vga_ctrl_inst|Add0~8, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[4] , vga_ctrl_inst|cnt_h[4], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~10 , vga_ctrl_inst|Add0~10, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~12 , vga_ctrl_inst|Add0~12, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[6] , vga_ctrl_inst|cnt_h[6], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~14 , vga_ctrl_inst|Add0~14, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[7] , vga_ctrl_inst|cnt_h[7], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~16 , vga_ctrl_inst|Add0~16, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add0~18 , vga_ctrl_inst|Add0~18, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h~1 , vga_ctrl_inst|cnt_h~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[9] , vga_ctrl_inst|cnt_h[9], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h~0 , vga_ctrl_inst|cnt_h~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[5] , vga_ctrl_inst|cnt_h[5], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Equal0~2 , vga_ctrl_inst|Equal0~2, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[1] , vga_ctrl_inst|cnt_h[1], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Equal0~1 , vga_ctrl_inst|Equal0~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Equal0~3 , vga_ctrl_inst|Equal0~3, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h~2 , vga_ctrl_inst|cnt_h~2, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_h[8] , vga_ctrl_inst|cnt_h[8], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan2~0 , vga_ctrl_inst|LessThan2~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan0~0 , vga_ctrl_inst|LessThan0~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[0]~9 , vga_ctrl_inst|cnt_v[0]~9, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[0] , vga_ctrl_inst|cnt_v[0], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[2]~8 , vga_ctrl_inst|cnt_v[2]~8, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[2] , vga_ctrl_inst|cnt_v[2], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[4]~6 , vga_ctrl_inst|cnt_v[4]~6, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[4] , vga_ctrl_inst|cnt_v[4], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|always1~1 , vga_ctrl_inst|always1~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[1]~0 , vga_ctrl_inst|cnt_v[1]~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[1] , vga_ctrl_inst|cnt_v[1], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|always1~2 , vga_ctrl_inst|always1~2, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[3]~7 , vga_ctrl_inst|cnt_v[3]~7, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[3] , vga_ctrl_inst|cnt_v[3], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan6~0 , vga_ctrl_inst|LessThan6~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[5]~2 , vga_ctrl_inst|cnt_v[5]~2, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[5] , vga_ctrl_inst|cnt_v[5], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~14 , vga_ctrl_inst|Add1~14, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[7]~4 , vga_ctrl_inst|cnt_v[7]~4, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[7] , vga_ctrl_inst|cnt_v[7], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add1~18 , vga_ctrl_inst|Add1~18, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[9]~1 , vga_ctrl_inst|cnt_v[9]~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[9] , vga_ctrl_inst|cnt_v[9], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[6]~5 , vga_ctrl_inst|cnt_v[6]~5, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|cnt_v[6] , vga_ctrl_inst|cnt_v[6], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|always1~0 , vga_ctrl_inst|always1~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan1~0 , vga_ctrl_inst|LessThan1~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan6~1 , vga_ctrl_inst|LessThan6~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~1 , vga_ctrl_inst|pix_data_req~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~2 , vga_ctrl_inst|pix_data_req~2, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan2~1 , vga_ctrl_inst|LessThan2~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb_valid~0 , vga_ctrl_inst|rgb_valid~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~1 , vga_ctrl_inst|Add2~1, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~3 , vga_ctrl_inst|Add2~3, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~5 , vga_ctrl_inst|Add2~5, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~7 , vga_ctrl_inst|Add2~7, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~9 , vga_ctrl_inst|Add2~9, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~10 , vga_ctrl_inst|Add2~10, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~12 , vga_ctrl_inst|Add2~12, vga_colorbar, 1 +instance = comp, \vga_pic_inst|LessThan14~0 , vga_pic_inst|LessThan14~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~14 , vga_ctrl_inst|Add2~14, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|Add2~16 , vga_ctrl_inst|Add2~16, vga_colorbar, 1 +instance = comp, \vga_pic_inst|LessThan6~0 , vga_pic_inst|LessThan6~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~0 , vga_ctrl_inst|pix_data_req~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|LessThan4~0 , vga_ctrl_inst|LessThan4~0, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~3 , vga_ctrl_inst|pix_data_req~3, vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|pix_data_req~4 , vga_ctrl_inst|pix_data_req~4, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~4 , vga_pic_inst|pix_data~4, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~9 , vga_pic_inst|pix_data~9, vga_colorbar, 1 +instance = comp, \vga_pic_inst|LessThan17~0 , vga_pic_inst|LessThan17~0, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~6 , vga_pic_inst|pix_data~6, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[4]~10 , vga_pic_inst|pix_data[4]~10, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~11 , vga_pic_inst|pix_data~11, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~12 , vga_pic_inst|pix_data~12, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~13 , vga_pic_inst|pix_data~13, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[0] , vga_pic_inst|pix_data[0], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[0]~0 , vga_ctrl_inst|rgb[0]~0, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[4]~7 , vga_pic_inst|pix_data[4]~7, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~16 , vga_pic_inst|pix_data~16, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[4] , vga_pic_inst|pix_data[4], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[1]~1 , vga_ctrl_inst|rgb[1]~1, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~25 , vga_pic_inst|pix_data~25, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[8] , vga_pic_inst|pix_data[8], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[5]~2 , vga_ctrl_inst|rgb[5]~2, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~18 , vga_pic_inst|pix_data~18, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~14 , vga_pic_inst|pix_data~14, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~26 , vga_pic_inst|pix_data~26, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~19 , vga_pic_inst|pix_data~19, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[9] , vga_pic_inst|pix_data[9], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[7]~3 , vga_ctrl_inst|rgb[7]~3, vga_colorbar, 1 +instance = comp, \vga_pic_inst|LessThan2~2 , vga_pic_inst|LessThan2~2, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~20 , vga_pic_inst|pix_data~20, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~21 , vga_pic_inst|pix_data~21, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[10] , vga_pic_inst|pix_data[10], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[10]~4 , vga_ctrl_inst|rgb[10]~4, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~22 , vga_pic_inst|pix_data~22, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~23 , vga_pic_inst|pix_data~23, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[13] , vga_pic_inst|pix_data[13], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[11]~5 , vga_ctrl_inst|rgb[11]~5, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data~24 , vga_pic_inst|pix_data~24, vga_colorbar, 1 +instance = comp, \vga_pic_inst|pix_data[15] , vga_pic_inst|pix_data[15], vga_colorbar, 1 +instance = comp, \vga_ctrl_inst|rgb[12]~6 , vga_ctrl_inst|rgb[12]~6, vga_colorbar, 1 diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_v.sdo b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_v.sdo new file mode 100644 index 0000000..3c460d1 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/simulation/modelsim/vga_colorbar_v.sdo @@ -0,0 +1,2108 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP4CE15F23C8 Package FBGA484 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE15F23C8, +// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim (Verilog) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "vga_colorbar") + (DATE "06/02/2023 04:42:20") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~4) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (460:460:460)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_pll") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll1) + (DELAY + (ABSOLUTE + (PORT areset (4503:4503:4503) (4503:4503:4503)) + (PORT inclk[0] (2340:2340:2340) (2340:2340:2340)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (960:960:960) (961:961:961)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~2) + (DELAY + (ABSOLUTE + (PORT datab (971:971:971) (950:950:950)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~4) + (DELAY + (ABSOLUTE + (PORT dataa (973:973:973) (953:953:953)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~6) + (DELAY + (ABSOLUTE + (PORT datab (1006:1006:1006) (978:978:978)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~8) + (DELAY + (ABSOLUTE + (PORT datab (569:569:569) (599:599:599)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~10) + (DELAY + (ABSOLUTE + (PORT datab (960:960:960) (939:939:939)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~12) + (DELAY + (ABSOLUTE + (PORT dataa (558:558:558) (603:603:603)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~16) + (DELAY + (ABSOLUTE + (PORT dataa (958:958:958) (962:962:962)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~0) + (DELAY + (ABSOLUTE + (PORT datab (397:397:397) (486:486:486)) + (PORT datad (343:343:343) (426:426:426)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[8\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (840:840:840) (788:788:788)) + (PORT datab (858:858:858) (836:836:836)) + (PORT datad (316:316:316) (356:356:356)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~5) + (DELAY + (ABSOLUTE + (PORT datab (1230:1230:1230) (1146:1146:1146)) + (PORT datad (924:924:924) (874:874:874)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~8) + (DELAY + (ABSOLUTE + (PORT dataa (1160:1160:1160) (1082:1082:1082)) + (PORT datab (967:967:967) (899:899:899)) + (PORT datac (937:937:937) (910:910:910)) + (PORT datad (1184:1184:1184) (1098:1098:1098)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~15) + (DELAY + (ABSOLUTE + (PORT dataa (841:841:841) (803:803:803)) + (PORT datab (509:509:509) (494:494:494)) + (PORT datac (245:245:245) (275:275:275)) + (PORT datad (262:262:262) (300:300:300)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~17) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (383:383:383)) + (PORT datac (842:842:842) (776:776:776)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_clk\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (806:806:806) (852:852:852)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|wire_pll1_clk\[0\]\~clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2339:2339:2339) (2308:2308:2308)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE hsync\~output) + (DELAY + (ABSOLUTE + (PORT i (2108:2108:2108) (2266:2266:2266)) + (IOPATH i o (3174:3174:3174) (3271:3271:3271)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE vsync\~output) + (DELAY + (ABSOLUTE + (PORT i (1864:1864:1864) (2034:2034:2034)) + (IOPATH i o (3184:3184:3184) (3281:3281:3281)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[0\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2928:2928:2928) (2696:2696:2696)) + (IOPATH i o (3271:3271:3271) (3174:3174:3174)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[1\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2872:2872:2872) (2631:2631:2631)) + (IOPATH i o (3281:3281:3281) (3184:3184:3184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[2\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3183:3183:3183) (2900:2900:2900)) + (IOPATH i o (3281:3281:3281) (3184:3184:3184)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[3\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3530:3530:3530) (3206:3206:3206)) + (IOPATH i o (3429:3429:3429) (3366:3366:3366)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[4\]\~output) + (DELAY + (ABSOLUTE + (PORT i (3524:3524:3524) (3201:3201:3201)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[5\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1540:1540:1540) (1460:1460:1460)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[6\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1581:1581:1581) (1475:1475:1475)) + (IOPATH i o (3409:3409:3409) (3346:3346:3346)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[7\]\~output) + (DELAY + (ABSOLUTE + (PORT i (2139:2139:2139) (1969:1969:1969)) + (IOPATH i o (3419:3419:3419) (3356:3356:3356)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[8\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1953:1953:1953) (1815:1815:1815)) + (IOPATH i o (3379:3379:3379) (3316:3316:3316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[9\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1947:1947:1947) (1781:1781:1781)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[10\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1885:1885:1885) (1698:1698:1698)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[11\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1851:1851:1851) (1680:1680:1680)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[12\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1486:1486:1486) (1329:1329:1329)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[13\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1506:1506:1506) (1334:1334:1334)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[14\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1091:1091:1091) (970:970:970)) + (IOPATH i o (3399:3399:3399) (3336:3336:3336)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE rgb\[15\]\~output) + (DELAY + (ABSOLUTE + (PORT i (1123:1123:1123) (999:999:999)) + (IOPATH i o (3389:3389:3389) (3326:3326:3326)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~0) + (DELAY + (ABSOLUTE + (PORT datab (366:366:366) (447:447:447)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE sys_rst_n\~input) + (DELAY + (ABSOLUTE + (IOPATH i o (766:766:766) (812:812:812)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE clk_gen_inst\|altpll_component\|auto_generated\|pll_lock_sync) + (DELAY + (ABSOLUTE + (PORT clk (2921:2921:2921) (2960:2960:2960)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (4667:4667:4667) (4459:4459:4459)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE rst_n\~0) + (DELAY + (ABSOLUTE + (PORT dataa (2254:2254:2254) (2277:2277:2277)) + (PORT datab (332:332:332) (408:408:408)) + (PORT datac (3743:3743:3743) (3918:3918:3918)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_clkctrl") + (INSTANCE rst_n\~0clkctrl) + (DELAY + (ABSOLUTE + (PORT inclk[0] (2220:2220:2220) (2115:2115:2115)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (370:370:370) (456:456:456)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~6) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (450:450:450)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~8) + (DELAY + (ABSOLUTE + (PORT datab (359:359:359) (436:436:436)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~10) + (DELAY + (ABSOLUTE + (PORT dataa (917:917:917) (889:889:889)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~12) + (DELAY + (ABSOLUTE + (PORT datab (369:369:369) (448:448:448)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~14) + (DELAY + (ABSOLUTE + (PORT dataa (362:362:362) (446:446:446)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~16) + (DELAY + (ABSOLUTE + (PORT datab (402:402:402) (492:492:492)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add0\~18) + (DELAY + (ABSOLUTE + (PORT datad (350:350:350) (435:435:435)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~1) + (DELAY + (ABSOLUTE + (PORT datab (848:848:848) (777:777:777)) + (PORT datac (240:240:240) (266:266:266)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~0) + (DELAY + (ABSOLUTE + (PORT datab (789:789:789) (706:706:706)) + (PORT datac (265:265:265) (291:291:291)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~2) + (DELAY + (ABSOLUTE + (PORT dataa (660:660:660) (668:668:668)) + (PORT datab (390:390:390) (477:477:477)) + (PORT datac (853:853:853) (839:839:839)) + (PORT datad (328:328:328) (405:405:405)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~1) + (DELAY + (ABSOLUTE + (PORT dataa (371:371:371) (461:461:461)) + (PORT datab (368:368:368) (451:451:451)) + (PORT datac (327:327:327) (412:412:412)) + (PORT datad (329:329:329) (405:405:405)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Equal0\~3) + (DELAY + (ABSOLUTE + (PORT dataa (895:895:895) (876:876:876)) + (PORT datab (741:741:741) (680:680:680)) + (PORT datac (724:724:724) (663:663:663)) + (PORT datad (917:917:917) (899:899:899)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_h\~2) + (DELAY + (ABSOLUTE + (PORT datab (279:279:279) (305:305:305)) + (PORT datac (806:806:806) (740:740:740)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_h\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1845:1845:1845) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1877:1877:1877) (1847:1847:1847)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~0) + (DELAY + (ABSOLUTE + (PORT datab (396:396:396) (485:485:485)) + (PORT datad (342:342:342) (425:425:425)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan0\~0) + (DELAY + (ABSOLUTE + (PORT dataa (858:858:858) (841:841:841)) + (PORT datab (933:933:933) (885:885:885)) + (PORT datac (767:767:767) (704:704:704)) + (PORT datad (328:328:328) (401:401:401)) + (IOPATH dataa combout (453:453:453) (446:446:446)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]\~9) + (DELAY + (ABSOLUTE + (PORT dataa (849:849:849) (802:802:802)) + (PORT datab (862:862:862) (841:841:841)) + (PORT datad (313:313:313) (352:352:352)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]\~8) + (DELAY + (ABSOLUTE + (PORT dataa (875:875:875) (832:832:832)) + (PORT datab (857:857:857) (834:834:834)) + (PORT datad (317:317:317) (358:358:358)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[2\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (1110:1110:1110) (1019:1019:1019)) + (PORT datab (856:856:856) (834:834:834)) + (PORT datad (318:318:318) (359:359:359)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~1) + (DELAY + (ABSOLUTE + (PORT dataa (1021:1021:1021) (997:997:997)) + (PORT datab (366:366:366) (449:449:449)) + (PORT datac (326:326:326) (408:408:408)) + (PORT datad (327:327:327) (401:401:401)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (1194:1194:1194) (1079:1079:1079)) + (PORT datab (860:860:860) (838:838:838)) + (PORT datad (315:315:315) (355:355:355)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[1\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~2) + (DELAY + (ABSOLUTE + (PORT dataa (307:307:307) (351:351:351)) + (PORT datab (367:367:367) (450:450:450)) + (PORT datac (450:450:450) (427:427:427)) + (PORT datad (337:337:337) (417:417:417)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (943:943:943) (877:877:877)) + (PORT datab (856:856:856) (834:834:834)) + (PORT datad (318:318:318) (358:358:358)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[3\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (450:450:450)) + (PORT datac (327:327:327) (409:409:409)) + (PORT datad (329:329:329) (402:402:402)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (893:893:893) (829:829:829)) + (PORT datab (860:860:860) (839:839:839)) + (PORT datad (315:315:315) (354:354:354)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[5\]) + (DELAY + (ABSOLUTE + (PORT clk (1844:1844:1844) (1855:1855:1855)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1876:1876:1876) (1846:1846:1846)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~14) + (DELAY + (ABSOLUTE + (PORT datab (569:569:569) (597:597:597)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (846:846:846)) + (PORT datab (279:279:279) (305:305:305)) + (PORT datad (1206:1206:1206) (1115:1115:1115)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[7\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add1\~18) + (DELAY + (ABSOLUTE + (PORT datad (333:333:333) (411:411:411)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (880:880:880) (846:846:846)) + (PORT datab (280:280:280) (306:306:306)) + (PORT datad (1207:1207:1207) (1116:1116:1116)) + (IOPATH dataa combout (421:421:421) (428:428:428)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (314:314:314)) + (PORT datab (1265:1265:1265) (1163:1163:1163)) + (PORT datad (838:838:838) (794:794:794)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (462:462:462) (482:482:482)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_ctrl_inst\|cnt_v\[6\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1856:1856:1856)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|always1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (360:360:360) (443:443:443)) + (PORT datab (359:359:359) (435:435:435)) + (PORT datac (872:872:872) (866:866:866)) + (PORT datad (893:893:893) (890:890:890)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan1\~0) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (326:326:326)) + (PORT datab (377:377:377) (459:459:459)) + (PORT datac (959:959:959) (948:948:948)) + (PORT datad (261:261:261) (296:296:296)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan6\~1) + (DELAY + (ABSOLUTE + (PORT datab (367:367:367) (449:449:449)) + (PORT datad (336:336:336) (416:416:416)) + (IOPATH datab combout (435:435:435) (433:433:433)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~1) + (DELAY + (ABSOLUTE + (PORT dataa (957:957:957) (961:961:961)) + (PORT datab (371:371:371) (451:451:451)) + (PORT datac (528:528:528) (560:560:560)) + (PORT datad (517:517:517) (552:552:552)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (457:457:457) (489:489:489)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~2) + (DELAY + (ABSOLUTE + (PORT dataa (285:285:285) (323:323:323)) + (PORT datab (277:277:277) (302:302:302)) + (PORT datac (698:698:698) (629:629:629)) + (PORT datad (265:265:265) (300:300:300)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan2\~1) + (DELAY + (ABSOLUTE + (PORT datab (930:930:930) (883:883:883)) + (PORT datac (848:848:848) (826:826:826)) + (PORT datad (326:326:326) (400:400:400)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb_valid\~0) + (DELAY + (ABSOLUTE + (PORT dataa (735:735:735) (684:684:684)) + (PORT datab (974:974:974) (944:944:944)) + (PORT datac (765:765:765) (703:703:703)) + (PORT datad (254:254:254) (280:280:280)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (455:455:455) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~1) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (628:628:628)) + (PORT datab (837:837:837) (806:806:806)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datab cout (565:565:565) (421:421:421)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~3) + (DELAY + (ABSOLUTE + (PORT dataa (618:618:618) (628:628:628)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~5) + (DELAY + (ABSOLUTE + (PORT dataa (570:570:570) (597:597:597)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~7) + (DELAY + (ABSOLUTE + (PORT dataa (582:582:582) (607:607:607)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~9) + (DELAY + (ABSOLUTE + (PORT dataa (853:853:853) (839:839:839)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~10) + (DELAY + (ABSOLUTE + (PORT datab (620:620:620) (627:627:627)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datab cout (565:565:565) (421:421:421)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~12) + (DELAY + (ABSOLUTE + (PORT dataa (855:855:855) (837:837:837)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan14\~0) + (DELAY + (ABSOLUTE + (PORT datab (337:337:337) (383:383:383)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~14) + (DELAY + (ABSOLUTE + (PORT dataa (644:644:644) (650:650:650)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH dataa cout (552:552:552) (416:416:416)) + (IOPATH datad combout (177:177:177) (155:155:155)) + (IOPATH cin combout (607:607:607) (577:577:577)) + (IOPATH cin cout (73:73:73) (73:73:73)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|Add2\~16) + (DELAY + (ABSOLUTE + (PORT dataa (619:619:619) (628:628:628)) + (IOPATH dataa combout (471:471:471) (481:481:481)) + (IOPATH cin combout (607:607:607) (577:577:577)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan6\~0) + (DELAY + (ABSOLUTE + (PORT dataa (839:839:839) (801:801:801)) + (PORT datab (278:278:278) (303:303:303)) + (PORT datac (273:273:273) (303:303:303)) + (PORT datad (274:274:274) (299:299:299)) + (IOPATH dataa combout (456:456:456) (486:486:486)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~0) + (DELAY + (ABSOLUTE + (PORT dataa (306:306:306) (351:351:351)) + (PORT datac (955:955:955) (943:943:943)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datac combout (327:327:327) (316:316:316)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|LessThan4\~0) + (DELAY + (ABSOLUTE + (PORT dataa (767:767:767) (710:710:710)) + (PORT datab (976:976:976) (946:946:946)) + (PORT datac (764:764:764) (701:701:701)) + (PORT datad (257:257:257) (283:283:283)) + (IOPATH dataa combout (420:420:420) (428:428:428)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~3) + (DELAY + (ABSOLUTE + (PORT dataa (736:736:736) (684:684:684)) + (PORT datab (976:976:976) (946:946:946)) + (PORT datac (723:723:723) (662:662:662)) + (PORT datad (256:256:256) (281:281:281)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|pix_data_req\~4) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (812:812:812)) + (PORT datab (918:918:918) (854:854:854)) + (PORT datac (237:237:237) (264:264:264)) + (PORT datad (238:238:238) (257:257:257)) + (IOPATH dataa combout (392:392:392) (407:407:407)) + (IOPATH datab combout (393:393:393) (412:412:412)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~4) + (DELAY + (ABSOLUTE + (PORT datab (1232:1232:1232) (1148:1148:1148)) + (PORT datad (847:847:847) (804:804:804)) + (IOPATH datab combout (472:472:472) (473:473:473)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~9) + (DELAY + (ABSOLUTE + (PORT dataa (281:281:281) (313:313:313)) + (PORT datab (888:888:888) (823:823:823)) + (PORT datac (934:934:934) (907:907:907)) + (PORT datad (279:279:279) (305:305:305)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan17\~0) + (DELAY + (ABSOLUTE + (PORT dataa (888:888:888) (855:855:855)) + (PORT datab (966:966:966) (898:898:898)) + (PORT datac (934:934:934) (907:907:907)) + (PORT datad (1188:1188:1188) (1104:1104:1104)) + (IOPATH dataa combout (404:404:404) (398:398:398)) + (IOPATH datab combout (407:407:407) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~6) + (DELAY + (ABSOLUTE + (PORT dataa (304:304:304) (351:351:351)) + (PORT datab (320:320:320) (350:350:350)) + (PORT datac (935:935:935) (908:908:908)) + (PORT datad (487:487:487) (468:468:468)) + (IOPATH dataa combout (481:481:481) (491:491:491)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~10) + (DELAY + (ABSOLUTE + (PORT datac (936:936:936) (910:910:910)) + (PORT datad (846:846:846) (803:803:803)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~11) + (DELAY + (ABSOLUTE + (PORT dataa (903:903:903) (824:824:824)) + (PORT datab (338:338:338) (384:384:384)) + (PORT datac (795:795:795) (753:753:753)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH dataa combout (432:432:432) (446:446:446)) + (IOPATH datab combout (437:437:437) (436:436:436)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~12) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (353:353:353)) + (PORT datab (304:304:304) (329:329:329)) + (PORT datac (243:243:243) (274:274:274)) + (PORT datad (802:802:802) (754:754:754)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~13) + (DELAY + (ABSOLUTE + (PORT dataa (573:573:573) (537:537:537)) + (PORT datab (285:285:285) (315:315:315)) + (PORT datac (288:288:288) (315:315:315)) + (PORT datad (245:245:245) (270:270:270)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[0\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[0\]\~0) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (815:815:815)) + (PORT datab (327:327:327) (381:381:381)) + (PORT datac (852:852:852) (839:839:839)) + (PORT datad (863:863:863) (814:814:814)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\[4\]\~7) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (856:856:856)) + (PORT datab (988:988:988) (944:944:944)) + (PORT datac (1120:1120:1120) (1040:1040:1040)) + (PORT datad (1190:1190:1190) (1106:1106:1106)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (435:435:435) (424:424:424)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~16) + (DELAY + (ABSOLUTE + (PORT dataa (288:288:288) (326:326:326)) + (PORT datab (322:322:322) (356:356:356)) + (PORT datac (245:245:245) (278:278:278)) + (PORT datad (501:501:501) (465:465:465)) + (IOPATH dataa combout (471:471:471) (472:472:472)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[4\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[1\]\~1) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (810:810:810)) + (PORT datab (917:917:917) (852:852:852)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (912:912:912) (892:892:892)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~25) + (DELAY + (ABSOLUTE + (PORT dataa (544:544:544) (510:510:510)) + (PORT datab (511:511:511) (499:499:499)) + (PORT datac (263:263:263) (289:289:289)) + (PORT datad (817:817:817) (766:766:766)) + (IOPATH dataa combout (453:453:453) (413:413:413)) + (IOPATH datab combout (455:455:455) (433:433:433)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[8\]) + (DELAY + (ABSOLUTE + (PORT clk (1846:1846:1846) (1857:1857:1857)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1878:1878:1878) (1848:1848:1848)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[5\]\~2) + (DELAY + (ABSOLUTE + (PORT dataa (834:834:834) (810:810:810)) + (PORT datab (916:916:916) (852:852:852)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (295:295:295) (365:365:365)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~18) + (DELAY + (ABSOLUTE + (PORT dataa (902:902:902) (824:824:824)) + (PORT datab (336:336:336) (382:382:382)) + (PORT datac (790:790:790) (746:746:746)) + (PORT datad (291:291:291) (318:318:318)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~14) + (DELAY + (ABSOLUTE + (PORT datab (314:314:314) (342:342:342)) + (PORT datac (796:796:796) (754:754:754)) + (PORT datad (299:299:299) (343:343:343)) + (IOPATH datab combout (473:473:473) (487:487:487)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~26) + (DELAY + (ABSOLUTE + (PORT dataa (833:833:833) (794:794:794)) + (PORT datab (275:275:275) (299:299:299)) + (PORT datac (270:270:270) (300:300:300)) + (PORT datad (267:267:267) (285:285:285)) + (IOPATH dataa combout (448:448:448) (472:472:472)) + (IOPATH datab combout (454:454:454) (473:473:473)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~19) + (DELAY + (ABSOLUTE + (PORT datab (930:930:930) (864:864:864)) + (PORT datad (500:500:500) (460:460:460)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[9\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[7\]\~3) + (DELAY + (ABSOLUTE + (PORT dataa (836:836:836) (812:812:812)) + (PORT datab (919:919:919) (856:856:856)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (829:829:829) (827:827:827)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|LessThan2\~2) + (DELAY + (ABSOLUTE + (PORT dataa (527:527:527) (519:519:519)) + (PORT datab (984:984:984) (924:924:924)) + (PORT datad (1189:1189:1189) (1104:1104:1104)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (410:410:410) (408:408:408)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~20) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (843:843:843)) + (PORT datac (849:849:849) (795:795:795)) + (PORT datad (908:908:908) (849:849:849)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~21) + (DELAY + (ABSOLUTE + (PORT dataa (564:564:564) (524:524:524)) + (PORT datab (928:928:928) (861:861:861)) + (PORT datac (475:475:475) (447:447:447)) + (PORT datad (239:239:239) (257:257:257)) + (IOPATH dataa combout (405:405:405) (398:398:398)) + (IOPATH datab combout (455:455:455) (436:436:436)) + (IOPATH datac combout (327:327:327) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[10\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[10\]\~4) + (DELAY + (ABSOLUTE + (PORT dataa (838:838:838) (815:815:815)) + (PORT datab (924:924:924) (861:861:861)) + (PORT datac (283:283:283) (342:342:342)) + (PORT datad (931:931:931) (915:915:915)) + (IOPATH dataa combout (393:393:393) (398:398:398)) + (IOPATH datab combout (393:393:393) (408:408:408)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~22) + (DELAY + (ABSOLUTE + (PORT dataa (305:305:305) (353:353:353)) + (PORT datab (886:886:886) (822:822:822)) + (PORT datac (936:936:936) (910:910:910)) + (PORT datad (282:282:282) (309:309:309)) + (IOPATH dataa combout (392:392:392) (398:398:398)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~23) + (DELAY + (ABSOLUTE + (PORT dataa (317:317:317) (352:352:352)) + (PORT datab (283:283:283) (311:311:311)) + (PORT datac (455:455:455) (430:430:430)) + (PORT datad (285:285:285) (317:317:317)) + (IOPATH dataa combout (421:421:421) (418:418:418)) + (IOPATH datab combout (494:494:494) (496:496:496)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[13\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[11\]\~5) + (DELAY + (ABSOLUTE + (PORT dataa (835:835:835) (811:811:811)) + (PORT datab (918:918:918) (911:911:911)) + (PORT datac (284:284:284) (343:343:343)) + (PORT datad (857:857:857) (807:807:807)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_pic_inst\|pix_data\~24) + (DELAY + (ABSOLUTE + (PORT dataa (289:289:289) (328:328:328)) + (PORT datab (325:325:325) (360:360:360)) + (PORT datac (455:455:455) (430:430:430)) + (PORT datad (276:276:276) (301:301:301)) + (IOPATH dataa combout (471:471:471) (453:453:453)) + (IOPATH datab combout (472:472:472) (452:452:452)) + (IOPATH datac combout (324:324:324) (316:316:316)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) + (CELL + (CELLTYPE "dffeas") + (INSTANCE vga_pic_inst\|pix_data\[15\]) + (DELAY + (ABSOLUTE + (PORT clk (1848:1848:1848) (1858:1858:1858)) + (PORT d (99:99:99) (115:115:115)) + (PORT clrn (1880:1880:1880) (1849:1849:1849)) + (IOPATH (posedge clk) q (261:261:261) (261:261:261)) + (IOPATH (negedge clrn) q (247:247:247) (247:247:247)) + ) + ) + (TIMINGCHECK + (HOLD d (posedge clk) (212:212:212)) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE vga_ctrl_inst\|rgb\[12\]\~6) + (DELAY + (ABSOLUTE + (PORT dataa (837:837:837) (814:814:814)) + (PORT datab (844:844:844) (810:810:810)) + (PORT datac (283:283:283) (342:342:342)) + (PORT datad (862:862:862) (812:812:812)) + (IOPATH dataa combout (461:461:461) (481:481:481)) + (IOPATH datab combout (455:455:455) (412:412:412)) + (IOPATH datac combout (327:327:327) (315:315:315)) + (IOPATH datad combout (177:177:177) (155:155:155)) + ) + ) + ) +) diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qpf b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qpf new file mode 100644 index 0000000..3e567ad --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 13:49:09 February 27, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "13:49:09 February 27, 2020" + +# Revisions + +PROJECT_REVISION = "vga_colorbar" diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qsf b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qsf new file mode 100644 index 0000000..d74cf77 --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qsf @@ -0,0 +1,99 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version +# Date created = 13:49:09 February 27, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# vga_colorbar_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE15F23C8 +set_global_assignment -name TOP_LEVEL_ENTITY vga_colorbar +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:49:09 FEBRUARY 27, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb_vga_ctrl -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME tb_vga_colorbar -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_vga_colorbar +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_vga_colorbar +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_vga_colorbar -section_id tb_vga_colorbar +set_global_assignment -name EDA_TEST_BENCH_NAME tb_vga_ctrl -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_vga_ctrl +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 us" -section_id tb_vga_ctrl +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_vga_ctrl -section_id tb_vga_ctrl +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +set_location_assignment PIN_T22 -to sys_clk +set_location_assignment PIN_U20 -to sys_rst_n +set_location_assignment PIN_AB17 -to vsync +set_location_assignment PIN_AA18 -to hsync +set_location_assignment PIN_J21 -to rgb[15] +set_location_assignment PIN_K21 -to rgb[14] +set_location_assignment PIN_L22 -to rgb[13] +set_location_assignment PIN_L21 -to rgb[12] +set_location_assignment PIN_M22 -to rgb[11] +set_location_assignment PIN_M21 -to rgb[10] +set_location_assignment PIN_N21 -to rgb[9] +set_location_assignment PIN_N20 -to rgb[8] +set_location_assignment PIN_U22 -to rgb[7] +set_location_assignment PIN_U21 -to rgb[6] +set_location_assignment PIN_W20 -to rgb[5] +set_location_assignment PIN_W19 -to rgb[4] +set_location_assignment PIN_Y21 -to rgb[3] +set_location_assignment PIN_AB19 -to rgb[2] +set_location_assignment PIN_AA19 -to rgb[1] +set_location_assignment PIN_AB18 -to rgb[0] + + +set_global_assignment -name VERILOG_FILE ../sim/tb_vga_ctrl.v +set_global_assignment -name VERILOG_FILE ../sim/tb_vga_colorbar.v +set_global_assignment -name VERILOG_FILE ../rtl/vga_pic.v +set_global_assignment -name VERILOG_FILE ../rtl/vga_ctrl.v +set_global_assignment -name VERILOG_FILE ../rtl/vga_colorbar.v +set_global_assignment -name QIP_FILE ip_core/clk_gen/clk_gen.qip +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_vga_colorbar.v -section_id tb_vga_colorbar +set_global_assignment -name EDA_TEST_BENCH_FILE ../sim/tb_vga_ctrl.v -section_id tb_vga_ctrl +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qws b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qws new file mode 100644 index 0000000..27fd4ea Binary files /dev/null and b/smh-ac415-fpga/examples/09_vga/vga/quartus_prj/vga_colorbar.qws differ diff --git a/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_colorbar.v b/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_colorbar.v new file mode 100644 index 0000000..6b5f4dc --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_colorbar.v @@ -0,0 +1,84 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/03/12 +// Module Name : vga_colorbar +// Project Name : vga_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : vga_colorbar顶层模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module vga_colorbar +( + input wire sys_clk , //输入工作时钟,频率50MHz + input wire sys_rst_n , //输入复位信号,低电平有效 + + output wire hsync , //输出行同步信号 + output wire vsync , //输出场同步信号 + output wire [15:0] rgb //输出像素信息 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//wire define +wire vga_clk ; //VGA工作时钟,频率25MHz +wire locked ; //PLL locked信号 +wire rst_n ; //VGA模块复位信号 +wire [9:0] pix_x ; //VGA有效显示区域X轴坐标 +wire [9:0] pix_y ; //VGA有效显示区域Y轴坐标 +wire [15:0] pix_data; //VGA像素点色彩信息 + +//rst_n:VGA模块复位信号 +assign rst_n = (sys_rst_n & locked); + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- clk_gen_inst ------------- +clk_gen clk_gen_inst +( + .areset (~sys_rst_n ), //输入复位信号,高电平有效,1bit + .inclk0 (sys_clk ), //输入50MHz晶振时钟,1bit + + .c0 (vga_clk ), //输出VGA工作时钟,频率25Mhz,1bit + .locked (locked ) //输出pll locked信号,1bit +); + +//------------- vga_ctrl_inst ------------- +vga_ctrl vga_ctrl_inst +( + .vga_clk (vga_clk ), //输入工作时钟,频率25MHz,1bit + .sys_rst_n (rst_n ), //输入复位信号,低电平有效,1bit + .pix_data (pix_data ), //输入像素点色彩信息,16bit + + .pix_x (pix_x ), //输出VGA有效显示区域像素点X轴坐标,10bit + .pix_y (pix_y ), //输出VGA有效显示区域像素点Y轴坐标,10bit + .hsync (hsync ), //输出行同步信号,1bit + .vsync (vsync ), //输出场同步信号,1bit + .rgb (rgb ) //输出像素点色彩信息,16bit +); + +//------------- vga_pic_inst ------------- +vga_pic vga_pic_inst +( + .vga_clk (vga_clk ), //输入工作时钟,频率25MHz,1bit + .sys_rst_n (rst_n ), //输入复位信号,低电平有效,1bit + .pix_x (pix_x ), //输入VGA有效显示区域像素点X轴坐标,10bit + .pix_y (pix_y ), //输入VGA有效显示区域像素点Y轴坐标,10bit + + .pix_data (pix_data ) //输出像素点色彩信息,16bit + +); + +endmodule diff --git a/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_ctrl.v b/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_ctrl.v new file mode 100644 index 0000000..c00ab5c --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_ctrl.v @@ -0,0 +1,113 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/03/12 +// Module Name : vga_ctrl +// Project Name : vga_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : VGA控制模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module vga_ctrl +( + input wire vga_clk , //输入工作时钟,频率25MHz + input wire sys_rst_n , //输入复位信号,低电平有效 + input wire [15:0] pix_data , //输入像素点色彩信息 + + output wire [9:0] pix_x , //输出VGA有效显示区域像素点X轴坐标 + output wire [9:0] pix_y , //输出VGA有效显示区域像素点Y轴坐标 + output wire hsync , //输出行同步信号 + output wire vsync , //输出场同步信号 + output wire [15:0] rgb //输出像素点色彩信息 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter H_SYNC = 10'd96 , //行同步 + H_BACK = 10'd40 , //行时序后沿 + H_LEFT = 10'd8 , //行时序左边框 + H_VALID = 10'd640 , //行有效数据 + H_RIGHT = 10'd8 , //行时序右边框 + H_FRONT = 10'd8 , //行时序前沿 + H_TOTAL = 10'd800 ; //行扫描周期 +parameter V_SYNC = 10'd2 , //场同步 + V_BACK = 10'd25 , //场时序后沿 + V_TOP = 10'd8 , //场时序上边框 + V_VALID = 10'd480 , //场有效数据 + V_BOTTOM = 10'd8 , //场时序下边框 + V_FRONT = 10'd2 , //场时序前沿 + V_TOTAL = 10'd525 ; //场扫描周期 + +//wire define +wire rgb_valid ; //VGA有效显示区域 +wire pix_data_req ; //像素点色彩信息请求信号 + +//reg define +reg [9:0] cnt_h ; //行同步信号计数器 +reg [9:0] cnt_v ; //场同步信号计数器 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +//cnt_h:行同步信号计数器 +always@(posedge vga_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_h <= 10'd0 ; + else if(cnt_h == H_TOTAL - 1'd1) + cnt_h <= 10'd0 ; + else + cnt_h <= cnt_h + 1'd1 ; + +//hsync:行同步信号 +assign hsync = (cnt_h <= H_SYNC - 1'd1) ? 1'b1 : 1'b0 ; + +//cnt_v:场同步信号计数器 +always@(posedge vga_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + cnt_v <= 10'd0 ; + else if((cnt_v == V_TOTAL - 1'd1) && (cnt_h == H_TOTAL-1'd1)) + cnt_v <= 10'd0 ; + else if(cnt_h == H_TOTAL - 1'd1) + cnt_v <= cnt_v + 1'd1 ; + else + cnt_v <= cnt_v ; + +//vsync:场同步信号 +assign vsync = (cnt_v <= V_SYNC - 1'd1) ? 1'b1 : 1'b0 ; + +//rgb_valid:VGA有效显示区域 +assign rgb_valid = (((cnt_h >= H_SYNC + H_BACK + H_LEFT) + && (cnt_h < H_SYNC + H_BACK + H_LEFT + H_VALID)) + &&((cnt_v >= V_SYNC + V_BACK + V_TOP) + && (cnt_v < V_SYNC + V_BACK + V_TOP + V_VALID))) + ? 1'b1 : 1'b0; + +//pix_data_req:像素点色彩信息请求信号,超前rgb_valid信号一个时钟周期 +assign pix_data_req = (((cnt_h >= H_SYNC + H_BACK + H_LEFT - 1'b1) + && (cnt_h < H_SYNC + H_BACK + H_LEFT + H_VALID - 1'b1)) + &&((cnt_v >= V_SYNC + V_BACK + V_TOP) + && (cnt_v < V_SYNC + V_BACK + V_TOP + V_VALID))) + ? 1'b1 : 1'b0; + +//pix_x,pix_y:VGA有效显示区域像素点坐标 +assign pix_x = (pix_data_req == 1'b1) + ? (cnt_h - (H_SYNC + H_BACK + H_LEFT - 1'b1)) : 10'h3ff; +assign pix_y = (pix_data_req == 1'b1) + ? (cnt_v - (V_SYNC + V_BACK + V_TOP)) : 10'h3ff; + +//rgb:输出像素点色彩信息 +assign rgb = (rgb_valid == 1'b1) ? pix_data : 16'b0 ; + +endmodule diff --git a/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_pic.v b/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_pic.v new file mode 100644 index 0000000..b0c178c --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/rtl/vga_pic.v @@ -0,0 +1,79 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/03/12 +// Module Name : vga_pic +// Project Name : vga_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : 图像数据生成模块 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module vga_pic +( + input wire vga_clk , //输入工作时钟,频率25MHz + input wire sys_rst_n , //输入复位信号,低电平有效 + input wire [9:0] pix_x , //输入VGA有效显示区域像素点X轴坐标 + input wire [9:0] pix_y , //输入VGA有效显示区域像素点Y轴坐标 + + output reg [15:0] pix_data //输出像素点色彩信息 +); + +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//parameter define +parameter H_VALID = 10'd640 , //行有效数据 + V_VALID = 10'd480 ; //场有效数据 + +parameter RED = 16'hF800, //红色 + ORANGE = 16'hFC00, //橙色 + YELLOW = 16'hFFE0, //黄色 + GREEN = 16'h07E0, //绿色 + CYAN = 16'h07FF, //青色 + BLUE = 16'h001F, //蓝色 + PURPPLE = 16'hF81F, //紫色 + BLACK = 16'h0000, //黑色 + WHITE = 16'hFFFF, //白色 + GRAY = 16'hD69A; //灰色 + +//********************************************************************// +//***************************** Main Code ****************************// +//********************************************************************// + +//pix_data:输出像素点色彩信息,根据当前像素点坐标指定当前像素点颜色数据 +always@(posedge vga_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + pix_data <= 16'd0; + else if((pix_x >= 0) && (pix_x < (H_VALID/10)*1)) + pix_data <= RED; + else if((pix_x >= (H_VALID/10)*1) && (pix_x < (H_VALID/10)*2)) + pix_data <= ORANGE; + else if((pix_x >= (H_VALID/10)*2) && (pix_x < (H_VALID/10)*3)) + pix_data <= YELLOW; + else if((pix_x >= (H_VALID/10)*3) && (pix_x < (H_VALID/10)*4)) + pix_data <= GREEN; + else if((pix_x >= (H_VALID/10)*4) && (pix_x < (H_VALID/10)*5)) + pix_data <= CYAN; + else if((pix_x >= (H_VALID/10)*5) && (pix_x < (H_VALID/10)*6)) + pix_data <= BLUE; + else if((pix_x >= (H_VALID/10)*6) && (pix_x < (H_VALID/10)*7)) + pix_data <= PURPPLE; + else if((pix_x >= (H_VALID/10)*7) && (pix_x < (H_VALID/10)*8)) + pix_data <= BLACK; + else if((pix_x >= (H_VALID/10)*8) && (pix_x < (H_VALID/10)*9)) + pix_data <= WHITE; + else if((pix_x >= (H_VALID/10)*9) && (pix_x < H_VALID)) + pix_data <= GRAY; + else + pix_data <= BLACK; + +endmodule diff --git a/smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_colorbar.v b/smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_colorbar.v new file mode 100644 index 0000000..6d6bb9f --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_colorbar.v @@ -0,0 +1,65 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/03/12 +// Module Name : tb_vga_colorbar +// Project Name : vga_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : vga_colorbar仿真文件 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module tb_vga_colorbar(); +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//wire define +wire hsync ; +wire [15:0] rgb ; +wire vsync ; + +//reg define +reg sys_clk ; +reg sys_rst_n ; + +//********************************************************************// +//**************************** Clk And Rst ***************************// +//********************************************************************// + +//sys_clk,sys_rst_n初始赋值 +initial + begin + sys_clk = 1'b1; + sys_rst_n <= 1'b0; + #200 + sys_rst_n <= 1'b1; + end + +//sys_clk：产生时钟 +always #10 sys_clk = ~sys_clk ; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- vga_colorbar_inst ------------- +vga_colorbar vga_colorbar_inst +( + .sys_clk (sys_clk ), //输入晶振时钟,频率50MHz,1bit + .sys_rst_n (sys_rst_n ), //输入复位信号,低电平有效,1bit + + .hsync (hsync ), //输出行同步信号,1bit + .vsync (vsync ), //输出场同步信号,1bit + .rgb (rgb ) //输出RGB图像信息,16bit +); + +endmodule + diff --git a/smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_ctrl.v b/smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_ctrl.v new file mode 100644 index 0000000..fe027dd --- /dev/null +++ b/smh-ac415-fpga/examples/09_vga/vga/sim/tb_vga_ctrl.v @@ -0,0 +1,88 @@ +`timescale 1ns/1ns +//////////////////////////////////////////////////////////////////////// +// Author : EmbedFire +// Create Date : 2019/03/12 +// Module Name : tb_vga_ctrl +// Project Name : vga_colorbar +// Target Devices: Altera EP4CE10F17C8N +// Tool Versions : Quartus 13.0 +// Description : vga_ctrl仿真文件 +// +// Revision : V1.0 +// Additional Comments: +// +// 实验平台: 野火_征途Pro_FPGA开发板 +// 公司 : http://www.embedfire.com +// 论坛 : http://www.firebbs.cn +// 淘宝 : https://fire-stm32.taobao.com +//////////////////////////////////////////////////////////////////////// + +module tb_vga_ctrl(); +//********************************************************************// +//****************** Parameter and Internal Signal *******************// +//********************************************************************// +//wire define +//wire locked ; +//wire rst_n ; +//wire vga_clk ; + +//reg define +reg sys_clk ; +reg sys_rst_n ; +reg [15:0] pix_data ; + +//********************************************************************// +//**************************** Clk And Rst ***************************// +//********************************************************************// + +//sys_clk,sys_rst_n初始赋值 +initial + begin + sys_clk = 1'b1; + sys_rst_n <= 1'b0; + #200 + sys_rst_n <= 1'b1; + end + +//sys_clk：产生时钟 +always #20 sys_clk = ~sys_clk; + +//rst_n:VGA模块复位信号 +//assign rst_n = (sys_rst_n & locked); + +//pix_data:输入像素点色彩信息 +always@(posedge sys_clk or negedge sys_rst_n) + if(sys_rst_n == 1'b0) + pix_data <= 16'h0; + else + pix_data <= 16'hffff; + +//********************************************************************// +//*************************** Instantiation **************************// +//********************************************************************// + +//------------- clk_gen_inst ------------- +/* clk_gen clk_gen_inst +( + .areset (~sys_rst_n ), //输入复位信号,高电平有效,1bit + .inclk0 (sys_clk ), //输入50MHz晶振时钟,1bit + .c0 (vga_clk ), //输出VGA工作时钟,频率25Mhz,1bit + .locked (locked ) //输出pll locked信号,1bit +); */ + +//------------- vga_ctrl_inst ------------- +vga_ctrl vga_ctrl_inst +( + .vga_clk (sys_clk ), //输入工作时钟,频率25MHz,1bit + .sys_rst_n (sys_rst_n ), //输入复位信号,低电平有效,1bit + .pix_data (pix_data ), //输入像素点色彩信息,16bit + + .pix_x (pix_x ), //输出VGA有效显示区域像素点X轴坐标,10bit + .pix_y (pix_y ), //输出VGA有效显示区域像素点Y轴坐标,10bit + .hsync (hsync ), //输出行同步信号,1bit + .vsync (vsync ), //输出场同步信号,1bit + .rgb (rgb ) //输出像素点色彩信息,16bit +); + +endmodule + diff --git "a/smh-ac415-fpga/examples/09_vga/\345\256\236\351\252\214\347\216\260\350\261\241.txt" "b/smh-ac415-fpga/examples/09_vga/\345\256\236\351\252\214\347\216\260\350\261\241.txt" new file mode 100644 index 0000000..0d9b9c8 --- /dev/null +++ "b/smh-ac415-fpga/examples/09_vga/\345\256\236\351\252\214\347\216\260\350\261\241.txt" @@ -0,0 +1,5 @@ +现象：用vga线连接显示器，可以显示色条colorbar。此例程参考野火fpga例程修改而来。具体可参考野火教程。 + +测试：可以测试vga接口是否正常。 + + -- cgit v1.2.3